From 7c0631d494b95fa5697d297ae443d7787321b5a1 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Sat, 18 Feb 2023 08:27:24 -0800 Subject: perf test: Fix offcpu test prev_state check On Fedora 36, the 'perf record' offcpu profiling tests are failing. It was because the BPF checks the prev task's state being S or D but actually it has more bits set. Let's check the LSB 8 bits for the purpose of offcpu profiling. Reported-by: Arnaldo Carvalho de Melo Signed-off-by: Namhyung Kim Acked-by: Ian Rogers Tested-by: Arnaldo Carvalho de Melo Cc: Adrian Hunter Cc: Ingo Molnar Cc: Jiri Olsa Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230218162724.1292657-1-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/bpf_skel/off_cpu.bpf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/bpf_skel/off_cpu.bpf.c b/tools/perf/util/bpf_skel/off_cpu.bpf.c index 38e3b287dbb2..d877a0a9731f 100644 --- a/tools/perf/util/bpf_skel/off_cpu.bpf.c +++ b/tools/perf/util/bpf_skel/off_cpu.bpf.c @@ -277,7 +277,7 @@ int on_switch(u64 *ctx) else prev_state = get_task_state(prev); - return off_cpu_stat(ctx, prev, next, prev_state); + return off_cpu_stat(ctx, prev, next, prev_state & 0xff); } char LICENSE[] SEC("license") = "Dual BSD/GPL"; -- cgit v1.2.3-58-ga151 From 484b2a8442d2ad413ac983775232544e2940fdd1 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:27:58 -0800 Subject: perf tools: Ensure evsel name is initialized Use the evsel__name accessor as otherwise name may be NULL resulting in a segv. This was observed with the perf stat shell test. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/synthetic-events.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/synthetic-events.c b/tools/perf/util/synthetic-events.c index 9ab9308ee80c..6def01036eb5 100644 --- a/tools/perf/util/synthetic-events.c +++ b/tools/perf/util/synthetic-events.c @@ -2004,7 +2004,7 @@ int perf_event__synthesize_event_update_name(struct perf_tool *tool, struct evse perf_event__handler_t process) { struct perf_record_event_update *ev; - size_t len = strlen(evsel->name); + size_t len = strlen(evsel__name(evsel)); int err; ev = event_update_event__new(len + 1, PERF_EVENT_UPDATE__NAME, evsel->core.id[0]); -- cgit v1.2.3-58-ga151 From 180a501346d19f2613f41208b5d67dc037638018 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:27:59 -0800 Subject: perf metrics: Improve variable names has_constraint implies the NMI_WATCHDOG_CONSTRAINT and if the constraint is detected it causes events not to be grouped. Most of the code cares about whether events are grouped or not, so rename has_constraint to group_events. Also remove group from metricgroup___watchdog_constraint_hint as the warning is specific to a metric. Make the warning message agree with this too. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-3-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/metricgroup.c | 45 +++++++++++++++++++++---------------------- 1 file changed, 22 insertions(+), 23 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index f3559be95541..b2aa6e049804 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -136,10 +136,9 @@ struct metric { /** Optional null terminated array of referenced metrics. */ struct metric_ref *metric_refs; /** - * Is there a constraint on the group of events? In which case the - * events won't be grouped. + * Should events of the metric be grouped? */ - bool has_constraint; + bool group_events; /** * Parsed events for the metric. Optional as events may be taken from a * different metric whose group contains all the IDs necessary for this @@ -148,12 +147,12 @@ struct metric { struct evlist *evlist; }; -static void metricgroup___watchdog_constraint_hint(const char *name, bool foot) +static void metric__watchdog_constraint_hint(const char *name, bool foot) { static bool violate_nmi_constraint; if (!foot) { - pr_warning("Splitting metric group %s into standalone metrics.\n", name); + pr_warning("Not grouping metric %s's events.\n", name); violate_nmi_constraint = true; return; } @@ -167,18 +166,18 @@ static void metricgroup___watchdog_constraint_hint(const char *name, bool foot) " echo 1 > /proc/sys/kernel/nmi_watchdog\n"); } -static bool metricgroup__has_constraint(const struct pmu_metric *pm) +static bool metric__group_events(const struct pmu_metric *pm) { if (!pm->metric_constraint) - return false; + return true; if (!strcmp(pm->metric_constraint, "NO_NMI_WATCHDOG") && sysctl__nmi_watchdog_enabled()) { - metricgroup___watchdog_constraint_hint(pm->metric_name, false); - return true; + metric__watchdog_constraint_hint(pm->metric_name, /*foot=*/false); + return false; } - return false; + return true; } static void metric__free(struct metric *m) @@ -227,7 +226,7 @@ static struct metric *metric__new(const struct pmu_metric *pm, } m->pctx->sctx.runtime = runtime; m->pctx->sctx.system_wide = system_wide; - m->has_constraint = metric_no_group || metricgroup__has_constraint(pm); + m->group_events = !metric_no_group && metric__group_events(pm); m->metric_refs = NULL; m->evlist = NULL; @@ -637,7 +636,7 @@ static int decode_all_metric_ids(struct evlist *perf_evlist, const char *modifie static int metricgroup__build_event_string(struct strbuf *events, const struct expr_parse_ctx *ctx, const char *modifier, - bool has_constraint) + bool group_events) { struct hashmap_entry *cur; size_t bkt; @@ -662,7 +661,7 @@ static int metricgroup__build_event_string(struct strbuf *events, } /* Separate events with commas and open the group if necessary. */ if (no_group) { - if (!has_constraint) { + if (group_events) { ret = strbuf_addch(events, '{'); RETURN_IF_NON_ZERO(ret); } @@ -716,7 +715,7 @@ static int metricgroup__build_event_string(struct strbuf *events, RETURN_IF_NON_ZERO(ret); } } - if (!no_group && !has_constraint) { + if (!no_group && group_events) { ret = strbuf_addf(events, "}:W"); RETURN_IF_NON_ZERO(ret); } @@ -1252,7 +1251,7 @@ static int metricgroup__add_metric_list(const char *list, bool metric_no_group, * Warn about nmi_watchdog if any parsed metrics had the * NO_NMI_WATCHDOG constraint. */ - metricgroup___watchdog_constraint_hint(NULL, true); + metric__watchdog_constraint_hint(NULL, /*foot=*/true); /* No metrics. */ if (count == 0) return -EINVAL; @@ -1295,7 +1294,7 @@ static void find_tool_events(const struct list_head *metric_list, } /** - * build_combined_expr_ctx - Make an expr_parse_ctx with all has_constraint + * build_combined_expr_ctx - Make an expr_parse_ctx with all !group_events * metric IDs, as the IDs are held in a set, * duplicates will be removed. * @metric_list: List to take metrics from. @@ -1315,7 +1314,7 @@ static int build_combined_expr_ctx(const struct list_head *metric_list, return -ENOMEM; list_for_each_entry(m, metric_list, nd) { - if (m->has_constraint && !m->modifier) { + if (!m->group_events && !m->modifier) { hashmap__for_each_entry(m->pctx->ids, cur, bkt) { dup = strdup(cur->pkey); if (!dup) { @@ -1342,14 +1341,14 @@ err_out: * @fake_pmu: used when testing metrics not supported by the current CPU. * @ids: the event identifiers parsed from a metric. * @modifier: any modifiers added to the events. - * @has_constraint: false if events should be placed in a weak group. + * @group_events: should events be placed in a weak group. * @tool_events: entries set true if the tool event of index could be present in * the overall list of metrics. * @out_evlist: the created list of events. */ static int parse_ids(bool metric_no_merge, struct perf_pmu *fake_pmu, struct expr_parse_ctx *ids, const char *modifier, - bool has_constraint, const bool tool_events[PERF_TOOL_MAX], + bool group_events, const bool tool_events[PERF_TOOL_MAX], struct evlist **out_evlist) { struct parse_events_error parse_error; @@ -1393,7 +1392,7 @@ static int parse_ids(bool metric_no_merge, struct perf_pmu *fake_pmu, } } ret = metricgroup__build_event_string(&events, ids, modifier, - has_constraint); + group_events); if (ret) return ret; @@ -1458,7 +1457,7 @@ static int parse_groups(struct evlist *perf_evlist, const char *str, if (!ret && combined && hashmap__size(combined->ids)) { ret = parse_ids(metric_no_merge, fake_pmu, combined, /*modifier=*/NULL, - /*has_constraint=*/true, + /*group_events=*/false, tool_events, &combined_evlist); } @@ -1476,7 +1475,7 @@ static int parse_groups(struct evlist *perf_evlist, const char *str, struct metric *n; struct metric_expr *expr; - if (combined_evlist && m->has_constraint) { + if (combined_evlist && !m->group_events) { metric_evlist = combined_evlist; } else if (!metric_no_merge) { /* @@ -1507,7 +1506,7 @@ static int parse_groups(struct evlist *perf_evlist, const char *str, } if (!metric_evlist) { ret = parse_ids(metric_no_merge, fake_pmu, m->pctx, m->modifier, - m->has_constraint, tool_events, &m->evlist); + m->group_events, tool_events, &m->evlist); if (ret) goto out; -- cgit v1.2.3-58-ga151 From 36d19bbbdf9310699603203b332d69dc32c971d0 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:00 -0800 Subject: perf pmu-events: Remove aggr_mode from pmu_event aggr_mode is used on Power to set a flag for metrics. For pmu_event it is unused. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-4-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/jevents.py | 2 +- tools/perf/pmu-events/pmu-events.h | 1 - tools/perf/tests/pmu-events.c | 6 ------ 3 files changed, 1 insertion(+), 8 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index 2bcd07ce609f..db8b92de113e 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -44,7 +44,7 @@ _json_event_attributes = [ # Seems useful, put it early. 'event', # Short things in alphabetical order. - 'aggr_mode', 'compat', 'deprecated', 'perpkg', 'unit', + 'compat', 'deprecated', 'perpkg', 'unit', # Longer things (the last won't be iterated over during decompress). 'long_desc' ] diff --git a/tools/perf/pmu-events/pmu-events.h b/tools/perf/pmu-events/pmu-events.h index b7d4a66b8ad2..cee8b83792f8 100644 --- a/tools/perf/pmu-events/pmu-events.h +++ b/tools/perf/pmu-events/pmu-events.h @@ -22,7 +22,6 @@ struct pmu_event { const char *pmu; const char *unit; const char *perpkg; - const char *aggr_mode; const char *deprecated; }; diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c index accf44b3d968..9b4c94ba5460 100644 --- a/tools/perf/tests/pmu-events.c +++ b/tools/perf/tests/pmu-events.c @@ -331,12 +331,6 @@ static int compare_pmu_events(const struct pmu_event *e1, const struct pmu_event return -1; } - if (!is_same(e1->aggr_mode, e2->aggr_mode)) { - pr_debug2("testing event e1 %s: mismatched aggr_mode, %s vs %s\n", - e1->name, e1->aggr_mode, e2->aggr_mode); - return -1; - } - if (!is_same(e1->deprecated, e2->deprecated)) { pr_debug2("testing event e1 %s: mismatched deprecated, %s vs %s\n", e1->name, e1->deprecated, e2->deprecated); -- cgit v1.2.3-58-ga151 From 1fa0c371c9824743fe373e624a55cb036bbb2de1 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:01 -0800 Subject: perf pmu-events: Change aggr_mode to be an enum Rather than use a string to encode aggr_mode, use an enum value. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-5-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/powerpc/util/header.c | 2 +- tools/perf/pmu-events/jevents.py | 17 +++++++++++------ tools/perf/pmu-events/pmu-events.h | 2 +- 3 files changed, 13 insertions(+), 8 deletions(-) (limited to 'tools') diff --git a/tools/perf/arch/powerpc/util/header.c b/tools/perf/arch/powerpc/util/header.c index 78eef77d8a8d..c8d0dc775e5d 100644 --- a/tools/perf/arch/powerpc/util/header.c +++ b/tools/perf/arch/powerpc/util/header.c @@ -45,6 +45,6 @@ int arch_get_runtimeparam(const struct pmu_metric *pm) int count; char path[PATH_MAX] = "/devices/hv_24x7/interface/"; - atoi(pm->aggr_mode) == PerChip ? strcat(path, "sockets") : strcat(path, "coresperchip"); + strcat(path, pm->aggr_mode == PerChip ? "sockets" : "coresperchip"); return sysfs__read_int(path, &count) < 0 ? 1 : count; } diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index db8b92de113e..2b08d7c18f4b 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -678,10 +678,13 @@ static void decompress_event(int offset, struct pmu_event *pe) { \tconst char *p = &big_c_string[offset]; """) + enum_attributes = ['aggr_mode'] for attr in _json_event_attributes: - _args.output_file.write(f""" -\tpe->{attr} = (*p == '\\0' ? NULL : p); -""") + _args.output_file.write(f'\n\tpe->{attr} = ') + if attr in enum_attributes: + _args.output_file.write("(*p == '\\0' ? 0 : *p - '0');\n") + else: + _args.output_file.write("(*p == '\\0' ? NULL : p);\n") if attr == _json_event_attributes[-1]: continue _args.output_file.write('\twhile (*p++);') @@ -692,9 +695,11 @@ static void decompress_metric(int offset, struct pmu_metric *pm) \tconst char *p = &big_c_string[offset]; """) for attr in _json_metric_attributes: - _args.output_file.write(f""" -\tpm->{attr} = (*p == '\\0' ? NULL : p); -""") + _args.output_file.write(f'\n\tpm->{attr} = ') + if attr in enum_attributes: + _args.output_file.write("(*p == '\\0' ? 0 : *p - '0');\n") + else: + _args.output_file.write("(*p == '\\0' ? NULL : p);\n") if attr == _json_metric_attributes[-1]: continue _args.output_file.write('\twhile (*p++);') diff --git a/tools/perf/pmu-events/pmu-events.h b/tools/perf/pmu-events/pmu-events.h index cee8b83792f8..7225efc4e4df 100644 --- a/tools/perf/pmu-events/pmu-events.h +++ b/tools/perf/pmu-events/pmu-events.h @@ -31,10 +31,10 @@ struct pmu_metric { const char *metric_expr; const char *unit; const char *compat; - const char *aggr_mode; const char *metric_constraint; const char *desc; const char *long_desc; + enum aggr_mode_class aggr_mode; }; struct pmu_events_table; -- cgit v1.2.3-58-ga151 From 9ed8b7dcb0e7816294b2f8d8ab907e8c5402008d Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:02 -0800 Subject: perf pmu-events: Change deprecated to be a bool Switch to a more natural bool rather than string encoding, where NULL implicitly meant false. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-6-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/jevents.py | 2 +- tools/perf/pmu-events/pmu-events.h | 4 +++- tools/perf/tests/pmu-events.c | 4 ++-- tools/perf/util/pmu.c | 10 ++++------ 4 files changed, 10 insertions(+), 10 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index 2b08d7c18f4b..35ca34eca74a 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -678,7 +678,7 @@ static void decompress_event(int offset, struct pmu_event *pe) { \tconst char *p = &big_c_string[offset]; """) - enum_attributes = ['aggr_mode'] + enum_attributes = ['aggr_mode', 'deprecated'] for attr in _json_event_attributes: _args.output_file.write(f'\n\tpe->{attr} = ') if attr in enum_attributes: diff --git a/tools/perf/pmu-events/pmu-events.h b/tools/perf/pmu-events/pmu-events.h index 7225efc4e4df..2434bc7cf92d 100644 --- a/tools/perf/pmu-events/pmu-events.h +++ b/tools/perf/pmu-events/pmu-events.h @@ -2,6 +2,8 @@ #ifndef PMU_EVENTS_H #define PMU_EVENTS_H +#include + struct perf_pmu; enum aggr_mode_class { @@ -22,7 +24,7 @@ struct pmu_event { const char *pmu; const char *unit; const char *perpkg; - const char *deprecated; + bool deprecated; }; struct pmu_metric { diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c index 9b4c94ba5460..937804c84e29 100644 --- a/tools/perf/tests/pmu-events.c +++ b/tools/perf/tests/pmu-events.c @@ -331,8 +331,8 @@ static int compare_pmu_events(const struct pmu_event *e1, const struct pmu_event return -1; } - if (!is_same(e1->deprecated, e2->deprecated)) { - pr_debug2("testing event e1 %s: mismatched deprecated, %s vs %s\n", + if (e1->deprecated != e2->deprecated) { + pr_debug2("testing event e1 %s: mismatched deprecated, %d vs %d\n", e1->name, e1->deprecated, e2->deprecated); return -1; } diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index c256b29defad..80644e25a568 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -331,14 +331,15 @@ static int __perf_pmu__new_alias(struct list_head *list, char *dir, char *name, int num; char newval[256]; char *long_desc = NULL, *topic = NULL, *unit = NULL, *perpkg = NULL, - *deprecated = NULL, *pmu_name = NULL; + *pmu_name = NULL; + bool deprecated = false; if (pe) { long_desc = (char *)pe->long_desc; topic = (char *)pe->topic; unit = (char *)pe->unit; perpkg = (char *)pe->perpkg; - deprecated = (char *)pe->deprecated; + deprecated = pe->deprecated; pmu_name = (char *)pe->pmu; } @@ -351,7 +352,7 @@ static int __perf_pmu__new_alias(struct list_head *list, char *dir, char *name, alias->unit[0] = '\0'; alias->per_pkg = false; alias->snapshot = false; - alias->deprecated = false; + alias->deprecated = deprecated; ret = parse_events_terms(&alias->terms, val); if (ret) { @@ -405,9 +406,6 @@ static int __perf_pmu__new_alias(struct list_head *list, char *dir, char *name, alias->str = strdup(newval); alias->pmu_name = pmu_name ? strdup(pmu_name) : NULL; - if (deprecated) - alias->deprecated = true; - if (!perf_pmu_merge_alias(alias, list)) list_add_tail(&alias->list, list); -- cgit v1.2.3-58-ga151 From bd6808618ceb7d5bb4d5488afc030b48ae612f63 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:03 -0800 Subject: perf pmu-events: Change perpkg to be a bool Switch to a more natural bool rather than string encoding, where NULL implicitly meant false. The only value of 'PerPkg' in the event json is '1'. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-7-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/jevents.py | 2 +- tools/perf/pmu-events/pmu-events.h | 2 +- tools/perf/tests/pmu-events.c | 4 ++-- tools/perf/util/pmu.c | 11 ++++------- 4 files changed, 8 insertions(+), 11 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index 35ca34eca74a..2da55408398f 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -678,7 +678,7 @@ static void decompress_event(int offset, struct pmu_event *pe) { \tconst char *p = &big_c_string[offset]; """) - enum_attributes = ['aggr_mode', 'deprecated'] + enum_attributes = ['aggr_mode', 'deprecated', 'perpkg'] for attr in _json_event_attributes: _args.output_file.write(f'\n\tpe->{attr} = ') if attr in enum_attributes: diff --git a/tools/perf/pmu-events/pmu-events.h b/tools/perf/pmu-events/pmu-events.h index 2434bc7cf92d..4d236bb32fd3 100644 --- a/tools/perf/pmu-events/pmu-events.h +++ b/tools/perf/pmu-events/pmu-events.h @@ -23,7 +23,7 @@ struct pmu_event { const char *long_desc; const char *pmu; const char *unit; - const char *perpkg; + bool perpkg; bool deprecated; }; diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c index 937804c84e29..521557c396bc 100644 --- a/tools/perf/tests/pmu-events.c +++ b/tools/perf/tests/pmu-events.c @@ -325,8 +325,8 @@ static int compare_pmu_events(const struct pmu_event *e1, const struct pmu_event return -1; } - if (!is_same(e1->perpkg, e2->perpkg)) { - pr_debug2("testing event e1 %s: mismatched perpkg, %s vs %s\n", + if (e1->perpkg != e2->perpkg) { + pr_debug2("testing event e1 %s: mismatched perpkg, %d vs %d\n", e1->name, e1->perpkg, e2->perpkg); return -1; } diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 80644e25a568..43b6182d96b7 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -328,17 +328,15 @@ static int __perf_pmu__new_alias(struct list_head *list, char *dir, char *name, struct parse_events_term *term; struct perf_pmu_alias *alias; int ret; - int num; char newval[256]; - char *long_desc = NULL, *topic = NULL, *unit = NULL, *perpkg = NULL, - *pmu_name = NULL; - bool deprecated = false; + char *long_desc = NULL, *topic = NULL, *unit = NULL, *pmu_name = NULL; + bool deprecated = false, perpkg = false; if (pe) { long_desc = (char *)pe->long_desc; topic = (char *)pe->topic; unit = (char *)pe->unit; - perpkg = (char *)pe->perpkg; + perpkg = pe->perpkg; deprecated = pe->deprecated; pmu_name = (char *)pe->pmu; } @@ -350,7 +348,7 @@ static int __perf_pmu__new_alias(struct list_head *list, char *dir, char *name, INIT_LIST_HEAD(&alias->terms); alias->scale = 1.0; alias->unit[0] = '\0'; - alias->per_pkg = false; + alias->per_pkg = perpkg; alias->snapshot = false; alias->deprecated = deprecated; @@ -402,7 +400,6 @@ static int __perf_pmu__new_alias(struct list_head *list, char *dir, char *name, return -1; snprintf(alias->unit, sizeof(alias->unit), "%s", unit); } - alias->per_pkg = perpkg && sscanf(perpkg, "%d", &num) == 1 && num == 1; alias->str = strdup(newval); alias->pmu_name = pmu_name ? strdup(pmu_name) : NULL; -- cgit v1.2.3-58-ga151 From 207f7df7271c346da4a421c5b8cdadda99a37964 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:04 -0800 Subject: perf expr: Make the online topology accessible globally Knowing the topology of online CPUs is useful for more than just expr literals. Move to a global function that caches the value. An additional upside is that this may also avoid computing the CPU topology in some situations. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-8-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/expr.c | 7 ++----- tools/perf/util/cputopo.c | 14 ++++++++++++++ tools/perf/util/cputopo.h | 5 +++++ tools/perf/util/expr.c | 16 ++++++---------- tools/perf/util/smt.c | 11 +++++------ tools/perf/util/smt.h | 12 ++++++------ 6 files changed, 38 insertions(+), 27 deletions(-) (limited to 'tools') diff --git a/tools/perf/tests/expr.c b/tools/perf/tests/expr.c index a9eb1ed6bd63..cbf0e0c74906 100644 --- a/tools/perf/tests/expr.c +++ b/tools/perf/tests/expr.c @@ -154,13 +154,10 @@ static int test__expr(struct test_suite *t __maybe_unused, int subtest __maybe_u /* Only EVENT1 or EVENT2 need be measured depending on the value of smt_on. */ { - struct cpu_topology *topology = cpu_topology__new(); - bool smton = smt_on(topology); + bool smton = smt_on(); bool corewide = core_wide(/*system_wide=*/false, - /*user_requested_cpus=*/false, - topology); + /*user_requested_cpus=*/false); - cpu_topology__delete(topology); expr__ctx_clear(ctx); TEST_ASSERT_VAL("find ids", expr__find_ids("EVENT1 if #smt_on else EVENT2", diff --git a/tools/perf/util/cputopo.c b/tools/perf/util/cputopo.c index e08797c3cdbc..ca1d833a0c26 100644 --- a/tools/perf/util/cputopo.c +++ b/tools/perf/util/cputopo.c @@ -238,6 +238,20 @@ static bool has_die_topology(void) return true; } +const struct cpu_topology *online_topology(void) +{ + static const struct cpu_topology *topology; + + if (!topology) { + topology = cpu_topology__new(); + if (!topology) { + pr_err("Error creating CPU topology"); + abort(); + } + } + return topology; +} + struct cpu_topology *cpu_topology__new(void) { struct cpu_topology *tp = NULL; diff --git a/tools/perf/util/cputopo.h b/tools/perf/util/cputopo.h index 969e5920a00e..8d42f6102954 100644 --- a/tools/perf/util/cputopo.h +++ b/tools/perf/util/cputopo.h @@ -56,6 +56,11 @@ struct hybrid_topology { struct hybrid_topology_node nodes[]; }; +/* + * The topology for online CPUs, lazily created. + */ +const struct cpu_topology *online_topology(void); + struct cpu_topology *cpu_topology__new(void); void cpu_topology__delete(struct cpu_topology *tp); /* Determine from the core list whether SMT was enabled. */ diff --git a/tools/perf/util/expr.c b/tools/perf/util/expr.c index c1da20b868db..d46a1878bc9e 100644 --- a/tools/perf/util/expr.c +++ b/tools/perf/util/expr.c @@ -402,7 +402,7 @@ double arch_get_tsc_freq(void) double expr__get_literal(const char *literal, const struct expr_scanner_ctx *ctx) { - static struct cpu_topology *topology; + const struct cpu_topology *topology; double result = NAN; if (!strcmp("#num_cpus", literal)) { @@ -421,31 +421,27 @@ double expr__get_literal(const char *literal, const struct expr_scanner_ctx *ctx * these strings gives an indication of the number of packages, dies, * etc. */ - if (!topology) { - topology = cpu_topology__new(); - if (!topology) { - pr_err("Error creating CPU topology"); - goto out; - } - } if (!strcasecmp("#smt_on", literal)) { - result = smt_on(topology) ? 1.0 : 0.0; + result = smt_on() ? 1.0 : 0.0; goto out; } if (!strcmp("#core_wide", literal)) { - result = core_wide(ctx->system_wide, ctx->user_requested_cpu_list, topology) + result = core_wide(ctx->system_wide, ctx->user_requested_cpu_list) ? 1.0 : 0.0; goto out; } if (!strcmp("#num_packages", literal)) { + topology = online_topology(); result = topology->package_cpus_lists; goto out; } if (!strcmp("#num_dies", literal)) { + topology = online_topology(); result = topology->die_cpus_lists; goto out; } if (!strcmp("#num_cores", literal)) { + topology = online_topology(); result = topology->core_cpus_lists; goto out; } diff --git a/tools/perf/util/smt.c b/tools/perf/util/smt.c index 994e9e418227..650e804d0adc 100644 --- a/tools/perf/util/smt.c +++ b/tools/perf/util/smt.c @@ -4,7 +4,7 @@ #include "cputopo.h" #include "smt.h" -bool smt_on(const struct cpu_topology *topology) +bool smt_on(void) { static bool cached; static bool cached_result; @@ -16,22 +16,21 @@ bool smt_on(const struct cpu_topology *topology) if (sysfs__read_int("devices/system/cpu/smt/active", &fs_value) >= 0) cached_result = (fs_value == 1); else - cached_result = cpu_topology__smt_on(topology); + cached_result = cpu_topology__smt_on(online_topology()); cached = true; return cached_result; } -bool core_wide(bool system_wide, const char *user_requested_cpu_list, - const struct cpu_topology *topology) +bool core_wide(bool system_wide, const char *user_requested_cpu_list) { /* If not everything running on a core is being recorded then we can't use core_wide. */ if (!system_wide) return false; /* Cheap case that SMT is disabled and therefore we're inherently core_wide. */ - if (!smt_on(topology)) + if (!smt_on()) return true; - return cpu_topology__core_wide(topology, user_requested_cpu_list); + return cpu_topology__core_wide(online_topology(), user_requested_cpu_list); } diff --git a/tools/perf/util/smt.h b/tools/perf/util/smt.h index ae9095f2c38c..01441fd2c0a2 100644 --- a/tools/perf/util/smt.h +++ b/tools/perf/util/smt.h @@ -2,16 +2,16 @@ #ifndef __SMT_H #define __SMT_H 1 -struct cpu_topology; - -/* Returns true if SMT (aka hyperthreading) is enabled. */ -bool smt_on(const struct cpu_topology *topology); +/* + * Returns true if SMT (aka hyperthreading) is enabled. Determined via sysfs or + * the online topology. + */ +bool smt_on(void); /* * Returns true when system wide and all SMT threads for a core are in the * user_requested_cpus map. */ -bool core_wide(bool system_wide, const char *user_requested_cpu_list, - const struct cpu_topology *topology); +bool core_wide(bool system_wide, const char *user_requested_cpu_list); #endif /* __SMT_H */ -- cgit v1.2.3-58-ga151 From 900536349d12516114eed9f5b47d30c362e68cdc Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:05 -0800 Subject: perf pmu-events: Make the metric_constraint an enum Rename metric_constraint to event_grouping to better explain what the variable is used for. Switch to use an enum for encoding instead of a string. Rather than just no constraint/grouping information or "NO_NMI_WATCHDOG", have 4 enum values. The values encode whether to group or not, and two cases where the behavior is dependent on either the NMI watchdog being enabled or SMT being enabled. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-9-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/jevents.py | 20 ++++++++++++++++---- tools/perf/pmu-events/pmu-events.h | 25 ++++++++++++++++++++++++- tools/perf/util/metricgroup.c | 19 ++++++++++++------- 3 files changed, 52 insertions(+), 12 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index 2da55408398f..dc0c56dccb5e 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -51,8 +51,8 @@ _json_event_attributes = [ # Attributes that are in pmu_metric rather than pmu_event. _json_metric_attributes = [ - 'metric_name', 'metric_group', 'metric_constraint', 'metric_expr', 'desc', - 'long_desc', 'unit', 'compat', 'aggr_mode' + 'metric_name', 'metric_group', 'metric_expr', 'desc', + 'long_desc', 'unit', 'compat', 'aggr_mode', 'event_grouping' ] def removesuffix(s: str, suffix: str) -> str: @@ -204,6 +204,18 @@ class JsonEvent: } return aggr_mode_to_enum[aggr_mode] + def convert_metric_constraint(metric_constraint: str) -> Optional[str]: + """Returns the metric_event_groups enum value associated with the JSON string.""" + if not metric_constraint: + return None + metric_constraint_to_enum = { + 'NO_GROUP_EVENTS': '1', + 'NO_GROUP_EVENTS_NMI': '2', + 'NO_NMI_WATCHDOG': '2', + 'NO_GROUP_EVENTS_SMT': '3', + } + return metric_constraint_to_enum[metric_constraint] + def lookup_msr(num: str) -> Optional[str]: """Converts the msr number, or first in a list to the appropriate event field.""" if not num: @@ -288,7 +300,7 @@ class JsonEvent: self.deprecated = jd.get('Deprecated') self.metric_name = jd.get('MetricName') self.metric_group = jd.get('MetricGroup') - self.metric_constraint = jd.get('MetricConstraint') + self.event_grouping = convert_metric_constraint(jd.get('MetricConstraint')) self.metric_expr = None if 'MetricExpr' in jd: self.metric_expr = metric.ParsePerfJson(jd['MetricExpr']).Simplify() @@ -678,7 +690,7 @@ static void decompress_event(int offset, struct pmu_event *pe) { \tconst char *p = &big_c_string[offset]; """) - enum_attributes = ['aggr_mode', 'deprecated', 'perpkg'] + enum_attributes = ['aggr_mode', 'deprecated', 'event_grouping', 'perpkg'] for attr in _json_event_attributes: _args.output_file.write(f'\n\tpe->{attr} = ') if attr in enum_attributes: diff --git a/tools/perf/pmu-events/pmu-events.h b/tools/perf/pmu-events/pmu-events.h index 4d236bb32fd3..57a38e3e5c32 100644 --- a/tools/perf/pmu-events/pmu-events.h +++ b/tools/perf/pmu-events/pmu-events.h @@ -11,6 +11,29 @@ enum aggr_mode_class { PerCore }; +/** + * enum metric_event_groups - How events within a pmu_metric should be grouped. + */ +enum metric_event_groups { + /** + * @MetricGroupEvents: Default, group events within the metric. + */ + MetricGroupEvents = 0, + /** + * @MetricNoGroupEvents: Don't group events for the metric. + */ + MetricNoGroupEvents = 1, + /** + * @MetricNoGroupEventsNmi: Don't group events for the metric if the NMI + * watchdog is enabled. + */ + MetricNoGroupEventsNmi = 2, + /** + * @MetricNoGroupEventsSmt: Don't group events for the metric if SMT is + * enabled. + */ + MetricNoGroupEventsSmt = 3, +}; /* * Describe each PMU event. Each CPU has a table of PMU events. */ @@ -33,10 +56,10 @@ struct pmu_metric { const char *metric_expr; const char *unit; const char *compat; - const char *metric_constraint; const char *desc; const char *long_desc; enum aggr_mode_class aggr_mode; + enum metric_event_groups event_grouping; }; struct pmu_events_table; diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index b2aa6e049804..868fc9c35606 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -13,6 +13,7 @@ #include "pmu.h" #include "pmu-hybrid.h" #include "print-events.h" +#include "smt.h" #include "expr.h" #include "rblist.h" #include @@ -168,16 +169,20 @@ static void metric__watchdog_constraint_hint(const char *name, bool foot) static bool metric__group_events(const struct pmu_metric *pm) { - if (!pm->metric_constraint) - return true; - - if (!strcmp(pm->metric_constraint, "NO_NMI_WATCHDOG") && - sysctl__nmi_watchdog_enabled()) { + switch (pm->event_grouping) { + case MetricNoGroupEvents: + return false; + case MetricNoGroupEventsNmi: + if (!sysctl__nmi_watchdog_enabled()) + return true; metric__watchdog_constraint_hint(pm->metric_name, /*foot=*/false); return false; + case MetricNoGroupEventsSmt: + return !smt_on(); + case MetricGroupEvents: + default: + return true; } - - return true; } static void metric__free(struct metric *m) -- cgit v1.2.3-58-ga151 From aa44724cb3179228bbfa509649ef021d14e4476f Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:06 -0800 Subject: perf pmu-events: Don't '\0' terminate enum values Encoding enums like '1\0' wastes a byte and could be '1' (no '\0' terminator) if the 0 case is '0', it also removes a branch for decompressing. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-10-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/jevents.py | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index dc0c56dccb5e..e82dff3a1228 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -54,6 +54,8 @@ _json_metric_attributes = [ 'metric_name', 'metric_group', 'metric_expr', 'desc', 'long_desc', 'unit', 'compat', 'aggr_mode', 'event_grouping' ] +# Attributes that are bools or enum int values, encoded as '0', '1',... +_json_enum_attributes = ['aggr_mode', 'deprecated', 'event_grouping', 'perpkg'] def removesuffix(s: str, suffix: str) -> str: """Remove the suffix from a string @@ -360,7 +362,10 @@ class JsonEvent: # Convert parsed metric expressions into a string. Slashes # must be doubled in the file. x = x.ToPerfJson().replace('\\', '\\\\') - s += f'{x}\\000' if x else '\\000' + if attr in _json_enum_attributes: + s += x if x else '0' + else: + s += f'{x}\\000' if x else '\\000' return s def to_c_string(self, metric: bool) -> str: @@ -690,16 +695,18 @@ static void decompress_event(int offset, struct pmu_event *pe) { \tconst char *p = &big_c_string[offset]; """) - enum_attributes = ['aggr_mode', 'deprecated', 'event_grouping', 'perpkg'] for attr in _json_event_attributes: _args.output_file.write(f'\n\tpe->{attr} = ') - if attr in enum_attributes: - _args.output_file.write("(*p == '\\0' ? 0 : *p - '0');\n") + if attr in _json_enum_attributes: + _args.output_file.write("*p - '0';\n") else: _args.output_file.write("(*p == '\\0' ? NULL : p);\n") if attr == _json_event_attributes[-1]: continue - _args.output_file.write('\twhile (*p++);') + if attr in _json_enum_attributes: + _args.output_file.write('\tp++;') + else: + _args.output_file.write('\twhile (*p++);') _args.output_file.write("""} static void decompress_metric(int offset, struct pmu_metric *pm) @@ -708,13 +715,16 @@ static void decompress_metric(int offset, struct pmu_metric *pm) """) for attr in _json_metric_attributes: _args.output_file.write(f'\n\tpm->{attr} = ') - if attr in enum_attributes: - _args.output_file.write("(*p == '\\0' ? 0 : *p - '0');\n") + if attr in _json_enum_attributes: + _args.output_file.write("*p - '0';\n") else: _args.output_file.write("(*p == '\\0' ? NULL : p);\n") if attr == _json_metric_attributes[-1]: continue - _args.output_file.write('\twhile (*p++);') + if attr in _json_enum_attributes: + _args.output_file.write('\tp++;') + else: + _args.output_file.write('\twhile (*p++);') _args.output_file.write("""} int pmu_events_table_for_each_event(const struct pmu_events_table *table, -- cgit v1.2.3-58-ga151 From ad10c9201d827f85195eb4d94bfcfd2b2ca000f4 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:07 -0800 Subject: perf vendor events intel: Refresh alderlake events Update the alderlake events from 1.16 to 1.18. Generation was done using https://github.com/intel/perfmon. Notable changes are new events and event descriptions, TMA metrics are updated to version 4.5, TMA info metrics are renamed from their node name to be lower case and prefixed by tma_info_, MetricThreshold expressions are added, smi_cost and transaction metric groups are added replicating existing hard coded metrics in stat-shadow. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-11-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/alderlake/adl-metrics.json | 3190 +++++++++++--------- .../perf/pmu-events/arch/x86/alderlake/cache.json | 36 +- .../arch/x86/alderlake/floating-point.json | 27 + .../pmu-events/arch/x86/alderlake/frontend.json | 9 + .../perf/pmu-events/arch/x86/alderlake/memory.json | 3 +- .../pmu-events/arch/x86/alderlake/pipeline.json | 14 +- .../arch/x86/alderlake/uncore-other.json | 28 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 8 files changed, 1902 insertions(+), 1407 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json b/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json index 2eb3d7464d9f..7bb8410a2bf9 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json @@ -1,2034 +1,2440 @@ [ { - "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / SLOTS", - "MetricGroup": "PGO;TopdownL1;tma_L1_group", - "MetricName": "tma_frontend_bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "C10 residency percent per package", + "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C10_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", - "MetricExpr": "topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / SLOTS", - "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_latency", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "C1 residency percent per core", + "MetricExpr": "cstate_core@c1\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C1_Core_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses", - "MetricExpr": "ICACHE_DATA.STALLS / CLKS", - "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_icache_misses", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "C2 residency percent per package", + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C2_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", - "MetricExpr": "ICACHE_TAG.STALLS / CLKS", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_itlb_misses", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "C3 residency percent per package", + "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", - "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CLKS + tma_unknown_branches", - "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_branch_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage", - "MetricExpr": "tma_branch_mispredicts / tma_bad_speculation * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group", - "MetricName": "tma_mispredicts_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears", - "MetricExpr": "(1 - tma_branch_mispredicts / tma_bad_speculation) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS", - "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group", - "MetricName": "tma_clears_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "C7 residency percent per core", + "MetricExpr": "cstate_core@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Core_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", - "MetricExpr": "INT_MISC.UNKNOWN_BRANCH_CYCLES / CLKS", - "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_branch_resteers_group", - "MetricName": "tma_unknown_branches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit). Sample with: FRONTEND_RETIRED.UNKNOWN_BRANCH", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "C7 residency percent per package", + "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_dsb_switches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "C8 residency percent per package", + "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C8_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", - "MetricExpr": "DECODE.LCP / CLKS", - "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_lcp", - "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "C9 residency percent per package", + "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C9_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", - "MetricExpr": "3 * IDQ.MS_SWITCHES / CLKS", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_ms_switches", - "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: FRONTEND_RETIRED.MS_FLOWS", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "tma_info_socket_clks / #num_dies / duration_time / 1e9", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", - "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)", - "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_bandwidth", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Percentage of cycles spent in System Management Interrupts.", + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", + "MetricGroup": "smi", + "MetricName": "smi_cycles", + "MetricThreshold": "smi_cycles > 0.1", + "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", - "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / CORE_CLKS / 2", - "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_group", - "MetricName": "tma_mite", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Number of SMI interrupts.", + "MetricExpr": "msr@smi@", + "MetricGroup": "smi", + "MetricName": "smi_num", + "ScaleUnit": "1SMI#" }, { - "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", - "MetricExpr": "(cpu_core@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu_core@INST_DECODED.DECODERS\\,cmask\\=2@) / CORE_CLKS", - "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_mite_group", - "MetricName": "tma_decoder0_alone", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Percentage of cycles in aborted transactions.", + "MetricExpr": "max(cpu@cycles\\-t@ - cpu@cycles\\-ct@, 0) / cycles", + "MetricGroup": "transaction", + "MetricName": "tsx_aborted_cycles", + "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", - "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / CORE_CLKS / 2", - "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group", - "MetricName": "tma_dsb", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Number of cycles within a transaction divided by the number of elisions.", + "MetricExpr": "cpu@cycles\\-t@ / cpu@el\\-start@", + "MetricGroup": "transaction", + "MetricName": "tsx_cycles_per_elision", + "ScaleUnit": "1cycles / elision" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit", - "MetricExpr": "(LSD.CYCLES_ACTIVE - LSD.CYCLES_OK) / CORE_CLKS / 2", - "MetricGroup": "FetchBW;LSD;TopdownL3;tma_fetch_bandwidth_group", - "MetricName": "tma_lsd", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit. LSD typically does well sustaining Uop supply. However; in some rare cases; optimal uop-delivery could not be reached for small loops whose size (in terms of number of uops) does not suit well the LSD structure.", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Number of cycles within a transaction divided by the number of transactions.", + "MetricExpr": "cpu@cycles\\-t@ / cpu@tx\\-start@", + "MetricGroup": "transaction", + "MetricName": "tsx_cycles_per_transaction", + "ScaleUnit": "1cycles / transaction" }, { - "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", - "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_bad_speculation", - "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Percentage of cycles within a transaction region.", + "MetricExpr": "cpu@cycles\\-t@ / cycles", + "MetricGroup": "transaction", + "MetricName": "tsx_transactional_cycles", + "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", - "MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_branch_mispredicts", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS", + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions.", + "MetricExpr": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_alloc_restriction", + "MetricThreshold": "tma_alloc_restriction > 0.1", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", - "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)", - "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_machine_clears", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT", + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls", + "MetricExpr": "TOPDOWN_BE_BOUND.ALL / tma_info_slots", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_backend_bound", + "MetricThreshold": "tma_backend_bound > 0.1", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. The rest of these subevents count backend stalls, in cycles, due to an outstanding request which is memory bound vs core bound. The subevents are not slot based events and therefore can not be precisely added or subtracted from the Backend_Bound_Aux subevents which are slot based.", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", - "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS", + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls", + "MetricExpr": "tma_backend_bound", "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_backend_bound", - "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", + "MetricName": "tma_backend_bound_aux", + "MetricThreshold": "tma_backend_bound_aux > 0.2", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that UOPS must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. All of these subevents count backend stalls, in slots, due to a resource limitation. These are not cycle based events and therefore can not be precisely added or subtracted from the Backend_Bound subevents which are cycle based. These subevents are supplementary to Backend_Bound and can be used to analyze results from a resource perspective at allocation.", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", - "MetricExpr": "topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS", - "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_memory_bound", - "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear", + "MetricExpr": "(tma_info_slots - (TOPDOWN_FE_BOUND.ALL + TOPDOWN_BE_BOUND.ALL + TOPDOWN_RETIRING.ALL)) / tma_info_slots", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_bad_speculation", + "MetricThreshold": "tma_bad_speculation > 0.15", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", - "MetricExpr": "max((EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS) / CLKS, 0)", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l1_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS", + "BriefDescription": "Counts the number of uops that are not from the microsequencer.", + "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS) / tma_info_slots", + "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_base", + "MetricThreshold": "tma_base > 0.6", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", - "MetricExpr": "min(7 * cpu_core@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS, 0)) / CLKS", - "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_dtlb_load", - "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS", + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend", + "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_DETECT / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_latency_group", + "MetricName": "tma_branch_detect", + "MetricThreshold": "tma_branch_detect > 0.05", + "PublicDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", - "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss", - "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group", - "MetricName": "tma_load_stlb_hit", + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to branch mispredicts.", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.MISPREDICT / tma_info_slots", + "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", + "MetricName": "tma_branch_mispredicts", + "MetricThreshold": "tma_branch_mispredicts > 0.05", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", - "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CLKS", - "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group", - "MetricName": "tma_load_stlb_miss", + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", + "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_RESTEER / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_latency_group", + "MetricName": "tma_branch_resteer", + "MetricThreshold": "tma_branch_resteer > 0.05", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", - "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_store_fwd_blk", - "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS).", + "MetricExpr": "TOPDOWN_FE_BOUND.CISC / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_bandwidth_group", + "MetricName": "tma_cisc", + "MetricThreshold": "tma_cisc > 0.05", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", - "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS", - "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_lock_latency", - "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS", + "BriefDescription": "Counts the number of cycles due to backend bound stalls that are core execution bound and not attributed to outstanding demand load or store stalls.", + "MetricExpr": "max(0, tma_backend_bound - tma_load_store_bound)", + "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "MetricThreshold": "tma_core_bound > 0.1", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", - "MetricExpr": "Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_split_loads", - "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS", + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to decode stalls.", + "MetricExpr": "TOPDOWN_FE_BOUND.DECODE / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_bandwidth_group", + "MetricName": "tma_decode", + "MetricThreshold": "tma_decode > 0.05", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", - "MetricExpr": "L1D_PEND_MISS.FB_FULL / CLKS", - "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_fb_full", - "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).", + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to memory disambiguation.", + "MetricExpr": "tma_nuke * (MACHINE_CLEARS.DISAMBIGUATION / MACHINE_CLEARS.SLOW)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", + "MetricName": "tma_disambiguation", + "MetricThreshold": "tma_disambiguation > 0.02", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", - "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS) / CLKS", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l2_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS", + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / tma_info_clks - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD", + "MetricGroup": "TopdownL3;tma_L3_group;tma_load_store_bound_group", + "MetricName": "tma_dram_bound", + "MetricThreshold": "tma_dram_bound > 0.1", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", - "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS) / CLKS", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l3_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear classified as a fast nuke due to memory ordering, memory disambiguation and memory renaming.", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.FASTNUKE / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group", + "MetricName": "tma_fast_nuke", + "MetricThreshold": "tma_fast_nuke > 0.05", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", - "MetricExpr": "(25 * Average_Frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 24 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_contested_accesses", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to FP assists.", + "MetricExpr": "tma_nuke * (MACHINE_CLEARS.FP_ASSIST / MACHINE_CLEARS.SLOW)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", + "MetricName": "tma_fp_assist", + "MetricThreshold": "tma_fp_assist > 0.02", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", - "MetricExpr": "24 * Average_Frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_data_sharing", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "BriefDescription": "Counts the number of floating point operations per uop with all default weighting.", + "MetricExpr": "UOPS_RETIRED.FPDIV / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_base_group", + "MetricName": "tma_fp_uops", + "MetricThreshold": "tma_fp_uops > 0.2", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", - "MetricExpr": "9 * Average_Frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS", - "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_l3_hit_latency", - "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", + "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / tma_info_slots", + "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_frontend_bandwidth", + "MetricThreshold": "tma_frontend_bandwidth > 0.1", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", - "MetricExpr": "(XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS) / CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_sq_full", - "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.", + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to frontend stalls.", + "MetricExpr": "TOPDOWN_FE_BOUND.ALL / tma_info_slots", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.2", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", - "MetricExpr": "MEMORY_ACTIVITY.STALLS_L3_MISS / CLKS", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_dram_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS", + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", + "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY / tma_info_slots", + "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_frontend_latency", + "MetricThreshold": "tma_frontend_latency > 0.15", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu_core@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group", - "MetricName": "tma_mem_bandwidth", - "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses.", + "MetricExpr": "TOPDOWN_FE_BOUND.ICACHE / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_latency_group", + "MetricName": "tma_icache", + "MetricThreshold": "tma_icache > 0.05", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group", - "MetricName": "tma_mem_latency", - "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Percentage of total non-speculative loads with a address aliasing block", + "MetricExpr": "100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricName": "tma_info_address_alias_blocks", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", - "MetricExpr": "tma_st_buffer", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_store_bound", - "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Ratio of all branches which mispredict", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": " ", + "MetricName": "tma_info_branch_mispredict_ratio", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", - "MetricExpr": "(MEM_STORE_RETIRED.L2_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group", - "MetricName": "tma_store_latency", - "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Ratio between Mispredicted branches and unknown branches", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BACLEARS.ANY", + "MetricGroup": " ", + "MetricName": "tma_info_branch_mispredict_to_unknown_branch_ratio", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", - "MetricExpr": "28 * Average_Frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group", - "MetricName": "tma_false_sharing", - "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "", + "MetricExpr": "CPU_CLK_UNHALTED.CORE", + "MetricGroup": " ", + "MetricName": "tma_info_clks", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents rate of split store accesses", - "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CORE_CLKS", - "MetricGroup": "TopdownL4;tma_store_bound_group", - "MetricName": "tma_split_stores", - "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "", + "MetricExpr": "CPU_CLK_UNHALTED.CORE_P", + "MetricGroup": " ", + "MetricName": "tma_info_clks_p", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores", - "MetricExpr": "9 * OCR.STREAMING_WR.ANY_RESPONSE / CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_store_bound_group", - "MetricName": "tma_streaming_stores", - "PublicDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck. Sample with: OCR.STREAMING_WR.ANY_RESPONSE", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Cycles Per Instruction", + "MetricExpr": "tma_info_clks / INST_RETIRED.ANY", + "MetricGroup": " ", + "MetricName": "tma_info_cpi", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", - "MetricExpr": "(7 * cpu_core@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CORE_CLKS", - "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group", - "MetricName": "tma_dtlb_store", - "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": " ", + "MetricName": "tma_info_cpu_utilization", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", - "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss", - "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group", - "MetricName": "tma_store_stlb_hit", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Cycle cost per DRAM hit", + "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_LOAD_UOPS_RETIRED.DRAM_HIT", + "MetricGroup": " ", + "MetricName": "tma_info_cycles_per_demand_load_dram_hit", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", - "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS", - "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group", - "MetricName": "tma_store_stlb_miss", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Cycle cost per L2 hit", + "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_LOAD_UOPS_RETIRED.L2_HIT", + "MetricGroup": " ", + "MetricName": "tma_info_cycles_per_demand_load_l2_hit", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", - "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)", - "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_core_bound", - "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Cycle cost per LLC hit", + "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_LOAD_UOPS_RETIRED.L3_HIT", + "MetricGroup": " ", + "MetricName": "tma_info_cycles_per_demand_load_l3_hit", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", - "MetricExpr": "ARITH.DIVIDER_ACTIVE / CLKS", - "MetricGroup": "TopdownL3;tma_core_bound_group", - "MetricName": "tma_divider", - "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Percentage of all uops which are FPDiv uops", + "MetricExpr": "100 * UOPS_RETIRED.FPDIV / UOPS_RETIRED.ALL", + "MetricGroup": " ", + "MetricName": "tma_info_fpdiv_uop_ratio", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", - "MetricExpr": "((cpu_core@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@)) / CLKS if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@) / CLKS)", - "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group", - "MetricName": "tma_ports_utilization", - "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Percentage of all uops which are IDiv uops", + "MetricExpr": "100 * UOPS_RETIRED.IDIV / UOPS_RETIRED.ALL", + "MetricGroup": " ", + "MetricName": "tma_info_idiv_uop_ratio", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "cpu_core@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ / CLKS + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS) / CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_0", - "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Percent of instruction miss cost that hit in DRAM", + "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / MEM_BOUND_STALLS.IFETCH", + "MetricGroup": " ", + "MetricName": "tma_info_inst_miss_cost_dramhit_percent", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations", - "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / CLKS", - "MetricGroup": "TopdownL5;tma_ports_utilized_0_group", - "MetricName": "tma_serializing_operation", - "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Percent of instruction miss cost that hit in the L2", + "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / MEM_BOUND_STALLS.IFETCH", + "MetricGroup": " ", + "MetricName": "tma_info_inst_miss_cost_l2hit_percent", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions", - "MetricExpr": "CPU_CLK_UNHALTED.PAUSE / CLKS", - "MetricGroup": "TopdownL6;tma_serializing_operation_group", - "MetricName": "tma_slow_pause", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: CPU_CLK_UNHALTED.PAUSE_INST", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Percent of instruction miss cost that hit in the L3", + "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / MEM_BOUND_STALLS.IFETCH", + "MetricGroup": " ", + "MetricName": "tma_info_inst_miss_cost_l3hit_percent", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions.", - "MetricExpr": "13 * MISC2_RETIRED.LFENCE / CLKS", - "MetricGroup": "TopdownL6;tma_serializing_operation_group", - "MetricName": "tma_memory_fence", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Instructions per Branch (lower number means higher occurance rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": " ", + "MetricName": "tma_info_ipbranch", + "Unit": "cpu_atom" }, { - "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued", - "MetricExpr": "160 * ASSISTS.SSE_AVX_MIX / CLKS", - "MetricGroup": "TopdownL5;tma_ports_utilized_0_group", - "MetricName": "tma_mixing_vectors", - "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Instructions Per Cycle", + "MetricExpr": "INST_RETIRED.ANY / tma_info_clks", + "MetricGroup": " ", + "MetricName": "tma_info_ipc", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "EXE_ACTIVITY.1_PORTS_UTIL / CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_1", - "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Instruction per (near) call (lower number means higher occurance rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.CALL", + "MetricGroup": " ", + "MetricName": "tma_info_ipcall", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "EXE_ACTIVITY.2_PORTS_UTIL / CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_2", - "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Instructions per Far Branch", + "MetricExpr": "INST_RETIRED.ANY / (BR_INST_RETIRED.FAR_BRANCH / 2)", + "MetricGroup": " ", + "MetricName": "tma_info_ipfarbranch", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_3m", - "PublicDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Instructions per Load", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": " ", + "MetricName": "tma_info_ipload", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5_11 + UOPS_DISPATCHED.PORT_6) / (5 * CORE_CLKS)", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_alu_op_utilization", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": " ", + "MetricName": "tma_info_ipmispredict", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) Sample with: UOPS_DISPATCHED.PORT_0", - "MetricExpr": "UOPS_DISPATCHED.PORT_0 / CORE_CLKS", - "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_0", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Instructions per Store", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": " ", + "MetricName": "tma_info_ipstore", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHED.PORT_1", - "MetricExpr": "UOPS_DISPATCHED.PORT_1 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_1", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Fraction of cycles spent in Kernel mode", + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE@k / CPU_CLK_UNHALTED.CORE", + "MetricGroup": " ", + "MetricName": "tma_info_kernel_utilization", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) Sample with: UOPS_DISPATCHED.PORT_6", - "MetricExpr": "UOPS_DISPATCHED.PORT_6 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_6", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Percentage of total non-speculative loads that are splits", + "MetricExpr": "100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricName": "tma_info_load_splits", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations Sample with: UOPS_DISPATCHED.PORT_2_3_10", - "MetricExpr": "UOPS_DISPATCHED.PORT_2_3_10 / (3 * CORE_CLKS)", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_load_op_utilization", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "load ops retired per 1000 instruction", + "MetricExpr": "1e3 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY", + "MetricGroup": " ", + "MetricName": "tma_info_memloadpki", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations Sample with: UOPS_DISPATCHED.PORT_7_8", - "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * CORE_CLKS)", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_store_op_utilization", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Percentage of all uops which are ucode ops", + "MetricExpr": "100 * UOPS_RETIRED.MS / UOPS_RETIRED.ALL", + "MetricGroup": " ", + "MetricName": "tma_info_microcode_uop_ratio", + "Unit": "cpu_atom" }, { - "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "", + "MetricExpr": "5 * tma_info_clks", + "MetricGroup": " ", + "MetricName": "tma_info_slots", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", - "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_light_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Percentage of total non-speculative loads with a store forward or unknown store address block", + "MetricExpr": "100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricName": "tma_info_store_fwd_blocks", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", - "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", - "MetricGroup": "HPC;TopdownL3;tma_light_operations_group", - "MetricName": "tma_fp_arith", - "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "tma_info_clks / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": " ", + "MetricName": "tma_info_turbo_utilization", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric serves as an approximation of legacy x87 usage", - "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD", - "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_x87_use", - "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "UOPS_RETIRED.ALL / INST_RETIRED.ANY", + "MetricGroup": " ", + "MetricName": "tma_info_upi", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / (tma_retiring * SLOTS)", - "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_fp_scalar", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", - "ScaleUnit": "100%", - "Unit": "cpu_core" + "BriefDescription": "Percentage of all uops which are x87 uops", + "MetricExpr": "100 * UOPS_RETIRED.X87 / UOPS_RETIRED.ALL", + "MetricGroup": " ", + "MetricName": "tma_info_x87_uop_ratio", + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", - "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / (tma_retiring * SLOTS)", - "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_fp_vector", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", + "MetricExpr": "TOPDOWN_FE_BOUND.ITLB / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_latency_group", + "MetricName": "tma_itlb", + "MetricThreshold": "tma_itlb > 0.05", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", - "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / (tma_retiring * SLOTS)", - "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group", - "MetricName": "tma_fp_vector_128b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.", + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a load block.", + "MetricExpr": "LD_HEAD.L1_BOUND_AT_RET / tma_info_clks", + "MetricGroup": "TopdownL3;tma_L3_group;tma_load_store_bound_group", + "MetricName": "tma_l1_bound", + "MetricThreshold": "tma_l1_bound > 0.1", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", - "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / (tma_retiring * SLOTS)", - "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group", - "MetricName": "tma_fp_vector_256b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.", + "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 Cache.", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / tma_info_clks - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD", + "MetricGroup": "TopdownL3;tma_L3_group;tma_load_store_bound_group", + "MetricName": "tma_l2_bound", + "MetricThreshold": "tma_l2_bound > 0.1", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired)", - "MetricExpr": "tma_int_vector_128b + tma_int_vector_256b + tma_shuffles", - "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group", - "MetricName": "tma_int_operations", - "PublicDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired). Vector/Matrix Int operations and shuffles are counted. Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain.", + "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", + "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / tma_info_clks - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD", + "MetricGroup": "TopdownL3;tma_L3_group;tma_load_store_bound_group", + "MetricName": "tma_l3_bound", + "MetricThreshold": "tma_l3_bound > 0.1", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.", - "MetricExpr": "(INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128) / (tma_retiring * SLOTS)", - "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_int_operations_group", - "MetricName": "tma_int_vector_128b", + "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to load buffer full", + "MetricExpr": "tma_mem_scheduler * MEM_SCHEDULER_BLOCK.LD_BUF / MEM_SCHEDULER_BLOCK.ALL", + "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", + "MetricName": "tma_ld_buffer", + "MetricThreshold": "tma_ld_buffer > 0.05", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.", - "MetricExpr": "(INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256) / (tma_retiring * SLOTS)", - "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_int_operations_group", - "MetricName": "tma_int_vector_256b", + "BriefDescription": "Counts the number of cycles the core is stalled due to stores or loads.", + "MetricExpr": "min(tma_backend_bound, LD_HEAD.ANY_AT_RET / tma_info_clks + tma_store_bound)", + "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_load_store_bound", + "MetricThreshold": "tma_load_store_bound > 0.2", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents Shuffle (cross \"vector lane\" data transfers) uops fraction the CPU has retired.", - "MetricExpr": "INT_VEC_RETIRED.SHUFFLES / (tma_retiring * SLOTS)", - "MetricGroup": "HPC;Pipeline;TopdownL4;tma_int_operations_group", - "MetricName": "tma_shuffles", + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS / tma_info_slots", + "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.05", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", - "MetricExpr": "tma_light_operations * MEM_UOP_RETIRED.ANY / (tma_retiring * SLOTS)", - "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group", - "MetricName": "tma_memory_operations", + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.", + "MetricExpr": "TOPDOWN_BE_BOUND.MEM_SCHEDULER / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_mem_scheduler", + "MetricThreshold": "tma_mem_scheduler > 0.1", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions", - "MetricExpr": "tma_light_operations * INST_RETIRED.MACRO_FUSED / (tma_retiring * SLOTS)", - "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group", - "MetricName": "tma_fused_instructions", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.", + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to memory ordering.", + "MetricExpr": "tma_nuke * (MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.SLOW)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", + "MetricName": "tma_memory_ordering", + "MetricThreshold": "tma_memory_ordering > 0.02", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused", - "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED) / (tma_retiring * SLOTS)", - "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group", - "MetricName": "tma_non_fused_branches", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", + "BriefDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS)", + "MetricExpr": "tma_microcode_sequencer", + "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_ms_uops", + "MetricThreshold": "tma_ms_uops > 0.05", + "PublicDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions", - "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (tma_retiring * SLOTS)", - "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group", - "MetricName": "tma_nop_instructions", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP", + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.", + "MetricExpr": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_non_mem_scheduler", + "MetricThreshold": "tma_non_mem_scheduler > 0.1", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", - "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_int_operations + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions))", - "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group", - "MetricName": "tma_other_light_ops", + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear (slow nuke).", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.NUKE / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group", + "MetricName": "tma_nuke", + "MetricThreshold": "tma_nuke > 0.05", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences", - "MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_heavy_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences. Sample with: UOPS_RETIRED.HEAVY", + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized.", + "MetricExpr": "TOPDOWN_FE_BOUND.OTHER / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_bandwidth_group", + "MetricName": "tma_other_fb", + "MetricThreshold": "tma_other_fb > 0.05", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops", - "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer", - "MetricGroup": "TopdownL3;tma_heavy_operations_group", - "MetricName": "tma_few_uops_instructions", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.", + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a number of other load blocks.", + "MetricExpr": "LD_HEAD.OTHER_AT_RET / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_other_l1", + "MetricThreshold": "tma_other_l1 > 0.05", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", - "MetricExpr": "tma_ms_uops", - "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group", - "MetricName": "tma_microcode_sequencer", - "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS", + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hits in the L2, LLC, DRAM or MMIO (Non-DRAM) but could not be correctly attributed or cycles in which the load miss is waiting on a request buffer.", + "MetricExpr": "max(0, tma_load_store_bound - (tma_store_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound))", + "MetricGroup": "TopdownL3;tma_L3_group;tma_load_store_bound_group", + "MetricName": "tma_other_load_store", + "MetricThreshold": "tma_other_load_store > 0.1", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", - "MetricExpr": "100 * cpu_core@ASSISTS.ANY\\,umask\\=0x1B@ / SLOTS", - "MetricGroup": "TopdownL4;tma_microcode_sequencer_group", - "MetricName": "tma_assists", - "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY", + "BriefDescription": "Counts the number of uops retired excluding ms and fp div uops.", + "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS - UOPS_RETIRED.FPDIV) / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_base_group", + "MetricName": "tma_other_ret", + "MetricThreshold": "tma_other_ret > 0.3", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults", - "MetricExpr": "99 * ASSISTS.PAGE_FAULT / SLOTS", - "MetricGroup": "TopdownL5;tma_assists_group", - "MetricName": "tma_page_faults", - "PublicDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults. A Page Fault may apply on first application access to a memory page. Note operating system handling of page faults accounts for the majority of its cost.", + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to page faults.", + "MetricExpr": "tma_nuke * (MACHINE_CLEARS.PAGE_FAULT / MACHINE_CLEARS.SLOW)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", + "MetricName": "tma_page_fault", + "MetricThreshold": "tma_page_fault > 0.02", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists", - "MetricExpr": "30 * ASSISTS.FP / SLOTS", - "MetricGroup": "HPC;TopdownL5;tma_assists_group", - "MetricName": "tma_fp_assists", - "PublicDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called denormals).", + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes.", + "MetricExpr": "TOPDOWN_FE_BOUND.PREDECODE / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_bandwidth_group", + "MetricName": "tma_predecode", + "MetricThreshold": "tma_predecode > 0.05", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists. ", - "MetricExpr": "63 * ASSISTS.SSE_AVX_MIX / SLOTS", - "MetricGroup": "HPC;TopdownL5;tma_assists_group", - "MetricName": "tma_avx_assists", + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).", + "MetricExpr": "TOPDOWN_BE_BOUND.REGISTER / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_register", + "MetricThreshold": "tma_register > 0.1", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", - "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", - "MetricGroup": "TopdownL4;tma_microcode_sequencer_group", - "MetricName": "tma_cisc", - "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources. Sample with: FRONTEND_RETIRED.MS_FLOWS", + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls).", + "MetricExpr": "TOPDOWN_BE_BOUND.REORDER_BUFFER / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_reorder_buffer", + "MetricThreshold": "tma_reorder_buffer > 0.1", "ScaleUnit": "100%", - "Unit": "cpu_core" + "Unit": "cpu_atom" }, { - "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", - "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "Mispredictions", - "Unit": "cpu_core" + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls", + "MetricExpr": "tma_backend_bound", + "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_aux_group", + "MetricName": "tma_resource_bound", + "MetricThreshold": "tma_resource_bound > 0.2", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count.", + "ScaleUnit": "100%", + "Unit": "cpu_atom" }, { - "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks", - "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "Memory_Bandwidth", - "Unit": "cpu_core" + "BriefDescription": "Counts the numer of issue slots that result in retirement slots.", + "MetricExpr": "TOPDOWN_RETIRING.ALL / tma_info_slots", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.75", + "ScaleUnit": "100%", + "Unit": "cpu_atom" }, { - "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)", - "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound))", - "MetricGroup": "Mem;MemoryLat;Offcore", - "MetricName": "Memory_Latency", - "Unit": "cpu_core" + "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to RSV full relative", + "MetricExpr": "tma_mem_scheduler * MEM_SCHEDULER_BLOCK.RSV / MEM_SCHEDULER_BLOCK.ALL", + "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", + "MetricName": "tma_rsv", + "MetricThreshold": "tma_rsv > 0.05", + "ScaleUnit": "100%", + "Unit": "cpu_atom" }, { - "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", - "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))", - "MetricGroup": "Mem;MemoryTLB;Offcore", - "MetricName": "Memory_Data_TLBs", - "Unit": "cpu_core" + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", + "MetricExpr": "TOPDOWN_BE_BOUND.SERIALIZATION / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_serialization", + "MetricThreshold": "tma_serialization > 0.1", + "ScaleUnit": "100%", + "Unit": "cpu_atom" }, { - "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", - "MetricExpr": "100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)", - "MetricGroup": "Ret", - "MetricName": "Branching_Overhead", - "Unit": "cpu_core" + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to SMC.", + "MetricExpr": "tma_nuke * (MACHINE_CLEARS.SMC / MACHINE_CLEARS.SLOW)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", + "MetricName": "tma_smc", + "MetricThreshold": "tma_smc > 0.02", + "ScaleUnit": "100%", + "Unit": "cpu_atom" }, { - "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", - "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", - "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB", - "MetricName": "Big_Code", - "Unit": "cpu_core" + "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to store buffer full", + "MetricExpr": "tma_store_bound", + "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", + "MetricName": "tma_st_buffer", + "MetricThreshold": "tma_st_buffer > 0.05", + "ScaleUnit": "100%", + "Unit": "cpu_atom" }, { - "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", - "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code", - "MetricGroup": "Fed;FetchBW;Frontend", - "MetricName": "Instruction_Fetch_BW", - "Unit": "cpu_core" + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a first level TLB miss.", + "MetricExpr": "LD_HEAD.DTLB_MISS_AT_RET / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_stlb_hit", + "MetricThreshold": "tma_stlb_hit > 0.05", + "ScaleUnit": "100%", + "Unit": "cpu_atom" }, { - "BriefDescription": "Instructions Per Cycle (per Logical Processor)", - "MetricExpr": "INST_RETIRED.ANY / CLKS", - "MetricGroup": "Ret;Summary", - "MetricName": "IPC", - "Unit": "cpu_core" + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a second level TLB miss requiring a page walk.", + "MetricExpr": "LD_HEAD.PGWALK_AT_RET / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_stlb_miss", + "MetricThreshold": "tma_stlb_miss > 0.05", + "ScaleUnit": "100%", + "Unit": "cpu_atom" }, { - "BriefDescription": "Uops Per Instruction", - "MetricExpr": "tma_retiring * SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Ret;Retire", - "MetricName": "UPI", - "Unit": "cpu_core" + "BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full.", + "MetricExpr": "tma_mem_scheduler * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_BLOCK.ALL)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_load_store_bound_group", + "MetricName": "tma_store_bound", + "MetricThreshold": "tma_store_bound > 0.1", + "ScaleUnit": "100%", + "Unit": "cpu_atom" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "tma_retiring * SLOTS / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW", - "MetricName": "UpTB", - "Unit": "cpu_core" + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a store forward block.", + "MetricExpr": "LD_HEAD.ST_ADDR_AT_RET / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_store_fwd", + "MetricThreshold": "tma_store_fwd > 0.05", + "ScaleUnit": "100%", + "Unit": "cpu_atom" }, { - "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / IPC", - "MetricGroup": "Mem;Pipeline", - "MetricName": "CPI", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5_11 + UOPS_DISPATCHED.PORT_6) / (5 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_alu_op_utilization", + "MetricThreshold": "tma_alu_op_utilization > 0.6", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Pipeline", - "MetricName": "CLKS", + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", + "MetricExpr": "100 * cpu_core@ASSISTS.ANY\\,umask\\=0x1B@ / tma_info_slots", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_assists", + "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", - "MetricExpr": "TOPDOWN.SLOTS", - "MetricGroup": "tma_L1_group", - "MetricName": "SLOTS", + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists.", + "MetricExpr": "63 * ASSISTS.SSE_AVX_MIX / tma_info_slots", + "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", + "MetricName": "tma_avx_assists", + "MetricThreshold": "tma_avx_assists > 0.1", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", - "MetricExpr": "(SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)", - "MetricGroup": "SMT;tma_L1_group", - "MetricName": "Slots_Utilization", + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", + "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_backend_bound", + "MetricThreshold": "tma_backend_bound > 0.2", + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "The ratio of Executed- by Issued-Uops", - "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", - "MetricGroup": "Cor;Pipeline", - "MetricName": "Execute_per_Issue", - "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage.", + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", + "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_bad_speculation", + "MetricThreshold": "tma_bad_speculation > 0.15", + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS", - "MetricGroup": "Ret;SMT;tma_L1_group", - "MetricName": "CoreIPC", + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", + "MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_slots", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", + "MetricName": "tma_branch_mispredicts", + "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredicts_resteers", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS", - "MetricGroup": "Flops;Ret", - "MetricName": "FLOPc", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", + "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks + tma_unknown_branches", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_branch_resteers", + "MetricThreshold": "tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", - "MetricExpr": "(FP_ARITH_DISPATCHED.PORT_0 + FP_ARITH_DISPATCHED.PORT_1 + FP_ARITH_DISPATCHED.PORT_5) / (2 * CORE_CLKS)", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "FP_Arith_Utilization", - "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common).", + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", + "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_cisc", + "MetricThreshold": "tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources. Sample with: FRONTEND_RETIRED.MS_FLOWS", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", - "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", - "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", - "MetricName": "ILP", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears", + "MetricExpr": "(1 - tma_branch_mispredicts / tma_bad_speculation) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks", + "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC", + "MetricName": "tma_clears_resteers", + "MetricThreshold": "tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", - "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)", - "MetricGroup": "Cor;SMT", - "MetricName": "Core_Bound_Likely", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(25 * tma_info_average_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 24 * tma_info_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_contested_accesses", + "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", - "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED", - "MetricGroup": "SMT", - "MetricName": "CORE_CLKS", + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", + "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)", + "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", - "MetricGroup": "InsType", - "MetricName": "IpLoad", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "24 * tma_info_average_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_data_sharing", + "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", - "MetricGroup": "InsType", - "MetricName": "IpStore", + "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", + "MetricExpr": "(cpu_core@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu_core@INST_DECODED.DECODERS\\,cmask\\=2@) / tma_info_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_issueD0;tma_mite_group", + "MetricName": "tma_decoder0_alone", + "MetricThreshold": "tma_decoder0_alone > 0.1 & (tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 6 > 0.35))", + "PublicDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder. Related metrics: tma_few_uops_instructions", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Fed;InsType", - "MetricName": "IpBranch", + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", + "MetricExpr": "ARITH.DIV_ACTIVE / tma_info_clks", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_divider", + "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "IpCall", + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_dram_bound", + "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", - "MetricName": "IpTB", + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", + "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / tma_info_core_clks / 2", + "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_dsb", + "MetricThreshold": "tma_dsb > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 6 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "BpTkBranch", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_clks", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_dsb_switches", + "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", - "MetricGroup": "Flops;InsType", - "MetricName": "IpFLOP", + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", + "MetricExpr": "min(7 * cpu_core@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group", + "MetricName": "tma_dtlb_load", + "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store, tma_info_memory_data_tlbs", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))", - "MetricGroup": "Flops;InsType", - "MetricName": "IpArith", - "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW.", + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", + "MetricExpr": "(7 * cpu_core@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group", + "MetricName": "tma_dtlb_store", + "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, tma_info_memory_data_tlbs", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", - "MetricGroup": "Flops;FpScalar;InsType", - "MetricName": "IpArith_Scalar_SP", - "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting.", + "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", + "MetricExpr": "28 * tma_info_average_frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group", + "MetricName": "tma_false_sharing", + "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", - "MetricGroup": "Flops;FpScalar;InsType", - "MetricName": "IpArith_Scalar_DP", - "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting.", + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", + "MetricExpr": "L1D_PEND_MISS.FB_FULL / tma_info_clks", + "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricName": "tma_fb_full", + "MetricThreshold": "tma_fb_full > 0.3", + "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_dram_bw_use, tma_info_memory_bandwidth, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX128", - "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting.", + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", + "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)", + "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", + "MetricName": "tma_fetch_bandwidth", + "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 6 > 0.35", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX256", - "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting.", + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", + "MetricExpr": "topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / tma_info_slots", + "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_latency", + "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / cpu_core@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", - "MetricGroup": "Prefetches", - "MetricName": "IpSWPF", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops", + "MetricExpr": "max(0, tma_heavy_operations - tma_microcode_sequencer)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueD0", + "MetricName": "tma_few_uops_instructions", + "MetricThreshold": "tma_few_uops_instructions > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions. Related metrics: tma_decoder0_alone", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary;tma_L1_group", - "MetricName": "Instructions", + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", + "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", + "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_fp_arith", + "MetricThreshold": "tma_fp_arith > 0.2 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", - "MetricExpr": "tma_retiring * SLOTS / cpu_core@UOPS_RETIRED.SLOTS\\,cmask\\=1@", - "MetricGroup": "Pipeline;Ret", - "MetricName": "Retire", + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists", + "MetricExpr": "30 * ASSISTS.FP / tma_info_slots", + "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", + "MetricName": "tma_fp_assists", + "MetricThreshold": "tma_fp_assists > 0.1", + "PublicDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals).", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions", - "MetricExpr": "INST_RETIRED.REP_ITERATION / cpu_core@UOPS_RETIRED.SLOTS\\,cmask\\=1@", - "MetricGroup": "Pipeline;Ret", - "MetricName": "Strings_Cycles", + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", + "MetricExpr": "cpu_core@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_scalar", + "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / cpu_core@ASSISTS.ANY\\,umask\\=0x1B@", - "MetricGroup": "Pipeline;Ret;Retire", - "MetricName": "IpAssist", + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", + "MetricExpr": "cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@ / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_vector", + "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "", - "MetricExpr": "UOPS_EXECUTED.THREAD / cpu_core@UOPS_EXECUTED.THREAD\\,cmask\\=1@", - "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", - "MetricName": "Execute", + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_128b", + "MetricThreshold": "tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Average number of Uops issued by front-end when it issued something", - "MetricExpr": "UOPS_ISSUED.ANY / cpu_core@UOPS_ISSUED.ANY\\,cmask\\=1@", - "MetricGroup": "Fed;FetchBW", - "MetricName": "Fetch_UpC", + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_256b", + "MetricThreshold": "tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache)", - "MetricExpr": "LSD.UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "Fed;LSD", - "MetricName": "LSD_Coverage", + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", + "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / tma_info_slots", + "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.15", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "DSB;Fed;FetchBW", - "MetricName": "DSB_Coverage", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions", + "MetricExpr": "tma_light_operations * INST_RETIRED.MACRO_FUSED / (tma_retiring * tma_info_slots)", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_fused_instructions", + "MetricThreshold": "tma_fused_instructions > 0.1 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu_core@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@", - "MetricGroup": "DSBmiss", - "MetricName": "DSB_Switch_Cost", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences", + "MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_slots", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_heavy_operations", + "MetricThreshold": "tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. Sample with: UOPS_RETIRED.HEAVY", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.", - "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_lsd + tma_mite))", - "MetricGroup": "DSBmiss;Fed", - "MetricName": "DSB_Misses", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses", + "MetricExpr": "ICACHE_DATA.STALLS / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_icache_misses", + "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", + "ScaleUnit": "100%", "Unit": "cpu_core" }, { - "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", - "MetricGroup": "DSBmiss;Fed", - "MetricName": "IpDSB_Miss_Ret", + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "tma_info_turbo_utilization * TSC / 1e9 / duration_time", + "MetricGroup": "Power;Summary", + "MetricName": "tma_info_average_frequency", "Unit": "cpu_core" }, { - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict", + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB;tma_issueBC", + "MetricName": "tma_info_big_code", + "MetricThreshold": "tma_info_big_code > 20", + "PublicDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses). Related metrics: tma_info_branching_overhead", "Unit": "cpu_core" }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BrMispredicts", - "MetricName": "Branch_Misprediction_Cost", + "BriefDescription": "Branch instructions per taken branch.", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_bptkbranch", "Unit": "cpu_core" }, { - "BriefDescription": "Fraction of branches that are non-taken conditionals", - "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches;CodeGen;PGO", - "MetricName": "Cond_NT", + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_slots / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts;tma_issueBM", + "MetricName": "tma_info_branch_misprediction_cost", + "PublicDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_branch_mispredicts, tma_info_mispredictions, tma_mispredicts_resteers", "Unit": "cpu_core" }, { - "BriefDescription": "Fraction of branches that are taken conditionals", - "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches;CodeGen;PGO", - "MetricName": "Cond_TK", + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "MetricExpr": "100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL)) / tma_info_slots)", + "MetricGroup": "Ret;tma_issueBC", + "MetricName": "tma_info_branching_overhead", + "MetricThreshold": "tma_info_branching_overhead > 10", + "PublicDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls). Related metrics: tma_info_big_code", "Unit": "cpu_core" }, { "BriefDescription": "Fraction of branches that are CALL or RET", "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES", "MetricGroup": "Bad;Branches", - "MetricName": "CallRet", + "MetricName": "tma_info_callret", "Unit": "cpu_core" }, { - "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", - "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches", - "MetricName": "Jump", - "Unit": "cpu_core" - }, - { - "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", - "MetricExpr": "1 - (Cond_NT + Cond_TK + CallRet + Jump)", - "MetricGroup": "Bad;Branches", - "MetricName": "Other_Branches", + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline", + "MetricName": "tma_info_clks", "Unit": "cpu_core" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY", - "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency", + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Fed;MemoryTLB", + "MetricName": "tma_info_code_stlb_mpki", "Unit": "cpu_core" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "Mem;MemoryBW;MemoryBound", - "MetricName": "MLP", + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "tma_info_cond_nt", "Unit": "cpu_core" }, { - "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI", + "BriefDescription": "Fraction of branches that are taken conditionals", + "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "tma_info_cond_tk", "Unit": "cpu_core" }, { - "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI_Load", + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if tma_info_smt_2t_utilization > 0.5 else 0)", + "MetricGroup": "Cor;SMT", + "MetricName": "tma_info_core_bound_likely", + "MetricThreshold": "tma_info_core_bound_likely > 0.5", "Unit": "cpu_core" }, { - "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Backend;CacheMisses;Mem", - "MetricName": "L2MPKI", + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED", + "MetricGroup": "SMT", + "MetricName": "tma_info_core_clks", "Unit": "cpu_core" }, { - "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem;Offcore", - "MetricName": "L2MPKI_All", + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_core_clks", + "MetricGroup": "Ret;SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_coreipc", "Unit": "cpu_core" }, { - "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2MPKI_Load", + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / tma_info_ipc", + "MetricGroup": "Mem;Pipeline", + "MetricName": "tma_info_cpi", "Unit": "cpu_core" }, { - "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", - "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2HPKI_All", + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "HPC;Summary", + "MetricName": "tma_info_cpu_utilization", "Unit": "cpu_core" }, { - "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2HPKI_Load", + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_data_l2_mlp", "Unit": "cpu_core" }, { - "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L3MPKI", + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;tma_issueBW", + "MetricName": "tma_info_dram_bw_use", + "PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_info_memory_bandwidth, tma_mem_bandwidth, tma_sq_full", "Unit": "cpu_core" }, { - "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "FB_HPKI", + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / UOPS_ISSUED.ANY", + "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", + "MetricName": "tma_info_dsb_coverage", + "MetricThreshold": "tma_info_dsb_coverage < 0.7 & tma_info_ipc / 6 > 0.35", + "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_misses, tma_info_iptb, tma_lcp", "Unit": "cpu_core" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (4 * CORE_CLKS)", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "Page_Walks_Utilization", + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck", + "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_lsd + tma_mite))", + "MetricGroup": "DSBmiss;Fed;tma_issueFB", + "MetricName": "tma_info_dsb_misses", + "MetricThreshold": "tma_info_dsb_misses > 10", + "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", "Unit": "cpu_core" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW", + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu_core@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@", + "MetricGroup": "DSBmiss", + "MetricName": "tma_info_dsb_switch_cost", "Unit": "cpu_core" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW", + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-thread", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu_core@UOPS_EXECUTED.THREAD\\,cmask\\=1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "tma_info_execute", "Unit": "cpu_core" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW", + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "tma_info_execute_per_issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage.", "Unit": "cpu_core" }, { - "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW", + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_fb_hpki", "Unit": "cpu_core" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "L1D_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW_1T", + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu_core@UOPS_ISSUED.ANY\\,cmask\\=1@", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_fetch_upc", "Unit": "cpu_core" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "L2_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW_1T", + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / tma_info_core_clks", + "MetricGroup": "Flops;Ret", + "MetricName": "tma_info_flopc", "Unit": "cpu_core" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW_1T", + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(FP_ARITH_DISPATCHED.PORT_0 + FP_ARITH_DISPATCHED.PORT_1 + FP_ARITH_DISPATCHED.PORT_5) / (2 * tma_info_core_clks)", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_fp_arith_utilization", + "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common).", "Unit": "cpu_core" }, { - "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Access_BW", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW_1T", + "BriefDescription": "Giga Floating Point Operations Per Second", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_gflops", + "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine.", "Unit": "cpu_core" }, { - "BriefDescription": "Average CPU Utilization", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", - "MetricGroup": "HPC;Summary", - "MetricName": "CPU_Utilization", + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck", + "MetricExpr": "100 * (tma_fetch_latency * tma_icache_misses / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", + "MetricGroup": "Fed;FetchLat;IcMiss;tma_issueFL", + "MetricName": "tma_info_ic_misses", + "MetricThreshold": "tma_info_ic_misses > 5", + "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck. Related metrics: ", "Unit": "cpu_core" }, { - "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", - "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time", - "MetricGroup": "Power;Summary", - "MetricName": "Average_Frequency", + "BriefDescription": "Average Latency for L1 instruction cache misses", + "MetricExpr": "ICACHE_DATA.STALLS / cpu_core@ICACHE_DATA.STALLS\\,cmask\\=1\\,edge@", + "MetricGroup": "Fed;FetchLat;IcMiss", + "MetricName": "tma_info_icache_miss_latency", "Unit": "cpu_core" }, { - "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs", - "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine.", + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", + "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", + "MetricName": "tma_info_ilp", "Unit": "cpu_core" }, { - "BriefDescription": "Average Frequency Utilization relative nominal frequency", - "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC", - "MetricGroup": "Power", - "MetricName": "Turbo_Utilization", + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_big_code", + "MetricGroup": "Fed;FetchBW;Frontend", + "MetricName": "tma_info_instruction_fetch_bw", + "MetricThreshold": "tma_info_instruction_fetch_bw > 20", "Unit": "cpu_core" }, { - "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", - "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)", - "MetricGroup": "SMT", - "MetricName": "SMT_2T_Utilization", + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;tma_L1_group", + "MetricName": "tma_info_instructions", + "PublicDescription": "Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST", "Unit": "cpu_core" }, { - "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "OS", - "MetricName": "Kernel_Utilization", + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (cpu_core@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_iparith", + "MetricThreshold": "tma_info_iparith < 10", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW.", "Unit": "cpu_core" }, { - "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", - "MetricGroup": "OS", - "MetricName": "Kernel_CPI", + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx128", + "MetricThreshold": "tma_info_iparith_avx128 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting.", "Unit": "cpu_core" }, { - "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", - "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3", - "MetricGroup": "HPC;Mem;MemoryBW;SoC", - "MetricName": "DRAM_BW_Use", + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx256", + "MetricThreshold": "tma_info_iparith_avx256 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting.", "Unit": "cpu_core" }, { - "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests", - "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL", - "MetricGroup": "Mem;SoC", - "MetricName": "MEM_Parallel_Requests", + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_iparith_scalar_dp", + "MetricThreshold": "tma_info_iparith_scalar_dp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting.", "Unit": "cpu_core" }, { - "BriefDescription": "Socket actual clocks when any core is active on that socket", - "MetricExpr": "UNC_CLOCK.SOCKET", - "MetricGroup": "SoC", - "MetricName": "Socket_CLKS", + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_iparith_scalar_sp", + "MetricThreshold": "tma_info_iparith_scalar_sp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting.", "Unit": "cpu_core" }, { - "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", - "MetricGroup": "Branches;OS", - "MetricName": "IpFarBranch", + "BriefDescription": "Instructions per a microcode Assist invocation", + "MetricExpr": "INST_RETIRED.ANY / cpu_core@ASSISTS.ANY\\,umask\\=0x1B@", + "MetricGroup": "Pipeline;Ret;Retire", + "MetricName": "tma_info_ipassist", + "MetricThreshold": "tma_info_ipassist < 100e3", + "PublicDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)", "Unit": "cpu_core" }, { - "BriefDescription": "Uncore frequency per die [GHZ]", - "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9", - "MetricGroup": "SoC", - "MetricName": "UNCORE_FREQ" + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "tma_info_ipbranch", + "MetricThreshold": "tma_info_ipbranch < 8", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to frontend stalls.", - "MetricExpr": "TOPDOWN_FE_BOUND.ALL / SLOTS", - "MetricGroup": "TopdownL1", - "MetricName": "tma_frontend_bound", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_clks", + "MetricGroup": "Ret;Summary", + "MetricName": "tma_info_ipc", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", - "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY / SLOTS", - "MetricGroup": "TopdownL2;tma_frontend_bound_group", - "MetricName": "tma_frontend_latency", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_ipcall", + "MetricThreshold": "tma_info_ipcall < 200", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses.", - "MetricExpr": "TOPDOWN_FE_BOUND.ICACHE / SLOTS", - "MetricGroup": "TopdownL3;tma_frontend_latency_group", - "MetricName": "tma_icache", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "tma_info_ipdsb_miss_ret", + "MetricThreshold": "tma_info_ipdsb_miss_ret < 50", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", - "MetricExpr": "TOPDOWN_FE_BOUND.ITLB / SLOTS", - "MetricGroup": "TopdownL3;tma_frontend_latency_group", - "MetricName": "tma_itlb", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "tma_info_ipfarbranch", + "MetricThreshold": "tma_info_ipfarbranch < 1e6", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend", - "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_DETECT / SLOTS", - "MetricGroup": "TopdownL3;tma_frontend_latency_group", - "MetricName": "tma_branch_detect", - "PublicDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_ipflop", + "MetricThreshold": "tma_info_ipflop < 10", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", - "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_RESTEER / SLOTS", - "MetricGroup": "TopdownL3;tma_frontend_latency_group", - "MetricName": "tma_branch_resteer", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipload", + "MetricThreshold": "tma_info_ipload < 3", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", - "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / SLOTS", - "MetricGroup": "TopdownL2;tma_frontend_bound_group", - "MetricName": "tma_frontend_bandwidth", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Instructions per retired mispredicts for conditional non-taken branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_NTAKEN", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_cond_ntaken", + "MetricThreshold": "tma_info_ipmisp_cond_ntaken < 200", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS).", - "MetricExpr": "TOPDOWN_FE_BOUND.CISC / SLOTS", - "MetricGroup": "TopdownL3;tma_frontend_bandwidth_group", - "MetricName": "tma_cisc", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Instructions per retired mispredicts for conditional taken branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_cond_taken", + "MetricThreshold": "tma_info_ipmisp_cond_taken < 200", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to decode stalls.", - "MetricExpr": "TOPDOWN_FE_BOUND.DECODE / SLOTS", - "MetricGroup": "TopdownL3;tma_frontend_bandwidth_group", - "MetricName": "tma_decode", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "cpu_core@BR_MISP_RETIRED.INDIRECT_CALL\\,umask\\=0x80@ / BR_MISP_RETIRED.INDIRECT", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_indirect", + "MetricThreshold": "tma_info_ipmisp_indirect < 1e3", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes.", - "MetricExpr": "TOPDOWN_FE_BOUND.PREDECODE / SLOTS", - "MetricGroup": "TopdownL3;tma_frontend_bandwidth_group", - "MetricName": "tma_predecode", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Instructions per retired mispredicts for return branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RET", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_ret", + "MetricThreshold": "tma_info_ipmisp_ret < 500", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized.", - "MetricExpr": "TOPDOWN_FE_BOUND.OTHER / SLOTS", - "MetricGroup": "TopdownL3;tma_frontend_bandwidth_group", - "MetricName": "tma_other_fb", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "tma_info_ipmispredict", + "MetricThreshold": "tma_info_ipmispredict < 200", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear", - "MetricExpr": "(SLOTS - (TOPDOWN_FE_BOUND.ALL + TOPDOWN_BE_BOUND.ALL + TOPDOWN_RETIRING.ALL)) / SLOTS", - "MetricGroup": "TopdownL1", - "MetricName": "tma_bad_speculation", - "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipstore", + "MetricThreshold": "tma_info_ipstore < 8", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to branch mispredicts.", - "MetricExpr": "TOPDOWN_BAD_SPECULATION.MISPREDICT / SLOTS", - "MetricGroup": "TopdownL2;tma_bad_speculation_group", - "MetricName": "tma_branch_mispredicts", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / cpu_core@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", + "MetricGroup": "Prefetches", + "MetricName": "tma_info_ipswpf", + "MetricThreshold": "tma_info_ipswpf < 100", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", - "MetricExpr": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS / SLOTS", - "MetricGroup": "TopdownL2;tma_bad_speculation_group", - "MetricName": "tma_machine_clears", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", + "MetricName": "tma_info_iptb", + "MetricThreshold": "tma_info_iptb < 13", + "PublicDescription": "Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_dsb_misses, tma_lcp", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear (slow nuke).", - "MetricExpr": "TOPDOWN_BAD_SPECULATION.NUKE / SLOTS", - "MetricGroup": "TopdownL3;tma_machine_clears_group", - "MetricName": "tma_nuke", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "tma_info_instructions / BACLEARS.ANY", + "MetricGroup": "Fed", + "MetricName": "tma_info_ipunknown_branch", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to SMC. ", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.SMC / MACHINE_CLEARS.SLOW)", - "MetricGroup": "TopdownL4;tma_nuke_group", - "MetricName": "tma_smc", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_jump", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to memory ordering. ", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.SLOW)", - "MetricGroup": "TopdownL4;tma_nuke_group", - "MetricName": "tma_memory_ordering", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_cpi", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to FP assists. ", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.FP_ASSIST / MACHINE_CLEARS.SLOW)", - "MetricGroup": "TopdownL4;tma_nuke_group", - "MetricName": "tma_fp_assist", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_utilization", + "MetricThreshold": "tma_info_kernel_utilization > 0.05", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to memory disambiguation. ", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.DISAMBIGUATION / MACHINE_CLEARS.SLOW)", - "MetricGroup": "TopdownL4;tma_nuke_group", - "MetricName": "tma_disambiguation", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to page faults. ", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.PAGE_FAULT / MACHINE_CLEARS.SLOW)", - "MetricGroup": "TopdownL4;tma_nuke_group", - "MetricName": "tma_page_fault", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "tma_info_l1d_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw_1t", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear classified as a fast nuke due to memory ordering, memory disambiguation and memory renaming.", - "MetricExpr": "TOPDOWN_BAD_SPECULATION.FASTNUKE / SLOTS", - "MetricGroup": "TopdownL3;tma_machine_clears_group", - "MetricName": "tma_fast_nuke", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l1mpki", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls", - "MetricExpr": "TOPDOWN_BE_BOUND.ALL / SLOTS", - "MetricGroup": "TopdownL1", - "MetricName": "tma_backend_bound", - "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. The rest of these subevents count backend stalls, in cycles, due to an outstanding request which is memory bound vs core bound. The subevents are not slot based events and therefore can not be precisely added or subtracted from the Backend_Bound_Aux subevents which are slot based.", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l1mpki_load", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of cycles due to backend bound stalls that are core execution bound and not attributed to outstanding demand load or store stalls. ", - "MetricExpr": "max(0, tma_backend_bound - tma_load_store_bound)", - "MetricGroup": "TopdownL2;tma_backend_bound_group", - "MetricName": "tma_core_bound", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of cycles the core is stalled due to stores or loads. ", - "MetricExpr": "min(tma_backend_bound, LD_HEAD.ANY_AT_RET / CLKS + tma_store_bound)", - "MetricGroup": "TopdownL2;tma_backend_bound_group", - "MetricName": "tma_load_store_bound", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "tma_info_l2_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw_1t", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full.", - "MetricExpr": "tma_st_buffer", - "MetricGroup": "TopdownL3;tma_load_store_bound_group", - "MetricName": "tma_store_bound", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2hpki_all", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a load block.", - "MetricExpr": "LD_HEAD.L1_BOUND_AT_RET / CLKS", - "MetricGroup": "TopdownL3;tma_load_store_bound_group", - "MetricName": "tma_l1_bound", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2hpki_load", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a store forward block.", - "MetricExpr": "LD_HEAD.ST_ADDR_AT_RET / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_store_fwd", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Backend;CacheMisses;Mem", + "MetricName": "tma_info_l2mpki", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a first level TLB miss.", - "MetricExpr": "LD_HEAD.DTLB_MISS_AT_RET / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_stlb_hit", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem;Offcore", + "MetricName": "tma_info_l2mpki_all", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a second level TLB miss requiring a page walk.", - "MetricExpr": "LD_HEAD.PGWALK_AT_RET / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_stlb_miss", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction", + "MetricExpr": "1e3 * FRONTEND_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss", + "MetricName": "tma_info_l2mpki_code", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a number of other load blocks.", - "MetricExpr": "LD_HEAD.OTHER_AT_RET / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_other_l1", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction", + "MetricExpr": "1e3 * L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss", + "MetricName": "tma_info_l2mpki_code_all", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 Cache.", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / CLKS - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD", - "MetricGroup": "TopdownL3;tma_load_store_bound_group", - "MetricName": "tma_l2_bound", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2mpki_load", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / CLKS - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD", - "MetricGroup": "TopdownL3;tma_load_store_bound_group", - "MetricName": "tma_l3_bound", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_l3_cache_access_bw", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / CLKS - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD", - "MetricGroup": "TopdownL3;tma_load_store_bound_group", - "MetricName": "tma_dram_bound", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_l3_cache_access_bw", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_l3_cache_access_bw_1t", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hits in the L2, LLC, DRAM or MMIO (Non-DRAM) but could not be correctly attributed or cycles in which the load miss is waiting on a request buffer.", - "MetricExpr": "max(0, tma_load_store_bound - (tma_store_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound))", - "MetricGroup": "TopdownL3;tma_load_store_bound_group", - "MetricName": "tma_other_load_store", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls", - "MetricExpr": "tma_backend_bound", - "MetricGroup": "TopdownL1", - "MetricName": "tma_backend_bound_aux", - "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that UOPS must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. All of these subevents count backend stalls, in slots, due to a resource limitation. These are not cycle based events and therefore can not be precisely added or subtracted from the Backend_Bound subevents which are cycle based. These subevents are supplementary to Backend_Bound and can be used to analyze results from a resource perspective at allocation. ", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_l3_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw_1t", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls", - "MetricExpr": "tma_backend_bound", - "MetricGroup": "TopdownL2;tma_backend_bound_aux_group", - "MetricName": "tma_resource_bound", - "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. ", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l3mpki", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.", - "MetricExpr": "TOPDOWN_BE_BOUND.MEM_SCHEDULER / SLOTS", - "MetricGroup": "TopdownL3;tma_resource_bound_group", - "MetricName": "tma_mem_scheduler", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore", + "MetricName": "tma_info_load_l2_miss_latency", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to store buffer full", - "MetricExpr": "tma_mem_scheduler * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_BLOCK.ALL)", - "MetricGroup": "TopdownL4;tma_mem_scheduler_group", - "MetricName": "tma_st_buffer", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / cpu_core@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,cmask\\=1@", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_load_l2_mlp", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to load buffer full", - "MetricExpr": "tma_mem_scheduler * MEM_SCHEDULER_BLOCK.LD_BUF / MEM_SCHEDULER_BLOCK.ALL", - "MetricGroup": "TopdownL4;tma_mem_scheduler_group", - "MetricName": "tma_ld_buffer", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Average Latency for L3 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore", + "MetricName": "tma_info_load_l3_miss_latency", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to RSV full relative ", - "MetricExpr": "tma_mem_scheduler * MEM_SCHEDULER_BLOCK.RSV / MEM_SCHEDULER_BLOCK.ALL", - "MetricGroup": "TopdownL4;tma_mem_scheduler_group", - "MetricName": "tma_rsv", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "tma_info_load_miss_real_latency", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.", - "MetricExpr": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER / SLOTS", - "MetricGroup": "TopdownL3;tma_resource_bound_group", - "MetricName": "tma_non_mem_scheduler", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_load_stlb_mpki", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).", - "MetricExpr": "TOPDOWN_BE_BOUND.REGISTER / SLOTS", - "MetricGroup": "TopdownL3;tma_resource_bound_group", - "MetricName": "tma_register", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache)", + "MetricExpr": "LSD.UOPS / UOPS_ISSUED.ANY", + "MetricGroup": "Fed;LSD", + "MetricName": "tma_info_lsd_coverage", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls).", - "MetricExpr": "TOPDOWN_BE_BOUND.REORDER_BUFFER / SLOTS", - "MetricGroup": "TopdownL3;tma_resource_bound_group", - "MetricName": "tma_reorder_buffer", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Average number of parallel data read requests to external memory", + "MetricExpr": "UNC_ARB_DAT_OCCUPANCY.RD / cpu_core@UNC_ARB_DAT_OCCUPANCY.RD\\,cmask\\=1@", + "MetricGroup": "Mem;MemoryBW;SoC", + "MetricName": "tma_info_mem_parallel_reads", + "PublicDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions.", - "MetricExpr": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / SLOTS", - "MetricGroup": "TopdownL3;tma_resource_bound_group", - "MetricName": "tma_alloc_restriction", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds)", + "MetricExpr": "(UNC_ARB_TRK_OCCUPANCY.RD + UNC_ARB_DAT_OCCUPANCY.RD) / UNC_ARB_TRK_REQUESTS.RD", + "MetricGroup": "Mem;MemoryLat;SoC", + "MetricName": "tma_info_mem_read_latency", + "PublicDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", - "MetricExpr": "TOPDOWN_BE_BOUND.SERIALIZATION / SLOTS", - "MetricGroup": "TopdownL3;tma_resource_bound_group", - "MetricName": "tma_serialization", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)", + "MetricExpr": "(UNC_ARB_TRK_OCCUPANCY.ALL + UNC_ARB_DAT_OCCUPANCY.RD) / UNC_ARB_TRK_REQUESTS.ALL", + "MetricGroup": "Mem;SoC", + "MetricName": "tma_info_mem_request_latency", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the numer of issue slots that result in retirement slots. ", - "MetricExpr": "TOPDOWN_RETIRING.ALL / SLOTS", - "MetricGroup": "TopdownL1", - "MetricName": "tma_retiring", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks", + "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))", + "MetricGroup": "Mem;MemoryBW;Offcore;tma_issueBW", + "MetricName": "tma_info_memory_bandwidth", + "MetricThreshold": "tma_info_memory_bandwidth > 20", + "PublicDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_mem_bandwidth, tma_sq_full", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of uops that are not from the microsequencer. ", - "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS) / SLOTS", - "MetricGroup": "TopdownL2;tma_retiring_group", - "MetricName": "tma_base", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", + "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))", + "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", + "MetricName": "tma_info_memory_data_tlbs", + "MetricThreshold": "tma_info_memory_data_tlbs > 20", + "PublicDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of floating point operations per uop with all default weighting.", - "MetricExpr": "UOPS_RETIRED.FPDIV / SLOTS", - "MetricGroup": "TopdownL3;tma_base_group", - "MetricName": "tma_fp_uops", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)", + "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound))", + "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", + "MetricName": "tma_info_memory_latency", + "MetricThreshold": "tma_info_memory_latency > 20", + "PublicDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches). Related metrics: tma_l3_hit_latency, tma_mem_latency", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of uops retired excluding ms and fp div uops.", - "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS - UOPS_RETIRED.FPDIV) / SLOTS", - "MetricGroup": "TopdownL3;tma_base_group", - "MetricName": "tma_other_ret", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", + "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", + "MetricName": "tma_info_mispredictions", + "MetricThreshold": "tma_info_mispredictions > 20", + "PublicDescription": "Total pipeline cost of Branch Misprediction related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_branch_misprediction_cost, tma_mispredicts_resteers", + "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS)", - "MetricExpr": "UOPS_RETIRED.MS / SLOTS", - "MetricGroup": "TopdownL2;tma_retiring_group", - "MetricName": "tma_ms_uops", - "PublicDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.", - "ScaleUnit": "100%", - "Unit": "cpu_atom" + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBW;MemoryBound", + "MetricName": "tma_info_mlp", + "PublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", + "Unit": "cpu_core" }, { - "BriefDescription": "", - "MetricExpr": "CPU_CLK_UNHALTED.CORE", - "MetricName": "CLKS", - "Unit": "cpu_atom" + "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", + "MetricExpr": "1 - (tma_info_cond_nt + tma_info_cond_tk + tma_info_callret + tma_info_jump)", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_other_branches", + "Unit": "cpu_core" }, { - "BriefDescription": "", - "MetricExpr": "CPU_CLK_UNHALTED.CORE_P", - "MetricName": "CLKS_P", - "Unit": "cpu_atom" + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (4 * tma_info_core_clks)", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_page_walks_utilization", + "MetricThreshold": "tma_info_page_walks_utilization > 0.5", + "Unit": "cpu_core" }, { - "BriefDescription": "", - "MetricExpr": "5 * CLKS", - "MetricName": "SLOTS", - "Unit": "cpu_atom" + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "MetricExpr": "tma_retiring * tma_info_slots / cpu_core@UOPS_RETIRED.SLOTS\\,cmask\\=1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "tma_info_retire", + "Unit": "cpu_core" }, { - "BriefDescription": "Instructions Per Cycle", - "MetricExpr": "INST_RETIRED.ANY / CLKS", - "MetricName": "IPC", - "Unit": "cpu_atom" + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "TOPDOWN.SLOTS", + "MetricGroup": "TmaL1;tma_L1_group", + "MetricName": "tma_info_slots", + "Unit": "cpu_core" }, { - "BriefDescription": "Cycles Per Instruction", - "MetricExpr": "CLKS / INST_RETIRED.ANY", - "MetricName": "CPI", - "Unit": "cpu_atom" + "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", + "MetricExpr": "(tma_info_slots / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)", + "MetricGroup": "SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_slots_utilization", + "Unit": "cpu_core" }, { - "BriefDescription": "Uops Per Instruction", - "MetricExpr": "UOPS_RETIRED.ALL / INST_RETIRED.ANY", - "MetricName": "UPI", - "Unit": "cpu_atom" + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)", + "MetricGroup": "SMT", + "MetricName": "tma_info_smt_2t_utilization", + "Unit": "cpu_core" }, { - "BriefDescription": "Percentage of total non-speculative loads with a store forward or unknown store address block", - "MetricExpr": "100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricName": "Store_Fwd_Blocks", - "Unit": "cpu_atom" + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "UNC_CLOCK.SOCKET", + "MetricGroup": "SoC", + "MetricName": "tma_info_socket_clks", + "Unit": "cpu_core" }, { - "BriefDescription": "Percentage of total non-speculative loads with a address aliasing block", - "MetricExpr": "100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricName": "Address_Alias_Blocks", - "Unit": "cpu_atom" + "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_store_stlb_mpki", + "Unit": "cpu_core" }, { - "BriefDescription": "Percentage of total non-speculative loads that are splits", - "MetricExpr": "100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricName": "Load_Splits", - "Unit": "cpu_atom" + "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions", + "MetricExpr": "INST_RETIRED.REP_ITERATION / cpu_core@UOPS_RETIRED.SLOTS\\,cmask\\=1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "tma_info_strings_cycles", + "MetricThreshold": "tma_info_strings_cycles > 0.1", + "Unit": "cpu_core" }, { - "BriefDescription": "Instructions per Branch (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricName": "IpBranch", - "Unit": "cpu_atom" + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "tma_info_clks / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power", + "MetricName": "tma_info_turbo_utilization", + "Unit": "cpu_core" }, { - "BriefDescription": "Instruction per (near) call (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.CALL", - "MetricName": "IpCall", - "Unit": "cpu_atom" + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "tma_retiring * tma_info_slots / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire", + "MetricName": "tma_info_uoppi", + "MetricThreshold": "tma_info_uoppi > 1.05", + "Unit": "cpu_core" }, { - "BriefDescription": "Instructions per Load", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricName": "IpLoad", - "Unit": "cpu_atom" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "tma_retiring * tma_info_slots / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "tma_info_uptb", + "MetricThreshold": "tma_info_uptb < 9", + "Unit": "cpu_core" }, { - "BriefDescription": "Instructions per Store", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", - "MetricName": "IpStore", - "Unit": "cpu_atom" + "BriefDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired)", + "MetricExpr": "tma_int_vector_128b + tma_int_vector_256b + tma_shuffles", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_int_operations", + "MetricThreshold": "tma_int_operations > 0.1 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired). Vector/Matrix Int operations and shuffles are counted. Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain.", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricName": "IpMispredict", - "Unit": "cpu_atom" + "BriefDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired", + "MetricExpr": "(INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128) / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group;tma_issue2P", + "MetricName": "tma_int_vector_128b", + "MetricThreshold": "tma_int_vector_128b > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6)", + "PublicDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "Instructions per Far Branch", - "MetricExpr": "INST_RETIRED.ANY / (BR_INST_RETIRED.FAR_BRANCH / 2)", - "MetricName": "IpFarBranch", - "Unit": "cpu_atom" + "BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired", + "MetricExpr": "(INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256) / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group;tma_issue2P", + "MetricName": "tma_int_vector_256b", + "MetricThreshold": "tma_int_vector_256b > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6)", + "PublicDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "Ratio of all branches which mispredict", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.ALL_BRANCHES", - "MetricName": "Branch_Mispredict_Ratio", - "Unit": "cpu_atom" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", + "MetricExpr": "ICACHE_TAG.STALLS / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "Ratio between Mispredicted branches and unknown branches", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BACLEARS.ANY", - "MetricName": "Branch_Mispredict_to_Unknown_Branch_Ratio", - "Unit": "cpu_atom" + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", + "MetricExpr": "max((EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS) / tma_info_clks, 0)", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group", + "MetricName": "tma_l1_bound", + "MetricThreshold": "tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "Percentage of all uops which are ucode ops", - "MetricExpr": "100 * UOPS_RETIRED.MS / UOPS_RETIRED.ALL", - "MetricName": "Microcode_Uop_Ratio", - "Unit": "cpu_atom" + "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS) / tma_info_clks", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l2_bound", + "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "Percentage of all uops which are FPDiv uops", - "MetricExpr": "100 * UOPS_RETIRED.FPDIV / UOPS_RETIRED.ALL", - "MetricName": "FPDiv_Uop_Ratio", - "Unit": "cpu_atom" + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", + "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS) / tma_info_clks", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l3_bound", + "MetricThreshold": "tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "Percentage of all uops which are IDiv uops", - "MetricExpr": "100 * UOPS_RETIRED.IDIV / UOPS_RETIRED.ALL", - "MetricName": "IDiv_Uop_Ratio", - "Unit": "cpu_atom" + "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", + "MetricExpr": "9 * tma_info_average_frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group", + "MetricName": "tma_l3_hit_latency", + "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_memory_latency, tma_mem_latency", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "Percentage of all uops which are x87 uops", - "MetricExpr": "100 * UOPS_RETIRED.X87 / UOPS_RETIRED.ALL", - "MetricName": "X87_Uop_Ratio", - "Unit": "cpu_atom" + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", + "MetricExpr": "DECODE.LCP / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_lcp", + "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "Average Frequency Utilization relative nominal frequency", - "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC", - "MetricName": "Turbo_Utilization", - "Unit": "cpu_atom" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", + "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_light_operations", + "MetricThreshold": "tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "Fraction of cycles spent in Kernel mode", - "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE@k / CPU_CLK_UNHALTED.CORE", - "MetricName": "Kernel_Utilization", - "Unit": "cpu_atom" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", + "MetricExpr": "UOPS_DISPATCHED.PORT_2_3_10 / (3 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_load_op_utilization", + "MetricThreshold": "tma_load_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3_10", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "Average CPU Utilization", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", - "MetricName": "CPU_Utilization", - "Unit": "cpu_atom" + "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", + "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", + "MetricName": "tma_load_stlb_hit", + "MetricThreshold": "tma_load_stlb_hit > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "Cycle cost per L2 hit", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_LOAD_UOPS_RETIRED.L2_HIT", - "MetricName": "Cycles_per_Demand_Load_L2_Hit", - "Unit": "cpu_atom" + "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", + "MetricName": "tma_load_stlb_miss", + "MetricThreshold": "tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "Cycle cost per LLC hit", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_LOAD_UOPS_RETIRED.L3_HIT", - "MetricName": "Cycles_per_Demand_Load_L3_Hit", - "Unit": "cpu_atom" + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / tma_info_clks", + "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group", + "MetricName": "tma_lock_latency", + "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "Cycle cost per DRAM hit", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_LOAD_UOPS_RETIRED.DRAM_HIT", - "MetricName": "Cycles_per_Demand_Load_DRAM_Hit", - "Unit": "cpu_atom" + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit", + "MetricExpr": "(LSD.CYCLES_ACTIVE - LSD.CYCLES_OK) / tma_info_core_clks / 2", + "MetricGroup": "FetchBW;LSD;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_lsd", + "MetricThreshold": "tma_lsd > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 6 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit. LSD typically does well sustaining Uop supply. However; in some rare cases; optimal uop-delivery could not be reached for small loops whose size (in terms of number of uops) does not suit well the LSD structure.", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "Percent of instruction miss cost that hit in the L2", - "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / MEM_BOUND_STALLS.IFETCH", - "MetricName": "Inst_Miss_Cost_L2Hit_Percent", - "Unit": "cpu_atom" + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", + "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)", + "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "Percent of instruction miss cost that hit in the L3", - "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / MEM_BOUND_STALLS.IFETCH", - "MetricName": "Inst_Miss_Cost_L3Hit_Percent", - "Unit": "cpu_atom" + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu_core@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW", + "MetricName": "tma_mem_bandwidth", + "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_info_memory_bandwidth, tma_sq_full", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "Percent of instruction miss cost that hit in DRAM", - "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / MEM_BOUND_STALLS.IFETCH", - "MetricName": "Inst_Miss_Cost_DRAMHit_Percent", - "Unit": "cpu_atom" + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_clks - tma_mem_bandwidth", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat", + "MetricName": "tma_mem_latency", + "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_info_memory_latency, tma_l3_hit_latency", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "load ops retired per 1000 instruction", - "MetricExpr": "1e3 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY", - "MetricName": "MemLoadPKI", - "Unit": "cpu_atom" + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", + "MetricExpr": "topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_slots", + "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_memory_bound", + "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "C1 residency percent per core", - "MetricExpr": "cstate_core@c1\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C1_Core_Residency", - "ScaleUnit": "100%" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions.", + "MetricExpr": "13 * MISC2_RETIRED.LFENCE / tma_info_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group", + "MetricName": "tma_memory_fence", + "MetricThreshold": "tma_memory_fence > 0.05 & (tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))))", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "C6 residency percent per core", - "MetricExpr": "cstate_core@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Core_Residency", - "ScaleUnit": "100%" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", + "MetricExpr": "tma_light_operations * MEM_UOP_RETIRED.ANY / (tma_retiring * tma_info_slots)", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_memory_operations", + "MetricThreshold": "tma_memory_operations > 0.1 & tma_light_operations > 0.6", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "C7 residency percent per core", - "MetricExpr": "cstate_core@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Core_Residency", - "ScaleUnit": "100%" + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", + "MetricExpr": "UOPS_RETIRED.MS / tma_info_slots", + "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS", + "MetricName": "tma_microcode_sequencer", + "MetricThreshold": "tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "C2 residency percent per package", - "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C2_Pkg_Residency", - "ScaleUnit": "100%" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage", + "MetricExpr": "tma_branch_mispredicts / tma_bad_speculation * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks", + "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM", + "MetricName": "tma_mispredicts_resteers", + "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_branch_misprediction_cost, tma_info_mispredictions", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "C3 residency percent per package", - "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Pkg_Residency", - "ScaleUnit": "100%" + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", + "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / tma_info_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_mite", + "MetricThreshold": "tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 6 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "C6 residency percent per package", - "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Pkg_Residency", - "ScaleUnit": "100%" + "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued", + "MetricExpr": "160 * ASSISTS.SSE_AVX_MIX / tma_info_clks", + "MetricGroup": "TopdownL5;tma_L5_group;tma_issueMV;tma_ports_utilized_0_group", + "MetricName": "tma_mixing_vectors", + "MetricThreshold": "tma_mixing_vectors > 0.05", + "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic. Related metrics: tma_ms_switches", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "C7 residency percent per package", - "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Pkg_Residency", - "ScaleUnit": "100%" + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", + "MetricExpr": "3 * cpu_core@UOPS_RETIRED.MS\\,cmask\\=1\\,edge@ / (tma_retiring * tma_info_slots / UOPS_ISSUED.ANY) / tma_info_clks", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", + "MetricName": "tma_ms_switches", + "MetricThreshold": "tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: FRONTEND_RETIRED.MS_FLOWS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "C8 residency percent per package", - "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C8_Pkg_Residency", - "ScaleUnit": "100%" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused", + "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED) / (tma_retiring * tma_info_slots)", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_non_fused_branches", + "MetricThreshold": "tma_non_fused_branches > 0.1 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "C9 residency percent per package", - "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C9_Pkg_Residency", - "ScaleUnit": "100%" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions", + "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (tma_retiring * tma_info_slots)", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_nop_instructions", + "MetricThreshold": "tma_nop_instructions > 0.1 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP", + "ScaleUnit": "100%", + "Unit": "cpu_core" }, { - "BriefDescription": "C10 residency percent per package", - "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C10_Pkg_Residency", - "ScaleUnit": "100%" + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes", + "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_int_operations + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions))", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_other_light_ops", + "MetricThreshold": "tma_other_light_ops > 0.3 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults", + "MetricExpr": "99 * ASSISTS.PAGE_FAULT / tma_info_slots", + "MetricGroup": "TopdownL5;tma_L5_group;tma_assists_group", + "MetricName": "tma_page_faults", + "MetricThreshold": "tma_page_faults > 0.05", + "PublicDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults. A Page Fault may apply on first application access to a memory page. Note operating system handling of page faults accounts for the majority of its cost.", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", + "MetricExpr": "UOPS_DISPATCHED.PORT_0 / tma_info_core_clks", + "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_0", + "MetricThreshold": "tma_port_0 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", + "MetricExpr": "UOPS_DISPATCHED.PORT_1 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_1", + "MetricThreshold": "tma_port_1 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", + "MetricExpr": "UOPS_DISPATCHED.PORT_6 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_6", + "MetricThreshold": "tma_port_6 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", + "MetricExpr": "((cpu_core@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS) + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@)) / tma_info_clks if ARITH.DIV_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu_core@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@) / tma_info_clks)", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_ports_utilization", + "MetricThreshold": "tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "cpu_core@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ / tma_info_clks + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS) / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_0", + "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "EXE_ACTIVITY.1_PORTS_UTIL / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_1", + "MetricThreshold": "tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL. Related metrics: tma_l1_bound", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "EXE_ACTIVITY.2_PORTS_UTIL / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_2", + "MetricThreshold": "tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_3m", + "MetricThreshold": "tma_ports_utilized_3m > 0.7 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations", + "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL5;tma_L5_group;tma_issueSO;tma_ports_utilized_0_group", + "MetricName": "tma_serializing_operation", + "MetricThreshold": "tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD. Related metrics: tma_ms_switches", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents Shuffle (cross \"vector lane\" data transfers) uops fraction the CPU has retired.", + "MetricExpr": "INT_VEC_RETIRED.SHUFFLES / (tma_retiring * tma_info_slots)", + "MetricGroup": "HPC;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group", + "MetricName": "tma_shuffles", + "MetricThreshold": "tma_shuffles > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6)", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions", + "MetricExpr": "CPU_CLK_UNHALTED.PAUSE / tma_info_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group", + "MetricName": "tma_slow_pause", + "MetricThreshold": "tma_slow_pause > 0.05 & (tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: CPU_CLK_UNHALTED.PAUSE_INST", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", + "MetricExpr": "tma_info_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_split_loads", + "MetricThreshold": "tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents rate of split store accesses", + "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / tma_info_core_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group", + "MetricName": "tma_split_stores", + "MetricThreshold": "tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", + "MetricExpr": "(XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS) / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group", + "MetricName": "tma_sq_full", + "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_info_memory_bandwidth, tma_mem_bandwidth", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", + "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_store_bound", + "MetricThreshold": "tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", + "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_store_fwd_blk", + "MetricThreshold": "tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", + "MetricExpr": "(MEM_STORE_RETIRED.L2_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_clks", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group", + "MetricName": "tma_store_latency", + "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_store_op_utilization", + "MetricThreshold": "tma_store_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations. Sample with: UOPS_DISPATCHED.PORT_7_8", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", + "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", + "MetricName": "tma_store_stlb_hit", + "MetricThreshold": "tma_store_stlb_hit > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", + "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / tma_info_core_clks", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", + "MetricName": "tma_store_stlb_miss", + "MetricThreshold": "tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores", + "MetricExpr": "9 * OCR.STREAMING_WR.ANY_RESPONSE / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueSmSt;tma_store_bound_group", + "MetricName": "tma_streaming_stores", + "MetricThreshold": "tma_streaming_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck. Sample with: OCR.STREAMING_WR.ANY_RESPONSE. Related metrics: tma_fb_full", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", + "MetricExpr": "INT_MISC.UNKNOWN_BRANCH_CYCLES / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", + "MetricName": "tma_unknown_branches", + "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit). Sample with: FRONTEND_RETIRED.UNKNOWN_BRANCH", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This metric serves as an approximation of legacy x87 usage", + "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD", + "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_x87_use", + "MetricThreshold": "tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", + "ScaleUnit": "100%", + "Unit": "cpu_core" } ] diff --git a/tools/perf/pmu-events/arch/x86/alderlake/cache.json b/tools/perf/pmu-events/arch/x86/alderlake/cache.json index adc9887b8ae0..51770416bcc2 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/cache.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/cache.json @@ -92,19 +92,19 @@ "Unit": "cpu_core" }, { - "BriefDescription": "All accesses to L2 cache[This event is alias to L2_RQSTS.REFERENCES]", + "BriefDescription": "All accesses to L2 cache [This event is alias to L2_RQSTS.REFERENCES]", "EventCode": "0x24", "EventName": "L2_REQUEST.ALL", - "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses.[This event is alias to L2_RQSTS.REFERENCES]", + "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES]", "SampleAfterValue": "200003", "UMask": "0xff", "Unit": "cpu_core" }, { - "BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_RQSTS.MISS]", + "BriefDescription": "Read requests with true-miss in L2 cache. [This event is alias to L2_RQSTS.MISS]", "EventCode": "0x24", "EventName": "L2_REQUEST.MISS", - "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses.[This event is alias to L2_RQSTS.MISS]", + "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS]", "SampleAfterValue": "200003", "UMask": "0x3f", "Unit": "cpu_core" @@ -198,19 +198,19 @@ "Unit": "cpu_core" }, { - "BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_REQUEST.MISS]", + "BriefDescription": "Read requests with true-miss in L2 cache. [This event is alias to L2_REQUEST.MISS]", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", - "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses.[This event is alias to L2_REQUEST.MISS]", + "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS]", "SampleAfterValue": "200003", "UMask": "0x3f", "Unit": "cpu_core" }, { - "BriefDescription": "All accesses to L2 cache[This event is alias to L2_REQUEST.ALL]", + "BriefDescription": "All accesses to L2 cache [This event is alias to L2_REQUEST.ALL]", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", - "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses.[This event is alias to L2_REQUEST.ALL]", + "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.ALL]", "SampleAfterValue": "200003", "UMask": "0xff", "Unit": "cpu_core" @@ -895,7 +895,7 @@ "Unit": "cpu_atom" }, { - "BriefDescription": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another cores caches which forwarded the unmodified data to the requesting core.", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -980,6 +980,15 @@ "UMask": "0x8", "Unit": "cpu_core" }, + { + "BriefDescription": "Cycles where at least 1 outstanding demand data read request is pending.", + "CounterMask": "1", + "EventCode": "0x20", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, { "BriefDescription": "For every cycle where the core is waiting on at least 1 outstanding Demand RFO request, increments by 1.", "CounterMask": "1", @@ -999,6 +1008,15 @@ "UMask": "0x8", "Unit": "cpu_core" }, + { + "BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.", + "EventCode": "0x20", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, { "BriefDescription": "Number of PREFETCHNTA instructions executed.", "EventCode": "0x40", diff --git a/tools/perf/pmu-events/arch/x86/alderlake/floating-point.json b/tools/perf/pmu-events/arch/x86/alderlake/floating-point.json index 3eb7cab9b431..c8ba96c4a7f8 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/floating-point.json @@ -85,6 +85,24 @@ "UMask": "0x20", "Unit": "cpu_core" }, + { + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x18", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "1000003", + "UMask": "0x3", + "Unit": "cpu_core" + }, { "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "EventCode": "0xc7", @@ -103,6 +121,15 @@ "UMask": "0x2", "Unit": "cpu_core" }, + { + "BriefDescription": "Number of any Vector retired FP arithmetic instructions", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.VECTOR", + "PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "1000003", + "UMask": "0xfc", + "Unit": "cpu_core" + }, { "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", "EventCode": "0xc3", diff --git a/tools/perf/pmu-events/arch/x86/alderlake/frontend.json b/tools/perf/pmu-events/arch/x86/alderlake/frontend.json index 250cd128b674..81349100fe32 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/frontend.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/frontend.json @@ -8,6 +8,15 @@ "UMask": "0x1", "Unit": "cpu_atom" }, + { + "BriefDescription": "Clears due to Unknown Branches.", + "EventCode": "0x60", + "EventName": "BACLEARS.ANY", + "PublicDescription": "Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + }, { "BriefDescription": "Stalls caused by changing prefix length of the instruction.", "EventCode": "0x87", diff --git a/tools/perf/pmu-events/arch/x86/alderlake/memory.json b/tools/perf/pmu-events/arch/x86/alderlake/memory.json index 7595eb4ab46f..37f3d062a788 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/memory.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/memory.json @@ -278,10 +278,9 @@ "Unit": "cpu_atom" }, { - "BriefDescription": "Demand Data Read requests who miss L3 cache", + "BriefDescription": "Counts demand data read requests that miss the L3 cache.", "EventCode": "0x21", "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", - "PublicDescription": "Demand Data Read requests who miss L3 cache.", "SampleAfterValue": "100003", "UMask": "0x10", "Unit": "cpu_core" diff --git a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json b/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json index f46fa7ba168a..2dba3a115f97 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json @@ -793,13 +793,25 @@ "Unit": "cpu_core" }, { - "BriefDescription": "INST_RETIRED.REP_ITERATION", + "BriefDescription": "Iterations of Repeat string retired instructions.", "EventCode": "0xc0", "EventName": "INST_RETIRED.REP_ITERATION", + "PublicDescription": "Number of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, and doubleword version and string instructions can be repeated using a repetition prefix, REP, that allows their architectural execution to be repeated a number of times as specified by the RCX register. Note the number of iterations is implementation-dependent.", "SampleAfterValue": "2000003", "UMask": "0x8", "Unit": "cpu_core" }, + { + "BriefDescription": "Clears speculative count", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xad", + "EventName": "INT_MISC.CLEARS_COUNT", + "PublicDescription": "Counts the number of speculative clears due to any type of branch misprediction or machine clears", + "SampleAfterValue": "500009", + "UMask": "0x1", + "Unit": "cpu_core" + }, { "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", "EventCode": "0xad", diff --git a/tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json b/tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json index bc5fb6b76065..5f3b4c6e2e39 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json @@ -24,7 +24,7 @@ "Unit": "ARB" }, { - "BriefDescription": "Number of coherent read requests sent to memory controller that were issued by any core.", + "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_REQ_TRK_REQUEST.DRD", "EventCode": "0x81", "EventName": "UNC_ARB_DAT_REQUESTS.RD", "PerPkg": "1", @@ -40,7 +40,15 @@ "Unit": "ARB" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_REQUESTS.RD", + "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_OCCUPANCY.RD]", + "EventCode": "0x80", + "EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_REQUESTS.RD]", "EventCode": "0x81", "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD", "PerPkg": "1", @@ -55,6 +63,14 @@ "UMask": "0x1", "Unit": "ARB" }, + { + "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_OCCUPANCY.DRD]", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.RD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, { "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.", "EventCode": "0x81", @@ -63,6 +79,14 @@ "UMask": "0x1", "Unit": "ARB" }, + { + "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_REQUEST.DRD]", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.RD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, { "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.", "EventCode": "0xff", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 5facdac6fe8e..4bcccab07ea9 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -1,5 +1,5 @@ Family-model,Version,Filename,EventType -GenuineIntel-6-(97|9A|B7|BA|BF),v1.16,alderlake,core +GenuineIntel-6-(97|9A|B7|BA|BF),v1.18,alderlake,core GenuineIntel-6-BE,v1.16,alderlaken,core GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core GenuineIntel-6-(3D|47),v26,broadwell,core -- cgit v1.2.3-58-ga151 From fa6073700b6e44fec8c4c9aa23497d3fe1f9a869 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:08 -0800 Subject: perf vendor events intel: Refresh alderlake-n metrics Update the alderlake-n events from 1.16 to 1.18 (no change) and metrics. Generation was done using https://github.com/intel/perfmon. Notable changes are TMA metrics are updated to version 4.5, TMA info metrics are renamed from their node name to be lower case and prefixed by tma_info_, MetricThreshold expressions are added and the smi_cost metric group is added replicating existing hard coded metrics in stat-shadow. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-12-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/x86/alderlaken/adln-metrics.json | 811 ++++++++++++--------- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 2 files changed, 454 insertions(+), 359 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json b/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json index 9ab1d5bcf4a2..5078c468480f 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json @@ -1,583 +1,678 @@ [ { - "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to frontend stalls.", - "MetricExpr": "TOPDOWN_FE_BOUND.ALL / SLOTS", - "MetricGroup": "TopdownL1", - "MetricName": "tma_frontend_bound", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", - "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY / SLOTS", - "MetricGroup": "TopdownL2;tma_frontend_bound_group", - "MetricName": "tma_frontend_latency", + "BriefDescription": "C10 residency percent per package", + "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C10_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses.", - "MetricExpr": "TOPDOWN_FE_BOUND.ICACHE / SLOTS", - "MetricGroup": "TopdownL3;tma_frontend_latency_group", - "MetricName": "tma_icache", + "BriefDescription": "C1 residency percent per core", + "MetricExpr": "cstate_core@c1\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C1_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", - "MetricExpr": "TOPDOWN_FE_BOUND.ITLB / SLOTS", - "MetricGroup": "TopdownL3;tma_frontend_latency_group", - "MetricName": "tma_itlb", + "BriefDescription": "C2 residency percent per package", + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C2_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend", - "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_DETECT / SLOTS", - "MetricGroup": "TopdownL3;tma_frontend_latency_group", - "MetricName": "tma_branch_detect", - "PublicDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", + "BriefDescription": "C3 residency percent per package", + "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", - "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_RESTEER / SLOTS", - "MetricGroup": "TopdownL3;tma_frontend_latency_group", - "MetricName": "tma_branch_resteer", + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", - "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / SLOTS", - "MetricGroup": "TopdownL2;tma_frontend_bound_group", - "MetricName": "tma_frontend_bandwidth", + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS).", - "MetricExpr": "TOPDOWN_FE_BOUND.CISC / SLOTS", - "MetricGroup": "TopdownL3;tma_frontend_bandwidth_group", - "MetricName": "tma_cisc", + "BriefDescription": "C7 residency percent per core", + "MetricExpr": "cstate_core@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to decode stalls.", - "MetricExpr": "TOPDOWN_FE_BOUND.DECODE / SLOTS", - "MetricGroup": "TopdownL3;tma_frontend_bandwidth_group", - "MetricName": "tma_decode", + "BriefDescription": "C7 residency percent per package", + "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes.", - "MetricExpr": "TOPDOWN_FE_BOUND.PREDECODE / SLOTS", - "MetricGroup": "TopdownL3;tma_frontend_bandwidth_group", - "MetricName": "tma_predecode", + "BriefDescription": "C8 residency percent per package", + "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C8_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized.", - "MetricExpr": "TOPDOWN_FE_BOUND.OTHER / SLOTS", - "MetricGroup": "TopdownL3;tma_frontend_bandwidth_group", - "MetricName": "tma_other_fb", + "BriefDescription": "C9 residency percent per package", + "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C9_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear", - "MetricExpr": "(SLOTS - (TOPDOWN_FE_BOUND.ALL + TOPDOWN_BE_BOUND.ALL + TOPDOWN_RETIRING.ALL)) / SLOTS", - "MetricGroup": "TopdownL1", - "MetricName": "tma_bad_speculation", - "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", + "BriefDescription": "Percentage of cycles spent in System Management Interrupts.", + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", + "MetricGroup": "smi", + "MetricName": "smi_cycles", + "MetricThreshold": "smi_cycles > 0.1", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to branch mispredicts.", - "MetricExpr": "TOPDOWN_BAD_SPECULATION.MISPREDICT / SLOTS", - "MetricGroup": "TopdownL2;tma_bad_speculation_group", - "MetricName": "tma_branch_mispredicts", - "ScaleUnit": "100%" + "BriefDescription": "Number of SMI interrupts.", + "MetricExpr": "msr@smi@", + "MetricGroup": "smi", + "MetricName": "smi_num", + "ScaleUnit": "1SMI#" }, { - "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", - "MetricExpr": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS / SLOTS", - "MetricGroup": "TopdownL2;tma_bad_speculation_group", - "MetricName": "tma_machine_clears", + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions.", + "MetricExpr": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_alloc_restriction", + "MetricThreshold": "tma_alloc_restriction > 0.1", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear (slow nuke).", - "MetricExpr": "TOPDOWN_BAD_SPECULATION.NUKE / SLOTS", - "MetricGroup": "TopdownL3;tma_machine_clears_group", - "MetricName": "tma_nuke", + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls", + "MetricExpr": "TOPDOWN_BE_BOUND.ALL / tma_info_slots", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_backend_bound", + "MetricThreshold": "tma_backend_bound > 0.1", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. The rest of these subevents count backend stalls, in cycles, due to an outstanding request which is memory bound vs core bound. The subevents are not slot based events and therefore can not be precisely added or subtracted from the Backend_Bound_Aux subevents which are slot based.", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to SMC. ", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.SMC / MACHINE_CLEARS.SLOW)", - "MetricGroup": "TopdownL4;tma_nuke_group", - "MetricName": "tma_smc", + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls", + "MetricExpr": "tma_backend_bound", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_backend_bound_aux", + "MetricThreshold": "tma_backend_bound_aux > 0.2", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that UOPS must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. All of these subevents count backend stalls, in slots, due to a resource limitation. These are not cycle based events and therefore can not be precisely added or subtracted from the Backend_Bound subevents which are cycle based. These subevents are supplementary to Backend_Bound and can be used to analyze results from a resource perspective at allocation.", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to memory ordering. ", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.SLOW)", - "MetricGroup": "TopdownL4;tma_nuke_group", - "MetricName": "tma_memory_ordering", + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear", + "MetricExpr": "(tma_info_slots - (TOPDOWN_FE_BOUND.ALL + TOPDOWN_BE_BOUND.ALL + TOPDOWN_RETIRING.ALL)) / tma_info_slots", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_bad_speculation", + "MetricThreshold": "tma_bad_speculation > 0.15", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to FP assists. ", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.FP_ASSIST / MACHINE_CLEARS.SLOW)", - "MetricGroup": "TopdownL4;tma_nuke_group", - "MetricName": "tma_fp_assist", + "BriefDescription": "Counts the number of uops that are not from the microsequencer.", + "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS) / tma_info_slots", + "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_base", + "MetricThreshold": "tma_base > 0.6", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to memory disambiguation. ", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.DISAMBIGUATION / MACHINE_CLEARS.SLOW)", - "MetricGroup": "TopdownL4;tma_nuke_group", - "MetricName": "tma_disambiguation", + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend", + "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_DETECT / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_latency_group", + "MetricName": "tma_branch_detect", + "MetricThreshold": "tma_branch_detect > 0.05", + "PublicDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to page faults. ", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.PAGE_FAULT / MACHINE_CLEARS.SLOW)", - "MetricGroup": "TopdownL4;tma_nuke_group", - "MetricName": "tma_page_fault", + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to branch mispredicts.", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.MISPREDICT / tma_info_slots", + "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", + "MetricName": "tma_branch_mispredicts", + "MetricThreshold": "tma_branch_mispredicts > 0.05", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear classified as a fast nuke due to memory ordering, memory disambiguation and memory renaming.", - "MetricExpr": "TOPDOWN_BAD_SPECULATION.FASTNUKE / SLOTS", - "MetricGroup": "TopdownL3;tma_machine_clears_group", - "MetricName": "tma_fast_nuke", + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", + "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_RESTEER / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_latency_group", + "MetricName": "tma_branch_resteer", + "MetricThreshold": "tma_branch_resteer > 0.05", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls", - "MetricExpr": "TOPDOWN_BE_BOUND.ALL / SLOTS", - "MetricGroup": "TopdownL1", - "MetricName": "tma_backend_bound", - "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. The rest of these subevents count backend stalls, in cycles, due to an outstanding request which is memory bound vs core bound. The subevents are not slot based events and therefore can not be precisely added or subtracted from the Backend_Bound_Aux subevents which are slot based.", + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS).", + "MetricExpr": "TOPDOWN_FE_BOUND.CISC / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_bandwidth_group", + "MetricName": "tma_cisc", + "MetricThreshold": "tma_cisc > 0.05", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of cycles due to backend bound stalls that are core execution bound and not attributed to outstanding demand load or store stalls. ", + "BriefDescription": "Counts the number of cycles due to backend bound stalls that are core execution bound and not attributed to outstanding demand load or store stalls.", "MetricExpr": "max(0, tma_backend_bound - tma_load_store_bound)", - "MetricGroup": "TopdownL2;tma_backend_bound_group", + "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_core_bound", + "MetricThreshold": "tma_core_bound > 0.1", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of cycles the core is stalled due to stores or loads. ", - "MetricExpr": "min(tma_backend_bound, LD_HEAD.ANY_AT_RET / CLKS + tma_store_bound)", - "MetricGroup": "TopdownL2;tma_backend_bound_group", - "MetricName": "tma_load_store_bound", + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to decode stalls.", + "MetricExpr": "TOPDOWN_FE_BOUND.DECODE / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_bandwidth_group", + "MetricName": "tma_decode", + "MetricThreshold": "tma_decode > 0.05", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full.", - "MetricExpr": "tma_st_buffer", - "MetricGroup": "TopdownL3;tma_load_store_bound_group", - "MetricName": "tma_store_bound", + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to memory disambiguation.", + "MetricExpr": "tma_nuke * (MACHINE_CLEARS.DISAMBIGUATION / MACHINE_CLEARS.SLOW)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", + "MetricName": "tma_disambiguation", + "MetricThreshold": "tma_disambiguation > 0.02", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a load block.", - "MetricExpr": "LD_HEAD.L1_BOUND_AT_RET / CLKS", - "MetricGroup": "TopdownL3;tma_load_store_bound_group", - "MetricName": "tma_l1_bound", + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / tma_info_clks - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD", + "MetricGroup": "TopdownL3;tma_L3_group;tma_load_store_bound_group", + "MetricName": "tma_dram_bound", + "MetricThreshold": "tma_dram_bound > 0.1", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a store forward block.", - "MetricExpr": "LD_HEAD.ST_ADDR_AT_RET / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_store_fwd", + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear classified as a fast nuke due to memory ordering, memory disambiguation and memory renaming.", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.FASTNUKE / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group", + "MetricName": "tma_fast_nuke", + "MetricThreshold": "tma_fast_nuke > 0.05", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a first level TLB miss.", - "MetricExpr": "LD_HEAD.DTLB_MISS_AT_RET / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_stlb_hit", + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to FP assists.", + "MetricExpr": "tma_nuke * (MACHINE_CLEARS.FP_ASSIST / MACHINE_CLEARS.SLOW)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", + "MetricName": "tma_fp_assist", + "MetricThreshold": "tma_fp_assist > 0.02", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a second level TLB miss requiring a page walk.", - "MetricExpr": "LD_HEAD.PGWALK_AT_RET / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_stlb_miss", + "BriefDescription": "Counts the number of floating point operations per uop with all default weighting.", + "MetricExpr": "UOPS_RETIRED.FPDIV / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_base_group", + "MetricName": "tma_fp_uops", + "MetricThreshold": "tma_fp_uops > 0.2", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a number of other load blocks.", - "MetricExpr": "LD_HEAD.OTHER_AT_RET / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_other_l1", + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", + "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / tma_info_slots", + "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_frontend_bandwidth", + "MetricThreshold": "tma_frontend_bandwidth > 0.1", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 Cache.", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / CLKS - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD", - "MetricGroup": "TopdownL3;tma_load_store_bound_group", - "MetricName": "tma_l2_bound", + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to frontend stalls.", + "MetricExpr": "TOPDOWN_FE_BOUND.ALL / tma_info_slots", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.2", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / CLKS - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD", - "MetricGroup": "TopdownL3;tma_load_store_bound_group", - "MetricName": "tma_l3_bound", + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", + "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY / tma_info_slots", + "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_frontend_latency", + "MetricThreshold": "tma_frontend_latency > 0.15", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / CLKS - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD", - "MetricGroup": "TopdownL3;tma_load_store_bound_group", - "MetricName": "tma_dram_bound", + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses.", + "MetricExpr": "TOPDOWN_FE_BOUND.ICACHE / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_latency_group", + "MetricName": "tma_icache", + "MetricThreshold": "tma_icache > 0.05", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hits in the L2, LLC, DRAM or MMIO (Non-DRAM) but could not be correctly attributed or cycles in which the load miss is waiting on a request buffer.", - "MetricExpr": "max(0, tma_load_store_bound - (tma_store_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound))", - "MetricGroup": "TopdownL3;tma_load_store_bound_group", - "MetricName": "tma_other_load_store", - "ScaleUnit": "100%" + "BriefDescription": "Percentage of total non-speculative loads with a address aliasing block", + "MetricExpr": "100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricName": "tma_info_address_alias_blocks" }, { - "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls", - "MetricExpr": "tma_backend_bound", - "MetricGroup": "TopdownL1", - "MetricName": "tma_backend_bound_aux", - "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that UOPS must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. All of these subevents count backend stalls, in slots, due to a resource limitation. These are not cycle based events and therefore can not be precisely added or subtracted from the Backend_Bound subevents which are cycle based. These subevents are supplementary to Backend_Bound and can be used to analyze results from a resource perspective at allocation. ", - "ScaleUnit": "100%" + "BriefDescription": "Ratio of all branches which mispredict", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": " ", + "MetricName": "tma_info_branch_mispredict_ratio" }, { - "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls", - "MetricExpr": "tma_backend_bound", - "MetricGroup": "TopdownL2;tma_backend_bound_aux_group", - "MetricName": "tma_resource_bound", - "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. ", - "ScaleUnit": "100%" + "BriefDescription": "Ratio between Mispredicted branches and unknown branches", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BACLEARS.ANY", + "MetricGroup": " ", + "MetricName": "tma_info_branch_mispredict_to_unknown_branch_ratio" }, { - "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.", - "MetricExpr": "TOPDOWN_BE_BOUND.MEM_SCHEDULER / SLOTS", - "MetricGroup": "TopdownL3;tma_resource_bound_group", - "MetricName": "tma_mem_scheduler", - "ScaleUnit": "100%" + "BriefDescription": "", + "MetricExpr": "CPU_CLK_UNHALTED.CORE", + "MetricGroup": " ", + "MetricName": "tma_info_clks" }, { - "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to store buffer full", - "MetricExpr": "tma_mem_scheduler * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_BLOCK.ALL)", - "MetricGroup": "TopdownL4;tma_mem_scheduler_group", - "MetricName": "tma_st_buffer", - "ScaleUnit": "100%" + "BriefDescription": "", + "MetricExpr": "CPU_CLK_UNHALTED.CORE_P", + "MetricGroup": " ", + "MetricName": "tma_info_clks_p" }, { - "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to load buffer full", - "MetricExpr": "tma_mem_scheduler * MEM_SCHEDULER_BLOCK.LD_BUF / MEM_SCHEDULER_BLOCK.ALL", - "MetricGroup": "TopdownL4;tma_mem_scheduler_group", - "MetricName": "tma_ld_buffer", - "ScaleUnit": "100%" + "BriefDescription": "Cycles Per Instruction", + "MetricExpr": "tma_info_clks / INST_RETIRED.ANY", + "MetricGroup": " ", + "MetricName": "tma_info_cpi" }, { - "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to RSV full relative ", - "MetricExpr": "tma_mem_scheduler * MEM_SCHEDULER_BLOCK.RSV / MEM_SCHEDULER_BLOCK.ALL", - "MetricGroup": "TopdownL4;tma_mem_scheduler_group", - "MetricName": "tma_rsv", - "ScaleUnit": "100%" + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": " ", + "MetricName": "tma_info_cpu_utilization" }, { - "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.", - "MetricExpr": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER / SLOTS", - "MetricGroup": "TopdownL3;tma_resource_bound_group", - "MetricName": "tma_non_mem_scheduler", - "ScaleUnit": "100%" + "BriefDescription": "Cycle cost per DRAM hit", + "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_LOAD_UOPS_RETIRED.DRAM_HIT", + "MetricGroup": " ", + "MetricName": "tma_info_cycles_per_demand_load_dram_hit" }, { - "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).", - "MetricExpr": "TOPDOWN_BE_BOUND.REGISTER / SLOTS", - "MetricGroup": "TopdownL3;tma_resource_bound_group", - "MetricName": "tma_register", - "ScaleUnit": "100%" + "BriefDescription": "Cycle cost per L2 hit", + "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_LOAD_UOPS_RETIRED.L2_HIT", + "MetricGroup": " ", + "MetricName": "tma_info_cycles_per_demand_load_l2_hit" }, { - "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls).", - "MetricExpr": "TOPDOWN_BE_BOUND.REORDER_BUFFER / SLOTS", - "MetricGroup": "TopdownL3;tma_resource_bound_group", - "MetricName": "tma_reorder_buffer", - "ScaleUnit": "100%" + "BriefDescription": "Cycle cost per LLC hit", + "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_LOAD_UOPS_RETIRED.L3_HIT", + "MetricGroup": " ", + "MetricName": "tma_info_cycles_per_demand_load_l3_hit" }, { - "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions.", - "MetricExpr": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / SLOTS", - "MetricGroup": "TopdownL3;tma_resource_bound_group", - "MetricName": "tma_alloc_restriction", - "ScaleUnit": "100%" + "BriefDescription": "Percentage of all uops which are FPDiv uops", + "MetricExpr": "100 * UOPS_RETIRED.FPDIV / UOPS_RETIRED.ALL", + "MetricGroup": " ", + "MetricName": "tma_info_fpdiv_uop_ratio" }, { - "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", - "MetricExpr": "TOPDOWN_BE_BOUND.SERIALIZATION / SLOTS", - "MetricGroup": "TopdownL3;tma_resource_bound_group", - "MetricName": "tma_serialization", - "ScaleUnit": "100%" + "BriefDescription": "Percentage of all uops which are IDiv uops", + "MetricExpr": "100 * UOPS_RETIRED.IDIV / UOPS_RETIRED.ALL", + "MetricGroup": " ", + "MetricName": "tma_info_idiv_uop_ratio" }, { - "BriefDescription": "Counts the numer of issue slots that result in retirement slots. ", - "MetricExpr": "TOPDOWN_RETIRING.ALL / SLOTS", - "MetricGroup": "TopdownL1", - "MetricName": "tma_retiring", - "ScaleUnit": "100%" + "BriefDescription": "Percent of instruction miss cost that hit in DRAM", + "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / MEM_BOUND_STALLS.IFETCH", + "MetricGroup": " ", + "MetricName": "tma_info_inst_miss_cost_dramhit_percent" }, { - "BriefDescription": "Counts the number of uops that are not from the microsequencer. ", - "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS) / SLOTS", - "MetricGroup": "TopdownL2;tma_retiring_group", - "MetricName": "tma_base", - "ScaleUnit": "100%" + "BriefDescription": "Percent of instruction miss cost that hit in the L2", + "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / MEM_BOUND_STALLS.IFETCH", + "MetricGroup": " ", + "MetricName": "tma_info_inst_miss_cost_l2hit_percent" }, { - "BriefDescription": "Counts the number of floating point operations per uop with all default weighting.", - "MetricExpr": "UOPS_RETIRED.FPDIV / SLOTS", - "MetricGroup": "TopdownL3;tma_base_group", - "MetricName": "tma_fp_uops", - "ScaleUnit": "100%" + "BriefDescription": "Percent of instruction miss cost that hit in the L3", + "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / MEM_BOUND_STALLS.IFETCH", + "MetricGroup": " ", + "MetricName": "tma_info_inst_miss_cost_l3hit_percent" }, { - "BriefDescription": "Counts the number of uops retired excluding ms and fp div uops.", - "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS - UOPS_RETIRED.FPDIV) / SLOTS", - "MetricGroup": "TopdownL3;tma_base_group", - "MetricName": "tma_other_ret", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Branch (lower number means higher occurance rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": " ", + "MetricName": "tma_info_ipbranch" }, { - "BriefDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS)", - "MetricExpr": "UOPS_RETIRED.MS / SLOTS", - "MetricGroup": "TopdownL2;tma_retiring_group", - "MetricName": "tma_ms_uops", - "PublicDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions Per Cycle", + "MetricExpr": "INST_RETIRED.ANY / tma_info_clks", + "MetricGroup": " ", + "MetricName": "tma_info_ipc" }, { - "BriefDescription": "", - "MetricExpr": "CPU_CLK_UNHALTED.CORE", - "MetricName": "CLKS" + "BriefDescription": "Instruction per (near) call (lower number means higher occurance rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.CALL", + "MetricGroup": " ", + "MetricName": "tma_info_ipcall" }, { - "BriefDescription": "", - "MetricExpr": "CPU_CLK_UNHALTED.CORE_P", - "MetricName": "CLKS_P" + "BriefDescription": "Instructions per Far Branch", + "MetricExpr": "INST_RETIRED.ANY / (BR_INST_RETIRED.FAR_BRANCH / 2)", + "MetricGroup": " ", + "MetricName": "tma_info_ipfarbranch" }, { - "BriefDescription": "", - "MetricExpr": "5 * CLKS", - "MetricName": "SLOTS" + "BriefDescription": "Instructions per Load", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": " ", + "MetricName": "tma_info_ipload" }, { - "BriefDescription": "Instructions Per Cycle", - "MetricExpr": "INST_RETIRED.ANY / CLKS", - "MetricName": "IPC" + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": " ", + "MetricName": "tma_info_ipmispredict" }, { - "BriefDescription": "Cycles Per Instruction", - "MetricExpr": "CLKS / INST_RETIRED.ANY", - "MetricName": "CPI" + "BriefDescription": "Instructions per Store", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": " ", + "MetricName": "tma_info_ipstore" }, { - "BriefDescription": "Uops Per Instruction", - "MetricExpr": "UOPS_RETIRED.ALL / INST_RETIRED.ANY", - "MetricName": "UPI" + "BriefDescription": "Fraction of cycles spent in Kernel mode", + "MetricExpr": "cpu@CPU_CLK_UNHALTED.CORE@k / CPU_CLK_UNHALTED.CORE", + "MetricGroup": " ", + "MetricName": "tma_info_kernel_utilization" }, { - "BriefDescription": "Percentage of total non-speculative loads with a store forward or unknown store address block", - "MetricExpr": "100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricName": "Store_Fwd_Blocks" + "BriefDescription": "Percentage of total non-speculative loads that are splits", + "MetricExpr": "100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricName": "tma_info_load_splits" }, { - "BriefDescription": "Percentage of total non-speculative loads with a address aliasing block", - "MetricExpr": "100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricName": "Address_Alias_Blocks" + "BriefDescription": "load ops retired per 1000 instruction", + "MetricExpr": "1e3 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY", + "MetricGroup": " ", + "MetricName": "tma_info_memloadpki" }, { - "BriefDescription": "Percentage of total non-speculative loads that are splits", - "MetricExpr": "100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricName": "Load_Splits" + "BriefDescription": "Percentage of all uops which are ucode ops", + "MetricExpr": "100 * UOPS_RETIRED.MS / UOPS_RETIRED.ALL", + "MetricGroup": " ", + "MetricName": "tma_info_microcode_uop_ratio" }, { - "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricName": "IpBranch" + "BriefDescription": "", + "MetricExpr": "5 * tma_info_clks", + "MetricGroup": " ", + "MetricName": "tma_info_slots" }, { - "BriefDescription": "Instruction per (near) call (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.CALL", - "MetricName": "IpCall" + "BriefDescription": "Percentage of total non-speculative loads with a store forward or unknown store address block", + "MetricExpr": "100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricName": "tma_info_store_fwd_blocks" }, { - "BriefDescription": "Instructions per Load", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricName": "IpLoad" + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "tma_info_clks / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": " ", + "MetricName": "tma_info_turbo_utilization" }, { - "BriefDescription": "Instructions per Store", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", - "MetricName": "IpStore" + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "UOPS_RETIRED.ALL / INST_RETIRED.ANY", + "MetricGroup": " ", + "MetricName": "tma_info_upi" }, { - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricName": "IpMispredict" + "BriefDescription": "Percentage of all uops which are x87 uops", + "MetricExpr": "100 * UOPS_RETIRED.X87 / UOPS_RETIRED.ALL", + "MetricGroup": " ", + "MetricName": "tma_info_x87_uop_ratio" }, { - "BriefDescription": "Instructions per Far Branch", - "MetricExpr": "INST_RETIRED.ANY / (BR_INST_RETIRED.FAR_BRANCH / 2)", - "MetricName": "IpFarBranch" + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", + "MetricExpr": "TOPDOWN_FE_BOUND.ITLB / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_latency_group", + "MetricName": "tma_itlb", + "MetricThreshold": "tma_itlb > 0.05", + "ScaleUnit": "100%" }, { - "BriefDescription": "Ratio of all branches which mispredict", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.ALL_BRANCHES", - "MetricName": "Branch_Mispredict_Ratio" + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a load block.", + "MetricExpr": "LD_HEAD.L1_BOUND_AT_RET / tma_info_clks", + "MetricGroup": "TopdownL3;tma_L3_group;tma_load_store_bound_group", + "MetricName": "tma_l1_bound", + "MetricThreshold": "tma_l1_bound > 0.1", + "ScaleUnit": "100%" }, { - "BriefDescription": "Ratio between Mispredicted branches and unknown branches", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BACLEARS.ANY", - "MetricName": "Branch_Mispredict_to_Unknown_Branch_Ratio" + "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 Cache.", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / tma_info_clks - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD", + "MetricGroup": "TopdownL3;tma_L3_group;tma_load_store_bound_group", + "MetricName": "tma_l2_bound", + "MetricThreshold": "tma_l2_bound > 0.1", + "ScaleUnit": "100%" }, { - "BriefDescription": "Percentage of all uops which are ucode ops", - "MetricExpr": "100 * UOPS_RETIRED.MS / UOPS_RETIRED.ALL", - "MetricName": "Microcode_Uop_Ratio" + "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", + "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / tma_info_clks - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD", + "MetricGroup": "TopdownL3;tma_L3_group;tma_load_store_bound_group", + "MetricName": "tma_l3_bound", + "MetricThreshold": "tma_l3_bound > 0.1", + "ScaleUnit": "100%" }, { - "BriefDescription": "Percentage of all uops which are FPDiv uops", - "MetricExpr": "100 * UOPS_RETIRED.FPDIV / UOPS_RETIRED.ALL", - "MetricName": "FPDiv_Uop_Ratio" + "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to load buffer full", + "MetricExpr": "tma_mem_scheduler * MEM_SCHEDULER_BLOCK.LD_BUF / MEM_SCHEDULER_BLOCK.ALL", + "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", + "MetricName": "tma_ld_buffer", + "MetricThreshold": "tma_ld_buffer > 0.05", + "ScaleUnit": "100%" }, { - "BriefDescription": "Percentage of all uops which are IDiv uops", - "MetricExpr": "100 * UOPS_RETIRED.IDIV / UOPS_RETIRED.ALL", - "MetricName": "IDiv_Uop_Ratio" + "BriefDescription": "Counts the number of cycles the core is stalled due to stores or loads.", + "MetricExpr": "min(tma_backend_bound, LD_HEAD.ANY_AT_RET / tma_info_clks + tma_store_bound)", + "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_load_store_bound", + "MetricThreshold": "tma_load_store_bound > 0.2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Percentage of all uops which are x87 uops", - "MetricExpr": "100 * UOPS_RETIRED.X87 / UOPS_RETIRED.ALL", - "MetricName": "X87_Uop_Ratio" + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS / tma_info_slots", + "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.05", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average Frequency Utilization relative nominal frequency", - "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC", - "MetricName": "Turbo_Utilization" + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.", + "MetricExpr": "TOPDOWN_BE_BOUND.MEM_SCHEDULER / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_mem_scheduler", + "MetricThreshold": "tma_mem_scheduler > 0.1", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of cycles spent in Kernel mode", - "MetricExpr": "cpu@CPU_CLK_UNHALTED.CORE@k / CPU_CLK_UNHALTED.CORE", - "MetricName": "Kernel_Utilization" + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to memory ordering.", + "MetricExpr": "tma_nuke * (MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.SLOW)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", + "MetricName": "tma_memory_ordering", + "MetricThreshold": "tma_memory_ordering > 0.02", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average CPU Utilization", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", - "MetricName": "CPU_Utilization" + "BriefDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS)", + "MetricExpr": "UOPS_RETIRED.MS / tma_info_slots", + "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_ms_uops", + "MetricThreshold": "tma_ms_uops > 0.05", + "PublicDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Cycle cost per L2 hit", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_LOAD_UOPS_RETIRED.L2_HIT", - "MetricName": "Cycles_per_Demand_Load_L2_Hit" + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.", + "MetricExpr": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_non_mem_scheduler", + "MetricThreshold": "tma_non_mem_scheduler > 0.1", + "ScaleUnit": "100%" }, { - "BriefDescription": "Cycle cost per LLC hit", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_LOAD_UOPS_RETIRED.L3_HIT", - "MetricName": "Cycles_per_Demand_Load_L3_Hit" + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear (slow nuke).", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.NUKE / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group", + "MetricName": "tma_nuke", + "MetricThreshold": "tma_nuke > 0.05", + "ScaleUnit": "100%" }, { - "BriefDescription": "Cycle cost per DRAM hit", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_LOAD_UOPS_RETIRED.DRAM_HIT", - "MetricName": "Cycles_per_Demand_Load_DRAM_Hit" + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized.", + "MetricExpr": "TOPDOWN_FE_BOUND.OTHER / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_bandwidth_group", + "MetricName": "tma_other_fb", + "MetricThreshold": "tma_other_fb > 0.05", + "ScaleUnit": "100%" }, { - "BriefDescription": "Percent of instruction miss cost that hit in the L2", - "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / MEM_BOUND_STALLS.IFETCH", - "MetricName": "Inst_Miss_Cost_L2Hit_Percent" + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a number of other load blocks.", + "MetricExpr": "LD_HEAD.OTHER_AT_RET / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_other_l1", + "MetricThreshold": "tma_other_l1 > 0.05", + "ScaleUnit": "100%" }, { - "BriefDescription": "Percent of instruction miss cost that hit in the L3", - "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / MEM_BOUND_STALLS.IFETCH", - "MetricName": "Inst_Miss_Cost_L3Hit_Percent" + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hits in the L2, LLC, DRAM or MMIO (Non-DRAM) but could not be correctly attributed or cycles in which the load miss is waiting on a request buffer.", + "MetricExpr": "max(0, tma_load_store_bound - (tma_store_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound))", + "MetricGroup": "TopdownL3;tma_L3_group;tma_load_store_bound_group", + "MetricName": "tma_other_load_store", + "MetricThreshold": "tma_other_load_store > 0.1", + "ScaleUnit": "100%" }, { - "BriefDescription": "Percent of instruction miss cost that hit in DRAM", - "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / MEM_BOUND_STALLS.IFETCH", - "MetricName": "Inst_Miss_Cost_DRAMHit_Percent" + "BriefDescription": "Counts the number of uops retired excluding ms and fp div uops.", + "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS - UOPS_RETIRED.FPDIV) / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_base_group", + "MetricName": "tma_other_ret", + "MetricThreshold": "tma_other_ret > 0.3", + "ScaleUnit": "100%" }, { - "BriefDescription": "load ops retired per 1000 instruction", - "MetricExpr": "1e3 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY", - "MetricName": "MemLoadPKI" + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to page faults.", + "MetricExpr": "tma_nuke * (MACHINE_CLEARS.PAGE_FAULT / MACHINE_CLEARS.SLOW)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", + "MetricName": "tma_page_fault", + "MetricThreshold": "tma_page_fault > 0.02", + "ScaleUnit": "100%" }, { - "BriefDescription": "C1 residency percent per core", - "MetricExpr": "cstate_core@c1\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C1_Core_Residency", + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes.", + "MetricExpr": "TOPDOWN_FE_BOUND.PREDECODE / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_bandwidth_group", + "MetricName": "tma_predecode", + "MetricThreshold": "tma_predecode > 0.05", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per core", - "MetricExpr": "cstate_core@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Core_Residency", + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).", + "MetricExpr": "TOPDOWN_BE_BOUND.REGISTER / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_register", + "MetricThreshold": "tma_register > 0.1", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per core", - "MetricExpr": "cstate_core@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Core_Residency", + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls).", + "MetricExpr": "TOPDOWN_BE_BOUND.REORDER_BUFFER / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_reorder_buffer", + "MetricThreshold": "tma_reorder_buffer > 0.1", "ScaleUnit": "100%" }, { - "BriefDescription": "C2 residency percent per package", - "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C2_Pkg_Residency", + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls", + "MetricExpr": "tma_backend_bound", + "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_aux_group", + "MetricName": "tma_resource_bound", + "MetricThreshold": "tma_resource_bound > 0.2", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count.", "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per package", - "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Pkg_Residency", + "BriefDescription": "Counts the numer of issue slots that result in retirement slots.", + "MetricExpr": "TOPDOWN_RETIRING.ALL / tma_info_slots", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.75", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per package", - "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Pkg_Residency", + "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to RSV full relative", + "MetricExpr": "tma_mem_scheduler * MEM_SCHEDULER_BLOCK.RSV / MEM_SCHEDULER_BLOCK.ALL", + "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", + "MetricName": "tma_rsv", + "MetricThreshold": "tma_rsv > 0.05", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per package", - "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Pkg_Residency", + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", + "MetricExpr": "TOPDOWN_BE_BOUND.SERIALIZATION / tma_info_slots", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_serialization", + "MetricThreshold": "tma_serialization > 0.1", "ScaleUnit": "100%" }, { - "BriefDescription": "C8 residency percent per package", - "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C8_Pkg_Residency", + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to SMC.", + "MetricExpr": "tma_nuke * (MACHINE_CLEARS.SMC / MACHINE_CLEARS.SLOW)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", + "MetricName": "tma_smc", + "MetricThreshold": "tma_smc > 0.02", "ScaleUnit": "100%" }, { - "BriefDescription": "C9 residency percent per package", - "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C9_Pkg_Residency", + "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to store buffer full", + "MetricExpr": "tma_store_bound", + "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", + "MetricName": "tma_st_buffer", + "MetricThreshold": "tma_st_buffer > 0.05", "ScaleUnit": "100%" }, { - "BriefDescription": "C10 residency percent per package", - "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C10_Pkg_Residency", + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a first level TLB miss.", + "MetricExpr": "LD_HEAD.DTLB_MISS_AT_RET / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_stlb_hit", + "MetricThreshold": "tma_stlb_hit > 0.05", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a second level TLB miss requiring a page walk.", + "MetricExpr": "LD_HEAD.PGWALK_AT_RET / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_stlb_miss", + "MetricThreshold": "tma_stlb_miss > 0.05", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full.", + "MetricExpr": "tma_mem_scheduler * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_BLOCK.ALL)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_load_store_bound_group", + "MetricName": "tma_store_bound", + "MetricThreshold": "tma_store_bound > 0.1", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a store forward block.", + "MetricExpr": "LD_HEAD.ST_ADDR_AT_RET / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_store_fwd", + "MetricThreshold": "tma_store_fwd > 0.05", "ScaleUnit": "100%" } ] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 4bcccab07ea9..cad51223d0ea 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -1,6 +1,6 @@ Family-model,Version,Filename,EventType GenuineIntel-6-(97|9A|B7|BA|BF),v1.18,alderlake,core -GenuineIntel-6-BE,v1.16,alderlaken,core +GenuineIntel-6-BE,v1.18,alderlaken,core GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core GenuineIntel-6-(3D|47),v26,broadwell,core GenuineIntel-6-56,v7,broadwellde,core -- cgit v1.2.3-58-ga151 From 1ab15f66b918425d9ea2529b54db0552025c9cc0 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:09 -0800 Subject: perf vendor events intel: Refresh broadwell metrics Update the broadwell metrics to TMA version 4.5. Generation was done using https://github.com/intel/perfmon. Notable changes are TMA info metrics are renamed from their node name to be lower case and prefixed by tma_info_, MetricThreshold expressions are added, and the smi_cost metric group is added replicating existing hard coded metrics in stat-shadow. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-13-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/broadwell/bdw-metrics.json | 1439 +++++++++++--------- 1 file changed, 805 insertions(+), 634 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json b/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json index c3ea39d6c944..51cf8560a8d3 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json @@ -1,965 +1,1136 @@ [ { - "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", - "MetricGroup": "PGO;TopdownL1;tma_L1_group", - "MetricName": "tma_frontend_bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", + "BriefDescription": "C2 residency percent per package", + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C2_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", - "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS", - "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_latency", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", + "BriefDescription": "C3 residency percent per core", + "MetricExpr": "cstate_core@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", - "MetricExpr": "ICACHE.IFDATA_STALL / CLKS", - "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_icache_misses", + "BriefDescription": "C3 residency percent per package", + "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", - "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * ITLB_MISSES.WALK_COMPLETED) / CLKS", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_itlb_misses", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED", + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", - "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / CLKS", - "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_branch_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group", - "MetricName": "tma_mispredicts_resteers", + "BriefDescription": "C7 residency percent per core", + "MetricExpr": "cstate_core@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ", - "MetricExpr": "MACHINE_CLEARS.COUNT * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)", - "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group", - "MetricName": "tma_clears_resteers", + "BriefDescription": "C7 residency percent per package", + "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", - "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers", - "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_branch_resteers_group", - "MetricName": "tma_unknown_branches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit). Sample with: BACLEARS.ANY", - "ScaleUnit": "100%" + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "tma_info_socket_clks / #num_dies / duration_time / 1e9", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_dsb_switches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "BriefDescription": "Percentage of cycles spent in System Management Interrupts.", + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", + "MetricGroup": "smi", + "MetricName": "smi_cycles", + "MetricThreshold": "smi_cycles > 0.1", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", - "MetricExpr": "ILD_STALL.LCP / CLKS", - "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_lcp", - "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", - "ScaleUnit": "100%" + "BriefDescription": "Number of SMI interrupts.", + "MetricExpr": "msr@smi@", + "MetricGroup": "smi", + "MetricName": "smi_num", + "ScaleUnit": "1SMI#" }, { - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", - "MetricExpr": "2 * IDQ.MS_SWITCHES / CLKS", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_ms_switches", - "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES", + "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", + "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_4k_aliasing", + "MetricThreshold": "tma_4k_aliasing > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", - "MetricExpr": "tma_frontend_bound - tma_fetch_latency", - "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_bandwidth", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / tma_info_slots", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_alu_op_utilization", + "MetricThreshold": "tma_alu_op_utilization > 0.6", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", - "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2", - "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_group", - "MetricName": "tma_mite", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", + "MetricExpr": "100 * OTHER_ASSISTS.ANY_WB_ASSIST / tma_info_slots", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_assists", + "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", - "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2", - "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group", - "MetricName": "tma_dsb", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_backend_bound", + "MetricThreshold": "tma_backend_bound > 0.2", + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", "ScaleUnit": "100%" }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", - "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", + "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", + "MetricThreshold": "tma_bad_speculation > 0.15", "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", - "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_machine_clears", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", + "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_branch_resteers", + "MetricThreshold": "tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", "ScaleUnit": "100%" }, { - "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", - "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_backend_bound", - "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_cisc", + "MetricThreshold": "tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) * tma_backend_bound", - "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_memory_bound", - "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears", + "MetricExpr": "MACHINE_CLEARS.COUNT * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)", + "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC", + "MetricName": "tma_clears_resteers", + "MetricThreshold": "tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", - "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CLKS, 0)", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l1_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT_PS;MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_contested_accesses", + "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", - "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * DTLB_LOAD_MISSES.WALK_COMPLETED) / CLKS", - "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_dtlb_load", - "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS", + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_backend_bound - tma_memory_bound", + "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", - "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_store_fwd_blk", - "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / tma_info_clks", + "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_data_sharing", + "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", - "MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS", - "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_lock_latency", - "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS", + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", + "MetricExpr": "ARITH.FPU_DIV_ACTIVE / tma_info_core_clks", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_divider", + "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", - "MetricExpr": "Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_split_loads", - "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_UOPS_RETIRED.SPLIT_LOADS_PS", + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", + "MetricConstraint": "NO_GROUP_EVENTS_SMT", + "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_dram_bound", + "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", - "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_4k_aliasing", - "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", + "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / tma_info_core_clks / 2", + "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_dsb", + "MetricThreshold": "tma_dsb > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", - "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / CLKS", - "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_fb_full", - "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_clks", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_dsb_switches", + "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Related metrics: tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l2_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS", + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", + "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * DTLB_LOAD_MISSES.WALK_COMPLETED) / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group", + "MetricName": "tma_dtlb_load", + "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", - "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l3_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS", + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", + "MetricExpr": "(8 * DTLB_STORE_MISSES.STLB_HIT + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * DTLB_STORE_MISSES.WALK_COMPLETED) / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group", + "MetricName": "tma_dtlb_store", + "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", - "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / CLKS", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_contested_accesses", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS", + "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", + "MetricExpr": "60 * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group", + "MetricName": "tma_false_sharing", + "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", - "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_data_sharing", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS", + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_info_load_miss_real_latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / tma_info_clks", + "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricName": "tma_fb_full", + "MetricThreshold": "tma_fb_full > 0.3", + "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", - "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS", - "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_l3_hit_latency", - "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS", + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", + "MetricExpr": "tma_frontend_bound - tma_fetch_latency", + "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", + "MetricName": "tma_fetch_bandwidth", + "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", - "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_sq_full", - "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.", + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", + "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / tma_info_slots", + "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_latency", + "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", - "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_dram_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS", + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", + "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", + "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_fp_arith", + "MetricThreshold": "tma_fp_arith > 0.2 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group", - "MetricName": "tma_mem_bandwidth", - "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", + "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_scalar", + "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group", - "MetricName": "tma_mem_latency", - "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", + "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@ / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_vector", + "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", - "MetricExpr": "RESOURCE_STALLS.SB / CLKS", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_store_bound", - "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES_PS", + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_128b", + "MetricThreshold": "tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", - "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group", - "MetricName": "tma_store_latency", - "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_256b", + "MetricThreshold": "tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", - "MetricExpr": "60 * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group", - "MetricName": "tma_false_sharing", - "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_slots", + "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.15", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents rate of split store accesses", - "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / CORE_CLKS", - "MetricGroup": "TopdownL4;tma_store_bound_group", - "MetricName": "tma_split_stores", - "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_UOPS_RETIRED.SPLIT_STORES_PS", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences", + "MetricExpr": "tma_microcode_sequencer", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_heavy_operations", + "MetricThreshold": "tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", - "MetricExpr": "(8 * DTLB_STORE_MISSES.STLB_HIT + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * DTLB_STORE_MISSES.WALK_COMPLETED) / CLKS", - "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group", - "MetricName": "tma_dtlb_store", - "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", + "MetricExpr": "ICACHE.IFDATA_STALL / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_icache_misses", + "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", - "MetricExpr": "tma_backend_bound - tma_memory_bound", - "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_core_bound", - "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", - "ScaleUnit": "100%" + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "tma_info_turbo_utilization * TSC / 1e9 / duration_time", + "MetricGroup": "Power;Summary", + "MetricName": "tma_info_average_frequency" }, { - "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", - "MetricExpr": "ARITH.FPU_DIV_ACTIVE / CORE_CLKS", - "MetricGroup": "TopdownL3;tma_core_bound_group", - "MetricName": "tma_divider", - "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS", - "ScaleUnit": "100%" + "BriefDescription": "Branch instructions per taken branch.", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_bptkbranch" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", - "MetricExpr": "((CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CLKS", - "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group", - "MetricName": "tma_ports_utilization", - "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", - "ScaleUnit": "100%" + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_slots / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts;tma_issueBM", + "MetricName": "tma_info_branch_misprediction_cost", + "PublicDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_branch_mispredicts, tma_mispredicts_resteers" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) / CORE_CLKS)", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_0", - "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", - "ScaleUnit": "100%" + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline", + "MetricName": "tma_info_clks" }, { - "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS)", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_1", - "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", - "ScaleUnit": "100%" + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else tma_info_clks))", + "MetricGroup": "SMT", + "MetricName": "tma_info_core_clks" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS)", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_2", - "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_core_clks", + "MetricGroup": "Ret;SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_coreipc" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", - "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_3m", - "ScaleUnit": "100%" + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / tma_info_ipc", + "MetricGroup": "Mem;Pipeline", + "MetricName": "tma_info_cpi" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_alu_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "HPC;Summary", + "MetricName": "tma_info_cpu_utilization" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) Sample with: UOPS_DISPATCHED_PORT.PORT_0", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS", - "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_0", - "ScaleUnit": "100%" + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_data_l2_mlp" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_1", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_1", - "ScaleUnit": "100%" + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;tma_issueBW", + "MetricName": "tma_info_dram_bw_use", + "PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_mem_bandwidth, tma_sq_full" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) Sample with: UOPS_DISPATCHED.PORT_5", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_5", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", + "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", + "MetricName": "tma_info_dsb_coverage", + "MetricThreshold": "tma_info_dsb_coverage < 0.7 & tma_info_ipc / 4 > 0.35", + "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_iptb, tma_lcp" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_6", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_6", - "ScaleUnit": "100%" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-thread", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "tma_info_execute" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations Sample with: UOPS_DISPATCHED.PORT_2_3", - "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_load_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "tma_info_execute_per_issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_2", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_load_op_utilization_group", - "MetricName": "tma_port_2", - "ScaleUnit": "100%" + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / tma_info_core_clks", + "MetricGroup": "Flops;Ret", + "MetricName": "tma_info_flopc" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_3", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_load_op_utilization_group", - "MetricName": "tma_port_3", - "ScaleUnit": "100%" + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", + "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@) / (2 * tma_info_core_clks)", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_fp_arith_utilization", + "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", - "MetricExpr": "tma_port_4", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_store_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Giga Floating Point Operations Per Second", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_gflops", + "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data) Sample with: UOPS_DISPATCHED_PORT.PORT_4", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_store_op_utilization_group", - "MetricName": "tma_port_4", - "ScaleUnit": "100%" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", + "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", + "MetricName": "tma_info_ilp" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address) Sample with: UOPS_DISPATCHED_PORT.PORT_7", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_store_op_utilization_group", - "MetricName": "tma_port_7", - "ScaleUnit": "100%" + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;tma_L1_group", + "MetricName": "tma_info_instructions", + "PublicDescription": "Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST" }, { - "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_iparith", + "MetricThreshold": "tma_info_iparith < 10", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", - "MetricExpr": "tma_retiring - tma_heavy_operations", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_light_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx128", + "MetricThreshold": "tma_info_iparith_avx128 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", - "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", - "MetricGroup": "HPC;TopdownL3;tma_light_operations_group", - "MetricName": "tma_fp_arith", - "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx256", + "MetricThreshold": "tma_info_iparith_avx256 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "This metric serves as an approximation of legacy x87 usage", - "MetricExpr": "INST_RETIRED.X87 * UPI / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_x87_use", - "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_iparith_scalar_dp", + "MetricThreshold": "tma_info_iparith_scalar_dp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_fp_scalar", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_iparith_scalar_sp", + "MetricThreshold": "tma_info_iparith_scalar_sp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", - "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_fp_vector", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "tma_info_ipbranch", + "MetricThreshold": "tma_info_ipbranch < 8" }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", - "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group", - "MetricName": "tma_fp_vector_128b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_clks", + "MetricGroup": "Ret;Summary", + "MetricName": "tma_info_ipc" }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", - "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group", - "MetricName": "tma_fp_vector_256b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_ipcall", + "MetricThreshold": "tma_info_ipcall < 200" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences", - "MetricExpr": "tma_microcode_sequencer", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_heavy_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "tma_info_ipfarbranch", + "MetricThreshold": "tma_info_ipfarbranch < 1e6" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS", - "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group", - "MetricName": "tma_microcode_sequencer", - "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_ipflop", + "MetricThreshold": "tma_info_ipflop < 10" }, { - "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", - "MetricExpr": "100 * OTHER_ASSISTS.ANY_WB_ASSIST / SLOTS", - "MetricGroup": "TopdownL4;tma_microcode_sequencer_group", - "MetricName": "tma_assists", - "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipload", + "MetricThreshold": "tma_info_ipload < 3" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", - "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", - "MetricGroup": "TopdownL4;tma_microcode_sequencer_group", - "MetricName": "tma_cisc", - "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "tma_info_instructions / (UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * cpu@BR_MISP_EXEC.ALL_BRANCHES\\,umask\\=0xE4@)", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_indirect", + "MetricThreshold": "tma_info_ipmisp_indirect < 1e3" }, { - "BriefDescription": "Instructions Per Cycle (per Logical Processor)", - "MetricExpr": "INST_RETIRED.ANY / CLKS", - "MetricGroup": "Ret;Summary", - "MetricName": "IPC" + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "tma_info_ipmispredict", + "MetricThreshold": "tma_info_ipmispredict < 200" }, { - "BriefDescription": "Uops Per Instruction", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Ret;Retire", - "MetricName": "UPI" + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipstore", + "MetricThreshold": "tma_info_ipstore < 8" }, { "BriefDescription": "Instruction per taken branch", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW", - "MetricName": "UpTB" + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", + "MetricName": "tma_info_iptb", + "MetricThreshold": "tma_info_iptb < 9", + "PublicDescription": "Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_lcp" }, { - "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / IPC", - "MetricGroup": "Mem;Pipeline", - "MetricName": "CPI" + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "tma_info_instructions / BACLEARS.ANY", + "MetricGroup": "Fed", + "MetricName": "tma_info_ipunknown_branch" }, { - "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Pipeline", - "MetricName": "CLKS" + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_cpi" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", - "MetricExpr": "4 * CORE_CLKS", - "MetricGroup": "tma_L1_group", - "MetricName": "SLOTS" + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_utilization", + "MetricThreshold": "tma_info_kernel_utilization > 0.05" }, { - "BriefDescription": "The ratio of Executed- by Issued-Uops", - "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", - "MetricGroup": "Cor;Pipeline", - "MetricName": "Execute_per_Issue", - "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw" }, { - "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS", - "MetricGroup": "Ret;SMT;tma_L1_group", - "MetricName": "CoreIPC" + "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "tma_info_l1d_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw_1t" }, { - "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS", - "MetricGroup": "Flops;Ret", - "MetricName": "FLOPc" + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l1mpki" }, { - "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "FP_Arith_Utilization", - "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw" }, { - "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", - "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", - "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", - "MetricName": "ILP" + "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "tma_info_l2_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw_1t" }, { - "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", - "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))", - "MetricGroup": "SMT", - "MetricName": "CORE_CLKS" + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2hpki_all" }, { - "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricGroup": "InsType", - "MetricName": "IpLoad" + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2hpki_load" }, { - "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", - "MetricGroup": "InsType", - "MetricName": "IpStore" + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Backend;CacheMisses;Mem", + "MetricName": "tma_info_l2mpki" }, { - "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Fed;InsType", - "MetricName": "IpBranch" + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem;Offcore", + "MetricName": "tma_info_l2mpki_all" }, { - "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "IpCall" + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2mpki_load" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", - "MetricName": "IpTB" + "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "0", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_l3_cache_access_bw_1t" }, { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "BpTkBranch" + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw" }, { - "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", - "MetricGroup": "Flops;InsType", - "MetricName": "IpFLOP" + "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_l3_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw_1t" }, { - "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))", - "MetricGroup": "Flops;InsType", - "MetricName": "IpArith", - "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l3mpki" }, { - "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", - "MetricGroup": "Flops;FpScalar;InsType", - "MetricName": "IpArith_Scalar_SP", - "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore", + "MetricName": "tma_info_load_l2_miss_latency" }, { - "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", - "MetricGroup": "Flops;FpScalar;InsType", - "MetricName": "IpArith_Scalar_DP", - "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_load_l2_mlp" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX128", - "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "tma_info_load_miss_real_latency" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX256", - "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "Average number of parallel requests to external memory", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", + "MetricGroup": "Mem;SoC", + "MetricName": "tma_info_mem_parallel_requests", + "PublicDescription": "Average number of parallel requests to external memory. Accounts for all requests" }, { - "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary;tma_L1_group", - "MetricName": "Instructions" + "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL", + "MetricGroup": "Mem;SoC", + "MetricName": "tma_info_mem_request_latency" + }, + { + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBW;MemoryBound", + "MetricName": "tma_info_mlp", + "PublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "(cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * (DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED)) / tma_info_core_clks", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_page_walks_utilization", + "MetricThreshold": "tma_info_page_walks_utilization > 0.5" }, { "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@", "MetricGroup": "Pipeline;Ret", - "MetricName": "Retire" + "MetricName": "tma_info_retire" }, { - "BriefDescription": "", - "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", - "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", - "MetricName": "Execute" + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * tma_info_core_clks", + "MetricGroup": "TmaL1;tma_L1_group", + "MetricName": "tma_info_slots" }, { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "DSB;Fed;FetchBW", - "MetricName": "DSB_Coverage" + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", + "MetricGroup": "SMT", + "MetricName": "tma_info_smt_2t_utilization" }, { - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "UNC_CLOCK.SOCKET", + "MetricGroup": "SoC", + "MetricName": "tma_info_socket_clks" }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BrMispredicts", - "MetricName": "Branch_Misprediction_Cost" + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "tma_info_clks / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power", + "MetricName": "tma_info_turbo_utilization" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)", - "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency" + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire", + "MetricName": "tma_info_uoppi", + "MetricThreshold": "tma_info_uoppi > 1.05" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "Mem;MemoryBW;MemoryBound", - "MetricName": "MLP" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "tma_info_uptb", + "MetricThreshold": "tma_info_uptb < 6" }, { - "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", + "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * ITLB_MISSES.WALK_COMPLETED) / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Backend;CacheMisses;Mem", - "MetricName": "L2MPKI" + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", + "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / tma_info_clks, 0)", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group", + "MetricName": "tma_l1_bound", + "MetricThreshold": "tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT_PS;MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem;Offcore", - "MetricName": "L2MPKI_All" + "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l2_bound", + "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2MPKI_Load" + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", + "MetricConstraint": "NO_GROUP_EVENTS_SMT", + "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_MISS / tma_info_clks", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l3_bound", + "MetricThreshold": "tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", - "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2HPKI_All" + "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / tma_info_clks", + "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group", + "MetricName": "tma_l3_hit_latency", + "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS. Related metrics: tma_mem_latency", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2HPKI_Load" + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", + "MetricExpr": "ILD_STALL.LCP / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_lcp", + "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_iptb", + "ScaleUnit": "100%" }, { - "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L3MPKI" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", + "MetricExpr": "tma_retiring - tma_heavy_operations", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_light_operations", + "MetricThreshold": "tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", + "ScaleUnit": "100%" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "(cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * (DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED)) / CORE_CLKS", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "Page_Walks_Utilization" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_load_op_utilization", + "MetricThreshold": "tma_load_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / tma_info_clks", + "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group", + "MetricName": "tma_lock_latency", + "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", + "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW", + "MetricName": "tma_mem_bandwidth", + "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_sq_full", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "L1D_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW_1T" + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_clks - tma_mem_bandwidth", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat", + "MetricName": "tma_mem_latency", + "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_l3_hit_latency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "L2_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW_1T" + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound", + "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_memory_bound", + "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW_1T" + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_slots", + "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS", + "MetricName": "tma_microcode_sequencer", + "MetricThreshold": "tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "0", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW_1T" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)", + "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM", + "MetricName": "tma_mispredicts_resteers", + "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Related metrics: tma_branch_mispredicts, tma_info_branch_misprediction_cost", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average CPU Utilization", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", - "MetricGroup": "HPC;Summary", - "MetricName": "CPU_Utilization" + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", + "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / tma_info_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_mite", + "MetricThreshold": "tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", - "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time", - "MetricGroup": "Power;Summary", - "MetricName": "Average_Frequency" + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", + "MetricExpr": "2 * IDQ.MS_SWITCHES / tma_info_clks", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", + "MetricName": "tma_ms_switches", + "MetricThreshold": "tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation", + "ScaleUnit": "100%" }, { - "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs", - "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / tma_info_core_clks", + "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_0", + "MetricThreshold": "tma_port_0 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED_PORT.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average Frequency Utilization relative nominal frequency", - "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC", - "MetricGroup": "Power", - "MetricName": "Turbo_Utilization" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_1", + "MetricThreshold": "tma_port_1 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", - "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", - "MetricGroup": "SMT", - "MetricName": "SMT_2T_Utilization" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", + "MetricName": "tma_port_2", + "MetricThreshold": "tma_port_2 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "OS", - "MetricName": "Kernel_Utilization" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", + "MetricName": "tma_port_3", + "MetricThreshold": "tma_port_3 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_3", + "ScaleUnit": "100%" }, { - "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", - "MetricGroup": "OS", - "MetricName": "Kernel_CPI" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)", + "MetricExpr": "tma_store_op_utilization", + "MetricGroup": "TopdownL6;tma_L6_group;tma_issueSpSt;tma_store_op_utilization_group", + "MetricName": "tma_port_4", + "MetricThreshold": "tma_port_4 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Sample with: UOPS_DISPATCHED_PORT.PORT_4. Related metrics: tma_split_stores", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", - "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3", - "MetricGroup": "HPC;Mem;MemoryBW;SoC", - "MetricName": "DRAM_BW_Use" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_5", + "MetricThreshold": "tma_port_5 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Sample with: UOPS_DISPATCHED.PORT_5. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)", - "MetricExpr": "MEM_Parallel_Requests", - "MetricGroup": "Mem;SoC", - "MetricName": "MEM_Request_Latency" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_6", + "MetricThreshold": "tma_port_6 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests", - "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL", - "MetricGroup": "Mem;SoC", - "MetricName": "MEM_Parallel_Requests" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group", + "MetricName": "tma_port_7", + "MetricThreshold": "tma_port_7 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address). Sample with: UOPS_DISPATCHED_PORT.PORT_7", + "ScaleUnit": "100%" }, { - "BriefDescription": "Socket actual clocks when any core is active on that socket", - "MetricExpr": "UNC_CLOCK.SOCKET", - "MetricGroup": "SoC", - "MetricName": "Socket_CLKS" + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_ports_utilization", + "MetricThreshold": "tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", - "MetricGroup": "Branches;OS", - "MetricName": "IpFarBranch" + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0)) / tma_info_core_clks)", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_0", + "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Uncore frequency per die [GHZ]", - "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9", - "MetricGroup": "SoC", - "MetricName": "UNCORE_FREQ" + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / tma_info_core_clks)", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_1", + "MetricThreshold": "tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Related metrics: tma_l1_bound", + "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per core", - "MetricExpr": "cstate_core@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Core_Residency", + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_clks)", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_2", + "MetricThreshold": "tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per core", - "MetricExpr": "cstate_core@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Core_Residency", + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", + "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_3m", + "MetricThreshold": "tma_ports_utilized_3m > 0.7 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per core", - "MetricExpr": "cstate_core@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Core_Residency", + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", "ScaleUnit": "100%" }, { - "BriefDescription": "C2 residency percent per package", - "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C2_Pkg_Residency", + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_info_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_split_loads", + "MetricThreshold": "tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_UOPS_RETIRED.SPLIT_LOADS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per package", - "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Pkg_Residency", + "BriefDescription": "This metric represents rate of split store accesses", + "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / tma_info_core_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group", + "MetricName": "tma_split_stores", + "MetricThreshold": "tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_UOPS_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per package", - "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Pkg_Residency", + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", + "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group", + "MetricName": "tma_sq_full", + "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_mem_bandwidth", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per package", - "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Pkg_Residency", + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", + "MetricExpr": "RESOURCE_STALLS.SB / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_store_bound", + "MetricThreshold": "tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", + "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_store_fwd_blk", + "MetricThreshold": "tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_clks", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group", + "MetricName": "tma_store_latency", + "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / tma_info_core_clks", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_store_op_utilization", + "MetricThreshold": "tma_store_op_utilization > 0.6", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", + "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers", + "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", + "MetricName": "tma_unknown_branches", + "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit). Sample with: BACLEARS.ANY", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric serves as an approximation of legacy x87 usage", + "MetricExpr": "INST_RETIRED.X87 * tma_info_uoppi / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_x87_use", + "MetricThreshold": "tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", "ScaleUnit": "100%" } ] -- cgit v1.2.3-58-ga151 From 7d38ef20bab229f40e671533c0c6c39e41c2cfa3 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:10 -0800 Subject: perf vendor events intel: Refresh broadwellde metrics Update the broadwellde metrics to TMA version 4.5. Generation was done using https://github.com/intel/perfmon. Notable changes are TMA info metrics are renamed from their node name to be lower case and prefixed by tma_info_, MetricThreshold expressions are added, and the smi_cost metric group is added replicating existing hard coded metrics in stat-shadow. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-14-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/x86/broadwellde/bdwde-metrics.json | 1405 +++++++++++--------- 1 file changed, 785 insertions(+), 620 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json b/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json index d35d30932b68..fb57c7382408 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json @@ -1,937 +1,1102 @@ [ { - "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", - "MetricGroup": "PGO;TopdownL1;tma_L1_group", - "MetricName": "tma_frontend_bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", - "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS", - "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_latency", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", + "BriefDescription": "C2 residency percent per package", + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C2_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses", - "MetricExpr": "ICACHE.IFDATA_STALL / CLKS", - "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_icache_misses", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", + "BriefDescription": "C3 residency percent per core", + "MetricExpr": "cstate_core@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", - "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * ITLB_MISSES.WALK_COMPLETED) / CLKS", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_itlb_misses", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", + "BriefDescription": "C3 residency percent per package", + "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", - "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / CLKS", - "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_branch_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group", - "MetricName": "tma_mispredicts_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES", + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears", - "MetricExpr": "MACHINE_CLEARS.COUNT * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)", - "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group", - "MetricName": "tma_clears_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES", + "BriefDescription": "C7 residency percent per core", + "MetricExpr": "cstate_core@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", - "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers", - "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_branch_resteers_group", - "MetricName": "tma_unknown_branches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit). Sample with: FRONTEND_RETIRED.UNKNOWN_BRANCH", + "BriefDescription": "C7 residency percent per package", + "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_dsb_switches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS", + "BriefDescription": "Percentage of cycles spent in System Management Interrupts.", + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", + "MetricGroup": "smi", + "MetricName": "smi_cycles", + "MetricThreshold": "smi_cycles > 0.1", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", - "MetricExpr": "ILD_STALL.LCP / CLKS", - "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_lcp", - "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", - "ScaleUnit": "100%" + "BriefDescription": "Number of SMI interrupts.", + "MetricExpr": "msr@smi@", + "MetricGroup": "smi", + "MetricName": "smi_num", + "ScaleUnit": "1SMI#" }, { - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", - "MetricExpr": "2 * IDQ.MS_SWITCHES / CLKS", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_ms_switches", - "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES", + "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", + "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_4k_aliasing", + "MetricThreshold": "tma_4k_aliasing > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", - "MetricExpr": "tma_frontend_bound - tma_fetch_latency", - "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_bandwidth", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / tma_info_slots", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_alu_op_utilization", + "MetricThreshold": "tma_alu_op_utilization > 0.6", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", - "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2", - "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_group", - "MetricName": "tma_mite", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS", + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", + "MetricExpr": "100 * OTHER_ASSISTS.ANY_WB_ASSIST / tma_info_slots", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_assists", + "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", - "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2", - "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group", - "MetricName": "tma_dsb", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_backend_bound", + "MetricThreshold": "tma_backend_bound > 0.2", + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", "ScaleUnit": "100%" }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", - "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", + "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", + "MetricThreshold": "tma_bad_speculation > 0.15", "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS", + "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", - "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_machine_clears", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", + "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_branch_resteers", + "MetricThreshold": "tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", "ScaleUnit": "100%" }, { - "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", - "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_backend_bound", - "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_cisc", + "MetricThreshold": "tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) * tma_backend_bound", - "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_memory_bound", - "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears", + "MetricExpr": "MACHINE_CLEARS.COUNT * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)", + "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC", + "MetricName": "tma_clears_resteers", + "MetricThreshold": "tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", - "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CLKS, 0)", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l1_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_contested_accesses", + "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", - "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * DTLB_LOAD_MISSES.WALK_COMPLETED) / CLKS", - "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_dtlb_load", - "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS", + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_backend_bound - tma_memory_bound", + "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", - "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_store_fwd_blk", - "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / tma_info_clks", + "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_data_sharing", + "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", - "MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS", - "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_lock_latency", - "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS", + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", + "MetricExpr": "ARITH.FPU_DIV_ACTIVE / tma_info_core_clks", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_divider", + "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", - "MetricExpr": "Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_split_loads", - "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS", + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", + "MetricConstraint": "NO_GROUP_EVENTS_SMT", + "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_dram_bound", + "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", - "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_4k_aliasing", - "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", + "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / tma_info_core_clks / 2", + "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_dsb", + "MetricThreshold": "tma_dsb > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", - "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / CLKS", - "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_fb_full", - "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_clks", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_dsb_switches", + "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l2_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS", + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", + "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * DTLB_LOAD_MISSES.WALK_COMPLETED) / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group", + "MetricName": "tma_dtlb_load", + "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", - "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l3_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", + "MetricExpr": "(8 * DTLB_STORE_MISSES.STLB_HIT + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * DTLB_STORE_MISSES.WALK_COMPLETED) / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group", + "MetricName": "tma_dtlb_store", + "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", - "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / CLKS", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_contested_accesses", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_info_load_miss_real_latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / tma_info_clks", + "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricName": "tma_fb_full", + "MetricThreshold": "tma_fb_full > 0.3", + "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", - "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_data_sharing", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", + "MetricExpr": "tma_frontend_bound - tma_fetch_latency", + "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", + "MetricName": "tma_fetch_bandwidth", + "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", - "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS", - "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_l3_hit_latency", - "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", + "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / tma_info_slots", + "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_latency", + "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", - "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_sq_full", - "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.", + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", + "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", + "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_fp_arith", + "MetricThreshold": "tma_fp_arith > 0.2 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", - "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / CLKS", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_dram_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS", + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", + "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_scalar", + "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group", - "MetricName": "tma_mem_bandwidth", - "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", + "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@ / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_vector", + "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group", - "MetricName": "tma_mem_latency", - "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_128b", + "MetricThreshold": "tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", - "MetricExpr": "RESOURCE_STALLS.SB / CLKS", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_store_bound", - "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS", + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_256b", + "MetricThreshold": "tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", - "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group", - "MetricName": "tma_store_latency", - "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_slots", + "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.15", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents rate of split store accesses", - "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / CORE_CLKS", - "MetricGroup": "TopdownL4;tma_store_bound_group", - "MetricName": "tma_split_stores", - "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences", + "MetricExpr": "tma_microcode_sequencer", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_heavy_operations", + "MetricThreshold": "tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", - "MetricExpr": "(8 * DTLB_STORE_MISSES.STLB_HIT + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * DTLB_STORE_MISSES.WALK_COMPLETED) / CLKS", - "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group", - "MetricName": "tma_dtlb_store", - "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses", + "MetricExpr": "ICACHE.IFDATA_STALL / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_icache_misses", + "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", - "MetricExpr": "tma_backend_bound - tma_memory_bound", - "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_core_bound", - "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", - "ScaleUnit": "100%" + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "tma_info_turbo_utilization * TSC / 1e9 / duration_time", + "MetricGroup": "Power;Summary", + "MetricName": "tma_info_average_frequency" }, { - "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", - "MetricExpr": "ARITH.FPU_DIV_ACTIVE / CORE_CLKS", - "MetricGroup": "TopdownL3;tma_core_bound_group", - "MetricName": "tma_divider", - "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE", - "ScaleUnit": "100%" + "BriefDescription": "Branch instructions per taken branch.", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_bptkbranch" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", - "MetricExpr": "((CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CLKS", - "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group", - "MetricName": "tma_ports_utilization", - "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", - "ScaleUnit": "100%" + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_slots / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts;tma_issueBM", + "MetricName": "tma_info_branch_misprediction_cost", + "PublicDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_branch_mispredicts, tma_mispredicts_resteers" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) / CORE_CLKS)", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_0", - "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", - "ScaleUnit": "100%" + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline", + "MetricName": "tma_info_clks" }, { - "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS)", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_1", - "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL", - "ScaleUnit": "100%" + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else tma_info_clks))", + "MetricGroup": "SMT", + "MetricName": "tma_info_core_clks" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS)", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_2", - "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL", - "ScaleUnit": "100%" + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_core_clks", + "MetricGroup": "Ret;SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_coreipc" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_3m", - "PublicDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3", - "ScaleUnit": "100%" + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / tma_info_ipc", + "MetricGroup": "Mem;Pipeline", + "MetricName": "tma_info_cpi" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_alu_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "HPC;Summary", + "MetricName": "tma_info_cpu_utilization" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) Sample with: UOPS_DISPATCHED.PORT_0", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS", - "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_0", - "ScaleUnit": "100%" + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_data_l2_mlp" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHED.PORT_1", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_1", - "ScaleUnit": "100%" + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1e6 / duration_time / 1e3", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;tma_issueBW", + "MetricName": "tma_info_dram_bw_use", + "PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_mem_bandwidth, tma_sq_full" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_5", - "ScaleUnit": "100%" - }, + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", + "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", + "MetricName": "tma_info_dsb_coverage", + "MetricThreshold": "tma_info_dsb_coverage < 0.7 & tma_info_ipc / 4 > 0.35", + "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_iptb, tma_lcp" + }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) Sample with: UOPS_DISPATCHED.PORT_6", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_6", - "ScaleUnit": "100%" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-thread", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "tma_info_execute" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations Sample with: UOPS_DISPATCHED.PORT_2_3_10", - "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_load_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "tma_info_execute_per_issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_load_op_utilization_group", - "MetricName": "tma_port_2", - "ScaleUnit": "100%" + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / tma_info_core_clks", + "MetricGroup": "Flops;Ret", + "MetricName": "tma_info_flopc" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_load_op_utilization_group", - "MetricName": "tma_port_3", - "ScaleUnit": "100%" + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", + "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@) / (2 * tma_info_core_clks)", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_fp_arith_utilization", + "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations Sample with: UOPS_DISPATCHED.PORT_7_8", - "MetricExpr": "tma_port_4", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_store_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Giga Floating Point Operations Per Second", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_gflops", + "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_store_op_utilization_group", - "MetricName": "tma_port_4", - "ScaleUnit": "100%" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", + "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", + "MetricName": "tma_info_ilp" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_store_op_utilization_group", - "MetricName": "tma_port_7", - "ScaleUnit": "100%" + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;tma_L1_group", + "MetricName": "tma_info_instructions", + "PublicDescription": "Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST" }, { - "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_iparith", + "MetricThreshold": "tma_info_iparith < 10", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", - "MetricExpr": "tma_retiring - tma_heavy_operations", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_light_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx128", + "MetricThreshold": "tma_info_iparith_avx128 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", - "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", - "MetricGroup": "HPC;TopdownL3;tma_light_operations_group", - "MetricName": "tma_fp_arith", - "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx256", + "MetricThreshold": "tma_info_iparith_avx256 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "This metric serves as an approximation of legacy x87 usage", - "MetricExpr": "INST_RETIRED.X87 * UPI / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_x87_use", - "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_iparith_scalar_dp", + "MetricThreshold": "tma_info_iparith_scalar_dp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_fp_scalar", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_iparith_scalar_sp", + "MetricThreshold": "tma_info_iparith_scalar_sp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", - "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_fp_vector", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "tma_info_ipbranch", + "MetricThreshold": "tma_info_ipbranch < 8" }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", - "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group", - "MetricName": "tma_fp_vector_128b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_clks", + "MetricGroup": "Ret;Summary", + "MetricName": "tma_info_ipc" }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", - "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group", - "MetricName": "tma_fp_vector_256b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_ipcall", + "MetricThreshold": "tma_info_ipcall < 200" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences", - "MetricExpr": "tma_microcode_sequencer", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_heavy_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "tma_info_ipfarbranch", + "MetricThreshold": "tma_info_ipfarbranch < 1e6" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS", - "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group", - "MetricName": "tma_microcode_sequencer", - "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_ipflop", + "MetricThreshold": "tma_info_ipflop < 10" }, { - "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", - "MetricExpr": "100 * OTHER_ASSISTS.ANY_WB_ASSIST / SLOTS", - "MetricGroup": "TopdownL4;tma_microcode_sequencer_group", - "MetricName": "tma_assists", - "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipload", + "MetricThreshold": "tma_info_ipload < 3" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", - "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", - "MetricGroup": "TopdownL4;tma_microcode_sequencer_group", - "MetricName": "tma_cisc", - "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "tma_info_instructions / (UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * cpu@BR_MISP_EXEC.ALL_BRANCHES\\,umask\\=0xE4@)", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_indirect", + "MetricThreshold": "tma_info_ipmisp_indirect < 1e3" }, { - "BriefDescription": "Instructions Per Cycle (per Logical Processor)", - "MetricExpr": "INST_RETIRED.ANY / CLKS", - "MetricGroup": "Ret;Summary", - "MetricName": "IPC" + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "tma_info_ipmispredict", + "MetricThreshold": "tma_info_ipmispredict < 200" }, { - "BriefDescription": "Uops Per Instruction", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Ret;Retire", - "MetricName": "UPI" + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipstore", + "MetricThreshold": "tma_info_ipstore < 8" }, { "BriefDescription": "Instruction per taken branch", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW", - "MetricName": "UpTB" + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", + "MetricName": "tma_info_iptb", + "MetricThreshold": "tma_info_iptb < 9", + "PublicDescription": "Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_lcp" }, { - "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / IPC", - "MetricGroup": "Mem;Pipeline", - "MetricName": "CPI" + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "tma_info_instructions / BACLEARS.ANY", + "MetricGroup": "Fed", + "MetricName": "tma_info_ipunknown_branch" }, { - "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Pipeline", - "MetricName": "CLKS" + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_cpi" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", - "MetricExpr": "4 * CORE_CLKS", - "MetricGroup": "tma_L1_group", - "MetricName": "SLOTS" + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_utilization", + "MetricThreshold": "tma_info_kernel_utilization > 0.05" }, { - "BriefDescription": "The ratio of Executed- by Issued-Uops", - "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", - "MetricGroup": "Cor;Pipeline", - "MetricName": "Execute_per_Issue", - "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw" }, { - "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS", - "MetricGroup": "Ret;SMT;tma_L1_group", - "MetricName": "CoreIPC" + "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "tma_info_l1d_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw_1t" }, { - "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS", - "MetricGroup": "Flops;Ret", - "MetricName": "FLOPc" + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l1mpki" }, { - "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "FP_Arith_Utilization", - "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw" }, { - "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", - "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", - "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", - "MetricName": "ILP" + "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "tma_info_l2_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw_1t" }, { - "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", - "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))", - "MetricGroup": "SMT", - "MetricName": "CORE_CLKS" + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2hpki_all" }, { - "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricGroup": "InsType", - "MetricName": "IpLoad" + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2hpki_load" }, { - "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", - "MetricGroup": "InsType", - "MetricName": "IpStore" + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Backend;CacheMisses;Mem", + "MetricName": "tma_info_l2mpki" }, { - "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Fed;InsType", - "MetricName": "IpBranch" + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem;Offcore", + "MetricName": "tma_info_l2mpki_all" }, { - "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "IpCall" + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2mpki_load" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", - "MetricName": "IpTB" + "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "0", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_l3_cache_access_bw_1t" }, { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "BpTkBranch" + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw" }, { - "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", - "MetricGroup": "Flops;InsType", - "MetricName": "IpFLOP" + "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_l3_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw_1t" }, { - "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))", - "MetricGroup": "Flops;InsType", - "MetricName": "IpArith", - "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l3mpki" }, { - "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", - "MetricGroup": "Flops;FpScalar;InsType", - "MetricName": "IpArith_Scalar_SP", - "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore", + "MetricName": "tma_info_load_l2_miss_latency" }, { - "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", - "MetricGroup": "Flops;FpScalar;InsType", - "MetricName": "IpArith_Scalar_DP", - "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_load_l2_mlp" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX128", - "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "tma_info_load_miss_real_latency" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX256", - "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBW;MemoryBound", + "MetricName": "tma_info_mlp", + "PublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)" }, { - "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary;tma_L1_group", - "MetricName": "Instructions" + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "(cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * (DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED)) / tma_info_core_clks", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_page_walks_utilization", + "MetricThreshold": "tma_info_page_walks_utilization > 0.5" }, { "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@", "MetricGroup": "Pipeline;Ret", - "MetricName": "Retire" + "MetricName": "tma_info_retire" }, { - "BriefDescription": "", - "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", - "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", - "MetricName": "Execute" + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * tma_info_core_clks", + "MetricGroup": "TmaL1;tma_L1_group", + "MetricName": "tma_info_slots" }, { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "DSB;Fed;FetchBW", - "MetricName": "DSB_Coverage" + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", + "MetricGroup": "SMT", + "MetricName": "tma_info_smt_2t_utilization" }, { - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "tma_info_clks / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power", + "MetricName": "tma_info_turbo_utilization" }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BrMispredicts", - "MetricName": "Branch_Misprediction_Cost" + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire", + "MetricName": "tma_info_uoppi", + "MetricThreshold": "tma_info_uoppi > 1.05" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)", - "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "tma_info_uptb", + "MetricThreshold": "tma_info_uptb < 6" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "Mem;MemoryBW;MemoryBound", - "MetricName": "MLP" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", + "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * ITLB_MISSES.WALK_COMPLETED) / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI" + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", + "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / tma_info_clks, 0)", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group", + "MetricName": "tma_l1_bound", + "MetricThreshold": "tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Backend;CacheMisses;Mem", - "MetricName": "L2MPKI" + "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l2_bound", + "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem;Offcore", - "MetricName": "L2MPKI_All" + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", + "MetricConstraint": "NO_GROUP_EVENTS_SMT", + "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_MISS / tma_info_clks", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l3_bound", + "MetricThreshold": "tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2MPKI_Load" + "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / tma_info_clks", + "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group", + "MetricName": "tma_l3_hit_latency", + "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_mem_latency", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", - "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2HPKI_All" + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", + "MetricExpr": "ILD_STALL.LCP / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_lcp", + "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_iptb", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2HPKI_Load" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", + "MetricExpr": "tma_retiring - tma_heavy_operations", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_light_operations", + "MetricThreshold": "tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", + "ScaleUnit": "100%" }, { - "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L3MPKI" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_load_op_utilization", + "MetricThreshold": "tma_load_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3_10", + "ScaleUnit": "100%" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * (DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED)) / (2 * CORE_CLKS)", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "Page_Walks_Utilization" + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / tma_info_clks", + "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group", + "MetricName": "tma_lock_latency", + "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", + "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW", + "MetricName": "tma_mem_bandwidth", + "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_sq_full", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_clks - tma_mem_bandwidth", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat", + "MetricName": "tma_mem_latency", + "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_l3_hit_latency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "L1D_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW_1T" + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound", + "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_memory_bound", + "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "L2_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW_1T" + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_slots", + "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS", + "MetricName": "tma_microcode_sequencer", + "MetricThreshold": "tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW_1T" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)", + "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM", + "MetricName": "tma_mispredicts_resteers", + "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_branch_misprediction_cost", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "0", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW_1T" + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", + "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / tma_info_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_mite", + "MetricThreshold": "tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average CPU Utilization", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", - "MetricGroup": "HPC;Summary", - "MetricName": "CPU_Utilization" + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", + "MetricExpr": "2 * IDQ.MS_SWITCHES / tma_info_clks", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", + "MetricName": "tma_ms_switches", + "MetricThreshold": "tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation", + "ScaleUnit": "100%" }, { - "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", - "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time", - "MetricGroup": "Power;Summary", - "MetricName": "Average_Frequency" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / tma_info_core_clks", + "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_0", + "MetricThreshold": "tma_port_0 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs", - "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_1", + "MetricThreshold": "tma_port_1 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average Frequency Utilization relative nominal frequency", - "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC", - "MetricGroup": "Power", - "MetricName": "Turbo_Utilization" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", + "MetricName": "tma_port_2", + "MetricThreshold": "tma_port_2 > 0.6", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", - "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", - "MetricGroup": "SMT", - "MetricName": "SMT_2T_Utilization" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", + "MetricName": "tma_port_3", + "MetricThreshold": "tma_port_3 > 0.6", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "OS", - "MetricName": "Kernel_Utilization" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)", + "MetricExpr": "tma_store_op_utilization", + "MetricGroup": "TopdownL6;tma_L6_group;tma_issueSpSt;tma_store_op_utilization_group", + "MetricName": "tma_port_4", + "MetricThreshold": "tma_port_4 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Related metrics: tma_split_stores", + "ScaleUnit": "100%" }, { - "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", - "MetricGroup": "OS", - "MetricName": "Kernel_CPI" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_5", + "MetricThreshold": "tma_port_5 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", - "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1e6 / duration_time / 1e3", - "MetricGroup": "HPC;Mem;MemoryBW;SoC", - "MetricName": "DRAM_BW_Use" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_6", + "MetricThreshold": "tma_port_6 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", - "MetricGroup": "Branches;OS", - "MetricName": "IpFarBranch" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group", + "MetricName": "tma_port_7", + "MetricThreshold": "tma_port_7 > 0.6", + "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per core", - "MetricExpr": "cstate_core@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Core_Residency", + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_ports_utilization", + "MetricThreshold": "tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per core", - "MetricExpr": "cstate_core@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Core_Residency", + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0)) / tma_info_core_clks)", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_0", + "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per core", - "MetricExpr": "cstate_core@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Core_Residency", + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / tma_info_core_clks)", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_1", + "MetricThreshold": "tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL. Related metrics: tma_l1_bound", "ScaleUnit": "100%" }, { - "BriefDescription": "C2 residency percent per package", - "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C2_Pkg_Residency", + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_clks)", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_2", + "MetricThreshold": "tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6", "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per package", - "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Pkg_Residency", + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_3m", + "MetricThreshold": "tma_ports_utilized_3m > 0.7 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per package", - "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Pkg_Residency", + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per package", - "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Pkg_Residency", + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_info_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_split_loads", + "MetricThreshold": "tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents rate of split store accesses", + "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / tma_info_core_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group", + "MetricName": "tma_split_stores", + "MetricThreshold": "tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", + "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group", + "MetricName": "tma_sq_full", + "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_mem_bandwidth", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", + "MetricExpr": "RESOURCE_STALLS.SB / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_store_bound", + "MetricThreshold": "tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", + "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_store_fwd_blk", + "MetricThreshold": "tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_clks", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group", + "MetricName": "tma_store_latency", + "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / tma_info_core_clks", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_store_op_utilization", + "MetricThreshold": "tma_store_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations. Sample with: UOPS_DISPATCHED.PORT_7_8", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", + "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers", + "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", + "MetricName": "tma_unknown_branches", + "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit). Sample with: FRONTEND_RETIRED.UNKNOWN_BRANCH", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric serves as an approximation of legacy x87 usage", + "MetricExpr": "INST_RETIRED.X87 * tma_info_uoppi / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_x87_use", + "MetricThreshold": "tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", "ScaleUnit": "100%" } ] -- cgit v1.2.3-58-ga151 From 46db21af50510376d7e68116b1bfd2094b38cbc0 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:11 -0800 Subject: perf vendor events intel: Refresh broadwellx metrics Update the broadwellx metrics to TMA version 4.5. Generation was done using https://github.com/intel/perfmon. Notable changes are TMA info metrics are renamed from their node name to be lower case and prefixed by tma_info_, MetricThreshold expressions are added, "Sample with" documentation is added to many TMA metrics, and the smi_cost metric group is added replicating existing hard coded metrics in stat-shadow. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-15-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/x86/broadwellx/bdx-metrics.json | 1626 ++++++++++---------- .../arch/x86/broadwellx/uncore-cache.json | 74 +- .../arch/x86/broadwellx/uncore-interconnect.json | 64 +- .../arch/x86/broadwellx/uncore-other.json | 4 +- 4 files changed, 873 insertions(+), 895 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json b/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json index f5c8f707c692..65ec0c9e55d1 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json @@ -1,1189 +1,1167 @@ [ { - "BriefDescription": "Instructions Per Cycle (per Logical Processor)", - "MetricExpr": "INST_RETIRED.ANY / CLKS", - "MetricGroup": "Ret;Summary", - "MetricName": "IPC" - }, - { - "BriefDescription": "Uops Per Instruction", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Ret;Retire", - "MetricName": "UPI" - }, - { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW", - "MetricName": "UpTB" - }, - { - "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / IPC", - "MetricGroup": "Mem;Pipeline", - "MetricName": "CPI" - }, - { - "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Pipeline", - "MetricName": "CLKS" - }, - { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", - "MetricExpr": "4 * CORE_CLKS", - "MetricGroup": "tma_L1_group", - "MetricName": "SLOTS" - }, - { - "BriefDescription": "The ratio of Executed- by Issued-Uops", - "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", - "MetricGroup": "Cor;Pipeline", - "MetricName": "Execute_per_Issue", - "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." - }, - { - "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS", - "MetricGroup": "Ret;SMT;tma_L1_group", - "MetricName": "CoreIPC" - }, - { - "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS", - "MetricGroup": "Flops;Ret", - "MetricName": "FLOPc" + "BriefDescription": "C2 residency percent per package", + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C2_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "FP_Arith_Utilization", - "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." + "BriefDescription": "C3 residency percent per core", + "MetricExpr": "cstate_core@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Core_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", - "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", - "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", - "MetricName": "ILP" + "BriefDescription": "C3 residency percent per package", + "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", - "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))", - "MetricGroup": "SMT", - "MetricName": "CORE_CLKS" + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricGroup": "InsType", - "MetricName": "IpLoad" + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", - "MetricGroup": "InsType", - "MetricName": "IpStore" + "BriefDescription": "C7 residency percent per core", + "MetricExpr": "cstate_core@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Core_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Fed;InsType", - "MetricName": "IpBranch" + "BriefDescription": "C7 residency percent per package", + "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "IpCall" + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "tma_info_socket_clks / #num_dies / duration_time / 1e9", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", - "MetricName": "IpTB" + "BriefDescription": "Percentage of cycles spent in System Management Interrupts.", + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", + "MetricGroup": "smi", + "MetricName": "smi_cycles", + "MetricThreshold": "smi_cycles > 0.1", + "ScaleUnit": "100%" }, { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "BpTkBranch" + "BriefDescription": "Number of SMI interrupts.", + "MetricExpr": "msr@smi@", + "MetricGroup": "smi", + "MetricName": "smi_num", + "ScaleUnit": "1SMI#" }, { - "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", - "MetricGroup": "Flops;InsType", - "MetricName": "IpFLOP" + "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", + "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_4k_aliasing", + "MetricThreshold": "tma_4k_aliasing > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))", - "MetricGroup": "Flops;InsType", - "MetricName": "IpArith", - "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / tma_info_slots", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_alu_op_utilization", + "MetricThreshold": "tma_alu_op_utilization > 0.6", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", - "MetricGroup": "Flops;FpScalar;InsType", - "MetricName": "IpArith_Scalar_SP", - "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", + "MetricExpr": "100 * OTHER_ASSISTS.ANY_WB_ASSIST / tma_info_slots", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_assists", + "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", - "MetricGroup": "Flops;FpScalar;InsType", - "MetricName": "IpArith_Scalar_DP", - "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_backend_bound", + "MetricThreshold": "tma_backend_bound > 0.2", + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX128", - "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", + "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_bad_speculation", + "MetricThreshold": "tma_bad_speculation > 0.15", + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX256", - "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", + "MetricName": "tma_branch_mispredicts", + "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_mispredicts_resteers", + "ScaleUnit": "100%" }, { - "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary;tma_L1_group", - "MetricName": "Instructions" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", + "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_branch_resteers", + "MetricThreshold": "tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@", - "MetricGroup": "Pipeline;Ret", - "MetricName": "Retire" + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_cisc", + "MetricThreshold": "tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", + "ScaleUnit": "100%" }, { - "BriefDescription": "", - "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", - "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", - "MetricName": "Execute" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears", + "MetricExpr": "MACHINE_CLEARS.COUNT * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)", + "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC", + "MetricName": "tma_clears_resteers", + "MetricThreshold": "tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "DSB;Fed;FetchBW", - "MetricName": "DSB_Coverage" + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_contested_accesses", + "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_backend_bound - tma_memory_bound", + "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BrMispredicts", - "MetricName": "Branch_Misprediction_Cost" + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / tma_info_clks", + "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_data_sharing", + "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)", - "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency" + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", + "MetricExpr": "ARITH.FPU_DIV_ACTIVE / tma_info_core_clks", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_divider", + "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "Mem;MemoryBW;MemoryBound", - "MetricName": "MLP" + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", + "MetricConstraint": "NO_GROUP_EVENTS_SMT", + "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_dram_bound", + "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI" + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", + "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / tma_info_core_clks / 2", + "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_dsb", + "MetricThreshold": "tma_dsb > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Backend;CacheMisses;Mem", - "MetricName": "L2MPKI" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_clks", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_dsb_switches", + "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Related metrics: tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem;Offcore", - "MetricName": "L2MPKI_All" + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", + "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * DTLB_LOAD_MISSES.WALK_COMPLETED) / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group", + "MetricName": "tma_dtlb_load", + "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2MPKI_Load" + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", + "MetricExpr": "(8 * DTLB_STORE_MISSES.STLB_HIT + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * DTLB_STORE_MISSES.WALK_COMPLETED) / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group", + "MetricName": "tma_dtlb_store", + "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", - "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2HPKI_All" + "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", + "MetricExpr": "(200 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE) / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group", + "MetricName": "tma_false_sharing", + "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2HPKI_Load" + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_info_load_miss_real_latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / tma_info_clks", + "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricName": "tma_fb_full", + "MetricThreshold": "tma_fb_full > 0.3", + "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", + "ScaleUnit": "100%" }, { - "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L3MPKI" + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", + "MetricExpr": "tma_frontend_bound - tma_fetch_latency", + "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", + "MetricName": "tma_fetch_bandwidth", + "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", + "ScaleUnit": "100%" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * (DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED)) / (2 * CORE_CLKS)", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "Page_Walks_Utilization" + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", + "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / tma_info_slots", + "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_latency", + "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", + "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", + "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_fp_arith", + "MetricThreshold": "tma_fp_arith > 0.2 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", + "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_scalar", + "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", + "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@ / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_vector", + "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "L1D_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW_1T" + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_128b", + "MetricThreshold": "tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "L2_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW_1T" + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_256b", + "MetricThreshold": "tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW_1T" + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_slots", + "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.15", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "0", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW_1T" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences", + "MetricExpr": "tma_microcode_sequencer", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_heavy_operations", + "MetricThreshold": "tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average CPU Utilization", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", - "MetricGroup": "HPC;Summary", - "MetricName": "CPU_Utilization" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", + "MetricExpr": "ICACHE.IFDATA_STALL / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_icache_misses", + "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "ScaleUnit": "100%" }, { "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", - "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time", + "MetricExpr": "tma_info_turbo_utilization * TSC / 1e9 / duration_time", "MetricGroup": "Power;Summary", - "MetricName": "Average_Frequency" + "MetricName": "tma_info_average_frequency" }, { - "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs", - "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." - }, - { - "BriefDescription": "Average Frequency Utilization relative nominal frequency", - "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC", - "MetricGroup": "Power", - "MetricName": "Turbo_Utilization" - }, - { - "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", - "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", - "MetricGroup": "SMT", - "MetricName": "SMT_2T_Utilization" - }, - { - "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "OS", - "MetricName": "Kernel_Utilization" - }, - { - "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", - "MetricGroup": "OS", - "MetricName": "Kernel_CPI" - }, - { - "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", - "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time", - "MetricGroup": "HPC;Mem;MemoryBW;SoC", - "MetricName": "DRAM_BW_Use" + "BriefDescription": "Branch instructions per taken branch.", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_bptkbranch" }, { - "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches", - "MetricExpr": "1e9 * (UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_INSERTS.MISS_OPCODE@filter_opc\\=0x182@) / (Socket_CLKS / duration_time)", - "MetricGroup": "Mem;MemoryLat;SoC", - "MetricName": "MEM_Read_Latency" + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_slots / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts;tma_issueBM", + "MetricName": "tma_info_branch_misprediction_cost", + "PublicDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_branch_mispredicts, tma_mispredicts_resteers" }, { - "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", - "MetricExpr": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182\\,thresh\\=1@", - "MetricGroup": "Mem;MemoryBW;SoC", - "MetricName": "MEM_Parallel_Reads" + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline", + "MetricName": "tma_info_clks" }, { - "BriefDescription": "Socket actual clocks when any core is active on that socket", - "MetricExpr": "cbox_0@event\\=0x0@", - "MetricGroup": "SoC", - "MetricName": "Socket_CLKS" + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else tma_info_clks))", + "MetricGroup": "SMT", + "MetricName": "tma_info_core_clks" }, { - "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", - "MetricGroup": "Branches;OS", - "MetricName": "IpFarBranch" + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_core_clks", + "MetricGroup": "Ret;SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_coreipc" }, { - "BriefDescription": "Uncore frequency per die [GHZ]", - "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9", - "MetricGroup": "SoC", - "MetricName": "UNCORE_FREQ" + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / tma_info_ipc", + "MetricGroup": "Mem;Pipeline", + "MetricName": "tma_info_cpi" }, { - "BriefDescription": "CPU operating frequency (in GHz)", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / duration_time", - "MetricName": "cpu_operating_frequency", - "ScaleUnit": "1GHz" + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "HPC;Summary", + "MetricName": "tma_info_cpu_utilization" }, { - "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY", - "MetricName": "cpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_data_l2_mlp" }, { - "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions", - "MetricExpr": "MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY", - "MetricName": "loads_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;tma_issueBW", + "MetricName": "tma_info_dram_bw_use", + "PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_mem_bandwidth, tma_sq_full" }, { - "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions", - "MetricExpr": "MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY", - "MetricName": "stores_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", + "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", + "MetricName": "tma_info_dsb_coverage", + "MetricThreshold": "tma_info_dsb_coverage < 0.7 & tma_info_ipc / 4 > 0.35", + "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_iptb, tma_lcp" }, { - "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions", - "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY", - "MetricName": "l1d_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-thread", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "tma_info_execute" }, { - "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions", - "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L1_HIT / INST_RETIRED.ANY", - "MetricName": "l1d_demand_data_read_hits_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "tma_info_execute_per_issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." }, { - "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions", - "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY", - "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / tma_info_core_clks", + "MetricGroup": "Flops;Ret", + "MetricName": "tma_info_flopc" }, { - "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions", - "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_HIT / INST_RETIRED.ANY", - "MetricName": "l2_demand_data_read_hits_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", + "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@) / (2 * tma_info_core_clks)", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_fp_arith_utilization", + "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." }, { - "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions", - "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY", - "MetricName": "l2_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Giga Floating Point Operations Per Second", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_gflops", + "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." }, { - "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions", - "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricName": "l2_demand_data_read_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", + "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", + "MetricName": "tma_info_ilp" }, { - "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions", - "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", - "MetricName": "l2_demand_code_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;tma_L1_group", + "MetricName": "tma_info_instructions", + "PublicDescription": "Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST" }, { - "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", - "MetricExpr": "(cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x192@) / INST_RETIRED.ANY", - "MetricName": "llc_data_read_mpi_demand_plus_prefetch", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_iparith", + "MetricThreshold": "tma_info_iparith < 10", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." }, { - "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", - "MetricExpr": "(cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x181@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x191@) / INST_RETIRED.ANY", - "MetricName": "llc_code_read_mpi_demand_plus_prefetch", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx128", + "MetricThreshold": "tma_info_iparith_avx128 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds", - "MetricExpr": "1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time", - "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency", - "ScaleUnit": "1ns" + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx256", + "MetricThreshold": "tma_info_iparith_avx256 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds", - "MetricExpr": "1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time", - "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests", - "ScaleUnit": "1ns" + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_iparith_scalar_dp", + "MetricThreshold": "tma_info_iparith_scalar_dp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds", - "MetricExpr": "1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time", - "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests", - "ScaleUnit": "1ns" + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_iparith_scalar_sp", + "MetricThreshold": "tma_info_iparith_scalar_sp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions", - "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", - "MetricName": "itlb_mpi", - "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "tma_info_ipbranch", + "MetricThreshold": "tma_info_ipbranch < 8" }, { - "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions", - "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY", - "MetricName": "itlb_large_page_mpi", - "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_clks", + "MetricGroup": "Ret;Summary", + "MetricName": "tma_info_ipc" }, { - "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions", - "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", - "MetricName": "dtlb_load_mpi", - "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_ipcall", + "MetricThreshold": "tma_info_ipcall < 200" }, { - "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions", - "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", - "MetricName": "dtlb_store_mpi", - "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "tma_info_ipfarbranch", + "MetricThreshold": "tma_info_ipfarbranch < 1e6" }, { - "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", - "MetricExpr": "cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / (cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@)", - "MetricName": "numa_reads_addressed_to_local_dram", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_ipflop", + "MetricThreshold": "tma_info_ipflop < 10" }, { - "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", - "MetricExpr": "cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / (cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@)", - "MetricName": "numa_reads_addressed_to_remote_dram", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipload", + "MetricThreshold": "tma_info_ipload < 3" }, { - "BriefDescription": "Uncore operating frequency in GHz", - "MetricExpr": "UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages) / 1e9 / duration_time", - "MetricName": "uncore_frequency", - "ScaleUnit": "1GHz" + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "tma_info_instructions / (UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * cpu@BR_MISP_EXEC.ALL_BRANCHES\\,umask\\=0xE4@)", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_indirect", + "MetricThreshold": "tma_info_ipmisp_indirect < 1e3" }, { - "BriefDescription": "Intel(R) Quick Path Interconnect (QPI) data transmit bandwidth (MB/sec)", - "MetricExpr": "UNC_Q_TxL_FLITS_G0.DATA * 8 / 1e6 / duration_time", - "MetricName": "qpi_data_transmit_bw", - "ScaleUnit": "1MB/s" + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "tma_info_ipmispredict", + "MetricThreshold": "tma_info_ipmispredict < 200" }, { - "BriefDescription": "DDR memory read bandwidth (MB/sec)", - "MetricExpr": "UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time", - "MetricName": "memory_bandwidth_read", - "ScaleUnit": "1MB/s" + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipstore", + "MetricThreshold": "tma_info_ipstore < 8" }, { - "BriefDescription": "DDR memory write bandwidth (MB/sec)", - "MetricExpr": "UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time", - "MetricName": "memory_bandwidth_write", - "ScaleUnit": "1MB/s" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", + "MetricName": "tma_info_iptb", + "MetricThreshold": "tma_info_iptb < 9", + "PublicDescription": "Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_lcp" }, { - "BriefDescription": "DDR memory bandwidth (MB/sec)", - "MetricExpr": "(UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e6 / duration_time", - "MetricName": "memory_bandwidth_total", - "ScaleUnit": "1MB/s" + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "tma_info_instructions / BACLEARS.ANY", + "MetricGroup": "Fed", + "MetricName": "tma_info_ipunknown_branch" }, { - "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.", - "MetricExpr": "cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x19e@ * 64 / 1e6 / duration_time", - "MetricName": "io_bandwidth_disk_or_network_writes", - "ScaleUnit": "1MB/s" + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_cpi" }, { - "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.", - "MetricExpr": "(cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x1c8\\,filter_tid\\=0x3e@ + cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x180\\,filter_tid\\=0x3e@) * 64 / 1e6 / duration_time", - "MetricName": "io_bandwidth_disk_or_network_reads", - "ScaleUnit": "1MB/s" + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_utilization", + "MetricThreshold": "tma_info_kernel_utilization > 0.05" }, { - "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue", - "MetricExpr": "IDQ.DSB_UOPS / UOPS_ISSUED.ANY", - "MetricName": "percent_uops_delivered_from_decoded_icache", - "ScaleUnit": "100%" + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw" }, { - "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue", - "MetricExpr": "IDQ.MITE_UOPS / UOPS_ISSUED.ANY", - "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline", - "ScaleUnit": "100%" + "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "tma_info_l1d_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw_1t" }, { - "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue", - "MetricExpr": "IDQ.MS_UOPS / UOPS_ISSUED.ANY", - "MetricName": "percent_uops_delivered_from_microcode_sequencer", - "ScaleUnit": "100%" + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l1mpki" }, { - "BriefDescription": "Uops delivered from loop stream detector(LSD) as a percent of total uops delivered to Instruction Decode Queue", - "MetricExpr": "LSD.UOPS / UOPS_ISSUED.ANY", - "MetricName": "percent_uops_delivered_from_loop_stream_detector", - "ScaleUnit": "100%" + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw" }, { - "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", - "MetricGroup": "PGO;TopdownL1;tma_L1_group;tma_L1_group", - "MetricName": "tma_frontend_bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", - "ScaleUnit": "100%" + "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "tma_info_l2_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw_1t" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", - "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS", - "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_latency", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.", - "ScaleUnit": "100%" + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2hpki_all" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", - "MetricExpr": "ICACHE.IFDATA_STALL / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_icache_misses", - "ScaleUnit": "100%" + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2hpki_load" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.", - "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=0x1@ + 7 * ITLB_MISSES.WALK_COMPLETED) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_itlb_misses", - "ScaleUnit": "100%" + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Backend;CacheMisses;Mem", + "MetricName": "tma_info_l2mpki" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", - "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_branch_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.", - "ScaleUnit": "100%" + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem;Offcore", + "MetricName": "tma_info_l2mpki_all" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group", - "MetricName": "tma_mispredicts_resteers", - "ScaleUnit": "100%" + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2mpki_load" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ", - "MetricExpr": "MACHINE_CLEARS.COUNT * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)", - "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group", - "MetricName": "tma_clears_resteers", - "ScaleUnit": "100%" + "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "0", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_l3_cache_access_bw_1t" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", - "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers", - "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", - "MetricName": "tma_unknown_branches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit).", - "ScaleUnit": "100%" + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_dsb_switches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", - "ScaleUnit": "100%" + "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_l3_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw_1t" }, { - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", - "MetricExpr": "ILD_STALL.LCP / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_lcp", - "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", - "ScaleUnit": "100%" + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l3mpki" }, { - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", - "MetricExpr": "2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_ms_switches", - "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", - "ScaleUnit": "100%" + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore", + "MetricName": "tma_info_load_l2_miss_latency" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", - "MetricExpr": "tma_frontend_bound - tma_fetch_latency", - "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_bandwidth", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", - "ScaleUnit": "100%" + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_load_l2_mlp" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", - "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2", - "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", - "MetricName": "tma_mite", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", - "ScaleUnit": "100%" + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "tma_info_load_miss_real_latency" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", - "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2", - "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", - "MetricName": "tma_dsb", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", - "ScaleUnit": "100%" + "BriefDescription": "Average number of parallel data read requests to external memory", + "MetricExpr": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182\\,thresh\\=1@", + "MetricGroup": "Mem;MemoryBW;SoC", + "MetricName": "tma_info_mem_parallel_reads", + "PublicDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches" }, { - "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", - "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group", - "MetricName": "tma_bad_speculation", - "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", - "ScaleUnit": "100%" + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds)", + "MetricExpr": "1e9 * (UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_INSERTS.MISS_OPCODE@filter_opc\\=0x182@) / (tma_info_socket_clks / duration_time)", + "MetricGroup": "Mem;MemoryLat;SoC", + "MetricName": "tma_info_mem_read_latency", + "PublicDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_branch_mispredicts", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.", - "ScaleUnit": "100%" + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBW;MemoryBound", + "MetricName": "tma_info_mlp", + "PublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", - "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_machine_clears", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", - "ScaleUnit": "100%" + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * (DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED)) / (2 * tma_info_core_clks)", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_page_walks_utilization", + "MetricThreshold": "tma_info_page_walks_utilization > 0.5" }, { - "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", - "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + UOPS_RETIRED.RETIRE_SLOTS / SLOTS)", - "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group", - "MetricName": "tma_backend_bound", - "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", - "ScaleUnit": "100%" + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "tma_info_retire" }, { - "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound", - "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_memory_bound", - "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", - "ScaleUnit": "100%" + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * tma_info_core_clks", + "MetricGroup": "TmaL1;tma_L1_group", + "MetricName": "tma_info_slots" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", - "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CPU_CLK_UNHALTED.THREAD, 0)", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_l1_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", + "MetricGroup": "SMT", + "MetricName": "tma_info_smt_2t_utilization" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", - "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=0x1@ + 7 * DTLB_LOAD_MISSES.WALK_COMPLETED) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_dtlb_load", - "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.", - "ScaleUnit": "100%" + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "cbox_0@event\\=0x0@", + "MetricGroup": "SoC", + "MetricName": "tma_info_socket_clks" }, { - "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", - "MetricExpr": "min(13 * LD_BLOCKS.STORE_FORWARD / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_store_fwd_blk", - "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", - "ScaleUnit": "100%" + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "tma_info_clks / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power", + "MetricName": "tma_info_turbo_utilization" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", - "MetricExpr": "min(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_lock_latency", - "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.", - "ScaleUnit": "100%" + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire", + "MetricName": "tma_info_uoppi", + "MetricThreshold": "tma_info_uoppi > 1.05" }, { - "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ", - "MetricExpr": "min(Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_split_loads", - "ScaleUnit": "100%" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "tma_info_uptb", + "MetricThreshold": "tma_info_uptb < 6" }, { - "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", - "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_4k_aliasing", - "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", + "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * ITLB_MISSES.WALK_COMPLETED) / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", - "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_fb_full", - "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).", + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", + "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / tma_info_clks, 0)", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group", + "MetricName": "tma_l1_bound", + "MetricThreshold": "tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT_PS;MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks", "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.", + "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", - "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_MISS / CPU_CLK_UNHALTED.THREAD", + "MetricConstraint": "NO_GROUP_EVENTS_SMT", + "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_MISS / tma_info_clks", "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l3_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", - "MetricExpr": "min((60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", - "MetricName": "tma_contested_accesses", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", - "MetricExpr": "min(43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", - "MetricName": "tma_data_sharing", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.", + "MetricThreshold": "tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", - "MetricExpr": "min(41 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "41 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / tma_info_clks", + "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", - "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", - "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group", - "MetricName": "tma_sq_full", - "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.", + "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS. Related metrics: tma_mem_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", - "MetricExpr": "min((1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_MISS / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_dram_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.", + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", + "MetricExpr": "ILD_STALL.LCP / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_lcp", + "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_iptb", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group", - "MetricName": "tma_mem_bandwidth", - "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", + "MetricExpr": "tma_retiring - tma_heavy_operations", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_light_operations", + "MetricThreshold": "tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CPU_CLK_UNHALTED.THREAD - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group", - "MetricName": "tma_mem_latency", - "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_load_op_utilization", + "MetricThreshold": "tma_load_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory", - "MetricExpr": "min(200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / tma_info_clks", "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group", "MetricName": "tma_local_dram", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory", - "MetricExpr": "min(310 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_remote_dram", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues", - "MetricExpr": "min((200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_remote_cache", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", - "MetricExpr": "RESOURCE_STALLS.SB / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_store_bound", - "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", - "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_store_latency", - "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", - "MetricExpr": "min((200 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_false_sharing", - "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents rate of split store accesses", - "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / CORE_CLKS", - "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_split_stores", - "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.", + "MetricThreshold": "tma_local_dram > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", - "MetricExpr": "min((8 * DTLB_STORE_MISSES.STLB_HIT + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=0x1@ + 7 * DTLB_STORE_MISSES.WALK_COMPLETED) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_dtlb_store", - "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.", + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / tma_info_clks", + "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group", + "MetricName": "tma_lock_latency", + "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", - "MetricExpr": "tma_backend_bound - tma_memory_bound", - "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_core_bound", - "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", + "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", - "MetricExpr": "ARITH.FPU_DIV_ACTIVE / CORE_CLKS", - "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", - "MetricName": "tma_divider", - "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.", + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW", + "MetricName": "tma_mem_bandwidth", + "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_sq_full", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", - "MetricName": "tma_ports_utilization", - "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_clks - tma_mem_bandwidth", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat", + "MetricName": "tma_mem_latency", + "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_l3_hit_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\=0x1\\,cmask\\=0x1@ / 2 if #SMT_on else CYCLE_ACTIVITY.STALLS_TOTAL - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0)) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_0", - "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + RESOURCE_STALLS.SB) / (CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound", + "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_memory_bound", + "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@) / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_1", - "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_slots", + "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS", + "MetricName": "tma_microcode_sequencer", + "MetricThreshold": "tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@) / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_2", - "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES * tma_branch_resteers / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)", + "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM", + "MetricName": "tma_mispredicts_resteers", + "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Related metrics: tma_branch_mispredicts, tma_info_branch_misprediction_cost", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", - "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_3m", + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", + "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / tma_info_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_mite", + "MetricThreshold": "tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", - "MetricName": "tma_alu_op_utilization", + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", + "MetricExpr": "2 * IDQ.MS_SWITCHES / tma_info_clks", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", + "MetricName": "tma_ms_switches", + "MetricThreshold": "tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS", - "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / tma_info_core_clks", + "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", "MetricName": "tma_port_0", + "MetricThreshold": "tma_port_0 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED_PORT.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", "MetricName": "tma_port_1", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", - "MetricName": "tma_port_5", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", - "MetricName": "tma_port_6", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", - "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", - "MetricName": "tma_load_op_utilization", + "MetricThreshold": "tma_port_1 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / tma_info_core_clks", "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", "MetricName": "tma_port_2", + "MetricThreshold": "tma_port_2 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_2", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / tma_info_core_clks", "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", "MetricName": "tma_port_3", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", - "MetricName": "tma_store_op_utilization", + "MetricThreshold": "tma_port_3 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_3", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)", "MetricExpr": "tma_store_op_utilization", - "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group", + "MetricGroup": "TopdownL6;tma_L6_group;tma_issueSpSt;tma_store_op_utilization_group", "MetricName": "tma_port_4", + "MetricThreshold": "tma_port_4 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Sample with: UOPS_DISPATCHED_PORT.PORT_4. Related metrics: tma_split_stores", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group", - "MetricName": "tma_port_7", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_5", + "MetricThreshold": "tma_port_5 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Sample with: UOPS_DISPATCHED.PORT_5. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group", - "MetricName": "tma_retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_6", + "MetricThreshold": "tma_port_6 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", - "MetricExpr": "tma_retiring - UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group", - "MetricName": "tma_light_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group", + "MetricName": "tma_port_7", + "MetricThreshold": "tma_port_7 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address). Sample with: UOPS_DISPATCHED_PORT.PORT_7", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", - "MetricExpr": "INST_RETIRED.X87 * UPI / UOPS_RETIRED.RETIRE_SLOTS + tma_fp_scalar + tma_fp_vector", - "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_fp_arith", - "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_TOTAL + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB - RESOURCE_STALLS.SB - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_ports_utilization", + "MetricThreshold": "tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric serves as an approximation of legacy x87 usage", - "MetricExpr": "INST_RETIRED.X87 * UPI / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", - "MetricName": "tma_x87_use", - "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (CYCLE_ACTIVITY.STALLS_TOTAL - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0)) / tma_info_core_clks)", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_0", + "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group", - "MetricName": "tma_fp_scalar", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / tma_info_core_clks)", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_1", + "MetricThreshold": "tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Related metrics: tma_l1_bound", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", - "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)", - "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group", - "MetricName": "tma_fp_vector", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_clks)", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_2", + "MetricThreshold": "tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", - "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)", - "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", - "MetricName": "tma_fp_vector_128b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.", + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", + "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_3m", + "MetricThreshold": "tma_ports_utilized_3m > 0.7 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", - "MetricExpr": "min((FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)", - "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", - "MetricName": "tma_fp_vector_256b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / tma_info_clks", + "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_issueSyncxn;tma_mem_latency_group", + "MetricName": "tma_remote_cache", + "MetricThreshold": "tma_remote_cache > 0.05 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group", - "MetricName": "tma_heavy_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "310 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / tma_info_clks", + "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", + "MetricName": "tma_remote_dram", + "MetricThreshold": "tma_remote_dram > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", - "MetricExpr": "tma_heavy_operations", - "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group", - "MetricName": "tma_microcode_sequencer", - "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.", + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", - "MetricExpr": "min(100 * OTHER_ASSISTS.ANY_WB_ASSIST / SLOTS, 1)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", - "MetricName": "tma_assists", - "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.", + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_info_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_split_loads", + "MetricThreshold": "tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_UOPS_RETIRED.SPLIT_LOADS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", - "MetricExpr": "max(0, tma_heavy_operations - tma_assists)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", - "MetricName": "tma_cisc", - "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", + "BriefDescription": "This metric represents rate of split store accesses", + "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / tma_info_core_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group", + "MetricName": "tma_split_stores", + "MetricThreshold": "tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_UOPS_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4", "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per core", - "MetricExpr": "cstate_core@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Core_Residency", + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", + "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group", + "MetricName": "tma_sq_full", + "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_mem_bandwidth", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per core", - "MetricExpr": "cstate_core@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Core_Residency", + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", + "MetricExpr": "RESOURCE_STALLS.SB / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_store_bound", + "MetricThreshold": "tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per core", - "MetricExpr": "cstate_core@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Core_Residency", + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", + "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_store_fwd_blk", + "MetricThreshold": "tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", "ScaleUnit": "100%" }, { - "BriefDescription": "C2 residency percent per package", - "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C2_Pkg_Residency", + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_clks", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group", + "MetricName": "tma_store_latency", + "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per package", - "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Pkg_Residency", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / tma_info_core_clks", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_store_op_utilization", + "MetricThreshold": "tma_store_op_utilization > 0.6", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per package", - "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Pkg_Residency", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", + "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tma_clears_resteers", + "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", + "MetricName": "tma_unknown_branches", + "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit). Sample with: BACLEARS.ANY", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per package", - "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Pkg_Residency", + "BriefDescription": "This metric serves as an approximation of legacy x87 usage", + "MetricExpr": "INST_RETIRED.X87 * tma_info_uoppi / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_x87_use", + "MetricThreshold": "tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", "ScaleUnit": "100%" } ] diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json index 38eaac5afd4b..746954775437 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json @@ -5,7 +5,7 @@ "EventName": "LLC_MISSES.CODE_LLC_PREFETCH", "Filter": "filter_opc=0x191", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -16,7 +16,7 @@ "EventName": "LLC_MISSES.DATA_LLC_PREFETCH", "Filter": "filter_opc=0x192", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -27,7 +27,7 @@ "EventName": "LLC_MISSES.DATA_READ", "Filter": "filter_opc=0x182", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -38,7 +38,7 @@ "EventName": "LLC_MISSES.MMIO_READ", "Filter": "filter_opc=0x187,filter_nc=1", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -49,7 +49,7 @@ "EventName": "LLC_MISSES.MMIO_WRITE", "Filter": "filter_opc=0x18f,filter_nc=1", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -60,7 +60,7 @@ "EventName": "LLC_MISSES.PCIE_NON_SNOOP_WRITE", "Filter": "filter_opc=0x1c8,filter_tid=0x3e", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -71,7 +71,7 @@ "EventName": "LLC_MISSES.PCIE_READ", "Filter": "filter_opc=0x19e", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -82,7 +82,7 @@ "EventName": "LLC_MISSES.PCIE_WRITE", "Filter": "filter_opc=0x1c8", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -93,7 +93,7 @@ "EventName": "LLC_MISSES.RFO_LLC_PREFETCH", "Filter": "filter_opc=0x190", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -104,7 +104,7 @@ "EventName": "LLC_MISSES.UNCACHEABLE", "Filter": "filter_opc=0x187", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -115,7 +115,7 @@ "EventName": "LLC_REFERENCES.CODE_LLC_PREFETCH", "Filter": "filter_opc=0x181", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", "Unit": "CBO" @@ -126,7 +126,7 @@ "EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE", "Filter": "filter_opc=0x180,filter_tid=0x3e", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "UMask": "0x1", "Unit": "CBO" }, @@ -136,7 +136,7 @@ "EventName": "LLC_REFERENCES.PCIE_READ", "Filter": "filter_opc=0x19e", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", "Unit": "CBO" @@ -147,7 +147,7 @@ "EventName": "LLC_REFERENCES.PCIE_WRITE", "Filter": "filter_opc=0x1c8,filter_tid=0x3e", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", "Unit": "CBO" @@ -158,7 +158,7 @@ "EventName": "LLC_REFERENCES.STREAMING_FULL", "Filter": "filter_opc=0x18c", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", "Unit": "CBO" @@ -169,7 +169,7 @@ "EventName": "LLC_REFERENCES.STREAMING_PARTIAL", "Filter": "filter_opc=0x18d", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", "Unit": "CBO" @@ -1157,7 +1157,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.ALL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.", "UMask": "0x8", "Unit": "CBO" }, @@ -1166,7 +1166,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.EVICTION", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Eviction transactions inserted into the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Eviction transactions inserted into the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).", "UMask": "0x4", "Unit": "CBO" }, @@ -1175,7 +1175,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOCAL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisifed by locally HOMed memory.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisifed by locally HOMed memory.", "UMask": "0x28", "Unit": "CBO" }, @@ -1184,7 +1184,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisifed by an opcode, inserted into the TOR that are satisifed by locally HOMed memory.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisifed by an opcode, inserted into the TOR that are satisifed by locally HOMed memory.", "UMask": "0x21", "Unit": "CBO" }, @@ -1193,7 +1193,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by locally HOMed memory.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by locally HOMed memory.", "UMask": "0x2a", "Unit": "CBO" }, @@ -1202,7 +1202,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisifed by an opcode, inserted into the TOR that are satisifed by locally HOMed memory.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisifed by an opcode, inserted into the TOR that are satisifed by locally HOMed memory.", "UMask": "0x23", "Unit": "CBO" }, @@ -1211,7 +1211,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "UMask": "0x3", "Unit": "CBO" }, @@ -1220,7 +1220,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by remote caches or remote memory.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by remote caches or remote memory.", "UMask": "0x8a", "Unit": "CBO" }, @@ -1229,7 +1229,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisifed by an opcode, inserted into the TOR that are satisifed by remote caches or remote memory.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisifed by an opcode, inserted into the TOR that are satisifed by remote caches or remote memory.", "UMask": "0x83", "Unit": "CBO" }, @@ -1238,7 +1238,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_ALL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x48", "Unit": "CBO" }, @@ -1247,7 +1247,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction transactions inserted into the TOR.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction transactions inserted into the TOR.", "UMask": "0x44", "Unit": "CBO" }, @@ -1256,7 +1256,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.", "UMask": "0x4a", "Unit": "CBO" }, @@ -1265,7 +1265,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode.", "UMask": "0x43", "Unit": "CBO" }, @@ -1274,7 +1274,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode.", "UMask": "0x41", "Unit": "CBO" }, @@ -1283,7 +1283,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_WB", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transactions inserted into the TOR.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transactions inserted into the TOR.", "UMask": "0x50", "Unit": "CBO" }, @@ -1292,7 +1292,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "UMask": "0x1", "Unit": "CBO" }, @@ -1301,7 +1301,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.REMOTE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisifed by remote caches or remote memory.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisifed by remote caches or remote memory.", "UMask": "0x88", "Unit": "CBO" }, @@ -1310,7 +1310,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisifed by an opcode, inserted into the TOR that are satisifed by remote caches or remote memory.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisifed by an opcode, inserted into the TOR that are satisifed by remote caches or remote memory.", "UMask": "0x81", "Unit": "CBO" }, @@ -1319,7 +1319,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.WB", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Write transactions inserted into the TOR. This does not include RFO, but actual operations that contain data being sent from the core.", + "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Write transactions inserted into the TOR. This does not include RFO, but actual operations that contain data being sent from the core.", "UMask": "0x10", "Unit": "CBO" }, @@ -1590,7 +1590,7 @@ "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.BL_CORE", "PerPkg": "1", - "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring. This is commonly used for transfering writeback data to the cache.", "UMask": "0x40", "Unit": "CBO" }, @@ -1737,7 +1737,7 @@ "EventCode": "0x41", "EventName": "UNC_H_DIRECTORY_LAT_OPT", "PerPkg": "1", - "PublicDescription": "Directory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory returned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc).", + "PublicDescription": "Directory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory retuned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc).", "Unit": "HA" }, { diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json index a5457c7ba58b..489a3673323d 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json @@ -3,7 +3,7 @@ "BriefDescription": "Number of non data (control) flits transmitted . Derived from unc_q_txl_flits_g0.non_data", "EventName": "QPI_CTL_BANDWIDTH_TX", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets.", "ScaleUnit": "8Bytes", "UMask": "0x4", "Unit": "QPI LL" @@ -12,7 +12,7 @@ "BriefDescription": "Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data", "EventName": "QPI_DATA_BANDWIDTH_TX", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets.", "ScaleUnit": "8Bytes", "UMask": "0x2", "Unit": "QPI LL" @@ -134,7 +134,7 @@ "EventCode": "0x9", "EventName": "UNC_Q_RxL_BYPASSED", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", "Unit": "QPI LL" }, { @@ -391,7 +391,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_RxL_FLITS_G0.IDLE", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits received over QPI that do not hold protocol payload. When QPI is not in a power saving state, it continuously transmits flits across the link. When there are no protocol flits to send, it will send IDLE and NULL flits across. These flits sometimes do carry a payload, such as credit returns, but are generall not considered part of the QPI bandwidth.", + "PublicDescription": "Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits received over QPI that do not hold protocol payload. When QPI is not in a power saving state, it continuously transmits flits across the link. When there are no protocol flits to send, it will send IDLE and NULL flits across. These flits sometimes do carry a payload, such as credit returns, but are generall not considered part of the QPI bandwidth.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -400,7 +400,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.DRS", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data.", "UMask": "0x18", "Unit": "QPI LL" }, @@ -409,7 +409,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).", "UMask": "0x8", "Unit": "QPI LL" }, @@ -418,7 +418,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.", "UMask": "0x10", "Unit": "QPI LL" }, @@ -427,7 +427,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.HOM", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits received over QPI on the home channel.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits received over QPI on the home channel.", "UMask": "0x6", "Unit": "QPI LL" }, @@ -436,7 +436,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits received over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits received over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.", "UMask": "0x4", "Unit": "QPI LL" }, @@ -445,7 +445,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request received over QPI on the home channel. This basically counts the number of remote memory requests received over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request received over QPI on the home channel. This basically counts the number of remote memory requests received over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.", "UMask": "0x2", "Unit": "QPI LL" }, @@ -454,7 +454,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.SNP", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits received over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are received on the home channel.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits received over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are received on the home channel.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -463,7 +463,7 @@ "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCB", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.", "UMask": "0xc", "Unit": "QPI LL" }, @@ -472,7 +472,7 @@ "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers.", "UMask": "0x4", "Unit": "QPI LL" }, @@ -481,7 +481,7 @@ "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.", "UMask": "0x8", "Unit": "QPI LL" }, @@ -490,7 +490,7 @@ "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCS", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits received over QPI. This includes extended headers.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits received over QPI. This includes extended headers.", "UMask": "0x10", "Unit": "QPI LL" }, @@ -499,7 +499,7 @@ "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -508,7 +508,7 @@ "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.", "UMask": "0x2", "Unit": "QPI LL" }, @@ -924,7 +924,7 @@ "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits", "EventName": "UNC_Q_TxL_FLITS_G0.DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets.", "UMask": "0x2", "Unit": "QPI LL" }, @@ -932,7 +932,7 @@ "BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits", "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets.", "UMask": "0x4", "Unit": "QPI LL" }, @@ -940,7 +940,7 @@ "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)", "EventName": "UNC_Q_TxL_FLITS_G1.DRS", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency.", + "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency.", "UMask": "0x18", "Unit": "QPI LL" }, @@ -948,7 +948,7 @@ "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits", "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).", + "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).", "UMask": "0x8", "Unit": "QPI LL" }, @@ -956,7 +956,7 @@ "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits", "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.", + "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.", "UMask": "0x10", "Unit": "QPI LL" }, @@ -964,7 +964,7 @@ "BriefDescription": "Flits Transferred - Group 1; HOM Flits", "EventName": "UNC_Q_TxL_FLITS_G1.HOM", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits transmitted over QPI on the home channel.", + "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits transmitted over QPI on the home channel.", "UMask": "0x6", "Unit": "QPI LL" }, @@ -972,7 +972,7 @@ "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits", "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits transmitted over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.", + "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits transmitted over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.", "UMask": "0x4", "Unit": "QPI LL" }, @@ -980,7 +980,7 @@ "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits", "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request transmitted over QPI on the home channel. This basically counts the number of remote memory requests transmitted over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.", + "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request transmitted over QPI on the home channel. This basically counts the number of remote memory requests transmitted over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.", "UMask": "0x2", "Unit": "QPI LL" }, @@ -988,7 +988,7 @@ "BriefDescription": "Flits Transferred - Group 1; SNP Flits", "EventName": "UNC_Q_TxL_FLITS_G1.SNP", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits transmitted over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are transmitted on the home channel.", + "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits transmitted over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are transmitted on the home channel.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -997,7 +997,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCB", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.", + "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.", "UMask": "0xc", "Unit": "QPI LL" }, @@ -1006,7 +1006,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not te NCB headers.", + "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not te NCB headers.", "UMask": "0x4", "Unit": "QPI LL" }, @@ -1015,7 +1015,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.", + "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.", "UMask": "0x8", "Unit": "QPI LL" }, @@ -1024,7 +1024,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCS", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits transmitted over QPI. This includes extended headers.", + "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits transmitted over QPI. This includes extended headers.", "UMask": "0x10", "Unit": "QPI LL" }, @@ -1033,7 +1033,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.", + "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -1042,7 +1042,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.", + "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.", "UMask": "0x2", "Unit": "QPI LL" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json index 495e34ee5bfb..a80d931dc3d5 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json @@ -2312,7 +2312,7 @@ "EventCode": "0x33", "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD", "PerPkg": "1", - "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", + "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transfered). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transfered in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", "Unit": "R3QPI" }, @@ -2321,7 +2321,7 @@ "EventCode": "0x33", "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL", "PerPkg": "1", - "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", + "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transfered). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transfered in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", "UMask": "0x4", "Unit": "R3QPI" }, -- cgit v1.2.3-58-ga151 From 6635df2f4cde6124accbb909b51961603908950c Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:12 -0800 Subject: perf vendor events intel: Refresh cascadelakex events Update the cascadelakex events from 1.16 to 1.17. Generation was done using https://github.com/intel/perfmon. Notable changes are new events and event descriptions, TMA metrics are updated to version 4.5, TMA info metrics are renamed from their node name to be lower case and prefixed by tma_info_, MetricThreshold expressions are added, "Sample with" documentation is added to many TMA metrics, smi_cost and transaction metric groups are added replicating existing hard coded metrics in stat-shadow. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-16-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/cascadelakex/cache.json | 24 +- .../arch/x86/cascadelakex/clx-metrics.json | 2198 ++++++++++---------- .../pmu-events/arch/x86/cascadelakex/frontend.json | 8 +- .../pmu-events/arch/x86/cascadelakex/pipeline.json | 16 + .../arch/x86/cascadelakex/uncore-memory.json | 18 +- .../arch/x86/cascadelakex/uncore-other.json | 120 +- .../arch/x86/cascadelakex/uncore-power.json | 8 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 8 files changed, 1236 insertions(+), 1158 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json b/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json index 1070ad317ec9..a842f05cb60d 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json @@ -234,20 +234,22 @@ "UMask": "0x4f" }, { - "BriefDescription": "All retired load instructions.", + "BriefDescription": "Retired load instructions.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.ALL_LOADS", "PEBS": "1", + "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.", "SampleAfterValue": "2000003", "UMask": "0x81" }, { - "BriefDescription": "All retired store instructions.", + "BriefDescription": "Retired store instructions.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.ALL_STORES", "PEBS": "1", + "PublicDescription": "Counts all retired store instructions.", "SampleAfterValue": "2000003", "UMask": "0x82" }, @@ -388,12 +390,12 @@ "UMask": "0x4" }, { - "BriefDescription": "Retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches. Precise event.", + "BriefDescription": "Retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.", "Data_LA": "1", "EventCode": "0xD3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM", "PEBS": "1", - "PublicDescription": "Counts retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode). Precise event", + "PublicDescription": "Counts retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode).", "SampleAfterValue": "100007", "UMask": "0x10" }, @@ -477,12 +479,12 @@ "UMask": "0x20" }, { - "BriefDescription": "Retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches. Precise event.", + "BriefDescription": "Retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.LOCAL_PMM", "PEBS": "1", - "PublicDescription": "Counts retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode). Precise event", + "PublicDescription": "Counts retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode).", "SampleAfterValue": "100003", "UMask": "0x80" }, @@ -5039,7 +5041,7 @@ "UMask": "0x80" }, { - "BriefDescription": "Cacheable and noncachaeble code read requests", + "BriefDescription": "Cacheable and non-cacheable code read requests", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "PublicDescription": "Counts both cacheable and non-cacheable code read requests.", @@ -5146,14 +5148,6 @@ "SampleAfterValue": "2000003", "UMask": "0x4" }, - { - "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, { "BriefDescription": "This event is deprecated. Refer to new event OCR.ALL_DATA_RD.ANY_RESPONSE", "Deprecated": "1", diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json b/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json index 356cf6603b69..4e993a3220e3 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json @@ -1,1548 +1,1608 @@ [ { - "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", - "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "Mispredictions" - }, - { - "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks", - "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "Memory_Bandwidth" - }, - { - "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)", - "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound))", - "MetricGroup": "Mem;MemoryLat;Offcore", - "MetricName": "Memory_Latency" - }, - { - "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", - "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency)))", - "MetricGroup": "Mem;MemoryTLB;Offcore", - "MetricName": "Memory_Data_TLBs" - }, - { - "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", - "MetricExpr": "100 * ((BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)", - "MetricGroup": "Ret", - "MetricName": "Branching_Overhead" - }, - { - "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", - "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", - "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB", - "MetricName": "Big_Code" - }, - { - "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", - "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code", - "MetricGroup": "Fed;FetchBW;Frontend", - "MetricName": "Instruction_Fetch_BW" - }, - { - "BriefDescription": "Instructions Per Cycle (per Logical Processor)", - "MetricExpr": "INST_RETIRED.ANY / CLKS", - "MetricGroup": "Ret;Summary", - "MetricName": "IPC" - }, - { - "BriefDescription": "Uops Per Instruction", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Ret;Retire", - "MetricName": "UPI" - }, - { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW", - "MetricName": "UpTB" - }, - { - "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / IPC", - "MetricGroup": "Mem;Pipeline", - "MetricName": "CPI" - }, - { - "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Pipeline", - "MetricName": "CLKS" - }, - { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", - "MetricExpr": "4 * CORE_CLKS", - "MetricGroup": "tma_L1_group", - "MetricName": "SLOTS" - }, - { - "BriefDescription": "The ratio of Executed- by Issued-Uops", - "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", - "MetricGroup": "Cor;Pipeline", - "MetricName": "Execute_per_Issue", - "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." - }, - { - "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS", - "MetricGroup": "Ret;SMT;tma_L1_group", - "MetricName": "CoreIPC" - }, - { - "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS", - "MetricGroup": "Flops;Ret", - "MetricName": "FLOPc" - }, - { - "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "FP_Arith_Utilization", - "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." - }, - { - "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", - "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", - "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", - "MetricName": "ILP" - }, - { - "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", - "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)", - "MetricGroup": "Cor;SMT", - "MetricName": "Core_Bound_Likely" - }, - { - "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", - "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))", - "MetricGroup": "SMT", - "MetricName": "CORE_CLKS" - }, - { - "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", - "MetricGroup": "InsType", - "MetricName": "IpLoad" - }, - { - "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", - "MetricGroup": "InsType", - "MetricName": "IpStore" - }, - { - "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Fed;InsType", - "MetricName": "IpBranch" + "BriefDescription": "C2 residency percent per package", + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C2_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "IpCall" + "BriefDescription": "C3 residency percent per core", + "MetricExpr": "cstate_core@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Core_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", - "MetricName": "IpTB" + "BriefDescription": "C3 residency percent per package", + "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "BpTkBranch" + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)", - "MetricGroup": "Flops;InsType", - "MetricName": "IpFLOP" + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))", - "MetricGroup": "Flops;InsType", - "MetricName": "IpArith", - "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." + "BriefDescription": "C7 residency percent per core", + "MetricExpr": "cstate_core@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Core_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", - "MetricGroup": "Flops;FpScalar;InsType", - "MetricName": "IpArith_Scalar_SP", - "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "C7 residency percent per package", + "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", - "MetricGroup": "Flops;FpScalar;InsType", - "MetricName": "IpArith_Scalar_DP", - "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "tma_info_socket_clks / #num_dies / duration_time / 1e9", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX128", - "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "Percentage of cycles spent in System Management Interrupts.", + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", + "MetricGroup": "smi", + "MetricName": "smi_cycles", + "MetricThreshold": "smi_cycles > 0.1", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX256", - "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "Number of SMI interrupts.", + "MetricExpr": "msr@smi@", + "MetricGroup": "smi", + "MetricName": "smi_num", + "ScaleUnit": "1SMI#" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX512", - "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", + "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_4k_aliasing", + "MetricThreshold": "tma_4k_aliasing > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", - "MetricGroup": "Prefetches", - "MetricName": "IpSWPF" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / tma_info_slots", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_alu_op_utilization", + "MetricThreshold": "tma_alu_op_utilization > 0.6", + "ScaleUnit": "100%" }, { - "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary;tma_L1_group", - "MetricName": "Instructions" + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", + "MetricExpr": "100 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / tma_info_slots", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_assists", + "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@", - "MetricGroup": "Pipeline;Ret", - "MetricName": "Retire" + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", + "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_backend_bound", + "MetricThreshold": "tma_backend_bound > 0.2", + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", + "ScaleUnit": "100%" }, { - "BriefDescription": "", - "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", - "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", - "MetricName": "Execute" + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", + "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_bad_speculation", + "MetricThreshold": "tma_bad_speculation > 0.15", + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of Uops issued by front-end when it issued something", - "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@", - "MetricGroup": "Fed;FetchBW", - "MetricName": "Fetch_UpC" + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", + "MetricName": "tma_branch_mispredicts", + "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredicts_resteers", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "DSB;Fed;FetchBW", - "MetricName": "DSB_Coverage" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", + "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks + tma_unknown_branches", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_branch_resteers", + "MetricThreshold": "tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHES.COUNT", - "MetricGroup": "DSBmiss", - "MetricName": "DSB_Switch_Cost" + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", + "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_cisc", + "MetricThreshold": "tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.", - "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))", - "MetricGroup": "DSBmiss;Fed", - "MetricName": "DSB_Misses" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears", + "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks", + "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC", + "MetricName": "tma_clears_resteers", + "MetricThreshold": "tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches", + "ScaleUnit": "100%" }, { - "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", - "MetricGroup": "DSBmiss;Fed", - "MetricName": "IpDSB_Miss_Ret" + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(44 * tma_info_average_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD))) + 44 * tma_info_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_contested_accesses", + "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_backend_bound - tma_memory_bound", + "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BrMispredicts", - "MetricName": "Branch_Misprediction_Cost" + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "44 * tma_info_average_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_data_sharing", + "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of branches that are non-taken conditionals", - "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches;CodeGen;PGO", - "MetricName": "Cond_NT" + "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", + "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) / tma_info_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_issueD0;tma_mite_group", + "MetricName": "tma_decoder0_alone", + "MetricThreshold": "tma_decoder0_alone > 0.1 & (tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35))", + "PublicDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder. Related metrics: tma_few_uops_instructions", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of branches that are taken conditionals", - "MetricExpr": "(BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches;CodeGen;PGO", - "MetricName": "Cond_TK" + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", + "MetricExpr": "ARITH.DIVIDER_ACTIVE / tma_info_clks", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_divider", + "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of branches that are CALL or RET", - "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches", - "MetricName": "CallRet" + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks - tma_l2_bound - tma_pmm_bound", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_dram_bound", + "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", - "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches", - "MetricName": "Jump" + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", + "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / tma_info_core_clks / 2", + "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_dsb", + "MetricThreshold": "tma_dsb > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)", - "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_clks", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_dsb_switches", + "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", + "ScaleUnit": "100%" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "Mem;MemoryBW;MemoryBound", - "MetricName": "MLP" + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group", + "MetricName": "tma_dtlb_load", + "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store, tma_info_memory_data_tlbs", + "ScaleUnit": "100%" }, { - "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI" + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", + "MetricExpr": "(9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group", + "MetricName": "tma_dtlb_store", + "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, tma_info_memory_data_tlbs", + "ScaleUnit": "100%" }, { - "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI_Load" + "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(110 * tma_info_average_frequency * (OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM + OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM) + 47.5 * tma_info_average_frequency * (OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE)) / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group", + "MetricName": "tma_false_sharing", + "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Backend;CacheMisses;Mem", - "MetricName": "L2MPKI" + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "tma_info_load_miss_real_latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / tma_info_clks", + "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricName": "tma_fb_full", + "MetricThreshold": "tma_fb_full > 0.3", + "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_dram_bw_use, tma_info_memory_bandwidth, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem;Offcore", - "MetricName": "L2MPKI_All" + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", + "MetricExpr": "tma_frontend_bound - tma_fetch_latency", + "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", + "MetricName": "tma_fetch_bandwidth", + "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2MPKI_Load" + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", + "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / tma_info_slots", + "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_latency", + "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", - "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2HPKI_All" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops", + "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer", + "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueD0", + "MetricName": "tma_few_uops_instructions", + "MetricThreshold": "tma_few_uops_instructions > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions. Related metrics: tma_decoder0_alone", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2HPKI_Load" + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", + "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_fp_arith", + "MetricThreshold": "tma_fp_arith > 0.2 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", + "ScaleUnit": "100%" }, { - "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L3MPKI" + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", + "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_scalar", + "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "FB_HPKI" + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_vector", + "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING) / (2 * CORE_CLKS)", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "Page_Walks_Utilization" + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_128b", + "MetricThreshold": "tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_256b", + "MetricThreshold": "tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_512b", + "MetricThreshold": "tma_fp_vector_512b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_slots", + "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.15", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions", + "MetricExpr": "tma_light_operations * UOPS_RETIRED.MACRO_FUSED / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_fused_instructions", + "MetricThreshold": "tma_fused_instructions > 0.1 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)", - "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / Instructions", - "MetricGroup": "L2Evicts;Mem;Server", - "MetricName": "L2_Evictions_Silent_PKI" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences", + "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / tma_info_slots", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_heavy_operations", + "MetricThreshold": "tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction", - "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / Instructions", - "MetricGroup": "L2Evicts;Mem;Server", - "MetricName": "L2_Evictions_NonSilent_PKI" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses", + "MetricExpr": "(ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@) / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_icache_misses", + "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "L1D_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW_1T" + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "tma_info_turbo_utilization * TSC / 1e9 / duration_time", + "MetricGroup": "Power;Summary", + "MetricName": "tma_info_average_frequency" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "L2_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW_1T" + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB;tma_issueBC", + "MetricName": "tma_info_big_code", + "MetricThreshold": "tma_info_big_code > 20", + "PublicDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses). Related metrics: tma_info_branching_overhead" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW_1T" + "BriefDescription": "Branch instructions per taken branch.", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_bptkbranch" }, { - "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Access_BW", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW_1T" + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_slots / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts;tma_issueBM", + "MetricName": "tma_info_branch_misprediction_cost", + "PublicDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_branch_mispredicts, tma_info_mispredictions, tma_mispredicts_resteers" }, { - "BriefDescription": "Average CPU Utilization", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", - "MetricGroup": "HPC;Summary", - "MetricName": "CPU_Utilization" + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "MetricExpr": "100 * ((BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL)) / tma_info_slots)", + "MetricGroup": "Ret;tma_issueBC", + "MetricName": "tma_info_branching_overhead", + "MetricThreshold": "tma_info_branching_overhead > 10", + "PublicDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls). Related metrics: tma_info_big_code" }, { - "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", - "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time", - "MetricGroup": "Power;Summary", - "MetricName": "Average_Frequency" + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_callret" }, { - "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs", - "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline", + "MetricName": "tma_info_clks" }, { - "BriefDescription": "Average Frequency Utilization relative nominal frequency", - "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC", - "MetricGroup": "Power", - "MetricName": "Turbo_Utilization" + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Fed;MemoryTLB", + "MetricName": "tma_info_code_stlb_mpki" }, { - "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0", - "MetricExpr": "(CORE_POWER.LVL0_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL0_TURBO_LICENSE / CORE_CLKS)", - "MetricGroup": "Power", - "MetricName": "Power_License0_Utilization", - "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes." + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "tma_info_cond_nt" }, { - "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1", - "MetricExpr": "(CORE_POWER.LVL1_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL1_TURBO_LICENSE / CORE_CLKS)", - "MetricGroup": "Power", - "MetricName": "Power_License1_Utilization", - "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions." + "BriefDescription": "Fraction of branches that are taken conditionals", + "MetricExpr": "(BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "tma_info_cond_tk" }, { - "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)", - "MetricExpr": "(CORE_POWER.LVL2_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL2_TURBO_LICENSE / CORE_CLKS)", - "MetricGroup": "Power", - "MetricName": "Power_License2_Utilization", - "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions." + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if tma_info_smt_2t_utilization > 0.5 else 0)", + "MetricGroup": "Cor;SMT", + "MetricName": "tma_info_core_bound_likely", + "MetricThreshold": "tma_info_core_bound_likely > 0.5" }, { - "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", - "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else tma_info_clks))", "MetricGroup": "SMT", - "MetricName": "SMT_2T_Utilization" + "MetricName": "tma_info_core_clks" }, { - "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "OS", - "MetricName": "Kernel_Utilization" + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_core_clks", + "MetricGroup": "Ret;SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_coreipc" }, { - "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", - "MetricGroup": "OS", - "MetricName": "Kernel_CPI" + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / tma_info_ipc", + "MetricGroup": "Mem;Pipeline", + "MetricName": "tma_info_cpi" }, { - "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", - "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time", - "MetricGroup": "HPC;Mem;MemoryBW;SoC", - "MetricName": "DRAM_BW_Use" + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "HPC;Summary", + "MetricName": "tma_info_cpu_utilization" }, { - "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches", - "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (Socket_CLKS / duration_time)", - "MetricGroup": "Mem;MemoryLat;SoC", - "MetricName": "MEM_Read_Latency" + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_data_l2_mlp" }, { - "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", - "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@thresh\\=1@", - "MetricGroup": "Mem;MemoryBW;SoC", - "MetricName": "MEM_Parallel_Reads" + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;tma_issueBW", + "MetricName": "tma_info_dram_bw_use", + "PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_info_memory_bandwidth, tma_mem_bandwidth, tma_sq_full" }, { - "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", - "MetricExpr": "1e9 * (UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS) / imc_0@event\\=0x0@", - "MetricGroup": "Mem;MemoryLat;Server;SoC", - "MetricName": "MEM_PMM_Read_Latency" + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", + "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", + "MetricName": "tma_info_dsb_coverage", + "MetricThreshold": "tma_info_dsb_coverage < 0.7 & tma_info_ipc / 4 > 0.35", + "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_misses, tma_info_iptb, tma_lcp" }, { - "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", - "MetricExpr": "1e9 * (UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSERTS) / imc_0@event\\=0x0@", - "MetricGroup": "Mem;MemoryLat;Server;SoC", - "MetricName": "MEM_DRAM_Read_Latency" + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))", + "MetricGroup": "DSBmiss;Fed;tma_issueFB", + "MetricName": "tma_info_dsb_misses", + "MetricThreshold": "tma_info_dsb_misses > 10", + "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_iptb, tma_lcp" }, { - "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]", - "MetricExpr": "64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW;Server;SoC", - "MetricName": "PMM_Read_BW" + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHES.COUNT", + "MetricGroup": "DSBmiss", + "MetricName": "tma_info_dsb_switch_cost" }, { - "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]", - "MetricExpr": "64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW;Server;SoC", - "MetricName": "PMM_Write_BW" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-thread", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "tma_info_execute" }, { - "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]", - "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1e9 / duration_time", - "MetricGroup": "IoBW;Mem;Server;SoC", - "MetricName": "IO_Write_BW" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "tma_info_execute_per_issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." }, { - "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]", - "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3) * 4 / 1e9 / duration_time", - "MetricGroup": "IoBW;Mem;Server;SoC", - "MetricName": "IO_Read_BW" + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_fb_hpki" }, { - "BriefDescription": "Socket actual clocks when any core is active on that socket", - "MetricExpr": "cha_0@event\\=0x0@", - "MetricGroup": "SoC", - "MetricName": "Socket_CLKS" + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_fetch_upc" }, { - "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", - "MetricGroup": "Branches;OS", - "MetricName": "IpFarBranch" + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / tma_info_core_clks", + "MetricGroup": "Flops;Ret", + "MetricName": "tma_info_flopc" }, { - "BriefDescription": "Uncore frequency per die [GHZ]", - "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9", - "MetricGroup": "SoC", - "MetricName": "UNCORE_FREQ" + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@) / (2 * tma_info_core_clks)", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_fp_arith_utilization", + "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." }, { - "BriefDescription": "Percentage of time spent in the active CPU power state C0", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", - "MetricName": "cpu_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Giga Floating Point Operations Per Second", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_gflops", + "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." }, { - "BriefDescription": "CPU operating frequency (in GHz)", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / duration_time", - "MetricName": "cpu_operating_frequency", - "ScaleUnit": "1GHz" + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck", + "MetricExpr": "100 * (tma_fetch_latency * tma_icache_misses / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", + "MetricGroup": "Fed;FetchLat;IcMiss;tma_issueFL", + "MetricName": "tma_info_ic_misses", + "MetricThreshold": "tma_info_ic_misses > 5", + "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck. Related metrics: " }, { - "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY", - "MetricName": "cpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Average Latency for L1 instruction cache misses", + "MetricExpr": "ICACHE_16B.IFDATA_STALL / cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@ + 2", + "MetricGroup": "Fed;FetchLat;IcMiss", + "MetricName": "tma_info_icache_miss_latency" }, { - "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions", - "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY", - "MetricName": "loads_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", + "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", + "MetricName": "tma_info_ilp" }, { - "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions", - "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY", - "MetricName": "stores_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_big_code", + "MetricGroup": "Fed;FetchBW;Frontend", + "MetricName": "tma_info_instruction_fetch_bw", + "MetricThreshold": "tma_info_instruction_fetch_bw > 20" }, { - "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions", - "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY", - "MetricName": "l1d_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;tma_L1_group", + "MetricName": "tma_info_instructions", + "PublicDescription": "Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST" }, { - "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ", - "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY", - "MetricName": "l1d_demand_data_read_hits_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]", + "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3) * 4 / 1e9 / duration_time", + "MetricGroup": "IoBW;Mem;Server;SoC", + "MetricName": "tma_info_io_read_bw" }, { - "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions", - "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY", - "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]", + "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1e9 / duration_time", + "MetricGroup": "IoBW;Mem;Server;SoC", + "MetricName": "tma_info_io_write_bw" }, { - "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ", - "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY", - "MetricName": "l2_demand_data_read_hits_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_iparith", + "MetricThreshold": "tma_info_iparith < 10", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." }, { - "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions", - "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY", - "MetricName": "l2_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx128", + "MetricThreshold": "tma_info_iparith_avx128 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions", - "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricName": "l2_demand_data_read_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx256", + "MetricThreshold": "tma_info_iparith_avx256 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions", - "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", - "MetricName": "l2_demand_code_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx512", + "MetricThreshold": "tma_info_iparith_avx512 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", - "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x12D4043300000000@ / INST_RETIRED.ANY", - "MetricName": "llc_data_read_mpi_demand_plus_prefetch", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_iparith_scalar_dp", + "MetricThreshold": "tma_info_iparith_scalar_dp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", - "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x12CC023300000000@ / INST_RETIRED.ANY", - "MetricName": "llc_code_read_mpi_demand_plus_prefetch", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_iparith_scalar_sp", + "MetricThreshold": "tma_info_iparith_scalar_sp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds", - "MetricExpr": "1e9 * (cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043300000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043300000000@) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages)) * duration_time", - "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency", - "ScaleUnit": "1ns" + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "tma_info_ipbranch", + "MetricThreshold": "tma_info_ipbranch < 8" }, { - "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds", - "MetricExpr": "1e9 * (cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043200000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages)) * duration_time", - "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests", - "ScaleUnit": "1ns" + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_clks", + "MetricGroup": "Ret;Summary", + "MetricName": "tma_info_ipc" }, { - "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds", - "MetricExpr": "1e9 * (cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043100000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages)) * duration_time", - "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests", - "ScaleUnit": "1ns" + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_ipcall", + "MetricThreshold": "tma_info_ipcall < 200" }, { - "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions", - "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", - "MetricName": "itlb_mpi", - "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "tma_info_ipdsb_miss_ret", + "MetricThreshold": "tma_info_ipdsb_miss_ret < 50" }, { - "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions", - "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY", - "MetricName": "itlb_large_page_mpi", - "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "tma_info_ipfarbranch", + "MetricThreshold": "tma_info_ipfarbranch < 1e6" }, { - "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions", - "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", - "MetricName": "dtlb_load_mpi", - "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_ipflop", + "MetricThreshold": "tma_info_ipflop < 10" }, { - "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions", - "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY", - "MetricName": "dtlb_2mb_large_page_load_mpi", - "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipload", + "MetricThreshold": "tma_info_ipload < 3" }, { - "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions", - "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", - "MetricName": "dtlb_store_mpi", - "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "tma_info_instructions / (UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * cpu@BR_MISP_EXEC.ALL_BRANCHES\\,umask\\=0xE4@)", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_indirect", + "MetricThreshold": "tma_info_ipmisp_indirect < 1e3" }, { - "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", - "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ / (cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@)", - "MetricName": "numa_reads_addressed_to_local_dram", - "ScaleUnit": "100%" + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "tma_info_ipmispredict", + "MetricThreshold": "tma_info_ipmispredict < 200" }, { - "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", - "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@ / (cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@)", - "MetricName": "numa_reads_addressed_to_remote_dram", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipstore", + "MetricThreshold": "tma_info_ipstore < 8" }, { - "BriefDescription": "Uncore operating frequency in GHz", - "MetricExpr": "UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages) / 1e9 / duration_time", - "MetricName": "uncore_frequency", - "ScaleUnit": "1GHz" + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", + "MetricGroup": "Prefetches", + "MetricName": "tma_info_ipswpf", + "MetricThreshold": "tma_info_ipswpf < 100" }, { - "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)", - "MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 7.111111111111111 / 1e6 / duration_time", - "MetricName": "upi_data_transmit_bw", - "ScaleUnit": "1MB/s" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", + "MetricName": "tma_info_iptb", + "MetricThreshold": "tma_info_iptb < 9", + "PublicDescription": "Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_dsb_misses, tma_lcp" }, { - "BriefDescription": "DDR memory read bandwidth (MB/sec)", - "MetricExpr": "UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time", - "MetricName": "memory_bandwidth_read", - "ScaleUnit": "1MB/s" + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "tma_info_instructions / BACLEARS.ANY", + "MetricGroup": "Fed", + "MetricName": "tma_info_ipunknown_branch" }, { - "BriefDescription": "DDR memory write bandwidth (MB/sec)", - "MetricExpr": "UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time", - "MetricName": "memory_bandwidth_write", - "ScaleUnit": "1MB/s" + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_jump" }, { - "BriefDescription": "DDR memory bandwidth (MB/sec)", - "MetricExpr": "(UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e6 / duration_time", - "MetricName": "memory_bandwidth_total", - "ScaleUnit": "1MB/s" + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_cpi" }, { - "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)", - "MetricExpr": "UNC_M_PMM_RPQ_INSERTS * 64 / 1e6 / duration_time", - "MetricName": "pmem_memory_bandwidth_read", - "ScaleUnit": "1MB/s" + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_utilization", + "MetricThreshold": "tma_info_kernel_utilization > 0.05" }, { - "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)", - "MetricExpr": "UNC_M_PMM_WPQ_INSERTS * 64 / 1e6 / duration_time", - "MetricName": "pmem_memory_bandwidth_write", - "ScaleUnit": "1MB/s" + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw" }, { - "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)", - "MetricExpr": "(UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS) * 64 / 1e6 / duration_time", - "MetricName": "pmem_memory_bandwidth_total", - "ScaleUnit": "1MB/s" + "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "tma_info_l1d_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw_1t" }, { - "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.", - "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1e6 / duration_time", - "MetricName": "io_bandwidth_disk_or_network_writes", - "ScaleUnit": "1MB/s" + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l1mpki" }, { - "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.", - "MetricExpr": "(UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3) * 4 / 1e6 / duration_time", - "MetricName": "io_bandwidth_disk_or_network_reads", - "ScaleUnit": "1MB/s" + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l1mpki_load" }, { - "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue", - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)", - "MetricName": "percent_uops_delivered_from_decoded_icache", - "ScaleUnit": "100%" + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw" }, { - "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue", - "MetricExpr": "IDQ.MITE_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)", - "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline", - "ScaleUnit": "100%" + "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "tma_info_l2_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw_1t" }, { - "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue", - "MetricExpr": "IDQ.MS_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)", - "MetricName": "percent_uops_delivered_from_microcode_sequencer", - "ScaleUnit": "100%" + "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction", + "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / tma_info_instructions", + "MetricGroup": "L2Evicts;Mem;Server", + "MetricName": "tma_info_l2_evictions_nonsilent_pki" }, { - "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.", - "MetricExpr": "UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1e6 / duration_time", - "MetricName": "llc_miss_local_memory_bandwidth_read", - "ScaleUnit": "1MB/s" + "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)", + "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / tma_info_instructions", + "MetricGroup": "L2Evicts;Mem;Server", + "MetricName": "tma_info_l2_evictions_silent_pki" }, { - "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.", - "MetricExpr": "UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1e6 / duration_time", - "MetricName": "llc_miss_local_memory_bandwidth_write", - "ScaleUnit": "1MB/s" + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2hpki_all" }, { - "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.", - "MetricExpr": "UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1e6 / duration_time", - "MetricName": "llc_miss_remote_memory_bandwidth_read", - "ScaleUnit": "1MB/s" + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2hpki_load" }, { - "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", - "MetricGroup": "PGO;TopdownL1;tma_L1_group;tma_L1_group", - "MetricName": "tma_frontend_bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", - "ScaleUnit": "100%" + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Backend;CacheMisses;Mem", + "MetricName": "tma_info_l2mpki" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", - "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS", - "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_latency", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.", - "ScaleUnit": "100%" + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem;Offcore", + "MetricName": "tma_info_l2mpki_all" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", - "MetricExpr": "(ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_icache_misses", - "ScaleUnit": "100%" + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction", + "MetricExpr": "1e3 * FRONTEND_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss", + "MetricName": "tma_info_l2mpki_code" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.", - "MetricExpr": "ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_itlb_misses", - "ScaleUnit": "100%" + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction", + "MetricExpr": "1e3 * L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss", + "MetricName": "tma_info_l2mpki_code_all" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", - "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + tma_unknown_branches", - "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_branch_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.", - "ScaleUnit": "100%" + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2mpki_load" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group", - "MetricName": "tma_mispredicts_resteers", - "ScaleUnit": "100%" + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_l3_cache_access_bw" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ", - "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group", - "MetricName": "tma_clears_resteers", - "ScaleUnit": "100%" + "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_l3_cache_access_bw", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_l3_cache_access_bw_1t" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", - "MetricExpr": "9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", - "MetricName": "tma_unknown_branches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit).", - "ScaleUnit": "100%" + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_dsb_switches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", - "ScaleUnit": "100%" + "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_l3_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw_1t" }, { - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", - "MetricExpr": "ILD_STALL.LCP / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_lcp", - "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", - "ScaleUnit": "100%" + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l3mpki" }, { - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", - "MetricExpr": "2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_ms_switches", - "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", - "ScaleUnit": "100%" + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore", + "MetricName": "tma_info_load_l2_miss_latency" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", - "MetricExpr": "tma_frontend_bound - tma_fetch_latency", - "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_bandwidth", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", - "ScaleUnit": "100%" + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_load_l2_mlp" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", - "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2", - "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", - "MetricName": "tma_mite", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", - "ScaleUnit": "100%" + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "tma_info_load_miss_real_latency" }, { - "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", - "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=0x1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=0x2@) / CORE_CLKS", - "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group", - "MetricName": "tma_decoder0_alone", - "ScaleUnit": "100%" + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_load_stlb_mpki" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", - "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2", - "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", - "MetricName": "tma_dsb", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", - "ScaleUnit": "100%" + "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]", + "MetricExpr": "1e9 * (UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSERTS) / imc_0@event\\=0x0@", + "MetricGroup": "Mem;MemoryLat;Server;SoC", + "MetricName": "tma_info_mem_dram_read_latency", + "PublicDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches" }, { - "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", - "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group", - "MetricName": "tma_bad_speculation", - "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", - "ScaleUnit": "100%" + "BriefDescription": "Average number of parallel data read requests to external memory", + "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@thresh\\=1@", + "MetricGroup": "Mem;MemoryBW;SoC", + "MetricName": "tma_info_mem_parallel_reads", + "PublicDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_branch_mispredicts", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.", - "ScaleUnit": "100%" + "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]", + "MetricExpr": "1e9 * (UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS) / imc_0@event\\=0x0@", + "MetricGroup": "Mem;MemoryLat;Server;SoC", + "MetricName": "tma_info_mem_pmm_read_latency", + "PublicDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", - "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_machine_clears", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", - "ScaleUnit": "100%" + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds)", + "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (tma_info_socket_clks / duration_time)", + "MetricGroup": "Mem;MemoryLat;SoC", + "MetricName": "tma_info_mem_read_latency", + "PublicDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)" }, { - "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", - "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group", - "MetricName": "tma_backend_bound", - "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))", + "MetricGroup": "Mem;MemoryBW;Offcore;tma_issueBW", + "MetricName": "tma_info_memory_bandwidth", + "MetricThreshold": "tma_info_memory_bandwidth > 20", + "PublicDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_mem_bandwidth, tma_sq_full" }, { - "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + UOPS_RETIRED.RETIRE_SLOTS / SLOTS * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound", - "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_memory_bound", - "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency)))", + "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", + "MetricName": "tma_info_memory_data_tlbs", + "MetricThreshold": "tma_info_memory_data_tlbs > 20", + "PublicDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", - "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CPU_CLK_UNHALTED.THREAD, 0)", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_l1_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound))", + "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", + "MetricName": "tma_info_memory_latency", + "MetricThreshold": "tma_info_memory_latency > 20", + "PublicDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches). Related metrics: tma_l3_hit_latency, tma_mem_latency" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", - "MetricExpr": "min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_dtlb_load", - "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", + "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", + "MetricName": "tma_info_mispredictions", + "MetricThreshold": "tma_info_mispredictions > 20", + "PublicDescription": "Total pipeline cost of Branch Misprediction related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_branch_misprediction_cost, tma_mispredicts_resteers" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", - "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss", - "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", - "MetricName": "tma_load_stlb_hit", - "ScaleUnit": "100%" + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBW;MemoryBound", + "MetricName": "tma_info_mlp", + "PublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)" }, { - "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", - "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", - "MetricName": "tma_load_stlb_miss", - "ScaleUnit": "100%" + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING) / (2 * tma_info_core_clks)", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_page_walks_utilization", + "MetricThreshold": "tma_info_page_walks_utilization > 0.5" }, { - "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", - "MetricExpr": "min(13 * LD_BLOCKS.STORE_FORWARD / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_store_fwd_blk", - "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", - "ScaleUnit": "100%" + "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]", + "MetricExpr": "64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW;Server;SoC", + "MetricName": "tma_info_pmm_read_bw" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", - "MetricExpr": "min((12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (11 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_lock_latency", - "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.", - "ScaleUnit": "100%" + "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]", + "MetricExpr": "64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW;Server;SoC", + "MetricName": "tma_info_pmm_write_bw" }, { - "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ", - "MetricExpr": "min(Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_split_loads", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0", + "MetricExpr": "(CORE_POWER.LVL0_TURBO_LICENSE / 2 / tma_info_core_clks if #SMT_on else CORE_POWER.LVL0_TURBO_LICENSE / tma_info_core_clks)", + "MetricGroup": "Power", + "MetricName": "tma_info_power_license0_utilization", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes." }, { - "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", - "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_4k_aliasing", - "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1", + "MetricExpr": "(CORE_POWER.LVL1_TURBO_LICENSE / 2 / tma_info_core_clks if #SMT_on else CORE_POWER.LVL1_TURBO_LICENSE / tma_info_core_clks)", + "MetricGroup": "Power", + "MetricName": "tma_info_power_license1_utilization", + "MetricThreshold": "tma_info_power_license1_utilization > 0.5", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions." }, { - "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", - "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_fb_full", - "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)", + "MetricExpr": "(CORE_POWER.LVL2_TURBO_LICENSE / 2 / tma_info_core_clks if #SMT_on else CORE_POWER.LVL2_TURBO_LICENSE / tma_info_core_clks)", + "MetricGroup": "Power", + "MetricName": "tma_info_power_license2_utilization", + "MetricThreshold": "tma_info_power_license2_utilization > 0.5", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions." }, { - "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", - "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD)", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_l2_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.", - "ScaleUnit": "100%" + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "tma_info_retire" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_l3_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.", - "ScaleUnit": "100%" + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * tma_info_core_clks", + "MetricGroup": "TmaL1;tma_L1_group", + "MetricName": "tma_info_slots" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", - "MetricExpr": "min(((47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD))) + (47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", - "MetricName": "tma_contested_accesses", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", + "MetricGroup": "SMT", + "MetricName": "tma_info_smt_2t_utilization" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", - "MetricExpr": "min((47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", - "MetricName": "tma_data_sharing", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.", - "ScaleUnit": "100%" + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "cha_0@event\\=0x0@", + "MetricGroup": "SoC", + "MetricName": "tma_info_socket_clks" }, { - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", - "MetricExpr": "min((20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group", - "MetricName": "tma_l3_hit_latency", - "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", - "ScaleUnit": "100%" + "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_store_stlb_mpki" }, { - "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", - "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group", - "MetricName": "tma_sq_full", - "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.", - "ScaleUnit": "100%" + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "tma_info_clks / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power", + "MetricName": "tma_info_turbo_utilization" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", - "MetricExpr": "min(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD - tma_l2_bound - min(((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0), 1), 1)", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_dram_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.", - "ScaleUnit": "100%" + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire", + "MetricName": "tma_info_uoppi", + "MetricThreshold": "tma_info_uoppi > 1.05" }, { - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group", - "MetricName": "tma_mem_bandwidth", - "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", - "ScaleUnit": "100%" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "tma_info_uptb", + "MetricThreshold": "tma_info_uptb < 6" }, { - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CPU_CLK_UNHALTED.THREAD - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group", - "MetricName": "tma_mem_latency", - "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", + "MetricExpr": "ICACHE_64B.IFTAG_STALL / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory", - "MetricExpr": "min((80 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_local_dram", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", + "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / tma_info_clks, 0)", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group", + "MetricName": "tma_l1_bound", + "MetricThreshold": "tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory", - "MetricExpr": "min((147.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_remote_dram", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", + "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks)", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l2_bound", + "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues", - "MetricExpr": "min(((110 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + (110 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_remote_cache", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / tma_info_clks", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l3_bound", + "MetricThreshold": "tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a", - "MetricExpr": "min(((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0), 1)", - "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_pmm_bound", - "PublicDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ", + "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", + "MetricExpr": "17 * tma_info_average_frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group", + "MetricName": "tma_l3_hit_latency", + "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_memory_latency, tma_mem_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", - "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_store_bound", - "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.", + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", + "MetricExpr": "ILD_STALL.LCP / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_lcp", + "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", - "MetricExpr": "(L2_RQSTS.RFO_HIT * 11 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_store_latency", - "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", + "MetricExpr": "tma_retiring - tma_heavy_operations", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_light_operations", + "MetricThreshold": "tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", - "MetricExpr": "min((110 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) * (OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM + OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM) + 47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) * (OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE)) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_false_sharing", - "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_load_op_utilization", + "MetricThreshold": "tma_load_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents rate of split store accesses", - "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CORE_CLKS", - "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_split_stores", - "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.", + "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", + "MetricName": "tma_load_stlb_hit", + "MetricThreshold": "tma_load_stlb_hit > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", - "MetricExpr": "min((9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CORE_CLKS, 1)", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_dtlb_store", - "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.", + "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", + "MetricName": "tma_load_stlb_miss", + "MetricThreshold": "tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", - "MetricExpr": "tma_dtlb_store - DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS", - "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", - "MetricName": "tma_store_stlb_hit", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory", + "MetricExpr": "59.5 * tma_info_average_frequency * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group", + "MetricName": "tma_local_dram", + "MetricThreshold": "tma_local_dram > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", - "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS", - "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", - "MetricName": "tma_store_stlb_miss", + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", + "MetricExpr": "(12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (11 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / tma_info_clks", + "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group", + "MetricName": "tma_lock_latency", + "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", - "MetricExpr": "tma_backend_bound - tma_memory_bound", - "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_core_bound", - "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", + "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", - "MetricExpr": "ARITH.DIVIDER_ACTIVE / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", - "MetricName": "tma_divider", - "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.", + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW", + "MetricName": "tma_mem_bandwidth", + "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_info_memory_bandwidth, tma_sq_full", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", - "MetricExpr": "((EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + UOPS_RETIRED.RETIRE_SLOTS / SLOTS * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + UOPS_RETIRED.RETIRE_SLOTS / SLOTS * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD)", - "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", - "MetricName": "tma_ports_utilization", - "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_clks - tma_mem_bandwidth", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat", + "MetricName": "tma_mem_latency", + "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_info_memory_latency, tma_l3_hit_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_NONE / 2 if #SMT_on else CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_0", - "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound", + "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_memory_bound", + "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations", - "MetricExpr": "PARTIAL_RAT_STALLS.SCOREBOARD / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group", - "MetricName": "tma_serializing_operation", - "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", + "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_memory_operations", + "MetricThreshold": "tma_memory_operations > 0.1 & tma_light_operations > 0.6", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.", - "MetricExpr": "40 * ROB_MISC_EVENTS.PAUSE_INST / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group", - "MetricName": "tma_slow_pause", + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_slots", + "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS", + "MetricName": "tma_microcode_sequencer", + "MetricThreshold": "tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY, 1)", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group", - "MetricName": "tma_mixing_vectors", - "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks", + "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM", + "MetricName": "tma_mispredicts_resteers", + "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_branch_misprediction_cost, tma_info_mispredictions", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2) / 2 if #SMT_on else EXE_ACTIVITY.1_PORTS_UTIL) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_1", - "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", + "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / tma_info_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_mite", + "MetricThreshold": "tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3) / 2 if #SMT_on else EXE_ACTIVITY.2_PORTS_UTIL) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_2", - "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", + "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued", + "MetricExpr": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY", + "MetricGroup": "TopdownL5;tma_L5_group;tma_issueMV;tma_ports_utilized_0_group", + "MetricName": "tma_mixing_vectors", + "MetricThreshold": "tma_mixing_vectors > 0.05", + "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic. Related metrics: tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", - "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_3) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_3m", + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", + "MetricExpr": "2 * IDQ.MS_SWITCHES / tma_info_clks", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", + "MetricName": "tma_ms_switches", + "MetricThreshold": "tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", - "MetricName": "tma_alu_op_utilization", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused", + "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_non_fused_branches", + "MetricThreshold": "tma_non_fused_branches > 0.1 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS", - "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group", - "MetricName": "tma_port_0", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions", + "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_nop_instructions", + "MetricThreshold": "tma_nop_instructions > 0.1 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", - "MetricName": "tma_port_1", + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes", + "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions))", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_other_light_ops", + "MetricThreshold": "tma_other_light_ops > 0.3 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", - "MetricName": "tma_port_5", + "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0)", + "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_pmm_bound", + "MetricThreshold": "tma_pmm_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", - "MetricName": "tma_port_6", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / tma_info_core_clks", + "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_0", + "MetricThreshold": "tma_port_0 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED_PORT.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", - "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", - "MetricName": "tma_load_op_utilization", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_1", + "MetricThreshold": "tma_port_1 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / tma_info_core_clks", "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", "MetricName": "tma_port_2", + "MetricThreshold": "tma_port_2 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_2", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / tma_info_core_clks", "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", "MetricName": "tma_port_3", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", - "MetricName": "tma_store_op_utilization", + "MetricThreshold": "tma_port_3 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_3", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)", "MetricExpr": "tma_store_op_utilization", - "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group", + "MetricGroup": "TopdownL6;tma_L6_group;tma_issueSpSt;tma_store_op_utilization_group", "MetricName": "tma_port_4", + "MetricThreshold": "tma_port_4 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Sample with: UOPS_DISPATCHED_PORT.PORT_4. Related metrics: tma_split_stores", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group", - "MetricName": "tma_port_7", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_5", + "MetricThreshold": "tma_port_5 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Sample with: UOPS_DISPATCHED.PORT_5. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group", - "MetricName": "tma_retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_6", + "MetricThreshold": "tma_port_6 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", - "MetricExpr": "tma_retiring - (UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / SLOTS", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group", - "MetricName": "tma_light_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group", + "MetricName": "tma_port_7", + "MetricThreshold": "tma_port_7 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address). Sample with: UOPS_DISPATCHED_PORT.PORT_7", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", - "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD + tma_fp_scalar + tma_fp_vector", - "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_fp_arith", - "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", + "MetricExpr": "((EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / tma_info_clks if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / tma_info_clks)", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_ports_utilization", + "MetricThreshold": "tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric serves as an approximation of legacy x87 usage", - "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD", - "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", - "MetricName": "tma_x87_use", - "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_NONE / 2 if #SMT_on else CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_core_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_0", + "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group", - "MetricName": "tma_fp_scalar", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2) / 2 if #SMT_on else EXE_ACTIVITY.1_PORTS_UTIL) / tma_info_core_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_1", + "MetricThreshold": "tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Related metrics: tma_l1_bound", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", - "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)", - "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group", - "MetricName": "tma_fp_vector", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3) / 2 if #SMT_on else EXE_ACTIVITY.2_PORTS_UTIL) / tma_info_core_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_2", + "MetricThreshold": "tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", - "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)", - "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", - "MetricName": "tma_fp_vector_128b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.", + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", + "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_3) / tma_info_core_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_3m", + "MetricThreshold": "tma_ports_utilized_3m > 0.7 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", - "MetricExpr": "min((FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)", - "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", - "MetricName": "tma_fp_vector_256b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "(89.5 * tma_info_average_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + 89.5 * tma_info_average_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_issueSyncxn;tma_mem_latency_group", + "MetricName": "tma_remote_cache", + "MetricThreshold": "tma_remote_cache > 0.05 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors", - "MetricExpr": "min((FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)", - "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", - "MetricName": "tma_fp_vector_512b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory", + "MetricExpr": "127 * tma_info_average_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", + "MetricName": "tma_remote_dram", + "MetricThreshold": "tma_remote_dram > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", - "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_memory_operations", + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions", - "MetricExpr": "tma_light_operations * UOPS_RETIRED.MACRO_FUSED / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_fused_instructions", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.", + "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations", + "MetricExpr": "PARTIAL_RAT_STALLS.SCOREBOARD / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL5;tma_L5_group;tma_issueSO;tma_ports_utilized_0_group", + "MetricName": "tma_serializing_operation", + "MetricThreshold": "tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: PARTIAL_RAT_STALLS.SCOREBOARD. Related metrics: tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused", - "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_non_fused_branches", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions", + "MetricExpr": "40 * ROB_MISC_EVENTS.PAUSE_INST / tma_info_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group", + "MetricName": "tma_slow_pause", + "MetricThreshold": "tma_slow_pause > 0.05 & (tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: MISC_RETIRED.PAUSE_INST", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions", - "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_nop_instructions", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "tma_info_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_split_loads", + "MetricThreshold": "tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", - "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions))", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_other_light_ops", + "BriefDescription": "This metric represents rate of split store accesses", + "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / tma_info_core_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group", + "MetricName": "tma_split_stores", + "MetricThreshold": "tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences", - "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / SLOTS", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group", - "MetricName": "tma_heavy_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.", + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", + "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group", + "MetricName": "tma_sq_full", + "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_info_memory_bandwidth, tma_mem_bandwidth", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops", - "MetricExpr": "tma_heavy_operations - UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS", - "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group", - "MetricName": "tma_few_uops_instructions", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.", + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", + "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_store_bound", + "MetricThreshold": "tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS", - "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group", - "MetricName": "tma_microcode_sequencer", - "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.", + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", + "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_store_fwd_blk", + "MetricThreshold": "tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", - "MetricExpr": "min(100 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / SLOTS, 1)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", - "MetricName": "tma_assists", - "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.", + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "(L2_RQSTS.RFO_HIT * 11 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_clks", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group", + "MetricName": "tma_store_latency", + "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", - "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", - "MetricName": "tma_cisc", - "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / tma_info_core_clks", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_store_op_utilization", + "MetricThreshold": "tma_store_op_utilization > 0.6", "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per core", - "MetricExpr": "cstate_core@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Core_Residency", + "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", + "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", + "MetricName": "tma_store_stlb_hit", + "MetricThreshold": "tma_store_stlb_hit > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per core", - "MetricExpr": "cstate_core@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Core_Residency", + "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", + "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / tma_info_core_clks", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", + "MetricName": "tma_store_stlb_miss", + "MetricThreshold": "tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per core", - "MetricExpr": "cstate_core@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Core_Residency", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", + "MetricExpr": "9 * BACLEARS.ANY / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", + "MetricName": "tma_unknown_branches", + "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit). Sample with: BACLEARS.ANY", "ScaleUnit": "100%" }, { - "BriefDescription": "C2 residency percent per package", - "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C2_Pkg_Residency", + "BriefDescription": "This metric serves as an approximation of legacy x87 usage", + "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD", + "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_x87_use", + "MetricThreshold": "tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per package", - "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Pkg_Residency", + "BriefDescription": "Percentage of cycles in aborted transactions.", + "MetricExpr": "max(cpu@cycles\\-t@ - cpu@cycles\\-ct@, 0) / cycles", + "MetricGroup": "transaction", + "MetricName": "tsx_aborted_cycles", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per package", - "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Pkg_Residency", - "ScaleUnit": "100%" + "BriefDescription": "Number of cycles within a transaction divided by the number of elisions.", + "MetricExpr": "cpu@cycles\\-t@ / cpu@el\\-start@", + "MetricGroup": "transaction", + "MetricName": "tsx_cycles_per_elision", + "ScaleUnit": "1cycles / elision" }, { - "BriefDescription": "C7 residency percent per package", - "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Pkg_Residency", + "BriefDescription": "Number of cycles within a transaction divided by the number of transactions.", + "MetricExpr": "cpu@cycles\\-t@ / cpu@tx\\-start@", + "MetricGroup": "transaction", + "MetricName": "tsx_cycles_per_transaction", + "ScaleUnit": "1cycles / transaction" + }, + { + "BriefDescription": "Percentage of cycles within a transaction region.", + "MetricExpr": "cpu@cycles\\-t@ / cycles", + "MetricGroup": "transaction", + "MetricName": "tsx_transactional_cycles", "ScaleUnit": "100%" } ] diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json b/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json index 13ccf50db43d..04f08e4d2402 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json @@ -322,7 +322,7 @@ "UMask": "0x4" }, { - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", @@ -331,7 +331,7 @@ "UMask": "0x30" }, { - "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -340,7 +340,7 @@ "UMask": "0x10" }, { - "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", "PublicDescription": "Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.", @@ -358,7 +358,7 @@ "UMask": "0x30" }, { - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.", diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json b/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json index 64e1fe351333..0f06e314fe36 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json @@ -93,6 +93,22 @@ "SampleAfterValue": "400009", "UMask": "0x10" }, + { + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0xff" + }, + { + "BriefDescription": "Speculative mispredicted indirect branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.INDIRECT", + "PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, { "BriefDescription": "All mispredicted macro branch instructions retired.", "EventCode": "0xC5", diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json index 70a2c0ff8dfd..aafd2c9b813b 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json @@ -192,7 +192,7 @@ "EventCode": "0x9", "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", "PerPkg": "1", - "PublicDescription": "Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit erros in lockstep mode.", + "PublicDescription": "Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit errors in lockstep mode.", "Unit": "iMC" }, { @@ -212,7 +212,7 @@ "Unit": "iMC" }, { - "BriefDescription": "UNC_M_MAJMODE2.PMM_CYC", + "BriefDescription": "Major Mode 2 : Cycles in PMM major mode", "EventCode": "0xED", "EventName": "UNC_M_MAJMODE2.PMM_CYC", "PerPkg": "1", @@ -220,7 +220,7 @@ "Unit": "iMC" }, { - "BriefDescription": "UNC_M_MAJMODE2.PMM_ENTER", + "BriefDescription": "Major Mode 2 : Entered PMM major mode", "EventCode": "0xED", "EventName": "UNC_M_MAJMODE2.PMM_ENTER", "PerPkg": "1", @@ -290,7 +290,7 @@ "Unit": "iMC" }, { - "BriefDescription": "All commands for Intel Optane DC persistent memory", + "BriefDescription": "All commands for Intel(R) Optane(TM) DC persistent memory", "EventCode": "0xEA", "EventName": "UNC_M_PMM_CMD1.ALL", "PerPkg": "1", @@ -314,7 +314,7 @@ "Unit": "iMC" }, { - "BriefDescription": "Regular reads(RPQ) commands for Intel Optane DC persistent memory", + "BriefDescription": "Regular reads(RPQ) commands for Intel(R) Optane(TM) DC persistent memory", "EventCode": "0xEA", "EventName": "UNC_M_PMM_CMD1.RD", "PerPkg": "1", @@ -331,7 +331,7 @@ "Unit": "iMC" }, { - "BriefDescription": "Underfill read commands for Intel Optane DC persistent memory", + "BriefDescription": "Underfill read commands for Intel(R) Optane(TM) DC persistent memory", "EventCode": "0xEA", "EventName": "UNC_M_PMM_CMD1.UFILL_RD", "PerPkg": "1", @@ -348,7 +348,7 @@ "Unit": "iMC" }, { - "BriefDescription": "Write commands for Intel Optane DC persistent memory", + "BriefDescription": "Write commands for Intel(R) Optane(TM) DC persistent memory", "EventCode": "0xEA", "EventName": "UNC_M_PMM_CMD1.WR", "PerPkg": "1", @@ -522,7 +522,7 @@ "Unit": "iMC" }, { - "BriefDescription": "Write Pending Queue Occupancy of all write requests for Intel Optane DC persistent memory", + "BriefDescription": "Write Pending Queue Occupancy of all write requests for Intel(R) Optane(TM) DC persistent memory", "EventCode": "0xE4", "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL", "PerPkg": "1", @@ -2735,7 +2735,7 @@ "EventCode": "0x81", "EventName": "UNC_M_WPQ_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller). They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. Is there a filter of sorts???", + "PublicDescription": "Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller). They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. Is there a filter of sorts???", "Unit": "iMC" }, { diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json index ef4767feb4e2..5f3ed5e843b9 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json @@ -44,7 +44,7 @@ "MetricName": "LLC_MISSES.PCIE_WRITE", "PerPkg": "1", "PortMask": "0x01", - "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part0 to a unit onthe main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", "ScaleUnit": "4Bytes", "UMask": "0x1", "Unit": "IIO" @@ -856,7 +856,7 @@ "Unit": "CHA" }, { - "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Deallocate HtiME$ on Reads without RspFwdI*", + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Deallocate HitME$ on Reads without RspFwdI*", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE", "PerPkg": "1", @@ -1210,7 +1210,7 @@ "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.WRITE", "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cachable and UC.", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.", "UMask": "0x5", "Unit": "CHA" }, @@ -3481,7 +3481,7 @@ "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", "PerPkg": "1", - "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspSFwd to local CA requests. This is returned when a remote caching agent forwards data but holds on to its currentl copy. This is common for data and code reads that hit in a remote socket in E or F state.", + "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspSFwd to local CA requests. This is returned when a remote caching agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state.", "UMask": "0x8", "Unit": "CHA" }, @@ -4082,10 +4082,11 @@ "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.ALL", + "BriefDescription": "TOR Occupancy : All", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL", "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0xff", "Unit": "CHA" }, @@ -4153,20 +4154,22 @@ "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", "Filter": "config1=0x40233", "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", "Filter": "config1=0x40433", "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x11", "Unit": "CHA" }, @@ -4189,20 +4192,22 @@ "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", + "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", "Filter": "config1=0x4b033", "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", "Filter": "config1=0x40033", "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x11", "Unit": "CHA" }, @@ -4216,11 +4221,12 @@ "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", "Filter": "config1=0x40233", "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x21", "Unit": "CHA" }, @@ -4253,20 +4259,22 @@ "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", + "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", "Filter": "config1=0x4b033", "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", "Filter": "config1=0x40033", "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x21", "Unit": "CHA" }, @@ -4308,7 +4316,7 @@ "Unit": "CHA" }, { - "BriefDescription": "TOR Occupancy; RDCUR isses from Local IO", + "BriefDescription": "TOR Occupancy; RDCUR misses from Local IO", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RDCUR", "Filter": "config1=0x43C33", @@ -11637,7 +11645,7 @@ "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", - "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part0 to a unit onthe main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", "UMask": "0x1", "Unit": "IIO" }, @@ -12024,7 +12032,7 @@ "Unit": "IIO" }, { - "BriefDescription": "UNC_IIO_NOTHING", + "BriefDescription": "Counting disabled", "EventName": "UNC_IIO_NOTHING", "PerPkg": "1", "Unit": "IIO" @@ -15622,7 +15630,7 @@ "EventCode": "0xC", "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.", + "PublicDescription": "Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.", "Unit": "IRP" }, { @@ -16128,35 +16136,35 @@ "Unit": "M2M" }, { - "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden", + "BriefDescription": "Number of reads in which direct to Intel(R) UPI transactions were overridden", "EventCode": "0x28", "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS", "PerPkg": "1", - "PublicDescription": "Counts reads in which direct to Intel Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overridden", + "PublicDescription": "Counts reads in which direct to Intel(R) Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overridden", "Unit": "M2M" }, { - "BriefDescription": "Cycles when direct to Intel UPI was disabled", + "BriefDescription": "Cycles when direct to Intel(R) UPI was disabled", "EventCode": "0x27", "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE", "PerPkg": "1", - "PublicDescription": "Counts cycles when the ability to send messages direct to the Intel Ultra Path Interconnect (bypassing the CHA) was disabled", + "PublicDescription": "Counts cycles when the ability to send messages direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA) was disabled", "Unit": "M2M" }, { - "BriefDescription": "Messages sent direct to the Intel UPI", + "BriefDescription": "Messages sent direct to the Intel(R) UPI", "EventCode": "0x26", "EventName": "UNC_M2M_DIRECT2UPI_TAKEN", "PerPkg": "1", - "PublicDescription": "Counts when messages were sent direct to the Intel Ultra Path Interconnect (bypassing the CHA)", + "PublicDescription": "Counts when messages were sent direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA)", "Unit": "M2M" }, { - "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden", + "BriefDescription": "Number of reads that a message sent direct2 Intel(R) UPI was overridden", "EventCode": "0x29", "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE", "PerPkg": "1", - "PublicDescription": "Counts when a read message that was sent direct to the Intel Ultra Path Interconnect (bypassing the CHA) was overridden", + "PublicDescription": "Counts when a read message that was sent direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA) was overridden", "Unit": "M2M" }, { @@ -16583,7 +16591,7 @@ "Unit": "M2M" }, { - "BriefDescription": "Read requests to Intel Optane DC persistent memory issued to the iMC from M2M", + "BriefDescription": "Read requests to Intel(R) Optane(TM) DC persistent memory issued to the iMC from M2M", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.TO_PMM", "PerPkg": "1", @@ -16650,7 +16658,7 @@ "Unit": "M2M" }, { - "BriefDescription": "Write requests to Intel Optane DC persistent memory issued to the iMC from M2M", + "BriefDescription": "Write requests to Intel(R) Optane(TM) DC persistent memory issued to the iMC from M2M", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.TO_PMM", "PerPkg": "1", @@ -16675,7 +16683,7 @@ "Unit": "M2M" }, { - "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - Regular; Channel 0", + "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - Regular; Channel 0", "EventCode": "0x4F", "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN0", "PerPkg": "1", @@ -16683,7 +16691,7 @@ "Unit": "M2M" }, { - "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - Regular; Channel 1", + "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - Regular; Channel 1", "EventCode": "0x4F", "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN1", "PerPkg": "1", @@ -16691,7 +16699,7 @@ "Unit": "M2M" }, { - "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - Regular; Channel 2", + "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - Regular; Channel 2", "EventCode": "0x4F", "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN2", "PerPkg": "1", @@ -16699,7 +16707,7 @@ "Unit": "M2M" }, { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0", + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0", "EventCode": "0x51", "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN0", "PerPkg": "1", @@ -16707,7 +16715,7 @@ "Unit": "M2M" }, { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1", + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1", "EventCode": "0x51", "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN1", "PerPkg": "1", @@ -16715,7 +16723,7 @@ "Unit": "M2M" }, { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2", + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2", "EventCode": "0x51", "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN2", "PerPkg": "1", @@ -16737,11 +16745,11 @@ "Unit": "M2M" }, { - "BriefDescription": "Prefecth requests that got turn into a demand request", + "BriefDescription": "Prefetch requests that got turn into a demand request", "EventCode": "0x56", "EventName": "UNC_M2M_PREFCAM_DEMAND_PROMOTIONS", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) promotes a outstanding request in the prefetch queue due to a subsequent demand read request that entered the M2M with the same address. Explanatory Side Note: The Prefecth queue is made of CAM (Content Addressable Memory)", + "PublicDescription": "Counts when the M2M (Mesh to Memory) promotes a outstanding request in the prefetch queue due to a subsequent demand read request that entered the M2M with the same address. Explanatory Side Note: The Prefetch queue is made of CAM (Content Addressable Memory)", "Unit": "M2M" }, { @@ -20804,7 +20812,7 @@ "EventCode": "0x40", "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB", "PerPkg": "1", - "PublicDescription": "Number ot times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while bl message is in arbitration", + "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while bl message is in arbitration", "UMask": "0x2", "Unit": "M3UPI" }, @@ -20813,7 +20821,7 @@ "EventCode": "0x40", "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE", "PerPkg": "1", - "PublicDescription": "Number ot times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while pipeline is idle", + "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while pipeline is idle", "UMask": "0x1", "Unit": "M3UPI" }, @@ -20822,7 +20830,7 @@ "EventCode": "0x40", "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT", "PerPkg": "1", - "PublicDescription": "Number ot times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 1 while merging with bl message in same flit", + "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 1 while merging with bl message in same flit", "UMask": "0x4", "Unit": "M3UPI" }, @@ -20831,7 +20839,7 @@ "EventCode": "0x40", "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT", "PerPkg": "1", - "PublicDescription": "Number ot times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 2 while merging with bl message in same flit", + "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 2 while merging with bl message in same flit", "UMask": "0x8", "Unit": "M3UPI" }, @@ -21397,7 +21405,7 @@ "Unit": "M3UPI" }, { - "BriefDescription": "Flit Gen - Header 1; Acumullate", + "BriefDescription": "Flit Gen - Header 1; Accumulate", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM", "PerPkg": "1", @@ -24618,7 +24626,7 @@ "EventCode": "0x29", "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN", "PerPkg": "1", - "PublicDescription": "Count cases where flow control queue that sits between the Intel Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller)", + "PublicDescription": "Count cases where flow control queue that sits between the Intel(R) Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller)", "Unit": "M3UPI" }, { @@ -24973,11 +24981,11 @@ "Unit": "M2M" }, { - "BriefDescription": "Clocks of the Intel Ultra Path Interconnect (UPI)", + "BriefDescription": "Clocks of the Intel(R) Ultra Path Interconnect (UPI)", "EventCode": "0x1", "EventName": "UNC_UPI_CLOCKTICKS", "PerPkg": "1", - "PublicDescription": "Counts clockticks of the fixed frequency clock controlling the Intel Ultra Path Interconnect (UPI). This clock runs at1/8th the 'GT/s' speed of the UPI link. For example, a 9.6GT/s link will have a fixed Frequency of 1.2 Ghz.", + "PublicDescription": "Counts clockticks of the fixed frequency clock controlling the Intel(R) Ultra Path Interconnect (UPI). This clock runs at1/8th the 'GT/s' speed of the UPI link. For example, a 9.6GT/s link will have a fixed Frequency of 1.2 Ghz.", "Unit": "UPI LL" }, { @@ -24999,11 +25007,11 @@ "Unit": "UPI LL" }, { - "BriefDescription": "Data Response packets that go direct to Intel UPI", + "BriefDescription": "Data Response packets that go direct to Intel(R) UPI", "EventCode": "0x12", "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2U", "PerPkg": "1", - "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to Intel Ultra Path Interconnect (UPI) bypassing the CHA .", + "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to Intel(R) Ultra Path Interconnect (UPI) bypassing the CHA .", "UMask": "0x2", "Unit": "UPI LL" }, @@ -25072,11 +25080,11 @@ "Unit": "UPI LL" }, { - "BriefDescription": "Cycles Intel UPI is in L1 power mode (shutdown)", + "BriefDescription": "Cycles Intel(R) UPI is in L1 power mode (shutdown)", "EventCode": "0x21", "EventName": "UNC_UPI_L1_POWER_CYCLES", "PerPkg": "1", - "PublicDescription": "Counts cycles when the Intel Ultra Path Interconnect (UPI) is in L1 power mode. L1 is a mode that totally shuts down the UPI link. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdown.", + "PublicDescription": "Counts cycles when the Intel(R) Ultra Path Interconnect (UPI) is in L1 power mode. L1 is a mode that totally shuts down the UPI link. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdown.", "Unit": "UPI LL" }, { @@ -25238,11 +25246,11 @@ "Unit": "UPI LL" }, { - "BriefDescription": "Cycles the Rx of the Intel UPI is in L0p power mode", + "BriefDescription": "Cycles the Rx of the Intel(R) UPI is in L0p power mode", "EventCode": "0x25", "EventName": "UNC_UPI_RxL0P_POWER_CYCLES", "PerPkg": "1", - "PublicDescription": "Counts cycles when the receive side (Rx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.", + "PublicDescription": "Counts cycles when the receive side (Rx) of the Intel(R) Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.", "Unit": "UPI LL" }, { @@ -25451,7 +25459,7 @@ "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", "PerPkg": "1", - "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.", + "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel(R) Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.", "UMask": "0xf", "Unit": "UPI LL" }, @@ -25460,7 +25468,7 @@ "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", "PerPkg": "1", - "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.", + "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel(R) Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.", "UMask": "0x27", "Unit": "UPI LL" }, @@ -25784,11 +25792,11 @@ "Unit": "UPI LL" }, { - "BriefDescription": "Cycles in which the Tx of the Intel Ultra Path Interconnect (UPI) is in L0p power mode", + "BriefDescription": "Cycles in which the Tx of the Intel(R) Ultra Path Interconnect (UPI) is in L0p power mode", "EventCode": "0x27", "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", "PerPkg": "1", - "PublicDescription": "Counts cycles when the transmit side (Tx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.", + "PublicDescription": "Counts cycles when the transmit side (Tx) of the Intel(R) Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.", "Unit": "UPI LL" }, { @@ -25960,7 +25968,7 @@ "EventCode": "0x41", "EventName": "UNC_UPI_TxL_BYPASSED", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link. However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR mode, increasing latency to transfer out to the link.", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel(R) Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link. However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR mode, increasing latency to transfer out to the link.", "Unit": "UPI LL" }, { @@ -25968,7 +25976,7 @@ "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", "PerPkg": "1", - "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel Ultra Path Interconnect (UPI) slots on this UPI unit.", + "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel(R) Ultra Path Interconnect (UPI) slots on this UPI unit.", "UMask": "0xf", "Unit": "UPI LL" }, @@ -25977,7 +25985,7 @@ "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", "PerPkg": "1", - "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel Ulra Path Interconnect (UPI) slots on this UPI unit.", + "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel(R) Ulra Path Interconnect (UPI) slots on this UPI unit.", "UMask": "0x27", "Unit": "UPI LL" }, @@ -26328,7 +26336,7 @@ "EventCode": "0x2", "EventName": "UPI_DATA_BANDWIDTH_TX", "PerPkg": "1", - "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel Ultra Path Interconnect (UPI) slots on this UPI unit.", + "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel(R) Ultra Path Interconnect (UPI) slots on this UPI unit.", "ScaleUnit": "7.11E-06Bytes", "UMask": "0xf", "Unit": "UPI LL" diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-power.json b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-power.json index 6835e14cd42c..c6254af7a468 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-power.json @@ -143,7 +143,7 @@ "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", "PerPkg": "1", - "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", + "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", "Unit": "PCU" }, { @@ -151,7 +151,7 @@ "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", "PerPkg": "1", - "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", + "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", "Unit": "PCU" }, { @@ -159,7 +159,7 @@ "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", "PerPkg": "1", - "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", + "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", "Unit": "PCU" }, { @@ -175,7 +175,7 @@ "EventCode": "0x9", "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that we are in Interal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.", + "PublicDescription": "Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.", "Unit": "PCU" }, { diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index cad51223d0ea..793076e00188 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -5,7 +5,7 @@ GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core GenuineIntel-6-(3D|47),v26,broadwell,core GenuineIntel-6-56,v7,broadwellde,core GenuineIntel-6-4F,v19,broadwellx,core -GenuineIntel-6-55-[56789ABCDEF],v1.16,cascadelakex,core +GenuineIntel-6-55-[56789ABCDEF],v1.17,cascadelakex,core GenuineIntel-6-9[6C],v1.03,elkhartlake,core GenuineIntel-6-5[CF],v13,goldmont,core GenuineIntel-6-7A,v1.01,goldmontplus,core -- cgit v1.2.3-58-ga151 From 1e8ad07e3425ec37e37b6035defc856fc7cdcd7f Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:13 -0800 Subject: perf vendor events intel: Add graniterapids events Add version 1.00 of the graniterapids events from https://github.com/intel/perfmon. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-17-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/graniterapids/cache.json | 54 +++++++ .../arch/x86/graniterapids/frontend.json | 10 ++ .../pmu-events/arch/x86/graniterapids/memory.json | 174 +++++++++++++++++++++ .../pmu-events/arch/x86/graniterapids/other.json | 29 ++++ .../arch/x86/graniterapids/pipeline.json | 102 ++++++++++++ .../arch/x86/graniterapids/virtual-memory.json | 26 +++ tools/perf/pmu-events/arch/x86/mapfile.csv | 1 + 7 files changed, 396 insertions(+) create mode 100644 tools/perf/pmu-events/arch/x86/graniterapids/cache.json create mode 100644 tools/perf/pmu-events/arch/x86/graniterapids/frontend.json create mode 100644 tools/perf/pmu-events/arch/x86/graniterapids/memory.json create mode 100644 tools/perf/pmu-events/arch/x86/graniterapids/other.json create mode 100644 tools/perf/pmu-events/arch/x86/graniterapids/pipeline.json create mode 100644 tools/perf/pmu-events/arch/x86/graniterapids/virtual-memory.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/cache.json b/tools/perf/pmu-events/arch/x86/graniterapids/cache.json new file mode 100644 index 000000000000..56212827870c --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/graniterapids/cache.json @@ -0,0 +1,54 @@ +[ + { + "BriefDescription": "L2 code requests", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "PublicDescription": "Counts the total number of L2 code requests.", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, + { + "BriefDescription": "Demand Data Read access L2 cache", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.", + "SampleAfterValue": "200003", + "UMask": "0xe1" + }, + { + "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", + "EventCode": "0x2e", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", + "SampleAfterValue": "100003", + "UMask": "0x41" + }, + { + "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)", + "EventCode": "0x2e", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", + "SampleAfterValue": "100003", + "UMask": "0x4f" + }, + { + "BriefDescription": "Retired load instructions.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.ALL_LOADS", + "PEBS": "1", + "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.", + "SampleAfterValue": "1000003", + "UMask": "0x81" + }, + { + "BriefDescription": "Retired store instructions.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.ALL_STORES", + "PEBS": "1", + "PublicDescription": "Counts all retired store instructions.", + "SampleAfterValue": "1000003", + "UMask": "0x82" + } +] diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/frontend.json b/tools/perf/pmu-events/arch/x86/graniterapids/frontend.json new file mode 100644 index 000000000000..dfd9c5ea1584 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/graniterapids/frontend.json @@ -0,0 +1,10 @@ +[ + { + "BriefDescription": "This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations.", + "EventCode": "0x9c", + "EventName": "IDQ_BUBBLES.CORE", + "PublicDescription": "This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations.\nThe count may be distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the nominator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.", + "SampleAfterValue": "1000003", + "UMask": "0x1" + } +] diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/memory.json b/tools/perf/pmu-events/arch/x86/graniterapids/memory.json new file mode 100644 index 000000000000..1c0e0e86e58e --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/graniterapids/memory.json @@ -0,0 +1,174 @@ +[ + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "1009", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "20011", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "503", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "101", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "2003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "50021", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE", + "PEBS": "2", + "PublicDescription": "Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_RFO.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FC00002", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of times an RTM execution aborted.", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED", + "PublicDescription": "Counts the number of times RTM abort was triggered.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of times an RTM execution successfully committed", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.COMMIT", + "PublicDescription": "Counts the number of times RTM commit succeeded.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of times an RTM execution started.", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.START", + "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_READ", + "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads", + "SampleAfterValue": "100003", + "UMask": "0x80" + }, + { + "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CONFLICT", + "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", + "SampleAfterValue": "100003", + "UMask": "0x1" + } +] diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/other.json b/tools/perf/pmu-events/arch/x86/graniterapids/other.json new file mode 100644 index 000000000000..5e799bae03ea --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/graniterapids/other.json @@ -0,0 +1,29 @@ +[ + { + "BriefDescription": "Counts demand data reads that have any type of response.", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FFC0002", + "SampleAfterValue": "100003", + "UMask": "0x1" + } +] diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/pipeline.json b/tools/perf/pmu-events/arch/x86/graniterapids/pipeline.json new file mode 100644 index 000000000000..d6aafb258708 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/graniterapids/pipeline.json @@ -0,0 +1,102 @@ +[ + { + "BriefDescription": "All branch instructions retired.", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "PublicDescription": "Counts all branch instructions retired.", + "SampleAfterValue": "400009" + }, + { + "BriefDescription": "All mispredicted branch instructions retired.", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", + "SampleAfterValue": "400009" + }, + { + "BriefDescription": "Reference cycles when the core is not in halt state.", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "Reference cycles when the core is not in halt state.", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", + "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Core cycles when the thread is not in halt state", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Thread cycles when thread is not in halt state", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", + "EventName": "INST_RETIRED.ANY", + "PEBS": "1", + "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.ANY_P", + "PEBS": "1", + "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", + "SampleAfterValue": "100003", + "UMask": "0x82" + }, + { + "BriefDescription": "This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions.", + "EventCode": "0xa4", + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", + "PublicDescription": "This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions.\nThe count is distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the nominator for the Backend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.", + "SampleAfterValue": "10000003", + "UMask": "0x2" + }, + { + "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", + "EventName": "TOPDOWN.SLOTS", + "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", + "SampleAfterValue": "10000003", + "UMask": "0x4" + }, + { + "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", + "EventCode": "0xa4", + "EventName": "TOPDOWN.SLOTS_P", + "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", + "SampleAfterValue": "10000003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric.", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.SLOTS", + "PublicDescription": "This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric.\nSoftware can use this event as the nominator for the Retiring metric (or top-level category) of the Top-down Microarchitecture Analysis method.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + } +] diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/virtual-memory.json b/tools/perf/pmu-events/arch/x86/graniterapids/virtual-memory.json new file mode 100644 index 000000000000..8784c97b7534 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/graniterapids/virtual-memory.json @@ -0,0 +1,26 @@ +[ + { + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", + "EventCode": "0x12", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0xe" + }, + { + "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", + "EventCode": "0x13", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0xe" + }, + { + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", + "EventCode": "0x11", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0xe" + } +] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 793076e00188..1677ec22e2e3 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -9,6 +9,7 @@ GenuineIntel-6-55-[56789ABCDEF],v1.17,cascadelakex,core GenuineIntel-6-9[6C],v1.03,elkhartlake,core GenuineIntel-6-5[CF],v13,goldmont,core GenuineIntel-6-7A,v1.01,goldmontplus,core +GenuineIntel-6-A[DE],v1.00,graniterapids,core GenuineIntel-6-(3C|45|46),v32,haswell,core GenuineIntel-6-3F,v26,haswellx,core GenuineIntel-6-(7D|7E|A7),v1.15,icelake,core -- cgit v1.2.3-58-ga151 From 2f244993435516a46a1c1d45030781de69b372fd Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:14 -0800 Subject: perf vendor events intel: Refresh haswell metrics Update the haswell metrics to TMA version 4.5. Generation was done using https://github.com/intel/perfmon. Notable changes are TMA info metrics are renamed from their node name to be lower case and prefixed by tma_info_, MetricThreshold expressions are added, and the smi_cost metric group is added replicating existing hard coded metrics in stat-shadow. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-18-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/haswell/hsw-metrics.json | 1220 +++++++++++--------- 1 file changed, 687 insertions(+), 533 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json b/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json index 2e032beee542..2528418200bb 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json +++ b/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json @@ -1,799 +1,953 @@ [ { - "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", - "MetricGroup": "PGO;TopdownL1;tma_L1_group", - "MetricName": "tma_frontend_bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", - "MetricExpr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / SLOTS", - "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_latency", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", + "BriefDescription": "C2 residency percent per package", + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C2_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", - "MetricExpr": "ICACHE.IFDATA_STALL / CLKS", - "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_icache_misses", + "BriefDescription": "C3 residency percent per core", + "MetricExpr": "cstate_core@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", - "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / CLKS", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_itlb_misses", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED", + "BriefDescription": "C3 residency percent per package", + "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", - "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / CLKS", - "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_branch_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_dsb_switches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", - "MetricExpr": "ILD_STALL.LCP / CLKS", - "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_lcp", - "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", + "BriefDescription": "C7 residency percent per core", + "MetricExpr": "cstate_core@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", - "MetricExpr": "2 * IDQ.MS_SWITCHES / CLKS", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_ms_switches", - "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES", + "BriefDescription": "C7 residency percent per package", + "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", - "MetricExpr": "tma_frontend_bound - tma_fetch_latency", - "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_bandwidth", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", - "ScaleUnit": "100%" + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "tma_info_socket_clks / #num_dies / duration_time / 1e9", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", - "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2", - "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_group", - "MetricName": "tma_mite", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", + "BriefDescription": "Percentage of cycles spent in System Management Interrupts.", + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", + "MetricGroup": "smi", + "MetricName": "smi_cycles", + "MetricThreshold": "smi_cycles > 0.1", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", - "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2", - "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group", - "MetricName": "tma_dsb", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", - "ScaleUnit": "100%" + "BriefDescription": "Number of SMI interrupts.", + "MetricExpr": "msr@smi@", + "MetricGroup": "smi", + "MetricName": "smi_num", + "ScaleUnit": "1SMI#" }, { - "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", - "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_bad_speculation", - "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", + "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_4k_aliasing", + "MetricThreshold": "tma_4k_aliasing > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_branch_mispredicts", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / tma_info_slots", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_alu_op_utilization", + "MetricThreshold": "tma_alu_op_utilization > 0.6", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", - "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_machine_clears", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT", + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", + "MetricExpr": "100 * OTHER_ASSISTS.ANY_WB_ASSIST / tma_info_slots", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_assists", + "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY", "ScaleUnit": "100%" }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)", - "MetricGroup": "TopdownL1;tma_L1_group", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", + "MetricThreshold": "tma_backend_bound > 0.2", "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", - "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if IPC > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB) if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if IPC > 1.8 else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB))) * tma_backend_bound", - "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_memory_bound", - "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", - "MetricExpr": "max((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) - CYCLE_ACTIVITY.STALLS_L1D_PENDING) / CLKS, 0)", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l1_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT_PS;MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", - "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / CLKS", - "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_dtlb_load", - "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", - "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_store_fwd_blk", - "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", - "MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS", - "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_lock_latency", - "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", - "MetricExpr": "Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_split_loads", - "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_UOPS_RETIRED.SPLIT_LOADS_PS", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", - "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_4k_aliasing", - "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", + "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_bad_speculation", + "MetricThreshold": "tma_bad_speculation > 0.15", + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", - "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.REQUEST_FB_FULL\\,cmask\\=1@ / CLKS", - "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_fb_full", - "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).", + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", + "MetricName": "tma_branch_mispredicts", + "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING) / CLKS", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l2_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", + "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_branch_resteers", + "MetricThreshold": "tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", - "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l3_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS", + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_cisc", + "MetricThreshold": "tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", - "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / CLKS", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS)))) / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", "MetricName": "tma_contested_accesses", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS", + "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", - "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_data_sharing", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS", + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_backend_bound - tma_memory_bound", + "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", - "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / CLKS", - "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_l3_hit_latency", - "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / tma_info_clks", + "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_data_sharing", + "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", - "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_sq_full", - "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.", + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", + "MetricExpr": "10 * ARITH.DIVIDER_UOPS / tma_info_core_clks", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_divider", + "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", - "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", + "MetricConstraint": "NO_GROUP_EVENTS_SMT", + "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_dram_bound", + "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=6@) / CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group", - "MetricName": "tma_mem_bandwidth", - "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", + "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / tma_info_core_clks / 2", + "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_dsb", + "MetricThreshold": "tma_dsb > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group", - "MetricName": "tma_mem_latency", - "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_clks", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_dsb_switches", + "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Related metrics: tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", - "MetricExpr": "RESOURCE_STALLS.SB / CLKS", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_store_bound", - "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES_PS", + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", + "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group", + "MetricName": "tma_dtlb_load", + "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", - "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group", - "MetricName": "tma_store_latency", - "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", + "MetricExpr": "(8 * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION) / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group", + "MetricName": "tma_dtlb_store", + "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", - "MetricExpr": "60 * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE / CLKS", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group", + "MetricExpr": "60 * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group", "MetricName": "tma_false_sharing", - "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents rate of split store accesses", - "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / CORE_CLKS", - "MetricGroup": "TopdownL4;tma_store_bound_group", - "MetricName": "tma_split_stores", - "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_UOPS_RETIRED.SPLIT_STORES_PS", + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_info_load_miss_real_latency * cpu@L1D_PEND_MISS.REQUEST_FB_FULL\\,cmask\\=1@ / tma_info_clks", + "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricName": "tma_fb_full", + "MetricThreshold": "tma_fb_full > 0.3", + "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", - "MetricExpr": "(8 * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION) / CLKS", - "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group", - "MetricName": "tma_dtlb_store", - "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS", + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", + "MetricExpr": "tma_frontend_bound - tma_fetch_latency", + "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", + "MetricName": "tma_fetch_bandwidth", + "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", - "MetricExpr": "tma_backend_bound - tma_memory_bound", - "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_core_bound", - "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", + "MetricExpr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / tma_info_slots", + "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_latency", + "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", - "MetricExpr": "10 * ARITH.DIVIDER_UOPS / CORE_CLKS", - "MetricGroup": "TopdownL3;tma_core_bound_group", - "MetricName": "tma_divider", - "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS", + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_slots", + "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.15", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", - "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if IPC > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB) if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if IPC > 1.8 else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / CLKS", - "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group", - "MetricName": "tma_ports_utilization", - "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences", + "MetricExpr": "tma_microcode_sequencer", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_heavy_operations", + "MetricThreshold": "tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) / CORE_CLKS)", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_0", - "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", + "MetricExpr": "ICACHE.IFDATA_STALL / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_icache_misses", + "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / CORE_CLKS)", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_1", - "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", - "ScaleUnit": "100%" + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "tma_info_turbo_utilization * TSC / 1e9 / duration_time", + "MetricGroup": "Power;Summary", + "MetricName": "tma_info_average_frequency" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / CORE_CLKS)", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_2", - "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", - "ScaleUnit": "100%" + "BriefDescription": "Branch instructions per taken branch.", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_bptkbranch" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", - "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_3m", - "ScaleUnit": "100%" + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline", + "MetricName": "tma_info_clks" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_alu_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else tma_info_clks))", + "MetricGroup": "SMT", + "MetricName": "tma_info_core_clks" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) Sample with: UOPS_DISPATCHED_PORT.PORT_0", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS", - "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_0", - "ScaleUnit": "100%" + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_core_clks", + "MetricGroup": "Ret;SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_coreipc" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_1", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_1", - "ScaleUnit": "100%" + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / tma_info_ipc", + "MetricGroup": "Mem;Pipeline", + "MetricName": "tma_info_cpi" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) Sample with: UOPS_DISPATCHED.PORT_5", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_5", - "ScaleUnit": "100%" + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "HPC;Summary", + "MetricName": "tma_info_cpu_utilization" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_6", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_6", - "ScaleUnit": "100%" + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_data_l2_mlp" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations Sample with: UOPS_DISPATCHED.PORT_2_3", - "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_load_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;tma_issueBW", + "MetricName": "tma_info_dram_bw_use", + "PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_mem_bandwidth, tma_sq_full" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_2", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_load_op_utilization_group", - "MetricName": "tma_port_2", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", + "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", + "MetricName": "tma_info_dsb_coverage", + "MetricThreshold": "tma_info_dsb_coverage < 0.7 & tma_info_ipc / 4 > 0.35", + "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_iptb, tma_lcp" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_3", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_load_op_utilization_group", - "MetricName": "tma_port_3", - "ScaleUnit": "100%" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", + "MetricExpr": "(UOPS_EXECUTED.CORE / 2 / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@) if #SMT_on else UOPS_EXECUTED.CORE / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@))", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", + "MetricName": "tma_info_ilp" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", - "MetricExpr": "tma_port_4", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_store_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;tma_L1_group", + "MetricName": "tma_info_instructions", + "PublicDescription": "Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data) Sample with: UOPS_DISPATCHED_PORT.PORT_4", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_store_op_utilization_group", - "MetricName": "tma_port_4", - "ScaleUnit": "100%" - }, + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "tma_info_ipbranch", + "MetricThreshold": "tma_info_ipbranch < 8" + }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address) Sample with: UOPS_DISPATCHED_PORT.PORT_7", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_store_op_utilization_group", - "MetricName": "tma_port_7", - "ScaleUnit": "100%" + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_clks", + "MetricGroup": "Ret;Summary", + "MetricName": "tma_info_ipc" }, { - "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_ipcall", + "MetricThreshold": "tma_info_ipcall < 200" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", - "MetricExpr": "tma_retiring - tma_heavy_operations", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_light_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "tma_info_ipfarbranch", + "MetricThreshold": "tma_info_ipfarbranch < 1e6" }, { - "BriefDescription": "This metric serves as an approximation of legacy x87 usage", - "MetricExpr": "INST_RETIRED.X87 * UPI / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_x87_use", - "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipload", + "MetricThreshold": "tma_info_ipload < 3" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences", - "MetricExpr": "tma_microcode_sequencer", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_heavy_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "tma_info_instructions / (UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * cpu@BR_MISP_EXEC.ALL_BRANCHES\\,umask\\=0xE4@)", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_indirect", + "MetricThreshold": "tma_info_ipmisp_indirect < 1e3" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS", - "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group", - "MetricName": "tma_microcode_sequencer", - "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS", - "ScaleUnit": "100%" + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "tma_info_ipmispredict", + "MetricThreshold": "tma_info_ipmispredict < 200" }, { - "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", - "MetricExpr": "100 * OTHER_ASSISTS.ANY_WB_ASSIST / SLOTS", - "MetricGroup": "TopdownL4;tma_microcode_sequencer_group", - "MetricName": "tma_assists", - "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipstore", + "MetricThreshold": "tma_info_ipstore < 8" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", - "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", - "MetricGroup": "TopdownL4;tma_microcode_sequencer_group", - "MetricName": "tma_cisc", - "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", - "ScaleUnit": "100%" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", + "MetricName": "tma_info_iptb", + "MetricThreshold": "tma_info_iptb < 9", + "PublicDescription": "Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_lcp" }, { - "BriefDescription": "Instructions Per Cycle (per Logical Processor)", - "MetricExpr": "INST_RETIRED.ANY / CLKS", - "MetricGroup": "Ret;Summary", - "MetricName": "IPC" + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "tma_info_instructions / BACLEARS.ANY", + "MetricGroup": "Fed", + "MetricName": "tma_info_ipunknown_branch" }, { - "BriefDescription": "Uops Per Instruction", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Ret;Retire", - "MetricName": "UPI" + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_cpi" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW", - "MetricName": "UpTB" + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_utilization", + "MetricThreshold": "tma_info_kernel_utilization > 0.05" }, { - "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / IPC", - "MetricGroup": "Mem;Pipeline", - "MetricName": "CPI" + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw" }, { - "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Pipeline", - "MetricName": "CLKS" + "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "tma_info_l1d_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw_1t" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", - "MetricExpr": "4 * CORE_CLKS", - "MetricGroup": "tma_L1_group", - "MetricName": "SLOTS" + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l1mpki" }, { - "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS", - "MetricGroup": "Ret;SMT;tma_L1_group", - "MetricName": "CoreIPC" + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw" }, { - "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", - "MetricExpr": "(UOPS_EXECUTED.CORE / 2 / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@) if #SMT_on else UOPS_EXECUTED.CORE / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@))", - "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", - "MetricName": "ILP" + "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "tma_info_l2_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw_1t" }, { - "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", - "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))", - "MetricGroup": "SMT", - "MetricName": "CORE_CLKS" + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Backend;CacheMisses;Mem", + "MetricName": "tma_info_l2mpki" }, { - "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricGroup": "InsType", - "MetricName": "IpLoad" + "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "0", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_l3_cache_access_bw_1t" }, { - "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", - "MetricGroup": "InsType", - "MetricName": "IpStore" + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw" }, { - "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Fed;InsType", - "MetricName": "IpBranch" + "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_l3_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw_1t" }, { - "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "IpCall" + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l3mpki" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", - "MetricName": "IpTB" + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore", + "MetricName": "tma_info_load_l2_miss_latency" }, { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "BpTkBranch" + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_load_l2_mlp" }, { - "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary;tma_L1_group", - "MetricName": "Instructions" + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "tma_info_load_miss_real_latency" + }, + { + "BriefDescription": "Average number of parallel requests to external memory", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", + "MetricGroup": "Mem;SoC", + "MetricName": "tma_info_mem_parallel_requests", + "PublicDescription": "Average number of parallel requests to external memory. Accounts for all requests" + }, + { + "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL", + "MetricGroup": "Mem;SoC", + "MetricName": "tma_info_mem_request_latency" + }, + { + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBW;MemoryBound", + "MetricName": "tma_info_mlp", + "PublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION) / tma_info_core_clks", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_page_walks_utilization", + "MetricThreshold": "tma_info_page_walks_utilization > 0.5" }, { "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@", "MetricGroup": "Pipeline;Ret", - "MetricName": "Retire" + "MetricName": "tma_info_retire" }, { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "DSB;Fed;FetchBW", - "MetricName": "DSB_Coverage" + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * tma_info_core_clks", + "MetricGroup": "TmaL1;tma_L1_group", + "MetricName": "tma_info_slots" }, { - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", + "MetricGroup": "SMT", + "MetricName": "tma_info_smt_2t_utilization" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)", - "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency" + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "UNC_CLOCK.SOCKET", + "MetricGroup": "SoC", + "MetricName": "tma_info_socket_clks" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "Mem;MemoryBW;MemoryBound", - "MetricName": "MLP" + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "tma_info_clks / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power", + "MetricName": "tma_info_turbo_utilization" }, { - "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI" + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire", + "MetricName": "tma_info_uoppi", + "MetricThreshold": "tma_info_uoppi > 1.05" }, { - "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Backend;CacheMisses;Mem", - "MetricName": "L2MPKI" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "tma_info_uptb", + "MetricThreshold": "tma_info_uptb < 6" }, { - "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L3MPKI" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", + "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED", + "ScaleUnit": "100%" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION) / CORE_CLKS", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "Page_Walks_Utilization" + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", + "MetricExpr": "max((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) - CYCLE_ACTIVITY.STALLS_L1D_PENDING) / tma_info_clks, 0)", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group", + "MetricName": "tma_l1_bound", + "MetricThreshold": "tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT_PS;MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" + "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING) / tma_info_clks", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l2_bound", + "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", + "MetricConstraint": "NO_GROUP_EVENTS_SMT", + "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_clks", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l3_bound", + "MetricThreshold": "tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" + "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.L3_MISS))) / tma_info_clks", + "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group", + "MetricName": "tma_l3_hit_latency", + "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS. Related metrics: tma_mem_latency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "L1D_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW_1T" + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", + "MetricExpr": "ILD_STALL.LCP / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_lcp", + "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_iptb", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "L2_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW_1T" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", + "MetricExpr": "tma_retiring - tma_heavy_operations", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_light_operations", + "MetricThreshold": "tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW_1T" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_load_op_utilization", + "MetricThreshold": "tma_load_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "0", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW_1T" + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / tma_info_clks", + "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group", + "MetricName": "tma_lock_latency", + "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average CPU Utilization", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", - "MetricGroup": "HPC;Summary", - "MetricName": "CPU_Utilization" + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", + "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", - "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time", - "MetricGroup": "Power;Summary", - "MetricName": "Average_Frequency" + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=6@) / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW", + "MetricName": "tma_mem_bandwidth", + "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_sq_full", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average Frequency Utilization relative nominal frequency", - "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC", - "MetricGroup": "Power", - "MetricName": "Turbo_Utilization" + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_clks - tma_mem_bandwidth", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat", + "MetricName": "tma_mem_latency", + "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_l3_hit_latency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", - "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", - "MetricGroup": "SMT", - "MetricName": "SMT_2T_Utilization" + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - (cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if tma_info_ipc > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@)) / 2 - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) if #SMT_on else min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - (cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if tma_info_ipc > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound", + "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_memory_bound", + "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "OS", - "MetricName": "Kernel_Utilization" + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_slots", + "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS", + "MetricName": "tma_microcode_sequencer", + "MetricThreshold": "tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches", + "ScaleUnit": "100%" }, { - "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", - "MetricGroup": "OS", - "MetricName": "Kernel_CPI" + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", + "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / tma_info_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_mite", + "MetricThreshold": "tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", - "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3", - "MetricGroup": "HPC;Mem;MemoryBW;SoC", - "MetricName": "DRAM_BW_Use" + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", + "MetricExpr": "2 * IDQ.MS_SWITCHES / tma_info_clks", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", + "MetricName": "tma_ms_switches", + "MetricThreshold": "tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)", - "MetricExpr": "MEM_Parallel_Requests", - "MetricGroup": "Mem;SoC", - "MetricName": "MEM_Request_Latency" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / tma_info_core_clks", + "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_0", + "MetricThreshold": "tma_port_0 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED_PORT.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_512b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests", - "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL", - "MetricGroup": "Mem;SoC", - "MetricName": "MEM_Parallel_Requests" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_1", + "MetricThreshold": "tma_port_1 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_512b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Socket actual clocks when any core is active on that socket", - "MetricExpr": "UNC_CLOCK.SOCKET", - "MetricGroup": "SoC", - "MetricName": "Socket_CLKS" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", + "MetricName": "tma_port_2", + "MetricThreshold": "tma_port_2 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", - "MetricGroup": "Branches;OS", - "MetricName": "IpFarBranch" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", + "MetricName": "tma_port_3", + "MetricThreshold": "tma_port_3 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_3", + "ScaleUnit": "100%" }, { - "BriefDescription": "Uncore frequency per die [GHZ]", - "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9", - "MetricGroup": "SoC", - "MetricName": "UNCORE_FREQ" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)", + "MetricExpr": "tma_store_op_utilization", + "MetricGroup": "TopdownL6;tma_L6_group;tma_issueSpSt;tma_store_op_utilization_group", + "MetricName": "tma_port_4", + "MetricThreshold": "tma_port_4 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Sample with: UOPS_DISPATCHED_PORT.PORT_4. Related metrics: tma_split_stores", + "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per core", - "MetricExpr": "cstate_core@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Core_Residency", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_5", + "MetricThreshold": "tma_port_5 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Sample with: UOPS_DISPATCHED.PORT_5. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per core", - "MetricExpr": "cstate_core@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Core_Residency", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_6", + "MetricThreshold": "tma_port_6 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per core", - "MetricExpr": "cstate_core@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Core_Residency", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group", + "MetricName": "tma_port_7", + "MetricThreshold": "tma_port_7 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address). Sample with: UOPS_DISPATCHED_PORT.PORT_7", "ScaleUnit": "100%" }, { - "BriefDescription": "C2 residency percent per package", - "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C2_Pkg_Residency", + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - (cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if tma_info_ipc > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@)) / 2 - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB if #SMT_on else min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - (cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if tma_info_ipc > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_ports_utilization", + "MetricThreshold": "tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per package", - "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Pkg_Residency", + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0)) / tma_info_core_clks)", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_0", + "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per package", - "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Pkg_Residency", + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / tma_info_core_clks)", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_1", + "MetricThreshold": "tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Related metrics: tma_l1_bound", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per package", - "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Pkg_Residency", + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / tma_info_core_clks)", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_2", + "MetricThreshold": "tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", + "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / tma_info_core_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_3m", + "MetricThreshold": "tma_ports_utilized_3m > 0.7 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_info_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_split_loads", + "MetricThreshold": "tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_UOPS_RETIRED.SPLIT_LOADS_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents rate of split store accesses", + "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / tma_info_core_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group", + "MetricName": "tma_split_stores", + "MetricThreshold": "tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_UOPS_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", + "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group", + "MetricName": "tma_sq_full", + "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_mem_bandwidth", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", + "MetricExpr": "RESOURCE_STALLS.SB / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_store_bound", + "MetricThreshold": "tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", + "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_store_fwd_blk", + "MetricThreshold": "tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_clks", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group", + "MetricName": "tma_store_latency", + "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / tma_info_core_clks", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_store_op_utilization", + "MetricThreshold": "tma_store_op_utilization > 0.6", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric serves as an approximation of legacy x87 usage", + "MetricExpr": "INST_RETIRED.X87 * tma_info_uoppi / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_x87_use", + "MetricThreshold": "tma_x87_use > 0.1", + "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", "ScaleUnit": "100%" } ] -- cgit v1.2.3-58-ga151 From 05dd42fe61453bf23b548e9cd10e8b94b33ab121 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:15 -0800 Subject: perf vendor events intel: Refresh haswellx metrics Update the haswellx metrics to TMA version 4.5. Generation was done using https://github.com/intel/perfmon. Notable changes are TMA info metrics are renamed from their node name to be lower case and prefixed by tma_info_, MetricThreshold expressions are added and "Sample with" documentation is added to many TMA metrics, and the smi_cost metric group is added replicating existing hard coded metrics in stat-shadow. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-19-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/haswellx/hsx-metrics.json | 1397 ++++++++++---------- 1 file changed, 679 insertions(+), 718 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json b/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json index 2e1fbc936d25..11f152c346eb 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json @@ -1,1023 +1,984 @@ [ { - "BriefDescription": "Instructions Per Cycle (per Logical Processor)", - "MetricExpr": "INST_RETIRED.ANY / CLKS", - "MetricGroup": "Ret;Summary", - "MetricName": "IPC" - }, - { - "BriefDescription": "Uops Per Instruction", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Ret;Retire", - "MetricName": "UPI" - }, - { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW", - "MetricName": "UpTB" - }, - { - "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / IPC", - "MetricGroup": "Mem;Pipeline", - "MetricName": "CPI" - }, - { - "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Pipeline", - "MetricName": "CLKS" - }, - { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", - "MetricExpr": "4 * CORE_CLKS", - "MetricGroup": "tma_L1_group", - "MetricName": "SLOTS" - }, - { - "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS", - "MetricGroup": "Ret;SMT;tma_L1_group", - "MetricName": "CoreIPC" - }, - { - "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", - "MetricExpr": "(UOPS_EXECUTED.CORE / 2 / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@) if #SMT_on else UOPS_EXECUTED.CORE / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@))", - "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", - "MetricName": "ILP" - }, - { - "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", - "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))", - "MetricGroup": "SMT", - "MetricName": "CORE_CLKS" - }, - { - "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricGroup": "InsType", - "MetricName": "IpLoad" - }, - { - "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", - "MetricGroup": "InsType", - "MetricName": "IpStore" - }, - { - "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Fed;InsType", - "MetricName": "IpBranch" - }, - { - "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "IpCall" - }, - { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", - "MetricName": "IpTB" - }, - { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "BpTkBranch" - }, - { - "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary;tma_L1_group", - "MetricName": "Instructions" - }, - { - "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@", - "MetricGroup": "Pipeline;Ret", - "MetricName": "Retire" + "BriefDescription": "C2 residency percent per package", + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C2_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "DSB;Fed;FetchBW", - "MetricName": "DSB_Coverage" + "BriefDescription": "C3 residency percent per core", + "MetricExpr": "cstate_core@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Core_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" + "BriefDescription": "C3 residency percent per package", + "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)", - "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency" + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "Mem;MemoryBW;MemoryBound", - "MetricName": "MLP" + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI" + "BriefDescription": "C7 residency percent per core", + "MetricExpr": "cstate_core@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Core_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Backend;CacheMisses;Mem", - "MetricName": "L2MPKI" + "BriefDescription": "C7 residency percent per package", + "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L3MPKI" + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "tma_info_socket_clks / #num_dies / duration_time / 1e9", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION) / CORE_CLKS", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "Page_Walks_Utilization" + "BriefDescription": "Percentage of cycles spent in System Management Interrupts.", + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", + "MetricGroup": "smi", + "MetricName": "smi_cycles", + "MetricThreshold": "smi_cycles > 0.1", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" + "BriefDescription": "Number of SMI interrupts.", + "MetricExpr": "msr@smi@", + "MetricGroup": "smi", + "MetricName": "smi_num", + "ScaleUnit": "1SMI#" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" + "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", + "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_4k_aliasing", + "MetricThreshold": "tma_4k_aliasing > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / tma_info_slots", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_alu_op_utilization", + "MetricThreshold": "tma_alu_op_utilization > 0.6", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "L1D_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW_1T" + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", + "MetricExpr": "100 * OTHER_ASSISTS.ANY_WB_ASSIST / tma_info_slots", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_assists", + "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "L2_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW_1T" + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_backend_bound", + "MetricThreshold": "tma_backend_bound > 0.2", + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW_1T" + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", + "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_bad_speculation", + "MetricThreshold": "tma_bad_speculation > 0.15", + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "0", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW_1T" + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", + "MetricName": "tma_branch_mispredicts", + "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_mispredicts_resteers", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average CPU Utilization", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", - "MetricGroup": "HPC;Summary", - "MetricName": "CPU_Utilization" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", + "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_branch_resteers", + "MetricThreshold": "tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "ScaleUnit": "100%" }, { - "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", - "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time", - "MetricGroup": "Power;Summary", - "MetricName": "Average_Frequency" + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_cisc", + "MetricThreshold": "tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average Frequency Utilization relative nominal frequency", - "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC", - "MetricGroup": "Power", - "MetricName": "Turbo_Utilization" + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_contested_accesses", + "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", - "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", - "MetricGroup": "SMT", - "MetricName": "SMT_2T_Utilization" + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_backend_bound - tma_memory_bound", + "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "OS", - "MetricName": "Kernel_Utilization" + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / tma_info_clks", + "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_data_sharing", + "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", - "MetricGroup": "OS", - "MetricName": "Kernel_CPI" + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", + "MetricExpr": "10 * ARITH.DIVIDER_UOPS / tma_info_core_clks", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_divider", + "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", - "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time", - "MetricGroup": "HPC;Mem;MemoryBW;SoC", - "MetricName": "DRAM_BW_Use" + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", + "MetricConstraint": "NO_GROUP_EVENTS_SMT", + "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_dram_bound", + "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches", - "MetricExpr": "1e9 * (UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_INSERTS.MISS_OPCODE@filter_opc\\=0x182@) / (Socket_CLKS / duration_time)", - "MetricGroup": "Mem;MemoryLat;SoC", - "MetricName": "MEM_Read_Latency" + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", + "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / tma_info_core_clks / 2", + "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_dsb", + "MetricThreshold": "tma_dsb > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", - "MetricExpr": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182\\,thresh\\=1@", - "MetricGroup": "Mem;MemoryBW;SoC", - "MetricName": "MEM_Parallel_Reads" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_clks", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_dsb_switches", + "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Related metrics: tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", + "ScaleUnit": "100%" }, { - "BriefDescription": "Socket actual clocks when any core is active on that socket", - "MetricExpr": "cbox_0@event\\=0x0@", - "MetricGroup": "SoC", - "MetricName": "Socket_CLKS" + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", + "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group", + "MetricName": "tma_dtlb_load", + "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", - "MetricGroup": "Branches;OS", - "MetricName": "IpFarBranch" + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", + "MetricExpr": "(8 * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION) / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group", + "MetricName": "tma_dtlb_store", + "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load", + "ScaleUnit": "100%" }, { - "BriefDescription": "Uncore frequency per die [GHZ]", - "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9", - "MetricGroup": "SoC", - "MetricName": "UNCORE_FREQ" + "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", + "MetricExpr": "(200 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE) / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group", + "MetricName": "tma_false_sharing", + "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "CPU operating frequency (in GHz)", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / duration_time", - "MetricName": "cpu_operating_frequency", - "ScaleUnit": "1GHz" + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_info_load_miss_real_latency * cpu@L1D_PEND_MISS.REQUEST_FB_FULL\\,cmask\\=1@ / tma_info_clks", + "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricName": "tma_fb_full", + "MetricThreshold": "tma_fb_full > 0.3", + "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", + "ScaleUnit": "100%" }, { - "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY", - "MetricName": "cpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", + "MetricExpr": "tma_frontend_bound - tma_fetch_latency", + "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", + "MetricName": "tma_fetch_bandwidth", + "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", + "ScaleUnit": "100%" }, { - "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions", - "MetricExpr": "MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY", - "MetricName": "loads_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", + "MetricExpr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / tma_info_slots", + "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_latency", + "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", + "ScaleUnit": "100%" }, { - "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions", - "MetricExpr": "MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY", - "MetricName": "stores_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_slots", + "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.15", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions", - "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY", - "MetricName": "l1d_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences", + "MetricExpr": "tma_microcode_sequencer", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_heavy_operations", + "MetricThreshold": "tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions", - "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L1_HIT / INST_RETIRED.ANY", - "MetricName": "l1d_demand_data_read_hits_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", + "MetricExpr": "ICACHE.IFDATA_STALL / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_icache_misses", + "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "ScaleUnit": "100%" }, { - "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions", - "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY", - "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "tma_info_turbo_utilization * TSC / 1e9 / duration_time", + "MetricGroup": "Power;Summary", + "MetricName": "tma_info_average_frequency" }, { - "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions", - "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_HIT / INST_RETIRED.ANY", - "MetricName": "l2_demand_data_read_hits_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Branch instructions per taken branch.", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_bptkbranch" }, { - "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions", - "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY", - "MetricName": "l2_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline", + "MetricName": "tma_info_clks" }, { - "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions", - "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricName": "l2_demand_data_read_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else tma_info_clks))", + "MetricGroup": "SMT", + "MetricName": "tma_info_core_clks" }, { - "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions", - "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", - "MetricName": "l2_demand_code_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_core_clks", + "MetricGroup": "Ret;SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_coreipc" }, { - "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds", - "MetricExpr": "1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time", - "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency", - "ScaleUnit": "1ns" + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / tma_info_ipc", + "MetricGroup": "Mem;Pipeline", + "MetricName": "tma_info_cpi" }, { - "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds", - "MetricExpr": "1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time", - "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests", - "ScaleUnit": "1ns" + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "HPC;Summary", + "MetricName": "tma_info_cpu_utilization" }, { - "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds", - "MetricExpr": "1e9 * (cbox@UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@) / (UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time", - "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests", - "ScaleUnit": "1ns" + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_data_l2_mlp" }, { - "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions", - "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", - "MetricName": "itlb_mpi", - "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;tma_issueBW", + "MetricName": "tma_info_dram_bw_use", + "PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_mem_bandwidth, tma_sq_full" }, { - "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions", - "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY", - "MetricName": "itlb_large_page_mpi", - "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", + "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", + "MetricName": "tma_info_dsb_coverage", + "MetricThreshold": "tma_info_dsb_coverage < 0.7 & tma_info_ipc / 4 > 0.35", + "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_iptb, tma_lcp" }, { - "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions", - "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", - "MetricName": "dtlb_load_mpi", - "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", + "MetricExpr": "(UOPS_EXECUTED.CORE / 2 / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@) if #SMT_on else UOPS_EXECUTED.CORE / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@))", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", + "MetricName": "tma_info_ilp" }, { - "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions", - "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", - "MetricName": "dtlb_store_mpi", - "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;tma_L1_group", + "MetricName": "tma_info_instructions", + "PublicDescription": "Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST" }, { - "BriefDescription": "Uncore operating frequency in GHz", - "MetricExpr": "UNC_C_CLOCKTICKS / (#num_cores / #num_packages * #num_packages) / 1e9 / duration_time", - "MetricName": "uncore_frequency", - "ScaleUnit": "1GHz" + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "tma_info_ipbranch", + "MetricThreshold": "tma_info_ipbranch < 8" }, { - "BriefDescription": "Intel(R) Quick Path Interconnect (QPI) data transmit bandwidth (MB/sec)", - "MetricExpr": "UNC_Q_TxL_FLITS_G0.DATA * 8 / 1e6 / duration_time", - "MetricName": "qpi_data_transmit_bw", - "ScaleUnit": "1MB/s" + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_clks", + "MetricGroup": "Ret;Summary", + "MetricName": "tma_info_ipc" }, { - "BriefDescription": "DDR memory read bandwidth (MB/sec)", - "MetricExpr": "UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time", - "MetricName": "memory_bandwidth_read", - "ScaleUnit": "1MB/s" + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_ipcall", + "MetricThreshold": "tma_info_ipcall < 200" }, { - "BriefDescription": "DDR memory write bandwidth (MB/sec)", - "MetricExpr": "UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time", - "MetricName": "memory_bandwidth_write", - "ScaleUnit": "1MB/s" + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "tma_info_ipfarbranch", + "MetricThreshold": "tma_info_ipfarbranch < 1e6" }, { - "BriefDescription": "DDR memory bandwidth (MB/sec)", - "MetricExpr": "(UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e6 / duration_time", - "MetricName": "memory_bandwidth_total", - "ScaleUnit": "1MB/s" + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipload", + "MetricThreshold": "tma_info_ipload < 3" }, { - "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.", - "MetricExpr": "cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x19e@ * 64 / 1e6 / duration_time", - "MetricName": "io_bandwidth_disk_or_network_writes", - "ScaleUnit": "1MB/s" + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "tma_info_instructions / (UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * cpu@BR_MISP_EXEC.ALL_BRANCHES\\,umask\\=0xE4@)", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_indirect", + "MetricThreshold": "tma_info_ipmisp_indirect < 1e3" }, { - "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.", - "MetricExpr": "cbox@UNC_C_TOR_INSERTS.OPCODE\\,filter_opc\\=0x1c8\\,filter_tid\\=0x3e@ * 64 / 1e6 / duration_time", - "MetricName": "io_bandwidth_disk_or_network_reads", - "ScaleUnit": "1MB/s" + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "tma_info_ipmispredict", + "MetricThreshold": "tma_info_ipmispredict < 200" }, { - "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue", - "MetricExpr": "IDQ.DSB_UOPS / UOPS_ISSUED.ANY", - "MetricName": "percent_uops_delivered_from_decoded_icache", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipstore", + "MetricThreshold": "tma_info_ipstore < 8" }, { - "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue", - "MetricExpr": "IDQ.MITE_UOPS / UOPS_ISSUED.ANY", - "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline", - "ScaleUnit": "100%" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", + "MetricName": "tma_info_iptb", + "MetricThreshold": "tma_info_iptb < 9", + "PublicDescription": "Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_lcp" }, { - "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue", - "MetricExpr": "IDQ.MS_UOPS / UOPS_ISSUED.ANY", - "MetricName": "percent_uops_delivered_from_microcode_sequencer", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "tma_info_instructions / BACLEARS.ANY", + "MetricGroup": "Fed", + "MetricName": "tma_info_ipunknown_branch" }, { - "BriefDescription": "Uops delivered from loop stream detector(LSD) as a percent of total uops delivered to Instruction Decode Queue", - "MetricExpr": "(UOPS_ISSUED.ANY - IDQ.MITE_UOPS - IDQ.MS_UOPS - IDQ.DSB_UOPS) / UOPS_ISSUED.ANY", - "MetricName": "percent_uops_delivered_from_loop_stream_detector", - "ScaleUnit": "100%" + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_cpi" }, { - "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", - "MetricExpr": "(cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x192@) / INST_RETIRED.ANY", - "MetricName": "llc_data_read_mpi_demand_plus_prefetch", - "ScaleUnit": "1per_instr" + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_utilization", + "MetricThreshold": "tma_info_kernel_utilization > 0.05" }, { - "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", - "MetricExpr": "(cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x181@ + cbox@UNC_C_TOR_INSERTS.MISS_OPCODE\\,filter_opc\\=0x191@) / INST_RETIRED.ANY", - "MetricName": "llc_code_read_mpi_demand_plus_prefetch", - "ScaleUnit": "1per_instr" + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw" }, { - "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", - "MetricExpr": "cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ / (cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@)", - "MetricName": "numa_reads_addressed_to_local_dram", - "ScaleUnit": "100%" + "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "tma_info_l1d_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw_1t" }, { - "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", - "MetricExpr": "cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@ / (cbox@UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE\\,filter_opc\\=0x182@ + cbox@UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE\\,filter_opc\\=0x182@)", - "MetricName": "numa_reads_addressed_to_remote_dram", - "ScaleUnit": "100%" + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l1mpki" }, { - "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", - "MetricGroup": "PGO;TopdownL1;tma_L1_group;tma_L1_group", - "MetricName": "tma_frontend_bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", - "ScaleUnit": "100%" + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", - "MetricExpr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / SLOTS", - "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_latency", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.", - "ScaleUnit": "100%" + "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "tma_info_l2_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw_1t" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", - "MetricExpr": "ICACHE.IFDATA_STALL / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_icache_misses", - "ScaleUnit": "100%" + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Backend;CacheMisses;Mem", + "MetricName": "tma_info_l2mpki" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.", - "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_itlb_misses", - "ScaleUnit": "100%" + "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "0", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_l3_cache_access_bw_1t" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", - "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_branch_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.", - "ScaleUnit": "100%" + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_dsb_switches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", - "ScaleUnit": "100%" + "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_l3_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw_1t" }, { - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", - "MetricExpr": "ILD_STALL.LCP / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_lcp", - "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", - "ScaleUnit": "100%" + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l3mpki" }, { - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", - "MetricExpr": "2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_ms_switches", - "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", - "ScaleUnit": "100%" + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore", + "MetricName": "tma_info_load_l2_miss_latency" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", - "MetricExpr": "tma_frontend_bound - tma_fetch_latency", - "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_bandwidth", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", - "ScaleUnit": "100%" + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_load_l2_mlp" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", - "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2", - "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", - "MetricName": "tma_mite", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", - "ScaleUnit": "100%" + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "tma_info_load_miss_real_latency" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", - "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2", - "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", - "MetricName": "tma_dsb", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", - "ScaleUnit": "100%" + "BriefDescription": "Average number of parallel data read requests to external memory", + "MetricExpr": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182\\,thresh\\=1@", + "MetricGroup": "Mem;MemoryBW;SoC", + "MetricName": "tma_info_mem_parallel_reads", + "PublicDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches" }, { - "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", - "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group", - "MetricName": "tma_bad_speculation", - "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", - "ScaleUnit": "100%" + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds)", + "MetricExpr": "1e9 * (UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_INSERTS.MISS_OPCODE@filter_opc\\=0x182@) / (tma_info_socket_clks / duration_time)", + "MetricGroup": "Mem;MemoryLat;SoC", + "MetricName": "tma_info_mem_read_latency", + "PublicDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_branch_mispredicts", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.", - "ScaleUnit": "100%" + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBW;MemoryBound", + "MetricName": "tma_info_mlp", + "PublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", - "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_machine_clears", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", - "ScaleUnit": "100%" + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION) / tma_info_core_clks", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_page_walks_utilization", + "MetricThreshold": "tma_info_page_walks_utilization > 0.5" }, { - "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", - "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + UOPS_RETIRED.RETIRE_SLOTS / SLOTS)", - "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group", - "MetricName": "tma_backend_bound", - "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", - "ScaleUnit": "100%" + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "tma_info_retire" }, { - "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", - "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - (cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@)) / 2 - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB if #SMT_on else min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - (cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound", - "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_memory_bound", - "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", - "ScaleUnit": "100%" + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * tma_info_core_clks", + "MetricGroup": "TmaL1;tma_L1_group", + "MetricName": "tma_info_slots" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", - "MetricExpr": "max((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) - CYCLE_ACTIVITY.STALLS_L1D_PENDING) / CPU_CLK_UNHALTED.THREAD, 0)", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_l1_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", + "MetricGroup": "SMT", + "MetricName": "tma_info_smt_2t_utilization" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", - "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_dtlb_load", - "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.", - "ScaleUnit": "100%" + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "cbox_0@event\\=0x0@", + "MetricGroup": "SoC", + "MetricName": "tma_info_socket_clks" }, { - "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", - "MetricExpr": "min(13 * LD_BLOCKS.STORE_FORWARD / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_store_fwd_blk", - "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", - "ScaleUnit": "100%" + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "tma_info_clks / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power", + "MetricName": "tma_info_turbo_utilization" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", - "MetricExpr": "min(MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_lock_latency", - "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.", - "ScaleUnit": "100%" + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire", + "MetricName": "tma_info_uoppi", + "MetricThreshold": "tma_info_uoppi > 1.05" }, { - "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ", - "MetricExpr": "min(Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_split_loads", - "ScaleUnit": "100%" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "tma_info_uptb", + "MetricThreshold": "tma_info_uptb < 6" }, { - "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", - "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_4k_aliasing", - "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", + "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", - "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.REQUEST_FB_FULL\\,cmask\\=0x1@ / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_fb_full", - "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).", + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", + "MetricExpr": "max((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) - CYCLE_ACTIVITY.STALLS_L1D_PENDING) / tma_info_clks, 0)", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group", + "MetricName": "tma_l1_bound", + "MetricThreshold": "tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT_PS;MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING) / CPU_CLK_UNHALTED.THREAD", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING) / tma_info_clks", "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.", + "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", - "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CPU_CLK_UNHALTED.THREAD", + "MetricConstraint": "NO_GROUP_EVENTS_SMT", + "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_clks", "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l3_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.", + "MetricThreshold": "tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", - "MetricExpr": "min((60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", - "MetricName": "tma_contested_accesses", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.", + "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "41 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / tma_info_clks", + "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group", + "MetricName": "tma_l3_hit_latency", + "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS. Related metrics: tma_mem_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", - "MetricExpr": "min(43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", - "MetricName": "tma_data_sharing", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.", + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", + "MetricExpr": "ILD_STALL.LCP / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_lcp", + "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_iptb", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", - "MetricExpr": "min(41 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group", - "MetricName": "tma_l3_hit_latency", - "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", + "MetricExpr": "tma_retiring - tma_heavy_operations", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_light_operations", + "MetricThreshold": "tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", - "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group", - "MetricName": "tma_sq_full", - "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_load_op_utilization", + "MetricThreshold": "tma_load_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", - "MetricExpr": "min((1 - MEM_LOAD_UOPS_RETIRED.L3_HIT / (MEM_LOAD_UOPS_RETIRED.L3_HIT + 7 * MEM_LOAD_UOPS_RETIRED.L3_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_dram_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / tma_info_clks", + "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group", + "MetricName": "tma_local_dram", + "MetricThreshold": "tma_local_dram > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / tma_info_clks", + "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group", + "MetricName": "tma_lock_latency", + "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", + "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x6@) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=6@) / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW", "MetricName": "tma_mem_bandwidth", - "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_sq_full", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CPU_CLK_UNHALTED.THREAD - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_clks - tma_mem_bandwidth", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat", "MetricName": "tma_mem_latency", - "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_l3_hit_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory", - "MetricExpr": "min(200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_local_dram", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - (cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if tma_info_ipc > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@)) / 2 - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) if #SMT_on else min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - (cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if tma_info_ipc > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound", + "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_memory_bound", + "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory", - "MetricExpr": "min(310 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_remote_dram", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_slots", + "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS", + "MetricName": "tma_microcode_sequencer", + "MetricThreshold": "tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues", - "MetricExpr": "min((200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_remote_cache", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", + "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / tma_info_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_mite", + "MetricThreshold": "tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", - "MetricExpr": "RESOURCE_STALLS.SB / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_store_bound", - "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.", + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", + "MetricExpr": "2 * IDQ.MS_SWITCHES / tma_info_clks", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", + "MetricName": "tma_ms_switches", + "MetricThreshold": "tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", - "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_store_latency", - "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / tma_info_core_clks", + "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_0", + "MetricThreshold": "tma_port_0 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED_PORT.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_512b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", - "MetricExpr": "min((200 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_false_sharing", - "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_1", + "MetricThreshold": "tma_port_1 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_512b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents rate of split store accesses", - "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / CORE_CLKS", - "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_split_stores", - "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", + "MetricName": "tma_port_2", + "MetricThreshold": "tma_port_2 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", - "MetricExpr": "min((8 * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_dtlb_store", - "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", + "MetricName": "tma_port_3", + "MetricThreshold": "tma_port_3 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_3", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", - "MetricExpr": "tma_backend_bound - tma_memory_bound", - "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_core_bound", - "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)", + "MetricExpr": "tma_store_op_utilization", + "MetricGroup": "TopdownL6;tma_L6_group;tma_issueSpSt;tma_store_op_utilization_group", + "MetricName": "tma_port_4", + "MetricThreshold": "tma_port_4 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Sample with: UOPS_DISPATCHED_PORT.PORT_4. Related metrics: tma_split_stores", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", - "MetricExpr": "10 * ARITH.DIVIDER_UOPS / CORE_CLKS", - "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", - "MetricName": "tma_divider", - "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_5", + "MetricThreshold": "tma_port_5 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Sample with: UOPS_DISPATCHED.PORT_5. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_6", + "MetricThreshold": "tma_port_6 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group", + "MetricName": "tma_port_7", + "MetricThreshold": "tma_port_7 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address). Sample with: UOPS_DISPATCHED_PORT.PORT_7", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", - "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - (cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@)) / 2 - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB if #SMT_on else min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - (cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ if INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / CPU_CLK_UNHALTED.THREAD", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - (cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if tma_info_ipc > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@)) / 2 - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB if #SMT_on else min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - (cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ if tma_info_ipc > 1.8 else cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / tma_info_clks", "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_ports_utilization", + "MetricThreshold": "tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\=0x1\\,cmask\\=0x1@ / 2 if #SMT_on else min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0)) / CORE_CLKS", + "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0)) / tma_info_core_clks)", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", "MetricName": "tma_ports_utilized_0", + "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@) / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / tma_info_core_clks)", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group", "MetricName": "tma_ports_utilized_1", - "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", + "MetricThreshold": "tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Related metrics: tma_l1_bound", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@) / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / tma_info_core_clks)", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group", "MetricName": "tma_ports_utilized_2", - "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", + "MetricThreshold": "tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", - "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=0x3@) / CORE_CLKS", + "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / tma_info_core_clks", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", "MetricName": "tma_ports_utilized_3m", + "MetricThreshold": "tma_ports_utilized_3m > 0.7 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", - "MetricName": "tma_alu_op_utilization", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS", - "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group", - "MetricName": "tma_port_0", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", - "MetricName": "tma_port_1", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", - "MetricName": "tma_port_5", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(200 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD)))) / tma_info_clks", + "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_issueSyncxn;tma_mem_latency_group", + "MetricName": "tma_remote_cache", + "MetricThreshold": "tma_remote_cache > 0.05 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", - "MetricName": "tma_port_6", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "310 * (MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD))) / tma_info_clks", + "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", + "MetricName": "tma_remote_dram", + "MetricThreshold": "tma_remote_dram > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", - "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", - "MetricName": "tma_load_op_utilization", + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", - "MetricName": "tma_port_2", + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_info_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_split_loads", + "MetricThreshold": "tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_UOPS_RETIRED.SPLIT_LOADS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", - "MetricName": "tma_port_3", + "BriefDescription": "This metric represents rate of split store accesses", + "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / tma_info_core_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group", + "MetricName": "tma_split_stores", + "MetricThreshold": "tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_UOPS_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", - "MetricName": "tma_store_op_utilization", + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", + "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group", + "MetricName": "tma_sq_full", + "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_mem_bandwidth", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)", - "MetricExpr": "tma_store_op_utilization", - "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group", - "MetricName": "tma_port_4", + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", + "MetricExpr": "RESOURCE_STALLS.SB / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_store_bound", + "MetricThreshold": "tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group", - "MetricName": "tma_port_7", + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", + "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_store_fwd_blk", + "MetricThreshold": "tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", "ScaleUnit": "100%" }, { - "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group", - "MetricName": "tma_retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ", + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_clks", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group", + "MetricName": "tma_store_latency", + "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", - "MetricExpr": "tma_retiring - UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group", - "MetricName": "tma_light_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / tma_info_core_clks", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_store_op_utilization", + "MetricThreshold": "tma_store_op_utilization > 0.6", "ScaleUnit": "100%" }, { "BriefDescription": "This metric serves as an approximation of legacy x87 usage", - "MetricExpr": "INST_RETIRED.X87 * UPI / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricExpr": "INST_RETIRED.X87 * tma_info_uoppi / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", "MetricName": "tma_x87_use", + "MetricThreshold": "tma_x87_use > 0.1", "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group", - "MetricName": "tma_heavy_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", - "MetricExpr": "tma_heavy_operations", - "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group", - "MetricName": "tma_microcode_sequencer", - "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", - "MetricExpr": "min(100 * OTHER_ASSISTS.ANY_WB_ASSIST / SLOTS, 1)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", - "MetricName": "tma_assists", - "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", - "MetricExpr": "max(0, tma_heavy_operations - tma_assists)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", - "MetricName": "tma_cisc", - "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "C3 residency percent per core", - "MetricExpr": "cstate_core@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Core_Residency", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "C6 residency percent per core", - "MetricExpr": "cstate_core@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Core_Residency", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "C7 residency percent per core", - "MetricExpr": "cstate_core@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Core_Residency", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "C2 residency percent per package", - "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C2_Pkg_Residency", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "C3 residency percent per package", - "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Pkg_Residency", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "C6 residency percent per package", - "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Pkg_Residency", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "C7 residency percent per package", - "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Pkg_Residency", - "ScaleUnit": "100%" } ] -- cgit v1.2.3-58-ga151 From 5d48694714b9d887b99e3175ccb9a065e52976e5 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:16 -0800 Subject: perf vendor events intel: Refresh icelake events Update the icelake events from 1.15 to 1.17. Generation was done using https://github.com/intel/perfmon. Notable changes are new events and event descriptions, TMA metrics are updated to version 4.5, TMA info metrics are renamed from their node name to be lower case and prefixed by tma_info_, MetricThreshold expressions are added, smi_cost and transaction metric groups are added replicating existing hard coded metrics in stat-shadow. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-20-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/icelake/cache.json | 16 + .../arch/x86/icelake/floating-point.json | 31 + .../pmu-events/arch/x86/icelake/icl-metrics.json | 1932 +++++++++++--------- .../perf/pmu-events/arch/x86/icelake/pipeline.json | 23 +- .../pmu-events/arch/x86/icelake/uncore-other.json | 56 + tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 6 files changed, 1235 insertions(+), 825 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/icelake/cache.json b/tools/perf/pmu-events/arch/x86/icelake/cache.json index bc6587391760..a9174a0837f0 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/cache.json +++ b/tools/perf/pmu-events/arch/x86/icelake/cache.json @@ -154,6 +154,22 @@ "SampleAfterValue": "200003", "UMask": "0x21" }, + { + "BriefDescription": "All requests that miss L2 cache. This event is not supported on ICL and ICX products, only supported on RKL products.", + "EventCode": "0x24", + "EventName": "L2_RQSTS.MISS", + "PublicDescription": "Counts all requests that miss L2 cache. This event is not supported on ICL and ICX products, only supported on RKL products.", + "SampleAfterValue": "200003", + "UMask": "0x3f" + }, + { + "BriefDescription": "All L2 requests. This event is not supported on ICL and ICX products, only supported on RKL products.", + "EventCode": "0x24", + "EventName": "L2_RQSTS.REFERENCES", + "PublicDescription": "Counts all L2 requests. This event is not supported on ICL and ICX products, only supported on RKL products.", + "SampleAfterValue": "200003", + "UMask": "0xff" + }, { "BriefDescription": "RFO requests that hit L2 cache", "EventCode": "0x24", diff --git a/tools/perf/pmu-events/arch/x86/icelake/floating-point.json b/tools/perf/pmu-events/arch/x86/icelake/floating-point.json index 655342dadac6..85c26c889088 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/icelake/floating-point.json @@ -39,6 +39,14 @@ "SampleAfterValue": "100003", "UMask": "0x20" }, + { + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x18" + }, { "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "EventCode": "0xc7", @@ -55,6 +63,22 @@ "SampleAfterValue": "100003", "UMask": "0x80" }, + { + "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x60" + }, + { + "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "1000003", + "UMask": "0x3" + }, { "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "EventCode": "0xc7", @@ -70,5 +94,12 @@ "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x2" + }, + { + "BriefDescription": "Number of any Vector retired FP arithmetic instructions", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.VECTOR", + "SampleAfterValue": "1000003", + "UMask": "0xfc" } ] diff --git a/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json b/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json index 2ad36e00d289..f45ae3483df4 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json @@ -1,1230 +1,1518 @@ [ { - "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / SLOTS", - "MetricGroup": "PGO;TopdownL1;tma_L1_group", - "MetricName": "tma_frontend_bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", - "MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / SLOTS", - "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_latency", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", + "BriefDescription": "C10 residency percent per package", + "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C10_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses", - "MetricExpr": "ICACHE_16B.IFDATA_STALL / CLKS", - "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_icache_misses", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", + "BriefDescription": "C2 residency percent per package", + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C2_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", - "MetricExpr": "ICACHE_64B.IFTAG_STALL / CLKS", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_itlb_misses", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", + "BriefDescription": "C3 residency percent per package", + "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", - "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CLKS + tma_unknown_branches", - "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_branch_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group", - "MetricName": "tma_mispredicts_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES", + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears", - "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS", - "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group", - "MetricName": "tma_clears_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES", + "BriefDescription": "C7 residency percent per core", + "MetricExpr": "cstate_core@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", - "MetricExpr": "10 * BACLEARS.ANY / CLKS", - "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_branch_resteers_group", - "MetricName": "tma_unknown_branches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit). Sample with: BACLEARS.ANY", + "BriefDescription": "C7 residency percent per package", + "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_dsb_switches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS", + "BriefDescription": "C8 residency percent per package", + "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C8_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", - "MetricExpr": "ILD_STALL.LCP / CLKS", - "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_lcp", - "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", + "BriefDescription": "C9 residency percent per package", + "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C9_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", - "MetricExpr": "3 * IDQ.MS_SWITCHES / CLKS", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_ms_switches", - "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES", - "ScaleUnit": "100%" + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "tma_info_socket_clks / #num_dies / duration_time / 1e9", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", - "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)", - "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_bandwidth", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS", + "BriefDescription": "Percentage of cycles spent in System Management Interrupts.", + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", + "MetricGroup": "smi", + "MetricName": "smi_cycles", + "MetricThreshold": "smi_cycles > 0.1", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", - "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / CORE_CLKS / 2", - "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_group", - "MetricName": "tma_mite", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS", - "ScaleUnit": "100%" + "BriefDescription": "Number of SMI interrupts.", + "MetricExpr": "msr@smi@", + "MetricGroup": "smi", + "MetricName": "smi_num", + "ScaleUnit": "1SMI#" }, { - "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", - "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) / CORE_CLKS", - "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_mite_group", - "MetricName": "tma_decoder0_alone", + "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", + "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_4k_aliasing", + "MetricThreshold": "tma_4k_aliasing > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles where (only) 4 uops were delivered by the MITE pipeline", - "MetricExpr": "(cpu@IDQ.MITE_UOPS\\,cmask\\=4@ - cpu@IDQ.MITE_UOPS\\,cmask\\=5@) / CLKS", - "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_mite_group", - "MetricName": "tma_mite_4wide", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5 + UOPS_DISPATCHED.PORT_6) / (4 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_alu_op_utilization", + "MetricThreshold": "tma_alu_op_utilization > 0.6", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", - "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / CORE_CLKS / 2", - "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group", - "MetricName": "tma_dsb", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", + "MetricExpr": "100 * ASSISTS.ANY / tma_info_slots", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_assists", + "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit", - "MetricExpr": "(LSD.CYCLES_ACTIVE - LSD.CYCLES_OK) / CORE_CLKS / 2", - "MetricGroup": "FetchBW;LSD;TopdownL3;tma_fetch_bandwidth_group", - "MetricName": "tma_lsd", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit. LSD typically does well sustaining Uop supply. However; in some rare cases; optimal uop-delivery could not be reached for small loops whose size (in terms of number of uops) does not suit well the LSD structure.", + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", + "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=1\\,edge@ / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_backend_bound", + "MetricThreshold": "tma_backend_bound > 0.2", + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", "ScaleUnit": "100%" }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)", - "MetricGroup": "TopdownL1;tma_L1_group", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", + "MetricThreshold": "tma_bad_speculation > 0.15", "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", "ScaleUnit": "100%" }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions.", + "MetricExpr": "tma_light_operations * BR_INST_RETIRED.ALL_BRANCHES / (tma_retiring * tma_info_slots)", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_branch_instructions", + "MetricThreshold": "tma_branch_instructions > 0.1 & tma_light_operations > 0.6", + "ScaleUnit": "100%" + }, { "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredicts_resteers", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", - "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)", - "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_machine_clears", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", + "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks + tma_unknown_branches", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_branch_resteers", + "MetricThreshold": "tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", "ScaleUnit": "100%" }, { - "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", - "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=1\\,edge@ / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_backend_bound", - "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", + "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_cisc", + "MetricThreshold": "tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound", - "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_memory_bound", - "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears", + "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks", + "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC", + "MetricName": "tma_clears_resteers", + "MetricThreshold": "tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", - "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CLKS, 0)", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l1_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(29 * tma_info_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM + 23.5 * tma_info_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_contested_accesses", + "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", - "MetricExpr": "min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / CLKS", - "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_dtlb_load", - "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS", + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", + "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)", + "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", - "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss", - "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group", - "MetricName": "tma_load_stlb_hit", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "23.5 * tma_info_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_data_sharing", + "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", - "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CLKS", - "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group", - "MetricName": "tma_load_stlb_miss", + "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", + "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) / tma_info_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_issueD0;tma_mite_group", + "MetricName": "tma_decoder0_alone", + "MetricThreshold": "tma_decoder0_alone > 0.1 & (tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 5 > 0.35))", + "PublicDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder. Related metrics: tma_few_uops_instructions", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", - "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_store_fwd_blk", - "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", + "MetricExpr": "ARITH.DIVIDER_ACTIVE / tma_info_clks", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_divider", + "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", - "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS", - "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_lock_latency", - "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS", + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks - tma_l2_bound", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_dram_bound", + "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", - "MetricExpr": "Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_split_loads", - "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS", + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", + "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / tma_info_core_clks / 2", + "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_dsb", + "MetricThreshold": "tma_dsb > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 5 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", - "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_4k_aliasing", - "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_clks", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_dsb_switches", + "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", - "MetricExpr": "L1D_PEND_MISS.FB_FULL / CLKS", - "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_fb_full", - "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).", + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", + "MetricExpr": "min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group", + "MetricName": "tma_dtlb_load", + "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store, tma_info_memory_data_tlbs", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", - "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS)", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l2_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS", + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", + "MetricExpr": "(7 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group", + "MetricName": "tma_dtlb_store", + "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, tma_info_memory_data_tlbs", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / CLKS", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l3_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", + "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", + "MetricExpr": "32.5 * tma_info_average_frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group", + "MetricName": "tma_false_sharing", + "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", - "MetricExpr": "(29 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM + 23.5 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_contested_accesses", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS", + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", + "MetricExpr": "L1D_PEND_MISS.FB_FULL / tma_info_clks", + "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricName": "tma_fb_full", + "MetricThreshold": "tma_fb_full > 0.3", + "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_dram_bw_use, tma_info_memory_bandwidth, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", - "MetricExpr": "23.5 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_data_sharing", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS", + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", + "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)", + "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", + "MetricName": "tma_fetch_bandwidth", + "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 5 > 0.35", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", - "MetricExpr": "9 * Average_Frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS", - "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_l3_hit_latency", - "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", + "MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / tma_info_slots", + "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_latency", + "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", - "MetricExpr": "L1D_PEND_MISS.L2_STALL / CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_sq_full", - "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops", + "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer", + "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueD0", + "MetricName": "tma_few_uops_instructions", + "MetricThreshold": "tma_few_uops_instructions > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions. Related metrics: tma_decoder0_alone", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", - "MetricExpr": "CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS - tma_l2_bound", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_dram_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS", + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", + "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", + "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_fp_arith", + "MetricThreshold": "tma_fp_arith > 0.2 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group", - "MetricName": "tma_mem_bandwidth", - "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", + "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_scalar", + "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group", - "MetricName": "tma_mem_latency", - "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", + "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_vector", + "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", - "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CLKS", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_store_bound", - "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS", + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_128b", + "MetricThreshold": "tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", - "MetricExpr": "(L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group", - "MetricName": "tma_store_latency", - "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_256b", + "MetricThreshold": "tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", - "MetricExpr": "32.5 * Average_Frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group", - "MetricName": "tma_false_sharing", - "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_512b", + "MetricThreshold": "tma_fp_vector_512b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents rate of split store accesses", - "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CORE_CLKS", - "MetricGroup": "TopdownL4;tma_store_bound_group", - "MetricName": "tma_split_stores", - "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS", + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", + "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / tma_info_slots", + "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.15", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores", - "MetricExpr": "9 * OCR.STREAMING_WR.ANY_RESPONSE / CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_store_bound_group", - "MetricName": "tma_streaming_stores", - "PublicDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck. Sample with: OCR.STREAMING_WR.ANY_RESPONSE", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences", + "MetricExpr": "tma_microcode_sequencer + tma_retiring * (UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=1@) / IDQ.MITE_UOPS", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_heavy_operations", + "MetricThreshold": "tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", - "MetricExpr": "(7 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CORE_CLKS", - "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group", - "MetricName": "tma_dtlb_store", - "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses", + "MetricExpr": "ICACHE_16B.IFDATA_STALL / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_icache_misses", + "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", - "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss", - "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group", - "MetricName": "tma_store_stlb_hit", - "ScaleUnit": "100%" + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "tma_info_turbo_utilization * TSC / 1e9 / duration_time", + "MetricGroup": "Power;Summary", + "MetricName": "tma_info_average_frequency" }, { - "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", - "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS", - "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group", - "MetricName": "tma_store_stlb_miss", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB;tma_issueBC", + "MetricName": "tma_info_big_code", + "MetricThreshold": "tma_info_big_code > 20", + "PublicDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses). Related metrics: tma_info_branching_overhead" }, { - "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", - "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)", - "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_core_bound", - "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", - "ScaleUnit": "100%" + "BriefDescription": "Branch instructions per taken branch.", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_bptkbranch" }, { - "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", - "MetricExpr": "ARITH.DIVIDER_ACTIVE / CLKS", - "MetricGroup": "TopdownL3;tma_core_bound_group", - "MetricName": "tma_divider", - "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE", - "ScaleUnit": "100%" + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_slots / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts;tma_issueBM", + "MetricName": "tma_info_branch_misprediction_cost", + "PublicDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_branch_mispredicts, tma_info_mispredictions, tma_mispredicts_resteers" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", - "MetricExpr": "((cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CLKS)", - "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group", - "MetricName": "tma_ports_utilization", - "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "MetricExpr": "100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL)) / tma_info_slots)", + "MetricGroup": "Ret;tma_issueBC", + "MetricName": "tma_info_branching_overhead", + "MetricThreshold": "tma_info_branching_overhead > 10", + "PublicDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls). Related metrics: tma_info_big_code" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ / CLKS + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_0", - "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_callret" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations", - "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / CLKS", - "MetricGroup": "TopdownL5;tma_ports_utilized_0_group", - "MetricName": "tma_serializing_operation", - "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD", - "ScaleUnit": "100%" + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline", + "MetricName": "tma_info_clks" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions", - "MetricExpr": "140 * MISC_RETIRED.PAUSE_INST / CLKS", - "MetricGroup": "TopdownL6;tma_serializing_operation_group", - "MetricName": "tma_slow_pause", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: MISC_RETIRED.PAUSE_INST", - "ScaleUnit": "100%" + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Fed;MemoryTLB", + "MetricName": "tma_info_code_stlb_mpki" }, { - "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued", - "MetricExpr": "CLKS * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY", - "MetricGroup": "TopdownL5;tma_ports_utilized_0_group", - "MetricName": "tma_mixing_vectors", - "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "tma_info_cond_nt" }, { - "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "EXE_ACTIVITY.1_PORTS_UTIL / CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_1", - "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of branches that are taken conditionals", + "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "tma_info_cond_tk" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "EXE_ACTIVITY.2_PORTS_UTIL / CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_2", - "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL", - "ScaleUnit": "100%" + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if tma_info_smt_2t_utilization > 0.5 else 0)", + "MetricGroup": "Cor;SMT", + "MetricName": "tma_info_core_bound_likely", + "MetricThreshold": "tma_info_core_bound_likely > 0.5" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_3m", - "PublicDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3", - "ScaleUnit": "100%" + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED", + "MetricGroup": "SMT", + "MetricName": "tma_info_core_clks" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5 + UOPS_DISPATCHED.PORT_6) / (4 * CORE_CLKS)", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_alu_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_core_clks", + "MetricGroup": "Ret;SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_coreipc" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) Sample with: UOPS_DISPATCHED.PORT_0", - "MetricExpr": "UOPS_DISPATCHED.PORT_0 / CORE_CLKS", - "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_0", - "ScaleUnit": "100%" + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / tma_info_ipc", + "MetricGroup": "Mem;Pipeline", + "MetricName": "tma_info_cpi" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHED.PORT_1", - "MetricExpr": "UOPS_DISPATCHED.PORT_1 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_1", - "ScaleUnit": "100%" + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "HPC;Summary", + "MetricName": "tma_info_cpu_utilization" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) Sample with: UOPS_DISPATCHED.PORT_5", - "MetricExpr": "UOPS_DISPATCHED.PORT_5 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_5", - "ScaleUnit": "100%" + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_data_l2_mlp" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) Sample with: UOPS_DISPATCHED.PORT_6", - "MetricExpr": "UOPS_DISPATCHED.PORT_6 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_6", - "ScaleUnit": "100%" + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;tma_issueBW", + "MetricName": "tma_info_dram_bw_use", + "PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_info_memory_bandwidth, tma_mem_bandwidth, tma_sq_full" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations Sample with: UOPS_DISPATCHED.PORT_2_3", - "MetricExpr": "UOPS_DISPATCHED.PORT_2_3 / (2 * CORE_CLKS)", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_load_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / UOPS_ISSUED.ANY", + "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", + "MetricName": "tma_info_dsb_coverage", + "MetricThreshold": "tma_info_dsb_coverage < 0.7 & tma_info_ipc / 5 > 0.35", + "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_misses, tma_info_iptb, tma_lcp" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations Sample with: UOPS_DISPATCHED.PORT_7_8", - "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * CORE_CLKS)", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_store_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck", + "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_lsd + tma_mite))", + "MetricGroup": "DSBmiss;Fed;tma_issueFB", + "MetricName": "tma_info_dsb_misses", + "MetricThreshold": "tma_info_dsb_misses > 10", + "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_iptb, tma_lcp" }, { - "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS", - "ScaleUnit": "100%" + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@", + "MetricGroup": "DSBmiss", + "MetricName": "tma_info_dsb_switch_cost" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", - "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_light_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", - "ScaleUnit": "100%" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-thread", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "tma_info_execute" }, { - "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", - "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", - "MetricGroup": "HPC;TopdownL3;tma_light_operations_group", - "MetricName": "tma_fp_arith", - "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", - "ScaleUnit": "100%" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "tma_info_execute_per_issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." }, { - "BriefDescription": "This metric serves as an approximation of legacy x87 usage", - "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD", - "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_x87_use", - "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", - "ScaleUnit": "100%" + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_fb_hpki" }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / (tma_retiring * SLOTS)", - "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_fp_scalar", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_fetch_upc" }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", - "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (tma_retiring * SLOTS)", - "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_fp_vector", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * cpu@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE\\,umask\\=0x18@ + 8 * cpu@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE\\,umask\\=0x60@ + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / tma_info_core_clks", + "MetricGroup": "Flops;Ret", + "MetricName": "tma_info_flopc" }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", - "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / (tma_retiring * SLOTS)", - "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group", - "MetricName": "tma_fp_vector_128b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@) / (2 * tma_info_core_clks)", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_fp_arith_utilization", + "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", - "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / (tma_retiring * SLOTS)", - "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group", - "MetricName": "tma_fp_vector_256b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Giga Floating Point Operations Per Second", + "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * cpu@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE\\,umask\\=0x18@ + 8 * cpu@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE\\,umask\\=0x60@ + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_gflops", + "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors", - "MetricExpr": "(FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (tma_retiring * SLOTS)", - "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group", - "MetricName": "tma_fp_vector_512b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck", + "MetricExpr": "100 * (tma_fetch_latency * tma_icache_misses / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", + "MetricGroup": "Fed;FetchLat;IcMiss;tma_issueFL", + "MetricName": "tma_info_ic_misses", + "MetricThreshold": "tma_info_ic_misses > 5", + "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck. Related metrics: " }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", - "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group", - "MetricName": "tma_memory_operations", - "ScaleUnit": "100%" + "BriefDescription": "Average Latency for L1 instruction cache misses", + "MetricExpr": "ICACHE_16B.IFDATA_STALL / cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@", + "MetricGroup": "Fed;FetchLat;IcMiss", + "MetricName": "tma_info_icache_miss_latency" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions.", - "MetricExpr": "tma_light_operations * BR_INST_RETIRED.ALL_BRANCHES / (tma_retiring * SLOTS)", - "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group", - "MetricName": "tma_branch_instructions", - "ScaleUnit": "100%" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", + "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", + "MetricName": "tma_info_ilp" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions", - "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (tma_retiring * SLOTS)", - "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group", - "MetricName": "tma_nop_instructions", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_big_code", + "MetricGroup": "Fed;FetchBW;Frontend", + "MetricName": "tma_info_instruction_fetch_bw", + "MetricThreshold": "tma_info_instruction_fetch_bw > 20" }, { - "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", - "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_branch_instructions + tma_nop_instructions))", - "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group", - "MetricName": "tma_other_light_ops", - "ScaleUnit": "100%" + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;tma_L1_group", + "MetricName": "tma_info_instructions", + "PublicDescription": "Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences", - "MetricExpr": "tma_microcode_sequencer + tma_retiring * (UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=1@) / IDQ.MITE_UOPS", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_heavy_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_iparith", + "MetricThreshold": "tma_info_iparith < 10", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops", - "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer", - "MetricGroup": "TopdownL3;tma_heavy_operations_group", - "MetricName": "tma_few_uops_instructions", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx128", + "MetricThreshold": "tma_info_iparith_avx128 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", - "MetricExpr": "tma_retiring * SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS", - "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group", - "MetricName": "tma_microcode_sequencer", - "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx256", + "MetricThreshold": "tma_info_iparith_avx256 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", - "MetricExpr": "100 * ASSISTS.ANY / SLOTS", - "MetricGroup": "TopdownL4;tma_microcode_sequencer_group", - "MetricName": "tma_assists", - "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx512", + "MetricThreshold": "tma_info_iparith_avx512 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", - "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", - "MetricGroup": "TopdownL4;tma_microcode_sequencer_group", - "MetricName": "tma_cisc", - "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_iparith_scalar_dp", + "MetricThreshold": "tma_info_iparith_scalar_dp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", - "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "Mispredictions" + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_iparith_scalar_sp", + "MetricThreshold": "tma_info_iparith_scalar_sp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks", - "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "Memory_Bandwidth" + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "tma_info_ipbranch", + "MetricThreshold": "tma_info_ipbranch < 8" }, { - "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)", - "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound))", - "MetricGroup": "Mem;MemoryLat;Offcore", - "MetricName": "Memory_Latency" + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_clks", + "MetricGroup": "Ret;Summary", + "MetricName": "tma_info_ipc" }, { - "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", - "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))", - "MetricGroup": "Mem;MemoryTLB;Offcore", - "MetricName": "Memory_Data_TLBs" + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_ipcall", + "MetricThreshold": "tma_info_ipcall < 200" }, { - "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", - "MetricExpr": "100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)", - "MetricGroup": "Ret", - "MetricName": "Branching_Overhead" + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "tma_info_ipdsb_miss_ret", + "MetricThreshold": "tma_info_ipdsb_miss_ret < 50" }, { - "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", - "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", - "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB", - "MetricName": "Big_Code" + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "tma_info_ipfarbranch", + "MetricThreshold": "tma_info_ipfarbranch < 1e6" }, { - "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", - "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code", - "MetricGroup": "Fed;FetchBW;Frontend", - "MetricName": "Instruction_Fetch_BW" + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * cpu@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE\\,umask\\=0x18@ + 8 * cpu@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE\\,umask\\=0x60@ + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_ipflop", + "MetricThreshold": "tma_info_ipflop < 10" }, { - "BriefDescription": "Instructions Per Cycle (per Logical Processor)", - "MetricExpr": "INST_RETIRED.ANY / CLKS", - "MetricGroup": "Ret;Summary", - "MetricName": "IPC" + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipload", + "MetricThreshold": "tma_info_ipload < 3" }, { - "BriefDescription": "Uops Per Instruction", - "MetricExpr": "tma_retiring * SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Ret;Retire", - "MetricName": "UPI" + "BriefDescription": "Instructions per retired mispredicts for conditional non-taken branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_NTAKEN", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_cond_ntaken", + "MetricThreshold": "tma_info_ipmisp_cond_ntaken < 200" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "tma_retiring * SLOTS / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW", - "MetricName": "UpTB" + "BriefDescription": "Instructions per retired mispredicts for conditional taken branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_cond_taken", + "MetricThreshold": "tma_info_ipmisp_cond_taken < 200" }, { - "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / IPC", - "MetricGroup": "Mem;Pipeline", - "MetricName": "CPI" + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_indirect", + "MetricThreshold": "tma_info_ipmisp_indirect < 1e3" }, { - "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Pipeline", - "MetricName": "CLKS" + "BriefDescription": "Instructions per retired mispredicts for return branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RET", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_ret", + "MetricThreshold": "tma_info_ipmisp_ret < 500" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", - "MetricExpr": "TOPDOWN.SLOTS", - "MetricGroup": "tma_L1_group", - "MetricName": "SLOTS" + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "tma_info_ipmispredict", + "MetricThreshold": "tma_info_ipmispredict < 200" }, { - "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", - "MetricExpr": "(SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)", - "MetricGroup": "SMT;tma_L1_group", - "MetricName": "Slots_Utilization" + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipstore", + "MetricThreshold": "tma_info_ipstore < 8" }, { - "BriefDescription": "The ratio of Executed- by Issued-Uops", - "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", - "MetricGroup": "Cor;Pipeline", - "MetricName": "Execute_per_Issue", - "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", + "MetricGroup": "Prefetches", + "MetricName": "tma_info_ipswpf", + "MetricThreshold": "tma_info_ipswpf < 100" }, { - "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS", - "MetricGroup": "Ret;SMT;tma_L1_group", - "MetricName": "CoreIPC" - }, - { - "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS", - "MetricGroup": "Flops;Ret", - "MetricName": "FLOPc" - }, - { - "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "FP_Arith_Utilization", - "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", + "MetricName": "tma_info_iptb", + "MetricThreshold": "tma_info_iptb < 11", + "PublicDescription": "Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_dsb_misses, tma_lcp" }, { - "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", - "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", - "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", - "MetricName": "ILP" + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "tma_info_instructions / BACLEARS.ANY", + "MetricGroup": "Fed", + "MetricName": "tma_info_ipunknown_branch" }, { - "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", - "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)", - "MetricGroup": "Cor;SMT", - "MetricName": "Core_Bound_Likely" + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_jump" }, { - "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", - "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED", - "MetricGroup": "SMT", - "MetricName": "CORE_CLKS" + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_cpi" }, { - "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", - "MetricGroup": "InsType", - "MetricName": "IpLoad" + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_utilization", + "MetricThreshold": "tma_info_kernel_utilization > 0.05" }, { - "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", - "MetricGroup": "InsType", - "MetricName": "IpStore" + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw" }, { - "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Fed;InsType", - "MetricName": "IpBranch" + "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "tma_info_l1d_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw_1t" }, { - "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "IpCall" + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l1mpki" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", - "MetricName": "IpTB" + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l1mpki_load" }, { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "BpTkBranch" + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw" }, { - "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)", - "MetricGroup": "Flops;InsType", - "MetricName": "IpFLOP" + "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "tma_info_l2_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw_1t" }, { - "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))", - "MetricGroup": "Flops;InsType", - "MetricName": "IpArith", - "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2hpki_load" }, { - "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", - "MetricGroup": "Flops;FpScalar;InsType", - "MetricName": "IpArith_Scalar_SP", - "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Backend;CacheMisses;Mem", + "MetricName": "tma_info_l2mpki" }, { - "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", - "MetricGroup": "Flops;FpScalar;InsType", - "MetricName": "IpArith_Scalar_DP", - "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "MetricExpr": "1e3 * (OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS) / tma_info_instructions", + "MetricGroup": "CacheMisses;Mem;Offcore", + "MetricName": "tma_info_l2mpki_all" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX128", - "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction", + "MetricExpr": "1e3 * FRONTEND_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss", + "MetricName": "tma_info_l2mpki_code" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX256", - "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction", + "MetricExpr": "1e3 * L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss", + "MetricName": "tma_info_l2mpki_code_all" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX512", - "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2mpki_load" }, { - "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", - "MetricGroup": "Prefetches", - "MetricName": "IpSWPF" + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_l3_cache_access_bw" }, { - "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary;tma_L1_group", - "MetricName": "Instructions" + "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_l3_cache_access_bw", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_l3_cache_access_bw_1t" }, { - "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", - "MetricExpr": "tma_retiring * SLOTS / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@", - "MetricGroup": "Pipeline;Ret", - "MetricName": "Retire" + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw" }, { - "BriefDescription": "", - "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", - "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", - "MetricName": "Execute" + "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_l3_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw_1t" }, { - "BriefDescription": "Average number of Uops issued by front-end when it issued something", - "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@", - "MetricGroup": "Fed;FetchBW", - "MetricName": "Fetch_UpC" + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l3mpki" }, { - "BriefDescription": "Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache)", - "MetricExpr": "LSD.UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "Fed;LSD", - "MetricName": "LSD_Coverage" + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore", + "MetricName": "tma_info_load_l2_miss_latency" }, { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "DSB;Fed;FetchBW", - "MetricName": "DSB_Coverage" + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,cmask\\=1@", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_load_l2_mlp" }, { - "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@", - "MetricGroup": "DSBmiss", - "MetricName": "DSB_Switch_Cost" + "BriefDescription": "Average Latency for L3 cache miss demand Loads", + "MetricExpr": "cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,umask\\=0x10@ / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore", + "MetricName": "tma_info_load_l3_miss_latency" }, { - "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.", - "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_lsd + tma_mite))", - "MetricGroup": "DSBmiss;Fed", - "MetricName": "DSB_Misses" + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "tma_info_load_miss_real_latency" }, { - "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", - "MetricGroup": "DSBmiss;Fed", - "MetricName": "IpDSB_Miss_Ret" + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_load_stlb_mpki" }, { - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" + "BriefDescription": "Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache)", + "MetricExpr": "LSD.UOPS / UOPS_ISSUED.ANY", + "MetricGroup": "Fed;LSD", + "MetricName": "tma_info_lsd_coverage" }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BrMispredicts", - "MetricName": "Branch_Misprediction_Cost" + "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks", + "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))", + "MetricGroup": "Mem;MemoryBW;Offcore;tma_issueBW", + "MetricName": "tma_info_memory_bandwidth", + "MetricThreshold": "tma_info_memory_bandwidth > 20", + "PublicDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_mem_bandwidth, tma_sq_full" }, { - "BriefDescription": "Fraction of branches that are non-taken conditionals", - "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches;CodeGen;PGO", - "MetricName": "Cond_NT" + "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", + "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))", + "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", + "MetricName": "tma_info_memory_data_tlbs", + "MetricThreshold": "tma_info_memory_data_tlbs > 20", + "PublicDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store" }, { - "BriefDescription": "Fraction of branches that are taken conditionals", - "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches;CodeGen;PGO", - "MetricName": "Cond_TK" + "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)", + "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound))", + "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", + "MetricName": "tma_info_memory_latency", + "MetricThreshold": "tma_info_memory_latency > 20", + "PublicDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches). Related metrics: tma_l3_hit_latency, tma_mem_latency" }, { - "BriefDescription": "Fraction of branches that are CALL or RET", - "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches", - "MetricName": "CallRet" + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", + "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", + "MetricName": "tma_info_mispredictions", + "MetricThreshold": "tma_info_mispredictions > 20", + "PublicDescription": "Total pipeline cost of Branch Misprediction related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_branch_misprediction_cost, tma_mispredicts_resteers" }, { - "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", - "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches", - "MetricName": "Jump" + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBW;MemoryBound", + "MetricName": "tma_info_mlp", + "PublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)" }, { "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", - "MetricExpr": "1 - (Cond_NT + Cond_TK + CallRet + Jump)", + "MetricExpr": "1 - (tma_info_cond_nt + tma_info_cond_tk + tma_info_callret + tma_info_jump)", "MetricGroup": "Bad;Branches", - "MetricName": "Other_Branches" - }, - { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)", - "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency" + "MetricName": "tma_info_other_branches" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "Mem;MemoryBW;MemoryBound", - "MetricName": "MLP" + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (2 * tma_info_core_clks)", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_page_walks_utilization", + "MetricThreshold": "tma_info_page_walks_utilization > 0.5" }, { - "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI" + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0", + "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / tma_info_core_clks", + "MetricGroup": "Power", + "MetricName": "tma_info_power_license0_utilization", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes." }, { - "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI_Load" + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1", + "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / tma_info_core_clks", + "MetricGroup": "Power", + "MetricName": "tma_info_power_license1_utilization", + "MetricThreshold": "tma_info_power_license1_utilization > 0.5", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions." }, { - "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Backend;CacheMisses;Mem", - "MetricName": "L2MPKI" + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)", + "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / tma_info_core_clks", + "MetricGroup": "Power", + "MetricName": "tma_info_power_license2_utilization", + "MetricThreshold": "tma_info_power_license2_utilization > 0.5", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions." }, { - "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", - "MetricExpr": "1e3 * (OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS) / Instructions", - "MetricGroup": "CacheMisses;Mem;Offcore", - "MetricName": "L2MPKI_All" + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "MetricExpr": "tma_retiring * tma_info_slots / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "tma_info_retire" }, { - "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2MPKI_Load" + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "TOPDOWN.SLOTS", + "MetricGroup": "TmaL1;tma_L1_group", + "MetricName": "tma_info_slots" }, { - "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2HPKI_Load" + "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", + "MetricExpr": "(tma_info_slots / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)", + "MetricGroup": "SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_slots_utilization" }, { - "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L3MPKI" + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)", + "MetricGroup": "SMT", + "MetricName": "tma_info_smt_2t_utilization" }, { - "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "FB_HPKI" + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "UNC_CLOCK.SOCKET", + "MetricGroup": "SoC", + "MetricName": "tma_info_socket_clks" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (2 * CORE_CLKS)", + "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", "MetricGroup": "Mem;MemoryTLB", - "MetricName": "Page_Walks_Utilization" + "MetricName": "tma_info_store_stlb_mpki" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "tma_info_clks / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power", + "MetricName": "tma_info_turbo_utilization" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "tma_retiring * tma_info_slots / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire", + "MetricName": "tma_info_uoppi", + "MetricThreshold": "tma_info_uoppi > 1.05" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "tma_retiring * tma_info_slots / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "tma_info_uptb", + "MetricThreshold": "tma_info_uptb < 7.5" }, { - "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", + "MetricExpr": "ICACHE_64B.IFTAG_STALL / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "L1D_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW_1T" + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", + "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / tma_info_clks, 0)", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group", + "MetricName": "tma_l1_bound", + "MetricThreshold": "tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "L2_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW_1T" + "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks)", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l2_bound", + "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW_1T" + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / tma_info_clks", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l3_bound", + "MetricThreshold": "tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Access_BW", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW_1T" + "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", + "MetricExpr": "9 * tma_info_average_frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group", + "MetricName": "tma_l3_hit_latency", + "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_memory_latency, tma_mem_latency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average CPU Utilization", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", - "MetricGroup": "HPC;Summary", - "MetricName": "CPU_Utilization" + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", + "MetricExpr": "ILD_STALL.LCP / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_lcp", + "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb", + "ScaleUnit": "100%" }, { - "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", - "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time", - "MetricGroup": "Power;Summary", - "MetricName": "Average_Frequency" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", + "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_light_operations", + "MetricThreshold": "tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", + "ScaleUnit": "100%" }, { - "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs", - "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", + "MetricExpr": "UOPS_DISPATCHED.PORT_2_3 / (2 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_load_op_utilization", + "MetricThreshold": "tma_load_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average Frequency Utilization relative nominal frequency", - "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC", - "MetricGroup": "Power", - "MetricName": "Turbo_Utilization" + "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", + "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", + "MetricName": "tma_load_stlb_hit", + "MetricThreshold": "tma_load_stlb_hit > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0", - "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / CORE_CLKS", - "MetricGroup": "Power", - "MetricName": "Power_License0_Utilization", - "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes." + "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", + "MetricName": "tma_load_stlb_miss", + "MetricThreshold": "tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1", - "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / CORE_CLKS", - "MetricGroup": "Power", - "MetricName": "Power_License1_Utilization", - "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions." + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / tma_info_clks", + "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group", + "MetricName": "tma_lock_latency", + "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)", - "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / CORE_CLKS", - "MetricGroup": "Power", - "MetricName": "Power_License2_Utilization", - "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions." + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit", + "MetricExpr": "(LSD.CYCLES_ACTIVE - LSD.CYCLES_OK) / tma_info_core_clks / 2", + "MetricGroup": "FetchBW;LSD;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_lsd", + "MetricThreshold": "tma_lsd > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 5 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit. LSD typically does well sustaining Uop supply. However; in some rare cases; optimal uop-delivery could not be reached for small loops whose size (in terms of number of uops) does not suit well the LSD structure.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", - "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)", - "MetricGroup": "SMT", - "MetricName": "SMT_2T_Utilization" + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", + "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)", + "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "OS", - "MetricName": "Kernel_Utilization" + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW", + "MetricName": "tma_mem_bandwidth", + "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_info_memory_bandwidth, tma_sq_full", + "ScaleUnit": "100%" }, { - "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", - "MetricGroup": "OS", - "MetricName": "Kernel_CPI" + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_clks - tma_mem_bandwidth", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat", + "MetricName": "tma_mem_latency", + "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_info_memory_latency, tma_l3_hit_latency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", - "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3", - "MetricGroup": "HPC;Mem;MemoryBW;SoC", - "MetricName": "DRAM_BW_Use" + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound", + "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_memory_bound", + "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Socket actual clocks when any core is active on that socket", - "MetricExpr": "UNC_CLOCK.SOCKET", - "MetricGroup": "SoC", - "MetricName": "Socket_CLKS" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", + "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_memory_operations", + "MetricThreshold": "tma_memory_operations > 0.1 & tma_light_operations > 0.6", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", - "MetricGroup": "Branches;OS", - "MetricName": "IpFarBranch" + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", + "MetricExpr": "tma_retiring * tma_info_slots / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_slots", + "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS", + "MetricName": "tma_microcode_sequencer", + "MetricThreshold": "tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches", + "ScaleUnit": "100%" }, { - "BriefDescription": "Uncore frequency per die [GHZ]", - "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9", - "MetricGroup": "SoC", - "MetricName": "UNCORE_FREQ" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks", + "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM", + "MetricName": "tma_mispredicts_resteers", + "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_branch_misprediction_cost, tma_info_mispredictions", + "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per core", - "MetricExpr": "cstate_core@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Core_Residency", + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", + "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / tma_info_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_mite", + "MetricThreshold": "tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 5 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per core", - "MetricExpr": "cstate_core@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Core_Residency", + "BriefDescription": "This metric represents fraction of cycles where (only) 4 uops were delivered by the MITE pipeline", + "MetricExpr": "(cpu@IDQ.MITE_UOPS\\,cmask\\=4@ - cpu@IDQ.MITE_UOPS\\,cmask\\=5@) / tma_info_clks", + "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group", + "MetricName": "tma_mite_4wide", + "MetricThreshold": "tma_mite_4wide > 0.05 & (tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 5 > 0.35))", "ScaleUnit": "100%" }, { - "BriefDescription": "C2 residency percent per package", - "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C2_Pkg_Residency", + "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued", + "MetricExpr": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY", + "MetricGroup": "TopdownL5;tma_L5_group;tma_issueMV;tma_ports_utilized_0_group", + "MetricName": "tma_mixing_vectors", + "MetricThreshold": "tma_mixing_vectors > 0.05", + "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic. Related metrics: tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per package", - "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Pkg_Residency", + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", + "MetricExpr": "3 * IDQ.MS_SWITCHES / tma_info_clks", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", + "MetricName": "tma_ms_switches", + "MetricThreshold": "tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per package", - "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Pkg_Residency", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions", + "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (tma_retiring * tma_info_slots)", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_nop_instructions", + "MetricThreshold": "tma_nop_instructions > 0.1 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per package", - "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Pkg_Residency", + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes", + "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_branch_instructions + tma_nop_instructions))", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_other_light_ops", + "MetricThreshold": "tma_other_light_ops > 0.3 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", "ScaleUnit": "100%" }, { - "BriefDescription": "C8 residency percent per package", - "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C8_Pkg_Residency", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", + "MetricExpr": "UOPS_DISPATCHED.PORT_0 / tma_info_core_clks", + "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_0", + "MetricThreshold": "tma_port_0 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "C9 residency percent per package", - "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C9_Pkg_Residency", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", + "MetricExpr": "UOPS_DISPATCHED.PORT_1 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_1", + "MetricThreshold": "tma_port_1 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "C10 residency percent per package", - "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C10_Pkg_Residency", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", + "MetricExpr": "UOPS_DISPATCHED.PORT_5 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_5", + "MetricThreshold": "tma_port_5 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Sample with: UOPS_DISPATCHED.PORT_5. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", + "MetricExpr": "UOPS_DISPATCHED.PORT_6 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_6", + "MetricThreshold": "tma_port_6 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", + "MetricExpr": "((cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / tma_info_clks if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / tma_info_clks)", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_ports_utilization", + "MetricThreshold": "tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ / tma_info_clks + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_0", + "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "EXE_ACTIVITY.1_PORTS_UTIL / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_1", + "MetricThreshold": "tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL. Related metrics: tma_l1_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "EXE_ACTIVITY.2_PORTS_UTIL / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_2", + "MetricThreshold": "tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_3m", + "MetricThreshold": "tma_ports_utilized_3m > 0.7 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations", + "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL5;tma_L5_group;tma_issueSO;tma_ports_utilized_0_group", + "MetricName": "tma_serializing_operation", + "MetricThreshold": "tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD. Related metrics: tma_ms_switches", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions", + "MetricExpr": "140 * MISC_RETIRED.PAUSE_INST / tma_info_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group", + "MetricName": "tma_slow_pause", + "MetricThreshold": "tma_slow_pause > 0.05 & (tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: MISC_RETIRED.PAUSE_INST", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", + "MetricExpr": "tma_info_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_split_loads", + "MetricThreshold": "tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents rate of split store accesses", + "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / tma_info_core_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group", + "MetricName": "tma_split_stores", + "MetricThreshold": "tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", + "MetricExpr": "L1D_PEND_MISS.L2_STALL / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group", + "MetricName": "tma_sq_full", + "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_info_memory_bandwidth, tma_mem_bandwidth", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", + "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_store_bound", + "MetricThreshold": "tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", + "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_store_fwd_blk", + "MetricThreshold": "tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", + "MetricExpr": "(L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_clks", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group", + "MetricName": "tma_store_latency", + "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_store_op_utilization", + "MetricThreshold": "tma_store_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations. Sample with: UOPS_DISPATCHED.PORT_7_8", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", + "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", + "MetricName": "tma_store_stlb_hit", + "MetricThreshold": "tma_store_stlb_hit > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", + "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / tma_info_core_clks", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", + "MetricName": "tma_store_stlb_miss", + "MetricThreshold": "tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores", + "MetricExpr": "9 * OCR.STREAMING_WR.ANY_RESPONSE / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueSmSt;tma_store_bound_group", + "MetricName": "tma_streaming_stores", + "MetricThreshold": "tma_streaming_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck. Sample with: OCR.STREAMING_WR.ANY_RESPONSE. Related metrics: tma_fb_full", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", + "MetricExpr": "10 * BACLEARS.ANY / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", + "MetricName": "tma_unknown_branches", + "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit). Sample with: BACLEARS.ANY", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric serves as an approximation of legacy x87 usage", + "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD", + "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_x87_use", + "MetricThreshold": "tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of cycles in aborted transactions.", + "MetricExpr": "max(cpu@cycles\\-t@ - cpu@cycles\\-ct@, 0) / cycles", + "MetricGroup": "transaction", + "MetricName": "tsx_aborted_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Number of cycles within a transaction divided by the number of elisions.", + "MetricExpr": "cpu@cycles\\-t@ / cpu@el\\-start@", + "MetricGroup": "transaction", + "MetricName": "tsx_cycles_per_elision", + "ScaleUnit": "1cycles / elision" + }, + { + "BriefDescription": "Number of cycles within a transaction divided by the number of transactions.", + "MetricExpr": "cpu@cycles\\-t@ / cpu@tx\\-start@", + "MetricGroup": "transaction", + "MetricName": "tsx_cycles_per_transaction", + "ScaleUnit": "1cycles / transaction" + }, + { + "BriefDescription": "Percentage of cycles within a transaction region.", + "MetricExpr": "cpu@cycles\\-t@ / cycles", + "MetricGroup": "transaction", + "MetricName": "tsx_transactional_cycles", "ScaleUnit": "100%" } ] diff --git a/tools/perf/pmu-events/arch/x86/icelake/pipeline.json b/tools/perf/pmu-events/arch/x86/icelake/pipeline.json index 3b31a842a0b1..154fee4b60fb 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/icelake/pipeline.json @@ -158,6 +158,15 @@ "SampleAfterValue": "50021", "UMask": "0x20" }, + { + "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.RET", + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.", + "SampleAfterValue": "50021", + "UMask": "0x8" + }, { "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.", "EventCode": "0xec", @@ -375,6 +384,16 @@ "SampleAfterValue": "2000003", "UMask": "0x3" }, + { + "BriefDescription": "Clears speculative count", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.CLEARS_COUNT", + "PublicDescription": "Counts the number of speculative clears due to any type of branch misprediction or machine clears", + "SampleAfterValue": "500009", + "UMask": "0x1" + }, { "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", "EventCode": "0x0d", @@ -747,7 +766,7 @@ "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.", "EventCode": "0x0e", "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", - "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.", + "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to 'Mixing Intel AVX and Intel SSE Code' section of the Optimization Guide.", "SampleAfterValue": "100003", "UMask": "0x2" }, @@ -775,7 +794,7 @@ "EventCode": "0xc2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", "Invert": "1", - "PublicDescription": "Counts the number of cycles using always true condition (uops_ret &lt; 16) applied to non PEBS uops retired event.", + "PublicDescription": "Counts the number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.", "SampleAfterValue": "1000003", "UMask": "0x2" } diff --git a/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json b/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json index f7aff8818f46..b27d95b2c857 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json @@ -7,6 +7,54 @@ "UMask": "0x1", "Unit": "ARB" }, + { + "BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core. This event is not supported on ICL products but is supported on RKL products.", + "EventCode": "0x85", + "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core. This event is not supported on ICL products but is supported on RKL products.", + "EventCode": "0x85", + "EventName": "UNC_ARB_DAT_OCCUPANCY.RD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches. This event is not supported on ICL products but is supported on RKL products.", + "EventCode": "0x80", + "EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches", + "EventCode": "0x81", + "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic. This event is not supported on ICL products but is supported on RKL products.", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches. This event is not supported on ICL products but is supported on RKL products.", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.RD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, { "BriefDescription": "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.", "EventCode": "0x81", @@ -15,6 +63,14 @@ "UMask": "0x1", "Unit": "ARB" }, + { + "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches. This event is not supported on ICL products but is supported on RKL products.", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.RD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, { "BriefDescription": "UNC_CLOCK.SOCKET", "EventCode": "0xff", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 1677ec22e2e3..b258702e0666 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -12,7 +12,7 @@ GenuineIntel-6-7A,v1.01,goldmontplus,core GenuineIntel-6-A[DE],v1.00,graniterapids,core GenuineIntel-6-(3C|45|46),v32,haswell,core GenuineIntel-6-3F,v26,haswellx,core -GenuineIntel-6-(7D|7E|A7),v1.15,icelake,core +GenuineIntel-6-(7D|7E|A7),v1.17,icelake,core GenuineIntel-6-6[AC],v1.17,icelakex,core GenuineIntel-6-3A,v23,ivybridge,core GenuineIntel-6-3E,v22,ivytown,core -- cgit v1.2.3-58-ga151 From 384133a4ede3d2eee056feaf26292574d8d71095 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:17 -0800 Subject: perf vendor events intel: Refresh icelakex metrics Update the icelakex metrics to TMA version 4.5. Generation was done using https://github.com/intel/perfmon. Notable changes are TMA info metrics are renamed from their node name to be lower case and prefixed by tma_info_, MetricThreshold expressions are added, "Sample with" documentation is added to many TMA metrics, smi_cost and transaction metric groups are added replicating existing hard coded metrics in stat-shadow. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-21-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/icelakex/icx-metrics.json | 2153 ++++++++++---------- .../arch/x86/icelakex/uncore-memory.json | 2 +- .../pmu-events/arch/x86/icelakex/uncore-other.json | 4 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 4 files changed, 1100 insertions(+), 1061 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json index 22b2a97d0ff8..8109088a4df7 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json @@ -1,1529 +1,1568 @@ [ { - "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", - "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "Mispredictions" - }, - { - "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks", - "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "Memory_Bandwidth" - }, - { - "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)", - "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound))", - "MetricGroup": "Mem;MemoryLat;Offcore", - "MetricName": "Memory_Latency" - }, - { - "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", - "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))", - "MetricGroup": "Mem;MemoryTLB;Offcore", - "MetricName": "Memory_Data_TLBs" - }, - { - "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", - "MetricExpr": "100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)", - "MetricGroup": "Ret", - "MetricName": "Branching_Overhead" - }, - { - "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", - "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", - "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB", - "MetricName": "Big_Code" - }, - { - "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", - "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code", - "MetricGroup": "Fed;FetchBW;Frontend", - "MetricName": "Instruction_Fetch_BW" - }, - { - "BriefDescription": "Instructions Per Cycle (per Logical Processor)", - "MetricExpr": "INST_RETIRED.ANY / CLKS", - "MetricGroup": "Ret;Summary", - "MetricName": "IPC" - }, - { - "BriefDescription": "Uops Per Instruction", - "MetricExpr": "tma_retiring * SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Ret;Retire", - "MetricName": "UPI" - }, - { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "tma_retiring * SLOTS / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW", - "MetricName": "UpTB" - }, - { - "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / IPC", - "MetricGroup": "Mem;Pipeline", - "MetricName": "CPI" - }, - { - "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Pipeline", - "MetricName": "CLKS" - }, - { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", - "MetricExpr": "TOPDOWN.SLOTS", - "MetricGroup": "tma_L1_group", - "MetricName": "SLOTS" - }, - { - "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", - "MetricExpr": "(SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)", - "MetricGroup": "SMT;tma_L1_group", - "MetricName": "Slots_Utilization" - }, - { - "BriefDescription": "The ratio of Executed- by Issued-Uops", - "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", - "MetricGroup": "Cor;Pipeline", - "MetricName": "Execute_per_Issue", - "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." - }, - { - "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS", - "MetricGroup": "Ret;SMT;tma_L1_group", - "MetricName": "CoreIPC" - }, - { - "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS", - "MetricGroup": "Flops;Ret", - "MetricName": "FLOPc" - }, - { - "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "FP_Arith_Utilization", - "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." - }, - { - "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", - "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", - "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", - "MetricName": "ILP" - }, - { - "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", - "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)", - "MetricGroup": "Cor;SMT", - "MetricName": "Core_Bound_Likely" - }, - { - "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", - "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED", - "MetricGroup": "SMT", - "MetricName": "CORE_CLKS" - }, - { - "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", - "MetricGroup": "InsType", - "MetricName": "IpLoad" - }, - { - "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", - "MetricGroup": "InsType", - "MetricName": "IpStore" - }, - { - "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Fed;InsType", - "MetricName": "IpBranch" - }, - { - "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "IpCall" + "BriefDescription": "C1 residency percent per core", + "MetricExpr": "cstate_core@c1\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C1_Core_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", - "MetricName": "IpTB" + "BriefDescription": "C2 residency percent per package", + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C2_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "BpTkBranch" + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)", - "MetricGroup": "Flops;InsType", - "MetricName": "IpFLOP" + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))", - "MetricGroup": "Flops;InsType", - "MetricName": "IpArith", - "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "tma_info_socket_clks / #num_dies / duration_time / 1e9", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" }, { - "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", - "MetricGroup": "Flops;FpScalar;InsType", - "MetricName": "IpArith_Scalar_SP", - "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "Percentage of cycles spent in System Management Interrupts.", + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", + "MetricGroup": "smi", + "MetricName": "smi_cycles", + "MetricThreshold": "smi_cycles > 0.1", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", - "MetricGroup": "Flops;FpScalar;InsType", - "MetricName": "IpArith_Scalar_DP", - "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "Number of SMI interrupts.", + "MetricExpr": "msr@smi@", + "MetricGroup": "smi", + "MetricName": "smi_num", + "ScaleUnit": "1SMI#" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX128", - "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", + "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_4k_aliasing", + "MetricThreshold": "tma_4k_aliasing > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX256", - "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5 + UOPS_DISPATCHED.PORT_6) / (4 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_alu_op_utilization", + "MetricThreshold": "tma_alu_op_utilization > 0.6", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX512", - "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", + "MetricExpr": "100 * ASSISTS.ANY / tma_info_slots", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_assists", + "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", - "MetricGroup": "Prefetches", - "MetricName": "IpSWPF" + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", + "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=1\\,edge@ / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_backend_bound", + "MetricThreshold": "tma_backend_bound > 0.2", + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary;tma_L1_group", - "MetricName": "Instructions" + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", + "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_bad_speculation", + "MetricThreshold": "tma_bad_speculation > 0.15", + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", - "MetricExpr": "tma_retiring * SLOTS / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@", - "MetricGroup": "Pipeline;Ret", - "MetricName": "Retire" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions.", + "MetricExpr": "tma_light_operations * BR_INST_RETIRED.ALL_BRANCHES / (tma_retiring * tma_info_slots)", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_branch_instructions", + "MetricThreshold": "tma_branch_instructions > 0.1 & tma_light_operations > 0.6", + "ScaleUnit": "100%" }, { - "BriefDescription": "", - "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", - "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", - "MetricName": "Execute" + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", + "MetricName": "tma_branch_mispredicts", + "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredicts_resteers", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of Uops issued by front-end when it issued something", - "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@", - "MetricGroup": "Fed;FetchBW", - "MetricName": "Fetch_UpC" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", + "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks + tma_unknown_branches", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_branch_resteers", + "MetricThreshold": "tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "DSB;Fed;FetchBW", - "MetricName": "DSB_Coverage" + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", + "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_cisc", + "MetricThreshold": "tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@", - "MetricGroup": "DSBmiss", - "MetricName": "DSB_Switch_Cost" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears", + "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks", + "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC", + "MetricName": "tma_clears_resteers", + "MetricThreshold": "tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches", + "ScaleUnit": "100%" }, { - "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.", - "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))", - "MetricGroup": "DSBmiss;Fed", - "MetricName": "DSB_Misses" + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(44 * tma_info_average_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 43.5 * tma_info_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_contested_accesses", + "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", - "MetricGroup": "DSBmiss;Fed", - "MetricName": "IpDSB_Miss_Ret" + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", + "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)", + "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "43.5 * tma_info_average_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_data_sharing", + "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BrMispredicts", - "MetricName": "Branch_Misprediction_Cost" + "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", + "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) / tma_info_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_issueD0;tma_mite_group", + "MetricName": "tma_decoder0_alone", + "MetricThreshold": "tma_decoder0_alone > 0.1 & (tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 5 > 0.35))", + "PublicDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder. Related metrics: tma_few_uops_instructions", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of branches that are non-taken conditionals", - "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches;CodeGen;PGO", - "MetricName": "Cond_NT" + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", + "MetricExpr": "ARITH.DIVIDER_ACTIVE / tma_info_clks", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_divider", + "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of branches that are taken conditionals", - "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches;CodeGen;PGO", - "MetricName": "Cond_TK" + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks - tma_l2_bound - tma_pmm_bound", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_dram_bound", + "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of branches that are CALL or RET", - "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches", - "MetricName": "CallRet" + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", + "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / tma_info_core_clks / 2", + "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_dsb", + "MetricThreshold": "tma_dsb > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 5 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", - "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches", - "MetricName": "Jump" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_clks", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_dsb_switches", + "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", - "MetricExpr": "1 - (Cond_NT + Cond_TK + CallRet + Jump)", - "MetricGroup": "Bad;Branches", - "MetricName": "Other_Branches" + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", + "MetricExpr": "min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group", + "MetricName": "tma_dtlb_load", + "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store, tma_info_memory_data_tlbs", + "ScaleUnit": "100%" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)", - "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency" + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", + "MetricExpr": "(7 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group", + "MetricName": "tma_dtlb_store", + "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, tma_info_memory_data_tlbs", + "ScaleUnit": "100%" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "Mem;MemoryBW;MemoryBound", - "MetricName": "MLP" + "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", + "MetricExpr": "48 * tma_info_average_frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group", + "MetricName": "tma_false_sharing", + "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI" + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", + "MetricExpr": "L1D_PEND_MISS.FB_FULL / tma_info_clks", + "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricName": "tma_fb_full", + "MetricThreshold": "tma_fb_full > 0.3", + "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_dram_bw_use, tma_info_memory_bandwidth, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", + "ScaleUnit": "100%" }, { - "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI_Load" + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", + "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)", + "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", + "MetricName": "tma_fetch_bandwidth", + "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 5 > 0.35", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Backend;CacheMisses;Mem", - "MetricName": "L2MPKI" + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", + "MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / tma_info_slots", + "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_latency", + "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", - "MetricExpr": "1e3 * (OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS) / Instructions", - "MetricGroup": "CacheMisses;Mem;Offcore", - "MetricName": "L2MPKI_All" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops", + "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer", + "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueD0", + "MetricName": "tma_few_uops_instructions", + "MetricThreshold": "tma_few_uops_instructions > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions. Related metrics: tma_decoder0_alone", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2MPKI_Load" + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", + "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", + "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_fp_arith", + "MetricThreshold": "tma_fp_arith > 0.2 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2HPKI_Load" + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", + "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_scalar", + "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L3MPKI" + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", + "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_vector", + "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "FB_HPKI" + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_128b", + "MetricThreshold": "tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (2 * CORE_CLKS)", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "Page_Walks_Utilization" + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_256b", + "MetricThreshold": "tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_512b", + "MetricThreshold": "tma_fp_vector_512b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", + "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / tma_info_slots", + "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.15", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences", + "MetricExpr": "tma_microcode_sequencer + tma_retiring * (UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=1@) / IDQ.MITE_UOPS", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_heavy_operations", + "MetricThreshold": "tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses", + "MetricExpr": "ICACHE_16B.IFDATA_STALL / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_icache_misses", + "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)", - "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / Instructions", - "MetricGroup": "L2Evicts;Mem;Server", - "MetricName": "L2_Evictions_Silent_PKI" + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "tma_info_turbo_utilization * TSC / 1e9 / duration_time", + "MetricGroup": "Power;Summary", + "MetricName": "tma_info_average_frequency" }, { - "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction", - "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / Instructions", - "MetricGroup": "L2Evicts;Mem;Server", - "MetricName": "L2_Evictions_NonSilent_PKI" + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB;tma_issueBC", + "MetricName": "tma_info_big_code", + "MetricThreshold": "tma_info_big_code > 20", + "PublicDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses). Related metrics: tma_info_branching_overhead" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "L1D_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW_1T" + "BriefDescription": "Branch instructions per taken branch.", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_bptkbranch" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "L2_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW_1T" + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_slots / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts;tma_issueBM", + "MetricName": "tma_info_branch_misprediction_cost", + "PublicDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_branch_mispredicts, tma_info_mispredictions, tma_mispredicts_resteers" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW_1T" + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "MetricExpr": "100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL)) / tma_info_slots)", + "MetricGroup": "Ret;tma_issueBC", + "MetricName": "tma_info_branching_overhead", + "MetricThreshold": "tma_info_branching_overhead > 10", + "PublicDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls). Related metrics: tma_info_big_code" }, { - "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Access_BW", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW_1T" + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_callret" }, { - "BriefDescription": "Average CPU Utilization", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", - "MetricGroup": "HPC;Summary", - "MetricName": "CPU_Utilization" + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline", + "MetricName": "tma_info_clks" }, { - "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", - "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time", - "MetricGroup": "Power;Summary", - "MetricName": "Average_Frequency" + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Fed;MemoryTLB", + "MetricName": "tma_info_code_stlb_mpki" }, { - "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs", - "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "tma_info_cond_nt" }, { - "BriefDescription": "Average Frequency Utilization relative nominal frequency", - "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC", - "MetricGroup": "Power", - "MetricName": "Turbo_Utilization" + "BriefDescription": "Fraction of branches that are taken conditionals", + "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "tma_info_cond_tk" }, { - "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0", - "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / CORE_CLKS", - "MetricGroup": "Power", - "MetricName": "Power_License0_Utilization", - "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes." + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if tma_info_smt_2t_utilization > 0.5 else 0)", + "MetricGroup": "Cor;SMT", + "MetricName": "tma_info_core_bound_likely", + "MetricThreshold": "tma_info_core_bound_likely > 0.5" }, { - "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1", - "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / CORE_CLKS", - "MetricGroup": "Power", - "MetricName": "Power_License1_Utilization", - "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions." + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED", + "MetricGroup": "SMT", + "MetricName": "tma_info_core_clks" }, { - "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)", - "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / CORE_CLKS", - "MetricGroup": "Power", - "MetricName": "Power_License2_Utilization", - "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions." + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_core_clks", + "MetricGroup": "Ret;SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_coreipc" }, { - "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", - "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)", - "MetricGroup": "SMT", - "MetricName": "SMT_2T_Utilization" + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / tma_info_ipc", + "MetricGroup": "Mem;Pipeline", + "MetricName": "tma_info_cpi" }, { - "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "OS", - "MetricName": "Kernel_Utilization" + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "HPC;Summary", + "MetricName": "tma_info_cpu_utilization" }, { - "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", - "MetricGroup": "OS", - "MetricName": "Kernel_CPI" + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_data_l2_mlp" }, { "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time", - "MetricGroup": "HPC;Mem;MemoryBW;SoC", - "MetricName": "DRAM_BW_Use" + "MetricGroup": "HPC;Mem;MemoryBW;SoC;tma_issueBW", + "MetricName": "tma_info_dram_bw_use", + "PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_info_memory_bandwidth, tma_mem_bandwidth, tma_sq_full" }, { - "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches", - "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (Socket_CLKS / duration_time)", - "MetricGroup": "Mem;MemoryLat;SoC", - "MetricName": "MEM_Read_Latency" + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / UOPS_ISSUED.ANY", + "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", + "MetricName": "tma_info_dsb_coverage", + "MetricThreshold": "tma_info_dsb_coverage < 0.7 & tma_info_ipc / 5 > 0.35", + "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_misses, tma_info_iptb, tma_lcp" }, { - "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", - "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@thresh\\=1@", - "MetricGroup": "Mem;MemoryBW;SoC", - "MetricName": "MEM_Parallel_Reads" + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck", + "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))", + "MetricGroup": "DSBmiss;Fed;tma_issueFB", + "MetricName": "tma_info_dsb_misses", + "MetricThreshold": "tma_info_dsb_misses > 10", + "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_iptb, tma_lcp" }, { - "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", - "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / cha_0@event\\=0x0@", - "MetricGroup": "Mem;MemoryLat;Server;SoC", - "MetricName": "MEM_PMM_Read_Latency" + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@", + "MetricGroup": "DSBmiss", + "MetricName": "tma_info_dsb_switch_cost" }, { - "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", - "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / cha_0@event\\=0x0@", - "MetricGroup": "Mem;MemoryLat;Server;SoC", - "MetricName": "MEM_DRAM_Read_Latency" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-thread", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "tma_info_execute" }, { - "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]", - "MetricExpr": "64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW;Server;SoC", - "MetricName": "PMM_Read_BW" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "tma_info_execute_per_issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." }, { - "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]", - "MetricExpr": "64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW;Server;SoC", - "MetricName": "PMM_Write_BW" + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_fb_hpki" }, { - "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]", - "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e9 / duration_time", - "MetricGroup": "IoBW;Mem;Server;SoC", - "MetricName": "IO_Write_BW" + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_fetch_upc" }, { - "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]", - "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR) * 64 / 1e9 / duration_time", - "MetricGroup": "IoBW;Mem;Server;SoC", - "MetricName": "IO_Read_BW" + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * cpu@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE\\,umask\\=0x18@ + 8 * cpu@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE\\,umask\\=0x60@ + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / tma_info_core_clks", + "MetricGroup": "Flops;Ret", + "MetricName": "tma_info_flopc" }, { - "BriefDescription": "Socket actual clocks when any core is active on that socket", - "MetricExpr": "cha_0@event\\=0x0@", - "MetricGroup": "SoC", - "MetricName": "Socket_CLKS" + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@) / (2 * tma_info_core_clks)", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_fp_arith_utilization", + "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." }, { - "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", - "MetricGroup": "Branches;OS", - "MetricName": "IpFarBranch" + "BriefDescription": "Giga Floating Point Operations Per Second", + "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * cpu@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE\\,umask\\=0x18@ + 8 * cpu@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE\\,umask\\=0x60@ + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_gflops", + "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." }, { - "BriefDescription": "Uncore frequency per die [GHZ]", - "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9", - "MetricGroup": "SoC", - "MetricName": "UNCORE_FREQ" + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck", + "MetricExpr": "100 * (tma_fetch_latency * tma_icache_misses / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", + "MetricGroup": "Fed;FetchLat;IcMiss;tma_issueFL", + "MetricName": "tma_info_ic_misses", + "MetricThreshold": "tma_info_ic_misses > 5", + "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck. Related metrics: " }, { - "BriefDescription": "Percentage of time spent in the active CPU power state C0", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", - "MetricName": "cpu_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Average Latency for L1 instruction cache misses", + "MetricExpr": "ICACHE_16B.IFDATA_STALL / cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@", + "MetricGroup": "Fed;FetchLat;IcMiss", + "MetricName": "tma_info_icache_miss_latency" + }, + { + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", + "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", + "MetricName": "tma_info_ilp" }, { - "BriefDescription": "CPU operating frequency (in GHz)", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / duration_time", - "MetricName": "cpu_operating_frequency", - "ScaleUnit": "1GHz" + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_big_code", + "MetricGroup": "Fed;FetchBW;Frontend", + "MetricName": "tma_info_instruction_fetch_bw", + "MetricThreshold": "tma_info_instruction_fetch_bw > 20" }, { - "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY", - "MetricName": "cpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;tma_L1_group", + "MetricName": "tma_info_instructions", + "PublicDescription": "Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST" }, { - "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions", - "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY", - "MetricName": "loads_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]", + "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR) * 64 / 1e9 / duration_time", + "MetricGroup": "IoBW;Mem;Server;SoC", + "MetricName": "tma_info_io_read_bw" }, { - "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions", - "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY", - "MetricName": "stores_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e9 / duration_time", + "MetricGroup": "IoBW;Mem;Server;SoC", + "MetricName": "tma_info_io_write_bw" }, { - "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions", - "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY", - "MetricName": "l1d_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_iparith", + "MetricThreshold": "tma_info_iparith < 10", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." }, { - "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ", - "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY", - "MetricName": "l1d_demand_data_read_hits_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx128", + "MetricThreshold": "tma_info_iparith_avx128 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions", - "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY", - "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx256", + "MetricThreshold": "tma_info_iparith_avx256 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ", - "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY", - "MetricName": "l2_demand_data_read_hits_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx512", + "MetricThreshold": "tma_info_iparith_avx512 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions", - "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY", - "MetricName": "l2_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_iparith_scalar_dp", + "MetricThreshold": "tma_info_iparith_scalar_dp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions", - "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricName": "l2_demand_data_read_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_iparith_scalar_sp", + "MetricThreshold": "tma_info_iparith_scalar_sp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions", - "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", - "MetricName": "l2_demand_code_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "tma_info_ipbranch", + "MetricThreshold": "tma_info_ipbranch < 8" }, { - "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", - "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA + UNC_CHA_TOR_INSERTS.IA_MISS_DRD + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF) / INST_RETIRED.ANY", - "MetricName": "llc_data_read_mpi_demand_plus_prefetch", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_clks", + "MetricGroup": "Ret;Summary", + "MetricName": "tma_info_ipc" }, { - "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", - "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_CRD + UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF) / INST_RETIRED.ANY", - "MetricName": "llc_code_read_mpi_demand_plus_prefetch", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_ipcall", + "MetricThreshold": "tma_info_ipcall < 200" }, { - "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds", - "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD) * #num_packages)) * duration_time", - "MetricName": "llc_demand_data_read_miss_latency", - "ScaleUnit": "1ns" + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "tma_info_ipdsb_miss_ret", + "MetricThreshold": "tma_info_ipdsb_miss_ret < 50" }, { - "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to local memory in nano seconds", - "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL) * #num_packages)) * duration_time", - "MetricName": "llc_demand_data_read_miss_latency_for_local_requests", - "ScaleUnit": "1ns" + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "tma_info_ipfarbranch", + "MetricThreshold": "tma_info_ipfarbranch < 1e6" }, { - "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to remote memory in nano seconds", - "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE) * #num_packages)) * duration_time", - "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests", - "ScaleUnit": "1ns" + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * cpu@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE\\,umask\\=0x18@ + 8 * cpu@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE\\,umask\\=0x60@ + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_ipflop", + "MetricThreshold": "tma_info_ipflop < 10" }, { - "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to Intel(R) Optane(TM) Persistent Memory(PMEM) in nano seconds", - "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM) * #num_packages)) * duration_time", - "MetricName": "llc_demand_data_read_miss_to_pmem_latency", - "ScaleUnit": "1ns" + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipload", + "MetricThreshold": "tma_info_ipload < 3" }, { - "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to DRAM in nano seconds", - "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR) * #num_packages)) * duration_time", - "MetricName": "llc_demand_data_read_miss_to_dram_latency", - "ScaleUnit": "1ns" + "BriefDescription": "Instructions per retired mispredicts for conditional non-taken branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_NTAKEN", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_cond_ntaken", + "MetricThreshold": "tma_info_ipmisp_cond_ntaken < 200" }, { - "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions", - "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", - "MetricName": "itlb_2nd_level_mpi", - "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per retired mispredicts for conditional taken branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_cond_taken", + "MetricThreshold": "tma_info_ipmisp_cond_taken < 200" }, { - "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions", - "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY", - "MetricName": "itlb_2nd_level_large_page_mpi", - "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_indirect", + "MetricThreshold": "tma_info_ipmisp_indirect < 1e3" }, { - "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions", - "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", - "MetricName": "dtlb_2nd_level_load_mpi", - "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per retired mispredicts for return branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RET", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_ret", + "MetricThreshold": "tma_info_ipmisp_ret < 500" }, { - "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions", - "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY", - "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi", - "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "tma_info_ipmispredict", + "MetricThreshold": "tma_info_ipmispredict < 200" }, { - "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions", - "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", - "MetricName": "dtlb_2nd_level_store_mpi", - "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipstore", + "MetricThreshold": "tma_info_ipstore < 8" }, { - "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", - "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE)", - "MetricName": "numa_reads_addressed_to_local_dram", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", + "MetricGroup": "Prefetches", + "MetricName": "tma_info_ipswpf", + "MetricThreshold": "tma_info_ipswpf < 100" }, { - "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", - "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE)", - "MetricName": "numa_reads_addressed_to_remote_dram", - "ScaleUnit": "100%" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", + "MetricName": "tma_info_iptb", + "MetricThreshold": "tma_info_iptb < 11", + "PublicDescription": "Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_dsb_misses, tma_lcp" }, { - "BriefDescription": "Uncore operating frequency in GHz", - "MetricExpr": "UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages) / 1e9 / duration_time", - "MetricName": "uncore_frequency", - "ScaleUnit": "1GHz" + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "tma_info_instructions / BACLEARS.ANY", + "MetricGroup": "Fed", + "MetricName": "tma_info_ipunknown_branch" }, { - "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)", - "MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 7.111111111111111 / 1e6 / duration_time", - "MetricName": "upi_data_transmit_bw", - "ScaleUnit": "1MB/s" + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_jump" }, { - "BriefDescription": "DDR memory read bandwidth (MB/sec)", - "MetricExpr": "UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time", - "MetricName": "memory_bandwidth_read", - "ScaleUnit": "1MB/s" + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_cpi" }, { - "BriefDescription": "DDR memory write bandwidth (MB/sec)", - "MetricExpr": "UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time", - "MetricName": "memory_bandwidth_write", - "ScaleUnit": "1MB/s" + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_utilization", + "MetricThreshold": "tma_info_kernel_utilization > 0.05" }, { - "BriefDescription": "DDR memory bandwidth (MB/sec)", - "MetricExpr": "(UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e6 / duration_time", - "MetricName": "memory_bandwidth_total", - "ScaleUnit": "1MB/s" + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw" }, { - "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)", - "MetricExpr": "UNC_M_PMM_RPQ_INSERTS * 64 / 1e6 / duration_time", - "MetricName": "pmem_memory_bandwidth_read", - "ScaleUnit": "1MB/s" + "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "tma_info_l1d_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw_1t" }, { - "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)", - "MetricExpr": "UNC_M_PMM_WPQ_INSERTS * 64 / 1e6 / duration_time", - "MetricName": "pmem_memory_bandwidth_write", - "ScaleUnit": "1MB/s" + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l1mpki" }, { - "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)", - "MetricExpr": "(UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS) * 64 / 1e6 / duration_time", - "MetricName": "pmem_memory_bandwidth_total", - "ScaleUnit": "1MB/s" + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l1mpki_load" }, { - "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.", - "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR + UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR) * 64 / 1e6 / duration_time", - "MetricName": "io_bandwidth_disk_or_network_writes", - "ScaleUnit": "1MB/s" + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw" }, { - "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.", - "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR) * 64 / 1e6 / duration_time", - "MetricName": "io_bandwidth_disk_or_network_reads", - "ScaleUnit": "1MB/s" + "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "tma_info_l2_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw_1t" }, { - "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue", - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)", - "MetricName": "percent_uops_delivered_from_decoded_icache", - "ScaleUnit": "100%" + "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction", + "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / tma_info_instructions", + "MetricGroup": "L2Evicts;Mem;Server", + "MetricName": "tma_info_l2_evictions_nonsilent_pki" }, { - "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue", - "MetricExpr": "IDQ.MITE_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)", - "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline", - "ScaleUnit": "100%" + "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)", + "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / tma_info_instructions", + "MetricGroup": "L2Evicts;Mem;Server", + "MetricName": "tma_info_l2_evictions_silent_pki" }, { - "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue", - "MetricExpr": "IDQ.MS_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)", - "MetricName": "percent_uops_delivered_from_microcode_sequencer", - "ScaleUnit": "100%" + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2hpki_load" }, { - "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.", - "MetricExpr": "UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1e6 / duration_time", - "MetricName": "llc_miss_local_memory_bandwidth_read", - "ScaleUnit": "1MB/s" + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Backend;CacheMisses;Mem", + "MetricName": "tma_info_l2mpki" }, { - "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.", - "MetricExpr": "UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1e6 / duration_time", - "MetricName": "llc_miss_local_memory_bandwidth_write", - "ScaleUnit": "1MB/s" + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "MetricExpr": "1e3 * (OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS) / tma_info_instructions", + "MetricGroup": "CacheMisses;Mem;Offcore", + "MetricName": "tma_info_l2mpki_all" }, { - "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.", - "MetricExpr": "UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1e6 / duration_time", - "MetricName": "llc_miss_remote_memory_bandwidth_read", - "ScaleUnit": "1MB/s" + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction", + "MetricExpr": "1e3 * FRONTEND_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss", + "MetricName": "tma_info_l2mpki_code" }, { - "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.", - "MetricExpr": "UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1e6 / duration_time", - "MetricName": "llc_miss_remote_memory_bandwidth_write", - "ScaleUnit": "1MB/s" + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction", + "MetricExpr": "1e3 * L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss", + "MetricName": "tma_info_l2mpki_code_all" }, { - "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / slots", - "MetricGroup": "PGO;TopdownL1;tma_L1_group;tma_L1_group", - "MetricName": "tma_frontend_bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", - "ScaleUnit": "100%" + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2mpki_load" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", - "MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / slots", - "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_latency", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.", - "ScaleUnit": "100%" + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_l3_cache_access_bw" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", - "MetricExpr": "ICACHE_16B.IFDATA_STALL / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_icache_misses", - "ScaleUnit": "100%" + "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_l3_cache_access_bw", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_l3_cache_access_bw_1t" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.", - "MetricExpr": "ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_itlb_misses", - "ScaleUnit": "100%" + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", - "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + tma_unknown_branches", - "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_branch_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.", - "ScaleUnit": "100%" + "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_l3_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw_1t" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group", - "MetricName": "tma_mispredicts_resteers", - "ScaleUnit": "100%" + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l3mpki" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ", - "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group", - "MetricName": "tma_clears_resteers", - "ScaleUnit": "100%" + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore", + "MetricName": "tma_info_load_l2_miss_latency" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", - "MetricExpr": "10 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", - "MetricName": "tma_unknown_branches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit).", - "ScaleUnit": "100%" + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,cmask\\=1@", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_load_l2_mlp" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_dsb_switches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", - "ScaleUnit": "100%" + "BriefDescription": "Average Latency for L3 cache miss demand Loads", + "MetricExpr": "cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,umask\\=0x10@ / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore", + "MetricName": "tma_info_load_l3_miss_latency" }, { - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", - "MetricExpr": "ILD_STALL.LCP / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_lcp", - "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", - "ScaleUnit": "100%" + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "tma_info_load_miss_real_latency" }, { - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", - "MetricExpr": "3 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_ms_switches", - "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", - "ScaleUnit": "100%" + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_load_stlb_mpki" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", - "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)", - "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_bandwidth", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", - "ScaleUnit": "100%" + "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]", + "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / cha_0@event\\=0x0@", + "MetricGroup": "Mem;MemoryLat;Server;SoC", + "MetricName": "tma_info_mem_dram_read_latency", + "PublicDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", - "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / CPU_CLK_UNHALTED.DISTRIBUTED / 2", - "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", - "MetricName": "tma_mite", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", - "ScaleUnit": "100%" + "BriefDescription": "Average number of parallel data read requests to external memory", + "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@thresh\\=1@", + "MetricGroup": "Mem;MemoryBW;SoC", + "MetricName": "tma_info_mem_parallel_reads", + "PublicDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches" }, { - "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", - "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=0x1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=0x2@) / CPU_CLK_UNHALTED.DISTRIBUTED", - "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group", - "MetricName": "tma_decoder0_alone", - "ScaleUnit": "100%" + "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]", + "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / cha_0@event\\=0x0@", + "MetricGroup": "Mem;MemoryLat;Server;SoC", + "MetricName": "tma_info_mem_pmm_read_latency", + "PublicDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches" }, { - "BriefDescription": "This metric represents fraction of cycles where (only) 4 uops were delivered by the MITE pipeline", - "MetricExpr": "(cpu@IDQ.MITE_UOPS\\,cmask\\=0x4@ - cpu@IDQ.MITE_UOPS\\,cmask\\=0x5@) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group", - "MetricName": "tma_mite_4wide", - "ScaleUnit": "100%" + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds)", + "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (tma_info_socket_clks / duration_time)", + "MetricGroup": "Mem;MemoryLat;SoC", + "MetricName": "tma_info_mem_read_latency", + "PublicDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", - "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / CPU_CLK_UNHALTED.DISTRIBUTED / 2", - "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", - "MetricName": "tma_dsb", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks", + "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))", + "MetricGroup": "Mem;MemoryBW;Offcore;tma_issueBW", + "MetricName": "tma_info_memory_bandwidth", + "MetricThreshold": "tma_info_memory_bandwidth > 20", + "PublicDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_mem_bandwidth, tma_sq_full" }, { - "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", - "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)), 0)", - "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group", - "MetricName": "tma_bad_speculation", - "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", + "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))", + "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", + "MetricName": "tma_info_memory_data_tlbs", + "MetricThreshold": "tma_info_memory_data_tlbs > 20", + "PublicDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_branch_mispredicts", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)", + "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound))", + "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", + "MetricName": "tma_info_memory_latency", + "MetricThreshold": "tma_info_memory_latency > 20", + "PublicDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches). Related metrics: tma_l3_hit_latency, tma_mem_latency" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", - "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)", - "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_machine_clears", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", + "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", + "MetricName": "tma_info_mispredictions", + "MetricThreshold": "tma_info_mispredictions > 20", + "PublicDescription": "Total pipeline cost of Branch Misprediction related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_branch_misprediction_cost, tma_mispredicts_resteers" }, { - "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", - "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=0x1\\,edge\\=0x1@ / slots", - "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group", - "MetricName": "tma_backend_bound", - "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", - "ScaleUnit": "100%" + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBW;MemoryBound", + "MetricName": "tma_info_mlp", + "PublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)" }, { - "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound", - "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_memory_bound", - "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", + "MetricExpr": "1 - (tma_info_cond_nt + tma_info_cond_tk + tma_info_callret + tma_info_jump)", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_other_branches" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", - "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CPU_CLK_UNHALTED.THREAD, 0)", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_l1_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.", - "ScaleUnit": "100%" + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (2 * tma_info_core_clks)", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_page_walks_utilization", + "MetricThreshold": "tma_info_page_walks_utilization > 0.5" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", - "MetricExpr": "min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_dtlb_load", - "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.", - "ScaleUnit": "100%" + "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]", + "MetricExpr": "64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW;Server;SoC", + "MetricName": "tma_info_pmm_read_bw" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", - "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss", - "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", - "MetricName": "tma_load_stlb_hit", - "ScaleUnit": "100%" + "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]", + "MetricExpr": "64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW;Server;SoC", + "MetricName": "tma_info_pmm_write_bw" }, { - "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", - "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", - "MetricName": "tma_load_stlb_miss", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0", + "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / tma_info_core_clks", + "MetricGroup": "Power", + "MetricName": "tma_info_power_license0_utilization", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes." }, { - "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", - "MetricExpr": "min(13 * LD_BLOCKS.STORE_FORWARD / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_store_fwd_blk", - "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1", + "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / tma_info_core_clks", + "MetricGroup": "Power", + "MetricName": "tma_info_power_license1_utilization", + "MetricThreshold": "tma_info_power_license1_utilization > 0.5", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions." }, { - "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", - "MetricExpr": "min((16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_lock_latency", - "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)", + "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / tma_info_core_clks", + "MetricGroup": "Power", + "MetricName": "tma_info_power_license2_utilization", + "MetricThreshold": "tma_info_power_license2_utilization > 0.5", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions." }, { - "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ", - "MetricExpr": "min(Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_split_loads", - "ScaleUnit": "100%" + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "MetricExpr": "tma_retiring * tma_info_slots / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "tma_info_retire" }, { - "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", - "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_4k_aliasing", - "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", - "ScaleUnit": "100%" + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "TOPDOWN.SLOTS", + "MetricGroup": "TmaL1;tma_L1_group", + "MetricName": "tma_info_slots" }, { - "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", - "MetricExpr": "L1D_PEND_MISS.FB_FULL / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_fb_full", - "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", + "MetricExpr": "(tma_info_slots / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)", + "MetricGroup": "SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_slots_utilization" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", - "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD)", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_l2_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)", + "MetricGroup": "SMT", + "MetricName": "tma_info_smt_2t_utilization" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_l3_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.", - "ScaleUnit": "100%" + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "cha_0@event\\=0x0@", + "MetricGroup": "SoC", + "MetricName": "tma_info_socket_clks" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", - "MetricExpr": "min(((48 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 4 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + (47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 4 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", - "MetricName": "tma_contested_accesses", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.", - "ScaleUnit": "100%" + "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_store_stlb_mpki" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", - "MetricExpr": "min((47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 4 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", - "MetricName": "tma_data_sharing", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.", - "ScaleUnit": "100%" + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "tma_info_clks / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power", + "MetricName": "tma_info_turbo_utilization" }, { - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", - "MetricExpr": "min((23 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 4 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group", - "MetricName": "tma_l3_hit_latency", - "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", - "ScaleUnit": "100%" + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "tma_retiring * tma_info_slots / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire", + "MetricName": "tma_info_uoppi", + "MetricThreshold": "tma_info_uoppi > 1.05" }, { - "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", - "MetricExpr": "L1D_PEND_MISS.L2_STALL / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group", - "MetricName": "tma_sq_full", - "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.", - "ScaleUnit": "100%" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "tma_retiring * tma_info_slots / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "tma_info_uptb", + "MetricThreshold": "tma_info_uptb < 7.5" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", - "MetricExpr": "min(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD - tma_l2_bound - min(((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0), 1), 1)", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_dram_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", + "MetricExpr": "ICACHE_64B.IFTAG_STALL / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group", - "MetricName": "tma_mem_bandwidth", - "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", + "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / tma_info_clks, 0)", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group", + "MetricName": "tma_l1_bound", + "MetricThreshold": "tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CPU_CLK_UNHALTED.THREAD - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group", - "MetricName": "tma_mem_latency", - "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks)", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l2_bound", + "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory", - "MetricExpr": "min((66.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 23 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_local_dram", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / tma_info_clks", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l3_bound", + "MetricThreshold": "tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory", - "MetricExpr": "min((131 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 23 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_remote_dram", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", + "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", + "MetricExpr": "19 * tma_info_average_frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group", + "MetricName": "tma_l3_hit_latency", + "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_memory_latency, tma_mem_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues", - "MetricExpr": "min(((120 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 23 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + (120 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 23 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_remote_cache", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", + "MetricExpr": "ILD_STALL.LCP / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_lcp", + "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a", - "MetricExpr": "min(((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0), 1)", - "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_pmm_bound", - "PublicDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", + "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_light_operations", + "MetricThreshold": "tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", - "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_store_bound", - "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", + "MetricExpr": "UOPS_DISPATCHED.PORT_2_3 / (2 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_load_op_utilization", + "MetricThreshold": "tma_load_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", - "MetricExpr": "(L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_store_latency", - "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", + "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", + "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", + "MetricName": "tma_load_stlb_hit", + "MetricThreshold": "tma_load_stlb_hit > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", - "MetricExpr": "min(48 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_false_sharing", - "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ", + "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", + "MetricName": "tma_load_stlb_miss", + "MetricThreshold": "tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents rate of split store accesses", - "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CPU_CLK_UNHALTED.DISTRIBUTED", - "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_split_stores", - "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory", + "MetricExpr": "43.5 * tma_info_average_frequency * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group", + "MetricName": "tma_local_dram", + "MetricThreshold": "tma_local_dram > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores", - "MetricExpr": "min(9 * OCR.STREAMING_WR.ANY_RESPONSE / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_streaming_stores", - "PublicDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck.", + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / tma_info_clks", + "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group", + "MetricName": "tma_lock_latency", + "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", - "MetricExpr": "min((7 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CPU_CLK_UNHALTED.DISTRIBUTED, 1)", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_dtlb_store", - "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.", + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", + "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)", + "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", - "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss", - "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", - "MetricName": "tma_store_stlb_hit", + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW", + "MetricName": "tma_mem_bandwidth", + "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_info_memory_bandwidth, tma_sq_full", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", - "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CPU_CLK_UNHALTED.DISTRIBUTED", - "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", - "MetricName": "tma_store_stlb_miss", + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_clks - tma_mem_bandwidth", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat", + "MetricName": "tma_mem_latency", + "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_info_memory_latency, tma_l3_hit_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", - "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)", - "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_core_bound", - "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound", + "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_memory_bound", + "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", - "MetricExpr": "ARITH.DIVIDER_ACTIVE / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", - "MetricName": "tma_divider", - "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", + "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_memory_operations", + "MetricThreshold": "tma_memory_operations > 0.1 & tma_light_operations > 0.6", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", - "MetricExpr": "((cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) + 0 * slots", - "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", - "MetricName": "tma_ports_utilization", - "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", + "MetricExpr": "tma_retiring * tma_info_slots / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_slots", + "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS", + "MetricName": "tma_microcode_sequencer", + "MetricThreshold": "tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ / CPU_CLK_UNHALTED.THREAD + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_0", - "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks", + "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM", + "MetricName": "tma_mispredicts_resteers", + "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_branch_misprediction_cost, tma_info_mispredictions", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations", - "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group", - "MetricName": "tma_serializing_operation", - "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", + "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / tma_info_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_mite", + "MetricThreshold": "tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 5 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.", - "MetricExpr": "37 * MISC_RETIRED.PAUSE_INST / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group", - "MetricName": "tma_slow_pause", + "BriefDescription": "This metric represents fraction of cycles where (only) 4 uops were delivered by the MITE pipeline", + "MetricExpr": "(cpu@IDQ.MITE_UOPS\\,cmask\\=4@ - cpu@IDQ.MITE_UOPS\\,cmask\\=5@) / tma_info_clks", + "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group", + "MetricName": "tma_mite_4wide", + "MetricThreshold": "tma_mite_4wide > 0.05 & (tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 5 > 0.35))", "ScaleUnit": "100%" }, { "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY, 1)", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group", + "MetricExpr": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY", + "MetricGroup": "TopdownL5;tma_L5_group;tma_issueMV;tma_ports_utilized_0_group", "MetricName": "tma_mixing_vectors", - "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", + "MetricThreshold": "tma_mixing_vectors > 0.05", + "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic. Related metrics: tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "EXE_ACTIVITY.1_PORTS_UTIL / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_1", - "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", + "MetricExpr": "3 * IDQ.MS_SWITCHES / tma_info_clks", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", + "MetricName": "tma_ms_switches", + "MetricThreshold": "tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "EXE_ACTIVITY.2_PORTS_UTIL / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_2", - "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions", + "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (tma_retiring * tma_info_slots)", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_nop_instructions", + "MetricThreshold": "tma_nop_instructions > 0.1 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", - "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_3m", + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes", + "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_branch_instructions + tma_nop_instructions))", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_other_light_ops", + "MetricThreshold": "tma_other_light_ops > 0.3 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5 + UOPS_DISPATCHED.PORT_6) / (4 * CPU_CLK_UNHALTED.DISTRIBUTED)", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", - "MetricName": "tma_alu_op_utilization", + "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a", + "MetricExpr": "((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0)", + "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_pmm_bound", + "MetricThreshold": "tma_pmm_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module.", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", - "MetricExpr": "UOPS_DISPATCHED.PORT_0 / CPU_CLK_UNHALTED.DISTRIBUTED", - "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group", + "MetricExpr": "UOPS_DISPATCHED.PORT_0 / tma_info_core_clks", + "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", "MetricName": "tma_port_0", + "MetricThreshold": "tma_port_0 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", - "MetricExpr": "UOPS_DISPATCHED.PORT_1 / CPU_CLK_UNHALTED.DISTRIBUTED", - "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", + "MetricExpr": "UOPS_DISPATCHED.PORT_1 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", "MetricName": "tma_port_1", + "MetricThreshold": "tma_port_1 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", - "MetricExpr": "UOPS_DISPATCHED.PORT_5 / CPU_CLK_UNHALTED.DISTRIBUTED", - "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", + "MetricExpr": "UOPS_DISPATCHED.PORT_5 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", "MetricName": "tma_port_5", + "MetricThreshold": "tma_port_5 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Sample with: UOPS_DISPATCHED.PORT_5. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", - "MetricExpr": "UOPS_DISPATCHED.PORT_6 / CPU_CLK_UNHALTED.DISTRIBUTED", - "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", + "MetricExpr": "UOPS_DISPATCHED.PORT_6 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", "MetricName": "tma_port_6", + "MetricThreshold": "tma_port_6 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", - "MetricExpr": "UOPS_DISPATCHED.PORT_2_3 / (2 * CPU_CLK_UNHALTED.DISTRIBUTED)", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", - "MetricName": "tma_load_op_utilization", + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", + "MetricExpr": "((cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / tma_info_clks if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / tma_info_clks)", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_ports_utilization", + "MetricThreshold": "tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", - "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * CPU_CLK_UNHALTED.DISTRIBUTED)", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", - "MetricName": "tma_store_op_utilization", + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ / tma_info_clks + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_0", + "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", "ScaleUnit": "100%" }, { - "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * slots", - "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group", - "MetricName": "tma_retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ", + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "EXE_ACTIVITY.1_PORTS_UTIL / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_1", + "MetricThreshold": "tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL. Related metrics: tma_l1_bound", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", - "MetricExpr": "max(0, topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - tma_heavy_operations)", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group", - "MetricName": "tma_light_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.", + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "EXE_ACTIVITY.2_PORTS_UTIL / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_2", + "MetricThreshold": "tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", - "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD + tma_fp_scalar + tma_fp_vector", - "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_fp_arith", - "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_3m", + "MetricThreshold": "tma_ports_utilized_3m > 0.7 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric serves as an approximation of legacy x87 usage", - "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD + 0 * slots", - "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", - "MetricName": "tma_x87_use", - "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues", + "MetricExpr": "(97 * tma_info_average_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + 97 * tma_info_average_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_issueSyncxn;tma_mem_latency_group", + "MetricName": "tma_remote_cache", + "MetricThreshold": "tma_remote_cache > 0.05 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)", - "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group", - "MetricName": "tma_fp_scalar", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory", + "MetricExpr": "108 * tma_info_average_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", + "MetricName": "tma_remote_dram", + "MetricThreshold": "tma_remote_dram > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", - "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)", - "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group", - "MetricName": "tma_fp_vector", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", - "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)", - "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", - "MetricName": "tma_fp_vector_128b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.", + "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations", + "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL5;tma_L5_group;tma_issueSO;tma_ports_utilized_0_group", + "MetricName": "tma_serializing_operation", + "MetricThreshold": "tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD. Related metrics: tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", - "MetricExpr": "min((FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)", - "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", - "MetricName": "tma_fp_vector_256b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions", + "MetricExpr": "37 * MISC_RETIRED.PAUSE_INST / tma_info_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group", + "MetricName": "tma_slow_pause", + "MetricThreshold": "tma_slow_pause > 0.05 & (tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: MISC_RETIRED.PAUSE_INST", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors", - "MetricExpr": "min((FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)", - "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", - "MetricName": "tma_fp_vector_512b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.", + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", + "MetricExpr": "tma_info_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_split_loads", + "MetricThreshold": "tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", - "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_memory_operations", + "BriefDescription": "This metric represents rate of split store accesses", + "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / tma_info_core_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group", + "MetricName": "tma_split_stores", + "MetricThreshold": "tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions.", - "MetricExpr": "tma_light_operations * BR_INST_RETIRED.ALL_BRANCHES / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_branch_instructions", + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", + "MetricExpr": "L1D_PEND_MISS.L2_STALL / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group", + "MetricName": "tma_sq_full", + "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_info_memory_bandwidth, tma_mem_bandwidth", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions", - "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_nop_instructions", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", + "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_store_bound", + "MetricThreshold": "tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", - "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_branch_instructions + tma_nop_instructions))", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_other_light_ops", + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", + "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_store_fwd_blk", + "MetricThreshold": "tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences", - "MetricExpr": "tma_microcode_sequencer + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * (UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=0x1@) / IDQ.MITE_UOPS", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group", - "MetricName": "tma_heavy_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.", + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", + "MetricExpr": "(L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_clks", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group", + "MetricName": "tma_store_latency", + "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops", - "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer", - "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group", - "MetricName": "tma_few_uops_instructions", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_store_op_utilization", + "MetricThreshold": "tma_store_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations. Sample with: UOPS_DISPATCHED.PORT_7_8", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", - "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots / UOPS_ISSUED.ANY * IDQ.MS_UOPS / slots", - "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group", - "MetricName": "tma_microcode_sequencer", - "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.", + "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", + "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", + "MetricName": "tma_store_stlb_hit", + "MetricThreshold": "tma_store_stlb_hit > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", - "MetricExpr": "min(100 * ASSISTS.ANY / slots, 1)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", - "MetricName": "tma_assists", - "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.", + "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", + "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / tma_info_core_clks", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", + "MetricName": "tma_store_stlb_miss", + "MetricThreshold": "tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", - "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", - "MetricName": "tma_cisc", - "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", + "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores", + "MetricExpr": "9 * OCR.STREAMING_WR.ANY_RESPONSE / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueSmSt;tma_store_bound_group", + "MetricName": "tma_streaming_stores", + "MetricThreshold": "tma_streaming_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck. Sample with: OCR.STREAMING_WR.ANY_RESPONSE. Related metrics: tma_fb_full", "ScaleUnit": "100%" }, { - "BriefDescription": "C1 residency percent per core", - "MetricExpr": "cstate_core@c1\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C1_Core_Residency", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", + "MetricExpr": "10 * BACLEARS.ANY / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", + "MetricName": "tma_unknown_branches", + "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit). Sample with: BACLEARS.ANY", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per core", - "MetricExpr": "cstate_core@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Core_Residency", + "BriefDescription": "This metric serves as an approximation of legacy x87 usage", + "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD", + "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_x87_use", + "MetricThreshold": "tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", "ScaleUnit": "100%" }, { - "BriefDescription": "C2 residency percent per package", - "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C2_Pkg_Residency", + "BriefDescription": "Percentage of cycles in aborted transactions.", + "MetricExpr": "max(cpu@cycles\\-t@ - cpu@cycles\\-ct@, 0) / cycles", + "MetricGroup": "transaction", + "MetricName": "tsx_aborted_cycles", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per package", - "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Pkg_Residency", + "BriefDescription": "Number of cycles within a transaction divided by the number of elisions.", + "MetricExpr": "cpu@cycles\\-t@ / cpu@el\\-start@", + "MetricGroup": "transaction", + "MetricName": "tsx_cycles_per_elision", + "ScaleUnit": "1cycles / elision" + }, + { + "BriefDescription": "Number of cycles within a transaction divided by the number of transactions.", + "MetricExpr": "cpu@cycles\\-t@ / cpu@tx\\-start@", + "MetricGroup": "transaction", + "MetricName": "tsx_cycles_per_transaction", + "ScaleUnit": "1cycles / transaction" + }, + { + "BriefDescription": "Percentage of cycles within a transaction region.", + "MetricExpr": "cpu@cycles\\-t@ / cycles", + "MetricGroup": "transaction", + "MetricName": "tsx_transactional_cycles", "ScaleUnit": "100%" } ] diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json index 0d495ae53f3d..66bb4538c6f2 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json @@ -538,7 +538,7 @@ "EventCode": "0x02", "EventName": "UNC_M_PRE_COUNT.PGT", "PerPkg": "1", - "PublicDescription": "DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel. : Prechages from Page Table", + "PublicDescription": "DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel. : Precharges from Page Table", "UMask": "0x10", "Unit": "iMC" }, diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json index 8c09d1358849..b1d29877c141 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json @@ -1296,7 +1296,7 @@ "Unit": "CHA" }, { - "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Deallocate HtiME$ on Reads without RspFwdI*", + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Deallocate HitME$ on Reads without RspFwdI*", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE", "PerPkg": "1", @@ -14927,7 +14927,7 @@ "EventCode": "0x0C", "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "Outbound Request Queue Occupancy : Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.", + "PublicDescription": "Outbound Request Queue Occupancy : Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.", "Unit": "IRP" }, { diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index b258702e0666..77af9d0bf6d4 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -13,7 +13,7 @@ GenuineIntel-6-A[DE],v1.00,graniterapids,core GenuineIntel-6-(3C|45|46),v32,haswell,core GenuineIntel-6-3F,v26,haswellx,core GenuineIntel-6-(7D|7E|A7),v1.17,icelake,core -GenuineIntel-6-6[AC],v1.17,icelakex,core +GenuineIntel-6-6[AC],v1.18,icelakex,core GenuineIntel-6-3A,v23,ivybridge,core GenuineIntel-6-3E,v22,ivytown,core GenuineIntel-6-2D,v21,jaketown,core -- cgit v1.2.3-58-ga151 From 115ae94c517c01d843ddef80700d22a7da079596 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:18 -0800 Subject: perf vendor events intel: Refresh ivybridge metrics Update the ivybridge metrics to TMA version 4.5. Generation was done using https://github.com/intel/perfmon. Notable changes are TMA info metrics are renamed from their node name to be lower case and prefixed by tma_info_, MetricThreshold expressions are added, and the smi_cost metric group is added replicating existing hard coded metrics in stat-shadow. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-22-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/ivybridge/ivb-metrics.json | 1270 +++++++++++--------- 1 file changed, 712 insertions(+), 558 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json b/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json index 88980c1a3a64..5247f69c13b6 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json @@ -1,842 +1,996 @@ [ { - "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", - "MetricGroup": "PGO;TopdownL1;tma_L1_group", - "MetricName": "tma_frontend_bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", - "MetricExpr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / SLOTS", - "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_latency", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", + "BriefDescription": "C2 residency percent per package", + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C2_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", - "MetricExpr": "ICACHE.IFETCH_STALL / CLKS - tma_itlb_misses", - "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_icache_misses", + "BriefDescription": "C3 residency percent per core", + "MetricExpr": "cstate_core@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", - "MetricExpr": "(12 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / CLKS", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_itlb_misses", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED", + "BriefDescription": "C3 residency percent per package", + "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", - "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / CLKS", - "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_branch_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_dsb_switches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", - "MetricExpr": "ILD_STALL.LCP / CLKS", - "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_lcp", - "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", + "BriefDescription": "C7 residency percent per core", + "MetricExpr": "cstate_core@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", - "MetricExpr": "3 * IDQ.MS_SWITCHES / CLKS", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_ms_switches", - "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES", + "BriefDescription": "C7 residency percent per package", + "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", - "MetricExpr": "tma_frontend_bound - tma_fetch_latency", - "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_bandwidth", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", - "ScaleUnit": "100%" + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "tma_info_socket_clks / #num_dies / duration_time / 1e9", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", - "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2", - "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_group", - "MetricName": "tma_mite", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", + "BriefDescription": "Percentage of cycles spent in System Management Interrupts.", + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", + "MetricGroup": "smi", + "MetricName": "smi_cycles", + "MetricThreshold": "smi_cycles > 0.1", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", - "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2", - "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group", - "MetricName": "tma_dsb", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", - "ScaleUnit": "100%" + "BriefDescription": "Number of SMI interrupts.", + "MetricExpr": "msr@smi@", + "MetricGroup": "smi", + "MetricName": "smi_num", + "ScaleUnit": "1SMI#" }, { - "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", - "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_bad_speculation", - "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", + "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_4k_aliasing", + "MetricThreshold": "tma_4k_aliasing > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_branch_mispredicts", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5) / (3 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_alu_op_utilization", + "MetricThreshold": "tma_alu_op_utilization > 0.6", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", - "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_machine_clears", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT", + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", + "MetricExpr": "100 * OTHER_ASSISTS.ANY_WB_ASSIST / tma_info_slots", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_assists", + "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY", "ScaleUnit": "100%" }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)", - "MetricGroup": "TopdownL1;tma_L1_group", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", + "MetricThreshold": "tma_backend_bound > 0.2", "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", - "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) * tma_backend_bound", - "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_memory_bound", - "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", - "MetricExpr": "max((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) - CYCLE_ACTIVITY.STALLS_L1D_PENDING) / CLKS, 0)", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l1_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT_PS;MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", - "MetricExpr": "(7 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / CLKS", - "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_dtlb_load", - "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", - "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_store_fwd_blk", - "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", - "MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS", - "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_lock_latency", - "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", - "MetricExpr": "13 * LD_BLOCKS.NO_SR / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_split_loads", - "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_UOPS_RETIRED.SPLIT_LOADS_PS", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", - "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_4k_aliasing", - "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", + "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_bad_speculation", + "MetricThreshold": "tma_bad_speculation > 0.15", + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", - "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / CLKS", - "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_fb_full", - "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).", + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", + "MetricName": "tma_branch_mispredicts", + "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING) / CLKS", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l2_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", + "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_branch_resteers", + "MetricThreshold": "tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", - "MetricExpr": "MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l3_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS", + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_cisc", + "MetricThreshold": "tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", - "MetricExpr": "(60 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) + 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS)))) / CLKS", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(60 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) + 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS)))) / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", "MetricName": "tma_contested_accesses", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS", + "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", - "MetricExpr": "43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) / CLKS", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_data_sharing", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS", + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_backend_bound - tma_memory_bound", + "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", - "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.LLC_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) / CLKS", - "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_l3_hit_latency", - "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) / tma_info_clks", + "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_data_sharing", + "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", - "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_sq_full", - "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.", + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", + "MetricExpr": "ARITH.FPU_DIV_ACTIVE / tma_info_core_clks", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_divider", + "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", - "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", + "MetricConstraint": "NO_GROUP_EVENTS_SMT", + "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_dram_bound", + "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=6@) / CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group", - "MetricName": "tma_mem_bandwidth", - "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", + "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / tma_info_core_clks / 2", + "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_dsb", + "MetricThreshold": "tma_dsb > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group", - "MetricName": "tma_mem_latency", - "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_clks", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_dsb_switches", + "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Related metrics: tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", - "MetricExpr": "RESOURCE_STALLS.SB / CLKS", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_store_bound", - "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES_PS", + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", + "MetricExpr": "(7 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group", + "MetricName": "tma_dtlb_load", + "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", - "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group", - "MetricName": "tma_store_latency", - "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", + "MetricExpr": "(7 * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION) / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group", + "MetricName": "tma_dtlb_store", + "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", - "MetricExpr": "60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE / CLKS", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group", + "MetricExpr": "60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group", "MetricName": "tma_false_sharing", - "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents rate of split store accesses", - "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / CORE_CLKS", - "MetricGroup": "TopdownL4;tma_store_bound_group", - "MetricName": "tma_split_stores", - "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_UOPS_RETIRED.SPLIT_STORES_PS", + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_info_load_miss_real_latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / tma_info_clks", + "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricName": "tma_fb_full", + "MetricThreshold": "tma_fb_full > 0.3", + "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", - "MetricExpr": "(7 * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION) / CLKS", - "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group", - "MetricName": "tma_dtlb_store", - "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS", + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", + "MetricExpr": "tma_frontend_bound - tma_fetch_latency", + "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", + "MetricName": "tma_fetch_bandwidth", + "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", - "MetricExpr": "tma_backend_bound - tma_memory_bound", - "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_core_bound", - "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", + "MetricExpr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / tma_info_slots", + "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_latency", + "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", - "MetricExpr": "ARITH.FPU_DIV_ACTIVE / CORE_CLKS", - "MetricGroup": "TopdownL3;tma_core_bound_group", - "MetricName": "tma_divider", - "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS", + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", + "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", + "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_fp_arith", + "MetricThreshold": "tma_fp_arith > 0.2 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", - "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / CLKS", - "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group", - "MetricName": "tma_ports_utilization", - "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", + "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) / UOPS_EXECUTED.THREAD", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_scalar", + "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) / CORE_CLKS)", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_0", - "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", + "MetricExpr": "(FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) / UOPS_EXECUTED.THREAD", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_vector", + "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS)", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_1", - "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_slots", + "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.15", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS)", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_2", - "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences", + "MetricExpr": "tma_microcode_sequencer", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_heavy_operations", + "MetricThreshold": "tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", - "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_3m", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", + "MetricExpr": "ICACHE.IFETCH_STALL / tma_info_clks - tma_itlb_misses", + "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_icache_misses", + "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5) / (3 * CORE_CLKS)", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_alu_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "tma_info_turbo_utilization * TSC / 1e9 / duration_time", + "MetricGroup": "Power;Summary", + "MetricName": "tma_info_average_frequency" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) Sample with: UOPS_DISPATCHED_PORT.PORT_0", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS", - "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_0", - "ScaleUnit": "100%" + "BriefDescription": "Branch instructions per taken branch.", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_bptkbranch" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_1", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_1", - "ScaleUnit": "100%" + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline", + "MetricName": "tma_info_clks" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) Sample with: UOPS_DISPATCHED.PORT_5", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_5", - "ScaleUnit": "100%" + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else tma_info_clks))", + "MetricGroup": "SMT", + "MetricName": "tma_info_core_clks" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations Sample with: UOPS_DISPATCHED.PORT_2_3", - "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_load_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_core_clks", + "MetricGroup": "Ret;SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_coreipc" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_2", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_load_op_utilization_group", - "MetricName": "tma_port_2", - "ScaleUnit": "100%" + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / tma_info_ipc", + "MetricGroup": "Mem;Pipeline", + "MetricName": "tma_info_cpi" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_3", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_load_op_utilization_group", - "MetricName": "tma_port_3", - "ScaleUnit": "100%" + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "HPC;Summary", + "MetricName": "tma_info_cpu_utilization" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", - "MetricExpr": "tma_port_4", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_store_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_data_l2_mlp" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data) Sample with: UOPS_DISPATCHED_PORT.PORT_4", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_store_op_utilization_group", - "MetricName": "tma_port_4", - "ScaleUnit": "100%" + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;tma_issueBW", + "MetricName": "tma_info_dram_bw_use", + "PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_mem_bandwidth, tma_sq_full" }, { - "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", - "MetricExpr": "tma_retiring - tma_heavy_operations", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_light_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", + "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", + "MetricName": "tma_info_dsb_coverage", + "MetricThreshold": "tma_info_dsb_coverage < 0.7 & tma_info_ipc / 4 > 0.35", + "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_iptb, tma_lcp" }, { - "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", - "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", - "MetricGroup": "HPC;TopdownL3;tma_light_operations_group", - "MetricName": "tma_fp_arith", - "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", - "ScaleUnit": "100%" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-thread", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "tma_info_execute" }, { - "BriefDescription": "This metric serves as an approximation of legacy x87 usage", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS * FP_COMP_OPS_EXE.X87 / UOPS_EXECUTED.THREAD", - "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_x87_use", - "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", - "ScaleUnit": "100%" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "tma_info_execute_per_issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) / UOPS_EXECUTED.THREAD", - "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_fp_scalar", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / tma_info_core_clks", + "MetricGroup": "Flops;Ret", + "MetricName": "tma_info_flopc" }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", - "MetricExpr": "(FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) / UOPS_EXECUTED.THREAD", - "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_fp_vector", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Giga Floating Point Operations Per Second", + "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1e9 / duration_time", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_gflops", + "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences", - "MetricExpr": "tma_microcode_sequencer", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_heavy_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.", - "ScaleUnit": "100%" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", + "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", + "MetricName": "tma_info_ilp" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS", - "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group", - "MetricName": "tma_microcode_sequencer", - "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS", - "ScaleUnit": "100%" + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;tma_L1_group", + "MetricName": "tma_info_instructions", + "PublicDescription": "Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST" }, { - "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", - "MetricExpr": "100 * OTHER_ASSISTS.ANY_WB_ASSIST / SLOTS", - "MetricGroup": "TopdownL4;tma_microcode_sequencer_group", - "MetricName": "tma_assists", - "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricExpr": "1 / (tma_fp_scalar + tma_fp_vector)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_iparith", + "MetricThreshold": "tma_info_iparith < 10", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", - "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", - "MetricGroup": "TopdownL4;tma_microcode_sequencer_group", - "MetricName": "tma_cisc", - "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "tma_info_ipbranch", + "MetricThreshold": "tma_info_ipbranch < 8" }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", - "MetricExpr": "INST_RETIRED.ANY / CLKS", + "MetricExpr": "INST_RETIRED.ANY / tma_info_clks", "MetricGroup": "Ret;Summary", - "MetricName": "IPC" + "MetricName": "tma_info_ipc" }, { - "BriefDescription": "Uops Per Instruction", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Ret;Retire", - "MetricName": "UPI" + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_ipcall", + "MetricThreshold": "tma_info_ipcall < 200" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW", - "MetricName": "UpTB" + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "tma_info_ipfarbranch", + "MetricThreshold": "tma_info_ipfarbranch < 1e6" }, { - "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / IPC", - "MetricGroup": "Mem;Pipeline", - "MetricName": "CPI" + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipload", + "MetricThreshold": "tma_info_ipload < 3" }, { - "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Pipeline", - "MetricName": "CLKS" + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "tma_info_instructions / (UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * cpu@BR_MISP_EXEC.ALL_BRANCHES\\,umask\\=0xE4@)", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_indirect", + "MetricThreshold": "tma_info_ipmisp_indirect < 1e3" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", - "MetricExpr": "4 * CORE_CLKS", - "MetricGroup": "tma_L1_group", - "MetricName": "SLOTS" + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "tma_info_ipmispredict", + "MetricThreshold": "tma_info_ipmispredict < 200" }, { - "BriefDescription": "The ratio of Executed- by Issued-Uops", - "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", - "MetricGroup": "Cor;Pipeline", - "MetricName": "Execute_per_Issue", - "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipstore", + "MetricThreshold": "tma_info_ipstore < 8" }, { - "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS", - "MetricGroup": "Ret;SMT;tma_L1_group", - "MetricName": "CoreIPC" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", + "MetricName": "tma_info_iptb", + "MetricThreshold": "tma_info_iptb < 9", + "PublicDescription": "Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_lcp" }, { - "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / CORE_CLKS", - "MetricGroup": "Flops;Ret", - "MetricName": "FLOPc" + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "tma_info_instructions / BACLEARS.ANY", + "MetricGroup": "Fed", + "MetricName": "tma_info_ipunknown_branch" }, { - "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", - "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", - "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", - "MetricName": "ILP" + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_cpi" }, { - "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", - "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))", - "MetricGroup": "SMT", - "MetricName": "CORE_CLKS" + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_utilization", + "MetricThreshold": "tma_info_kernel_utilization > 0.05" }, { - "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricGroup": "InsType", - "MetricName": "IpLoad" + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw" }, { - "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", - "MetricGroup": "InsType", - "MetricName": "IpStore" + "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "tma_info_l1d_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw_1t" }, { - "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Fed;InsType", - "MetricName": "IpBranch" + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l1mpki" }, { - "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "IpCall" + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", - "MetricName": "IpTB" + "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "tma_info_l2_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw_1t" }, { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "BpTkBranch" + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Backend;CacheMisses;Mem", + "MetricName": "tma_info_l2mpki" }, { - "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", - "MetricExpr": "1 / (tma_fp_scalar + tma_fp_vector)", - "MetricGroup": "Flops;InsType", - "MetricName": "IpArith", - "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." + "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "0", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_l3_cache_access_bw_1t" }, { - "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary;tma_L1_group", - "MetricName": "Instructions" + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw" }, { - "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@", - "MetricGroup": "Pipeline;Ret", - "MetricName": "Retire" + "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_l3_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw_1t" }, { - "BriefDescription": "", - "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", - "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", - "MetricName": "Execute" + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l3mpki" }, { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "DSB;Fed;FetchBW", - "MetricName": "DSB_Coverage" + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore", + "MetricName": "tma_info_load_l2_miss_latency" }, { - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_load_l2_mlp" }, { "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)", "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency" + "MetricName": "tma_info_load_miss_real_latency" + }, + { + "BriefDescription": "Average number of parallel requests to external memory", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", + "MetricGroup": "Mem;SoC", + "MetricName": "tma_info_mem_parallel_requests", + "PublicDescription": "Average number of parallel requests to external memory. Accounts for all requests" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", + "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL", + "MetricGroup": "Mem;SoC", + "MetricName": "tma_info_mem_request_latency" + }, + { + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", "MetricGroup": "Mem;MemoryBW;MemoryBound", - "MetricName": "MLP" + "MetricName": "tma_info_mlp", + "PublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)" }, { - "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI" + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION) / tma_info_core_clks", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_page_walks_utilization", + "MetricThreshold": "tma_info_page_walks_utilization > 0.5" }, { - "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Backend;CacheMisses;Mem", - "MetricName": "L2MPKI" + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "tma_info_retire" }, { - "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L3MPKI" + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * tma_info_core_clks", + "MetricGroup": "TmaL1;tma_L1_group", + "MetricName": "tma_info_slots" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION) / CORE_CLKS", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "Page_Walks_Utilization" + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", + "MetricGroup": "SMT", + "MetricName": "tma_info_smt_2t_utilization" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "UNC_CLOCK.SOCKET", + "MetricGroup": "SoC", + "MetricName": "tma_info_socket_clks" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "tma_info_clks / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power", + "MetricName": "tma_info_turbo_utilization" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire", + "MetricName": "tma_info_uoppi", + "MetricThreshold": "tma_info_uoppi > 1.05" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "L1D_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW_1T" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "tma_info_uptb", + "MetricThreshold": "tma_info_uptb < 6" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "L2_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW_1T" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", + "MetricExpr": "(12 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW_1T" + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", + "MetricExpr": "max((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) - CYCLE_ACTIVITY.STALLS_L1D_PENDING) / tma_info_clks, 0)", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group", + "MetricName": "tma_l1_bound", + "MetricThreshold": "tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT_PS;MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "0", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW_1T" + "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING) / tma_info_clks", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l2_bound", + "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average CPU Utilization", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", - "MetricGroup": "HPC;Summary", - "MetricName": "CPU_Utilization" + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", + "MetricConstraint": "NO_GROUP_EVENTS_SMT", + "MetricExpr": "MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_clks", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l3_bound", + "MetricThreshold": "tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", - "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time", - "MetricGroup": "Power;Summary", - "MetricName": "Average_Frequency" + "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.LLC_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS))) / tma_info_clks", + "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group", + "MetricName": "tma_l3_hit_latency", + "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS. Related metrics: tma_mem_latency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1e9 / duration_time", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs", - "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", + "MetricExpr": "ILD_STALL.LCP / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_lcp", + "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_iptb", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average Frequency Utilization relative nominal frequency", - "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC", - "MetricGroup": "Power", - "MetricName": "Turbo_Utilization" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", + "MetricExpr": "tma_retiring - tma_heavy_operations", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_light_operations", + "MetricThreshold": "tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", - "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", - "MetricGroup": "SMT", - "MetricName": "SMT_2T_Utilization" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_load_op_utilization", + "MetricThreshold": "tma_load_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "OS", - "MetricName": "Kernel_Utilization" + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / tma_info_clks", + "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group", + "MetricName": "tma_lock_latency", + "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", - "MetricGroup": "OS", - "MetricName": "Kernel_CPI" + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", + "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", - "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3", - "MetricGroup": "HPC;Mem;MemoryBW;SoC", - "MetricName": "DRAM_BW_Use" + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=6@) / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW", + "MetricName": "tma_mem_bandwidth", + "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_sq_full", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)", - "MetricExpr": "MEM_Parallel_Requests", - "MetricGroup": "Mem;SoC", - "MetricName": "MEM_Request_Latency" + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_clks - tma_mem_bandwidth", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat", + "MetricName": "tma_mem_latency", + "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_l3_hit_latency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests", - "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL", - "MetricGroup": "Mem;SoC", - "MetricName": "MEM_Parallel_Requests" + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound", + "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_memory_bound", + "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Socket actual clocks when any core is active on that socket", - "MetricExpr": "UNC_CLOCK.SOCKET", - "MetricGroup": "SoC", - "MetricName": "Socket_CLKS" + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_slots", + "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS", + "MetricName": "tma_microcode_sequencer", + "MetricThreshold": "tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", - "MetricGroup": "Branches;OS", - "MetricName": "IpFarBranch" + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", + "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / tma_info_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_mite", + "MetricThreshold": "tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Uncore frequency per die [GHZ]", - "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9", - "MetricGroup": "SoC", - "MetricName": "UNCORE_FREQ" + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", + "MetricExpr": "3 * IDQ.MS_SWITCHES / tma_info_clks", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", + "MetricName": "tma_ms_switches", + "MetricThreshold": "tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation", + "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per core", - "MetricExpr": "cstate_core@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Core_Residency", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / tma_info_core_clks", + "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_0", + "MetricThreshold": "tma_port_0 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED_PORT.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_512b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per core", - "MetricExpr": "cstate_core@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Core_Residency", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_1", + "MetricThreshold": "tma_port_1 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_512b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per core", - "MetricExpr": "cstate_core@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Core_Residency", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", + "MetricName": "tma_port_2", + "MetricThreshold": "tma_port_2 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_2", "ScaleUnit": "100%" }, { - "BriefDescription": "C2 residency percent per package", - "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C2_Pkg_Residency", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", + "MetricName": "tma_port_3", + "MetricThreshold": "tma_port_3 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_3", "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per package", - "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Pkg_Residency", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)", + "MetricExpr": "tma_store_op_utilization", + "MetricGroup": "TopdownL6;tma_L6_group;tma_issueSpSt;tma_store_op_utilization_group", + "MetricName": "tma_port_4", + "MetricThreshold": "tma_port_4 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Sample with: UOPS_DISPATCHED_PORT.PORT_4. Related metrics: tma_split_stores", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per package", - "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Pkg_Residency", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_5", + "MetricThreshold": "tma_port_5 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Sample with: UOPS_DISPATCHED.PORT_5. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per package", - "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Pkg_Residency", + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_ports_utilization", + "MetricThreshold": "tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0)) / tma_info_core_clks)", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_0", + "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / tma_info_core_clks)", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_1", + "MetricThreshold": "tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Related metrics: tma_l1_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_clks)", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_2", + "MetricThreshold": "tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", + "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_3m", + "MetricThreshold": "tma_ports_utilized_3m > 0.7 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "13 * LD_BLOCKS.NO_SR / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_split_loads", + "MetricThreshold": "tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_UOPS_RETIRED.SPLIT_LOADS_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents rate of split store accesses", + "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / tma_info_core_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group", + "MetricName": "tma_split_stores", + "MetricThreshold": "tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_UOPS_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", + "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group", + "MetricName": "tma_sq_full", + "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_mem_bandwidth", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", + "MetricExpr": "RESOURCE_STALLS.SB / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_store_bound", + "MetricThreshold": "tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", + "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_store_fwd_blk", + "MetricThreshold": "tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_clks", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group", + "MetricName": "tma_store_latency", + "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / tma_info_core_clks", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_store_op_utilization", + "MetricThreshold": "tma_store_op_utilization > 0.6", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric serves as an approximation of legacy x87 usage", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS * FP_COMP_OPS_EXE.X87 / UOPS_EXECUTED.THREAD", + "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_x87_use", + "MetricThreshold": "tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", "ScaleUnit": "100%" } ] -- cgit v1.2.3-58-ga151 From 56c178be7775dda3448171efef6326861ba142d8 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:19 -0800 Subject: perf vendor events intel: Refresh ivytown metrics Update the ivytown metrics to TMA version 4.5. Generation was done using https://github.com/intel/perfmon. Notable changes are TMA info metrics are renamed from their node name to be lower case and prefixed by tma_info_, MetricThreshold expressions are added, and the smi_cost metric group is added replicating existing hard coded metrics in stat-shadow. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-23-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/ivytown/ivt-metrics.json | 1311 +++++++++++--------- 1 file changed, 736 insertions(+), 575 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json b/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json index 80444bc4e66e..89469b10fa30 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json @@ -1,866 +1,1027 @@ [ { - "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", - "MetricGroup": "PGO;TopdownL1;tma_L1_group", - "MetricName": "tma_frontend_bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", - "MetricExpr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / SLOTS", - "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_latency", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", + "BriefDescription": "C2 residency percent per package", + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C2_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", - "MetricExpr": "ICACHE.IFETCH_STALL / CLKS - tma_itlb_misses", - "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_icache_misses", + "BriefDescription": "C3 residency percent per core", + "MetricExpr": "cstate_core@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", - "MetricExpr": "(12 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / CLKS", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_itlb_misses", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED", + "BriefDescription": "C3 residency percent per package", + "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", - "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / CLKS", - "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_branch_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_dsb_switches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", - "MetricExpr": "ILD_STALL.LCP / CLKS", - "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_lcp", - "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", + "BriefDescription": "C7 residency percent per core", + "MetricExpr": "cstate_core@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", - "MetricExpr": "3 * IDQ.MS_SWITCHES / CLKS", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_ms_switches", - "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES", + "BriefDescription": "C7 residency percent per package", + "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", - "MetricExpr": "tma_frontend_bound - tma_fetch_latency", - "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_bandwidth", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", - "ScaleUnit": "100%" + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "tma_info_socket_clks / #num_dies / duration_time / 1e9", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", - "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2", - "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_group", - "MetricName": "tma_mite", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", + "BriefDescription": "Percentage of cycles spent in System Management Interrupts.", + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", + "MetricGroup": "smi", + "MetricName": "smi_cycles", + "MetricThreshold": "smi_cycles > 0.1", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", - "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2", - "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group", - "MetricName": "tma_dsb", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", - "ScaleUnit": "100%" + "BriefDescription": "Number of SMI interrupts.", + "MetricExpr": "msr@smi@", + "MetricGroup": "smi", + "MetricName": "smi_num", + "ScaleUnit": "1SMI#" }, { - "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", - "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_bad_speculation", - "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", + "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_4k_aliasing", + "MetricThreshold": "tma_4k_aliasing > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_branch_mispredicts", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5) / (3 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_alu_op_utilization", + "MetricThreshold": "tma_alu_op_utilization > 0.6", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", - "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_machine_clears", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT", + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", + "MetricExpr": "100 * OTHER_ASSISTS.ANY_WB_ASSIST / tma_info_slots", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_assists", + "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY", "ScaleUnit": "100%" }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)", - "MetricGroup": "TopdownL1;tma_L1_group", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", + "MetricThreshold": "tma_backend_bound > 0.2", "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", - "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) * tma_backend_bound", - "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_memory_bound", - "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", + "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_bad_speculation", + "MetricThreshold": "tma_bad_speculation > 0.15", + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", - "MetricExpr": "max((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) - CYCLE_ACTIVITY.STALLS_L1D_PENDING) / CLKS, 0)", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l1_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT_PS;MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS", + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", + "MetricName": "tma_branch_mispredicts", + "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", - "MetricExpr": "(7 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / CLKS", - "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_dtlb_load", - "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", + "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_branch_resteers", + "MetricThreshold": "tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", - "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_store_fwd_blk", - "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_cisc", + "MetricThreshold": "tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", - "MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / CLKS", - "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_lock_latency", - "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(60 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD)))) / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_contested_accesses", + "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", - "MetricExpr": "13 * LD_BLOCKS.NO_SR / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_split_loads", - "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_UOPS_RETIRED.SPLIT_LOADS_PS", + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_backend_bound - tma_memory_bound", + "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", - "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_4k_aliasing", - "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / tma_info_clks", + "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_data_sharing", + "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", - "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / CLKS", - "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_fb_full", - "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).", + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", + "MetricExpr": "ARITH.FPU_DIV_ACTIVE / tma_info_core_clks", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_divider", + "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING) / CLKS", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l2_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS", + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", + "MetricConstraint": "NO_GROUP_EVENTS_SMT", + "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_dram_bound", + "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", - "MetricExpr": "MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l3_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS", + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", + "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / tma_info_core_clks / 2", + "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_dsb", + "MetricThreshold": "tma_dsb > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", - "MetricExpr": "(60 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD)))) / CLKS", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_contested_accesses", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_clks", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_dsb_switches", + "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Related metrics: tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", - "MetricExpr": "43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / CLKS", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_data_sharing", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS", + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", + "MetricExpr": "(7 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group", + "MetricName": "tma_dtlb_load", + "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", - "MetricExpr": "41 * (MEM_LOAD_UOPS_RETIRED.LLC_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / CLKS", - "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_l3_hit_latency", - "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS", + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", + "MetricExpr": "(7 * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION) / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group", + "MetricName": "tma_dtlb_store", + "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", - "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_sq_full", - "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.", + "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", + "MetricExpr": "(200 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE) / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group", + "MetricName": "tma_false_sharing", + "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", - "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_dram_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS", + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_info_load_miss_real_latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / tma_info_clks", + "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricName": "tma_fb_full", + "MetricThreshold": "tma_fb_full > 0.3", + "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=6@) / CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group", - "MetricName": "tma_mem_bandwidth", - "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", + "MetricExpr": "tma_frontend_bound - tma_fetch_latency", + "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", + "MetricName": "tma_fetch_bandwidth", + "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group", - "MetricName": "tma_mem_latency", - "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", + "MetricExpr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / tma_info_slots", + "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_latency", + "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory", - "MetricExpr": "200 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / CLKS", - "MetricGroup": "Server;TopdownL5;tma_mem_latency_group", - "MetricName": "tma_local_dram", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS", + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", + "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", + "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_fp_arith", + "MetricThreshold": "tma_fp_arith > 0.2 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory", - "MetricExpr": "310 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / CLKS", - "MetricGroup": "Server;Snoop;TopdownL5;tma_mem_latency_group", - "MetricName": "tma_remote_dram", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS", + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", + "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) / UOPS_EXECUTED.THREAD", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_scalar", + "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues", - "MetricExpr": "(200 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD)))) / CLKS", - "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_mem_latency_group", - "MetricName": "tma_remote_cache", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS", + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", + "MetricExpr": "(FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) / UOPS_EXECUTED.THREAD", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_vector", + "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", - "MetricExpr": "RESOURCE_STALLS.SB / CLKS", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_store_bound", - "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES_PS", + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_slots", + "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.15", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", - "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group", - "MetricName": "tma_store_latency", - "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences", + "MetricExpr": "tma_microcode_sequencer", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_heavy_operations", + "MetricThreshold": "tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", - "MetricExpr": "(200 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM + 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE) / CLKS", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group", - "MetricName": "tma_false_sharing", - "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", + "MetricExpr": "ICACHE.IFETCH_STALL / tma_info_clks - tma_itlb_misses", + "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_icache_misses", + "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents rate of split store accesses", - "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / CORE_CLKS", - "MetricGroup": "TopdownL4;tma_store_bound_group", - "MetricName": "tma_split_stores", - "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_UOPS_RETIRED.SPLIT_STORES_PS", - "ScaleUnit": "100%" + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "tma_info_turbo_utilization * TSC / 1e9 / duration_time", + "MetricGroup": "Power;Summary", + "MetricName": "tma_info_average_frequency" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", - "MetricExpr": "(7 * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES.WALK_DURATION) / CLKS", - "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group", - "MetricName": "tma_dtlb_store", - "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS", - "ScaleUnit": "100%" + "BriefDescription": "Branch instructions per taken branch.", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_bptkbranch" }, { - "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", - "MetricExpr": "tma_backend_bound - tma_memory_bound", - "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_core_bound", - "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", - "ScaleUnit": "100%" + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline", + "MetricName": "tma_info_clks" }, { - "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", - "MetricExpr": "ARITH.FPU_DIV_ACTIVE / CORE_CLKS", - "MetricGroup": "TopdownL3;tma_core_bound_group", - "MetricName": "tma_divider", - "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS", - "ScaleUnit": "100%" + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else tma_info_clks))", + "MetricGroup": "SMT", + "MetricName": "tma_info_core_clks" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", - "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if IPC > 1.8 else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / CLKS", - "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group", - "MetricName": "tma_ports_utilization", - "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_core_clks", + "MetricGroup": "Ret;SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_coreipc" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) / CORE_CLKS)", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_0", - "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", - "ScaleUnit": "100%" + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / tma_info_ipc", + "MetricGroup": "Mem;Pipeline", + "MetricName": "tma_info_cpi" }, { - "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / CORE_CLKS)", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_1", - "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", - "ScaleUnit": "100%" + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "HPC;Summary", + "MetricName": "tma_info_cpu_utilization" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS)", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_2", - "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", - "ScaleUnit": "100%" + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_data_l2_mlp" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", - "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_3m", - "ScaleUnit": "100%" + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;tma_issueBW", + "MetricName": "tma_info_dram_bw_use", + "PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_mem_bandwidth, tma_sq_full" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5) / (3 * CORE_CLKS)", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_alu_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", + "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", + "MetricName": "tma_info_dsb_coverage", + "MetricThreshold": "tma_info_dsb_coverage < 0.7 & tma_info_ipc / 4 > 0.35", + "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_iptb, tma_lcp" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) Sample with: UOPS_DISPATCHED_PORT.PORT_0", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS", - "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_0", - "ScaleUnit": "100%" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-thread", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "tma_info_execute" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_1", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_1", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) Sample with: UOPS_DISPATCHED.PORT_5", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_5", - "ScaleUnit": "100%" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "tma_info_execute_per_issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations Sample with: UOPS_DISPATCHED.PORT_2_3", - "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_load_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / tma_info_core_clks", + "MetricGroup": "Flops;Ret", + "MetricName": "tma_info_flopc" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_2", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_load_op_utilization_group", - "MetricName": "tma_port_2", - "ScaleUnit": "100%" + "BriefDescription": "Giga Floating Point Operations Per Second", + "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1e9 / duration_time", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_gflops", + "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_3", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_load_op_utilization_group", - "MetricName": "tma_port_3", - "ScaleUnit": "100%" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", + "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", + "MetricName": "tma_info_ilp" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", - "MetricExpr": "tma_port_4", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_store_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;tma_L1_group", + "MetricName": "tma_info_instructions", + "PublicDescription": "Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data) Sample with: UOPS_DISPATCHED_PORT.PORT_4", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_store_op_utilization_group", - "MetricName": "tma_port_4", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricExpr": "1 / (tma_fp_scalar + tma_fp_vector)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_iparith", + "MetricThreshold": "tma_info_iparith < 10", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." }, { - "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "tma_info_ipbranch", + "MetricThreshold": "tma_info_ipbranch < 8" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", - "MetricExpr": "tma_retiring - tma_heavy_operations", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_light_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", - "ScaleUnit": "100%" + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_clks", + "MetricGroup": "Ret;Summary", + "MetricName": "tma_info_ipc" }, { - "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", - "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", - "MetricGroup": "HPC;TopdownL3;tma_light_operations_group", - "MetricName": "tma_fp_arith", - "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_ipcall", + "MetricThreshold": "tma_info_ipcall < 200" }, { - "BriefDescription": "This metric serves as an approximation of legacy x87 usage", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS * FP_COMP_OPS_EXE.X87 / UOPS_EXECUTED.THREAD", - "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_x87_use", - "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "tma_info_ipfarbranch", + "MetricThreshold": "tma_info_ipfarbranch < 1e6" }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) / UOPS_EXECUTED.THREAD", - "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_fp_scalar", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipload", + "MetricThreshold": "tma_info_ipload < 3" }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", - "MetricExpr": "(FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) / UOPS_EXECUTED.THREAD", - "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_fp_vector", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "tma_info_instructions / (UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * cpu@BR_MISP_EXEC.ALL_BRANCHES\\,umask\\=0xE4@)", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_indirect", + "MetricThreshold": "tma_info_ipmisp_indirect < 1e3" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences", - "MetricExpr": "tma_microcode_sequencer", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_heavy_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.", - "ScaleUnit": "100%" + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "tma_info_ipmispredict", + "MetricThreshold": "tma_info_ipmispredict < 200" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS", - "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group", - "MetricName": "tma_microcode_sequencer", - "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipstore", + "MetricThreshold": "tma_info_ipstore < 8" }, { - "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", - "MetricExpr": "100 * OTHER_ASSISTS.ANY_WB_ASSIST / SLOTS", - "MetricGroup": "TopdownL4;tma_microcode_sequencer_group", - "MetricName": "tma_assists", - "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY", - "ScaleUnit": "100%" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", + "MetricName": "tma_info_iptb", + "MetricThreshold": "tma_info_iptb < 9", + "PublicDescription": "Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_lcp" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", - "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", - "MetricGroup": "TopdownL4;tma_microcode_sequencer_group", - "MetricName": "tma_cisc", - "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "tma_info_instructions / BACLEARS.ANY", + "MetricGroup": "Fed", + "MetricName": "tma_info_ipunknown_branch" }, { - "BriefDescription": "Instructions Per Cycle (per Logical Processor)", - "MetricExpr": "INST_RETIRED.ANY / CLKS", - "MetricGroup": "Ret;Summary", - "MetricName": "IPC" + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_cpi" }, { - "BriefDescription": "Uops Per Instruction", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Ret;Retire", - "MetricName": "UPI" + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_utilization", + "MetricThreshold": "tma_info_kernel_utilization > 0.05" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW", - "MetricName": "UpTB" + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw" }, { - "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / IPC", - "MetricGroup": "Mem;Pipeline", - "MetricName": "CPI" + "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "tma_info_l1d_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw_1t" }, { - "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Pipeline", - "MetricName": "CLKS" + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l1mpki" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", - "MetricExpr": "4 * CORE_CLKS", - "MetricGroup": "tma_L1_group", - "MetricName": "SLOTS" + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw" }, { - "BriefDescription": "The ratio of Executed- by Issued-Uops", - "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", - "MetricGroup": "Cor;Pipeline", - "MetricName": "Execute_per_Issue", - "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." + "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "tma_info_l2_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw_1t" }, { - "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS", - "MetricGroup": "Ret;SMT;tma_L1_group", - "MetricName": "CoreIPC" + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Backend;CacheMisses;Mem", + "MetricName": "tma_info_l2mpki" }, { - "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / CORE_CLKS", - "MetricGroup": "Flops;Ret", - "MetricName": "FLOPc" + "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "0", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_l3_cache_access_bw_1t" }, { - "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", - "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", - "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", - "MetricName": "ILP" + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw" }, { - "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", - "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))", - "MetricGroup": "SMT", - "MetricName": "CORE_CLKS" + "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_l3_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw_1t" }, { - "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricGroup": "InsType", - "MetricName": "IpLoad" + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l3mpki" }, { - "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", - "MetricGroup": "InsType", - "MetricName": "IpStore" + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore", + "MetricName": "tma_info_load_l2_miss_latency" }, { - "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Fed;InsType", - "MetricName": "IpBranch" + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_load_l2_mlp" }, { - "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "IpCall" + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "tma_info_load_miss_real_latency" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", - "MetricName": "IpTB" + "BriefDescription": "Average number of parallel data read requests to external memory", + "MetricExpr": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182\\,thresh\\=1@", + "MetricGroup": "Mem;MemoryBW;SoC", + "MetricName": "tma_info_mem_parallel_reads", + "PublicDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches" }, { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "BpTkBranch" + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds)", + "MetricExpr": "1e9 * (UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_INSERTS.MISS_OPCODE@filter_opc\\=0x182@) / (tma_info_socket_clks / duration_time)", + "MetricGroup": "Mem;MemoryLat;SoC", + "MetricName": "tma_info_mem_read_latency", + "PublicDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)" }, { - "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", - "MetricExpr": "1 / (tma_fp_scalar + tma_fp_vector)", - "MetricGroup": "Flops;InsType", - "MetricName": "IpArith", - "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBW;MemoryBound", + "MetricName": "tma_info_mlp", + "PublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)" }, { - "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary;tma_L1_group", - "MetricName": "Instructions" + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION) / tma_info_core_clks", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_page_walks_utilization", + "MetricThreshold": "tma_info_page_walks_utilization > 0.5" }, { "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@", "MetricGroup": "Pipeline;Ret", - "MetricName": "Retire" + "MetricName": "tma_info_retire" }, { - "BriefDescription": "", - "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", - "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", - "MetricName": "Execute" + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * tma_info_core_clks", + "MetricGroup": "TmaL1;tma_L1_group", + "MetricName": "tma_info_slots" }, { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "DSB;Fed;FetchBW", - "MetricName": "DSB_Coverage" + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", + "MetricGroup": "SMT", + "MetricName": "tma_info_smt_2t_utilization" }, { - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "cbox_0@event\\=0x0@", + "MetricGroup": "SoC", + "MetricName": "tma_info_socket_clks" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_UOPS_RETIRED.L1_MISS + MEM_LOAD_UOPS_RETIRED.HIT_LFB)", - "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency" + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "tma_info_clks / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power", + "MetricName": "tma_info_turbo_utilization" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "Mem;MemoryBW;MemoryBound", - "MetricName": "MLP" + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire", + "MetricName": "tma_info_uoppi", + "MetricThreshold": "tma_info_uoppi > 1.05" }, { - "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "tma_info_uptb", + "MetricThreshold": "tma_info_uptb < 6" }, { - "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Backend;CacheMisses;Mem", - "MetricName": "L2MPKI" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", + "MetricExpr": "(12 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED", + "ScaleUnit": "100%" }, { - "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L3MPKI" + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", + "MetricExpr": "max((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) - CYCLE_ACTIVITY.STALLS_L1D_PENDING) / tma_info_clks, 0)", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group", + "MetricName": "tma_l1_bound", + "MetricThreshold": "tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_UOPS_RETIRED.L1_HIT_PS;MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1", + "ScaleUnit": "100%" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION) / CORE_CLKS", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "Page_Walks_Utilization" + "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING) / tma_info_clks", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l2_bound", + "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", + "MetricConstraint": "NO_GROUP_EVENTS_SMT", + "MetricExpr": "MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_clks", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l3_bound", + "MetricThreshold": "tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" + "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "41 * (MEM_LOAD_UOPS_RETIRED.LLC_HIT * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / tma_info_clks", + "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group", + "MetricName": "tma_l3_hit_latency", + "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS. Related metrics: tma_mem_latency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", + "MetricExpr": "ILD_STALL.LCP / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_lcp", + "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_iptb", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "L1D_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW_1T" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", + "MetricExpr": "tma_retiring - tma_heavy_operations", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_light_operations", + "MetricThreshold": "tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "L2_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW_1T" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_load_op_utilization", + "MetricThreshold": "tma_load_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW_1T" + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "200 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / tma_info_clks", + "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group", + "MetricName": "tma_local_dram", + "MetricThreshold": "tma_local_dram > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "0", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW_1T" + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO) / tma_info_clks", + "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group", + "MetricName": "tma_lock_latency", + "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_UOPS_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average CPU Utilization", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", - "MetricGroup": "HPC;Summary", - "MetricName": "CPU_Utilization" + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", + "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", - "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time", - "MetricGroup": "Power;Summary", - "MetricName": "Average_Frequency" + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=6@) / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW", + "MetricName": "tma_mem_bandwidth", + "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_sq_full", + "ScaleUnit": "100%" }, { - "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1e9 / duration_time", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs", - "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_clks - tma_mem_bandwidth", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat", + "MetricName": "tma_mem_latency", + "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_l3_hit_latency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average Frequency Utilization relative nominal frequency", - "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC", - "MetricGroup": "Power", - "MetricName": "Turbo_Utilization" + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound", + "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_memory_bound", + "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", - "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", - "MetricGroup": "SMT", - "MetricName": "SMT_2T_Utilization" + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_slots", + "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS", + "MetricName": "tma_microcode_sequencer", + "MetricThreshold": "tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "OS", - "MetricName": "Kernel_Utilization" + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", + "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / tma_info_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_mite", + "MetricThreshold": "tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", - "MetricGroup": "OS", - "MetricName": "Kernel_CPI" + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", + "MetricExpr": "3 * IDQ.MS_SWITCHES / tma_info_clks", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", + "MetricName": "tma_ms_switches", + "MetricThreshold": "tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", - "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time", - "MetricGroup": "HPC;Mem;MemoryBW;SoC", - "MetricName": "DRAM_BW_Use" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / tma_info_core_clks", + "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_0", + "MetricThreshold": "tma_port_0 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED_PORT.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_512b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches", - "MetricExpr": "1e9 * (UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_INSERTS.MISS_OPCODE@filter_opc\\=0x182@) / (Socket_CLKS / duration_time)", - "MetricGroup": "Mem;MemoryLat;SoC", - "MetricName": "MEM_Read_Latency" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_1", + "MetricThreshold": "tma_port_1 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_512b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", - "MetricExpr": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182\\,thresh\\=1@", - "MetricGroup": "Mem;MemoryBW;SoC", - "MetricName": "MEM_Parallel_Reads" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", + "MetricName": "tma_port_2", + "MetricThreshold": "tma_port_2 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Socket actual clocks when any core is active on that socket", - "MetricExpr": "cbox_0@event\\=0x0@", - "MetricGroup": "SoC", - "MetricName": "Socket_CLKS" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", + "MetricName": "tma_port_3", + "MetricThreshold": "tma_port_3 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_3", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", - "MetricGroup": "Branches;OS", - "MetricName": "IpFarBranch" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)", + "MetricExpr": "tma_store_op_utilization", + "MetricGroup": "TopdownL6;tma_L6_group;tma_issueSpSt;tma_store_op_utilization_group", + "MetricName": "tma_port_4", + "MetricThreshold": "tma_port_4 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Sample with: UOPS_DISPATCHED_PORT.PORT_4. Related metrics: tma_split_stores", + "ScaleUnit": "100%" }, { - "BriefDescription": "Uncore frequency per die [GHZ]", - "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9", - "MetricGroup": "SoC", - "MetricName": "UNCORE_FREQ" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_5", + "MetricThreshold": "tma_port_5 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Sample with: UOPS_DISPATCHED.PORT_5. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per core", - "MetricExpr": "cstate_core@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Core_Residency", + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - (UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC if tma_info_ipc > 1.8 else UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING)) / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_ports_utilization", + "MetricThreshold": "tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per core", - "MetricExpr": "cstate_core@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Core_Residency", + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0)) / tma_info_core_clks)", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_0", + "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per core", - "MetricExpr": "cstate_core@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Core_Residency", + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC - UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC) / tma_info_core_clks)", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_1", + "MetricThreshold": "tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Related metrics: tma_l1_bound", "ScaleUnit": "100%" }, { - "BriefDescription": "C2 residency percent per package", - "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C2_Pkg_Residency", + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "((cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC - UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_clks)", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_2", + "MetricThreshold": "tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6", "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per package", - "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Pkg_Residency", + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", + "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_3m", + "MetricThreshold": "tma_ports_utilized_3m > 0.7 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per package", - "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Pkg_Residency", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(200 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) + 180 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD)))) / tma_info_clks", + "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_issueSyncxn;tma_mem_latency_group", + "MetricName": "tma_remote_cache", + "MetricThreshold": "tma_remote_cache > 0.05 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per package", - "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Pkg_Residency", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "310 * (MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD))) / tma_info_clks", + "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", + "MetricName": "tma_remote_dram", + "MetricThreshold": "tma_remote_dram > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "13 * LD_BLOCKS.NO_SR / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_split_loads", + "MetricThreshold": "tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_UOPS_RETIRED.SPLIT_LOADS_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents rate of split store accesses", + "MetricExpr": "2 * MEM_UOPS_RETIRED.SPLIT_STORES / tma_info_core_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group", + "MetricName": "tma_split_stores", + "MetricThreshold": "tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_UOPS_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", + "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group", + "MetricName": "tma_sq_full", + "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_mem_bandwidth", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", + "MetricExpr": "RESOURCE_STALLS.SB / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_store_bound", + "MetricThreshold": "tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", + "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_store_fwd_blk", + "MetricThreshold": "tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_clks", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group", + "MetricName": "tma_store_latency", + "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / tma_info_core_clks", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_store_op_utilization", + "MetricThreshold": "tma_store_op_utilization > 0.6", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric serves as an approximation of legacy x87 usage", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS * FP_COMP_OPS_EXE.X87 / UOPS_EXECUTED.THREAD", + "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_x87_use", + "MetricThreshold": "tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", "ScaleUnit": "100%" } ] -- cgit v1.2.3-58-ga151 From 5c3f73c124813869dfba07198aa1030da4690a43 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:20 -0800 Subject: perf vendor events intel: Refresh jaketown events Update the jaketown events from 21 to 22. Generation was done using https://github.com/intel/perfmon. Notable changes are improved event descriptions, TMA metrics are updated to version 4.5, TMA info metrics are renamed from their node name to be lower case and prefixed by tma_info_, MetricThreshold expressions are added, and the smi_cost metric group is added replicating existing hard coded metrics in stat-shadow. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-24-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/jaketown/cache.json | 6 +- .../arch/x86/jaketown/floating-point.json | 2 +- .../pmu-events/arch/x86/jaketown/frontend.json | 12 +- .../pmu-events/arch/x86/jaketown/jkt-metrics.json | 602 ++++++++++++--------- .../pmu-events/arch/x86/jaketown/pipeline.json | 2 +- .../pmu-events/arch/x86/jaketown/uncore-cache.json | 22 +- .../arch/x86/jaketown/uncore-interconnect.json | 74 +-- .../arch/x86/jaketown/uncore-memory.json | 4 +- .../pmu-events/arch/x86/jaketown/uncore-other.json | 22 +- .../pmu-events/arch/x86/jaketown/uncore-power.json | 8 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 11 files changed, 409 insertions(+), 347 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/jaketown/cache.json b/tools/perf/pmu-events/arch/x86/jaketown/cache.json index f1271039b6b2..b9769d39940c 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/cache.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/cache.json @@ -37,7 +37,7 @@ "UMask": "0x5" }, { - "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", @@ -45,7 +45,7 @@ "UMask": "0x2" }, { - "BriefDescription": "L1D miss oustandings duration in cycles.", + "BriefDescription": "L1D miss outstanding duration in cycles.", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "SampleAfterValue": "2000003", @@ -500,7 +500,7 @@ "UMask": "0x8" }, { - "BriefDescription": "Cacheable and noncachaeble code read requests.", + "BriefDescription": "Cacheable and non-cacheable code read requests.", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "SampleAfterValue": "100003", diff --git a/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json b/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json index 8c2a246adef9..79e8f403c426 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json @@ -64,7 +64,7 @@ "UMask": "0x20" }, { - "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.", + "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.X87", "SampleAfterValue": "2000003", diff --git a/tools/perf/pmu-events/arch/x86/jaketown/frontend.json b/tools/perf/pmu-events/arch/x86/jaketown/frontend.json index 3f4fc3481112..754ee2749485 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/frontend.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/frontend.json @@ -134,7 +134,7 @@ "UMask": "0x4" }, { - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", @@ -143,7 +143,7 @@ "UMask": "0x30" }, { - "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -151,7 +151,7 @@ "UMask": "0x10" }, { - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy.", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -160,14 +160,14 @@ "UMask": "0x10" }, { - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_UOPS", "SampleAfterValue": "2000003", "UMask": "0x10" }, { - "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", "SampleAfterValue": "2000003", @@ -183,7 +183,7 @@ "UMask": "0x30" }, { - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "SampleAfterValue": "2000003", diff --git a/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json b/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json index cb1420df3768..e8f4e5c01c9f 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json @@ -1,449 +1,511 @@ [ { - "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", - "MetricGroup": "PGO;TopdownL1;tma_L1_group", - "MetricName": "tma_frontend_bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", - "MetricExpr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / SLOTS", - "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_latency", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", + "BriefDescription": "C2 residency percent per package", + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C2_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", - "MetricExpr": "(12 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / CLKS", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_itlb_misses", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED", + "BriefDescription": "C3 residency percent per core", + "MetricExpr": "cstate_core@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", - "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / CLKS", - "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_branch_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "C3 residency percent per package", + "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_dsb_switches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", - "MetricExpr": "ILD_STALL.LCP / CLKS", - "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_lcp", - "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", - "MetricExpr": "3 * IDQ.MS_SWITCHES / CLKS", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_ms_switches", - "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES", + "BriefDescription": "C7 residency percent per core", + "MetricExpr": "cstate_core@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", - "MetricExpr": "tma_frontend_bound - tma_fetch_latency", - "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_bandwidth", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", + "BriefDescription": "C7 residency percent per package", + "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", - "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_bad_speculation", - "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", - "ScaleUnit": "100%" + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "tma_info_socket_clks / #num_dies / duration_time / 1e9", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_branch_mispredicts", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "Percentage of cycles spent in System Management Interrupts.", + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", + "MetricGroup": "smi", + "MetricName": "smi_cycles", + "MetricThreshold": "smi_cycles > 0.1", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", - "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_machine_clears", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT", - "ScaleUnit": "100%" + "BriefDescription": "Number of SMI interrupts.", + "MetricExpr": "msr@smi@", + "MetricGroup": "smi", + "MetricName": "smi_num", + "ScaleUnit": "1SMI#" }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)", - "MetricGroup": "TopdownL1;tma_L1_group", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", + "MetricThreshold": "tma_backend_bound > 0.2", "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", - "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if IPC > 1.8 else (cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) * tma_backend_bound", - "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_memory_bound", - "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", - "MetricExpr": "(7 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / CLKS", - "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_dtlb_load", - "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", - "MetricExpr": "MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l3_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", - "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_dram_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=6@) / CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group", - "MetricName": "tma_mem_bandwidth", - "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", + "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_bad_speculation", + "MetricThreshold": "tma_bad_speculation > 0.15", + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group", - "MetricName": "tma_mem_latency", - "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", + "MetricName": "tma_branch_mispredicts", + "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", - "MetricExpr": "RESOURCE_STALLS.SB / CLKS", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_store_bound", - "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES_PS", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", + "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_branch_resteers", + "MetricThreshold": "tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_backend_bound - tma_memory_bound", - "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_core_bound", + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", - "MetricExpr": "ARITH.FPU_DIV_ACTIVE / CORE_CLKS", - "MetricGroup": "TopdownL3;tma_core_bound_group", + "MetricExpr": "ARITH.FPU_DIV_ACTIVE / tma_info_core_clks", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_divider", + "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", - "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if IPC > 1.8 else (cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING)) / CLKS", - "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group", - "MetricName": "tma_ports_utilization", - "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", + "MetricConstraint": "NO_GROUP_EVENTS_SMT", + "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_dram_bound", + "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_clks", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_dsb_switches", + "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Related metrics: tma_fetch_bandwidth, tma_info_dsb_coverage, tma_lcp", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", - "MetricExpr": "tma_retiring - tma_heavy_operations", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_light_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", + "MetricExpr": "(7 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group", + "MetricName": "tma_dtlb_load", + "MetricThreshold": "tma_dtlb_load > 0.1", + "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", + "MetricExpr": "tma_frontend_bound - tma_fetch_latency", + "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", + "MetricName": "tma_fetch_bandwidth", + "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_lcp", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", + "MetricExpr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / tma_info_slots", + "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_latency", + "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", - "MetricGroup": "HPC;TopdownL3;tma_light_operations_group", + "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", "MetricName": "tma_fp_arith", + "MetricThreshold": "tma_fp_arith > 0.2 & tma_light_operations > 0.6", "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", "ScaleUnit": "100%" }, - { - "BriefDescription": "This metric serves as an approximation of legacy x87 usage", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS * FP_COMP_OPS_EXE.X87 / UOPS_DISPATCHED.THREAD", - "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_x87_use", - "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", - "ScaleUnit": "100%" - }, { "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) / UOPS_DISPATCHED.THREAD", - "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", "MetricName": "tma_fp_scalar", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", + "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_512b, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", "MetricExpr": "(FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) / UOPS_DISPATCHED.THREAD", - "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", "MetricName": "tma_fp_vector", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", + "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_512b, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_slots", + "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.15", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences", "MetricExpr": "tma_microcode_sequencer", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_heavy_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.", + "MetricThreshold": "tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS", - "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group", - "MetricName": "tma_microcode_sequencer", - "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS", - "ScaleUnit": "100%" + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "tma_info_turbo_utilization * TSC / 1e9 / duration_time", + "MetricGroup": "Power;Summary", + "MetricName": "tma_info_average_frequency" }, { - "BriefDescription": "Instructions Per Cycle (per Logical Processor)", - "MetricExpr": "INST_RETIRED.ANY / CLKS", - "MetricGroup": "Ret;Summary", - "MetricName": "IPC" + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline", + "MetricName": "tma_info_clks" }, { - "BriefDescription": "Uops Per Instruction", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Ret;Retire", - "MetricName": "UPI" + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else tma_info_clks))", + "MetricGroup": "SMT", + "MetricName": "tma_info_core_clks" + }, + { + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_core_clks", + "MetricGroup": "Ret;SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_coreipc" }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / IPC", + "MetricExpr": "1 / tma_info_ipc", "MetricGroup": "Mem;Pipeline", - "MetricName": "CPI" + "MetricName": "tma_info_cpi" }, { - "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Pipeline", - "MetricName": "CLKS" + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "HPC;Summary", + "MetricName": "tma_info_cpu_utilization" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", - "MetricExpr": "4 * CORE_CLKS", - "MetricGroup": "tma_L1_group", - "MetricName": "SLOTS" + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;tma_issueBW", + "MetricName": "tma_info_dram_bw_use", + "PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_mem_bandwidth" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", + "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", + "MetricName": "tma_info_dsb_coverage", + "MetricThreshold": "tma_info_dsb_coverage < 0.7 & tma_info_ipc / 4 > 0.35", + "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_lcp" }, { "BriefDescription": "The ratio of Executed- by Issued-Uops", "MetricExpr": "UOPS_DISPATCHED.THREAD / UOPS_ISSUED.ANY", "MetricGroup": "Cor;Pipeline", - "MetricName": "Execute_per_Issue", + "MetricName": "tma_info_execute_per_issue", "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." }, - { - "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS", - "MetricGroup": "Ret;SMT;tma_L1_group", - "MetricName": "CoreIPC" - }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / CORE_CLKS", + "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / tma_info_core_clks", "MetricGroup": "Flops;Ret", - "MetricName": "FLOPc" + "MetricName": "tma_info_flopc" + }, + { + "BriefDescription": "Giga Floating Point Operations Per Second", + "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1e9 / duration_time", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_gflops", + "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." }, { "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", "MetricExpr": "UOPS_DISPATCHED.THREAD / (cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@)", "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", - "MetricName": "ILP" + "MetricName": "tma_info_ilp" }, { - "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", - "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))", - "MetricGroup": "SMT", - "MetricName": "CORE_CLKS" + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;tma_L1_group", + "MetricName": "tma_info_instructions", + "PublicDescription": "Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST" }, { - "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary;tma_L1_group", - "MetricName": "Instructions" + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_clks", + "MetricGroup": "Ret;Summary", + "MetricName": "tma_info_ipc" }, { - "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@", - "MetricGroup": "Pipeline;Ret", - "MetricName": "Retire" + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "tma_info_ipfarbranch", + "MetricThreshold": "tma_info_ipfarbranch < 1e6" }, { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "DSB;Fed;FetchBW", - "MetricName": "DSB_Coverage" + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_cpi" }, { - "BriefDescription": "Average CPU Utilization", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", - "MetricGroup": "HPC;Summary", - "MetricName": "CPU_Utilization" + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_utilization", + "MetricThreshold": "tma_info_kernel_utilization > 0.05" }, { - "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", - "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time", - "MetricGroup": "Power;Summary", - "MetricName": "Average_Frequency" + "BriefDescription": "Average number of parallel data read requests to external memory", + "MetricExpr": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182\\,thresh\\=1@", + "MetricGroup": "Mem;MemoryBW;SoC", + "MetricName": "tma_info_mem_parallel_reads", + "PublicDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches" }, { - "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1e9 / duration_time", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs", - "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds)", + "MetricExpr": "1e9 * (UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_INSERTS.MISS_OPCODE@filter_opc\\=0x182@) / (tma_info_socket_clks / duration_time)", + "MetricGroup": "Mem;MemoryLat;SoC", + "MetricName": "tma_info_mem_read_latency", + "PublicDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)" }, { - "BriefDescription": "Average Frequency Utilization relative nominal frequency", - "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC", - "MetricGroup": "Power", - "MetricName": "Turbo_Utilization" + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "tma_info_retire" + }, + { + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * tma_info_core_clks", + "MetricGroup": "TmaL1;tma_L1_group", + "MetricName": "tma_info_slots" }, { "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", "MetricGroup": "SMT", - "MetricName": "SMT_2T_Utilization" + "MetricName": "tma_info_smt_2t_utilization" }, { - "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "OS", - "MetricName": "Kernel_Utilization" + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "cbox_0@event\\=0x0@", + "MetricGroup": "SoC", + "MetricName": "tma_info_socket_clks" }, { - "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", - "MetricGroup": "OS", - "MetricName": "Kernel_CPI" + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "tma_info_clks / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power", + "MetricName": "tma_info_turbo_utilization" }, { - "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", - "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time", - "MetricGroup": "HPC;Mem;MemoryBW;SoC", - "MetricName": "DRAM_BW_Use" + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire", + "MetricName": "tma_info_uoppi", + "MetricThreshold": "tma_info_uoppi > 1.05" }, { - "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches", - "MetricExpr": "1e9 * (UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_INSERTS.MISS_OPCODE@filter_opc\\=0x182@) / (Socket_CLKS / duration_time)", - "MetricGroup": "Mem;MemoryLat;SoC", - "MetricName": "MEM_Read_Latency" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", + "MetricExpr": "(12 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", - "MetricExpr": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182@ / UNC_C_TOR_OCCUPANCY.MISS_OPCODE@filter_opc\\=0x182\\,thresh\\=1@", - "MetricGroup": "Mem;MemoryBW;SoC", - "MetricName": "MEM_Parallel_Reads" + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", + "MetricConstraint": "NO_GROUP_EVENTS_SMT", + "MetricExpr": "MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_RETIRED.LLC_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_clks", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l3_bound", + "MetricThreshold": "tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Socket actual clocks when any core is active on that socket", - "MetricExpr": "cbox_0@event\\=0x0@", - "MetricGroup": "SoC", - "MetricName": "Socket_CLKS" + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", + "MetricExpr": "ILD_STALL.LCP / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_lcp", + "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", - "MetricGroup": "Branches;OS", - "MetricName": "IpFarBranch" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", + "MetricExpr": "tma_retiring - tma_heavy_operations", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_light_operations", + "MetricThreshold": "tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", + "ScaleUnit": "100%" }, { - "BriefDescription": "Uncore frequency per die [GHZ]", - "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9", - "MetricGroup": "SoC", - "MetricName": "UNCORE_FREQ" + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", + "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per core", - "MetricExpr": "cstate_core@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Core_Residency", + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=6@) / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW", + "MetricName": "tma_mem_bandwidth", + "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_info_dram_bw_use", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per core", - "MetricExpr": "cstate_core@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Core_Residency", + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_clks - tma_mem_bandwidth", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat", + "MetricName": "tma_mem_latency", + "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: ", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per core", - "MetricExpr": "cstate_core@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Core_Residency", + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - (cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if tma_info_ipc > 1.8 else cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound", + "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_memory_bound", + "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", "ScaleUnit": "100%" }, { - "BriefDescription": "C2 residency percent per package", - "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C2_Pkg_Residency", + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_slots", + "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS", + "MetricName": "tma_microcode_sequencer", + "MetricThreshold": "tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per package", - "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Pkg_Residency", + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", + "MetricExpr": "3 * IDQ.MS_SWITCHES / tma_info_clks", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", + "MetricName": "tma_ms_switches", + "MetricThreshold": "tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per package", - "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Pkg_Residency", + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - (cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if tma_info_ipc > 1.8 else cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING)) / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_ports_utilization", + "MetricThreshold": "tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per package", - "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Pkg_Residency", + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", + "MetricExpr": "RESOURCE_STALLS.SB / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_store_bound", + "MetricThreshold": "tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric serves as an approximation of legacy x87 usage", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS * FP_COMP_OPS_EXE.X87 / UOPS_DISPATCHED.THREAD", + "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_x87_use", + "MetricThreshold": "tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", "ScaleUnit": "100%" } ] diff --git a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json b/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json index 11d41ce8c922..85c04fe7632a 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json @@ -501,7 +501,7 @@ "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding.", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", - "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", + "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", "SampleAfterValue": "100003", "UMask": "0x2" }, diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json index b9e68f9f33ea..47830ca5c682 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json @@ -572,7 +572,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.EVICTION", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x4", "Unit": "CBO" }, @@ -581,7 +581,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_ALL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0xa", "Unit": "CBO" }, @@ -590,7 +590,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x3", "Unit": "CBO" }, @@ -599,7 +599,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_ALL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x48", "Unit": "CBO" }, @@ -608,7 +608,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x44", "Unit": "CBO" }, @@ -617,7 +617,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x4a", "Unit": "CBO" }, @@ -626,7 +626,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x43", "Unit": "CBO" }, @@ -635,7 +635,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x41", "Unit": "CBO" }, @@ -644,7 +644,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_WB", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x50", "Unit": "CBO" }, @@ -653,7 +653,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x1", "Unit": "CBO" }, @@ -662,7 +662,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.WB", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x10", "Unit": "CBO" }, diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json index 1c2cf94889a1..b16bb649225d 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json @@ -20,7 +20,7 @@ "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.", "UMask": "0x2", "Unit": "QPI LL" }, @@ -29,7 +29,7 @@ "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.", "UMask": "0x8", "Unit": "QPI LL" }, @@ -38,7 +38,7 @@ "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.", "UMask": "0x4", "Unit": "QPI LL" }, @@ -47,7 +47,7 @@ "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.SUCCESS", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -80,7 +80,7 @@ "EventCode": "0x9", "EventName": "UNC_Q_RxL_BYPASSED", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", "Unit": "QPI LL" }, { @@ -176,7 +176,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_RxL_FLITS_G0.DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", + "PublicDescription": "Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", "UMask": "0x2", "Unit": "QPI LL" }, @@ -185,7 +185,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_RxL_FLITS_G0.IDLE", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", + "PublicDescription": "Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -194,7 +194,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_RxL_FLITS_G0.NON_DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", + "PublicDescription": "Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", "UMask": "0x4", "Unit": "QPI LL" }, @@ -203,7 +203,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.DRS", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x18", "Unit": "QPI LL" }, @@ -212,7 +212,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x8", "Unit": "QPI LL" }, @@ -221,7 +221,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x10", "Unit": "QPI LL" }, @@ -230,7 +230,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.HOM", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x6", "Unit": "QPI LL" }, @@ -239,7 +239,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x4", "Unit": "QPI LL" }, @@ -248,7 +248,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x2", "Unit": "QPI LL" }, @@ -257,7 +257,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.SNP", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -266,7 +266,7 @@ "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCB", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0xc", "Unit": "QPI LL" }, @@ -275,7 +275,7 @@ "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x4", "Unit": "QPI LL" }, @@ -284,7 +284,7 @@ "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x8", "Unit": "QPI LL" }, @@ -293,7 +293,7 @@ "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCS", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x10", "Unit": "QPI LL" }, @@ -302,7 +302,7 @@ "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -311,7 +311,7 @@ "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x2", "Unit": "QPI LL" }, @@ -553,7 +553,7 @@ "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits", "EventName": "UNC_Q_TxL_FLITS_G0.DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", "UMask": "0x2", "Unit": "QPI LL" }, @@ -561,7 +561,7 @@ "BriefDescription": "Flits Transferred - Group 0; Idle and Null Flits", "EventName": "UNC_Q_TxL_FLITS_G0.IDLE", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -569,7 +569,7 @@ "BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits", "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", "UMask": "0x4", "Unit": "QPI LL" }, @@ -577,7 +577,7 @@ "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)", "EventName": "UNC_Q_TxL_FLITS_G1.DRS", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x18", "Unit": "QPI LL" }, @@ -585,7 +585,7 @@ "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits", "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x8", "Unit": "QPI LL" }, @@ -593,7 +593,7 @@ "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits", "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x10", "Unit": "QPI LL" }, @@ -601,7 +601,7 @@ "BriefDescription": "Flits Transferred - Group 1; HOM Flits", "EventName": "UNC_Q_TxL_FLITS_G1.HOM", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x6", "Unit": "QPI LL" }, @@ -609,7 +609,7 @@ "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits", "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x4", "Unit": "QPI LL" }, @@ -617,7 +617,7 @@ "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits", "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x2", "Unit": "QPI LL" }, @@ -625,7 +625,7 @@ "BriefDescription": "Flits Transferred - Group 1; SNP Flits", "EventName": "UNC_Q_TxL_FLITS_G1.SNP", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -634,7 +634,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCB", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0xc", "Unit": "QPI LL" }, @@ -643,7 +643,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x4", "Unit": "QPI LL" }, @@ -652,7 +652,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x8", "Unit": "QPI LL" }, @@ -661,7 +661,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCS", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x10", "Unit": "QPI LL" }, @@ -670,7 +670,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -679,7 +679,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x2", "Unit": "QPI LL" }, diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json index 2faf0dc6675d..6dcc9415a462 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json @@ -101,7 +101,7 @@ "EventCode": "0x9", "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", "PerPkg": "1", - "PublicDescription": "Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit erros in lockstep mode.", + "PublicDescription": "Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit errors in lockstep mode.", "Unit": "iMC" }, { @@ -413,7 +413,7 @@ "EventCode": "0x81", "EventName": "UNC_M_WPQ_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.", + "PublicDescription": "Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.", "Unit": "iMC" }, { diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-other.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-other.json index 51a9a4e81046..ca727c0e1865 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-other.json @@ -284,7 +284,7 @@ "EventCode": "0xD", "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.", + "PublicDescription": "Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.", "Unit": "IRP" }, { @@ -630,7 +630,7 @@ "EventCode": "0x20", "EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.DRS", "PerPkg": "1", - "PublicDescription": "Counts the number of times the NCS/NCB/DRS credit is acquried in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions). This event can only track one message class at a time.", + "PublicDescription": "Counts the number of times the NCS/NCB/DRS credit is acquired in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", "UMask": "0x8", "Unit": "R3QPI" }, @@ -639,7 +639,7 @@ "EventCode": "0x20", "EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.NCB", "PerPkg": "1", - "PublicDescription": "Counts the number of times the NCS/NCB/DRS credit is acquried in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions). This event can only track one message class at a time.", + "PublicDescription": "Counts the number of times the NCS/NCB/DRS credit is acquired in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", "UMask": "0x10", "Unit": "R3QPI" }, @@ -648,7 +648,7 @@ "EventCode": "0x20", "EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.NCS", "PerPkg": "1", - "PublicDescription": "Counts the number of times the NCS/NCB/DRS credit is acquried in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions). This event can only track one message class at a time.", + "PublicDescription": "Counts the number of times the NCS/NCB/DRS credit is acquired in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", "UMask": "0x20", "Unit": "R3QPI" }, @@ -657,7 +657,7 @@ "EventCode": "0x21", "EventName": "UNC_R3_IIO_CREDITS_REJECT.DRS", "PerPkg": "1", - "PublicDescription": "Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions). This event can only track one message class at a time.", + "PublicDescription": "Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", "UMask": "0x8", "Unit": "R3QPI" }, @@ -666,7 +666,7 @@ "EventCode": "0x21", "EventName": "UNC_R3_IIO_CREDITS_REJECT.NCB", "PerPkg": "1", - "PublicDescription": "Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions). This event can only track one message class at a time.", + "PublicDescription": "Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", "UMask": "0x10", "Unit": "R3QPI" }, @@ -675,7 +675,7 @@ "EventCode": "0x21", "EventName": "UNC_R3_IIO_CREDITS_REJECT.NCS", "PerPkg": "1", - "PublicDescription": "Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions). This event can only track one message class at a time.", + "PublicDescription": "Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", "UMask": "0x20", "Unit": "R3QPI" }, @@ -684,7 +684,7 @@ "EventCode": "0x22", "EventName": "UNC_R3_IIO_CREDITS_USED.DRS", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions). This event can only track one message class at a time.", + "PublicDescription": "Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", "UMask": "0x8", "Unit": "R3QPI" }, @@ -693,7 +693,7 @@ "EventCode": "0x22", "EventName": "UNC_R3_IIO_CREDITS_USED.NCB", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions). This event can only track one message class at a time.", + "PublicDescription": "Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", "UMask": "0x10", "Unit": "R3QPI" }, @@ -702,7 +702,7 @@ "EventCode": "0x22", "EventName": "UNC_R3_IIO_CREDITS_USED.NCS", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transfering data without coherency, and DRS is used for transfering data with coherency (cachable PCI transactions). This event can only track one message class at a time.", + "PublicDescription": "Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", "UMask": "0x20", "Unit": "R3QPI" }, @@ -1107,7 +1107,7 @@ "EventCode": "0x33", "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED", "PerPkg": "1", - "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transfered). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transfered in a given message class using an qfclk event.", + "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.", "Unit": "R3QPI" }, { diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json index 638aa8a35cdb..b3ee5d741015 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json @@ -234,7 +234,7 @@ "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", "PerPkg": "1", - "PublicDescription": "This is an occupancy event that tracks the number of cores that are in C0. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", + "PublicDescription": "This is an occupancy event that tracks the number of cores that are in C0. It can be used by itself to get the average number of cores in C0, with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", "Unit": "PCU" }, { @@ -242,7 +242,7 @@ "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", "PerPkg": "1", - "PublicDescription": "This is an occupancy event that tracks the number of cores that are in C0. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", + "PublicDescription": "This is an occupancy event that tracks the number of cores that are in C0. It can be used by itself to get the average number of cores in C0, with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", "Unit": "PCU" }, { @@ -250,7 +250,7 @@ "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", "PerPkg": "1", - "PublicDescription": "This is an occupancy event that tracks the number of cores that are in C0. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", + "PublicDescription": "This is an occupancy event that tracks the number of cores that are in C0. It can be used by itself to get the average number of cores in C0, with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", "Unit": "PCU" }, { @@ -266,7 +266,7 @@ "EventCode": "0x9", "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that we are in Interal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.", + "PublicDescription": "Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.", "Unit": "PCU" }, { diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 77af9d0bf6d4..afe811f154d7 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -16,7 +16,7 @@ GenuineIntel-6-(7D|7E|A7),v1.17,icelake,core GenuineIntel-6-6[AC],v1.18,icelakex,core GenuineIntel-6-3A,v23,ivybridge,core GenuineIntel-6-3E,v22,ivytown,core -GenuineIntel-6-2D,v21,jaketown,core +GenuineIntel-6-2D,v22,jaketown,core GenuineIntel-6-(57|85),v9,knightslanding,core GenuineIntel-6-A[AC],v1.00,meteorlake,core GenuineIntel-6-1[AEF],v3,nehalemep,core -- cgit v1.2.3-58-ga151 From 0a080050433f49fe885de824670472b4c133637b Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:21 -0800 Subject: perf vendor events intel: Refresh knightslanding events Update the knightslanding events from 9 to 10. Generation was done using https://github.com/intel/perfmon. The most notable change is in corrections to event descriptions. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-25-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/knightslanding/cache.json | 94 +++++++++++----------- .../arch/x86/knightslanding/pipeline.json | 8 +- .../arch/x86/knightslanding/uncore-other.json | 8 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 4 files changed, 56 insertions(+), 56 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/cache.json b/tools/perf/pmu-events/arch/x86/knightslanding/cache.json index 01aea3d2832e..d9876cb06b08 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/cache.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/cache.json @@ -6,7 +6,7 @@ "SampleAfterValue": "200003" }, { - "BriefDescription": "Counts the number of core cycles the fetch stalls because of an icache miss. This is a cummulative count of core cycles the fetch stalled for all icache misses.", + "BriefDescription": "Counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of core cycles the fetch stalled for all icache misses.", "EventCode": "0x86", "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", "PublicDescription": "This event counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache misses.", @@ -28,7 +28,7 @@ "UMask": "0x4f" }, { - "BriefDescription": "Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) exlcuding SW prefetches filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times", + "BriefDescription": "Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) excluding SW prefetches filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times", "EventCode": "0x30", "EventName": "L2_REQUESTS_REJECT.ALL", "SampleAfterValue": "200003" @@ -108,7 +108,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -135,7 +135,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -198,7 +198,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts Demand code reads and prefetch code read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -216,7 +216,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -243,7 +243,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -306,7 +306,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -324,7 +324,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "BriefDescription": "Counts any Prefetch requests that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -351,7 +351,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "BriefDescription": "Counts any Prefetch requests that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -405,7 +405,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "BriefDescription": "Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.OUTSTANDING", "MSRIndex": "0x1a6", @@ -423,7 +423,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts any Read request that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "BriefDescription": "Counts any Read request that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -450,7 +450,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts any Read request that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "BriefDescription": "Counts any Read request that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -513,7 +513,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts any Read request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "BriefDescription": "Counts any Read request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING", "MSRIndex": "0x1a6", @@ -531,7 +531,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts any request that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "BriefDescription": "Counts any request that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -558,7 +558,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts any request that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "BriefDescription": "Counts any request that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -621,7 +621,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "BriefDescription": "Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING", "MSRIndex": "0x1a6", @@ -639,7 +639,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts Demand cacheable data write requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -666,7 +666,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts Demand cacheable data write requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -729,7 +729,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts Demand cacheable data write requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "BriefDescription": "Counts Demand cacheable data write requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING", "MSRIndex": "0x1a6", @@ -747,7 +747,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -774,7 +774,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -837,7 +837,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "BriefDescription": "Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING", "MSRIndex": "0x1a6", @@ -855,7 +855,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -882,7 +882,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -945,7 +945,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "BriefDescription": "Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -1035,7 +1035,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -1053,7 +1053,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -1080,7 +1080,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -1143,7 +1143,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "BriefDescription": "Counts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", "MSRIndex": "0x1a6", @@ -1170,7 +1170,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -1197,7 +1197,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -1260,7 +1260,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.OUTSTANDING", "MSRIndex": "0x1a6", @@ -1287,7 +1287,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE", "MSRIndex": "0x1a7", @@ -1314,7 +1314,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a7", @@ -1386,7 +1386,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -1413,7 +1413,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -1476,7 +1476,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "BriefDescription": "Counts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -1494,7 +1494,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -1521,7 +1521,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -1566,7 +1566,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "BriefDescription": "Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -1602,7 +1602,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -1683,7 +1683,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "BriefDescription": "Counts Software Prefetches that accounts for responses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -1710,7 +1710,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "BriefDescription": "Counts Software Prefetches that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -1773,7 +1773,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "BriefDescription": "Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.OUTSTANDING", "MSRIndex": "0x1a6", @@ -1818,7 +1818,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -1881,7 +1881,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0.", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.OUTSTANDING", "MSRIndex": "0x1a6", diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json b/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json index 1b803fa38641..3dc532107ead 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json @@ -254,14 +254,14 @@ "UMask": "0x80" }, { - "BriefDescription": "Counts the number of occurences a retired load gets blocked because its address overlaps with a store whose data is not ready", + "BriefDescription": "Counts the number of occurrences a retired load gets blocked because its address overlaps with a store whose data is not ready", "EventCode": "0x03", "EventName": "RECYCLEQ.LD_BLOCK_STD_NOTREADY", "SampleAfterValue": "200003", "UMask": "0x2" }, { - "BriefDescription": "Counts the number of occurences a retired load gets blocked because its address partially overlaps with a store", + "BriefDescription": "Counts the number of occurrences a retired load gets blocked because its address partially overlaps with a store", "Data_LA": "1", "EventCode": "0x03", "EventName": "RECYCLEQ.LD_BLOCK_ST_FORWARD", @@ -270,7 +270,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts the number of occurences a retired load that is a cache line split. Each split should be counted only once.", + "BriefDescription": "Counts the number of occurrences a retired load that is a cache line split. Each split should be counted only once.", "Data_LA": "1", "EventCode": "0x03", "EventName": "RECYCLEQ.LD_SPLITS", @@ -293,7 +293,7 @@ "UMask": "0x20" }, { - "BriefDescription": "Counts the number of occurences a retired store that is a cache line split. Each split should be counted only once.", + "BriefDescription": "Counts the number of occurrences a retired store that is a cache line split. Each split should be counted only once.", "EventCode": "0x03", "EventName": "RECYCLEQ.ST_SPLITS", "PublicDescription": "This event counts the number of retired store that experienced a cache line boundary split(Precise Event). Note that each spilt should be counted only once.", diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json index 3abd9c3fdc48..491cb37ddab0 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json @@ -1084,7 +1084,7 @@ "Unit": "CHA" }, { - "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Writeback transactions from L2 to the LLC This includes all write transactions -- both Cachable and UC.", + "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.", "EventCode": "0x37", "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.E_STATE", "PerPkg": "1", @@ -1843,7 +1843,7 @@ "Unit": "CHA" }, { - "BriefDescription": "Counts cycles source throttling is adderted - horizontal", + "BriefDescription": "Counts cycles source throttling is asserted - horizontal", "EventCode": "0xA5", "EventName": "UNC_H_FAST_ASSERTED.HORZ", "PerPkg": "1", @@ -1851,7 +1851,7 @@ "Unit": "CHA" }, { - "BriefDescription": "Counts cycles source throttling is adderted - vertical", + "BriefDescription": "Counts cycles source throttling is asserted - vertical", "EventCode": "0xA5", "EventName": "UNC_H_FAST_ASSERTED.VERT", "PerPkg": "1", @@ -2929,7 +2929,7 @@ "Unit": "CHA" }, { - "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Writeback transactions from L2 to the LLC This includes all write transactions -- both Cachable and UC.", + "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.", "EventCode": "0x34", "EventName": "UNC_H_SF_LOOKUP.WRITE", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index afe811f154d7..41bd13baa265 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -17,7 +17,7 @@ GenuineIntel-6-6[AC],v1.18,icelakex,core GenuineIntel-6-3A,v23,ivybridge,core GenuineIntel-6-3E,v22,ivytown,core GenuineIntel-6-2D,v22,jaketown,core -GenuineIntel-6-(57|85),v9,knightslanding,core +GenuineIntel-6-(57|85),v10,knightslanding,core GenuineIntel-6-A[AC],v1.00,meteorlake,core GenuineIntel-6-1[AEF],v3,nehalemep,core GenuineIntel-6-2E,v3,nehalemex,core -- cgit v1.2.3-58-ga151 From 4507f603ffd21598f93d55ffb592bbaa27f2356e Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:22 -0800 Subject: perf vendor events intel: Refresh sandybridge events Update the sandybridge events from 17 to 18. Generation was done using https://github.com/intel/perfmon. Notable changes are improved event descriptions, TMA metrics are updated to version 4.5, TMA info metrics are renamed from their node name to be lower case and prefixed by tma_info_, MetricThreshold expressions are added, and the smi_cost metric group is added replicating existing hard coded metrics in stat-shadow. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-26-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- .../pmu-events/arch/x86/sandybridge/cache.json | 8 +- .../arch/x86/sandybridge/floating-point.json | 2 +- .../pmu-events/arch/x86/sandybridge/frontend.json | 12 +- .../pmu-events/arch/x86/sandybridge/pipeline.json | 2 +- .../arch/x86/sandybridge/snb-metrics.json | 601 ++++++++++++--------- 6 files changed, 344 insertions(+), 283 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 41bd13baa265..02715cbe4fd8 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -21,7 +21,7 @@ GenuineIntel-6-(57|85),v10,knightslanding,core GenuineIntel-6-A[AC],v1.00,meteorlake,core GenuineIntel-6-1[AEF],v3,nehalemep,core GenuineIntel-6-2E,v3,nehalemex,core -GenuineIntel-6-2A,v17,sandybridge,core +GenuineIntel-6-2A,v18,sandybridge,core GenuineIntel-6-(8F|CF),v1.09,sapphirerapids,core GenuineIntel-6-(37|4A|4C|4D|5A),v14,silvermont,core GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v53,skylake,core diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/cache.json b/tools/perf/pmu-events/arch/x86/sandybridge/cache.json index 65696ea2a581..4e5572ee7dfe 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/cache.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/cache.json @@ -37,7 +37,7 @@ "UMask": "0x5" }, { - "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", @@ -45,7 +45,7 @@ "UMask": "0x2" }, { - "BriefDescription": "L1D miss oustandings duration in cycles.", + "BriefDescription": "L1D miss outstanding duration in cycles.", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "SampleAfterValue": "2000003", @@ -493,7 +493,7 @@ "UMask": "0x8" }, { - "BriefDescription": "Cacheable and noncachaeble code read requests.", + "BriefDescription": "Cacheable and noncacheable code read requests.", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "SampleAfterValue": "100003", @@ -898,7 +898,7 @@ "UMask": "0x1" }, { - "BriefDescription": "COREWB & ANY_RESPONSE", + "BriefDescription": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json b/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json index 8c2a246adef9..79e8f403c426 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json @@ -64,7 +64,7 @@ "UMask": "0x20" }, { - "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.", + "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.X87", "SampleAfterValue": "2000003", diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json b/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json index 69ab8d215f84..700716b42f1a 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json @@ -134,7 +134,7 @@ "UMask": "0x4" }, { - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", @@ -143,7 +143,7 @@ "UMask": "0x30" }, { - "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -151,7 +151,7 @@ "UMask": "0x10" }, { - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy.", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -160,14 +160,14 @@ "UMask": "0x10" }, { - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_UOPS", "SampleAfterValue": "2000003", "UMask": "0x10" }, { - "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", "SampleAfterValue": "2000003", @@ -183,7 +183,7 @@ "UMask": "0x30" }, { - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "SampleAfterValue": "2000003", diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json b/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json index 53ab5993e8b0..54454e5e262c 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json @@ -509,7 +509,7 @@ "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding.", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", - "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", + "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. See the table of not supported store forwards in the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", "SampleAfterValue": "100003", "UMask": "0x2" }, diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json b/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json index a7b3c835b03d..4a99fe515f4b 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json @@ -1,449 +1,510 @@ [ { - "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", - "MetricGroup": "PGO;TopdownL1;tma_L1_group", - "MetricName": "tma_frontend_bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", - "MetricExpr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / SLOTS", - "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_latency", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", + "BriefDescription": "C2 residency percent per package", + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C2_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", - "MetricExpr": "(12 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / CLKS", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_itlb_misses", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED", + "BriefDescription": "C3 residency percent per core", + "MetricExpr": "cstate_core@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", - "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / CLKS", - "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_branch_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "C3 residency percent per package", + "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_dsb_switches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", - "MetricExpr": "ILD_STALL.LCP / CLKS", - "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_lcp", - "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", - "MetricExpr": "3 * IDQ.MS_SWITCHES / CLKS", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_ms_switches", - "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES", + "BriefDescription": "C7 residency percent per core", + "MetricExpr": "cstate_core@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", - "MetricExpr": "tma_frontend_bound - tma_fetch_latency", - "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_bandwidth", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", + "BriefDescription": "C7 residency percent per package", + "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", - "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_bad_speculation", - "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", - "ScaleUnit": "100%" + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "tma_info_socket_clks / #num_dies / duration_time / 1e9", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_branch_mispredicts", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "Percentage of cycles spent in System Management Interrupts.", + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", + "MetricGroup": "smi", + "MetricName": "smi_cycles", + "MetricThreshold": "smi_cycles > 0.1", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", - "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_machine_clears", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT", - "ScaleUnit": "100%" + "BriefDescription": "Number of SMI interrupts.", + "MetricExpr": "msr@smi@", + "MetricGroup": "smi", + "MetricName": "smi_num", + "ScaleUnit": "1SMI#" }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)", - "MetricGroup": "TopdownL1;tma_L1_group", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", + "MetricThreshold": "tma_backend_bound > 0.2", "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", - "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if IPC > 1.8 else (cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) * tma_backend_bound", - "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_memory_bound", - "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", - "MetricExpr": "(7 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / CLKS", - "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_dtlb_load", - "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", - "MetricExpr": "MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l3_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", - "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / CLKS", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_dram_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=6@) / CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group", - "MetricName": "tma_mem_bandwidth", - "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", + "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_bad_speculation", + "MetricThreshold": "tma_bad_speculation > 0.15", + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group", - "MetricName": "tma_mem_latency", - "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", + "MetricName": "tma_branch_mispredicts", + "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_mispredicts_resteers", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", - "MetricExpr": "RESOURCE_STALLS.SB / CLKS", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_store_bound", - "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES_PS", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", + "MetricExpr": "12 * (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY) / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_branch_resteers", + "MetricThreshold": "tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_backend_bound - tma_memory_bound", - "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_core_bound", + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", - "MetricExpr": "ARITH.FPU_DIV_ACTIVE / CORE_CLKS", - "MetricGroup": "TopdownL3;tma_core_bound_group", + "MetricExpr": "ARITH.FPU_DIV_ACTIVE / tma_info_core_clks", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_divider", + "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_UOPS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", - "MetricExpr": "((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if IPC > 1.8 else (cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@ - RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else RESOURCE_STALLS.SB)) - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING)) / CLKS", - "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group", - "MetricName": "tma_ports_utilization", - "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", + "MetricConstraint": "NO_GROUP_EVENTS_SMT", + "MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS)) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_dram_bound", + "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_MISS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_clks", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_dsb_switches", + "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Related metrics: tma_fetch_bandwidth, tma_info_dsb_coverage, tma_lcp", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", - "MetricExpr": "tma_retiring - tma_heavy_operations", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_light_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", + "MetricExpr": "(7 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.WALK_DURATION) / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group", + "MetricName": "tma_dtlb_load", + "MetricThreshold": "tma_dtlb_load > 0.1", + "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", + "MetricExpr": "tma_frontend_bound - tma_fetch_latency", + "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", + "MetricName": "tma_fetch_bandwidth", + "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_lcp", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", + "MetricExpr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) / tma_info_slots", + "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_latency", + "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: RS_EVENTS.EMPTY_END", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", - "MetricGroup": "HPC;TopdownL3;tma_light_operations_group", + "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", "MetricName": "tma_fp_arith", + "MetricThreshold": "tma_fp_arith > 0.2 & tma_light_operations > 0.6", "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", "ScaleUnit": "100%" }, - { - "BriefDescription": "This metric serves as an approximation of legacy x87 usage", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS * FP_COMP_OPS_EXE.X87 / UOPS_DISPATCHED.THREAD", - "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_x87_use", - "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", - "ScaleUnit": "100%" - }, { "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) / UOPS_DISPATCHED.THREAD", - "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", "MetricName": "tma_fp_scalar", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", + "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_512b, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", "MetricExpr": "(FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) / UOPS_DISPATCHED.THREAD", - "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", "MetricName": "tma_fp_vector", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", + "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_512b, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_slots", + "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.15", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences", "MetricExpr": "tma_microcode_sequencer", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", "MetricName": "tma_heavy_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.", + "MetricThreshold": "tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS", - "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group", - "MetricName": "tma_microcode_sequencer", - "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS", - "ScaleUnit": "100%" + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "tma_info_turbo_utilization * TSC / 1e9 / duration_time", + "MetricGroup": "Power;Summary", + "MetricName": "tma_info_average_frequency" }, { - "BriefDescription": "Instructions Per Cycle (per Logical Processor)", - "MetricExpr": "INST_RETIRED.ANY / CLKS", - "MetricGroup": "Ret;Summary", - "MetricName": "IPC" + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline", + "MetricName": "tma_info_clks" }, { - "BriefDescription": "Uops Per Instruction", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Ret;Retire", - "MetricName": "UPI" + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else tma_info_clks))", + "MetricGroup": "SMT", + "MetricName": "tma_info_core_clks" + }, + { + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_core_clks", + "MetricGroup": "Ret;SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_coreipc" }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / IPC", + "MetricExpr": "1 / tma_info_ipc", "MetricGroup": "Mem;Pipeline", - "MetricName": "CPI" + "MetricName": "tma_info_cpi" }, { - "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Pipeline", - "MetricName": "CLKS" + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "HPC;Summary", + "MetricName": "tma_info_cpu_utilization" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", - "MetricExpr": "4 * CORE_CLKS", - "MetricGroup": "tma_L1_group", - "MetricName": "SLOTS" + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;tma_issueBW", + "MetricName": "tma_info_dram_bw_use", + "PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_mem_bandwidth" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", + "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", + "MetricName": "tma_info_dsb_coverage", + "MetricThreshold": "tma_info_dsb_coverage < 0.7 & tma_info_ipc / 4 > 0.35", + "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_lcp" }, { "BriefDescription": "The ratio of Executed- by Issued-Uops", "MetricExpr": "UOPS_DISPATCHED.THREAD / UOPS_ISSUED.ANY", "MetricGroup": "Cor;Pipeline", - "MetricName": "Execute_per_Issue", + "MetricName": "tma_info_execute_per_issue", "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." }, - { - "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS", - "MetricGroup": "Ret;SMT;tma_L1_group", - "MetricName": "CoreIPC" - }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / CORE_CLKS", + "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / tma_info_core_clks", "MetricGroup": "Flops;Ret", - "MetricName": "FLOPc" + "MetricName": "tma_info_flopc" + }, + { + "BriefDescription": "Giga Floating Point Operations Per Second", + "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1e9 / duration_time", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_gflops", + "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." }, { "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", "MetricExpr": "UOPS_DISPATCHED.THREAD / (cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@ / 2 if #SMT_on else cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@)", "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", - "MetricName": "ILP" + "MetricName": "tma_info_ilp" }, { - "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", - "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))", - "MetricGroup": "SMT", - "MetricName": "CORE_CLKS" + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;tma_L1_group", + "MetricName": "tma_info_instructions", + "PublicDescription": "Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST" }, { - "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary;tma_L1_group", - "MetricName": "Instructions" + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_clks", + "MetricGroup": "Ret;Summary", + "MetricName": "tma_info_ipc" }, { - "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@", - "MetricGroup": "Pipeline;Ret", - "MetricName": "Retire" + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "tma_info_ipfarbranch", + "MetricThreshold": "tma_info_ipfarbranch < 1e6" }, { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "DSB;Fed;FetchBW", - "MetricName": "DSB_Coverage" + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_cpi" }, { - "BriefDescription": "Average CPU Utilization", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", - "MetricGroup": "HPC;Summary", - "MetricName": "CPU_Utilization" + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_utilization", + "MetricThreshold": "tma_info_kernel_utilization > 0.05" }, { - "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", - "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time", - "MetricGroup": "Power;Summary", - "MetricName": "Average_Frequency" + "BriefDescription": "Average number of parallel requests to external memory", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", + "MetricGroup": "Mem;SoC", + "MetricName": "tma_info_mem_parallel_requests", + "PublicDescription": "Average number of parallel requests to external memory. Accounts for all requests" }, { - "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "(FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * (FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) + 8 * SIMD_FP_256.PACKED_SINGLE) / 1e9 / duration_time", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs", - "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." + "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL", + "MetricGroup": "Mem;SoC", + "MetricName": "tma_info_mem_request_latency" }, { - "BriefDescription": "Average Frequency Utilization relative nominal frequency", - "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC", - "MetricGroup": "Power", - "MetricName": "Turbo_Utilization" + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "tma_info_retire" + }, + { + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * tma_info_core_clks", + "MetricGroup": "TmaL1;tma_L1_group", + "MetricName": "tma_info_slots" }, { "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", "MetricGroup": "SMT", - "MetricName": "SMT_2T_Utilization" + "MetricName": "tma_info_smt_2t_utilization" }, { - "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "OS", - "MetricName": "Kernel_Utilization" + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "UNC_CLOCK.SOCKET", + "MetricGroup": "SoC", + "MetricName": "tma_info_socket_clks" }, { - "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", - "MetricGroup": "OS", - "MetricName": "Kernel_CPI" + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "tma_info_clks / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power", + "MetricName": "tma_info_turbo_utilization" }, { - "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", - "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3", - "MetricGroup": "HPC;Mem;MemoryBW;SoC", - "MetricName": "DRAM_BW_Use" + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire", + "MetricName": "tma_info_uoppi", + "MetricThreshold": "tma_info_uoppi > 1.05" }, { - "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)", - "MetricExpr": "MEM_Parallel_Requests", - "MetricGroup": "Mem;SoC", - "MetricName": "MEM_Request_Latency" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", + "MetricExpr": "(12 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURATION) / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_MISSES.WALK_COMPLETED", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests", - "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL", - "MetricGroup": "Mem;SoC", - "MetricName": "MEM_Parallel_Requests" + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", + "MetricConstraint": "NO_GROUP_EVENTS_SMT", + "MetricExpr": "MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS) * CYCLE_ACTIVITY.STALLS_L2_PENDING / tma_info_clks", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l3_bound", + "MetricThreshold": "tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Socket actual clocks when any core is active on that socket", - "MetricExpr": "UNC_CLOCK.SOCKET", - "MetricGroup": "SoC", - "MetricName": "Socket_CLKS" + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", + "MetricExpr": "ILD_STALL.LCP / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_lcp", + "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", - "MetricGroup": "Branches;OS", - "MetricName": "IpFarBranch" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", + "MetricExpr": "tma_retiring - tma_heavy_operations", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_light_operations", + "MetricThreshold": "tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", + "ScaleUnit": "100%" }, { - "BriefDescription": "Uncore frequency per die [GHZ]", - "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9", - "MetricGroup": "SoC", - "MetricName": "UNCORE_FREQ" + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", + "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per core", - "MetricExpr": "cstate_core@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Core_Residency", + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=6@) / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW", + "MetricName": "tma_mem_bandwidth", + "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_info_dram_bw_use", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per core", - "MetricExpr": "cstate_core@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Core_Residency", + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_clks - tma_mem_bandwidth", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat", + "MetricName": "tma_mem_latency", + "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: ", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per core", - "MetricExpr": "cstate_core@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Core_Residency", + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - (cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if tma_info_ipc > 1.8 else cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB) * tma_backend_bound", + "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_memory_bound", + "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", "ScaleUnit": "100%" }, { - "BriefDescription": "C2 residency percent per package", - "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C2_Pkg_Residency", + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_slots", + "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS", + "MetricName": "tma_microcode_sequencer", + "MetricThreshold": "tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per package", - "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Pkg_Residency", + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", + "MetricExpr": "3 * IDQ.MS_SWITCHES / tma_info_clks", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", + "MetricName": "tma_ms_switches", + "MetricThreshold": "tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per package", - "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Pkg_Residency", + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_DISPATCH) + cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=1@ - (cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=3@ if tma_info_ipc > 1.8 else cpu@UOPS_DISPATCHED.THREAD\\,cmask\\=2@) - (RS_EVENTS.EMPTY_CYCLES if tma_fetch_latency > 0.1 else 0) + RESOURCE_STALLS.SB - RESOURCE_STALLS.SB - min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_L1D_PENDING)) / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_ports_utilization", + "MetricThreshold": "tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per package", - "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Pkg_Residency", + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", + "MetricExpr": "RESOURCE_STALLS.SB / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_store_bound", + "MetricThreshold": "tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_UOPS_RETIRED.ALL_STORES_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric serves as an approximation of legacy x87 usage", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS * FP_COMP_OPS_EXE.X87 / UOPS_DISPATCHED.THREAD", + "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_x87_use", + "MetricThreshold": "tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", "ScaleUnit": "100%" } ] -- cgit v1.2.3-58-ga151 From aa2050030d65777596498256acd5f1584421e33a Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:23 -0800 Subject: perf vendor events intel: Refresh sapphirerapids events Update the sapphirerapids events from 1.09 to 1.11. Generation was done using https://github.com/intel/perfmon. Notable changes are new events and event descriptions, TMA metrics are updated to version 4.5, TMA info metrics are renamed from their node name to be lower case and prefixed by tma_info_, MetricThreshold expressions are added, smi_cost and transaction metric groups are added replicating existing hard coded metrics in stat-shadow. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-27-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- .../pmu-events/arch/x86/sapphirerapids/cache.json | 24 +- .../arch/x86/sapphirerapids/floating-point.json | 32 + .../arch/x86/sapphirerapids/frontend.json | 8 + .../arch/x86/sapphirerapids/pipeline.json | 19 +- .../arch/x86/sapphirerapids/spr-metrics.json | 2283 ++++++++++---------- .../arch/x86/sapphirerapids/uncore-other.json | 60 + 7 files changed, 1304 insertions(+), 1124 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 02715cbe4fd8..1f611a7dbdda 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -22,7 +22,7 @@ GenuineIntel-6-A[AC],v1.00,meteorlake,core GenuineIntel-6-1[AEF],v3,nehalemep,core GenuineIntel-6-2E,v3,nehalemex,core GenuineIntel-6-2A,v18,sandybridge,core -GenuineIntel-6-(8F|CF),v1.09,sapphirerapids,core +GenuineIntel-6-(8F|CF),v1.11,sapphirerapids,core GenuineIntel-6-(37|4A|4C|4D|5A),v14,silvermont,core GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v53,skylake,core GenuineIntel-6-55-[01234],v1.28,skylakex,core diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json index 92a605ecac6e..9606e76b98d6 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json @@ -97,18 +97,18 @@ "UMask": "0x4" }, { - "BriefDescription": "All accesses to L2 cache[This event is alias to L2_RQSTS.REFERENCES]", + "BriefDescription": "All accesses to L2 cache [This event is alias to L2_RQSTS.REFERENCES]", "EventCode": "0x24", "EventName": "L2_REQUEST.ALL", - "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses.[This event is alias to L2_RQSTS.REFERENCES]", + "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES]", "SampleAfterValue": "200003", "UMask": "0xff" }, { - "BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_RQSTS.MISS]", + "BriefDescription": "Read requests with true-miss in L2 cache. [This event is alias to L2_RQSTS.MISS]", "EventCode": "0x24", "EventName": "L2_REQUEST.MISS", - "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses.[This event is alias to L2_RQSTS.MISS]", + "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS]", "SampleAfterValue": "200003", "UMask": "0x3f" }, @@ -199,18 +199,18 @@ "UMask": "0x30" }, { - "BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_REQUEST.MISS]", + "BriefDescription": "Read requests with true-miss in L2 cache. [This event is alias to L2_REQUEST.MISS]", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", - "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses.[This event is alias to L2_REQUEST.MISS]", + "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS]", "SampleAfterValue": "200003", "UMask": "0x3f" }, { - "BriefDescription": "All accesses to L2 cache[This event is alias to L2_REQUEST.ALL]", + "BriefDescription": "All accesses to L2 cache [This event is alias to L2_REQUEST.ALL]", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", - "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses.[This event is alias to L2_REQUEST.ALL]", + "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.ALL]", "SampleAfterValue": "200003", "UMask": "0xff" }, @@ -863,6 +863,14 @@ "SampleAfterValue": "1000003", "UMask": "0x1" }, + { + "BriefDescription": "Counts bus locks, accounts for cache line split locks and UC locks.", + "EventCode": "0x2c", + "EventName": "SQ_MISC.BUS_LOCK", + "PublicDescription": "Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically. Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, { "BriefDescription": "Number of PREFETCHNTA instructions executed.", "EventCode": "0x40", diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/floating-point.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/floating-point.json index 01baea3df562..4a9d211e9d4f 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/floating-point.json @@ -75,6 +75,14 @@ "SampleAfterValue": "100003", "UMask": "0x20" }, + { + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x18" + }, { "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "EventCode": "0xc7", @@ -91,6 +99,22 @@ "SampleAfterValue": "100003", "UMask": "0x80" }, + { + "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x60" + }, + { + "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "1000003", + "UMask": "0x3" + }, { "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "EventCode": "0xc7", @@ -107,6 +131,14 @@ "SampleAfterValue": "100003", "UMask": "0x2" }, + { + "BriefDescription": "Number of any Vector retired FP arithmetic instructions", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.VECTOR", + "PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "1000003", + "UMask": "0xfc" + }, { "BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", "EventCode": "0xcf", diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/frontend.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/frontend.json index 2c7c617f27ed..860a415e5e79 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/frontend.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/frontend.json @@ -1,4 +1,12 @@ [ + { + "BriefDescription": "Clears due to Unknown Branches.", + "EventCode": "0x60", + "EventName": "BACLEARS.ANY", + "PublicDescription": "Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Stalls caused by changing prefix length of the instruction.", "EventCode": "0x87", diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json index ceb14181ebc8..40e52357ade1 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json @@ -1,15 +1,17 @@ [ { - "BriefDescription": "AMX_OPS_RETIRED.BF16", + "BriefDescription": "AMX retired arithmetic BF16 operations.", "EventCode": "0xce", "EventName": "AMX_OPS_RETIRED.BF16", + "PublicDescription": "Number of AMX-based retired arithmetic bfloat16 (BF16) floating-point operations. Counts TDPBF16PS FP instructions. SW to use operation multiplier of 4", "SampleAfterValue": "1000003", "UMask": "0x2" }, { - "BriefDescription": "AMX_OPS_RETIRED.INT8", + "BriefDescription": "AMX retired arithmetic integer 8-bit operations.", "EventCode": "0xce", "EventName": "AMX_OPS_RETIRED.INT8", + "PublicDescription": "Number of AMX-based retired arithmetic integer operations of 8-bit width source operands. Counts TDPB[SS,UU,US,SU]D instructions. SW should use operation multiplier of 8.", "SampleAfterValue": "1000003", "UMask": "0x1" }, @@ -461,12 +463,23 @@ "UMask": "0x1" }, { - "BriefDescription": "INST_RETIRED.REP_ITERATION", + "BriefDescription": "Iterations of Repeat string retired instructions.", "EventCode": "0xc0", "EventName": "INST_RETIRED.REP_ITERATION", + "PublicDescription": "Number of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, and doubleword version and string instructions can be repeated using a repetition prefix, REP, that allows their architectural execution to be repeated a number of times as specified by the RCX register. Note the number of iterations is implementation-dependent.", "SampleAfterValue": "2000003", "UMask": "0x8" }, + { + "BriefDescription": "Clears speculative count", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xad", + "EventName": "INT_MISC.CLEARS_COUNT", + "PublicDescription": "Counts the number of speculative clears due to any type of branch misprediction or machine clears", + "SampleAfterValue": "500009", + "UMask": "0x1" + }, { "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", "EventCode": "0xad", diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json index ce18fc458e37..149cc4c07fb5 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json @@ -1,1616 +1,1675 @@ [ { - "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", - "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "Mispredictions" - }, - { - "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks", - "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "Memory_Bandwidth" + "BriefDescription": "C1 residency percent per core", + "MetricExpr": "cstate_core@c1\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C1_Core_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)", - "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound))", - "MetricGroup": "Mem;MemoryLat;Offcore", - "MetricName": "Memory_Latency" + "BriefDescription": "C2 residency percent per package", + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C2_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", - "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))", - "MetricGroup": "Mem;MemoryTLB;Offcore", - "MetricName": "Memory_Data_TLBs" + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", - "MetricExpr": "100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)", - "MetricGroup": "Ret", - "MetricName": "Branching_Overhead" + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", - "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", - "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB", - "MetricName": "Big_Code" + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "tma_info_socket_clks / #num_dies / duration_time / 1e9", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" }, { - "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", - "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code", - "MetricGroup": "Fed;FetchBW;Frontend", - "MetricName": "Instruction_Fetch_BW" + "BriefDescription": "Percentage of cycles spent in System Management Interrupts.", + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", + "MetricGroup": "smi", + "MetricName": "smi_cycles", + "MetricThreshold": "smi_cycles > 0.1", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions Per Cycle (per Logical Processor)", - "MetricExpr": "INST_RETIRED.ANY / CLKS", - "MetricGroup": "Ret;Summary", - "MetricName": "IPC" + "BriefDescription": "Number of SMI interrupts.", + "MetricExpr": "msr@smi@", + "MetricGroup": "smi", + "MetricName": "smi_num", + "ScaleUnit": "1SMI#" }, { - "BriefDescription": "Uops Per Instruction", - "MetricExpr": "tma_retiring * SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Ret;Retire", - "MetricName": "UPI" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5_11 + UOPS_DISPATCHED.PORT_6) / (5 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_alu_op_utilization", + "MetricThreshold": "tma_alu_op_utilization > 0.6", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "tma_retiring * SLOTS / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW", - "MetricName": "UpTB" + "BriefDescription": "This metric estimates fraction of cycles where the Advanced Matrix Extensions (AMX) execution engine was busy with tile (arithmetic) operations", + "MetricExpr": "EXE.AMX_BUSY / tma_info_core_clks", + "MetricGroup": "Compute;HPC;Server;TopdownL5;tma_L5_group;tma_ports_utilized_0_group", + "MetricName": "tma_amx_busy", + "MetricThreshold": "tma_amx_busy > 0.5 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)))", + "ScaleUnit": "100%" }, { - "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / IPC", - "MetricGroup": "Mem;Pipeline", - "MetricName": "CPI" + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", + "MetricExpr": "100 * cpu@ASSISTS.ANY\\,umask\\=0x1B@ / tma_info_slots", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_assists", + "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY", + "ScaleUnit": "100%" }, { - "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Pipeline", - "MetricName": "CLKS" + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists.", + "MetricExpr": "63 * ASSISTS.SSE_AVX_MIX / tma_info_slots", + "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", + "MetricName": "tma_avx_assists", + "MetricThreshold": "tma_avx_assists > 0.1", + "ScaleUnit": "100%" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", - "MetricExpr": "TOPDOWN.SLOTS", - "MetricGroup": "tma_L1_group", - "MetricName": "SLOTS" + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", + "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_backend_bound", + "MetricThreshold": "tma_backend_bound > 0.2", + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", - "MetricExpr": "(SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)", - "MetricGroup": "SMT;tma_L1_group", - "MetricName": "Slots_Utilization" + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", + "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_bad_speculation", + "MetricThreshold": "tma_bad_speculation > 0.15", + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "ScaleUnit": "100%" }, { - "BriefDescription": "The ratio of Executed- by Issued-Uops", - "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", - "MetricGroup": "Cor;Pipeline", - "MetricName": "Execute_per_Issue", - "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", + "MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_slots", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", + "MetricName": "tma_branch_mispredicts", + "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredicts_resteers", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS", - "MetricGroup": "Ret;SMT;tma_L1_group", - "MetricName": "CoreIPC" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", + "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks + tma_unknown_branches", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_branch_resteers", + "MetricThreshold": "tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "ScaleUnit": "100%" }, { - "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF + 4 * AMX_OPS_RETIRED.BF16) / CORE_CLKS", - "MetricGroup": "Flops;Ret", - "MetricName": "FLOPc" + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", + "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_cisc", + "MetricThreshold": "tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources. Sample with: FRONTEND_RETIRED.MS_FLOWS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", - "MetricExpr": "(FP_ARITH_DISPATCHED.PORT_0 + FP_ARITH_DISPATCHED.PORT_1 + FP_ARITH_DISPATCHED.PORT_5) / (2 * CORE_CLKS)", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "FP_Arith_Utilization", - "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears", + "MetricExpr": "(1 - tma_branch_mispredicts / tma_bad_speculation) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks", + "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC", + "MetricName": "tma_clears_resteers", + "MetricThreshold": "tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", - "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", - "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", - "MetricName": "ILP" + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(76 * tma_info_average_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 75.5 * tma_info_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_contested_accesses", + "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", - "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)", - "MetricGroup": "Cor;SMT", - "MetricName": "Core_Bound_Likely" + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", + "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)", + "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", - "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED", - "MetricGroup": "SMT", - "MetricName": "CORE_CLKS" + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "75.5 * tma_info_average_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_data_sharing", + "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", - "MetricGroup": "InsType", - "MetricName": "IpLoad" + "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", + "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) / tma_info_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_issueD0;tma_mite_group", + "MetricName": "tma_decoder0_alone", + "MetricThreshold": "tma_decoder0_alone > 0.1 & (tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 6 > 0.35))", + "PublicDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder. Related metrics: tma_few_uops_instructions", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", - "MetricGroup": "InsType", - "MetricName": "IpStore" + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", + "MetricExpr": "ARITH.DIV_ACTIVE / tma_info_clks", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_divider", + "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Fed;InsType", - "MetricName": "IpBranch" + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_clks - tma_pmm_bound", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_dram_bound", + "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "IpCall" + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", + "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / tma_info_core_clks / 2", + "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_dsb", + "MetricThreshold": "tma_dsb > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 6 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", - "MetricName": "IpTB" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_clks", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_dsb_switches", + "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", + "ScaleUnit": "100%" }, { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "BpTkBranch" + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", + "MetricExpr": "min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group", + "MetricName": "tma_dtlb_load", + "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store, tma_info_memory_data_tlbs", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF + 4 * AMX_OPS_RETIRED.BF16)", - "MetricGroup": "Flops;InsType", - "MetricName": "IpFLOP" + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", + "MetricExpr": "(7 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group", + "MetricName": "tma_dtlb_store", + "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, tma_info_memory_data_tlbs", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.VECTOR))", - "MetricGroup": "Flops;InsType", - "MetricName": "IpArith", - "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." + "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", + "MetricExpr": "80 * tma_info_average_frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group", + "MetricName": "tma_false_sharing", + "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", - "MetricGroup": "Flops;FpScalar;InsType", - "MetricName": "IpArith_Scalar_SP", - "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", + "MetricExpr": "L1D_PEND_MISS.FB_FULL / tma_info_clks", + "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricName": "tma_fb_full", + "MetricThreshold": "tma_fb_full > 0.3", + "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_dram_bw_use, tma_info_memory_bandwidth, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", - "MetricGroup": "Flops;FpScalar;InsType", - "MetricName": "IpArith_Scalar_DP", - "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", + "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)", + "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", + "MetricName": "tma_fetch_bandwidth", + "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 6 > 0.35", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX128", - "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", + "MetricExpr": "topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / tma_info_slots", + "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_latency", + "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX256", - "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops", + "MetricExpr": "max(0, tma_heavy_operations - tma_microcode_sequencer)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueD0", + "MetricName": "tma_few_uops_instructions", + "MetricThreshold": "tma_few_uops_instructions > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions. Related metrics: tma_decoder0_alone", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX512", - "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "This metric approximates arithmetic floating-point (FP) matrix uops fraction the CPU has retired (aggregated across all supported FP datatypes in AMX engine)", + "MetricExpr": "cpu@AMX_OPS_RETIRED.BF16\\,cmask\\=1@ / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;HPC;Pipeline;Server;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_fp_amx", + "MetricThreshold": "tma_fp_amx > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) matrix uops fraction the CPU has retired (aggregated across all supported FP datatypes in AMX engine). Refer to AMX_Busy and GFLOPs metrics for actual AMX utilization and FP performance, resp.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic AMX operation (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / AMX_OPS_RETIRED.BF16", - "MetricGroup": "Flops;FpVector;InsType;Server", - "MetricName": "IpArith_AMX_F16", - "PublicDescription": "Instructions per FP Arithmetic AMX operation (lower number means higher occurrence rate). Operations factored per matrices' sizes of the AMX instructions." + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", + "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector + tma_fp_amx", + "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_fp_arith", + "MetricThreshold": "tma_fp_arith > 0.2 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Integer Arithmetic AMX operation (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / AMX_OPS_RETIRED.INT8", - "MetricGroup": "InsType;IntVector;Server", - "MetricName": "IpArith_AMX_Int8", - "PublicDescription": "Instructions per Integer Arithmetic AMX operation (lower number means higher occurrence rate). Operations factored per matrices' sizes of the AMX instructions." + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists", + "MetricExpr": "30 * ASSISTS.FP / tma_info_slots", + "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", + "MetricName": "tma_fp_assists", + "MetricThreshold": "tma_fp_assists > 0.1", + "PublicDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called Denormals).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", - "MetricGroup": "Prefetches", - "MetricName": "IpSWPF" + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", + "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + FP_ARITH_INST_RETIRED2.SCALAR) / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_scalar", + "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary;tma_L1_group", - "MetricName": "Instructions" + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", + "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@ + FP_ARITH_INST_RETIRED2.VECTOR) / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_vector", + "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", - "MetricExpr": "tma_retiring * SLOTS / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@", - "MetricGroup": "Pipeline;Ret", - "MetricName": "Retire" + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF) / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_128b", + "MetricThreshold": "tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions", - "MetricExpr": "INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@", - "MetricGroup": "Pipeline;Ret", - "MetricName": "Strings_Cycles" + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF) / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_256b", + "MetricThreshold": "tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / cpu@ASSISTS.ANY\\,umask\\=0x1B@", - "MetricGroup": "Pipeline;Ret;Retire", - "MetricName": "IpAssist" + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_512b", + "MetricThreshold": "tma_fp_vector_512b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "", - "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", - "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", - "MetricName": "Execute" + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", + "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / tma_info_slots", + "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.15", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of Uops issued by front-end when it issued something", - "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@", - "MetricGroup": "Fed;FetchBW", - "MetricName": "Fetch_UpC" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions", + "MetricExpr": "tma_light_operations * INST_RETIRED.MACRO_FUSED / (tma_retiring * tma_info_slots)", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_fused_instructions", + "MetricThreshold": "tma_fused_instructions > 0.1 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "DSB;Fed;FetchBW", - "MetricName": "DSB_Coverage" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences", + "MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_slots", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_heavy_operations", + "MetricThreshold": "tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences. Sample with: UOPS_RETIRED.HEAVY", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@", - "MetricGroup": "DSBmiss", - "MetricName": "DSB_Switch_Cost" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses", + "MetricExpr": "ICACHE_DATA.STALLS / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_icache_misses", + "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.", - "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))", - "MetricGroup": "DSBmiss;Fed", - "MetricName": "DSB_Misses" + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "tma_info_turbo_utilization * TSC / 1e9 / duration_time", + "MetricGroup": "Power;Summary", + "MetricName": "tma_info_average_frequency" }, { - "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", - "MetricGroup": "DSBmiss;Fed", - "MetricName": "IpDSB_Miss_Ret" + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB;tma_issueBC", + "MetricName": "tma_info_big_code", + "MetricThreshold": "tma_info_big_code > 20", + "PublicDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses). Related metrics: tma_info_branching_overhead" }, { - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" + "BriefDescription": "Branch instructions per taken branch.", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_bptkbranch" }, { "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BrMispredicts", - "MetricName": "Branch_Misprediction_Cost" - }, - { - "BriefDescription": "Fraction of branches that are non-taken conditionals", - "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches;CodeGen;PGO", - "MetricName": "Cond_NT" - }, - { - "BriefDescription": "Fraction of branches that are taken conditionals", - "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches;CodeGen;PGO", - "MetricName": "Cond_TK" - }, - { - "BriefDescription": "Fraction of branches that are CALL or RET", - "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches", - "MetricName": "CallRet" - }, - { - "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", - "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches", - "MetricName": "Jump" - }, - { - "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", - "MetricExpr": "1 - (Cond_NT + Cond_TK + CallRet + Jump)", - "MetricGroup": "Bad;Branches", - "MetricName": "Other_Branches" - }, - { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY", - "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency" - }, - { - "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "Mem;MemoryBW;MemoryBound", - "MetricName": "MLP" - }, - { - "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI" - }, - { - "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI_Load" - }, - { - "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Backend;CacheMisses;Mem", - "MetricName": "L2MPKI" - }, - { - "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem;Offcore", - "MetricName": "L2MPKI_All" - }, - { - "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2MPKI_Load" - }, - { - "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", - "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2HPKI_All" - }, - { - "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2HPKI_Load" + "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_slots / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts;tma_issueBM", + "MetricName": "tma_info_branch_misprediction_cost", + "PublicDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_branch_mispredicts, tma_info_mispredictions, tma_mispredicts_resteers" }, { - "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L3MPKI" - }, - { - "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "FB_HPKI" - }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (4 * CORE_CLKS)", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "Page_Walks_Utilization" - }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "MetricExpr": "100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL)) / tma_info_slots)", + "MetricGroup": "Ret;tma_issueBC", + "MetricName": "tma_info_branching_overhead", + "MetricThreshold": "tma_info_branching_overhead > 10", + "PublicDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls). Related metrics: tma_info_big_code" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_callret" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline", + "MetricName": "tma_info_clks" }, { - "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW" + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Fed;MemoryTLB", + "MetricName": "tma_info_code_stlb_mpki" }, { - "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)", - "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / Instructions", - "MetricGroup": "L2Evicts;Mem;Server", - "MetricName": "L2_Evictions_Silent_PKI" + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "tma_info_cond_nt" }, { - "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction", - "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / Instructions", - "MetricGroup": "L2Evicts;Mem;Server", - "MetricName": "L2_Evictions_NonSilent_PKI" + "BriefDescription": "Fraction of branches that are taken conditionals", + "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "tma_info_cond_tk" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "L1D_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW_1T" + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if tma_info_smt_2t_utilization > 0.5 else 0)", + "MetricGroup": "Cor;SMT", + "MetricName": "tma_info_core_bound_likely", + "MetricThreshold": "tma_info_core_bound_likely > 0.5" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "L2_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW_1T" + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED", + "MetricGroup": "SMT", + "MetricName": "tma_info_core_clks" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW_1T" + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_core_clks", + "MetricGroup": "Ret;SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_coreipc" }, { - "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Access_BW", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW_1T" + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / tma_info_ipc", + "MetricGroup": "Mem;Pipeline", + "MetricName": "tma_info_cpi" }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", "MetricGroup": "HPC;Summary", - "MetricName": "CPU_Utilization" - }, - { - "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", - "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time", - "MetricGroup": "Power;Summary", - "MetricName": "Average_Frequency" - }, - { - "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF + 4 * AMX_OPS_RETIRED.BF16) / 1e9 / duration_time", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs", - "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." + "MetricName": "tma_info_cpu_utilization" }, { - "BriefDescription": "Tera Integer (matrix) Operations Per Second", - "MetricExpr": "8 * AMX_OPS_RETIRED.INT8 / 1e12 / duration_time", - "MetricGroup": "Cor;HPC;IntVector;Server", - "MetricName": "TIOPS" + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_data_l2_mlp" }, { - "BriefDescription": "Average Frequency Utilization relative nominal frequency", - "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC", - "MetricGroup": "Power", - "MetricName": "Turbo_Utilization" + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;tma_issueBW", + "MetricName": "tma_info_dram_bw_use", + "PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_info_memory_bandwidth, tma_mem_bandwidth, tma_sq_full" }, { - "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", - "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)", - "MetricGroup": "SMT", - "MetricName": "SMT_2T_Utilization" + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / UOPS_ISSUED.ANY", + "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", + "MetricName": "tma_info_dsb_coverage", + "MetricThreshold": "tma_info_dsb_coverage < 0.7 & tma_info_ipc / 6 > 0.35", + "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_misses, tma_info_iptb, tma_lcp" }, { - "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "OS", - "MetricName": "Kernel_Utilization" + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck", + "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))", + "MetricGroup": "DSBmiss;Fed;tma_issueFB", + "MetricName": "tma_info_dsb_misses", + "MetricThreshold": "tma_info_dsb_misses > 10", + "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_iptb, tma_lcp" }, { - "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", - "MetricGroup": "OS", - "MetricName": "Kernel_CPI" + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@", + "MetricGroup": "DSBmiss", + "MetricName": "tma_info_dsb_switch_cost" }, { - "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", - "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time", - "MetricGroup": "HPC;Mem;MemoryBW;SoC", - "MetricName": "DRAM_BW_Use" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-thread", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "tma_info_execute" }, { - "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches", - "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (Socket_CLKS / duration_time)", - "MetricGroup": "Mem;MemoryLat;SoC", - "MetricName": "MEM_Read_Latency" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "tma_info_execute_per_issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." }, { - "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", - "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@thresh\\=1@", - "MetricGroup": "Mem;MemoryBW;SoC", - "MetricName": "MEM_Parallel_Reads" + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_fb_hpki" }, { - "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", - "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / uncore_cha_0@event\\=0x1@", - "MetricGroup": "Mem;MemoryLat;Server;SoC", - "MetricName": "MEM_PMM_Read_Latency" + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_fetch_upc" }, { - "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", - "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / uncore_cha_0@event\\=0x1@", - "MetricGroup": "Mem;MemoryLat;Server;SoC", - "MetricName": "MEM_DRAM_Read_Latency" + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + FP_ARITH_INST_RETIRED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * cpu@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE\\,umask\\=0x18@ + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + cpu@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE\\,umask\\=0x60@) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF + 4 * AMX_OPS_RETIRED.BF16", + "MetricGroup": "Flops;Ret", + "MetricName": "tma_info_flopc" }, { - "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]", - "MetricExpr": "64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW;Server;SoC", - "MetricName": "PMM_Read_BW" + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(FP_ARITH_DISPATCHED.PORT_0 + FP_ARITH_DISPATCHED.PORT_1 + FP_ARITH_DISPATCHED.PORT_5) / (2 * tma_info_core_clks)", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_fp_arith_utilization", + "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." }, { - "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]", - "MetricExpr": "64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW;Server;SoC", - "MetricName": "PMM_Write_BW" + "BriefDescription": "Giga Floating Point Operations Per Second", + "MetricExpr": "tma_info_flopc / duration_time", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_gflops", + "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." }, { - "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]", - "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e9 / duration_time", - "MetricGroup": "IoBW;Mem;Server;SoC", - "MetricName": "IO_Write_BW" + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck", + "MetricExpr": "100 * (tma_fetch_latency * tma_icache_misses / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", + "MetricGroup": "Fed;FetchLat;IcMiss;tma_issueFL", + "MetricName": "tma_info_ic_misses", + "MetricThreshold": "tma_info_ic_misses > 5", + "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck. Related metrics: " }, { - "BriefDescription": "Socket actual clocks when any core is active on that socket", - "MetricExpr": "uncore_cha_0@event\\=0x1@", - "MetricGroup": "SoC", - "MetricName": "Socket_CLKS" + "BriefDescription": "Average Latency for L1 instruction cache misses", + "MetricExpr": "ICACHE_DATA.STALLS / cpu@ICACHE_DATA.STALLS\\,cmask\\=1\\,edge@", + "MetricGroup": "Fed;FetchLat;IcMiss", + "MetricName": "tma_info_icache_miss_latency" }, { - "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", - "MetricGroup": "Branches;OS", - "MetricName": "IpFarBranch" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", + "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", + "MetricName": "tma_info_ilp" }, { - "BriefDescription": "Uncore frequency per die [GHZ]", - "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9", - "MetricGroup": "SoC", - "MetricName": "UNCORE_FREQ" + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_big_code", + "MetricGroup": "Fed;FetchBW;Frontend", + "MetricName": "tma_info_instruction_fetch_bw", + "MetricThreshold": "tma_info_instruction_fetch_bw > 20" }, { - "BriefDescription": "Percentage of time spent in the active CPU power state C0", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", - "MetricName": "cpu_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;tma_L1_group", + "MetricName": "tma_info_instructions", + "PublicDescription": "Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST" }, { - "BriefDescription": "CPU operating frequency (in GHz)", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / duration_time", - "MetricName": "cpu_operating_frequency", - "ScaleUnit": "1GHz" + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e9 / duration_time", + "MetricGroup": "IoBW;Mem;Server;SoC", + "MetricName": "tma_info_io_write_bw" }, { - "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY", - "MetricName": "cpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + FP_ARITH_INST_RETIRED2.SCALAR + (cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@ + FP_ARITH_INST_RETIRED2.VECTOR))", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_iparith", + "MetricThreshold": "tma_info_iparith < 10", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." }, { - "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions", - "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY", - "MetricName": "loads_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per FP Arithmetic AMX operation (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / AMX_OPS_RETIRED.BF16", + "MetricGroup": "Flops;FpVector;InsType;Server", + "MetricName": "tma_info_iparith_amx_f16", + "MetricThreshold": "tma_info_iparith_amx_f16 < 10", + "PublicDescription": "Instructions per FP Arithmetic AMX operation (lower number means higher occurrence rate). Operations factored per matrices' sizes of the AMX instructions." }, { - "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions", - "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY", - "MetricName": "stores_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per Integer Arithmetic AMX operation (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / AMX_OPS_RETIRED.INT8", + "MetricGroup": "InsType;IntVector;Server", + "MetricName": "tma_info_iparith_amx_int8", + "MetricThreshold": "tma_info_iparith_amx_int8 < 10", + "PublicDescription": "Instructions per Integer Arithmetic AMX operation (lower number means higher occurrence rate). Operations factored per matrices' sizes of the AMX instructions." }, { - "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions", - "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY", - "MetricName": "l1d_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx128", + "MetricThreshold": "tma_info_iparith_avx128 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ", - "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY", - "MetricName": "l1d_demand_data_read_hits_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx256", + "MetricThreshold": "tma_info_iparith_avx256 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions", - "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY", - "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx512", + "MetricThreshold": "tma_info_iparith_avx512 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ", - "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY", - "MetricName": "l2_demand_data_read_hits_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_iparith_scalar_dp", + "MetricThreshold": "tma_info_iparith_scalar_dp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions", - "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY", - "MetricName": "l2_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_iparith_scalar_sp", + "MetricThreshold": "tma_info_iparith_scalar_sp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions", - "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricName": "l2_demand_data_read_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per a microcode Assist invocation", + "MetricExpr": "INST_RETIRED.ANY / cpu@ASSISTS.ANY\\,umask\\=0x1B@", + "MetricGroup": "Pipeline;Ret;Retire", + "MetricName": "tma_info_ipassist", + "MetricThreshold": "tma_info_ipassist < 100e3", + "PublicDescription": "Instructions per a microcode Assist invocation. See Assists tree node for details (lower number means higher occurrence rate)" }, { - "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions", - "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", - "MetricName": "l2_demand_code_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "tma_info_ipbranch", + "MetricThreshold": "tma_info_ipbranch < 8" }, { - "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", - "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA + UNC_CHA_TOR_INSERTS.IA_MISS_DRD + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF) / INST_RETIRED.ANY", - "MetricName": "llc_data_read_mpi_demand_plus_prefetch", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_clks", + "MetricGroup": "Ret;Summary", + "MetricName": "tma_info_ipc" }, { - "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", - "MetricExpr": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD / INST_RETIRED.ANY", - "MetricName": "llc_code_read_mpi_demand_plus_prefetch", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_ipcall", + "MetricThreshold": "tma_info_ipcall < 200" }, { - "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) in nano seconds", - "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD) * #num_packages)) * duration_time", - "MetricName": "llc_demand_data_read_miss_latency", - "ScaleUnit": "1ns" + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "tma_info_ipdsb_miss_ret", + "MetricThreshold": "tma_info_ipdsb_miss_ret < 50" }, { - "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to local memory in nano seconds", - "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL) * #num_packages)) * duration_time", - "MetricName": "llc_demand_data_read_miss_latency_for_local_requests", - "ScaleUnit": "1ns" + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "tma_info_ipfarbranch", + "MetricThreshold": "tma_info_ipfarbranch < 1e6" }, { - "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to remote memory in nano seconds", - "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE) * #num_packages)) * duration_time", - "MetricName": "llc_demand_data_read_miss_latency_for_remote_requests", - "ScaleUnit": "1ns" + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_flopc", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_ipflop", + "MetricThreshold": "tma_info_ipflop < 10" }, { - "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to Intel(R) Optane(TM) Persistent Memory(PMEM) in nano seconds", - "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM) * #num_packages)) * duration_time", - "MetricName": "llc_demand_data_read_miss_to_pmem_latency", - "ScaleUnit": "1ns" + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipload", + "MetricThreshold": "tma_info_ipload < 3" }, { - "BriefDescription": "Average latency of a last level cache (LLC) demand data read miss (read memory access) addressed to DRAM in nano seconds", - "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR) * #num_packages)) * duration_time", - "MetricName": "llc_demand_data_read_miss_to_dram_latency", - "ScaleUnit": "1ns" + "BriefDescription": "Instructions per retired mispredicts for conditional non-taken branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_NTAKEN", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_cond_ntaken", + "MetricThreshold": "tma_info_ipmisp_cond_ntaken < 200" }, { - "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions", - "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", - "MetricName": "itlb_2nd_level_mpi", - "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per retired mispredicts for conditional taken branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_cond_taken", + "MetricThreshold": "tma_info_ipmisp_cond_taken < 200" }, { - "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions", - "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY", - "MetricName": "itlb_2nd_level_large_page_mpi", - "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_indirect", + "MetricThreshold": "tma_info_ipmisp_indirect < 1e3" }, { - "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions", - "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", - "MetricName": "dtlb_2nd_level_load_mpi", - "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per retired mispredicts for return branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RET", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_ret", + "MetricThreshold": "tma_info_ipmisp_ret < 500" }, { - "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions", - "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY", - "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi", - "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "tma_info_ipmispredict", + "MetricThreshold": "tma_info_ipmispredict < 200" }, { - "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions", - "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", - "MetricName": "dtlb_2nd_level_store_mpi", - "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipstore", + "MetricThreshold": "tma_info_ipstore < 8" }, { - "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", - "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE)", - "MetricName": "numa_reads_addressed_to_local_dram", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", + "MetricGroup": "Prefetches", + "MetricName": "tma_info_ipswpf", + "MetricThreshold": "tma_info_ipswpf < 100" }, { - "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", - "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE)", - "MetricName": "numa_reads_addressed_to_remote_dram", - "ScaleUnit": "100%" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", + "MetricName": "tma_info_iptb", + "MetricThreshold": "tma_info_iptb < 13", + "PublicDescription": "Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_dsb_misses, tma_lcp" }, { - "BriefDescription": "Uncore operating frequency in GHz", - "MetricExpr": "UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTICKS) * #num_packages) / 1e9 / duration_time", - "MetricName": "uncore_frequency", - "ScaleUnit": "1GHz" + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "tma_info_instructions / BACLEARS.ANY", + "MetricGroup": "Fed", + "MetricName": "tma_info_ipunknown_branch" }, { - "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)", - "MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 7.111111111111111 / 1e6 / duration_time", - "MetricName": "upi_data_transmit_bw", - "ScaleUnit": "1MB/s" + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_jump" }, { - "BriefDescription": "DDR memory read bandwidth (MB/sec)", - "MetricExpr": "UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time", - "MetricName": "memory_bandwidth_read", - "ScaleUnit": "1MB/s" + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_cpi" }, { - "BriefDescription": "DDR memory write bandwidth (MB/sec)", - "MetricExpr": "UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time", - "MetricName": "memory_bandwidth_write", - "ScaleUnit": "1MB/s" + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_utilization", + "MetricThreshold": "tma_info_kernel_utilization > 0.05" }, { - "BriefDescription": "DDR memory bandwidth (MB/sec)", - "MetricExpr": "(UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e6 / duration_time", - "MetricName": "memory_bandwidth_total", - "ScaleUnit": "1MB/s" + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw" }, { - "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory read bandwidth (MB/sec)", - "MetricExpr": "UNC_M_PMM_RPQ_INSERTS * 64 / 1e6 / duration_time", - "MetricName": "pmem_memory_bandwidth_read", - "ScaleUnit": "1MB/s" + "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "tma_info_l1d_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw_1t" }, { - "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory write bandwidth (MB/sec)", - "MetricExpr": "UNC_M_PMM_WPQ_INSERTS * 64 / 1e6 / duration_time", - "MetricName": "pmem_memory_bandwidth_write", - "ScaleUnit": "1MB/s" + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l1mpki" }, { - "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) memory bandwidth (MB/sec)", - "MetricExpr": "(UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS) * 64 / 1e6 / duration_time", - "MetricName": "pmem_memory_bandwidth_total", - "ScaleUnit": "1MB/s" + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l1mpki_load" }, { - "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.", - "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e6 / duration_time", - "MetricName": "io_bandwidth_disk_or_network_writes", - "ScaleUnit": "1MB/s" + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw" }, { - "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.", - "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR) * 64 / 1e6 / duration_time", - "MetricName": "io_bandwidth_disk_or_network_reads", - "ScaleUnit": "1MB/s" + "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "tma_info_l2_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw_1t" }, { - "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue", - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)", - "MetricName": "percent_uops_delivered_from_decoded_icache", - "ScaleUnit": "100%" + "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction", + "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / tma_info_instructions", + "MetricGroup": "L2Evicts;Mem;Server", + "MetricName": "tma_info_l2_evictions_nonsilent_pki" }, { - "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue", - "MetricExpr": "IDQ.MITE_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)", - "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline", - "ScaleUnit": "100%" + "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)", + "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / tma_info_instructions", + "MetricGroup": "L2Evicts;Mem;Server", + "MetricName": "tma_info_l2_evictions_silent_pki" }, { - "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue", - "MetricExpr": "IDQ.MS_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS + LSD.UOPS)", - "MetricName": "percent_uops_delivered_from_microcode_sequencer", - "ScaleUnit": "100%" + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2hpki_all" }, { - "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.", - "MetricExpr": "UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1e6 / duration_time", - "MetricName": "llc_miss_local_memory_bandwidth_read", - "ScaleUnit": "1MB/s" + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2hpki_load" }, { - "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.", - "MetricExpr": "UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1e6 / duration_time", - "MetricName": "llc_miss_local_memory_bandwidth_write", - "ScaleUnit": "1MB/s" + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Backend;CacheMisses;Mem", + "MetricName": "tma_info_l2mpki" }, { - "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.", - "MetricExpr": "UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1e6 / duration_time", - "MetricName": "llc_miss_remote_memory_bandwidth_read", - "ScaleUnit": "1MB/s" + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem;Offcore", + "MetricName": "tma_info_l2mpki_all" }, { - "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to remote memory.", - "MetricExpr": "UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1e6 / duration_time", - "MetricName": "llc_miss_remote_memory_bandwidth_write", - "ScaleUnit": "1MB/s" + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction", + "MetricExpr": "1e3 * FRONTEND_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss", + "MetricName": "tma_info_l2mpki_code" }, { - "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / slots", - "MetricGroup": "PGO;TopdownL1;tma_L1_group;tma_L1_group", - "MetricName": "tma_frontend_bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", - "ScaleUnit": "100%" + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction", + "MetricExpr": "1e3 * L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss", + "MetricName": "tma_info_l2mpki_code_all" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", - "MetricExpr": "topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / slots", - "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_latency", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.", - "ScaleUnit": "100%" + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2mpki_load" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", - "MetricExpr": "ICACHE_DATA.STALLS / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_icache_misses", - "ScaleUnit": "100%" + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_l3_cache_access_bw" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.", - "MetricExpr": "ICACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_itlb_misses", - "ScaleUnit": "100%" + "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_l3_cache_access_bw", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_l3_cache_access_bw_1t" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", - "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + tma_unknown_branches", - "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_branch_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.", - "ScaleUnit": "100%" + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ", - "MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) / max(1 - (tma_frontend_bound + topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)), 0) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group", - "MetricName": "tma_mispredicts_resteers", - "ScaleUnit": "100%" + "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_l3_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw_1t" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ", - "MetricExpr": "(1 - topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) / max(1 - (tma_frontend_bound + topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)), 0)) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group", - "MetricName": "tma_clears_resteers", - "ScaleUnit": "100%" + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l3mpki" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", - "MetricExpr": "INT_MISC.UNKNOWN_BRANCH_CYCLES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", - "MetricName": "tma_unknown_branches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit).", - "ScaleUnit": "100%" + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore", + "MetricName": "tma_info_load_l2_miss_latency" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_dsb_switches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", - "ScaleUnit": "100%" + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,cmask\\=1@", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_load_l2_mlp" }, { - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", - "MetricExpr": "DECODE.LCP / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_lcp", - "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", - "ScaleUnit": "100%" + "BriefDescription": "Average Latency for L3 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore", + "MetricName": "tma_info_load_l3_miss_latency" }, { - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", - "MetricExpr": "3 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_ms_switches", - "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", - "ScaleUnit": "100%" + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_ANY", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "tma_info_load_miss_real_latency" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", - "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)", - "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_bandwidth", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", - "ScaleUnit": "100%" + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_load_stlb_mpki" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", - "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / CPU_CLK_UNHALTED.DISTRIBUTED / 2", - "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", - "MetricName": "tma_mite", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", - "ScaleUnit": "100%" + "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]", + "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / uncore_cha_0@event\\=0x1@", + "MetricGroup": "Mem;MemoryLat;Server;SoC", + "MetricName": "tma_info_mem_dram_read_latency", + "PublicDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches" }, { - "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", - "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=0x1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=0x2@) / CPU_CLK_UNHALTED.DISTRIBUTED", - "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group", - "MetricName": "tma_decoder0_alone", - "ScaleUnit": "100%" + "BriefDescription": "Average number of parallel data read requests to external memory", + "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@thresh\\=1@", + "MetricGroup": "Mem;MemoryBW;SoC", + "MetricName": "tma_info_mem_parallel_reads", + "PublicDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", - "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / CPU_CLK_UNHALTED.DISTRIBUTED / 2", - "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", - "MetricName": "tma_dsb", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", - "ScaleUnit": "100%" + "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]", + "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / uncore_cha_0@event\\=0x1@", + "MetricGroup": "Mem;MemoryLat;Server;SoC", + "MetricName": "tma_info_mem_pmm_read_latency", + "PublicDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches" }, { - "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", - "MetricExpr": "max(1 - (tma_frontend_bound + topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)), 0)", - "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group", - "MetricName": "tma_bad_speculation", - "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", - "ScaleUnit": "100%" + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds)", + "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (tma_info_socket_clks / duration_time)", + "MetricGroup": "Mem;MemoryLat;SoC", + "MetricName": "tma_info_mem_read_latency", + "PublicDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", - "MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * slots", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_branch_mispredicts", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks", + "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))", + "MetricGroup": "Mem;MemoryBW;Offcore;tma_issueBW", + "MetricName": "tma_info_memory_bandwidth", + "MetricThreshold": "tma_info_memory_bandwidth > 20", + "PublicDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_mem_bandwidth, tma_sq_full" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", - "MetricExpr": "max(0, tma_bad_speculation - topdown\\-br\\-mispredict / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound))", - "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_machine_clears", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", + "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))", + "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", + "MetricName": "tma_info_memory_data_tlbs", + "MetricThreshold": "tma_info_memory_data_tlbs > 20", + "PublicDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store" }, { - "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", - "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * slots", - "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group", - "MetricName": "tma_backend_bound", - "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)", + "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound))", + "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", + "MetricName": "tma_info_memory_latency", + "MetricThreshold": "tma_info_memory_latency > 20", + "PublicDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches). Related metrics: tma_l3_hit_latency, tma_mem_latency" }, { - "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", - "MetricExpr": "topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * slots", - "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_memory_bound", - "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", + "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", + "MetricName": "tma_info_mispredictions", + "MetricThreshold": "tma_info_mispredictions > 20", + "PublicDescription": "Total pipeline cost of Branch Misprediction related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_branch_misprediction_cost, tma_mispredicts_resteers" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", - "MetricExpr": "max((EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS) / CPU_CLK_UNHALTED.THREAD, 0)", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_l1_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.", - "ScaleUnit": "100%" + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBW;MemoryBound", + "MetricName": "tma_info_mlp", + "PublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", - "MetricExpr": "min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS, 0)) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_dtlb_load", - "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", + "MetricExpr": "1 - (tma_info_cond_nt + tma_info_cond_tk + tma_info_callret + tma_info_jump)", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_other_branches" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", - "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss", - "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", - "MetricName": "tma_load_stlb_hit", - "ScaleUnit": "100%" + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (4 * tma_info_core_clks)", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_page_walks_utilization", + "MetricThreshold": "tma_info_page_walks_utilization > 0.5" }, { - "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", - "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", - "MetricName": "tma_load_stlb_miss", - "ScaleUnit": "100%" + "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]", + "MetricExpr": "64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW;Server;SoC", + "MetricName": "tma_info_pmm_read_bw" }, { - "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", - "MetricExpr": "min(13 * LD_BLOCKS.STORE_FORWARD / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_store_fwd_blk", - "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", - "ScaleUnit": "100%" + "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]", + "MetricExpr": "64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW;Server;SoC", + "MetricName": "tma_info_pmm_write_bw" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", - "MetricExpr": "min((16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_lock_latency", - "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.", - "ScaleUnit": "100%" + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "MetricExpr": "tma_retiring * tma_info_slots / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "tma_info_retire" }, { - "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ", - "MetricExpr": "min(Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_split_loads", - "ScaleUnit": "100%" + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "TOPDOWN.SLOTS", + "MetricGroup": "TmaL1;tma_L1_group", + "MetricName": "tma_info_slots" }, { - "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", - "MetricExpr": "L1D_PEND_MISS.FB_FULL / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_fb_full", - "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", + "MetricExpr": "(tma_info_slots / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)", + "MetricGroup": "SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_slots_utilization" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", - "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_l2_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)", + "MetricGroup": "SMT", + "MetricName": "tma_info_smt_2t_utilization" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", - "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_l3_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.", - "ScaleUnit": "100%" + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "uncore_cha_0@event\\=0x1@", + "MetricGroup": "SoC", + "MetricName": "tma_info_socket_clks" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", - "MetricExpr": "min(((28 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + (27 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", - "MetricName": "tma_contested_accesses", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.", - "ScaleUnit": "100%" + "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_store_stlb_mpki" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", - "MetricExpr": "min((27 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", - "MetricName": "tma_data_sharing", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.", - "ScaleUnit": "100%" + "BriefDescription": "Estimated fraction of retirement-cycles dealing with repeat instructions", + "MetricExpr": "INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "tma_info_strings_cycles", + "MetricThreshold": "tma_info_strings_cycles > 0.1" }, { - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", - "MetricExpr": "min((12 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group", - "MetricName": "tma_l3_hit_latency", - "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", - "ScaleUnit": "100%" + "BriefDescription": "Tera Integer (matrix) Operations Per Second", + "MetricExpr": "8 * AMX_OPS_RETIRED.INT8 / 1e12 / duration_time", + "MetricGroup": "Cor;HPC;IntVector;Server", + "MetricName": "tma_info_tiops" }, { - "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", - "MetricExpr": "(XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group", - "MetricName": "tma_sq_full", - "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.", - "ScaleUnit": "100%" + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "tma_info_clks / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power", + "MetricName": "tma_info_turbo_utilization" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", - "MetricExpr": "min(MEMORY_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD - tma_pmm_bound, 1)", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_dram_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.", - "ScaleUnit": "100%" + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "tma_retiring * tma_info_slots / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire", + "MetricName": "tma_info_uoppi", + "MetricThreshold": "tma_info_uoppi > 1.05" }, { - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group", - "MetricName": "tma_mem_bandwidth", - "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", - "ScaleUnit": "100%" + "BriefDescription": "Cross-socket Ultra Path Interconnect (UPI) data transmit bandwidth for data only [MB / sec]", + "MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 64 / 9 / 1e6", + "MetricGroup": "Server;SoC", + "MetricName": "tma_info_upi_data_transmit_bw" }, { - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to memory bandwidth Allocation feature (RDT's memory bandwidth throttling).", - "MetricExpr": "INT_MISC.MBA_STALLS / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryBW;Offcore;Server;TopdownL5;tma_L5_group;tma_mem_bandwidth_group", - "MetricName": "tma_mba_stalls", - "ScaleUnit": "100%" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "tma_retiring * tma_info_slots / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "tma_info_uptb", + "MetricThreshold": "tma_info_uptb < 9" }, { - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CPU_CLK_UNHALTED.THREAD - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group", - "MetricName": "tma_mem_latency", - "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric approximates arithmetic Integer (Int) matrix uops fraction the CPU has retired (aggregated across all supported Int datatypes in AMX engine)", + "MetricExpr": "cpu@AMX_OPS_RETIRED.INT8\\,cmask\\=1@ / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;HPC;IntVector;Pipeline;Server;TopdownL4;tma_L4_group;tma_int_operations_group", + "MetricName": "tma_int_amx", + "MetricThreshold": "tma_int_amx > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic Integer (Int) matrix uops fraction the CPU has retired (aggregated across all supported Int datatypes in AMX engine). Refer to AMX_Busy and TIOPs metrics for actual AMX utilization and Int performance, resp.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory", - "MetricExpr": "min((66.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 12 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_local_dram", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", + "BriefDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired)", + "MetricExpr": "tma_int_vector_128b + tma_int_vector_256b + tma_shuffles + tma_int_amx", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_int_operations", + "MetricThreshold": "tma_int_operations > 0.1 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired). Vector/Matrix Int operations and shuffles are counted. Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory", - "MetricExpr": "min((131 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 12 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_remote_dram", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", + "BriefDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired", + "MetricExpr": "(INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128) / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group;tma_issue2P", + "MetricName": "tma_int_vector_128b", + "MetricThreshold": "tma_int_vector_128b > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6)", + "PublicDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues", - "MetricExpr": "min(((120 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 12 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + (120 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 12 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_remote_cache", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", + "BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired", + "MetricExpr": "(INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256) / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group;tma_issue2P", + "MetricName": "tma_int_vector_256b", + "MetricThreshold": "tma_int_vector_256b > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6)", + "PublicDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a", - "MetricExpr": "min(((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (MEMORY_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0), 1)", - "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_pmm_bound", - "PublicDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module. ", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", + "MetricExpr": "ICACHE_TAG.STALLS / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", - "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_store_bound", - "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.", + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", + "MetricExpr": "max((EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.STALLS_L1D_MISS) / tma_info_clks, 0)", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group", + "MetricName": "tma_l1_bound", + "MetricThreshold": "tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", - "MetricExpr": "(MEM_STORE_RETIRED.L2_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_store_latency", - "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", + "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.STALLS_L2_MISS) / tma_info_clks", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l2_bound", + "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", - "MetricExpr": "min(28 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_false_sharing", - "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ", + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", + "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.STALLS_L3_MISS) / tma_info_clks", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l3_bound", + "MetricThreshold": "tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents rate of split store accesses", - "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CPU_CLK_UNHALTED.DISTRIBUTED", - "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_split_stores", - "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.", + "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", + "MetricExpr": "33 * tma_info_average_frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group", + "MetricName": "tma_l3_hit_latency", + "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_memory_latency, tma_mem_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores", - "MetricExpr": "min(9 * OCR.STREAMING_WR.ANY_RESPONSE / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_streaming_stores", - "PublicDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck.", + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", + "MetricExpr": "DECODE.LCP / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_lcp", + "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", - "MetricExpr": "min((7 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CPU_CLK_UNHALTED.DISTRIBUTED, 1)", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_dtlb_store", - "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", + "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_light_operations", + "MetricThreshold": "tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", - "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss", - "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", - "MetricName": "tma_store_stlb_hit", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", + "MetricExpr": "UOPS_DISPATCHED.PORT_2_3_10 / (3 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_load_op_utilization", + "MetricThreshold": "tma_load_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3_10", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", - "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CPU_CLK_UNHALTED.DISTRIBUTED", - "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", - "MetricName": "tma_store_stlb_miss", + "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", + "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", + "MetricName": "tma_load_stlb_hit", + "MetricThreshold": "tma_load_stlb_hit > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", - "MetricExpr": "max(0, topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)) + 0 * slots", - "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_core_bound", - "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + }, + { + "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", + "MetricName": "tma_load_stlb_miss", + "MetricThreshold": "tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", - "MetricExpr": "ARITH.DIVIDER_ACTIVE / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", - "MetricName": "tma_divider", - "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory", + "MetricExpr": "71 * tma_info_average_frequency * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group", + "MetricName": "tma_local_dram", + "MetricThreshold": "tma_local_dram > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", - "MetricExpr": "((cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS else (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@) / CPU_CLK_UNHALTED.THREAD) + 0 * slots", - "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", - "MetricName": "tma_ports_utilization", - "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / tma_info_clks", + "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group", + "MetricName": "tma_lock_latency", + "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ / CPU_CLK_UNHALTED.THREAD + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_0", - "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", + "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)", + "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations", - "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group", - "MetricName": "tma_serializing_operation", - "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to memory bandwidth Allocation feature (RDT's memory bandwidth throttling).", + "MetricExpr": "INT_MISC.MBA_STALLS / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;Server;TopdownL5;tma_L5_group;tma_mem_bandwidth_group", + "MetricName": "tma_mba_stalls", + "MetricThreshold": "tma_mba_stalls > 0.1 & (tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions.", - "MetricExpr": "CPU_CLK_UNHALTED.PAUSE / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group", - "MetricName": "tma_slow_pause", + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW", + "MetricName": "tma_mem_bandwidth", + "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_info_memory_bandwidth, tma_sq_full", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions.", - "MetricExpr": "min(13 * MISC2_RETIRED.LFENCE / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group", - "MetricName": "tma_memory_fence", + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_clks - tma_mem_bandwidth", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat", + "MetricName": "tma_mem_latency", + "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_info_memory_latency, tma_l3_hit_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued", - "MetricExpr": "min(160 * ASSISTS.SSE_AVX_MIX / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group", - "MetricName": "tma_mixing_vectors", - "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", + "MetricExpr": "topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_slots", + "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_memory_bound", + "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the Advanced Matrix Extensions (AMX) execution engine was busy with tile (arithmetic) operations", - "MetricExpr": "EXE.AMX_BUSY / CPU_CLK_UNHALTED.DISTRIBUTED", - "MetricGroup": "Compute;HPC;Server;TopdownL5;tma_L5_group;tma_ports_utilized_0_group", - "MetricName": "tma_amx_busy", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to LFENCE Instructions.", + "MetricExpr": "13 * MISC2_RETIRED.LFENCE / tma_info_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group", + "MetricName": "tma_memory_fence", + "MetricThreshold": "tma_memory_fence > 0.05 & (tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))))", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "EXE_ACTIVITY.1_PORTS_UTIL / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_1", - "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", + "MetricExpr": "tma_light_operations * MEM_UOP_RETIRED.ANY / (tma_retiring * tma_info_slots)", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_memory_operations", + "MetricThreshold": "tma_memory_operations > 0.1 & tma_light_operations > 0.6", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "EXE_ACTIVITY.2_PORTS_UTIL / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_2", - "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", + "MetricExpr": "UOPS_RETIRED.MS / tma_info_slots", + "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS", + "MetricName": "tma_microcode_sequencer", + "MetricThreshold": "tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: UOPS_RETIRED.MS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", - "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_3m", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage", + "MetricExpr": "tma_branch_mispredicts / tma_bad_speculation * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks", + "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM", + "MetricName": "tma_mispredicts_resteers", + "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_branch_misprediction_cost, tma_info_mispredictions", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5_11 + UOPS_DISPATCHED.PORT_6) / (5 * CPU_CLK_UNHALTED.DISTRIBUTED)", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", - "MetricName": "tma_alu_op_utilization", + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", + "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / tma_info_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_mite", + "MetricThreshold": "tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 6 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", - "MetricExpr": "UOPS_DISPATCHED.PORT_0 / CPU_CLK_UNHALTED.DISTRIBUTED", - "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group", - "MetricName": "tma_port_0", + "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued", + "MetricExpr": "160 * ASSISTS.SSE_AVX_MIX / tma_info_clks", + "MetricGroup": "TopdownL5;tma_L5_group;tma_issueMV;tma_ports_utilized_0_group", + "MetricName": "tma_mixing_vectors", + "MetricThreshold": "tma_mixing_vectors > 0.05", + "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic. Related metrics: tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", - "MetricExpr": "UOPS_DISPATCHED.PORT_1 / CPU_CLK_UNHALTED.DISTRIBUTED", - "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", - "MetricName": "tma_port_1", + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", + "MetricExpr": "3 * cpu@UOPS_RETIRED.MS\\,cmask\\=1\\,edge@ / (tma_retiring * tma_info_slots / UOPS_ISSUED.ANY) / tma_info_clks", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", + "MetricName": "tma_ms_switches", + "MetricThreshold": "tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: FRONTEND_RETIRED.MS_FLOWS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", - "MetricExpr": "UOPS_DISPATCHED.PORT_6 / CPU_CLK_UNHALTED.DISTRIBUTED", - "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", - "MetricName": "tma_port_6", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused", + "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED) / (tma_retiring * tma_info_slots)", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_non_fused_branches", + "MetricThreshold": "tma_non_fused_branches > 0.1 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", - "MetricExpr": "UOPS_DISPATCHED.PORT_2_3_10 / (3 * CPU_CLK_UNHALTED.DISTRIBUTED)", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", - "MetricName": "tma_load_op_utilization", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions", + "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (tma_retiring * tma_info_slots)", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_nop_instructions", + "MetricThreshold": "tma_nop_instructions > 0.1 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", - "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * CPU_CLK_UNHALTED.DISTRIBUTED)", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", - "MetricName": "tma_store_op_utilization", + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes", + "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_int_operations + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions))", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_other_light_ops", + "MetricThreshold": "tma_other_light_ops > 0.3 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", "ScaleUnit": "100%" }, { - "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * slots", - "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group", - "MetricName": "tma_retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ", + "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults", + "MetricExpr": "99 * ASSISTS.PAGE_FAULT / tma_info_slots", + "MetricGroup": "TopdownL5;tma_L5_group;tma_assists_group", + "MetricName": "tma_page_faults", + "MetricThreshold": "tma_page_faults > 0.05", + "PublicDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults. A Page Fault may apply on first application access to a memory page. Note operating system handling of page faults accounts for the majority of its cost.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", - "MetricExpr": "max(0, topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)) + 0 * slots", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group", - "MetricName": "tma_light_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.", + "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a", + "MetricExpr": "((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_clks) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0)", + "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_pmm_bound", + "MetricThreshold": "tma_pmm_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a. IXP) memory by loads, PMM stands for Persistent Memory Module.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", - "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD + tma_fp_scalar + tma_fp_vector + tma_fp_amx", - "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_fp_arith", - "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", + "MetricExpr": "UOPS_DISPATCHED.PORT_0 / tma_info_core_clks", + "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_0", + "MetricThreshold": "tma_port_0 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric serves as an approximation of legacy x87 usage", - "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD + 0 * slots", - "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", - "MetricName": "tma_x87_use", - "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", + "MetricExpr": "UOPS_DISPATCHED.PORT_1 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_1", + "MetricThreshold": "tma_port_1 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + FP_ARITH_INST_RETIRED2.SCALAR) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)", - "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group", - "MetricName": "tma_fp_scalar", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", + "MetricExpr": "UOPS_DISPATCHED.PORT_6 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_6", + "MetricThreshold": "tma_port_6 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", - "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.VECTOR) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)", - "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group", - "MetricName": "tma_fp_vector", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", + "MetricExpr": "((cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS) + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@)) / tma_info_clks if ARITH.DIV_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=0xc@) / tma_info_clks)", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_ports_utilization", + "MetricThreshold": "tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", - "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)", - "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", - "MetricName": "tma_fp_vector_128b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.", + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ / tma_info_clks + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS) / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_0", + "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", - "MetricExpr": "min((FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)", - "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", - "MetricName": "tma_fp_vector_256b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.", + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "EXE_ACTIVITY.1_PORTS_UTIL / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_1", + "MetricThreshold": "tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL. Related metrics: tma_l1_bound", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors", - "MetricExpr": "min((FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots), 1)", - "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", - "MetricName": "tma_fp_vector_512b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.", + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "EXE_ACTIVITY.2_PORTS_UTIL / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_2", + "MetricThreshold": "tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) matrix uops fraction the CPU has retired (aggregated across all supported FP datatypes in AMX engine)", - "MetricExpr": "cpu@AMX_OPS_RETIRED.BF16\\,cmask\\=0x1@ / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)", - "MetricGroup": "Compute;Flops;HPC;Pipeline;Server;TopdownL4;tma_L4_group;tma_fp_arith_group", - "MetricName": "tma_fp_amx", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) matrix uops fraction the CPU has retired (aggregated across all supported FP datatypes in AMX engine). Refer to AMX_Busy and GFLOPs metrics for actual AMX utilization and FP performance, resp.", + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_3m", + "MetricThreshold": "tma_ports_utilized_3m > 0.7 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired)", - "MetricExpr": "tma_int_vector_128b + tma_int_vector_256b + tma_shuffles", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_int_operations", - "PublicDescription": "This metric represents overall Integer (Int) select operations fraction the CPU has executed (retired). Vector/Matrix Int operations and shuffles are counted. Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain.", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues", + "MetricExpr": "(135.5 * tma_info_average_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + 135.5 * tma_info_average_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_issueSyncxn;tma_mem_latency_group", + "MetricName": "tma_remote_cache", + "MetricThreshold": "tma_remote_cache > 0.05 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents 128-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.", - "MetricExpr": "(INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)", - "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group", - "MetricName": "tma_int_vector_128b", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory", + "MetricExpr": "149 * tma_info_average_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", + "MetricName": "tma_remote_dram", + "MetricThreshold": "tma_remote_dram > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents 256-bit vector Integer ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the CPU has retired.", - "MetricExpr": "(INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 + INT_VEC_RETIRED.VNNI_256) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)", - "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group", - "MetricName": "tma_int_vector_256b", + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic Integer (Int) matrix uops fraction the CPU has retired (aggregated across all supported Int datatypes in AMX engine)", - "MetricExpr": "cpu@AMX_OPS_RETIRED.INT8\\,cmask\\=0x1@ / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)", - "MetricGroup": "Compute;HPC;IntVector;Pipeline;Server;TopdownL4;tma_L4_group;tma_int_operations_group", - "MetricName": "tma_int_amx", - "PublicDescription": "This metric approximates arithmetic Integer (Int) matrix uops fraction the CPU has retired (aggregated across all supported Int datatypes in AMX engine). Refer to AMX_Busy and TIOPs metrics for actual AMX utilization and Int performance, resp.", + "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations", + "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL5;tma_L5_group;tma_issueSO;tma_ports_utilized_0_group", + "MetricName": "tma_serializing_operation", + "MetricThreshold": "tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD. Related metrics: tma_ms_switches", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Shuffle (cross \"vector lane\" data transfers) uops fraction the CPU has retired.", - "MetricExpr": "INT_VEC_RETIRED.SHUFFLES / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)", + "MetricExpr": "INT_VEC_RETIRED.SHUFFLES / (tma_retiring * tma_info_slots)", "MetricGroup": "HPC;Pipeline;TopdownL4;tma_L4_group;tma_int_operations_group", "MetricName": "tma_shuffles", + "MetricThreshold": "tma_shuffles > 0.1 & (tma_int_operations > 0.1 & tma_light_operations > 0.6)", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", - "MetricExpr": "max(0, topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)) * MEM_UOP_RETIRED.ANY / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_memory_operations", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions", + "MetricExpr": "CPU_CLK_UNHALTED.PAUSE / tma_info_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group", + "MetricName": "tma_slow_pause", + "MetricThreshold": "tma_slow_pause > 0.05 & (tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: CPU_CLK_UNHALTED.PAUSE_INST", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions", - "MetricExpr": "max(0, topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)) * INST_RETIRED.MACRO_FUSED / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_fused_instructions", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.", + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", + "MetricExpr": "tma_info_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_split_loads", + "MetricThreshold": "tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused", - "MetricExpr": "max(0, topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)) * (BR_INST_RETIRED.ALL_BRANCHES - INST_RETIRED.MACRO_FUSED) / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_non_fused_branches", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", + "BriefDescription": "This metric represents rate of split store accesses", + "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / tma_info_core_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group", + "MetricName": "tma_split_stores", + "MetricThreshold": "tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions", - "MetricExpr": "max(0, topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)) * INST_RETIRED.NOP / (topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * slots)", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_nop_instructions", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", + "MetricExpr": "(XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS) / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group", + "MetricName": "tma_sq_full", + "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_info_memory_bandwidth, tma_mem_bandwidth", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", - "MetricExpr": "max(0, max(0, topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)) - (tma_fp_arith + tma_int_operations + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions))", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_other_light_ops", + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", + "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_store_bound", + "MetricThreshold": "tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences", - "MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * slots", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group", - "MetricName": "tma_heavy_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.", + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", + "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_store_fwd_blk", + "MetricThreshold": "tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops", - "MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - tma_microcode_sequencer", - "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group", - "MetricName": "tma_few_uops_instructions", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.", + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", + "MetricExpr": "(MEM_STORE_RETIRED.L2_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_clks", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group", + "MetricName": "tma_store_latency", + "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", - "MetricExpr": "UOPS_RETIRED.MS / slots", - "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group", - "MetricName": "tma_microcode_sequencer", - "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_store_op_utilization", + "MetricThreshold": "tma_store_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations. Sample with: UOPS_DISPATCHED.PORT_7_8", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", - "MetricExpr": "min(100 * cpu@ASSISTS.ANY\\,umask\\=0x1B@ / slots, 1)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", - "MetricName": "tma_assists", - "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.", + "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", + "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", + "MetricName": "tma_store_stlb_hit", + "MetricThreshold": "tma_store_stlb_hit > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults", - "MetricExpr": "99 * ASSISTS.PAGE_FAULT / slots", - "MetricGroup": "TopdownL5;tma_L5_group;tma_assists_group", - "MetricName": "tma_page_faults", - "PublicDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Page Faults. A Page Fault may apply on first application access to a memory page. Note operating system handling of page faults accounts for the majority of its cost.", + "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", + "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / tma_info_core_clks", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", + "MetricName": "tma_store_stlb_miss", + "MetricThreshold": "tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists", - "MetricExpr": "30 * ASSISTS.FP / slots", - "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", - "MetricName": "tma_fp_assists", - "PublicDescription": "This metric roughly estimates fraction of slots the CPU retired uops as a result of handing Floating Point (FP) Assists. FP Assist may apply when working with very small floating point values (so-called denormals).", + "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores", + "MetricExpr": "9 * OCR.STREAMING_WR.ANY_RESPONSE / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueSmSt;tma_store_bound_group", + "MetricName": "tma_streaming_stores", + "MetricThreshold": "tma_streaming_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck. Sample with: OCR.STREAMING_WR.ANY_RESPONSE. Related metrics: tma_fb_full", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists. ", - "MetricExpr": "63 * ASSISTS.SSE_AVX_MIX / slots", - "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", - "MetricName": "tma_avx_assists", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", + "MetricExpr": "INT_MISC.UNKNOWN_BRANCH_CYCLES / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", + "MetricName": "tma_unknown_branches", + "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit). Sample with: FRONTEND_RETIRED.UNKNOWN_BRANCH", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", - "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", - "MetricName": "tma_cisc", - "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", + "BriefDescription": "This metric serves as an approximation of legacy x87 usage", + "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD", + "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_x87_use", + "MetricThreshold": "tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", "ScaleUnit": "100%" }, { - "BriefDescription": "C1 residency percent per core", - "MetricExpr": "cstate_core@c1\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C1_Core_Residency", + "BriefDescription": "Percentage of cycles in aborted transactions.", + "MetricExpr": "max(cpu@cycles\\-t@ - cpu@cycles\\-ct@, 0) / cycles", + "MetricGroup": "transaction", + "MetricName": "tsx_aborted_cycles", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per core", - "MetricExpr": "cstate_core@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Core_Residency", - "ScaleUnit": "100%" + "BriefDescription": "Number of cycles within a transaction divided by the number of elisions.", + "MetricExpr": "cpu@cycles\\-t@ / cpu@el\\-start@", + "MetricGroup": "transaction", + "MetricName": "tsx_cycles_per_elision", + "ScaleUnit": "1cycles / elision" }, { - "BriefDescription": "C2 residency percent per package", - "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C2_Pkg_Residency", - "ScaleUnit": "100%" + "BriefDescription": "Number of cycles within a transaction divided by the number of transactions.", + "MetricExpr": "cpu@cycles\\-t@ / cpu@tx\\-start@", + "MetricGroup": "transaction", + "MetricName": "tsx_cycles_per_transaction", + "ScaleUnit": "1cycles / transaction" }, { - "BriefDescription": "C6 residency percent per package", - "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Pkg_Residency", + "BriefDescription": "Percentage of cycles within a transaction region.", + "MetricExpr": "cpu@cycles\\-t@ / cycles", + "MetricGroup": "transaction", + "MetricName": "tsx_transactional_cycles", "ScaleUnit": "100%" } ] diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-other.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-other.json index fd253e3276df..11c037e8291d 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-other.json @@ -2832,6 +2832,16 @@ "UMask": "0x80", "Unit": "IIO" }, + { + "BriefDescription": "Read request for 4 bytes made by IIO Part0-7 to Memory", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00ff", + "UMask": "0x4", + "Unit": "IIO" + }, { "BriefDescription": "Read request for 4 bytes made by IIO Part0 to Memory", "EventCode": "0x83", @@ -2920,6 +2930,16 @@ "UMask": "0x4", "Unit": "IIO" }, + { + "BriefDescription": "Write request of 4 bytes made by IIO Part0-7 to Memory", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00ff", + "UMask": "0x1", + "Unit": "IIO" + }, { "BriefDescription": "Write request of 4 bytes made by IIO Part0 to Memory", "EventCode": "0x83", @@ -4038,6 +4058,46 @@ "PublicDescription": "FlowQ Generated Prefetch : Count cases where FlowQ causes spawn of Prefetch to iMC/SMI3 target", "Unit": "M3UPI" }, + { + "BriefDescription": "All CAS commands issued", + "EventCode": "0x05", + "EventName": "UNC_MCHBM_CAS_COUNT.ALL", + "PerPkg": "1", + "UMask": "0xff", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Read CAS commands issued (regular and underfill)", + "EventCode": "0x05", + "EventName": "UNC_MCHBM_CAS_COUNT.RD", + "PerPkg": "1", + "UMask": "0xcf", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Regular read CAS commands issued (does not include underfills)", + "EventCode": "0x05", + "EventName": "UNC_MCHBM_CAS_COUNT.RD_REG", + "PerPkg": "1", + "UMask": "0xc1", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Underfill read CAS commands issued", + "EventCode": "0x05", + "EventName": "UNC_MCHBM_CAS_COUNT.RD_UNDERFILL", + "PerPkg": "1", + "UMask": "0xc4", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Write CAS commands issued", + "EventCode": "0x05", + "EventName": "UNC_MCHBM_CAS_COUNT.WR", + "PerPkg": "1", + "UMask": "0xf0", + "Unit": "MCHBM" + }, { "BriefDescription": "UPI Clockticks", "EventCode": "0x01", -- cgit v1.2.3-58-ga151 From c3fdd79d6161559b2b3dd111e593842e65ccbd8b Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:24 -0800 Subject: perf vendor events intel: Refresh silvermont events Update the silvermont events from 14 to 15. Generation was done using https://github.com/intel/perfmon. The most notable change is in corrections to event descriptions. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-28-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- tools/perf/pmu-events/arch/x86/silvermont/frontend.json | 2 +- tools/perf/pmu-events/arch/x86/silvermont/pipeline.json | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 1f611a7dbdda..d1d40d0f2b2c 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -23,7 +23,7 @@ GenuineIntel-6-1[AEF],v3,nehalemep,core GenuineIntel-6-2E,v3,nehalemex,core GenuineIntel-6-2A,v18,sandybridge,core GenuineIntel-6-(8F|CF),v1.11,sapphirerapids,core -GenuineIntel-6-(37|4A|4C|4D|5A),v14,silvermont,core +GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v53,skylake,core GenuineIntel-6-55-[01234],v1.28,skylakex,core GenuineIntel-6-86,v1.20,snowridgex,core diff --git a/tools/perf/pmu-events/arch/x86/silvermont/frontend.json b/tools/perf/pmu-events/arch/x86/silvermont/frontend.json index c35da10f7133..cd6ed3f59e26 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/frontend.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/frontend.json @@ -11,7 +11,7 @@ "BriefDescription": "Counts the number of JCC baclears", "EventCode": "0xE6", "EventName": "BACLEARS.COND", - "PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.COND event counts the number of JCC (Jump on Condtional Code) baclears.", + "PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.COND event counts the number of JCC (Jump on Conditional Code) baclears.", "SampleAfterValue": "200003", "UMask": "0x10" }, diff --git a/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json b/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json index 59f6116a7eae..2d4214bf9e39 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json @@ -228,7 +228,7 @@ "BriefDescription": "Counts the number of cycles when no uops are allocated, the IQ is empty, and no other condition is blocking allocation.", "EventCode": "0xCA", "EventName": "NO_ALLOC_CYCLES.NOT_DELIVERED", - "PublicDescription": "The NO_ALLOC_CYCLES.NOT_DELIVERED event is used to measure front-end inefficiencies, i.e. when front-end of the machine is not delivering micro-ops to the back-end and the back-end is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into micro-ops (uops) in machine understandable format and putting them into a micro-op queue to be consumed by back end. The back-end then takes these micro-ops, allocates the required resources. When all resources are ready, micro-ops are executed. If the back-end is not ready to accept micro-ops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more UOPS. This event counts the cycles only when back-end is requesting more uops and front-end is not able to provide them. Some examples of conditions that cause front-end efficiencies are: Icache misses, ITLB misses, and decoder restrictions that limit the the front-end bandwidth.", + "PublicDescription": "The NO_ALLOC_CYCLES.NOT_DELIVERED event is used to measure front-end inefficiencies, i.e. when front-end of the machine is not delivering micro-ops to the back-end and the back-end is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into micro-ops (uops) in machine understandable format and putting them into a micro-op queue to be consumed by back end. The back-end then takes these micro-ops, allocates the required resources. When all resources are ready, micro-ops are executed. If the back-end is not ready to accept micro-ops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more UOPS. This event counts the cycles only when back-end is requesting more uops and front-end is not able to provide them. Some examples of conditions that cause front-end efficiencies are: Icache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth.", "SampleAfterValue": "200003", "UMask": "0x50" }, -- cgit v1.2.3-58-ga151 From 9d9675bb411b08bc6c5bb2f399ee497f5880b551 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:25 -0800 Subject: perf vendor events intel: Refresh skylake events Update the skylake events from 53 to 54. Generation was done using https://github.com/intel/perfmon. Notable changes are updated events and event descriptions, TMA metrics are updated to version 4.5, TMA info metrics are renamed from their node name to be lower case and prefixed by tma_info_ and MetricThreshold expressions are added, smi_cost and transaction metric groups are added replicating existing hard coded metrics in stat-shadow. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-29-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- tools/perf/pmu-events/arch/x86/skylake/cache.json | 25 +- .../perf/pmu-events/arch/x86/skylake/frontend.json | 8 +- tools/perf/pmu-events/arch/x86/skylake/other.json | 1 + .../perf/pmu-events/arch/x86/skylake/pipeline.json | 16 + .../pmu-events/arch/x86/skylake/skl-metrics.json | 1877 +++++++++++--------- .../pmu-events/arch/x86/skylake/uncore-other.json | 1 + 7 files changed, 1115 insertions(+), 815 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index d1d40d0f2b2c..22aa63f90f89 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -24,7 +24,7 @@ GenuineIntel-6-2E,v3,nehalemex,core GenuineIntel-6-2A,v18,sandybridge,core GenuineIntel-6-(8F|CF),v1.11,sapphirerapids,core GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core -GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v53,skylake,core +GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v54,skylake,core GenuineIntel-6-55-[01234],v1.28,skylakex,core GenuineIntel-6-86,v1.20,snowridgex,core GenuineIntel-6-8[CD],v1.08,tigerlake,core diff --git a/tools/perf/pmu-events/arch/x86/skylake/cache.json b/tools/perf/pmu-events/arch/x86/skylake/cache.json index 1538ddb5752f..0080ac27b899 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/cache.json +++ b/tools/perf/pmu-events/arch/x86/skylake/cache.json @@ -72,6 +72,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF", + "Deprecated": "1", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.USELESS_PREF", "SampleAfterValue": "200003", @@ -232,20 +233,22 @@ "UMask": "0x4f" }, { - "BriefDescription": "All retired load instructions.", + "BriefDescription": "Retired load instructions.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.ALL_LOADS", "PEBS": "1", + "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.", "SampleAfterValue": "2000003", "UMask": "0x81" }, { - "BriefDescription": "All retired store instructions.", + "BriefDescription": "Retired store instructions.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.ALL_STORES", "PEBS": "1", + "PublicDescription": "Counts all retired store instructions.", "SampleAfterValue": "2000003", "UMask": "0x82" }, @@ -443,7 +446,7 @@ "UMask": "0x80" }, { - "BriefDescription": "Cacheable and noncachaeble code read requests", + "BriefDescription": "Cacheable and non-cacheable code read requests", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "PublicDescription": "Counts both cacheable and non-cacheable code read requests.", @@ -551,15 +554,7 @@ "UMask": "0x4" }, { - "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code readshave any response type.", + "BriefDescription": "Counts all demand code reads have any response type.", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -946,7 +941,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data readshave any response type.", + "BriefDescription": "Counts demand data reads have any response type.", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1333,7 +1328,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)have any response type.", + "BriefDescription": "Counts all demand data writes (RFOs) have any response type.", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1720,7 +1715,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts any other requestshave any response type.", + "BriefDescription": "Counts any other requests have any response type.", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/skylake/frontend.json b/tools/perf/pmu-events/arch/x86/skylake/frontend.json index 13ccf50db43d..04f08e4d2402 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/frontend.json +++ b/tools/perf/pmu-events/arch/x86/skylake/frontend.json @@ -322,7 +322,7 @@ "UMask": "0x4" }, { - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", @@ -331,7 +331,7 @@ "UMask": "0x30" }, { - "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -340,7 +340,7 @@ "UMask": "0x10" }, { - "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", "PublicDescription": "Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.", @@ -358,7 +358,7 @@ "UMask": "0x30" }, { - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.", diff --git a/tools/perf/pmu-events/arch/x86/skylake/other.json b/tools/perf/pmu-events/arch/x86/skylake/other.json index 9f3a9dffb807..d75d53279b4e 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/other.json +++ b/tools/perf/pmu-events/arch/x86/skylake/other.json @@ -8,6 +8,7 @@ "UMask": "0x1" }, { + "BriefDescription": "MEMORY_DISAMBIGUATION.HISTORY_RESET", "EventCode": "0x09", "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", "SampleAfterValue": "2000003", diff --git a/tools/perf/pmu-events/arch/x86/skylake/pipeline.json b/tools/perf/pmu-events/arch/x86/skylake/pipeline.json index cf35a535c2f6..2c827d806554 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/skylake/pipeline.json @@ -93,6 +93,22 @@ "SampleAfterValue": "400009", "UMask": "0x10" }, + { + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0xff" + }, + { + "BriefDescription": "Speculative mispredicted indirect branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.INDIRECT", + "PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, { "BriefDescription": "All mispredicted macro branch instructions retired.", "EventCode": "0xC5", diff --git a/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json b/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json index 972d3744c2c8..a6d212b349f5 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json @@ -1,1197 +1,1484 @@ [ { - "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", - "MetricGroup": "PGO;TopdownL1;tma_L1_group", - "MetricName": "tma_frontend_bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", - "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS", - "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_latency", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", + "BriefDescription": "C2 residency percent per package", + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C2_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses", - "MetricExpr": "(ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@) / CLKS", - "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_icache_misses", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", + "BriefDescription": "C3 residency percent per core", + "MetricExpr": "cstate_core@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", - "MetricExpr": "ICACHE_64B.IFTAG_STALL / CLKS", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_itlb_misses", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", + "BriefDescription": "C3 residency percent per package", + "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", - "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CLKS + tma_unknown_branches", - "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_branch_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group", - "MetricName": "tma_mispredicts_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES", + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears", - "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS", - "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group", - "MetricName": "tma_clears_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES", + "BriefDescription": "C7 residency percent per core", + "MetricExpr": "cstate_core@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", - "MetricExpr": "9 * BACLEARS.ANY / CLKS", - "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_branch_resteers_group", - "MetricName": "tma_unknown_branches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit). Sample with: BACLEARS.ANY", + "BriefDescription": "C7 residency percent per package", + "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_dsb_switches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS", - "ScaleUnit": "100%" + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "tma_info_socket_clks / #num_dies / duration_time / 1e9", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" }, { - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", - "MetricExpr": "ILD_STALL.LCP / CLKS", - "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_lcp", - "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", + "BriefDescription": "Percentage of cycles spent in System Management Interrupts.", + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", + "MetricGroup": "smi", + "MetricName": "smi_cycles", + "MetricThreshold": "smi_cycles > 0.1", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", - "MetricExpr": "2 * IDQ.MS_SWITCHES / CLKS", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_ms_switches", - "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES", - "ScaleUnit": "100%" + "BriefDescription": "Number of SMI interrupts.", + "MetricExpr": "msr@smi@", + "MetricGroup": "smi", + "MetricName": "smi_num", + "ScaleUnit": "1SMI#" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", - "MetricExpr": "tma_frontend_bound - tma_fetch_latency", - "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_bandwidth", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS", + "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", + "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_4k_aliasing", + "MetricThreshold": "tma_4k_aliasing > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", - "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2", - "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_group", - "MetricName": "tma_mite", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / tma_info_slots", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_alu_op_utilization", + "MetricThreshold": "tma_alu_op_utilization > 0.6", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", - "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) / CORE_CLKS", - "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_mite_group", - "MetricName": "tma_decoder0_alone", + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", + "MetricExpr": "100 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / tma_info_slots", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_assists", + "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", - "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2", - "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group", - "MetricName": "tma_dsb", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", + "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_backend_bound", + "MetricThreshold": "tma_backend_bound > 0.2", + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", "ScaleUnit": "100%" }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", - "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", + "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", + "MetricThreshold": "tma_bad_speculation > 0.15", "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", + "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredicts_resteers", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", - "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_machine_clears", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", + "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks + tma_unknown_branches", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_branch_resteers", + "MetricThreshold": "tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", "ScaleUnit": "100%" }, { - "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", - "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_backend_bound", - "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", + "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_cisc", + "MetricThreshold": "tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound", - "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_memory_bound", - "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears", + "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks", + "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC", + "MetricName": "tma_clears_resteers", + "MetricThreshold": "tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", - "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CLKS, 0)", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l1_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(18.5 * tma_info_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM + 16.5 * tma_info_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_contested_accesses", + "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", - "MetricExpr": "min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / CLKS", - "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_dtlb_load", - "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS", + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_backend_bound - tma_memory_bound", + "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", - "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss", - "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group", - "MetricName": "tma_load_stlb_hit", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "16.5 * tma_info_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_data_sharing", + "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", - "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CLKS", - "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group", - "MetricName": "tma_load_stlb_miss", + "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", + "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) / tma_info_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_issueD0;tma_mite_group", + "MetricName": "tma_decoder0_alone", + "MetricThreshold": "tma_decoder0_alone > 0.1 & (tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35))", + "PublicDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder. Related metrics: tma_few_uops_instructions", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", - "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_store_fwd_blk", - "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", + "MetricExpr": "ARITH.DIVIDER_ACTIVE / tma_info_clks", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_divider", + "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", - "MetricExpr": "(12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (9 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS", - "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_lock_latency", - "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS", + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks - tma_l2_bound", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_dram_bound", + "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", - "MetricExpr": "Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_split_loads", - "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS", + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", + "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / tma_info_core_clks / 2", + "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_dsb", + "MetricThreshold": "tma_dsb > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", - "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_4k_aliasing", - "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_clks", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_dsb_switches", + "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", - "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / CLKS", - "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_fb_full", - "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).", + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group", + "MetricName": "tma_dtlb_load", + "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store, tma_info_memory_data_tlbs", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", - "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS)", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l2_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS", + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", + "MetricExpr": "(9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group", + "MetricName": "tma_dtlb_store", + "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, tma_info_memory_data_tlbs", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / CLKS", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l3_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", + "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "22 * tma_info_average_frequency * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group", + "MetricName": "tma_false_sharing", + "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", - "MetricExpr": "(18.5 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM + 16.5 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_contested_accesses", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS", + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "tma_info_load_miss_real_latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / tma_info_clks", + "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricName": "tma_fb_full", + "MetricThreshold": "tma_fb_full > 0.3", + "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_dram_bw_use, tma_info_memory_bandwidth, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", - "MetricExpr": "16.5 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_data_sharing", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS", + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", + "MetricExpr": "tma_frontend_bound - tma_fetch_latency", + "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", + "MetricName": "tma_fetch_bandwidth", + "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", - "MetricExpr": "6.5 * Average_Frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS", - "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_l3_hit_latency", - "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", + "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / tma_info_slots", + "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_latency", + "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", - "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_sq_full", - "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops", + "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer", + "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueD0", + "MetricName": "tma_few_uops_instructions", + "MetricThreshold": "tma_few_uops_instructions > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions. Related metrics: tma_decoder0_alone", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", - "MetricExpr": "CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS - tma_l2_bound", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_dram_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS", + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", + "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_fp_arith", + "MetricThreshold": "tma_fp_arith > 0.2 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group", - "MetricName": "tma_mem_bandwidth", - "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", + "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_scalar", + "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group", - "MetricName": "tma_mem_latency", - "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@ / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_vector", + "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", - "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CLKS", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_store_bound", - "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS", + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_128b", + "MetricThreshold": "tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", - "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group", - "MetricName": "tma_store_latency", - "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_256b", + "MetricThreshold": "tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", - "MetricExpr": "22 * Average_Frequency * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group", - "MetricName": "tma_false_sharing", - "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_slots", + "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.15", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents rate of split store accesses", - "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CORE_CLKS", - "MetricGroup": "TopdownL4;tma_store_bound_group", - "MetricName": "tma_split_stores", - "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions", + "MetricExpr": "tma_light_operations * UOPS_RETIRED.MACRO_FUSED / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_fused_instructions", + "MetricThreshold": "tma_fused_instructions > 0.1 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", - "MetricExpr": "(9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CORE_CLKS", - "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group", - "MetricName": "tma_dtlb_store", - "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences", + "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / tma_info_slots", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_heavy_operations", + "MetricThreshold": "tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", - "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss", - "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group", - "MetricName": "tma_store_stlb_hit", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses", + "MetricExpr": "(ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@) / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_icache_misses", + "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", - "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS", - "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group", - "MetricName": "tma_store_stlb_miss", - "ScaleUnit": "100%" + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "tma_info_turbo_utilization * TSC / 1e9 / duration_time", + "MetricGroup": "Power;Summary", + "MetricName": "tma_info_average_frequency" }, { - "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", - "MetricExpr": "tma_backend_bound - tma_memory_bound", - "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_core_bound", - "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB;tma_issueBC", + "MetricName": "tma_info_big_code", + "MetricThreshold": "tma_info_big_code > 20", + "PublicDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses). Related metrics: tma_info_branching_overhead" }, { - "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", - "MetricExpr": "ARITH.DIVIDER_ACTIVE / CLKS", - "MetricGroup": "TopdownL3;tma_core_bound_group", - "MetricName": "tma_divider", - "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE", - "ScaleUnit": "100%" + "BriefDescription": "Branch instructions per taken branch.", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_bptkbranch" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", - "MetricExpr": "((EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CLKS)", - "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group", - "MetricName": "tma_ports_utilization", - "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", - "ScaleUnit": "100%" + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_slots / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts;tma_issueBM", + "MetricName": "tma_info_branch_misprediction_cost", + "PublicDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_branch_mispredicts, tma_info_mispredictions, tma_mispredicts_resteers" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_NONE / 2 if #SMT_on else CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_0", - "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "MetricExpr": "100 * ((BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL)) / tma_info_slots)", + "MetricGroup": "Ret;tma_issueBC", + "MetricName": "tma_info_branching_overhead", + "MetricThreshold": "tma_info_branching_overhead > 10", + "PublicDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls). Related metrics: tma_info_big_code" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations", - "MetricExpr": "PARTIAL_RAT_STALLS.SCOREBOARD / CLKS", - "MetricGroup": "TopdownL5;tma_ports_utilized_0_group", - "MetricName": "tma_serializing_operation", - "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: PARTIAL_RAT_STALLS.SCOREBOARD", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_callret" }, { - "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued", - "MetricExpr": "CLKS * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY", - "MetricGroup": "TopdownL5;tma_ports_utilized_0_group", - "MetricName": "tma_mixing_vectors", - "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", - "ScaleUnit": "100%" + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline", + "MetricName": "tma_info_clks" }, { - "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2) / 2 if #SMT_on else EXE_ACTIVITY.1_PORTS_UTIL) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_1", - "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", - "ScaleUnit": "100%" + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Fed;MemoryTLB", + "MetricName": "tma_info_code_stlb_mpki" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3) / 2 if #SMT_on else EXE_ACTIVITY.2_PORTS_UTIL) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_2", - "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "tma_info_cond_nt" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", - "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_3) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_3m", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of branches that are taken conditionals", + "MetricExpr": "(BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "tma_info_cond_tk" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_alu_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if tma_info_smt_2t_utilization > 0.5 else 0)", + "MetricGroup": "Cor;SMT", + "MetricName": "tma_info_core_bound_likely", + "MetricThreshold": "tma_info_core_bound_likely > 0.5" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) Sample with: UOPS_DISPATCHED_PORT.PORT_0", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS", - "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_0", - "ScaleUnit": "100%" + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else tma_info_clks))", + "MetricGroup": "SMT", + "MetricName": "tma_info_core_clks" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_1", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_1", - "ScaleUnit": "100%" + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_core_clks", + "MetricGroup": "Ret;SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_coreipc" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) Sample with: UOPS_DISPATCHED.PORT_5", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_5", - "ScaleUnit": "100%" + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / tma_info_ipc", + "MetricGroup": "Mem;Pipeline", + "MetricName": "tma_info_cpi" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) Sample with: UOPS_DISPATCHED_PORT.PORT_6", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_6", - "ScaleUnit": "100%" + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "HPC;Summary", + "MetricName": "tma_info_cpu_utilization" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations Sample with: UOPS_DISPATCHED.PORT_2_3", - "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_load_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_data_l2_mlp" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_2", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_load_op_utilization_group", - "MetricName": "tma_port_2", - "ScaleUnit": "100%" + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;tma_issueBW", + "MetricName": "tma_info_dram_bw_use", + "PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_info_memory_bandwidth, tma_mem_bandwidth, tma_sq_full" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads) Sample with: UOPS_DISPATCHED_PORT.PORT_3", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_load_op_utilization_group", - "MetricName": "tma_port_3", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", + "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", + "MetricName": "tma_info_dsb_coverage", + "MetricThreshold": "tma_info_dsb_coverage < 0.7 & tma_info_ipc / 4 > 0.35", + "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_misses, tma_info_iptb, tma_lcp" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", - "MetricExpr": "tma_port_4", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_store_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))", + "MetricGroup": "DSBmiss;Fed;tma_issueFB", + "MetricName": "tma_info_dsb_misses", + "MetricThreshold": "tma_info_dsb_misses > 10", + "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_iptb, tma_lcp" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data) Sample with: UOPS_DISPATCHED_PORT.PORT_4", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_store_op_utilization_group", - "MetricName": "tma_port_4", - "ScaleUnit": "100%" + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHES.COUNT", + "MetricGroup": "DSBmiss", + "MetricName": "tma_info_dsb_switch_cost" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address) Sample with: UOPS_DISPATCHED_PORT.PORT_7", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_store_op_utilization_group", - "MetricName": "tma_port_7", - "ScaleUnit": "100%" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-thread", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "tma_info_execute" }, { - "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", - "ScaleUnit": "100%" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "tma_info_execute_per_issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", - "MetricExpr": "tma_retiring - tma_heavy_operations", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_light_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", - "ScaleUnit": "100%" + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_fb_hpki" }, { - "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", - "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", - "MetricGroup": "HPC;TopdownL3;tma_light_operations_group", - "MetricName": "tma_fp_arith", - "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", - "ScaleUnit": "100%" + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_fetch_upc" }, { - "BriefDescription": "This metric serves as an approximation of legacy x87 usage", - "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD", - "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_x87_use", - "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", - "ScaleUnit": "100%" + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / tma_info_core_clks", + "MetricGroup": "Flops;Ret", + "MetricName": "tma_info_flopc" }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_fp_scalar", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@) / (2 * tma_info_core_clks)", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_fp_arith_utilization", + "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", - "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_fp_vector", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Giga Floating Point Operations Per Second", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_gflops", + "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", - "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group", - "MetricName": "tma_fp_vector_128b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck", + "MetricExpr": "100 * (tma_fetch_latency * tma_icache_misses / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", + "MetricGroup": "Fed;FetchLat;IcMiss;tma_issueFL", + "MetricName": "tma_info_ic_misses", + "MetricThreshold": "tma_info_ic_misses > 5", + "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck. Related metrics: " }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", - "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group", - "MetricName": "tma_fp_vector_256b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Average Latency for L1 instruction cache misses", + "MetricExpr": "ICACHE_16B.IFDATA_STALL / cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@ + 2", + "MetricGroup": "Fed;FetchLat;IcMiss", + "MetricName": "tma_info_icache_miss_latency" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", - "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group", - "MetricName": "tma_memory_operations", - "ScaleUnit": "100%" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", + "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", + "MetricName": "tma_info_ilp" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions", - "MetricExpr": "tma_light_operations * UOPS_RETIRED.MACRO_FUSED / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group", - "MetricName": "tma_fused_instructions", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_big_code", + "MetricGroup": "Fed;FetchBW;Frontend", + "MetricName": "tma_info_instruction_fetch_bw", + "MetricThreshold": "tma_info_instruction_fetch_bw > 20" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused", - "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group", - "MetricName": "tma_non_fused_branches", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", - "ScaleUnit": "100%" + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;tma_L1_group", + "MetricName": "tma_info_instructions", + "PublicDescription": "Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions", - "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group", - "MetricName": "tma_nop_instructions", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0x3c@)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_iparith", + "MetricThreshold": "tma_info_iparith < 10", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." }, { - "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", - "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions))", - "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group", - "MetricName": "tma_other_light_ops", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx128", + "MetricThreshold": "tma_info_iparith_avx128 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences", - "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / SLOTS", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_heavy_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx256", + "MetricThreshold": "tma_info_iparith_avx256 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops", - "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer", - "MetricGroup": "TopdownL3;tma_heavy_operations_group", - "MetricName": "tma_few_uops_instructions", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_iparith_scalar_dp", + "MetricThreshold": "tma_info_iparith_scalar_dp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS", - "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group", - "MetricName": "tma_microcode_sequencer", - "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_iparith_scalar_sp", + "MetricThreshold": "tma_info_iparith_scalar_sp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", - "MetricExpr": "100 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / SLOTS", - "MetricGroup": "TopdownL4;tma_microcode_sequencer_group", - "MetricName": "tma_assists", - "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "tma_info_ipbranch", + "MetricThreshold": "tma_info_ipbranch < 8" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", - "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", - "MetricGroup": "TopdownL4;tma_microcode_sequencer_group", - "MetricName": "tma_cisc", - "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_clks", + "MetricGroup": "Ret;Summary", + "MetricName": "tma_info_ipc" }, { - "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", - "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "Mispredictions" + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_ipcall", + "MetricThreshold": "tma_info_ipcall < 200" }, { - "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks", - "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "Memory_Bandwidth" + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "tma_info_ipdsb_miss_ret", + "MetricThreshold": "tma_info_ipdsb_miss_ret < 50" }, { - "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)", - "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound))", - "MetricGroup": "Mem;MemoryLat;Offcore", - "MetricName": "Memory_Latency" + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "tma_info_ipfarbranch", + "MetricThreshold": "tma_info_ipfarbranch < 1e6" }, { - "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", - "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency)))", - "MetricGroup": "Mem;MemoryTLB;Offcore", - "MetricName": "Memory_Data_TLBs" + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_ipflop", + "MetricThreshold": "tma_info_ipflop < 10" }, { - "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", - "MetricExpr": "100 * ((BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)", - "MetricGroup": "Ret", - "MetricName": "Branching_Overhead" + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipload", + "MetricThreshold": "tma_info_ipload < 3" }, { - "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", - "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", - "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB", - "MetricName": "Big_Code" + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "tma_info_instructions / (UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * cpu@BR_MISP_EXEC.ALL_BRANCHES\\,umask\\=0xE4@)", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_indirect", + "MetricThreshold": "tma_info_ipmisp_indirect < 1e3" }, { - "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", - "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code", - "MetricGroup": "Fed;FetchBW;Frontend", - "MetricName": "Instruction_Fetch_BW" + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "tma_info_ipmispredict", + "MetricThreshold": "tma_info_ipmispredict < 200" }, { - "BriefDescription": "Instructions Per Cycle (per Logical Processor)", - "MetricExpr": "INST_RETIRED.ANY / CLKS", - "MetricGroup": "Ret;Summary", - "MetricName": "IPC" + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipstore", + "MetricThreshold": "tma_info_ipstore < 8" }, { - "BriefDescription": "Uops Per Instruction", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Ret;Retire", - "MetricName": "UPI" + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", + "MetricGroup": "Prefetches", + "MetricName": "tma_info_ipswpf", + "MetricThreshold": "tma_info_ipswpf < 100" }, { "BriefDescription": "Instruction per taken branch", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW", - "MetricName": "UpTB" + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", + "MetricName": "tma_info_iptb", + "MetricThreshold": "tma_info_iptb < 9", + "PublicDescription": "Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_dsb_misses, tma_lcp" }, { - "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / IPC", - "MetricGroup": "Mem;Pipeline", - "MetricName": "CPI" + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "tma_info_instructions / BACLEARS.ANY", + "MetricGroup": "Fed", + "MetricName": "tma_info_ipunknown_branch" }, { - "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Pipeline", - "MetricName": "CLKS" + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_jump" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", - "MetricExpr": "4 * CORE_CLKS", - "MetricGroup": "tma_L1_group", - "MetricName": "SLOTS" + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_cpi" }, { - "BriefDescription": "The ratio of Executed- by Issued-Uops", - "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", - "MetricGroup": "Cor;Pipeline", - "MetricName": "Execute_per_Issue", - "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_utilization", + "MetricThreshold": "tma_info_kernel_utilization > 0.05" }, { - "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS", - "MetricGroup": "Ret;SMT;tma_L1_group", - "MetricName": "CoreIPC" + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw" }, { - "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / CORE_CLKS", - "MetricGroup": "Flops;Ret", - "MetricName": "FLOPc" + "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "tma_info_l1d_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw_1t" }, { - "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)) / (2 * CORE_CLKS)", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "FP_Arith_Utilization", - "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l1mpki" }, { - "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", - "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", - "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", - "MetricName": "ILP" + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l1mpki_load" }, { - "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", - "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)", - "MetricGroup": "Cor;SMT", - "MetricName": "Core_Bound_Likely" + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw" }, { - "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", - "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))", - "MetricGroup": "SMT", - "MetricName": "CORE_CLKS" + "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "tma_info_l2_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw_1t" }, { - "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", - "MetricGroup": "InsType", - "MetricName": "IpLoad" + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2hpki_all" }, { - "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", - "MetricGroup": "InsType", - "MetricName": "IpStore" + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2hpki_load" }, { - "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Fed;InsType", - "MetricName": "IpBranch" + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Backend;CacheMisses;Mem", + "MetricName": "tma_info_l2mpki" }, { - "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "IpCall" + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem;Offcore", + "MetricName": "tma_info_l2mpki_all" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", - "MetricName": "IpTB" + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction", + "MetricExpr": "1e3 * FRONTEND_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss", + "MetricName": "tma_info_l2mpki_code" }, { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "BpTkBranch" + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction", + "MetricExpr": "1e3 * L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss", + "MetricName": "tma_info_l2mpki_code_all" }, { - "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", - "MetricGroup": "Flops;InsType", - "MetricName": "IpFLOP" + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2mpki_load" }, { - "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE))", - "MetricGroup": "Flops;InsType", - "MetricName": "IpArith", - "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_l3_cache_access_bw" }, { - "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", - "MetricGroup": "Flops;FpScalar;InsType", - "MetricName": "IpArith_Scalar_SP", - "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_l3_cache_access_bw", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_l3_cache_access_bw_1t" }, { - "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", - "MetricGroup": "Flops;FpScalar;InsType", - "MetricName": "IpArith_Scalar_DP", - "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX128", - "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_l3_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw_1t" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX256", - "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l3mpki" }, { - "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", - "MetricGroup": "Prefetches", - "MetricName": "IpSWPF" + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore", + "MetricName": "tma_info_load_l2_miss_latency" }, { - "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary;tma_L1_group", - "MetricName": "Instructions" + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_load_l2_mlp" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "tma_info_load_miss_real_latency" + }, + { + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_load_stlb_mpki" + }, + { + "BriefDescription": "Average number of parallel data read requests to external memory", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.DATA_READ / UNC_ARB_TRK_OCCUPANCY.DATA_READ@thresh\\=1@", + "MetricGroup": "Mem;MemoryBW;SoC", + "MetricName": "tma_info_mem_parallel_reads", + "PublicDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches" + }, + { + "BriefDescription": "Average number of parallel requests to external memory", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", + "MetricGroup": "Mem;SoC", + "MetricName": "tma_info_mem_parallel_requests", + "PublicDescription": "Average number of parallel requests to external memory. Accounts for all requests" + }, + { + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds)", + "MetricExpr": "1e9 * (UNC_ARB_TRK_OCCUPANCY.DATA_READ / UNC_ARB_TRK_REQUESTS.DATA_READ) / (tma_info_socket_clks / duration_time)", + "MetricGroup": "Mem;MemoryLat;SoC", + "MetricName": "tma_info_mem_read_latency", + "PublicDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)" + }, + { + "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL", + "MetricGroup": "Mem;SoC", + "MetricName": "tma_info_mem_request_latency" + }, + { + "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))", + "MetricGroup": "Mem;MemoryBW;Offcore;tma_issueBW", + "MetricName": "tma_info_memory_bandwidth", + "MetricThreshold": "tma_info_memory_bandwidth > 20", + "PublicDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_mem_bandwidth, tma_sq_full" + }, + { + "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency)))", + "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", + "MetricName": "tma_info_memory_data_tlbs", + "MetricThreshold": "tma_info_memory_data_tlbs > 20", + "PublicDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store" + }, + { + "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound))", + "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", + "MetricName": "tma_info_memory_latency", + "MetricThreshold": "tma_info_memory_latency > 20", + "PublicDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches). Related metrics: tma_l3_hit_latency, tma_mem_latency" + }, + { + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", + "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", + "MetricName": "tma_info_mispredictions", + "MetricThreshold": "tma_info_mispredictions > 20", + "PublicDescription": "Total pipeline cost of Branch Misprediction related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_branch_misprediction_cost, tma_mispredicts_resteers" + }, + { + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBW;MemoryBound", + "MetricName": "tma_info_mlp", + "PublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING) / (2 * tma_info_core_clks)", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_page_walks_utilization", + "MetricThreshold": "tma_info_page_walks_utilization > 0.5" }, { "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@", "MetricGroup": "Pipeline;Ret", - "MetricName": "Retire" + "MetricName": "tma_info_retire" }, { - "BriefDescription": "", - "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", - "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", - "MetricName": "Execute" + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * tma_info_core_clks", + "MetricGroup": "TmaL1;tma_L1_group", + "MetricName": "tma_info_slots" }, { - "BriefDescription": "Average number of Uops issued by front-end when it issued something", - "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@", - "MetricGroup": "Fed;FetchBW", - "MetricName": "Fetch_UpC" + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", + "MetricGroup": "SMT", + "MetricName": "tma_info_smt_2t_utilization" }, { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "DSB;Fed;FetchBW", - "MetricName": "DSB_Coverage" + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "UNC_CLOCK.SOCKET", + "MetricGroup": "SoC", + "MetricName": "tma_info_socket_clks" }, { - "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHES.COUNT", - "MetricGroup": "DSBmiss", - "MetricName": "DSB_Switch_Cost" + "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_store_stlb_mpki" }, { - "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.", - "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))", - "MetricGroup": "DSBmiss;Fed", - "MetricName": "DSB_Misses" + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "tma_info_clks / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power", + "MetricName": "tma_info_turbo_utilization" }, { - "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", - "MetricGroup": "DSBmiss;Fed", - "MetricName": "IpDSB_Miss_Ret" + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire", + "MetricName": "tma_info_uoppi", + "MetricThreshold": "tma_info_uoppi > 1.05" }, { - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "tma_info_uptb", + "MetricThreshold": "tma_info_uptb < 6" }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BrMispredicts", - "MetricName": "Branch_Misprediction_Cost" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", + "MetricExpr": "ICACHE_64B.IFTAG_STALL / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of branches that are non-taken conditionals", - "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches;CodeGen;PGO", - "MetricName": "Cond_NT" + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", + "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / tma_info_clks, 0)", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group", + "MetricName": "tma_l1_bound", + "MetricThreshold": "tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of branches that are taken conditionals", - "MetricExpr": "(BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches;CodeGen;PGO", - "MetricName": "Cond_TK" + "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks)", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l2_bound", + "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of branches that are CALL or RET", - "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches", - "MetricName": "CallRet" + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / tma_info_clks", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l3_bound", + "MetricThreshold": "tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", - "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches", - "MetricName": "Jump" + "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", + "MetricExpr": "6.5 * tma_info_average_frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group", + "MetricName": "tma_l3_hit_latency", + "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_memory_latency, tma_mem_latency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)", - "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency" + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", + "MetricExpr": "ILD_STALL.LCP / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_lcp", + "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb", + "ScaleUnit": "100%" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "Mem;MemoryBW;MemoryBound", - "MetricName": "MLP" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", + "MetricExpr": "tma_retiring - tma_heavy_operations", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_light_operations", + "MetricThreshold": "tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", + "ScaleUnit": "100%" }, { - "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_load_op_utilization", + "MetricThreshold": "tma_load_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3", + "ScaleUnit": "100%" }, { - "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI_Load" + "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", + "MetricName": "tma_load_stlb_hit", + "MetricThreshold": "tma_load_stlb_hit > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Backend;CacheMisses;Mem", - "MetricName": "L2MPKI" + "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", + "MetricName": "tma_load_stlb_miss", + "MetricThreshold": "tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem;Offcore", - "MetricName": "L2MPKI_All" + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", + "MetricExpr": "(12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (9 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / tma_info_clks", + "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group", + "MetricName": "tma_lock_latency", + "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2MPKI_Load" + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", + "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", - "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2HPKI_All" + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW", + "MetricName": "tma_mem_bandwidth", + "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_info_memory_bandwidth, tma_sq_full", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2HPKI_Load" + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_clks - tma_mem_bandwidth", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat", + "MetricName": "tma_mem_latency", + "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_info_memory_latency, tma_l3_hit_latency", + "ScaleUnit": "100%" }, { - "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L3MPKI" + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound", + "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_memory_bound", + "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "FB_HPKI" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", + "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_memory_operations", + "MetricThreshold": "tma_memory_operations > 0.1 & tma_light_operations > 0.6", + "ScaleUnit": "100%" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING) / (2 * CORE_CLKS)", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "Page_Walks_Utilization" + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_slots", + "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS", + "MetricName": "tma_microcode_sequencer", + "MetricThreshold": "tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks", + "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM", + "MetricName": "tma_mispredicts_resteers", + "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_branch_misprediction_cost, tma_info_mispredictions", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", + "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / tma_info_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_mite", + "MetricThreshold": "tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" + "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued", + "MetricExpr": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY", + "MetricGroup": "TopdownL5;tma_L5_group;tma_issueMV;tma_ports_utilized_0_group", + "MetricName": "tma_mixing_vectors", + "MetricThreshold": "tma_mixing_vectors > 0.05", + "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic. Related metrics: tma_ms_switches", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW" + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", + "MetricExpr": "2 * IDQ.MS_SWITCHES / tma_info_clks", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", + "MetricName": "tma_ms_switches", + "MetricThreshold": "tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "L1D_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW_1T" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused", + "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_non_fused_branches", + "MetricThreshold": "tma_non_fused_branches > 0.1 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "L2_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW_1T" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions", + "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_nop_instructions", + "MetricThreshold": "tma_nop_instructions > 0.1 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW_1T" + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes", + "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions))", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_other_light_ops", + "MetricThreshold": "tma_other_light_ops > 0.3 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Access_BW", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW_1T" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / tma_info_core_clks", + "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_0", + "MetricThreshold": "tma_port_0 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED_PORT.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average CPU Utilization", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", - "MetricGroup": "HPC;Summary", - "MetricName": "CPU_Utilization" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_1", + "MetricThreshold": "tma_port_1 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", - "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time", - "MetricGroup": "Power;Summary", - "MetricName": "Average_Frequency" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", + "MetricName": "tma_port_2", + "MetricThreshold": "tma_port_2 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / 1e9 / duration_time", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs", - "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", + "MetricName": "tma_port_3", + "MetricThreshold": "tma_port_3 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_3", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average Frequency Utilization relative nominal frequency", - "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC", - "MetricGroup": "Power", - "MetricName": "Turbo_Utilization" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)", + "MetricExpr": "tma_store_op_utilization", + "MetricGroup": "TopdownL6;tma_L6_group;tma_issueSpSt;tma_store_op_utilization_group", + "MetricName": "tma_port_4", + "MetricThreshold": "tma_port_4 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Sample with: UOPS_DISPATCHED_PORT.PORT_4. Related metrics: tma_split_stores", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", - "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", - "MetricGroup": "SMT", - "MetricName": "SMT_2T_Utilization" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_5", + "MetricThreshold": "tma_port_5 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Sample with: UOPS_DISPATCHED.PORT_5. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "OS", - "MetricName": "Kernel_Utilization" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_6", + "MetricThreshold": "tma_port_6 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", - "MetricGroup": "OS", - "MetricName": "Kernel_CPI" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group", + "MetricName": "tma_port_7", + "MetricThreshold": "tma_port_7 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address). Sample with: UOPS_DISPATCHED_PORT.PORT_7", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", - "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1e6 / duration_time / 1e3", - "MetricGroup": "HPC;Mem;MemoryBW;SoC", - "MetricName": "DRAM_BW_Use" + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", + "MetricExpr": "((EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / tma_info_clks if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / tma_info_clks)", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_ports_utilization", + "MetricThreshold": "tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)", - "MetricExpr": "MEM_Parallel_Requests", - "MetricGroup": "Mem;SoC", - "MetricName": "MEM_Request_Latency" + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_NONE / 2 if #SMT_on else CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_core_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_0", + "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests", - "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL", - "MetricGroup": "Mem;SoC", - "MetricName": "MEM_Parallel_Requests" + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2) / 2 if #SMT_on else EXE_ACTIVITY.1_PORTS_UTIL) / tma_info_core_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_1", + "MetricThreshold": "tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Related metrics: tma_l1_bound", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches", - "MetricExpr": "1e9 * (UNC_ARB_TRK_OCCUPANCY.DATA_READ / UNC_ARB_TRK_REQUESTS.DATA_READ) / (Socket_CLKS / duration_time)", - "MetricGroup": "Mem;MemoryLat;SoC", - "MetricName": "MEM_Read_Latency" + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3) / 2 if #SMT_on else EXE_ACTIVITY.2_PORTS_UTIL) / tma_info_core_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_2", + "MetricThreshold": "tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", - "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.DATA_READ / UNC_ARB_TRK_OCCUPANCY.DATA_READ@thresh\\=1@", - "MetricGroup": "Mem;MemoryBW;SoC", - "MetricName": "MEM_Parallel_Reads" + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", + "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_3) / tma_info_core_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_3m", + "MetricThreshold": "tma_ports_utilized_3m > 0.7 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "ScaleUnit": "100%" }, { - "BriefDescription": "Socket actual clocks when any core is active on that socket", - "MetricExpr": "UNC_CLOCK.SOCKET", - "MetricGroup": "SoC", - "MetricName": "Socket_CLKS" + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", - "MetricGroup": "Branches;OS", - "MetricName": "IpFarBranch" + "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations", + "MetricExpr": "PARTIAL_RAT_STALLS.SCOREBOARD / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL5;tma_L5_group;tma_issueSO;tma_ports_utilized_0_group", + "MetricName": "tma_serializing_operation", + "MetricThreshold": "tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: PARTIAL_RAT_STALLS.SCOREBOARD. Related metrics: tma_ms_switches", + "ScaleUnit": "100%" }, { - "BriefDescription": "Uncore frequency per die [GHZ]", - "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9", - "MetricGroup": "SoC", - "MetricName": "UNCORE_FREQ" + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "tma_info_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_split_loads", + "MetricThreshold": "tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per core", - "MetricExpr": "cstate_core@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Core_Residency", + "BriefDescription": "This metric represents rate of split store accesses", + "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / tma_info_core_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group", + "MetricName": "tma_split_stores", + "MetricThreshold": "tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per core", - "MetricExpr": "cstate_core@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Core_Residency", + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", + "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group", + "MetricName": "tma_sq_full", + "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_info_memory_bandwidth, tma_mem_bandwidth", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per core", - "MetricExpr": "cstate_core@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Core_Residency", + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", + "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_store_bound", + "MetricThreshold": "tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "C2 residency percent per package", - "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C2_Pkg_Residency", + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", + "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_store_fwd_blk", + "MetricThreshold": "tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per package", - "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Pkg_Residency", + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_clks", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group", + "MetricName": "tma_store_latency", + "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per package", - "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Pkg_Residency", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / tma_info_core_clks", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_store_op_utilization", + "MetricThreshold": "tma_store_op_utilization > 0.6", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per package", - "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Pkg_Residency", + "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", + "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", + "MetricName": "tma_store_stlb_hit", + "MetricThreshold": "tma_store_stlb_hit > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", + "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / tma_info_core_clks", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", + "MetricName": "tma_store_stlb_miss", + "MetricThreshold": "tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", + "MetricExpr": "9 * BACLEARS.ANY / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", + "MetricName": "tma_unknown_branches", + "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit). Sample with: BACLEARS.ANY", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric serves as an approximation of legacy x87 usage", + "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD", + "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_x87_use", + "MetricThreshold": "tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of cycles in aborted transactions.", + "MetricExpr": "max(cpu@cycles\\-t@ - cpu@cycles\\-ct@, 0) / cycles", + "MetricGroup": "transaction", + "MetricName": "tsx_aborted_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Number of cycles within a transaction divided by the number of elisions.", + "MetricExpr": "cpu@cycles\\-t@ / cpu@el\\-start@", + "MetricGroup": "transaction", + "MetricName": "tsx_cycles_per_elision", + "ScaleUnit": "1cycles / elision" + }, + { + "BriefDescription": "Number of cycles within a transaction divided by the number of transactions.", + "MetricExpr": "cpu@cycles\\-t@ / cpu@tx\\-start@", + "MetricGroup": "transaction", + "MetricName": "tsx_cycles_per_transaction", + "ScaleUnit": "1cycles / transaction" + }, + { + "BriefDescription": "Percentage of cycles within a transaction region.", + "MetricExpr": "cpu@cycles\\-t@ / cycles", + "MetricGroup": "transaction", + "MetricName": "tsx_transactional_cycles", "ScaleUnit": "100%" } ] diff --git a/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json b/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json index e6d4cd625597..ef804df3f41e 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json @@ -33,6 +33,7 @@ "Unit": "ARB" }, { + "BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.ALL", "PerPkg": "1", -- cgit v1.2.3-58-ga151 From 100ee7c3de193df9e6fd54f9190aae73b1b43ee8 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:26 -0800 Subject: perf vendor events intel: Refresh skylakex metrics Update the skylakex events from 1.28 to 1.29 and metrics to TMA version 4.5. Generation was done using https://github.com/intel/perfmon. Notable changes are TMA info metrics are renamed from their node name to be lower case and prefixed by tma_info_, MetricThreshold expressions are added, "Sample with" documentation is added to many TMA metrics, smi_cost and transaction metric groups are added replicating existing hard coded metrics in stat-shadow. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-30-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- tools/perf/pmu-events/arch/x86/skylakex/cache.json | 8 +- .../pmu-events/arch/x86/skylakex/frontend.json | 8 +- .../pmu-events/arch/x86/skylakex/pipeline.json | 16 + .../pmu-events/arch/x86/skylakex/skx-metrics.json | 2097 ++++++++++---------- .../arch/x86/skylakex/uncore-memory.json | 2 +- .../pmu-events/arch/x86/skylakex/uncore-other.json | 96 +- .../pmu-events/arch/x86/skylakex/uncore-power.json | 6 +- 8 files changed, 1167 insertions(+), 1068 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 22aa63f90f89..07f0b4758a83 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -25,7 +25,7 @@ GenuineIntel-6-2A,v18,sandybridge,core GenuineIntel-6-(8F|CF),v1.11,sapphirerapids,core GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v54,skylake,core -GenuineIntel-6-55-[01234],v1.28,skylakex,core +GenuineIntel-6-55-[01234],v1.29,skylakex,core GenuineIntel-6-86,v1.20,snowridgex,core GenuineIntel-6-8[CD],v1.08,tigerlake,core GenuineIntel-6-2C,v3,westmereep-dp,core diff --git a/tools/perf/pmu-events/arch/x86/skylakex/cache.json b/tools/perf/pmu-events/arch/x86/skylakex/cache.json index 92da692795e7..d28d8822a51a 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/cache.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/cache.json @@ -234,20 +234,22 @@ "UMask": "0x4f" }, { - "BriefDescription": "All retired load instructions.", + "BriefDescription": "Retired load instructions.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.ALL_LOADS", "PEBS": "1", + "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.", "SampleAfterValue": "2000003", "UMask": "0x81" }, { - "BriefDescription": "All retired store instructions.", + "BriefDescription": "Retired store instructions.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.ALL_STORES", "PEBS": "1", + "PublicDescription": "Counts all retired store instructions.", "SampleAfterValue": "2000003", "UMask": "0x82" }, @@ -484,7 +486,7 @@ "UMask": "0x80" }, { - "BriefDescription": "Cacheable and noncachaeble code read requests", + "BriefDescription": "Cacheable and non-cacheable code read requests", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "PublicDescription": "Counts both cacheable and non-cacheable code read requests.", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/frontend.json b/tools/perf/pmu-events/arch/x86/skylakex/frontend.json index 13ccf50db43d..04f08e4d2402 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/frontend.json @@ -322,7 +322,7 @@ "UMask": "0x4" }, { - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", @@ -331,7 +331,7 @@ "UMask": "0x30" }, { - "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -340,7 +340,7 @@ "UMask": "0x10" }, { - "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", "PublicDescription": "Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.", @@ -358,7 +358,7 @@ "UMask": "0x30" }, { - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json b/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json index 64e1fe351333..0f06e314fe36 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json @@ -93,6 +93,22 @@ "SampleAfterValue": "400009", "UMask": "0x10" }, + { + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0xff" + }, + { + "BriefDescription": "Speculative mispredicted indirect branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.INDIRECT", + "PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, { "BriefDescription": "All mispredicted macro branch instructions retired.", "EventCode": "0xC5", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json b/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json index 1f8d60cce3ce..fa2f7f126a30 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json @@ -1,1497 +1,1570 @@ [ { - "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", - "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "Mispredictions" - }, - { - "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks", - "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "Memory_Bandwidth" - }, - { - "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)", - "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound))", - "MetricGroup": "Mem;MemoryLat;Offcore", - "MetricName": "Memory_Latency" - }, - { - "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", - "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency)))", - "MetricGroup": "Mem;MemoryTLB;Offcore", - "MetricName": "Memory_Data_TLBs" - }, - { - "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", - "MetricExpr": "100 * ((BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)", - "MetricGroup": "Ret", - "MetricName": "Branching_Overhead" - }, - { - "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", - "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", - "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB", - "MetricName": "Big_Code" - }, - { - "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", - "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code", - "MetricGroup": "Fed;FetchBW;Frontend", - "MetricName": "Instruction_Fetch_BW" - }, - { - "BriefDescription": "Instructions Per Cycle (per Logical Processor)", - "MetricExpr": "INST_RETIRED.ANY / CLKS", - "MetricGroup": "Ret;Summary", - "MetricName": "IPC" - }, - { - "BriefDescription": "Uops Per Instruction", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Ret;Retire", - "MetricName": "UPI" - }, - { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW", - "MetricName": "UpTB" + "BriefDescription": "C2 residency percent per package", + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C2_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / IPC", - "MetricGroup": "Mem;Pipeline", - "MetricName": "CPI" + "BriefDescription": "C3 residency percent per core", + "MetricExpr": "cstate_core@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Core_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Pipeline", - "MetricName": "CLKS" + "BriefDescription": "C3 residency percent per package", + "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", - "MetricExpr": "4 * CORE_CLKS", - "MetricGroup": "tma_L1_group", - "MetricName": "SLOTS" + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "The ratio of Executed- by Issued-Uops", - "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", - "MetricGroup": "Cor;Pipeline", - "MetricName": "Execute_per_Issue", - "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS", - "MetricGroup": "Ret;SMT;tma_L1_group", - "MetricName": "CoreIPC" + "BriefDescription": "C7 residency percent per core", + "MetricExpr": "cstate_core@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Core_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS", - "MetricGroup": "Flops;Ret", - "MetricName": "FLOPc" + "BriefDescription": "C7 residency percent per package", + "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Pkg_Residency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "FP_Arith_Utilization", - "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "tma_info_socket_clks / #num_dies / duration_time / 1e9", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" }, { - "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", - "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", - "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", - "MetricName": "ILP" + "BriefDescription": "Percentage of cycles spent in System Management Interrupts.", + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", + "MetricGroup": "smi", + "MetricName": "smi_cycles", + "MetricThreshold": "smi_cycles > 0.1", + "ScaleUnit": "100%" }, { - "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", - "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)", - "MetricGroup": "Cor;SMT", - "MetricName": "Core_Bound_Likely" + "BriefDescription": "Number of SMI interrupts.", + "MetricExpr": "msr@smi@", + "MetricGroup": "smi", + "MetricName": "smi_num", + "ScaleUnit": "1SMI#" }, { - "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", - "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else CLKS))", - "MetricGroup": "SMT", - "MetricName": "CORE_CLKS" + "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", + "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_4k_aliasing", + "MetricThreshold": "tma_4k_aliasing > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", - "MetricGroup": "InsType", - "MetricName": "IpLoad" + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / tma_info_slots", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_alu_op_utilization", + "MetricThreshold": "tma_alu_op_utilization > 0.6", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", - "MetricGroup": "InsType", - "MetricName": "IpStore" + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", + "MetricExpr": "100 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / tma_info_slots", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_assists", + "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.ANY", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Fed;InsType", - "MetricName": "IpBranch" + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", + "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_backend_bound", + "MetricThreshold": "tma_backend_bound > 0.2", + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "IpCall" + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", + "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_bad_speculation", + "MetricThreshold": "tma_bad_speculation > 0.15", + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", - "MetricName": "IpTB" + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", + "MetricName": "tma_branch_mispredicts", + "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredicts_resteers", + "ScaleUnit": "100%" }, { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "BpTkBranch" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", + "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks + tma_unknown_branches", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_branch_resteers", + "MetricThreshold": "tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)", - "MetricGroup": "Flops;InsType", - "MetricName": "IpFLOP" + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", + "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_cisc", + "MetricThreshold": "tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))", - "MetricGroup": "Flops;InsType", - "MetricName": "IpArith", - "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears", + "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks", + "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC", + "MetricName": "tma_clears_resteers", + "MetricThreshold": "tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", - "MetricGroup": "Flops;FpScalar;InsType", - "MetricName": "IpArith_Scalar_SP", - "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(44 * tma_info_average_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 44 * tma_info_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_contested_accesses", + "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", - "MetricGroup": "Flops;FpScalar;InsType", - "MetricName": "IpArith_Scalar_DP", - "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_backend_bound - tma_memory_bound", + "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX128", - "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "44 * tma_info_average_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_data_sharing", + "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX256", - "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", + "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) / tma_info_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_issueD0;tma_mite_group", + "MetricName": "tma_decoder0_alone", + "MetricThreshold": "tma_decoder0_alone > 0.1 & (tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35))", + "PublicDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder. Related metrics: tma_few_uops_instructions", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX512", - "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", + "MetricExpr": "ARITH.DIVIDER_ACTIVE / tma_info_clks", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_divider", + "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", - "MetricGroup": "Prefetches", - "MetricName": "IpSWPF" + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks - tma_l2_bound", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_dram_bound", + "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary;tma_L1_group", - "MetricName": "Instructions" + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", + "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / tma_info_core_clks / 2", + "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_dsb", + "MetricThreshold": "tma_dsb > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@", - "MetricGroup": "Pipeline;Ret", - "MetricName": "Retire" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_clks", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_dsb_switches", + "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", + "ScaleUnit": "100%" }, { - "BriefDescription": "", - "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", - "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", - "MetricName": "Execute" + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group", + "MetricName": "tma_dtlb_load", + "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store, tma_info_memory_data_tlbs", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of Uops issued by front-end when it issued something", - "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@", - "MetricGroup": "Fed;FetchBW", - "MetricName": "Fetch_UpC" + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", + "MetricExpr": "(9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group", + "MetricName": "tma_dtlb_store", + "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, tma_info_memory_data_tlbs", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "DSB;Fed;FetchBW", - "MetricName": "DSB_Coverage" + "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(110 * tma_info_average_frequency * (OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM) + 47.5 * tma_info_average_frequency * (OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE)) / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group", + "MetricName": "tma_false_sharing", + "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHES.COUNT", - "MetricGroup": "DSBmiss", - "MetricName": "DSB_Switch_Cost" + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "tma_info_load_miss_real_latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / tma_info_clks", + "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricName": "tma_fb_full", + "MetricThreshold": "tma_fb_full > 0.3", + "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_dram_bw_use, tma_info_memory_bandwidth, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", + "ScaleUnit": "100%" }, { - "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.", - "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))", - "MetricGroup": "DSBmiss;Fed", - "MetricName": "DSB_Misses" + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", + "MetricExpr": "tma_frontend_bound - tma_fetch_latency", + "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", + "MetricName": "tma_fetch_bandwidth", + "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", + "ScaleUnit": "100%" }, { - "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", - "MetricGroup": "DSBmiss;Fed", - "MetricName": "IpDSB_Miss_Ret" + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", + "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / tma_info_slots", + "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_latency", + "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops", + "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer", + "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueD0", + "MetricName": "tma_few_uops_instructions", + "MetricThreshold": "tma_few_uops_instructions > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions. Related metrics: tma_decoder0_alone", + "ScaleUnit": "100%" }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BrMispredicts", - "MetricName": "Branch_Misprediction_Cost" + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", + "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_fp_arith", + "MetricThreshold": "tma_fp_arith > 0.2 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of branches that are non-taken conditionals", - "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches;CodeGen;PGO", - "MetricName": "Cond_NT" + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", + "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_scalar", + "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of branches that are taken conditionals", - "MetricExpr": "(BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches;CodeGen;PGO", - "MetricName": "Cond_TK" + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_vector", + "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of branches that are CALL or RET", - "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches", - "MetricName": "CallRet" + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_128b", + "MetricThreshold": "tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", - "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches", - "MetricName": "Jump" + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_256b", + "MetricThreshold": "tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)", - "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency" + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_512b", + "MetricThreshold": "tma_fp_vector_512b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "Mem;MemoryBW;MemoryBound", - "MetricName": "MLP" + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_slots", + "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.15", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions", + "MetricExpr": "tma_light_operations * UOPS_RETIRED.MACRO_FUSED / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_fused_instructions", + "MetricThreshold": "tma_fused_instructions > 0.1 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.", + "ScaleUnit": "100%" }, { - "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI_Load" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences", + "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / tma_info_slots", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_heavy_operations", + "MetricThreshold": "tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Backend;CacheMisses;Mem", - "MetricName": "L2MPKI" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses", + "MetricExpr": "(ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@) / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_icache_misses", + "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem;Offcore", - "MetricName": "L2MPKI_All" + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "tma_info_turbo_utilization * TSC / 1e9 / duration_time", + "MetricGroup": "Power;Summary", + "MetricName": "tma_info_average_frequency" }, { - "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2MPKI_Load" + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB;tma_issueBC", + "MetricName": "tma_info_big_code", + "MetricThreshold": "tma_info_big_code > 20", + "PublicDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses). Related metrics: tma_info_branching_overhead" }, { - "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", - "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2HPKI_All" + "BriefDescription": "Branch instructions per taken branch.", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_bptkbranch" }, { - "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2HPKI_Load" + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_slots / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts;tma_issueBM", + "MetricName": "tma_info_branch_misprediction_cost", + "PublicDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_branch_mispredicts, tma_info_mispredictions, tma_mispredicts_resteers" }, { - "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L3MPKI" + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "MetricExpr": "100 * ((BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL)) / tma_info_slots)", + "MetricGroup": "Ret;tma_issueBC", + "MetricName": "tma_info_branching_overhead", + "MetricThreshold": "tma_info_branching_overhead > 10", + "PublicDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls). Related metrics: tma_info_big_code" }, { - "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "FB_HPKI" + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_callret" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING) / (2 * CORE_CLKS)", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "Page_Walks_Utilization" + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline", + "MetricName": "tma_info_clks" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Fed;MemoryTLB", + "MetricName": "tma_info_code_stlb_mpki" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "tma_info_cond_nt" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" + "BriefDescription": "Fraction of branches that are taken conditionals", + "MetricExpr": "(BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "tma_info_cond_tk" }, { - "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW" + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if tma_info_smt_2t_utilization > 0.5 else 0)", + "MetricGroup": "Cor;SMT", + "MetricName": "tma_info_core_bound_likely", + "MetricThreshold": "tma_info_core_bound_likely > 0.5" }, { - "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)", - "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / Instructions", - "MetricGroup": "L2Evicts;Mem;Server", - "MetricName": "L2_Evictions_Silent_PKI" + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / 2 * (1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK) if #core_wide < 1 else (CPU_CLK_UNHALTED.THREAD_ANY / 2 if #SMT_on else tma_info_clks))", + "MetricGroup": "SMT", + "MetricName": "tma_info_core_clks" }, { - "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction", - "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / Instructions", - "MetricGroup": "L2Evicts;Mem;Server", - "MetricName": "L2_Evictions_NonSilent_PKI" + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_core_clks", + "MetricGroup": "Ret;SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_coreipc" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "L1D_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW_1T" + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / tma_info_ipc", + "MetricGroup": "Mem;Pipeline", + "MetricName": "tma_info_cpi" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "L2_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW_1T" + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "HPC;Summary", + "MetricName": "tma_info_cpu_utilization" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW_1T" + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_data_l2_mlp" }, { - "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Access_BW", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW_1T" + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;tma_issueBW", + "MetricName": "tma_info_dram_bw_use", + "PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_info_memory_bandwidth, tma_mem_bandwidth, tma_sq_full" }, { - "BriefDescription": "Average CPU Utilization", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", - "MetricGroup": "HPC;Summary", - "MetricName": "CPU_Utilization" + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", + "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", + "MetricName": "tma_info_dsb_coverage", + "MetricThreshold": "tma_info_dsb_coverage < 0.7 & tma_info_ipc / 4 > 0.35", + "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_misses, tma_info_iptb, tma_lcp" }, { - "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", - "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time", - "MetricGroup": "Power;Summary", - "MetricName": "Average_Frequency" + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_mite))", + "MetricGroup": "DSBmiss;Fed;tma_issueFB", + "MetricName": "tma_info_dsb_misses", + "MetricThreshold": "tma_info_dsb_misses > 10", + "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_iptb, tma_lcp" }, { - "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs", - "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / DSB2MITE_SWITCHES.COUNT", + "MetricGroup": "DSBmiss", + "MetricName": "tma_info_dsb_switch_cost" }, { - "BriefDescription": "Average Frequency Utilization relative nominal frequency", - "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC", - "MetricGroup": "Power", - "MetricName": "Turbo_Utilization" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-thread", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "tma_info_execute" }, { - "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0", - "MetricExpr": "(CORE_POWER.LVL0_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL0_TURBO_LICENSE / CORE_CLKS)", - "MetricGroup": "Power", - "MetricName": "Power_License0_Utilization", - "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes." + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "tma_info_execute_per_issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." }, { - "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1", - "MetricExpr": "(CORE_POWER.LVL1_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL1_TURBO_LICENSE / CORE_CLKS)", - "MetricGroup": "Power", - "MetricName": "Power_License1_Utilization", - "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions." + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_fb_hpki" }, { - "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)", - "MetricExpr": "(CORE_POWER.LVL2_TURBO_LICENSE / 2 / CORE_CLKS if #SMT_on else CORE_POWER.LVL2_TURBO_LICENSE / CORE_CLKS)", - "MetricGroup": "Power", - "MetricName": "Power_License2_Utilization", - "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions." + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_fetch_upc" }, { - "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", - "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", - "MetricGroup": "SMT", - "MetricName": "SMT_2T_Utilization" + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / tma_info_core_clks", + "MetricGroup": "Flops;Ret", + "MetricName": "tma_info_flopc" }, { - "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "OS", - "MetricName": "Kernel_Utilization" + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@) / (2 * tma_info_core_clks)", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_fp_arith_utilization", + "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." }, { - "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", - "MetricGroup": "OS", - "MetricName": "Kernel_CPI" + "BriefDescription": "Giga Floating Point Operations Per Second", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_gflops", + "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." }, { - "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", - "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e9 / duration_time", - "MetricGroup": "HPC;Mem;MemoryBW;SoC", - "MetricName": "DRAM_BW_Use" + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck", + "MetricExpr": "100 * (tma_fetch_latency * tma_icache_misses / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", + "MetricGroup": "Fed;FetchLat;IcMiss;tma_issueFL", + "MetricName": "tma_info_ic_misses", + "MetricThreshold": "tma_info_ic_misses > 5", + "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck. Related metrics: " }, { - "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches", - "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (Socket_CLKS / duration_time)", - "MetricGroup": "Mem;MemoryLat;SoC", - "MetricName": "MEM_Read_Latency" + "BriefDescription": "Average Latency for L1 instruction cache misses", + "MetricExpr": "ICACHE_16B.IFDATA_STALL / cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@ + 2", + "MetricGroup": "Fed;FetchLat;IcMiss", + "MetricName": "tma_info_icache_miss_latency" }, { - "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", - "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@thresh\\=1@", - "MetricGroup": "Mem;MemoryBW;SoC", - "MetricName": "MEM_Parallel_Reads" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", + "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", + "MetricName": "tma_info_ilp" }, { - "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", - "MetricExpr": "1e9 * (UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSERTS) / imc_0@event\\=0x0@", - "MetricGroup": "Mem;MemoryLat;Server;SoC", - "MetricName": "MEM_DRAM_Read_Latency" + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_big_code", + "MetricGroup": "Fed;FetchBW;Frontend", + "MetricName": "tma_info_instruction_fetch_bw", + "MetricThreshold": "tma_info_instruction_fetch_bw > 20" }, { - "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]", - "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1e9 / duration_time", - "MetricGroup": "IoBW;Mem;Server;SoC", - "MetricName": "IO_Write_BW" + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;tma_L1_group", + "MetricName": "tma_info_instructions", + "PublicDescription": "Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST" }, { "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]", "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3) * 4 / 1e9 / duration_time", "MetricGroup": "IoBW;Mem;Server;SoC", - "MetricName": "IO_Read_BW" + "MetricName": "tma_info_io_read_bw" }, { - "BriefDescription": "Socket actual clocks when any core is active on that socket", - "MetricExpr": "cha_0@event\\=0x0@", - "MetricGroup": "SoC", - "MetricName": "Socket_CLKS" + "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]", + "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1e9 / duration_time", + "MetricGroup": "IoBW;Mem;Server;SoC", + "MetricName": "tma_info_io_write_bw" }, { - "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", - "MetricGroup": "Branches;OS", - "MetricName": "IpFarBranch" + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_iparith", + "MetricThreshold": "tma_info_iparith < 10", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." }, { - "BriefDescription": "Uncore frequency per die [GHZ]", - "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1e9", - "MetricGroup": "SoC", - "MetricName": "UNCORE_FREQ" + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx128", + "MetricThreshold": "tma_info_iparith_avx128 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Percentage of time spent in the active CPU power state C0", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", - "MetricName": "cpu_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx256", + "MetricThreshold": "tma_info_iparith_avx256 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "CPU operating frequency (in GHz)", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / duration_time", - "MetricName": "cpu_operating_frequency", - "ScaleUnit": "1GHz" + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx512", + "MetricThreshold": "tma_info_iparith_avx512 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Cycles per instruction retired; indicating how much time each executed instruction took; in units of cycles.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY", - "MetricName": "cpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_iparith_scalar_dp", + "MetricThreshold": "tma_info_iparith_scalar_dp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "The ratio of number of completed memory load instructions to the total number completed instructions", - "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY", - "MetricName": "loads_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_iparith_scalar_sp", + "MetricThreshold": "tma_info_iparith_scalar_sp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "The ratio of number of completed memory store instructions to the total number completed instructions", - "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY", - "MetricName": "stores_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "tma_info_ipbranch", + "MetricThreshold": "tma_info_ipbranch < 8" }, { - "BriefDescription": "Ratio of number of requests missing L1 data cache (includes data+rfo w/ prefetches) to the total number of completed instructions", - "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY", - "MetricName": "l1d_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_clks", + "MetricGroup": "Ret;Summary", + "MetricName": "tma_info_ipc" }, { - "BriefDescription": "Ratio of number of demand load requests hitting in L1 data cache to the total number of completed instructions ", - "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY", - "MetricName": "l1d_demand_data_read_hits_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_ipcall", + "MetricThreshold": "tma_info_ipcall < 200" }, { - "BriefDescription": "Ratio of number of code read requests missing in L1 instruction cache (includes prefetches) to the total number of completed instructions", - "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY", - "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "tma_info_ipdsb_miss_ret", + "MetricThreshold": "tma_info_ipdsb_miss_ret < 50" }, { - "BriefDescription": "Ratio of number of completed demand load requests hitting in L2 cache to the total number of completed instructions ", - "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY", - "MetricName": "l2_demand_data_read_hits_per_instr", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "tma_info_ipfarbranch", + "MetricThreshold": "tma_info_ipfarbranch < 1e6" }, { - "BriefDescription": "Ratio of number of requests missing L2 cache (includes code+data+rfo w/ prefetches) to the total number of completed instructions", - "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY", - "MetricName": "l2_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_ipflop", + "MetricThreshold": "tma_info_ipflop < 10" }, { - "BriefDescription": "Ratio of number of completed data read request missing L2 cache to the total number of completed instructions", - "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricName": "l2_demand_data_read_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipload", + "MetricThreshold": "tma_info_ipload < 3" }, { - "BriefDescription": "Ratio of number of code read request missing L2 cache to the total number of completed instructions", - "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", - "MetricName": "l2_demand_code_mpi", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "tma_info_instructions / (UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * cpu@BR_MISP_EXEC.ALL_BRANCHES\\,umask\\=0xE4@)", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_indirect", + "MetricThreshold": "tma_info_ipmisp_indirect < 1e3" }, { - "BriefDescription": "Ratio of number of data read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", - "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x12D4043300000000@ / INST_RETIRED.ANY", - "MetricName": "llc_data_read_mpi_demand_plus_prefetch", - "ScaleUnit": "1per_instr" + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "tma_info_ipmispredict", + "MetricThreshold": "tma_info_ipmispredict < 200" }, { - "BriefDescription": "Ratio of number of code read requests missing last level core cache (includes demand w/ prefetches) to the total number of completed instructions", - "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x12CC023300000000@ / INST_RETIRED.ANY", - "MetricName": "llc_code_read_mpi_demand_plus_prefetch", - "ScaleUnit": "1per_instr" + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipstore", + "MetricThreshold": "tma_info_ipstore < 8" }, { - "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) in nano seconds", - "MetricExpr": "1e9 * (cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043300000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043300000000@) / (UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time", - "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency", - "ScaleUnit": "1ns" + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", + "MetricGroup": "Prefetches", + "MetricName": "tma_info_ipswpf", + "MetricThreshold": "tma_info_ipswpf < 100" }, { - "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to local memory in nano seconds", - "MetricExpr": "1e9 * (cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043200000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@) / (UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time", - "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_local_requests", - "ScaleUnit": "1ns" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", + "MetricName": "tma_info_iptb", + "MetricThreshold": "tma_info_iptb < 9", + "PublicDescription": "Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_dsb_misses, tma_lcp" }, { - "BriefDescription": "Average latency of a last level cache (LLC) demand and prefetch data read miss (read memory access) addressed to remote memory in nano seconds", - "MetricExpr": "1e9 * (cha@unc_cha_tor_occupancy.ia_miss\\,config1\\=0x4043100000000@ / cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@) / (UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_packages)) * duration_time", - "MetricName": "llc_data_read_demand_plus_prefetch_miss_latency_for_remote_requests", - "ScaleUnit": "1ns" + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "tma_info_instructions / BACLEARS.ANY", + "MetricGroup": "Fed", + "MetricName": "tma_info_ipunknown_branch" }, { - "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions", - "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", - "MetricName": "itlb_mpi", - "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - (BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN) - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_jump" }, { - "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions", - "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY", - "MetricName": "itlb_large_page_mpi", - "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total number of completed instructions. This implies it missed in the Instruction Translation Lookaside Buffer (ITLB) and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_cpi" }, { - "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions", - "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", - "MetricName": "dtlb_load_mpi", - "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_utilization", + "MetricThreshold": "tma_info_kernel_utilization > 0.05" }, { - "BriefDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions", - "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY", - "MetricName": "dtlb_2mb_large_page_load_mpi", - "PublicDescription": "Ratio of number of completed page walks (for 2 megabyte page sizes) caused by demand data loads to the total number of completed instructions. This implies it missed in the Data Translation Lookaside Buffer (DTLB) and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw" }, { - "BriefDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions", - "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", - "MetricName": "dtlb_store_mpi", - "PublicDescription": "Ratio of number of completed page walks (for all page sizes) caused by demand data stores to the total number of completed instructions. This implies it missed in the DTLB and further levels of TLB.", - "ScaleUnit": "1per_instr" + "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "tma_info_l1d_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw_1t" }, { - "BriefDescription": "Memory read that miss the last level cache (LLC) addressed to local DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", - "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ / (cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@)", - "MetricName": "numa_reads_addressed_to_local_dram", - "ScaleUnit": "100%" + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l1mpki" }, { - "BriefDescription": "Memory reads that miss the last level cache (LLC) addressed to remote DRAM as a percentage of total memory read accesses, does not include LLC prefetches.", - "MetricExpr": "cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@ / (cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043200000000@ + cha@unc_cha_tor_inserts.ia_miss\\,config1\\=0x4043100000000@)", - "MetricName": "numa_reads_addressed_to_remote_dram", - "ScaleUnit": "100%" + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l1mpki_load" }, { - "BriefDescription": "Uncore operating frequency in GHz", - "MetricExpr": "UNC_CHA_CLOCKTICKS / (#num_cores / #num_packages * #num_packages) / 1e9 / duration_time", - "MetricName": "uncore_frequency", - "ScaleUnit": "1GHz" + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw" }, { - "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data transmit bandwidth (MB/sec)", - "MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 7.111111111111111 / 1e6 / duration_time", - "MetricName": "upi_data_transmit_bw", - "ScaleUnit": "1MB/s" + "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "tma_info_l2_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw_1t" }, { - "BriefDescription": "DDR memory read bandwidth (MB/sec)", - "MetricExpr": "UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time", - "MetricName": "memory_bandwidth_read", - "ScaleUnit": "1MB/s" + "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction", + "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / tma_info_instructions", + "MetricGroup": "L2Evicts;Mem;Server", + "MetricName": "tma_info_l2_evictions_nonsilent_pki" }, { - "BriefDescription": "DDR memory write bandwidth (MB/sec)", - "MetricExpr": "UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time", - "MetricName": "memory_bandwidth_write", - "ScaleUnit": "1MB/s" + "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)", + "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / tma_info_instructions", + "MetricGroup": "L2Evicts;Mem;Server", + "MetricName": "tma_info_l2_evictions_silent_pki" }, { - "BriefDescription": "DDR memory bandwidth (MB/sec)", - "MetricExpr": "(UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e6 / duration_time", - "MetricName": "memory_bandwidth_total", - "ScaleUnit": "1MB/s" + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2hpki_all" }, { - "BriefDescription": "Bandwidth of IO reads that are initiated by end device controllers that are requesting memory from the CPU.", - "MetricExpr": "(UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3) * 4 / 1e6 / duration_time", - "MetricName": "io_bandwidth_disk_or_network_writes", - "ScaleUnit": "1MB/s" + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2hpki_load" }, { - "BriefDescription": "Bandwidth of IO writes that are initiated by end device controllers that are writing memory to the CPU.", - "MetricExpr": "(UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2 + UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3) * 4 / 1e6 / duration_time", - "MetricName": "io_bandwidth_disk_or_network_reads", - "ScaleUnit": "1MB/s" + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Backend;CacheMisses;Mem", + "MetricName": "tma_info_l2mpki" }, { - "BriefDescription": "Uops delivered from decoded instruction cache (decoded stream buffer or DSB) as a percent of total uops delivered to Instruction Decode Queue", - "MetricExpr": "IDQ.DSB_UOPS / UOPS_ISSUED.ANY", - "MetricName": "percent_uops_delivered_from_decoded_icache", - "ScaleUnit": "100%" + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem;Offcore", + "MetricName": "tma_info_l2mpki_all" }, { - "BriefDescription": "Uops delivered from legacy decode pipeline (Micro-instruction Translation Engine or MITE) as a percent of total uops delivered to Instruction Decode Queue", - "MetricExpr": "IDQ.MITE_UOPS / UOPS_ISSUED.ANY", - "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline", - "ScaleUnit": "100%" + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction", + "MetricExpr": "1e3 * FRONTEND_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss", + "MetricName": "tma_info_l2mpki_code" }, { - "BriefDescription": "Uops delivered from microcode sequencer (MS) as a percent of total uops delivered to Instruction Decode Queue", - "MetricExpr": "IDQ.MS_UOPS / UOPS_ISSUED.ANY", - "MetricName": "percent_uops_delivered_from_microcode_sequencer", - "ScaleUnit": "100%" + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction", + "MetricExpr": "1e3 * L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss", + "MetricName": "tma_info_l2mpki_code_all" }, { - "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to local memory.", - "MetricExpr": "UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1e6 / duration_time", - "MetricName": "llc_miss_local_memory_bandwidth_read", - "ScaleUnit": "1MB/s" + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2mpki_load" }, { - "BriefDescription": "Bandwidth (MB/sec) of write requests that miss the last level cache (LLC) and go to local memory.", - "MetricExpr": "UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1e6 / duration_time", - "MetricName": "llc_miss_local_memory_bandwidth_write", - "ScaleUnit": "1MB/s" + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_l3_cache_access_bw" }, { - "BriefDescription": "Bandwidth (MB/sec) of read requests that miss the last level cache (LLC) and go to remote memory.", - "MetricExpr": "UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1e6 / duration_time", - "MetricName": "llc_miss_remote_memory_bandwidth_read", - "ScaleUnit": "1MB/s" + "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_l3_cache_access_bw", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_l3_cache_access_bw_1t" }, { - "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / SLOTS", - "MetricGroup": "PGO;TopdownL1;tma_L1_group;tma_L1_group", - "MetricName": "tma_frontend_bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", - "ScaleUnit": "100%" + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", - "MetricExpr": "4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / SLOTS", - "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_latency", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period.", - "ScaleUnit": "100%" + "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_l3_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw_1t" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses.", - "MetricExpr": "(ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=0x1\\,edge\\=0x1@) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_icache_misses", - "ScaleUnit": "100%" + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l3mpki" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses.", - "MetricExpr": "ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_itlb_misses", - "ScaleUnit": "100%" + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore", + "MetricName": "tma_info_load_l2_miss_latency" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", - "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + tma_unknown_branches", - "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_branch_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings.", - "ScaleUnit": "100%" + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_load_l2_mlp" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. ", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group", - "MetricName": "tma_mispredicts_resteers", - "ScaleUnit": "100%" + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "tma_info_load_miss_real_latency" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. ", - "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group", - "MetricName": "tma_clears_resteers", - "ScaleUnit": "100%" + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_load_stlb_mpki" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", - "MetricExpr": "9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", - "MetricName": "tma_unknown_branches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit).", - "ScaleUnit": "100%" + "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]", + "MetricExpr": "1e9 * (UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSERTS) / imc_0@event\\=0x0@", + "MetricGroup": "Mem;MemoryLat;Server;SoC", + "MetricName": "tma_info_mem_dram_read_latency", + "PublicDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_dsb_switches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty.", - "ScaleUnit": "100%" + "BriefDescription": "Average number of parallel data read requests to external memory", + "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD@thresh\\=1@", + "MetricGroup": "Mem;MemoryBW;SoC", + "MetricName": "tma_info_mem_parallel_reads", + "PublicDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches" }, { - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", - "MetricExpr": "ILD_STALL.LCP / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_lcp", - "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", - "ScaleUnit": "100%" + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds)", + "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD) / (tma_info_socket_clks / duration_time)", + "MetricGroup": "Mem;MemoryLat;SoC", + "MetricName": "tma_info_mem_read_latency", + "PublicDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)" }, { - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", - "MetricExpr": "2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_ms_switches", - "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals.", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))", + "MetricGroup": "Mem;MemoryBW;Offcore;tma_issueBW", + "MetricName": "tma_info_memory_bandwidth", + "MetricThreshold": "tma_info_memory_bandwidth > 20", + "PublicDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_mem_bandwidth, tma_sq_full" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", - "MetricExpr": "tma_frontend_bound - tma_fetch_latency", - "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_bandwidth", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend.", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency)))", + "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", + "MetricName": "tma_info_memory_data_tlbs", + "MetricThreshold": "tma_info_memory_data_tlbs > 20", + "PublicDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", - "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / CORE_CLKS / 2", - "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", - "MetricName": "tma_mite", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck.", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound))", + "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", + "MetricName": "tma_info_memory_latency", + "MetricThreshold": "tma_info_memory_latency > 20", + "PublicDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches). Related metrics: tma_l3_hit_latency, tma_mem_latency" }, { - "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", - "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=0x1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=0x2@) / CORE_CLKS", - "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group", - "MetricName": "tma_decoder0_alone", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", + "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", + "MetricName": "tma_info_mispredictions", + "MetricThreshold": "tma_info_mispredictions > 20", + "PublicDescription": "Total pipeline cost of Branch Misprediction related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_branch_misprediction_cost, tma_mispredicts_resteers" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", - "MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / CORE_CLKS / 2", - "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", - "MetricName": "tma_dsb", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", - "ScaleUnit": "100%" + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBW;MemoryBound", + "MetricName": "tma_info_mlp", + "PublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)" }, { - "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", - "MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group", - "MetricName": "tma_bad_speculation", - "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", - "ScaleUnit": "100%" + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING) / (2 * tma_info_core_clks)", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_page_walks_utilization", + "MetricThreshold": "tma_info_page_walks_utilization > 0.5" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_branch_mispredicts", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path.", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0", + "MetricExpr": "(CORE_POWER.LVL0_TURBO_LICENSE / 2 / tma_info_core_clks if #SMT_on else CORE_POWER.LVL0_TURBO_LICENSE / tma_info_core_clks)", + "MetricGroup": "Power", + "MetricName": "tma_info_power_license0_utilization", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes." }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", - "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_machine_clears", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes.", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1", + "MetricExpr": "(CORE_POWER.LVL1_TURBO_LICENSE / 2 / tma_info_core_clks if #SMT_on else CORE_POWER.LVL1_TURBO_LICENSE / tma_info_core_clks)", + "MetricGroup": "Power", + "MetricName": "tma_info_power_license1_utilization", + "MetricThreshold": "tma_info_power_license1_utilization > 0.5", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions." }, { - "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", - "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group", - "MetricName": "tma_backend_bound", - "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)", + "MetricExpr": "(CORE_POWER.LVL2_TURBO_LICENSE / 2 / tma_info_core_clks if #SMT_on else CORE_POWER.LVL2_TURBO_LICENSE / tma_info_core_clks)", + "MetricGroup": "Power", + "MetricName": "tma_info_power_license2_utilization", + "MetricThreshold": "tma_info_power_license2_utilization > 0.5", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions." }, { - "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + UOPS_RETIRED.RETIRE_SLOTS / SLOTS * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound", - "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_memory_bound", - "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", - "ScaleUnit": "100%" + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "tma_info_retire" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", - "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CPU_CLK_UNHALTED.THREAD, 0)", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_l1_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache.", - "ScaleUnit": "100%" + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * tma_info_core_clks", + "MetricGroup": "TmaL1;tma_L1_group", + "MetricName": "tma_info_slots" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", - "MetricExpr": "min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_dtlb_load", - "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss.", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #SMT_on else 0)", + "MetricGroup": "SMT", + "MetricName": "tma_info_smt_2t_utilization" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", - "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss", - "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", - "MetricName": "tma_load_stlb_hit", - "ScaleUnit": "100%" + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "cha_0@event\\=0x0@", + "MetricGroup": "SoC", + "MetricName": "tma_info_socket_clks" }, { - "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", - "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", - "MetricName": "tma_load_stlb_miss", - "ScaleUnit": "100%" + "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_store_stlb_mpki" }, { - "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", - "MetricExpr": "min(13 * LD_BLOCKS.STORE_FORWARD / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_store_fwd_blk", - "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", - "ScaleUnit": "100%" + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "tma_info_clks / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power", + "MetricName": "tma_info_turbo_utilization" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", - "MetricExpr": "min((12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (11 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_lock_latency", - "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them.", - "ScaleUnit": "100%" + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire", + "MetricName": "tma_info_uoppi", + "MetricThreshold": "tma_info_uoppi > 1.05" }, { - "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. ", - "MetricExpr": "min(Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_split_loads", - "ScaleUnit": "100%" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "tma_info_uptb", + "MetricThreshold": "tma_info_uptb < 6" }, { - "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", - "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_4k_aliasing", - "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", + "MetricExpr": "ICACHE_64B.IFTAG_STALL / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", - "MetricExpr": "Load_Miss_Real_Latency * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@ / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_fb_full", - "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).", + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", + "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / tma_info_clks, 0)", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group", + "MetricName": "tma_l1_bound", + "MetricThreshold": "tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", - "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=0x1@) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks)", "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance.", + "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS", "ScaleUnit": "100%" }, { "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / CPU_CLK_UNHALTED.THREAD", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / tma_info_clks", "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l3_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance.", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", - "MetricExpr": "min(((47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + (47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", - "MetricName": "tma_contested_accesses", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing.", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", - "MetricExpr": "min((47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * (MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_l3_bound_group", - "MetricName": "tma_data_sharing", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance.", + "MetricThreshold": "tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", - "MetricExpr": "min((20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 3.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_l3_bound_group", + "MetricExpr": "17 * tma_info_average_frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", - "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings.", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", - "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / CORE_CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_l3_bound_group", - "MetricName": "tma_sq_full", - "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", - "MetricExpr": "min(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CPU_CLK_UNHALTED.THREAD - tma_l2_bound, 1)", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_dram_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance.", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=0x4@) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group", - "MetricName": "tma_mem_bandwidth", - "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_memory_latency, tma_mem_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CPU_CLK_UNHALTED.THREAD - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group", - "MetricName": "tma_mem_latency", - "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory", - "MetricExpr": "min((80 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_local_dram", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance.", + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", + "MetricExpr": "ILD_STALL.LCP / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_lcp", + "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory", - "MetricExpr": "min((147.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_remote_dram", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", + "MetricExpr": "tma_retiring - tma_heavy_operations", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_light_operations", + "MetricThreshold": "tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues", - "MetricExpr": "min(((110 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + (110 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) - 20.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3))) * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", - "MetricName": "tma_remote_cache", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", + "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_load_op_utilization", + "MetricThreshold": "tma_load_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", - "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_store_bound", - "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck.", + "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", + "MetricName": "tma_load_stlb_hit", + "MetricThreshold": "tma_load_stlb_hit > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", - "MetricExpr": "(L2_RQSTS.RFO_HIT * 11 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_store_latency", - "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", + "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", + "MetricName": "tma_load_stlb_miss", + "MetricThreshold": "tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", - "MetricExpr": "min((110 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) * (OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM) + 47.5 * (CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC * #SYSTEM_TSC_FREQ / 1e9 / (duration_time * 1e3 / 1e3)) * (OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE)) / CPU_CLK_UNHALTED.THREAD, 1)", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_false_sharing", - "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. ", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory", + "MetricExpr": "59.5 * tma_info_average_frequency * MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_group", + "MetricName": "tma_local_dram", + "MetricThreshold": "tma_local_dram > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from local memory. Caching will improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents rate of split store accesses", - "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CORE_CLKS", - "MetricGroup": "TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_split_stores", - "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity.", + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", + "MetricExpr": "(12 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (11 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / tma_info_clks", + "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group", + "MetricName": "tma_lock_latency", + "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", - "MetricExpr": "min((9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=0x1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CORE_CLKS, 1)", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_store_bound_group", - "MetricName": "tma_dtlb_store", - "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data.", + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", + "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", - "MetricExpr": "tma_dtlb_store - DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS", - "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", - "MetricName": "tma_store_stlb_hit", + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW", + "MetricName": "tma_mem_bandwidth", + "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_info_memory_bandwidth, tma_sq_full", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", - "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS", - "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", - "MetricName": "tma_store_stlb_miss", + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_clks - tma_mem_bandwidth", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat", + "MetricName": "tma_mem_latency", + "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_info_memory_latency, tma_l3_hit_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", - "MetricExpr": "tma_backend_bound - tma_memory_bound", - "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_core_bound", - "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound", + "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_memory_bound", + "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", - "MetricExpr": "ARITH.DIVIDER_ACTIVE / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", - "MetricName": "tma_divider", - "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", + "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_memory_operations", + "MetricThreshold": "tma_memory_operations > 0.1 & tma_light_operations > 0.6", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", - "MetricExpr": "((EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + UOPS_RETIRED.RETIRE_SLOTS / SLOTS * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + UOPS_RETIRED.RETIRE_SLOTS / SLOTS * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD)", - "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", - "MetricName": "tma_ports_utilization", - "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_slots", + "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS", + "MetricName": "tma_microcode_sequencer", + "MetricThreshold": "tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_NONE / 2 if #SMT_on else CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_0", - "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks", + "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM", + "MetricName": "tma_mispredicts_resteers", + "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_branch_misprediction_cost, tma_info_mispredictions", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations", - "MetricExpr": "PARTIAL_RAT_STALLS.SCOREBOARD / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group", - "MetricName": "tma_serializing_operation", - "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance.", + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", + "MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / tma_info_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_mite", + "MetricThreshold": "tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 4 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS", "ScaleUnit": "100%" }, { "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY, 1)", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_0_group", + "MetricExpr": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY", + "MetricGroup": "TopdownL5;tma_L5_group;tma_issueMV;tma_ports_utilized_0_group", "MetricName": "tma_mixing_vectors", - "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", + "MetricThreshold": "tma_mixing_vectors > 0.05", + "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic. Related metrics: tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2) / 2 if #SMT_on else EXE_ACTIVITY.1_PORTS_UTIL) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_1", - "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful.", + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", + "MetricExpr": "2 * IDQ.MS_SWITCHES / tma_info_clks", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", + "MetricName": "tma_ms_switches", + "MetricThreshold": "tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3) / 2 if #SMT_on else EXE_ACTIVITY.2_PORTS_UTIL) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_2", - "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused", + "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_non_fused_branches", + "MetricThreshold": "tma_non_fused_branches > 0.1 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", - "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_3) / CORE_CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_3m", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions", + "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / UOPS_RETIRED.RETIRE_SLOTS", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_nop_instructions", + "MetricThreshold": "tma_nop_instructions > 0.1 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_0 + UOPS_DISPATCHED_PORT.PORT_1 + UOPS_DISPATCHED_PORT.PORT_5 + UOPS_DISPATCHED_PORT.PORT_6) / SLOTS", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", - "MetricName": "tma_alu_op_utilization", + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes", + "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions))", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_other_light_ops", + "MetricThreshold": "tma_other_light_ops > 0.3 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / CORE_CLKS", - "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_0 / tma_info_core_clks", + "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", "MetricName": "tma_port_0", + "MetricThreshold": "tma_port_0 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED_PORT.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_1 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", "MetricName": "tma_port_1", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", - "MetricName": "tma_port_5", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group", - "MetricName": "tma_port_6", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", - "MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 + UOPS_DISPATCHED_PORT.PORT_7 - UOPS_DISPATCHED_PORT.PORT_4) / (2 * CORE_CLKS)", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", - "MetricName": "tma_load_op_utilization", + "MetricThreshold": "tma_port_1 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / CORE_CLKS", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_2 / tma_info_core_clks", "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", "MetricName": "tma_port_2", + "MetricThreshold": "tma_port_2 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_2", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / CORE_CLKS", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_3 / tma_info_core_clks", "MetricGroup": "TopdownL6;tma_L6_group;tma_load_op_utilization_group", "MetricName": "tma_port_3", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / CORE_CLKS", - "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", - "MetricName": "tma_store_op_utilization", + "MetricThreshold": "tma_port_3 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads). Sample with: UOPS_DISPATCHED_PORT.PORT_3", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)", "MetricExpr": "tma_store_op_utilization", - "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group", + "MetricGroup": "TopdownL6;tma_L6_group;tma_issueSpSt;tma_store_op_utilization_group", "MetricName": "tma_port_4", + "MetricThreshold": "tma_port_4 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Sample with: UOPS_DISPATCHED_PORT.PORT_4. Related metrics: tma_split_stores", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)", - "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group", - "MetricName": "tma_port_7", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_5 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_5", + "MetricThreshold": "tma_port_5 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Sample with: UOPS_DISPATCHED.PORT_5. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group;tma_L1_group", - "MetricName": "tma_retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_6 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_6", + "MetricThreshold": "tma_port_6 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED_PORT.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", - "MetricExpr": "tma_retiring - (UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / SLOTS", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group", - "MetricName": "tma_light_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved.", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address)", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_7 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_store_op_utilization_group", + "MetricName": "tma_port_7", + "MetricThreshold": "tma_port_7 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 7 ([HSW+]simple Store-address). Sample with: UOPS_DISPATCHED_PORT.PORT_7", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", - "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD + tma_fp_scalar + tma_fp_vector", - "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_fp_arith", - "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", + "MetricExpr": "((EXE_ACTIVITY.EXE_BOUND_0_PORTS + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / tma_info_clks if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / tma_info_clks)", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_ports_utilization", + "MetricThreshold": "tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric serves as an approximation of legacy x87 usage", - "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD", - "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", - "MetricName": "tma_x87_use", - "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_NONE / 2 if #SMT_on else CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_core_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_0", + "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group", - "MetricName": "tma_fp_scalar", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_1 - UOPS_EXECUTED.CORE_CYCLES_GE_2) / 2 if #SMT_on else EXE_ACTIVITY.1_PORTS_UTIL) / tma_info_core_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_1", + "MetricThreshold": "tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Related metrics: tma_l1_bound", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", - "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)", - "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group", - "MetricName": "tma_fp_vector", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "((UOPS_EXECUTED.CORE_CYCLES_GE_2 - UOPS_EXECUTED.CORE_CYCLES_GE_3) / 2 if #SMT_on else EXE_ACTIVITY.2_PORTS_UTIL) / tma_info_core_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_2", + "MetricThreshold": "tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", - "MetricExpr": "min((FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)", - "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", - "MetricName": "tma_fp_vector_128b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.", + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise).", + "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_3) / tma_info_core_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_3m", + "MetricThreshold": "tma_ports_utilized_3m > 0.7 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", - "MetricExpr": "min((FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)", - "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", - "MetricName": "tma_fp_vector_256b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "(89.5 * tma_info_average_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM + 89.5 * tma_info_average_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_issueSyncxn;tma_mem_latency_group", + "MetricName": "tma_remote_cache", + "MetricThreshold": "tma_remote_cache > 0.05 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote cache in other sockets including synchronizations issues. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors", - "MetricExpr": "min((FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / UOPS_RETIRED.RETIRE_SLOTS, 1)", - "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group", - "MetricName": "tma_fp_vector_512b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory", + "MetricExpr": "127 * tma_info_average_frequency * MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latency_group", + "MetricName": "tma_remote_dram", + "MetricThreshold": "tma_remote_dram > 0.1 & (tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling loads from remote memory. This is caused often due to non-optimal NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", - "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_memory_operations", + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.RETIRE_SLOTS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions", - "MetricExpr": "tma_light_operations * UOPS_RETIRED.MACRO_FUSED / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_fused_instructions", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring fused instructions -- where one uop can represent multiple contiguous instructions. The instruction pairs of CMP+JCC or DEC+JCC are commonly used examples.", + "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations", + "MetricExpr": "PARTIAL_RAT_STALLS.SCOREBOARD / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL5;tma_L5_group;tma_issueSO;tma_ports_utilized_0_group", + "MetricName": "tma_serializing_operation", + "MetricThreshold": "tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: PARTIAL_RAT_STALLS.SCOREBOARD. Related metrics: tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused", - "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHES - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_non_fused_branches", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions that were not fused. Non-conditional branches like direct JMP or CALL would count here. Can be used to examine fusible conditional jumps that were not fused.", + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "tma_info_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_split_loads", + "MetricThreshold": "tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions", - "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_nop_instructions", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body.", + "BriefDescription": "This metric represents rate of split store accesses", + "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / tma_info_core_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group", + "MetricName": "tma_split_stores", + "MetricThreshold": "tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", - "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_fused_instructions + tma_non_fused_branches + tma_nop_instructions))", - "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", - "MetricName": "tma_other_light_ops", + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", + "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on else OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group", + "MetricName": "tma_sq_full", + "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_info_memory_bandwidth, tma_mem_bandwidth", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences", - "MetricExpr": "(UOPS_RETIRED.RETIRE_SLOTS + UOPS_RETIRED.MACRO_FUSED - INST_RETIRED.ANY) / SLOTS", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_L2_group;tma_retiring_group", - "MetricName": "tma_heavy_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.", + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", + "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_store_bound", + "MetricThreshold": "tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops", - "MetricExpr": "tma_heavy_operations - UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS", - "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group", - "MetricName": "tma_few_uops_instructions", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.", + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", + "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_store_fwd_blk", + "MetricThreshold": "tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS", - "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group", - "MetricName": "tma_microcode_sequencer", - "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided.", + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "(L2_RQSTS.RFO_HIT * 11 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_clks", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group", + "MetricName": "tma_store_latency", + "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", - "MetricExpr": "min(100 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / SLOTS, 1)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", - "MetricName": "tma_assists", - "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases.", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "MetricExpr": "UOPS_DISPATCHED_PORT.PORT_4 / tma_info_core_clks", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_store_op_utilization", + "MetricThreshold": "tma_store_op_utilization > 0.6", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", - "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", - "MetricName": "tma_cisc", - "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", + "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", + "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", + "MetricName": "tma_store_stlb_hit", + "MetricThreshold": "tma_store_stlb_hit > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per core", - "MetricExpr": "cstate_core@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Core_Residency", + "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", + "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / tma_info_core_clks", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", + "MetricName": "tma_store_stlb_miss", + "MetricThreshold": "tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per core", - "MetricExpr": "cstate_core@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Core_Residency", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", + "MetricExpr": "9 * BACLEARS.ANY / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", + "MetricName": "tma_unknown_branches", + "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit). Sample with: BACLEARS.ANY", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per core", - "MetricExpr": "cstate_core@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Core_Residency", + "BriefDescription": "This metric serves as an approximation of legacy x87 usage", + "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD", + "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_x87_use", + "MetricThreshold": "tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", "ScaleUnit": "100%" }, { - "BriefDescription": "C2 residency percent per package", - "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C2_Pkg_Residency", + "BriefDescription": "Percentage of cycles in aborted transactions.", + "MetricExpr": "max(cpu@cycles\\-t@ - cpu@cycles\\-ct@, 0) / cycles", + "MetricGroup": "transaction", + "MetricName": "tsx_aborted_cycles", "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per package", - "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Pkg_Residency", - "ScaleUnit": "100%" + "BriefDescription": "Number of cycles within a transaction divided by the number of elisions.", + "MetricExpr": "cpu@cycles\\-t@ / cpu@el\\-start@", + "MetricGroup": "transaction", + "MetricName": "tsx_cycles_per_elision", + "ScaleUnit": "1cycles / elision" }, { - "BriefDescription": "C6 residency percent per package", - "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Pkg_Residency", - "ScaleUnit": "100%" + "BriefDescription": "Number of cycles within a transaction divided by the number of transactions.", + "MetricExpr": "cpu@cycles\\-t@ / cpu@tx\\-start@", + "MetricGroup": "transaction", + "MetricName": "tsx_cycles_per_transaction", + "ScaleUnit": "1cycles / transaction" }, { - "BriefDescription": "C7 residency percent per package", - "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Pkg_Residency", + "BriefDescription": "Percentage of cycles within a transaction region.", + "MetricExpr": "cpu@cycles\\-t@ / cycles", + "MetricGroup": "transaction", + "MetricName": "tsx_transactional_cycles", "ScaleUnit": "100%" } ] diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json b/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json index 8784118123b4..e0840c24e7aa 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json @@ -1952,7 +1952,7 @@ "EventCode": "0x81", "EventName": "UNC_M_WPQ_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller). They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. Is there a filter of sorts???", + "PublicDescription": "Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller). They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. Is there a filter of sorts???", "Unit": "iMC" }, { diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json index 37003115c6c7..92a4bdcd4bd7 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json @@ -804,7 +804,7 @@ "Unit": "CHA" }, { - "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Deallocate HtiME$ on Reads without RspFwdI*", + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Deallocate HitME$ on Reads without RspFwdI*", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE", "PerPkg": "1", @@ -3321,7 +3321,7 @@ "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSP_FWD_WB", "PerPkg": "1", - "PublicDescription": "Counts when a transaction with the opcode type Rsp*Fwd*WB Snoop Response was received which indicates the data was written back to its home socket, and the cacheline was forwarded to the requestor socket. This snoop response is only used in >= 4 socket systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to its home socket to be written back to memory.", + "PublicDescription": "Counts when a transaction with the opcode type Rsp*Fwd*WB Snoop Response was received which indicates the data was written back to its home socket, and the cacheline was forwarded to the requestor socket. This snoop response is only used in >= 4 socket systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to its home socket to be written back to memory.", "UMask": "0x20", "Unit": "CHA" }, @@ -4039,20 +4039,22 @@ "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", "Filter": "config1=0x40233", "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", "Filter": "config1=0x40433", "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x11", "Unit": "CHA" }, @@ -4075,20 +4077,22 @@ "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", + "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", "Filter": "config1=0x4b033", "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x11", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", "Filter": "config1=0x40033", "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x11", "Unit": "CHA" }, @@ -4102,20 +4106,22 @@ "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", "Filter": "config1=0x40233", "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", "Filter": "config1=0x40433", "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x21", "Unit": "CHA" }, @@ -4138,20 +4144,22 @@ "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", + "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", "Filter": "config1=0x4b033", "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x21", "Unit": "CHA" }, { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", "Filter": "config1=0x40033", "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0x21", "Unit": "CHA" }, @@ -11909,7 +11917,7 @@ "Unit": "IIO" }, { - "BriefDescription": "UNC_IIO_NOTHING", + "BriefDescription": "Counting disabled", "EventName": "UNC_IIO_NOTHING", "PerPkg": "1", "Unit": "IIO" @@ -15507,7 +15515,7 @@ "EventCode": "0xC", "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.", + "PublicDescription": "Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.", "Unit": "IRP" }, { @@ -16013,35 +16021,35 @@ "Unit": "M2M" }, { - "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden", + "BriefDescription": "Number of reads in which direct to Intel(R) UPI transactions were overridden", "EventCode": "0x28", "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS", "PerPkg": "1", - "PublicDescription": "Counts reads in which direct to Intel Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overridden", + "PublicDescription": "Counts reads in which direct to Intel(R) Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overridden", "Unit": "M2M" }, { - "BriefDescription": "Cycles when direct to Intel UPI was disabled", + "BriefDescription": "Cycles when direct to Intel(R) UPI was disabled", "EventCode": "0x27", "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE", "PerPkg": "1", - "PublicDescription": "Counts cycles when the ability to send messages direct to the Intel Ultra Path Interconnect (bypassing the CHA) was disabled", + "PublicDescription": "Counts cycles when the ability to send messages direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA) was disabled", "Unit": "M2M" }, { - "BriefDescription": "Messages sent direct to the Intel UPI", + "BriefDescription": "Messages sent direct to the Intel(R) UPI", "EventCode": "0x26", "EventName": "UNC_M2M_DIRECT2UPI_TAKEN", "PerPkg": "1", - "PublicDescription": "Counts when messages were sent direct to the Intel Ultra Path Interconnect (bypassing the CHA)", + "PublicDescription": "Counts when messages were sent direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA)", "Unit": "M2M" }, { - "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden", + "BriefDescription": "Number of reads that a message sent direct2 Intel(R) UPI was overridden", "EventCode": "0x29", "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE", "PerPkg": "1", - "PublicDescription": "Counts when a read message that was sent direct to the Intel Ultra Path Interconnect (bypassing the CHA) was overridden", + "PublicDescription": "Counts when a read message that was sent direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA) was overridden", "Unit": "M2M" }, { @@ -20785,7 +20793,7 @@ "EventCode": "0x61", "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO", "PerPkg": "1", - "PublicDescription": "Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo", + "PublicDescription": "Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo", "UMask": "0x2", "Unit": "M3UPI" }, @@ -20794,7 +20802,7 @@ "EventCode": "0x61", "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH", "PerPkg": "1", - "PublicDescription": "Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo)", + "PublicDescription": "Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo)", "UMask": "0x4", "Unit": "M3UPI" }, @@ -21180,7 +21188,7 @@ "Unit": "M3UPI" }, { - "BriefDescription": "Flit Gen - Header 1; Acumullate", + "BriefDescription": "Flit Gen - Header 1; Accumulate", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM", "PerPkg": "1", @@ -21851,7 +21859,7 @@ "Unit": "M3UPI" }, { - "BriefDescription": "Remote VNA Credits; Level < 1", + "BriefDescription": "Remote VNA Credits; Level < 1", "EventCode": "0x5B", "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1", "PerPkg": "1", @@ -21860,7 +21868,7 @@ "Unit": "M3UPI" }, { - "BriefDescription": "Remote VNA Credits; Level < 4", + "BriefDescription": "Remote VNA Credits; Level < 4", "EventCode": "0x5B", "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4", "PerPkg": "1", @@ -21869,7 +21877,7 @@ "Unit": "M3UPI" }, { - "BriefDescription": "Remote VNA Credits; Level < 5", + "BriefDescription": "Remote VNA Credits; Level < 5", "EventCode": "0x5B", "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5", "PerPkg": "1", @@ -24401,7 +24409,7 @@ "EventCode": "0x29", "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN", "PerPkg": "1", - "PublicDescription": "Count cases where flow control queue that sits between the Intel Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller)", + "PublicDescription": "Count cases where flow control queue that sits between the Intel(R) Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller)", "Unit": "M3UPI" }, { @@ -24756,11 +24764,11 @@ "Unit": "M2M" }, { - "BriefDescription": "Clocks of the Intel Ultra Path Interconnect (UPI)", + "BriefDescription": "Clocks of the Intel(R) Ultra Path Interconnect (UPI)", "EventCode": "0x1", "EventName": "UNC_UPI_CLOCKTICKS", "PerPkg": "1", - "PublicDescription": "Counts clockticks of the fixed frequency clock controlling the Intel Ultra Path Interconnect (UPI). This clock runs at1/8th the 'GT/s' speed of the UPI link. For example, a 9.6GT/s link will have a fixed Frequency of 1.2 Ghz.", + "PublicDescription": "Counts clockticks of the fixed frequency clock controlling the Intel(R) Ultra Path Interconnect (UPI). This clock runs at1/8th the 'GT/s' speed of the UPI link. For example, a 9.6GT/s link will have a fixed Frequency of 1.2 Ghz.", "Unit": "UPI LL" }, { @@ -24782,11 +24790,11 @@ "Unit": "UPI LL" }, { - "BriefDescription": "Data Response packets that go direct to Intel UPI", + "BriefDescription": "Data Response packets that go direct to Intel(R) UPI", "EventCode": "0x12", "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2U", "PerPkg": "1", - "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to Intel Ultra Path Interconnect (UPI) bypassing the CHA .", + "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to Intel(R) Ultra Path Interconnect (UPI) bypassing the CHA .", "UMask": "0x2", "Unit": "UPI LL" }, @@ -24855,11 +24863,11 @@ "Unit": "UPI LL" }, { - "BriefDescription": "Cycles Intel UPI is in L1 power mode (shutdown)", + "BriefDescription": "Cycles Intel(R) UPI is in L1 power mode (shutdown)", "EventCode": "0x21", "EventName": "UNC_UPI_L1_POWER_CYCLES", "PerPkg": "1", - "PublicDescription": "Counts cycles when the Intel Ultra Path Interconnect (UPI) is in L1 power mode. L1 is a mode that totally shuts down the UPI link. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdown.", + "PublicDescription": "Counts cycles when the Intel(R) Ultra Path Interconnect (UPI) is in L1 power mode. L1 is a mode that totally shuts down the UPI link. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdown.", "Unit": "UPI LL" }, { @@ -25021,11 +25029,11 @@ "Unit": "UPI LL" }, { - "BriefDescription": "Cycles the Rx of the Intel UPI is in L0p power mode", + "BriefDescription": "Cycles the Rx of the Intel(R) UPI is in L0p power mode", "EventCode": "0x25", "EventName": "UNC_UPI_RxL0P_POWER_CYCLES", "PerPkg": "1", - "PublicDescription": "Counts cycles when the receive side (Rx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.", + "PublicDescription": "Counts cycles when the receive side (Rx) of the Intel(R) Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.", "Unit": "UPI LL" }, { @@ -25218,7 +25226,7 @@ "EventCode": "0x8", "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT", "PerPkg": "1", - "PublicDescription": "Number of LLR Requests were transmitted. This should generally be <= the number of CRC errors detected. If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs.", + "PublicDescription": "Number of LLR Requests were transmitted. This should generally be <= the number of CRC errors detected. If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs.", "Unit": "UPI LL" }, { @@ -25250,7 +25258,7 @@ "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", "PerPkg": "1", - "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.", + "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel(R) Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.", "UMask": "0xf", "Unit": "UPI LL" }, @@ -25259,7 +25267,7 @@ "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", "PerPkg": "1", - "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.", + "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel(R) Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.", "UMask": "0x27", "Unit": "UPI LL" }, @@ -25583,11 +25591,11 @@ "Unit": "UPI LL" }, { - "BriefDescription": "Cycles in which the Tx of the Intel Ultra Path Interconnect (UPI) is in L0p power mode", + "BriefDescription": "Cycles in which the Tx of the Intel(R) Ultra Path Interconnect (UPI) is in L0p power mode", "EventCode": "0x27", "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", "PerPkg": "1", - "PublicDescription": "Counts cycles when the transmit side (Tx) of the Intel Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.", + "PublicDescription": "Counts cycles when the transmit side (Tx) of the Intel(R) Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.", "Unit": "UPI LL" }, { @@ -25759,7 +25767,7 @@ "EventCode": "0x41", "EventName": "UNC_UPI_TxL_BYPASSED", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link. However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR mode, increasing latency to transfer out to the link.", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel(R) Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link. However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR mode, increasing latency to transfer out to the link.", "Unit": "UPI LL" }, { @@ -25767,7 +25775,7 @@ "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", "PerPkg": "1", - "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel Ultra Path Interconnect (UPI) slots on this UPI unit.", + "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel(R) Ultra Path Interconnect (UPI) slots on this UPI unit.", "UMask": "0xf", "Unit": "UPI LL" }, @@ -25776,7 +25784,7 @@ "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", "PerPkg": "1", - "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel Ulra Path Interconnect (UPI) slots on this UPI unit.", + "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel(R) Ulra Path Interconnect (UPI) slots on this UPI unit.", "UMask": "0x27", "Unit": "UPI LL" }, @@ -26127,7 +26135,7 @@ "EventCode": "0x2", "EventName": "UPI_DATA_BANDWIDTH_TX", "PerPkg": "1", - "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel Ultra Path Interconnect (UPI) slots on this UPI unit.", + "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel(R) Ultra Path Interconnect (UPI) slots on this UPI unit.", "ScaleUnit": "7.11E-06Bytes", "UMask": "0xf", "Unit": "UPI LL" diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-power.json b/tools/perf/pmu-events/arch/x86/skylakex/uncore-power.json index 8e21dc3eff16..c6254af7a468 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-power.json @@ -143,7 +143,7 @@ "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", "PerPkg": "1", - "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", + "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", "Unit": "PCU" }, { @@ -151,7 +151,7 @@ "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", "PerPkg": "1", - "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", + "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", "Unit": "PCU" }, { @@ -159,7 +159,7 @@ "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", "PerPkg": "1", - "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", + "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", "Unit": "PCU" }, { -- cgit v1.2.3-58-ga151 From de44486fd46134e10c42f3acc09695e74ad91be8 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:27 -0800 Subject: perf vendor events intel: Refresh tigerlake events Update the tigerlake events from 1.08 to 1.10. Generation was done using https://github.com/intel/perfmon. Notable changes are new events and event descriptions, TMA metrics are updated to version 4.5, TMA info metrics are renamed from their node name to be lower case and prefixed by tma_info_, MetricThreshold expressions are added, smi_cost and transaction metric groups are added replicating existing hard coded metrics in stat-shadow. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-31-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- .../arch/x86/tigerlake/floating-point.json | 31 + .../pmu-events/arch/x86/tigerlake/pipeline.json | 18 + .../pmu-events/arch/x86/tigerlake/tgl-metrics.json | 1942 +++++++++++--------- .../arch/x86/tigerlake/uncore-other.json | 28 +- 5 files changed, 1198 insertions(+), 823 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 07f0b4758a83..bc2c4e756f44 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -27,7 +27,7 @@ GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v54,skylake,core GenuineIntel-6-55-[01234],v1.29,skylakex,core GenuineIntel-6-86,v1.20,snowridgex,core -GenuineIntel-6-8[CD],v1.08,tigerlake,core +GenuineIntel-6-8[CD],v1.10,tigerlake,core GenuineIntel-6-2C,v3,westmereep-dp,core GenuineIntel-6-25,v3,westmereep-sp,core GenuineIntel-6-2F,v3,westmereex,core diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json b/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json index 655342dadac6..63b5b56d1ed0 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json @@ -39,6 +39,14 @@ "SampleAfterValue": "100003", "UMask": "0x20" }, + { + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x18" + }, { "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "EventCode": "0xc7", @@ -55,6 +63,22 @@ "SampleAfterValue": "100003", "UMask": "0x80" }, + { + "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x60" + }, + { + "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "1000003", + "UMask": "0x3" + }, { "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "EventCode": "0xc7", @@ -70,5 +94,12 @@ "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x2" + }, + { + "BriefDescription": "Number of any Vector retired FP arithmetic instructions", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.VECTOR", + "SampleAfterValue": "1000003", + "UMask": "0xfc" } ] diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json b/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json index 9d43decd75ec..a0aeeb801fd7 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json @@ -158,6 +158,15 @@ "SampleAfterValue": "50021", "UMask": "0x20" }, + { + "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.RET", + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.", + "SampleAfterValue": "50021", + "UMask": "0x8" + }, { "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.", "EventCode": "0xec", @@ -383,6 +392,15 @@ "SampleAfterValue": "2000003", "UMask": "0x3" }, + { + "BriefDescription": "Clears speculative count", + "CounterMask": "1", + "EventCode": "0x0d", + "EventName": "INT_MISC.CLEARS_COUNT", + "PublicDescription": "Counts the number of speculative clears due to any type of branch misprediction or machine clears", + "SampleAfterValue": "500009", + "UMask": "0x1" + }, { "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", "EventCode": "0x0d", diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json b/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json index 7e22a9127156..4c80d6be6cf1 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json @@ -1,1230 +1,1532 @@ [ { - "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / SLOTS", - "MetricGroup": "PGO;TopdownL1;tma_L1_group", - "MetricName": "tma_frontend_bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", - "MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / SLOTS", - "MetricGroup": "Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_latency", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses", - "MetricExpr": "ICACHE_16B.IFDATA_STALL / CLKS", - "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_icache_misses", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", + "BriefDescription": "C10 residency percent per package", + "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C10_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", - "MetricExpr": "ICACHE_64B.IFTAG_STALL / CLKS", - "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_itlb_misses", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", + "BriefDescription": "C2 residency percent per package", + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C2_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", - "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / CLKS + tma_unknown_branches", - "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_branch_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "BriefDescription": "C3 residency percent per package", + "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C3_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_branch_resteers_group", - "MetricName": "tma_mispredicts_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES", + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears", - "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / CLKS", - "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_branch_resteers_group", - "MetricName": "tma_clears_resteers", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES", + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", - "MetricExpr": "10 * BACLEARS.ANY / CLKS", - "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_branch_resteers_group", - "MetricName": "tma_unknown_branches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (First fetch or hitting BPU capacity limit). Sample with: BACLEARS.ANY", + "BriefDescription": "C7 residency percent per core", + "MetricExpr": "cstate_core@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Core_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / CLKS", - "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_dsb_switches", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS", + "BriefDescription": "C7 residency percent per package", + "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C7_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", - "MetricExpr": "ILD_STALL.LCP / CLKS", - "MetricGroup": "FetchLat;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_lcp", - "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs.", + "BriefDescription": "C8 residency percent per package", + "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C8_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", - "MetricExpr": "3 * IDQ.MS_SWITCHES / CLKS", - "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_fetch_latency_group", - "MetricName": "tma_ms_switches", - "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES", + "BriefDescription": "C9 residency percent per package", + "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C9_Pkg_Residency", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", - "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)", - "MetricGroup": "FetchBW;Frontend;TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_bandwidth", - "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS", + "BriefDescription": "Percentage of cycles spent in System Management Interrupts.", + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", + "MetricGroup": "smi", + "MetricName": "smi_cycles", + "MetricThreshold": "smi_cycles > 0.1", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", - "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / CORE_CLKS / 2", - "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_fetch_bandwidth_group", - "MetricName": "tma_mite", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS", - "ScaleUnit": "100%" + "BriefDescription": "Number of SMI interrupts.", + "MetricExpr": "msr@smi@", + "MetricGroup": "smi", + "MetricName": "smi_num", + "ScaleUnit": "1SMI#" }, { - "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", - "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) / CORE_CLKS", - "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_mite_group", - "MetricName": "tma_decoder0_alone", + "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", + "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_4k_aliasing", + "MetricThreshold": "tma_4k_aliasing > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles where (only) 4 uops were delivered by the MITE pipeline", - "MetricExpr": "(cpu@IDQ.MITE_UOPS\\,cmask\\=4@ - cpu@IDQ.MITE_UOPS\\,cmask\\=5@) / CLKS", - "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_mite_group", - "MetricName": "tma_mite_4wide", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", + "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5 + UOPS_DISPATCHED.PORT_6) / (4 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_alu_op_utilization", + "MetricThreshold": "tma_alu_op_utilization > 0.6", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", - "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / CORE_CLKS / 2", - "MetricGroup": "DSB;FetchBW;TopdownL3;tma_fetch_bandwidth_group", - "MetricName": "tma_dsb", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", + "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", + "MetricExpr": "100 * ASSISTS.ANY / tma_info_slots", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_assists", + "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit", - "MetricExpr": "(LSD.CYCLES_ACTIVE - LSD.CYCLES_OK) / CORE_CLKS / 2", - "MetricGroup": "FetchBW;LSD;TopdownL3;tma_fetch_bandwidth_group", - "MetricName": "tma_lsd", - "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit. LSD typically does well sustaining Uop supply. However; in some rare cases; optimal uop-delivery could not be reached for small loops whose size (in terms of number of uops) does not suit well the LSD structure.", + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", + "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=1\\,edge@ / tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_backend_bound", + "MetricThreshold": "tma_backend_bound > 0.2", + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", "ScaleUnit": "100%" }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + tma_retiring), 0)", - "MetricGroup": "TopdownL1;tma_L1_group", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", + "MetricThreshold": "tma_bad_speculation > 0.15", "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", "ScaleUnit": "100%" }, + { + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions.", + "MetricExpr": "tma_light_operations * BR_INST_RETIRED.ALL_BRANCHES / (tma_retiring * tma_info_slots)", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_branch_instructions", + "MetricThreshold": "tma_branch_instructions > 0.1 & tma_light_operations > 0.6", + "ScaleUnit": "100%" + }, { "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL2;tma_L2_group;tma_bad_speculation_group", + "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", + "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction. These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: BR_MISP_RETIRED.ALL_BRANCHES. Related metrics: tma_info_branch_misprediction_cost, tma_info_mispredictions, tma_mispredicts_resteers", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", - "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)", - "MetricGroup": "BadSpec;MachineClears;TopdownL2;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_machine_clears", - "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers", + "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks + tma_unknown_branches", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_branch_resteers", + "MetricThreshold": "tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES", "ScaleUnit": "100%" }, { - "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", - "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * cpu@INT_MISC.RECOVERY_CYCLES\\,cmask\\=1\\,edge@ / SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_backend_bound", - "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", + "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", + "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group", + "MetricName": "tma_cisc", + "MetricThreshold": "tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound", - "MetricGroup": "Backend;TopdownL2;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_memory_bound", - "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears", + "MetricExpr": "(1 - BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT)) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks", + "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC", + "MetricName": "tma_clears_resteers", + "MetricThreshold": "tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", - "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / CLKS, 0)", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l1_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(49 * tma_info_average_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 48 * tma_info_average_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_contested_accesses", + "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", - "MetricExpr": "min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / CLKS", - "MetricGroup": "MemoryTLB;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_dtlb_load", - "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS", + "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", + "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)", + "MetricGroup": "Backend;Compute;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", - "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss", - "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group", - "MetricName": "tma_load_stlb_hit", + "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "48 * tma_info_average_frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_data_sharing", + "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_contested_accesses, tma_false_sharing, tma_machine_clears, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", - "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / CLKS", - "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_load_group", - "MetricName": "tma_load_stlb_miss", + "BriefDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder", + "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=1@ - cpu@INST_DECODED.DECODERS\\,cmask\\=2@) / tma_info_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_issueD0;tma_mite_group", + "MetricName": "tma_decoder0_alone", + "MetricThreshold": "tma_decoder0_alone > 0.1 & (tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 5 > 0.35))", + "PublicDescription": "This metric represents fraction of cycles where decoder-0 was the only active decoder. Related metrics: tma_few_uops_instructions", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", - "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_store_fwd_blk", - "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", + "MetricExpr": "ARITH.DIVIDER_ACTIVE / tma_info_clks", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_divider", + "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", - "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / CLKS", - "MetricGroup": "Offcore;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_lock_latency", - "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS", + "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks - tma_l2_bound", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_dram_bound", + "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", - "MetricExpr": "Load_Miss_Real_Latency * LD_BLOCKS.NO_SR / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_split_loads", - "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS", + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline", + "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / tma_info_core_clks / 2", + "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_dsb", + "MetricThreshold": "tma_dsb > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 5 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example; inefficient utilization of the DSB cache structure or bank conflict when reading from it; are categorized here.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset", - "MetricExpr": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS / CLKS", - "MetricGroup": "TopdownL4;tma_l1_bound_group", - "MetricName": "tma_4k_aliasing", - "PublicDescription": "This metric estimates how often memory load accesses were aliased by preceding stores (in program order) with a 4K address offset. False match is possible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidden by the out-of-order core and HW optimizations; hence a user may safely ignore a high value of this metric unless it manages to propagate up into parent nodes of the hierarchy (e.g. to L1_Bound).", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_clks", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_dsb_switches", + "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-end directly delivers Uops (micro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter latency and delivered higher bandwidth than the MITE (legacy instruction decode pipeline). Switching between the two pipelines can cause penalties hence this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DSB_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", - "MetricExpr": "L1D_PEND_MISS.FB_FULL / CLKS", - "MetricGroup": "MemoryBW;TopdownL4;tma_l1_bound_group", - "MetricName": "tma_fb_full", - "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory).", + "BriefDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses", + "MetricExpr": "min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_l1_bound_group", + "MetricName": "tma_dtlb_load", + "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Translation Look-aside Buffers) are processor caches for recently used entries out of the Page Tables that are used to map virtual- to physical-addresses by the operating system. This metric approximates the potential delay of demand loads missing the first-level data TLB (assuming worst case scenario with back to back misses to different pages). This includes hitting in the second-level TLB (STLB) as well as performing a hardware page walk on an STLB miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: tma_dtlb_store, tma_info_memory_data_tlbs", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", - "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS)", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l2_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS", + "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", + "MetricExpr": "(7 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_clks", + "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_store_bound_group", + "MetricName": "tma_dtlb_store", + "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, tma_info_memory_data_tlbs", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", - "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / CLKS", - "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_l3_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", + "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", + "MetricExpr": "54 * tma_info_average_frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_clks", + "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSyncxn;tma_store_bound_group", + "MetricName": "tma_false_sharing", + "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma_remote_cache", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses", - "MetricExpr": "(49 * Average_Frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 48 * Average_Frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_contested_accesses", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to contested accesses. Contested accesses occur when data written by one Logical Processor are read by another Logical Processor on a different Physical Core. Examples of contested accesses include synchronizations such as locks; true data sharing such as modified locked variables; and false sharing. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "BriefDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed", + "MetricExpr": "L1D_PEND_MISS.FB_FULL / tma_info_clks", + "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_issueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricName": "tma_fb_full", + "MetricThreshold": "tma_fb_full > 0.3", + "PublicDescription": "This metric does a *rough estimation* of how often L1D Fill Buffer unavailability limited additional L1D miss memory access requests to proceed. The higher the metric value; the deeper the memory hierarchy level the misses are satisfied from (metric values >1 are valid). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or external memory). Related metrics: tma_info_dram_bw_use, tma_info_memory_bandwidth, tma_mem_bandwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses", - "MetricExpr": "48 * Average_Frequency * (MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_data_sharing", - "PublicDescription": "This metric estimates fraction of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Data shared by multiple Logical Processors (even just read shared) may cause increased access latency due to cache coherency. Excessive data sharing can drastically harm multithreaded performance. Sample with: MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues", + "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)", + "MetricGroup": "FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group;tma_issueFB", + "MetricName": "tma_fetch_bandwidth", + "MetricThreshold": "tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 5 > 0.35", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend bandwidth issues. For example; inefficiencies at the instruction decoders; or restrictions for caching in the DSB (decoded uops cache) are categorized under Fetch Bandwidth. In such cases; the Frontend typically delivers suboptimal amount of uops to the Backend. Sample with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_switches, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb, tma_lcp", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", - "MetricExpr": "17.5 * Average_Frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / CLKS", - "MetricGroup": "MemoryLat;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_l3_hit_latency", - "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", + "BriefDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues", + "MetricExpr": "(5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / tma_info_slots", + "MetricGroup": "Frontend;TmaL2;TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_latency", + "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU was stalled due to Frontend latency issues. For example; instruction-cache misses; iTLB misses or fetch stalls after a branch misprediction are categorized under Frontend Latency. In such cases; the Frontend eventually delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", - "MetricExpr": "L1D_PEND_MISS.L2_STALL / CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_l3_bound_group", - "MetricName": "tma_sq_full", - "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). The Super Queue is used for requests to access the L2 cache or to go out to the Uncore.", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops", + "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer", + "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueD0", + "MetricName": "tma_few_uops_instructions", + "MetricThreshold": "tma_few_uops_instructions > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions. Related metrics: tma_decoder0_alone", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", - "MetricExpr": "CYCLE_ACTIVITY.STALLS_L3_MISS / CLKS + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / CLKS - tma_l2_bound", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_dram_bound", - "PublicDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads. Better caching can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_MISS_PS", + "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", + "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", + "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_fp_arith", + "MetricThreshold": "tma_fp_arith > 0.2 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_dram_bound_group", - "MetricName": "tma_mem_bandwidth", - "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that).", + "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", + "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_scalar", + "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", - "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / CLKS - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_dram_bound_group", - "MetricName": "tma_mem_latency", - "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that).", + "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", + "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@ / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_group;tma_issue2P", + "MetricName": "tma_fp_vector", + "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", - "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / CLKS", - "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_memory_bound_group", - "MetricName": "tma_store_bound", - "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS", + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_128b", + "MetricThreshold": "tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", - "MetricExpr": "(L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / CLKS", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_store_bound_group", - "MetricName": "tma_store_latency", - "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full)", + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_256b", + "MetricThreshold": "tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing", - "MetricExpr": "54 * Average_Frequency * OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM / CLKS", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_store_bound_group", - "MetricName": "tma_false_sharing", - "PublicDescription": "This metric roughly estimates how often CPU was handling synchronizations due to False Sharing. False Sharing is a multithreading hiccup; where multiple Logical Processors contend on different data-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (tma_retiring * tma_info_slots)", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector_group;tma_issue2P", + "MetricName": "tma_fp_vector_512b", + "MetricThreshold": "tma_fp_vector_512b > 0.1 & (tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric represents rate of split store accesses", - "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / CORE_CLKS", - "MetricGroup": "TopdownL4;tma_store_bound_group", - "MetricName": "tma_split_stores", - "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS", + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", + "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UOP_DROPPING / tma_info_slots", + "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.15", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Pipeline_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. Sample with: FRONTEND_RETIRED.LATENCY_GE_4_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores", - "MetricExpr": "9 * OCR.STREAMING_WR.ANY_RESPONSE / CLKS", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_store_bound_group", - "MetricName": "tma_streaming_stores", - "PublicDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck. Sample with: OCR.STREAMING_WR.ANY_RESPONSE", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences", + "MetricExpr": "tma_microcode_sequencer + tma_retiring * (UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=1@) / IDQ.MITE_UOPS", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_heavy_operations", + "MetricThreshold": "tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro-coded sequences. This highly-correlates with the uop length of these instructions/sequences.", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses", - "MetricExpr": "(7 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE) / CORE_CLKS", - "MetricGroup": "MemoryTLB;TopdownL4;tma_store_bound_group", - "MetricName": "tma_dtlb_store", - "PublicDescription": "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store misses. As with ordinary data caching; focus on improving data locality and reducing working-set size to reduce DTLB overhead. Additionally; consider using profile-guided optimization (PGO) to collocate frequently-used data on the same page. Try using larger page sizes for large amounts of frequently-used data. Sample with: MEM_INST_RETIRED.STLB_MISS_STORES_PS", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses", + "MetricExpr": "ICACHE_16B.IFDATA_STALL / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;IcMiss;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_icache_misses", + "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RETIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", "ScaleUnit": "100%" }, { - "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", - "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss", - "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group", - "MetricName": "tma_store_stlb_hit", - "ScaleUnit": "100%" + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "tma_info_turbo_utilization * TSC / 1e9 / duration_time", + "MetricGroup": "Power;Summary", + "MetricName": "tma_info_average_frequency" }, { - "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", - "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / CORE_CLKS", - "MetricGroup": "MemoryTLB;TopdownL5;tma_dtlb_store_group", - "MetricName": "tma_store_stlb_miss", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB;tma_issueBC", + "MetricName": "tma_info_big_code", + "MetricThreshold": "tma_info_big_code > 20", + "PublicDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses). Related metrics: tma_info_branching_overhead" }, { - "BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck", - "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)", - "MetricGroup": "Backend;Compute;TopdownL2;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_core_bound", - "PublicDescription": "This metric represents fraction of slots where Core non-memory issues were of a bottleneck. Shortage in hardware compute resources; or dependencies in software's instructions are both categorized under Core Bound. Hence it may indicate the machine ran out of an out-of-order resource; certain execution units are overloaded or dependencies in program's data- or instruction-flow are limiting the performance (e.g. FP-chained long-latency arithmetic operations).", - "ScaleUnit": "100%" + "BriefDescription": "Branch instructions per taken branch.", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_bptkbranch" }, { - "BriefDescription": "This metric represents fraction of cycles where the Divider unit was active", - "MetricExpr": "ARITH.DIVIDER_ACTIVE / CLKS", - "MetricGroup": "TopdownL3;tma_core_bound_group", - "MetricName": "tma_divider", - "PublicDescription": "This metric represents fraction of cycles where the Divider unit was active. Divide and square root instructions are performed by the Divider unit and can take considerably longer latency than integer or Floating Point addition; subtraction; or multiplication. Sample with: ARITH.DIVIDER_ACTIVE", - "ScaleUnit": "100%" + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * tma_info_slots / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts;tma_issueBM", + "MetricName": "tma_info_branch_misprediction_cost", + "PublicDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear). Related metrics: tma_branch_mispredicts, tma_info_mispredictions, tma_mispredicts_resteers" }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", - "MetricExpr": "((cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CLKS if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / CLKS)", - "MetricGroup": "PortsUtil;TopdownL3;tma_core_bound_group", - "MetricName": "tma_ports_utilization", - "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "MetricExpr": "100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL)) / tma_info_slots)", + "MetricGroup": "Ret;tma_issueBC", + "MetricName": "tma_info_branching_overhead", + "MetricThreshold": "tma_info_branching_overhead > 10", + "PublicDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls). Related metrics: tma_info_big_code" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ / CLKS + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_0", - "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_callret" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations", - "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / CLKS", - "MetricGroup": "TopdownL5;tma_ports_utilized_0_group", - "MetricName": "tma_serializing_operation", - "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD", - "ScaleUnit": "100%" + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline", + "MetricName": "tma_info_clks" }, { - "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions", - "MetricExpr": "140 * MISC_RETIRED.PAUSE_INST / CLKS", - "MetricGroup": "TopdownL6;tma_serializing_operation_group", - "MetricName": "tma_slow_pause", - "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: MISC_RETIRED.PAUSE_INST", - "ScaleUnit": "100%" + "BriefDescription": "STLB (2nd level TLB) code speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Fed;MemoryTLB", + "MetricName": "tma_info_code_stlb_mpki" }, { - "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued", - "MetricExpr": "CLKS * UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY", - "MetricGroup": "TopdownL5;tma_ports_utilized_0_group", - "MetricName": "tma_mixing_vectors", - "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic.", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "tma_info_cond_nt" }, { - "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "EXE_ACTIVITY.1_PORTS_UTIL / CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_1", - "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of branches that are taken conditionals", + "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "tma_info_cond_tk" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "EXE_ACTIVITY.2_PORTS_UTIL / CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_2", - "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL", - "ScaleUnit": "100%" + "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", + "MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if tma_info_smt_2t_utilization > 0.5 else 0)", + "MetricGroup": "Cor;SMT", + "MetricName": "tma_info_core_bound_likely", + "MetricThreshold": "tma_info_core_bound_likely > 0.5" }, { - "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", - "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / CLKS", - "MetricGroup": "PortsUtil;TopdownL4;tma_ports_utilization_group", - "MetricName": "tma_ports_utilized_3m", - "PublicDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3", - "ScaleUnit": "100%" + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED", + "MetricGroup": "SMT", + "MetricName": "tma_info_core_clks" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.", - "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + UOPS_DISPATCHED.PORT_5 + UOPS_DISPATCHED.PORT_6) / (4 * CORE_CLKS)", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_alu_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_core_clks", + "MetricGroup": "Ret;SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_coreipc" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch) Sample with: UOPS_DISPATCHED.PORT_0", - "MetricExpr": "UOPS_DISPATCHED.PORT_0 / CORE_CLKS", - "MetricGroup": "Compute;TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_0", - "ScaleUnit": "100%" + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / tma_info_ipc", + "MetricGroup": "Mem;Pipeline", + "MetricName": "tma_info_cpi" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU) Sample with: UOPS_DISPATCHED.PORT_1", - "MetricExpr": "UOPS_DISPATCHED.PORT_1 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_1", - "ScaleUnit": "100%" + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "HPC;Summary", + "MetricName": "tma_info_cpu_utilization" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU) Sample with: UOPS_DISPATCHED.PORT_5", - "MetricExpr": "UOPS_DISPATCHED.PORT_5 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_5", - "ScaleUnit": "100%" + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD / OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_data_l2_mlp" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU) Sample with: UOPS_DISPATCHED.PORT_6", - "MetricExpr": "UOPS_DISPATCHED.PORT_6 / CORE_CLKS", - "MetricGroup": "TopdownL6;tma_alu_op_utilization_group", - "MetricName": "tma_port_6", - "ScaleUnit": "100%" + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1e6 / duration_time / 1e3", + "MetricGroup": "HPC;Mem;MemoryBW;SoC;tma_issueBW", + "MetricName": "tma_info_dram_bw_use", + "PublicDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]. Related metrics: tma_fb_full, tma_info_memory_bandwidth, tma_mem_bandwidth, tma_sq_full" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations Sample with: UOPS_DISPATCHED.PORT_2_3", - "MetricExpr": "UOPS_DISPATCHED.PORT_2_3 / (2 * CORE_CLKS)", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_load_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / UOPS_ISSUED.ANY", + "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", + "MetricName": "tma_info_dsb_coverage", + "MetricThreshold": "tma_info_dsb_coverage < 0.7 & tma_info_ipc / 5 > 0.35", + "PublicDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_misses, tma_info_iptb, tma_lcp" }, { - "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations Sample with: UOPS_DISPATCHED.PORT_7_8", - "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * CORE_CLKS)", - "MetricGroup": "TopdownL5;tma_ports_utilized_3m_group", - "MetricName": "tma_store_op_utilization", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck", + "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_lsd + tma_mite))", + "MetricGroup": "DSBmiss;Fed;tma_issueFB", + "MetricName": "tma_info_dsb_misses", + "MetricThreshold": "tma_info_dsb_misses > 10", + "PublicDescription": "Total pipeline cost of DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_iptb, tma_lcp" }, { - "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * SLOTS", - "MetricGroup": "TopdownL1;tma_L1_group", - "MetricName": "tma_retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS", - "ScaleUnit": "100%" + "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@", + "MetricGroup": "DSBmiss", + "MetricName": "tma_info_dsb_switch_cost" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", - "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_light_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", - "ScaleUnit": "100%" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-thread", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "tma_info_execute" }, { - "BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired)", - "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", - "MetricGroup": "HPC;TopdownL3;tma_light_operations_group", - "MetricName": "tma_fp_arith", - "PublicDescription": "This metric represents overall arithmetic floating-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may exceed its parent due to use of \"Uops\" CountDomain and FMA double-counting.", - "ScaleUnit": "100%" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "tma_info_execute_per_issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." }, { - "BriefDescription": "This metric serves as an approximation of legacy x87 usage", - "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD", - "MetricGroup": "Compute;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_x87_use", - "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", - "ScaleUnit": "100%" + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_fb_hpki" }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) / (tma_retiring * SLOTS)", - "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_fp_scalar", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction the CPU has retired. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_fetch_upc" }, { - "BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths", - "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (tma_retiring * SLOTS)", - "MetricGroup": "Compute;Flops;TopdownL4;tma_fp_arith_group", - "MetricName": "tma_fp_vector", - "PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction the CPU has retired aggregated across all vector widths. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * cpu@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE\\,umask\\=0x18@ + 8 * cpu@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE\\,umask\\=0x60@ + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / tma_info_core_clks", + "MetricGroup": "Flops;Ret", + "MetricName": "tma_info_flopc" }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors", - "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE) / (tma_retiring * SLOTS)", - "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group", - "MetricName": "tma_fp_vector_128b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 128-bit wide vectors. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@) / (2 * tma_info_core_clks)", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_fp_arith_utilization", + "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors", - "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) / (tma_retiring * SLOTS)", - "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group", - "MetricName": "tma_fp_vector_256b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 256-bit wide vectors. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Giga Floating Point Operations Per Second", + "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * cpu@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE\\,umask\\=0x18@ + 8 * cpu@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE\\,umask\\=0x60@ + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_gflops", + "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." }, { - "BriefDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors", - "MetricExpr": "(FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / (tma_retiring * SLOTS)", - "MetricGroup": "Compute;Flops;TopdownL5;tma_fp_vector_group", - "MetricName": "tma_fp_vector_512b", - "PublicDescription": "This metric approximates arithmetic FP vector uops fraction the CPU has retired for 512-bit wide vectors. May overcount due to FMA double counting.", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck", + "MetricExpr": "100 * (tma_fetch_latency * tma_icache_misses / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", + "MetricGroup": "Fed;FetchLat;IcMiss;tma_issueFL", + "MetricName": "tma_info_ic_misses", + "MetricThreshold": "tma_info_ic_misses > 5", + "PublicDescription": "Total pipeline cost of Instruction Cache misses - subset of the Big_Code Bottleneck. Related metrics: " }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", - "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group", - "MetricName": "tma_memory_operations", - "ScaleUnit": "100%" + "BriefDescription": "Average Latency for L1 instruction cache misses", + "MetricExpr": "ICACHE_16B.IFDATA_STALL / cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@", + "MetricGroup": "Fed;FetchLat;IcMiss", + "MetricName": "tma_info_icache_miss_latency" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring branch instructions.", - "MetricExpr": "tma_light_operations * BR_INST_RETIRED.ALL_BRANCHES / (tma_retiring * SLOTS)", - "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group", - "MetricName": "tma_branch_instructions", - "ScaleUnit": "100%" + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", + "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", + "MetricName": "tma_info_ilp" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions", - "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (tma_retiring * SLOTS)", - "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group", - "MetricName": "tma_nop_instructions", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP", - "ScaleUnit": "100%" + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_big_code", + "MetricGroup": "Fed;FetchBW;Frontend", + "MetricName": "tma_info_instruction_fetch_bw", + "MetricThreshold": "tma_info_instruction_fetch_bw > 20" }, { - "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", - "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_branch_instructions + tma_nop_instructions))", - "MetricGroup": "Pipeline;TopdownL3;tma_light_operations_group", - "MetricName": "tma_other_light_ops", - "ScaleUnit": "100%" + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;tma_L1_group", + "MetricName": "tma_info_instructions", + "PublicDescription": "Total number of retired Instructions. Sample with: INST_RETIRED.PREC_DIST" }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences", - "MetricExpr": "tma_microcode_sequencer + tma_retiring * (UOPS_DECODED.DEC0 - cpu@UOPS_DECODED.DEC0\\,cmask\\=1@) / IDQ.MITE_UOPS", - "MetricGroup": "Retire;TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_heavy_operations", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring heavy-weight operations -- instructions that require two or more uops or microcoded sequences. This highly-correlates with the uop length of these instructions/sequences.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=0xfc@)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_iparith", + "MetricThreshold": "tma_info_iparith < 10", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." }, { - "BriefDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops", - "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer", - "MetricGroup": "TopdownL3;tma_heavy_operations_group", - "MetricName": "tma_few_uops_instructions", - "PublicDescription": "This metric represents fraction of slots where the CPU was retiring instructions that that are decoder into two or up to ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number of uops in such instructions.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx128", + "MetricThreshold": "tma_info_iparith_avx128 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", - "MetricExpr": "tma_retiring * SLOTS / UOPS_ISSUED.ANY * IDQ.MS_UOPS / SLOTS", - "MetricGroup": "MicroSeq;TopdownL3;tma_heavy_operations_group", - "MetricName": "tma_microcode_sequencer", - "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx256", + "MetricThreshold": "tma_info_iparith_avx256 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists", - "MetricExpr": "100 * ASSISTS.ANY / SLOTS", - "MetricGroup": "TopdownL4;tma_microcode_sequencer_group", - "MetricName": "tma_assists", - "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_iparith_avx512", + "MetricThreshold": "tma_info_iparith_avx512 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction", - "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", - "MetricGroup": "TopdownL4;tma_microcode_sequencer_group", - "MetricName": "tma_cisc", - "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.", - "ScaleUnit": "100%" + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_iparith_scalar_dp", + "MetricThreshold": "tma_info_iparith_scalar_dp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", - "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "Mispredictions" + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_iparith_scalar_sp", + "MetricThreshold": "tma_info_iparith_scalar_sp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." }, { - "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks", - "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "Memory_Bandwidth" + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "tma_info_ipbranch", + "MetricThreshold": "tma_info_ipbranch < 8" }, { - "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)", - "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound))", - "MetricGroup": "Mem;MemoryLat;Offcore", - "MetricName": "Memory_Latency" + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_clks", + "MetricGroup": "Ret;Summary", + "MetricName": "tma_info_ipc" }, { - "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", - "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))", - "MetricGroup": "Mem;MemoryTLB;Offcore", - "MetricName": "Memory_Data_TLBs" + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_ipcall", + "MetricThreshold": "tma_info_ipcall < 200" }, { - "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", - "MetricExpr": "100 * ((BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL)) / SLOTS)", - "MetricGroup": "Ret", - "MetricName": "Branching_Overhead" + "BriefDescription": "Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "tma_info_ipdsb_miss_ret", + "MetricThreshold": "tma_info_ipdsb_miss_ret < 50" }, { - "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", - "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", - "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB", - "MetricName": "Big_Code" + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "tma_info_ipfarbranch", + "MetricThreshold": "tma_info_ipfarbranch < 1e6" }, { - "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", - "MetricExpr": "100 * (tma_frontend_bound - tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) - Big_Code", - "MetricGroup": "Fed;FetchBW;Frontend", - "MetricName": "Instruction_Fetch_BW" + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\=0x03@ + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * cpu@FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE\\,umask\\=0x18@ + 8 * cpu@FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE\\,umask\\=0x60@ + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_ipflop", + "MetricThreshold": "tma_info_ipflop < 10" }, { - "BriefDescription": "Instructions Per Cycle (per Logical Processor)", - "MetricExpr": "INST_RETIRED.ANY / CLKS", - "MetricGroup": "Ret;Summary", - "MetricName": "IPC" + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipload", + "MetricThreshold": "tma_info_ipload < 3" }, { - "BriefDescription": "Uops Per Instruction", - "MetricExpr": "tma_retiring * SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Ret;Retire", - "MetricName": "UPI" + "BriefDescription": "Instructions per retired mispredicts for conditional non-taken branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_NTAKEN", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_cond_ntaken", + "MetricThreshold": "tma_info_ipmisp_cond_ntaken < 200" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "tma_retiring * SLOTS / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW", - "MetricName": "UpTB" + "BriefDescription": "Instructions per retired mispredicts for conditional taken branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_cond_taken", + "MetricThreshold": "tma_info_ipmisp_cond_taken < 200" }, { - "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / IPC", - "MetricGroup": "Mem;Pipeline", - "MetricName": "CPI" + "BriefDescription": "Instructions per retired mispredicts for indirect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_indirect", + "MetricThreshold": "tma_info_ipmisp_indirect < 1e3" }, { - "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Pipeline", - "MetricName": "CLKS" + "BriefDescription": "Instructions per retired mispredicts for return branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RET", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_ipmisp_ret", + "MetricThreshold": "tma_info_ipmisp_ret < 500" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", - "MetricExpr": "TOPDOWN.SLOTS", - "MetricGroup": "tma_L1_group", - "MetricName": "SLOTS" + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "tma_info_ipmispredict", + "MetricThreshold": "tma_info_ipmispredict < 200" }, { - "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", - "MetricExpr": "(SLOTS / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)", - "MetricGroup": "SMT;tma_L1_group", - "MetricName": "Slots_Utilization" + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "tma_info_ipstore", + "MetricThreshold": "tma_info_ipstore < 8" }, { - "BriefDescription": "The ratio of Executed- by Issued-Uops", - "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", - "MetricGroup": "Cor;Pipeline", - "MetricName": "Execute_per_Issue", - "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." + "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", + "MetricGroup": "Prefetches", + "MetricName": "tma_info_ipswpf", + "MetricThreshold": "tma_info_ipswpf < 100" }, { - "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / CORE_CLKS", - "MetricGroup": "Ret;SMT;tma_L1_group", - "MetricName": "CoreIPC" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", + "MetricName": "tma_info_iptb", + "MetricThreshold": "tma_info_iptb < 11", + "PublicDescription": "Instruction per taken branch. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_dsb_misses, tma_lcp" }, { - "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / CORE_CLKS", - "MetricGroup": "Flops;Ret", - "MetricName": "FLOPc" - }, - { - "BriefDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width)", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)) / (2 * CORE_CLKS)", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "FP_Arith_Utilization", - "PublicDescription": "Actual per-core usage of the Floating Point non-X87 execution units (regardless of precision or vector-width). Values > 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less common)." + "BriefDescription": "Instructions per speculative Unknown Branch Misprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "tma_info_instructions / BACLEARS.ANY", + "MetricGroup": "Fed", + "MetricName": "tma_info_ipunknown_branch" }, { - "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core", - "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", - "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", - "MetricName": "ILP" + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_jump" }, { - "BriefDescription": "Probability of Core Bound bottleneck hidden by SMT-profiling artifacts", - "MetricExpr": "((1 - tma_core_bound / tma_ports_utilization if tma_core_bound < tma_ports_utilization else 1) if SMT_2T_Utilization > 0.5 else 0)", - "MetricGroup": "Cor;SMT", - "MetricName": "Core_Bound_Likely" + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_cpi" }, { - "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", - "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED", - "MetricGroup": "SMT", - "MetricName": "CORE_CLKS" + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", + "MetricName": "tma_info_kernel_utilization", + "MetricThreshold": "tma_info_kernel_utilization > 0.05" }, { - "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", - "MetricGroup": "InsType", - "MetricName": "IpLoad" + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw" }, { - "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", - "MetricGroup": "InsType", - "MetricName": "IpStore" + "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "tma_info_l1d_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l1d_cache_fill_bw_1t" }, { - "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Fed;InsType", - "MetricName": "IpBranch" + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l1mpki" }, { - "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "IpCall" + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l1mpki_load" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", - "MetricName": "IpTB" + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw" }, { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fed;PGO", - "MetricName": "BpTkBranch" + "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "tma_info_l2_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l2_cache_fill_bw_1t" }, { - "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)", - "MetricGroup": "Flops;InsType", - "MetricName": "IpFLOP" + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2hpki_all" }, { - "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE))", - "MetricGroup": "Flops;InsType", - "MetricName": "IpArith", - "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2hpki_load" }, { - "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", - "MetricGroup": "Flops;FpScalar;InsType", - "MetricName": "IpArith_Scalar_SP", - "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Backend;CacheMisses;Mem", + "MetricName": "tma_info_l2mpki" }, { - "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", - "MetricGroup": "Flops;FpScalar;InsType", - "MetricName": "IpArith_Scalar_DP", - "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem;Offcore", + "MetricName": "tma_info_l2mpki_all" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX128", - "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "L2 cache true code cacheline misses per kilo instruction", + "MetricExpr": "1e3 * FRONTEND_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss", + "MetricName": "tma_info_l2mpki_code" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX256", - "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "L2 cache speculative code cacheline misses per kilo instruction", + "MetricExpr": "1e3 * L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss", + "MetricName": "tma_info_l2mpki_code_all" }, { - "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE)", - "MetricGroup": "Flops;FpVector;InsType", - "MetricName": "IpArith_AVX512", - "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l2mpki_load" }, { - "BriefDescription": "Instructions per Software prefetch instruction (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umask\\=0xF@", - "MetricGroup": "Prefetches", - "MetricName": "IpSWPF" + "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_l3_cache_access_bw" }, { - "BriefDescription": "Total number of retired Instructions Sample with: INST_RETIRED.PREC_DIST", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary;tma_L1_group", - "MetricName": "Instructions" + "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_l3_cache_access_bw", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_l3_cache_access_bw_1t" }, { - "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", - "MetricExpr": "tma_retiring * SLOTS / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@", - "MetricGroup": "Pipeline;Ret", - "MetricName": "Retire" + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw" }, { - "BriefDescription": "", - "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@", - "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", - "MetricName": "Execute" + "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "tma_info_l3_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_l3_cache_fill_bw_1t" }, { - "BriefDescription": "Average number of Uops issued by front-end when it issued something", - "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@", - "MetricGroup": "Fed;FetchBW", - "MetricName": "Fetch_UpC" + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Mem", + "MetricName": "tma_info_l3mpki" }, { - "BriefDescription": "Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache)", - "MetricExpr": "LSD.UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "Fed;LSD", - "MetricName": "LSD_Coverage" + "BriefDescription": "Average Latency for L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore", + "MetricName": "tma_info_load_l2_miss_latency" }, { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "DSB;Fed;FetchBW", - "MetricName": "DSB_Coverage" + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,cmask\\=1@", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_load_l2_mlp" }, { - "BriefDescription": "Average number of cycles of a switch from the DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details.", - "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWITCHES.PENALTY_CYCLES\\,cmask\\=1\\,edge@", - "MetricGroup": "DSBmiss", - "MetricName": "DSB_Switch_Cost" + "BriefDescription": "Average Latency for L3 cache miss demand Loads", + "MetricExpr": "cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,umask\\=0x10@ / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore", + "MetricName": "tma_info_load_l3_miss_latency" }, { - "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset of the Instruction_Fetch_BW Bottleneck.", - "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tma_lsd + tma_mite))", - "MetricGroup": "DSBmiss;Fed", - "MetricName": "DSB_Misses" + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "tma_info_load_miss_real_latency" }, { - "BriefDescription": "Number of Instructions per non-speculative DSB miss (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", - "MetricGroup": "DSBmiss;Fed", - "MetricName": "IpDSB_Miss_Ret" + "BriefDescription": "STLB (2nd level TLB) data load speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_load_stlb_mpki" }, { - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BadSpec;BrMispredicts", - "MetricName": "IpMispredict" + "BriefDescription": "Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache)", + "MetricExpr": "LSD.UOPS / UOPS_ISSUED.ANY", + "MetricGroup": "Fed;LSD", + "MetricName": "tma_info_lsd_coverage" }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricExpr": "(tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) * SLOTS / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;BrMispredicts", - "MetricName": "Branch_Misprediction_Cost" + "BriefDescription": "Average number of parallel data read requests to external memory", + "MetricExpr": "UNC_ARB_DAT_OCCUPANCY.RD / UNC_ARB_DAT_OCCUPANCY.RD@cmask\\=1@", + "MetricGroup": "Mem;MemoryBW;SoC", + "MetricName": "tma_info_mem_parallel_reads", + "PublicDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches" }, { - "BriefDescription": "Fraction of branches that are non-taken conditionals", - "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches;CodeGen;PGO", - "MetricName": "Cond_NT" + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds)", + "MetricExpr": "(UNC_ARB_TRK_OCCUPANCY.RD + UNC_ARB_DAT_OCCUPANCY.RD) / UNC_ARB_TRK_REQUESTS.RD", + "MetricGroup": "Mem;MemoryLat;SoC", + "MetricName": "tma_info_mem_read_latency", + "PublicDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches. ([RKL+]memory-controller only)" }, { - "BriefDescription": "Fraction of branches that are taken conditionals", - "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches;CodeGen;PGO", - "MetricName": "Cond_TK" + "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)", + "MetricExpr": "(UNC_ARB_TRK_OCCUPANCY.ALL + UNC_ARB_DAT_OCCUPANCY.RD) / arb@event\\=0x81\\,umask\\=0x1@", + "MetricGroup": "Mem;SoC", + "MetricName": "tma_info_mem_request_latency" }, { - "BriefDescription": "Fraction of branches that are CALL or RET", - "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN) / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches", - "MetricName": "CallRet" + "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks", + "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full))) + tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk))", + "MetricGroup": "Mem;MemoryBW;Offcore;tma_issueBW", + "MetricName": "tma_info_memory_bandwidth", + "MetricThreshold": "tma_info_memory_bandwidth > 20", + "PublicDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_mem_bandwidth, tma_sq_full" }, { - "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", - "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Bad;Branches", - "MetricName": "Jump" + "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", + "MetricExpr": "100 * tma_memory_bound * (tma_l1_bound / max(tma_memory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))", + "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", + "MetricName": "tma_info_memory_data_tlbs", + "MetricThreshold": "tma_info_memory_data_tlbs > 20", + "PublicDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store" }, { - "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", - "MetricExpr": "1 - (Cond_NT + Cond_TK + CallRet + Jump)", - "MetricGroup": "Bad;Branches", - "MetricName": "Other_Branches" + "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)", + "MetricExpr": "100 * tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound))", + "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", + "MetricName": "tma_info_memory_latency", + "MetricThreshold": "tma_info_memory_latency > 20", + "PublicDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches). Related metrics: tma_l3_hit_latency, tma_mem_latency" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)", - "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT)", - "MetricGroup": "Mem;MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency" + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "MetricExpr": "100 * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", + "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", + "MetricName": "tma_info_mispredictions", + "MetricThreshold": "tma_info_mispredictions > 20", + "PublicDescription": "Total pipeline cost of Branch Misprediction related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_branch_misprediction_cost, tma_mispredicts_resteers" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss", "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", "MetricGroup": "Mem;MemoryBW;MemoryBound", - "MetricName": "MLP" + "MetricName": "tma_info_mlp", + "PublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)" }, { - "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI" + "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", + "MetricExpr": "1 - (tma_info_cond_nt + tma_info_cond_tk + tma_info_callret + tma_info_jump)", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_other_branches" }, { - "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L1MPKI_Load" + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (2 * tma_info_core_clks)", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_page_walks_utilization", + "MetricThreshold": "tma_info_page_walks_utilization > 0.5" }, { - "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Backend;CacheMisses;Mem", - "MetricName": "L2MPKI" + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0", + "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / tma_info_core_clks", + "MetricGroup": "Power", + "MetricName": "tma_info_power_license0_utilization", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes." }, { - "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all request types (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem;Offcore", - "MetricName": "L2MPKI_All" + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1", + "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / tma_info_core_clks", + "MetricGroup": "Power", + "MetricName": "tma_info_power_license1_utilization", + "MetricThreshold": "tma_info_power_license1_utilization > 0.5", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions." }, { - "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2MPKI_Load" + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)", + "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / tma_info_core_clks", + "MetricGroup": "Power", + "MetricName": "tma_info_power_license2_utilization", + "MetricThreshold": "tma_info_power_license2_utilization > 0.5", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions." }, { - "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", - "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2HPKI_All" + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.", + "MetricExpr": "tma_retiring * tma_info_slots / cpu@UOPS_RETIRED.SLOTS\\,cmask\\=1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "tma_info_retire" }, { - "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", - "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L2HPKI_Load" + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "TOPDOWN.SLOTS", + "MetricGroup": "TmaL1;tma_L1_group", + "MetricName": "tma_info_slots" }, { - "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "L3MPKI" + "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", + "MetricExpr": "(tma_info_slots / (TOPDOWN.SLOTS / 2) if #SMT_on else 1)", + "MetricGroup": "SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_slots_utilization" }, { - "BriefDescription": "Fill Buffer (FB) hits per kilo instructions for retired demand loads (L1D misses that merge into ongoing miss-handling entries)", - "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Mem", - "MetricName": "FB_HPKI" + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)", + "MetricGroup": "SMT", + "MetricName": "tma_info_smt_2t_utilization" }, { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING) / (2 * CORE_CLKS)", + "BriefDescription": "STLB (2nd level TLB) data store speculative misses per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", "MetricGroup": "Mem;MemoryTLB", - "MetricName": "Page_Walks_Utilization" + "MetricName": "tma_info_store_stlb_mpki" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW" + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "tma_info_clks / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power", + "MetricName": "tma_info_turbo_utilization" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW" + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "tma_retiring * tma_info_slots / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire", + "MetricName": "tma_info_uoppi", + "MetricThreshold": "tma_info_uoppi > 1.05" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "tma_retiring * tma_info_slots / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "tma_info_uptb", + "MetricThreshold": "tma_info_uptb < 7.5" }, { - "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW" + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses", + "MetricExpr": "ICACHE_64B.IFTAG_STALL / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;MemoryTLB;TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTEND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]", - "MetricExpr": "L1D_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L1D_Cache_Fill_BW_1T" + "BriefDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache", + "MetricExpr": "max((CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS) / tma_info_clks, 0)", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_issueL1;tma_issueMC;tma_memory_bound_group", + "MetricName": "tma_l1_bound", + "MetricThreshold": "tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled without loads missing the L1 data cache. The L1 data cache typically has the shortest latency. However; in certain cases like loads blocked on older stores; a load might suffer due to high latency even though it is being satisfied by the L1. Another example is loads who miss in the TLB. These cases are characterized by execution unit stalls; while some non-completed demand load lives in the machine without having that demand load missing the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB_HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches, tma_ports_utilized_1", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]", - "MetricExpr": "L2_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L2_Cache_Fill_BW_1T" + "BriefDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks)", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l2_bound", + "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 misses/L2 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L2_HIT_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Fill_BW", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "L3_Cache_Fill_BW_1T" + "BriefDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS) / tma_info_clks", + "MetricGroup": "CacheMisses;MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_l3_bound", + "MetricThreshold": "tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was stalled due to loads accesses to L3 cache or contended with a sibling Core. Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]", - "MetricExpr": "L3_Cache_Access_BW", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "L3_Cache_Access_BW_1T" + "BriefDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited)", + "MetricExpr": "17.5 * tma_info_average_frequency * MEM_LOAD_RETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_clks", + "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_l3_bound_group", + "MetricName": "tma_l3_hit_latency", + "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles with demand load accesses that hit the L3 cache under unloaded scenarios (possibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3 hits) will improve the latency; reduce contention with sibling physical cores and increase performance. Note the value of this node may overlap with its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tma_info_memory_latency, tma_mem_latency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average CPU Utilization", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", - "MetricGroup": "HPC;Summary", - "MetricName": "CPU_Utilization" + "BriefDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs)", + "MetricExpr": "ILD_STALL.LCP / tma_info_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueFB", + "MetricName": "tma_lcp", + "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles CPU was stalled due to Length Changing Prefixes (LCPs). Using proper compiler flags or Intel Compiler by default will certainly avoid this. #Link: Optimization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_bandwidth, tma_info_dsb_coverage, tma_info_dsb_misses, tma_info_iptb", + "ScaleUnit": "100%" }, { - "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", - "MetricExpr": "Turbo_Utilization * TSC / 1e9 / duration_time", - "MetricGroup": "Power;Summary", - "MetricName": "Average_Frequency" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation)", + "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)", + "MetricGroup": "Retire;TmaL2;TopdownL2;tma_L2_group;tma_retiring_group", + "MetricName": "tma_light_operations", + "MetricThreshold": "tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring light-weight operations -- instructions that require no more than one uop (micro-operation). This correlates with total number of instructions used by the program. A uops-per-instruction (see UopPI metric) ratio of 1 or less should be expected for decently optimized software running on Intel Core/Xeon products. While this often indicates efficient X86 instructions were executed; high value does not necessarily mean better performance cannot be achieved. Sample with: INST_RETIRED.PREC_DIST", + "ScaleUnit": "100%" }, { - "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * (FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE) + 8 * (FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1e9 / duration_time", - "MetricGroup": "Cor;Flops;HPC", - "MetricName": "GFLOPs", - "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine." + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations", + "MetricExpr": "UOPS_DISPATCHED.PORT_2_3 / (2 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_load_op_utilization", + "MetricThreshold": "tma_load_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Load operations. Sample with: UOPS_DISPATCHED.PORT_2_3", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average Frequency Utilization relative nominal frequency", - "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC", - "MetricGroup": "Power", - "MetricName": "Turbo_Utilization" + "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) DTLB was missed by load accesses, that later on hit in second-level TLB (STLB)", + "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", + "MetricName": "tma_load_stlb_hit", + "MetricThreshold": "tma_load_stlb_hit > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0", - "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / CORE_CLKS", - "MetricGroup": "Power", - "MetricName": "Power_License0_Utilization", - "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes." + "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by load accesses, performing a hardware page walk", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / tma_info_clks", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_group", + "MetricName": "tma_load_stlb_miss", + "MetricThreshold": "tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1", - "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / CORE_CLKS", - "MetricGroup": "Power", - "MetricName": "Power_License1_Utilization", - "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions." + "BriefDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS.ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10 * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO))) / tma_info_clks", + "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1_bound_group", + "MetricName": "tma_lock_latency", + "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles the CPU spent handling cache misses due to lock operations. Due to the microarchitecture handling of locks; they are classified as L1_Bound regardless of what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOADS_PS. Related metrics: tma_store_latency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)", - "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / CORE_CLKS", - "MetricGroup": "Power", - "MetricName": "Power_License2_Utilization", - "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions." + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit", + "MetricExpr": "(LSD.CYCLES_ACTIVE - LSD.CYCLES_OK) / tma_info_core_clks / 2", + "MetricGroup": "FetchBW;LSD;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_lsd", + "MetricThreshold": "tma_lsd > 0.15 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 5 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to LSD (Loop Stream Detector) unit. LSD typically does well sustaining Uop supply. However; in some rare cases; optimal uop-delivery could not be reached for small loops whose size (in terms of number of uops) does not suit well the LSD structure.", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", - "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0)", - "MetricGroup": "SMT", - "MetricName": "SMT_2T_Utilization" + "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears", + "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts)", + "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation > 0.15", + "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Machine Clears. These slots are either wasted by uops fetched prior to the clear; or stalls the out-of-order portion of the machine needs to recover its state after the clear. For example; this can happen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modifying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_cache", + "ScaleUnit": "100%" }, { - "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "OS", - "MetricName": "Kernel_Utilization" + "BriefDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@) / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueBW", + "MetricName": "tma_mem_bandwidth", + "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the core's performance was likely hurt due to approaching bandwidth limits of external memory (DRAM). The underlying heuristic assumes that a similar off-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests by this logical processor; requests from other IA Logical Processors/Physical Cores/sockets; or other non-IA devices like GPU; hence the maximum external memory bandwidth limits may or may not be approached when this metric is flagged (see Uncore counters for that). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_info_memory_bandwidth, tma_sq_full", + "ScaleUnit": "100%" }, { - "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", - "MetricGroup": "OS", - "MetricName": "Kernel_CPI" + "BriefDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tma_info_clks - tma_mem_bandwidth", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_bound_group;tma_issueLat", + "MetricName": "tma_mem_latency", + "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles where the performance was likely hurt due to latency from external memory (DRAM). This metric does not aggregate requests from other Logical Processors/Physical Cores/sockets (see Uncore counters for that). Related metrics: tma_info_memory_latency, tma_l3_hit_latency", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", - "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1e6 / duration_time / 1e3", - "MetricGroup": "HPC;Mem;MemoryBW;SoC", - "MetricName": "DRAM_BW_Use" + "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * tma_backend_bound", + "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_memory_bound", + "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", + "PublicDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck. Memory Bound estimates fraction of slots where pipeline is likely stalled due to demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory demand loads which coincides with execution units starvation; in addition to (2) cases where stores could impose backpressure on the pipeline when many of them get buffered at the same time (less common out of the two).", + "ScaleUnit": "100%" }, { - "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests", - "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@", - "MetricGroup": "Mem;SoC", - "MetricName": "MEM_Parallel_Requests" + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring memory operations -- uops for memory load or store accesses.", + "MetricExpr": "tma_light_operations * MEM_INST_RETIRED.ANY / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_memory_operations", + "MetricThreshold": "tma_memory_operations > 0.1 & tma_light_operations > 0.6", + "ScaleUnit": "100%" }, { - "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", - "MetricGroup": "Branches;OS", - "MetricName": "IpFarBranch" + "BriefDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", + "MetricExpr": "tma_retiring * tma_info_slots / UOPS_ISSUED.ANY * IDQ.MS_UOPS / tma_info_slots", + "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operations_group;tma_issueMC;tma_issueMS", + "MetricName": "tma_microcode_sequencer", + "MetricThreshold": "tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1", + "PublicDescription": "This metric represents fraction of slots the CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The MS is used for CISC instructions not supported by the default decoders (like repeat move strings; or CPUID); or by microcode assists used to address some operation modes (like in Floating Point assists). These cases can often be avoided. Sample with: IDQ.MS_UOPS. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_ms_switches", + "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per core", - "MetricExpr": "cstate_core@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Core_Residency", + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_clks", + "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueBM", + "MetricName": "tma_mispredicts_resteers", + "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Branch Misprediction at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_branch_mispredicts, tma_info_branch_misprediction_cost, tma_info_mispredictions", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per core", - "MetricExpr": "cstate_core@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Core_Residency", + "BriefDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline)", + "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / tma_info_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "MetricName": "tma_mite", + "MetricThreshold": "tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 5 > 0.35)", + "PublicDescription": "This metric represents Core fraction of cycles in which CPU was likely limited due to the MITE pipeline (the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or LSD. For example; inefficiencies due to asymmetric decoders; use of long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sample with: FRONTEND_RETIRED.ANY_DSB_MISS", "ScaleUnit": "100%" }, { - "BriefDescription": "C2 residency percent per package", - "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C2_Pkg_Residency", + "BriefDescription": "This metric represents fraction of cycles where (only) 4 uops were delivered by the MITE pipeline", + "MetricExpr": "(cpu@IDQ.MITE_UOPS\\,cmask\\=4@ - cpu@IDQ.MITE_UOPS\\,cmask\\=5@) / tma_info_clks", + "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_mite_group", + "MetricName": "tma_mite_4wide", + "MetricThreshold": "tma_mite_4wide > 0.05 & (tma_mite > 0.1 & (tma_fetch_bandwidth > 0.1 & tma_frontend_bound > 0.15 & tma_info_ipc / 5 > 0.35))", "ScaleUnit": "100%" }, { - "BriefDescription": "C3 residency percent per package", - "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C3_Pkg_Residency", + "BriefDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued", + "MetricExpr": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH / UOPS_ISSUED.ANY", + "MetricGroup": "TopdownL5;tma_L5_group;tma_issueMV;tma_ports_utilized_0_group", + "MetricName": "tma_mixing_vectors", + "MetricThreshold": "tma_mixing_vectors > 0.05", + "PublicDescription": "The Mixing_Vectors metric gives the percentage of injected blend uops out of all uops issued. Usually a Mixing_Vectors over 5% is worth investigating. Read more in Appendix B1 of the Optimizations Guide for this topic. Related metrics: tma_ms_switches", "ScaleUnit": "100%" }, { - "BriefDescription": "C6 residency percent per package", - "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C6_Pkg_Residency", + "BriefDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS)", + "MetricExpr": "3 * IDQ.MS_SWITCHES / tma_info_clks", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch_latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", + "MetricName": "tma_ms_switches", + "MetricThreshold": "tma_ms_switches > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric estimates the fraction of cycles when the CPU was stalled due to switches of uop delivery to the Microcode Sequencer (MS). Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Certain operations cannot be handled natively by the execution pipeline; and must be performed by microcode (small programs injected into the execution stream). Switching to the MS too often can negatively impact performance. The MS is designated to deliver long uop flows required by CISC instructions like CPUID; or uncommon conditions like Floating Point Assists when dealing with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_resteers, tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operation", "ScaleUnit": "100%" }, { - "BriefDescription": "C7 residency percent per package", - "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C7_Pkg_Residency", + "BriefDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions", + "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (tma_retiring * tma_info_slots)", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_nop_instructions", + "MetricThreshold": "tma_nop_instructions > 0.1 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents fraction of slots where the CPU was retiring NOP (no op) instructions. Compilers often use NOPs for certain address alignments - e.g. start address of a function or loop body. Sample with: INST_RETIRED.NOP", "ScaleUnit": "100%" }, { - "BriefDescription": "C8 residency percent per package", - "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C8_Pkg_Residency", + "BriefDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes", + "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_memory_operations + tma_branch_instructions + tma_nop_instructions))", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operations_group", + "MetricName": "tma_other_light_ops", + "MetricThreshold": "tma_other_light_ops > 0.3 & tma_light_operations > 0.6", + "PublicDescription": "This metric represents the remaining light uops fraction the CPU has executed - remaining means not covered by other sibling nodes. May undercount due to FMA double counting", "ScaleUnit": "100%" }, { - "BriefDescription": "C9 residency percent per package", - "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C9_Pkg_Residency", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch)", + "MetricExpr": "UOPS_DISPATCHED.PORT_0 / tma_info_core_clks", + "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_0", + "MetricThreshold": "tma_port_0 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd branch). Sample with: UOPS_DISPATCHED.PORT_0. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", "ScaleUnit": "100%" }, { - "BriefDescription": "C10 residency percent per package", - "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC", - "MetricGroup": "Power", - "MetricName": "C10_Pkg_Residency", + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU)", + "MetricExpr": "UOPS_DISPATCHED.PORT_1 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_1", + "MetricThreshold": "tma_port_1 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATCHED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU)", + "MetricExpr": "UOPS_DISPATCHED.PORT_5 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_5", + "MetricThreshold": "tma_port_5 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 5 ([SNB+] Branches and ALU; [HSW+] ALU). Sample with: UOPS_DISPATCHED.PORT_5. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU)", + "MetricExpr": "UOPS_DISPATCHED.PORT_6 / tma_info_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_group;tma_issue2P", + "MetricName": "tma_port_6", + "MetricThreshold": "tma_port_6 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port 6 ([HSW+]Primary Branch and simple ALU). Sample with: UOPS_DISPATCHED.PORT_6. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_ports_utilized_2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related)", + "MetricExpr": "((cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) + (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / tma_info_clks if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL) / tma_info_clks)", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_ports_utilization", + "MetricThreshold": "tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates fraction of cycles the CPU performance was potentially limited due to Core computation issues (non divider-related). Two distinct categories can be attributed into this metric: (1) heavy data-dependency among contiguous instructions would manifest in this metric - such cases are often referred to as low Instruction Level Parallelism (ILP). (2) Contention on some hardware execution unit other than Divider. For example; when there are too many multiply operations.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=0x80@ / tma_info_clks + tma_serializing_operation * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_0", + "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed no uops on any execution port (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions like divides may contribute to this metric.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "EXE_ACTIVITY.1_PORTS_UTIL / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_1", + "MetricThreshold": "tma_ports_utilized_1 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles where the CPU executed total of 1 uop per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). This can be due to heavy data-dependency among software instructions; or over oversubscribing a particular hardware resource. In some other cases with high 1_Port_Utilized and L1_Bound; this metric can point to L1 data-cache latency bottleneck that may not necessarily manifest with complete execution starvation (due to the short L1 latency e.g. walking a linked list) - looking at the assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL. Related metrics: tma_l1_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "EXE_ACTIVITY.2_PORTS_UTIL / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_2", + "MetricThreshold": "tma_ports_utilized_2 > 0.15 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 2 uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization -most compilers feature auto-Vectorization options today- reduces pressure on the execution ports as multiple elements are calculated with same uop. Sample with: EXE_ACTIVITY.2_PORTS_UTIL. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_port_0, tma_port_1, tma_port_5, tma_port_6", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utilization_group", + "MetricName": "tma_ports_utilized_3m", + "MetricThreshold": "tma_ports_utilized_3m > 0.7 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CPU executed total of 3 or more uops per cycle on all execution ports (Logical Processor cycles since ICL, Physical Core cycles otherwise). Sample with: UOPS_EXECUTED.CYCLES_GE_3", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_slots", + "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.1", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. Sample with: UOPS_RETIRED.SLOTS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations", + "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / tma_info_clks", + "MetricGroup": "PortsUtil;TopdownL5;tma_L5_group;tma_issueSO;tma_ports_utilized_0_group", + "MetricName": "tma_serializing_operation", + "MetricThreshold": "tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2)))", + "PublicDescription": "This metric represents fraction of cycles the CPU issue-pipeline was stalled due to serializing operations. Instructions like CPUID; WRMSR or LFENCE serialize the out-of-order execution which may limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD. Related metrics: tma_ms_switches", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions", + "MetricExpr": "140 * MISC_RETIRED.PAUSE_INST / tma_info_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_serializing_operation_group", + "MetricName": "tma_slow_pause", + "MetricThreshold": "tma_slow_pause > 0.05 & (tma_serializing_operation > 0.1 & (tma_ports_utilized_0 > 0.2 & (tma_ports_utilization > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to PAUSE Instructions. Sample with: MISC_RETIRED.PAUSE_INST", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary", + "MetricExpr": "tma_info_load_miss_real_latency * LD_BLOCKS.NO_SR / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_split_loads", + "MetricThreshold": "tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache line boundary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents rate of split store accesses", + "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / tma_info_core_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bound_group", + "MetricName": "tma_split_stores", + "MetricThreshold": "tma_split_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents rate of split store accesses. Consider aligning your data to the 64-byte cache line granularity. Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_4", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors)", + "MetricExpr": "L1D_PEND_MISS.L2_STALL / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueBW;tma_l3_bound_group", + "MetricName": "tma_sq_full", + "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric measures fraction of cycles where the Super Queue (SQ) was full taking into account all request-types and both hardware SMT threads (Logical Processors). Related metrics: tma_fb_full, tma_info_dram_bw_use, tma_info_memory_bandwidth, tma_mem_bandwidth", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write", + "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / tma_info_clks", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", + "MetricName": "tma_store_bound", + "MetricThreshold": "tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often CPU was stalled due to RFO store memory accesses; RFO store issue a read-for-ownership request before the write. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should RFO stores be a bottleneck. Sample with: MEM_INST_RETIRED.ALL_STORES_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores", + "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / tma_info_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_store_fwd_blk", + "MetricThreshold": "tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cycles when the memory subsystem had loads blocked since they could not forward data from earlier (in program order) overlapping stores. To streamline memory operations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writing the data that the load wants to read (store forwarding process). However; in some cases the load may be blocked for a significant time pending the store forward. For example; when the prior store is writing a smaller region than the load is reading.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses", + "MetricExpr": "(L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_clks", + "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_issueSL;tma_store_bound_group", + "MetricName": "tma_store_latency", + "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles the CPU spent handling L1D store misses. Store accesses usually less impact out-of-order core performance; however; holding resources for longer time can lead into undesired implications (e.g. contention on L1D fill-buffer entries - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations", + "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_8) / (4 * tma_info_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group", + "MetricName": "tma_store_op_utilization", + "MetricThreshold": "tma_store_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution port for Store operations. Sample with: UOPS_DISPATCHED.PORT_7_8", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates the fraction of cycles where the TLB was missed by store accesses, hitting in the second-level TLB (STLB)", + "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", + "MetricName": "tma_store_stlb_hit", + "MetricThreshold": "tma_store_stlb_hit > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates the fraction of cycles where the STLB was missed by store accesses, performing a hardware page walk", + "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / tma_info_core_clks", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_group", + "MetricName": "tma_store_stlb_miss", + "MetricThreshold": "tma_store_stlb_miss > 0.05 & (tma_dtlb_store > 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)))", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores", + "MetricExpr": "9 * OCR.STREAMING_WR.ANY_RESPONSE / tma_info_clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueSmSt;tma_store_bound_group", + "MetricName": "tma_streaming_stores", + "MetricThreshold": "tma_streaming_stores > 0.2 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates how often CPU was stalled due to Streaming store memory accesses; Streaming store optimize out a read request required by RFO stores. Even though store accesses do not typically stall out-of-order CPUs; there are few cases where stores can lead to actual stalls. This metric will be flagged should Streaming stores be a bottleneck. Sample with: OCR.STREAMING_WR.ANY_RESPONSE. Related metrics: tma_fb_full", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears", + "MetricExpr": "10 * BACLEARS.ANY / tma_info_clks", + "MetricGroup": "BigFoot;FetchLat;TopdownL4;tma_L4_group;tma_branch_resteers_group", + "MetricName": "tma_unknown_branches", + "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to new branch address clears. These are fetched branches the Branch Prediction Unit was unable to recognize (e.g. first time the branch is fetched or hitting BTB capacity limit). Sample with: BACLEARS.ANY", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric serves as an approximation of legacy x87 usage", + "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.THREAD", + "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_x87_use", + "MetricThreshold": "tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6)", + "PublicDescription": "This metric serves as an approximation of legacy x87 usage. It accounts for instructions beyond X87 FP arithmetic operations; hence may be used as a thermometer to avoid X87 high usage and preferably upgrade to modern ISA. See Tip under Tuning Hint.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of cycles in aborted transactions.", + "MetricExpr": "max(cpu@cycles\\-t@ - cpu@cycles\\-ct@, 0) / cycles", + "MetricGroup": "transaction", + "MetricName": "tsx_aborted_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Number of cycles within a transaction divided by the number of elisions.", + "MetricExpr": "cpu@cycles\\-t@ / cpu@el\\-start@", + "MetricGroup": "transaction", + "MetricName": "tsx_cycles_per_elision", + "ScaleUnit": "1cycles / elision" + }, + { + "BriefDescription": "Number of cycles within a transaction divided by the number of transactions.", + "MetricExpr": "cpu@cycles\\-t@ / cpu@tx\\-start@", + "MetricGroup": "transaction", + "MetricName": "tsx_cycles_per_transaction", + "ScaleUnit": "1cycles / transaction" + }, + { + "BriefDescription": "Percentage of cycles within a transaction region.", + "MetricExpr": "cpu@cycles\\-t@ / cycles", + "MetricGroup": "transaction", + "MetricName": "tsx_transactional_cycles", "ScaleUnit": "100%" } ] diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json index e2ea5ccfe3bc..a5a254327ae9 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json @@ -24,7 +24,7 @@ "Unit": "ARB" }, { - "BriefDescription": "Number of coherent read requests sent to memory controller that were issued by any core.", + "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_REQ_TRK_REQUEST.DRD", "EventCode": "0x81", "EventName": "UNC_ARB_DAT_REQUESTS.RD", "PerPkg": "1", @@ -40,7 +40,15 @@ "Unit": "ARB" }, { - "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_REQUESTS.RD", + "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_OCCUPANCY.RD]", + "EventCode": "0x80", + "EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_REQUESTS.RD]", "EventCode": "0x81", "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD", "PerPkg": "1", @@ -55,6 +63,14 @@ "UMask": "0x1", "Unit": "ARB" }, + { + "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_OCCUPANCY.DRD]", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.RD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, { "BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL", "EventCode": "0x81", @@ -63,6 +79,14 @@ "UMask": "0x1", "Unit": "ARB" }, + { + "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_REQUEST.DRD]", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.RD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, { "BriefDescription": "UNC_CLOCK.SOCKET", "EventCode": "0xff", -- cgit v1.2.3-58-ga151 From 1aa52f9490d50cba4a8872f34d297bc8400735b7 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:28 -0800 Subject: perf vendor events intel: Refresh westmereep-dp events Update the westmereep-dp events from 3 to 4. Generation was done using https://github.com/intel/perfmon. The most notable change is in corrections to event descriptions. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-32-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json | 2 +- tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index bc2c4e756f44..1c6eef118e61 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -28,7 +28,7 @@ GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v54,skylake,core GenuineIntel-6-55-[01234],v1.29,skylakex,core GenuineIntel-6-86,v1.20,snowridgex,core GenuineIntel-6-8[CD],v1.10,tigerlake,core -GenuineIntel-6-2C,v3,westmereep-dp,core +GenuineIntel-6-2C,v4,westmereep-dp,core GenuineIntel-6-25,v3,westmereep-sp,core GenuineIntel-6-2F,v3,westmereex,core AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]),v2,amdzen1,core diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json index 5c897da3cd6b..4dae735fb636 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json @@ -182,7 +182,7 @@ "UMask": "0x20" }, { - "BriefDescription": "L2 lines alloacated", + "BriefDescription": "L2 lines allocated", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ANY", "SampleAfterValue": "100000", diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json index ef635bff1522..f75084309041 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json @@ -56,7 +56,7 @@ "UMask": "0x80" }, { - "BriefDescription": "DTLB misses casued by low part of address", + "BriefDescription": "DTLB misses caused by low part of address", "EventCode": "0x49", "EventName": "DTLB_MISSES.PDE_MISS", "SampleAfterValue": "200000", -- cgit v1.2.3-58-ga151 From 77d78b4c19f25810202d7033f4b9d7be2cdc898f Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:29 -0800 Subject: perf jevents: Add rand support to metrics rand (reverse and) is useful in the parsing of metric thresholds. Update the documentation on operator precedence to clarify the simple expression parser and python differences wrt binary/logical operators. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-33-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/metric.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/metric.py b/tools/perf/pmu-events/metric.py index 77ea6ff98538..8ec0ba884673 100644 --- a/tools/perf/pmu-events/metric.py +++ b/tools/perf/pmu-events/metric.py @@ -44,6 +44,9 @@ class Expression: def __and__(self, other: Union[int, float, 'Expression']) -> 'Operator': return Operator('&', self, other) + def __rand__(self, other: Union[int, float, 'Expression']) -> 'Operator': + return Operator('&', other, self) + def __lt__(self, other: Union[int, float, 'Expression']) -> 'Operator': return Operator('<', self, other) @@ -88,7 +91,10 @@ def _Constify(val: Union[bool, int, float, Expression]) -> Expression: # Simple lookup for operator precedence, used to avoid unnecessary -# brackets. Precedence matches that of python and the simple expression parser. +# brackets. Precedence matches that of the simple expression parser +# but differs from python where comparisons are lower precedence than +# the bitwise &, ^, | but not the logical versions that the expression +# parser doesn't have. _PRECEDENCE = { '|': 0, '^': 1, -- cgit v1.2.3-58-ga151 From 45e8867a962a069763f0978d30f1d7cd82ead0cb Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:30 -0800 Subject: perf jevent: Parse metric thresholds Parse the metric threshold and add to the pmu-events.c file. The metric isn't parsed as the parser uses python's parser and will break the operator precedence. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-34-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/jevents.py | 7 ++++++- tools/perf/pmu-events/pmu-events.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index e82dff3a1228..40b9e626fc15 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -51,7 +51,7 @@ _json_event_attributes = [ # Attributes that are in pmu_metric rather than pmu_event. _json_metric_attributes = [ - 'metric_name', 'metric_group', 'metric_expr', 'desc', + 'metric_name', 'metric_group', 'metric_expr', 'metric_threshold', 'desc', 'long_desc', 'unit', 'compat', 'aggr_mode', 'event_grouping' ] # Attributes that are bools or enum int values, encoded as '0', '1',... @@ -306,6 +306,9 @@ class JsonEvent: self.metric_expr = None if 'MetricExpr' in jd: self.metric_expr = metric.ParsePerfJson(jd['MetricExpr']).Simplify() + # Note, the metric formula for the threshold isn't parsed as the & + # and > have incorrect precedence. + self.metric_threshold = jd.get('MetricThreshold') arch_std = jd.get('ArchStdEvent') if precise and self.desc and '(Precise Event)' not in self.desc: @@ -362,6 +365,8 @@ class JsonEvent: # Convert parsed metric expressions into a string. Slashes # must be doubled in the file. x = x.ToPerfJson().replace('\\', '\\\\') + if metric and x and attr == 'metric_threshold': + x = x.replace('\\', '\\\\') if attr in _json_enum_attributes: s += x if x else '0' else: diff --git a/tools/perf/pmu-events/pmu-events.h b/tools/perf/pmu-events/pmu-events.h index 57a38e3e5c32..b7dff8f1021f 100644 --- a/tools/perf/pmu-events/pmu-events.h +++ b/tools/perf/pmu-events/pmu-events.h @@ -54,6 +54,7 @@ struct pmu_metric { const char *metric_name; const char *metric_group; const char *metric_expr; + const char *metric_threshold; const char *unit; const char *compat; const char *desc; -- cgit v1.2.3-58-ga151 From 62e10d937d6d5d0f100d6d13c17b4376d1466044 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:31 -0800 Subject: perf pmu-events: Test parsing metric thresholds with the fake PMU Test the correctness of metric thresholds by testing them all with the fake PMU logic. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-35-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/pmu-events.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'tools') diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c index 521557c396bc..db2fed0c6993 100644 --- a/tools/perf/tests/pmu-events.c +++ b/tools/perf/tests/pmu-events.c @@ -1021,12 +1021,34 @@ static int test__parsing_fake(struct test_suite *test __maybe_unused, return pmu_for_each_sys_metric(test__parsing_fake_callback, NULL); } +static int test__parsing_threshold_callback(const struct pmu_metric *pm, + const struct pmu_metrics_table *table __maybe_unused, + void *data __maybe_unused) +{ + if (!pm->metric_threshold) + return 0; + return metric_parse_fake(pm->metric_name, pm->metric_threshold); +} + +static int test__parsing_threshold(struct test_suite *test __maybe_unused, + int subtest __maybe_unused) +{ + int err = 0; + + err = pmu_for_each_core_metric(test__parsing_threshold_callback, NULL); + if (err) + return err; + + return pmu_for_each_sys_metric(test__parsing_threshold_callback, NULL); +} + static struct test_case pmu_events_tests[] = { TEST_CASE("PMU event table sanity", pmu_event_table), TEST_CASE("PMU event map aliases", aliases), TEST_CASE_REASON("Parsing of PMU event table metrics", parsing, "some metrics failed"), TEST_CASE("Parsing of PMU event table metrics with fake PMUs", parsing_fake), + TEST_CASE("Parsing of metric thresholds with fake PMUs", parsing_threshold), { .name = NULL, } }; -- cgit v1.2.3-58-ga151 From c7551a2e33c60189147f84b17934cb5f1784d0dd Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:32 -0800 Subject: perf list: Support for printing metric thresholds Add to json output by default. For regular output, only enable with the --detail flag. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-36-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-list.c | 13 ++++++++++++- tools/perf/util/metricgroup.c | 3 +++ tools/perf/util/print-events.h | 1 + 3 files changed, 16 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/builtin-list.c b/tools/perf/builtin-list.c index 791f513ae5b4..76e1d31a68ee 100644 --- a/tools/perf/builtin-list.c +++ b/tools/perf/builtin-list.c @@ -168,6 +168,7 @@ static void default_print_metric(void *ps, const char *desc, const char *long_desc, const char *expr, + const char *threshold, const char *unit __maybe_unused) { struct print_state *print_state = ps; @@ -227,6 +228,11 @@ static void default_print_metric(void *ps, wordwrap(expr, 8, pager_get_columns(), 0); printf("]\n"); } + if (threshold && print_state->detailed) { + printf("%*s", 8, "["); + wordwrap(threshold, 8, pager_get_columns(), 0); + printf("]\n"); + } } struct json_print_state { @@ -367,7 +373,7 @@ static void json_print_event(void *ps, const char *pmu_name, const char *topic, static void json_print_metric(void *ps __maybe_unused, const char *group, const char *name, const char *desc, const char *long_desc, const char *expr, - const char *unit) + const char *threshold, const char *unit) { struct json_print_state *print_state = ps; bool need_sep = false; @@ -388,6 +394,11 @@ static void json_print_metric(void *ps __maybe_unused, const char *group, fix_escape_printf(&buf, "%s\t\"MetricExpr\": \"%S\"", need_sep ? ",\n" : "", expr); need_sep = true; } + if (threshold) { + fix_escape_printf(&buf, "%s\t\"MetricThreshold\": \"%S\"", need_sep ? ",\n" : "", + threshold); + need_sep = true; + } if (unit) { fix_escape_printf(&buf, "%s\t\"ScaleUnit\": \"%S\"", need_sep ? ",\n" : "", unit); need_sep = true; diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index 868fc9c35606..b1d56a73223d 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -368,6 +368,7 @@ struct mep { const char *metric_desc; const char *metric_long_desc; const char *metric_expr; + const char *metric_threshold; const char *metric_unit; }; @@ -447,6 +448,7 @@ static int metricgroup__add_to_mep_groups(const struct pmu_metric *pm, me->metric_desc = pm->desc; me->metric_long_desc = pm->long_desc; me->metric_expr = pm->metric_expr; + me->metric_threshold = pm->metric_threshold; me->metric_unit = pm->unit; } } @@ -522,6 +524,7 @@ void metricgroup__print(const struct print_callbacks *print_cb, void *print_stat me->metric_desc, me->metric_long_desc, me->metric_expr, + me->metric_threshold, me->metric_unit); next = rb_next(node); rblist__remove_node(&groups, node); diff --git a/tools/perf/util/print-events.h b/tools/perf/util/print-events.h index 716dcf4b4859..e75a3d7e3fe3 100644 --- a/tools/perf/util/print-events.h +++ b/tools/perf/util/print-events.h @@ -23,6 +23,7 @@ struct print_callbacks { const char *desc, const char *long_desc, const char *expr, + const char *threshold, const char *unit); }; -- cgit v1.2.3-58-ga151 From d0a3052f6faefffcb15e93853c06f56207c32743 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:33 -0800 Subject: perf metric: Compute and print threshold values Compute the threshold metric and use it to color the metric value as red or green. The threshold expression is used to generate the set of events as the threshold may require additional events. A later patch make this behavior optional with a --metric-no-threshold flag. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-37-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/metricgroup.c | 24 +++++++++++++++++++++--- tools/perf/util/metricgroup.h | 1 + tools/perf/util/stat-shadow.c | 24 ++++++++++++++++-------- 3 files changed, 38 insertions(+), 11 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index b1d56a73223d..d83885697125 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -129,6 +129,8 @@ struct metric { const char *modifier; /** The expression to parse, for example, "instructions/cycles". */ const char *metric_expr; + /** Optional threshold expression where zero value is green, otherwise red. */ + const char *metric_threshold; /** * The "ScaleUnit" that scales and adds a unit to the metric during * output. @@ -222,6 +224,7 @@ static struct metric *metric__new(const struct pmu_metric *pm, goto out_err; } m->metric_expr = pm->metric_expr; + m->metric_threshold = pm->metric_threshold; m->metric_unit = pm->unit; m->pctx->sctx.user_requested_cpu_list = NULL; if (user_requested_cpu_list) { @@ -901,6 +904,7 @@ static int __add_metric(struct list_head *metric_list, const struct visited_metric *vm; int ret; bool is_root = !root_metric; + const char *expr; struct visited_metric visited_node = { .name = pm->metric_name, .parent = visited, @@ -963,16 +967,29 @@ static int __add_metric(struct list_head *metric_list, * For both the parent and referenced metrics, we parse * all the metric's IDs and add it to the root context. */ - if (expr__find_ids(pm->metric_expr, NULL, root_metric->pctx) < 0) { + ret = 0; + expr = pm->metric_expr; + if (is_root && pm->metric_threshold) { + /* + * Threshold expressions are built off the actual metric. Switch + * to use that in case of additional necessary events. Change + * the visited node name to avoid this being flagged as + * recursion. + */ + assert(strstr(pm->metric_threshold, pm->metric_name)); + expr = pm->metric_threshold; + visited_node.name = "__threshold__"; + } + if (expr__find_ids(expr, NULL, root_metric->pctx) < 0) { /* Broken metric. */ ret = -EINVAL; - } else { + } + if (!ret) { /* Resolve referenced metrics. */ ret = resolve_metric(metric_list, modifier, metric_no_group, user_requested_cpu_list, system_wide, root_metric, &visited_node, table); } - if (ret) { if (is_root) metric__free(root_metric); @@ -1554,6 +1571,7 @@ static int parse_groups(struct evlist *perf_evlist, const char *str, free(metric_events); goto out; } + expr->metric_threshold = m->metric_threshold; expr->metric_unit = m->metric_unit; expr->metric_events = metric_events; expr->runtime = m->pctx->sctx.runtime; diff --git a/tools/perf/util/metricgroup.h b/tools/perf/util/metricgroup.h index 84030321a057..32eb3a5381fb 100644 --- a/tools/perf/util/metricgroup.h +++ b/tools/perf/util/metricgroup.h @@ -47,6 +47,7 @@ struct metric_expr { const char *metric_expr; /** The name of the meric such as "IPC". */ const char *metric_name; + const char *metric_threshold; /** * The "ScaleUnit" that scales and adds a unit to the metric during * output. For example, "6.4e-05MiB" means to scale the resulting metric diff --git a/tools/perf/util/stat-shadow.c b/tools/perf/util/stat-shadow.c index 806b32156459..a41f186c6ec8 100644 --- a/tools/perf/util/stat-shadow.c +++ b/tools/perf/util/stat-shadow.c @@ -777,6 +777,7 @@ static int prepare_metric(struct evsel **metric_events, static void generic_metric(struct perf_stat_config *config, const char *metric_expr, + const char *metric_threshold, struct evsel **metric_events, struct metric_ref *metric_refs, char *name, @@ -789,9 +790,10 @@ static void generic_metric(struct perf_stat_config *config, { print_metric_t print_metric = out->print_metric; struct expr_parse_ctx *pctx; - double ratio, scale; + double ratio, scale, threshold; int i; void *ctxp = out->ctx; + const char *color = NULL; pctx = expr__ctx_new(); if (!pctx) @@ -811,6 +813,12 @@ static void generic_metric(struct perf_stat_config *config, char *unit; char metric_bf[64]; + if (metric_threshold && + expr__parse(&threshold, pctx, metric_threshold) == 0) { + color = fpclassify(threshold) == FP_ZERO + ? PERF_COLOR_GREEN : PERF_COLOR_RED; + } + if (metric_unit && metric_name) { if (perf_pmu__convert_scale(metric_unit, &unit, &scale) >= 0) { @@ -823,22 +831,22 @@ static void generic_metric(struct perf_stat_config *config, scnprintf(metric_bf, sizeof(metric_bf), "%s %s", unit, metric_name); - print_metric(config, ctxp, NULL, "%8.1f", + print_metric(config, ctxp, color, "%8.1f", metric_bf, ratio); } else { - print_metric(config, ctxp, NULL, "%8.2f", + print_metric(config, ctxp, color, "%8.2f", metric_name ? metric_name : out->force_header ? name : "", ratio); } } else { - print_metric(config, ctxp, NULL, NULL, + print_metric(config, ctxp, color, /*unit=*/NULL, out->force_header ? (metric_name ? metric_name : name) : "", 0); } } else { - print_metric(config, ctxp, NULL, NULL, + print_metric(config, ctxp, color, /*unit=*/NULL, out->force_header ? (metric_name ? metric_name : name) : "", 0); } @@ -1214,9 +1222,9 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, list_for_each_entry (mexp, &me->head, nd) { if (num++ > 0) out->new_line(config, ctxp); - generic_metric(config, mexp->metric_expr, mexp->metric_events, - mexp->metric_refs, evsel->name, mexp->metric_name, - mexp->metric_unit, mexp->runtime, + generic_metric(config, mexp->metric_expr, mexp->metric_threshold, + mexp->metric_events, mexp->metric_refs, evsel->name, + mexp->metric_name, mexp->metric_unit, mexp->runtime, map_idx, out, st); } } -- cgit v1.2.3-58-ga151 From 798029341baf398b519591f2bba897b08e4cdc27 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:34 -0800 Subject: perf expr: More explicit NAN handling Comparison and logical operations on NAN won't ensure the result is NAN. Ensure NANs are propogated so that threshold expressions like "tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15" don't yield a number when the components are NAN. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-38-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/expr.y | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/expr.y b/tools/perf/util/expr.y index 635e562350c5..250e444bf032 100644 --- a/tools/perf/util/expr.y +++ b/tools/perf/util/expr.y @@ -127,7 +127,11 @@ static struct ids handle_id(struct expr_parse_ctx *ctx, char *id, if (!compute_ids || (is_const(LHS.val) && is_const(RHS.val))) { \ assert(LHS.ids == NULL); \ assert(RHS.ids == NULL); \ - RESULT.val = (long)LHS.val OP (long)RHS.val; \ + if (isnan(LHS.val) || isnan(RHS.val)) { \ + RESULT.val = NAN; \ + } else { \ + RESULT.val = (long)LHS.val OP (long)RHS.val; \ + } \ RESULT.ids = NULL; \ } else { \ RESULT = union_expr(LHS, RHS); \ @@ -137,7 +141,11 @@ static struct ids handle_id(struct expr_parse_ctx *ctx, char *id, if (!compute_ids || (is_const(LHS.val) && is_const(RHS.val))) { \ assert(LHS.ids == NULL); \ assert(RHS.ids == NULL); \ - RESULT.val = LHS.val OP RHS.val; \ + if (isnan(LHS.val) || isnan(RHS.val)) { \ + RESULT.val = NAN; \ + } else { \ + RESULT.val = LHS.val OP RHS.val; \ + } \ RESULT.ids = NULL; \ } else { \ RESULT = union_expr(LHS, RHS); \ -- cgit v1.2.3-58-ga151 From 1fd09e299bdd434b259da3ffcfdcae2dfeac9b2e Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:35 -0800 Subject: perf metric: Add --metric-no-threshold option Thresholds may need additional events, this can impact things like sharing groups of events to avoid multiplexing. Add a flag to make the threshold calculations optional. The threshold will still be computed if no additional events are necessary. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-39-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-stat.c | 4 +++ tools/perf/tests/expand-cgroup.c | 3 +- tools/perf/tests/parse-metric.c | 1 - tools/perf/tests/pmu-events.c | 4 +-- tools/perf/util/metricgroup.c | 62 +++++++++++++++++++++++++--------------- tools/perf/util/metricgroup.h | 3 +- tools/perf/util/stat-shadow.c | 3 +- tools/perf/util/stat.h | 1 + 8 files changed, 49 insertions(+), 32 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index 5d18a5a6f662..5e13171a7bba 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -1256,6 +1256,8 @@ static struct option stat_options[] = { "don't group metric events, impacts multiplexing"), OPT_BOOLEAN(0, "metric-no-merge", &stat_config.metric_no_merge, "don't try to share events between metrics in a group"), + OPT_BOOLEAN(0, "metric-no-threshold", &stat_config.metric_no_threshold, + "don't try to share events between metrics in a group "), OPT_BOOLEAN(0, "topdown", &topdown_run, "measure top-down statistics"), OPT_UINTEGER(0, "td-level", &stat_config.topdown_level, @@ -1852,6 +1854,7 @@ static int add_default_attributes(void) return metricgroup__parse_groups(evsel_list, "transaction", stat_config.metric_no_group, stat_config.metric_no_merge, + stat_config.metric_no_threshold, stat_config.user_requested_cpu_list, stat_config.system_wide, &stat_config.metric_events); @@ -2519,6 +2522,7 @@ int cmd_stat(int argc, const char **argv) metricgroup__parse_groups(evsel_list, metrics, stat_config.metric_no_group, stat_config.metric_no_merge, + stat_config.metric_no_threshold, stat_config.user_requested_cpu_list, stat_config.system_wide, &stat_config.metric_events); diff --git a/tools/perf/tests/expand-cgroup.c b/tools/perf/tests/expand-cgroup.c index 672a27f37060..ec340880a848 100644 --- a/tools/perf/tests/expand-cgroup.c +++ b/tools/perf/tests/expand-cgroup.c @@ -187,8 +187,7 @@ static int expand_metric_events(void) rblist__init(&metric_events); pme_test = find_core_metrics_table("testarch", "testcpu"); - ret = metricgroup__parse_groups_test(evlist, pme_test, metric_str, - false, false, &metric_events); + ret = metricgroup__parse_groups_test(evlist, pme_test, metric_str, &metric_events); if (ret < 0) { pr_debug("failed to parse '%s' metric\n", metric_str); goto out; diff --git a/tools/perf/tests/parse-metric.c b/tools/perf/tests/parse-metric.c index 9fec6040950c..132c9b945a42 100644 --- a/tools/perf/tests/parse-metric.c +++ b/tools/perf/tests/parse-metric.c @@ -98,7 +98,6 @@ static int __compute_metric(const char *name, struct value *vals, /* Parse the metric into metric_events list. */ pme_test = find_core_metrics_table("testarch", "testcpu"); err = metricgroup__parse_groups_test(evlist, pme_test, name, - false, false, &metric_events); if (err) goto out; diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c index db2fed0c6993..50b99a0f8f59 100644 --- a/tools/perf/tests/pmu-events.c +++ b/tools/perf/tests/pmu-events.c @@ -846,9 +846,7 @@ static int test__parsing_callback(const struct pmu_metric *pm, perf_evlist__set_maps(&evlist->core, cpus, NULL); runtime_stat__init(&st); - err = metricgroup__parse_groups_test(evlist, table, pm->metric_name, - false, false, - &metric_events); + err = metricgroup__parse_groups_test(evlist, table, pm->metric_name, &metric_events); if (err) { if (!strcmp(pm->metric_name, "M1") || !strcmp(pm->metric_name, "M2") || !strcmp(pm->metric_name, "M3")) { diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index d83885697125..afb6f2fdc24e 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -771,6 +771,7 @@ struct metricgroup_add_iter_data { int *ret; bool *has_match; bool metric_no_group; + bool metric_no_threshold; const char *user_requested_cpu_list; bool system_wide; struct metric *root_metric; @@ -786,6 +787,7 @@ static int add_metric(struct list_head *metric_list, const struct pmu_metric *pm, const char *modifier, bool metric_no_group, + bool metric_no_threshold, const char *user_requested_cpu_list, bool system_wide, struct metric *root_metric, @@ -813,6 +815,7 @@ static int add_metric(struct list_head *metric_list, static int resolve_metric(struct list_head *metric_list, const char *modifier, bool metric_no_group, + bool metric_no_threshold, const char *user_requested_cpu_list, bool system_wide, struct metric *root_metric, @@ -861,8 +864,8 @@ static int resolve_metric(struct list_head *metric_list, */ for (i = 0; i < pending_cnt; i++) { ret = add_metric(metric_list, &pending[i].pm, modifier, metric_no_group, - user_requested_cpu_list, system_wide, root_metric, visited, - table); + metric_no_threshold, user_requested_cpu_list, system_wide, + root_metric, visited, table); if (ret) break; } @@ -879,6 +882,7 @@ static int resolve_metric(struct list_head *metric_list, * @metric_no_group: Should events written to events be grouped "{}" or * global. Grouping is the default but due to multiplexing the * user may override. + * @metric_no_threshold: Should threshold expressions be ignored? * @runtime: A special argument for the parser only known at runtime. * @user_requested_cpu_list: Command line specified CPUs to record on. * @system_wide: Are events for all processes recorded. @@ -894,6 +898,7 @@ static int __add_metric(struct list_head *metric_list, const struct pmu_metric *pm, const char *modifier, bool metric_no_group, + bool metric_no_threshold, int runtime, const char *user_requested_cpu_list, bool system_wide, @@ -974,10 +979,12 @@ static int __add_metric(struct list_head *metric_list, * Threshold expressions are built off the actual metric. Switch * to use that in case of additional necessary events. Change * the visited node name to avoid this being flagged as - * recursion. + * recursion. If the threshold events are disabled, just use the + * metric's name as a reference. This allows metric threshold + * computation if there are sufficient events. */ assert(strstr(pm->metric_threshold, pm->metric_name)); - expr = pm->metric_threshold; + expr = metric_no_threshold ? pm->metric_name : pm->metric_threshold; visited_node.name = "__threshold__"; } if (expr__find_ids(expr, NULL, root_metric->pctx) < 0) { @@ -987,8 +994,8 @@ static int __add_metric(struct list_head *metric_list, if (!ret) { /* Resolve referenced metrics. */ ret = resolve_metric(metric_list, modifier, metric_no_group, - user_requested_cpu_list, system_wide, - root_metric, &visited_node, table); + metric_no_threshold, user_requested_cpu_list, + system_wide, root_metric, &visited_node, table); } if (ret) { if (is_root) @@ -1035,6 +1042,7 @@ static int add_metric(struct list_head *metric_list, const struct pmu_metric *pm, const char *modifier, bool metric_no_group, + bool metric_no_threshold, const char *user_requested_cpu_list, bool system_wide, struct metric *root_metric, @@ -1046,9 +1054,9 @@ static int add_metric(struct list_head *metric_list, pr_debug("metric expr %s for %s\n", pm->metric_expr, pm->metric_name); if (!strstr(pm->metric_expr, "?")) { - ret = __add_metric(metric_list, pm, modifier, metric_no_group, 0, - user_requested_cpu_list, system_wide, root_metric, - visited, table); + ret = __add_metric(metric_list, pm, modifier, metric_no_group, + metric_no_threshold, 0, user_requested_cpu_list, + system_wide, root_metric, visited, table); } else { int j, count; @@ -1060,9 +1068,9 @@ static int add_metric(struct list_head *metric_list, */ for (j = 0; j < count && !ret; j++) - ret = __add_metric(metric_list, pm, modifier, metric_no_group, j, - user_requested_cpu_list, system_wide, - root_metric, visited, table); + ret = __add_metric(metric_list, pm, modifier, metric_no_group, + metric_no_threshold, j, user_requested_cpu_list, + system_wide, root_metric, visited, table); } return ret; @@ -1079,8 +1087,8 @@ static int metricgroup__add_metric_sys_event_iter(const struct pmu_metric *pm, return 0; ret = add_metric(d->metric_list, pm, d->modifier, d->metric_no_group, - d->user_requested_cpu_list, d->system_wide, - d->root_metric, d->visited, d->table); + d->metric_no_threshold, d->user_requested_cpu_list, + d->system_wide, d->root_metric, d->visited, d->table); if (ret) goto out; @@ -1124,6 +1132,7 @@ struct metricgroup__add_metric_data { const char *modifier; const char *user_requested_cpu_list; bool metric_no_group; + bool metric_no_threshold; bool system_wide; bool has_match; }; @@ -1141,8 +1150,9 @@ static int metricgroup__add_metric_callback(const struct pmu_metric *pm, data->has_match = true; ret = add_metric(data->list, pm, data->modifier, data->metric_no_group, - data->user_requested_cpu_list, data->system_wide, - /*root_metric=*/NULL, /*visited_metrics=*/NULL, table); + data->metric_no_threshold, data->user_requested_cpu_list, + data->system_wide, /*root_metric=*/NULL, + /*visited_metrics=*/NULL, table); } return ret; } @@ -1163,7 +1173,7 @@ static int metricgroup__add_metric_callback(const struct pmu_metric *pm, * architecture perf is running upon. */ static int metricgroup__add_metric(const char *metric_name, const char *modifier, - bool metric_no_group, + bool metric_no_group, bool metric_no_threshold, const char *user_requested_cpu_list, bool system_wide, struct list_head *metric_list, @@ -1179,6 +1189,7 @@ static int metricgroup__add_metric(const char *metric_name, const char *modifier .metric_name = metric_name, .modifier = modifier, .metric_no_group = metric_no_group, + .metric_no_threshold = metric_no_threshold, .user_requested_cpu_list = user_requested_cpu_list, .system_wide = system_wide, .has_match = false, @@ -1241,6 +1252,7 @@ out: * architecture perf is running upon. */ static int metricgroup__add_metric_list(const char *list, bool metric_no_group, + bool metric_no_threshold, const char *user_requested_cpu_list, bool system_wide, struct list_head *metric_list, const struct pmu_metrics_table *table) @@ -1259,7 +1271,8 @@ static int metricgroup__add_metric_list(const char *list, bool metric_no_group, *modifier++ = '\0'; ret = metricgroup__add_metric(metric_name, modifier, - metric_no_group, user_requested_cpu_list, + metric_no_group, metric_no_threshold, + user_requested_cpu_list, system_wide, metric_list, table); if (ret == -EINVAL) pr_err("Cannot find metric or group `%s'\n", metric_name); @@ -1449,6 +1462,7 @@ err_out: static int parse_groups(struct evlist *perf_evlist, const char *str, bool metric_no_group, bool metric_no_merge, + bool metric_no_threshold, const char *user_requested_cpu_list, bool system_wide, struct perf_pmu *fake_pmu, @@ -1463,7 +1477,7 @@ static int parse_groups(struct evlist *perf_evlist, const char *str, if (metric_events_list->nr_entries == 0) metricgroup__rblist_init(metric_events_list); - ret = metricgroup__add_metric_list(str, metric_no_group, + ret = metricgroup__add_metric_list(str, metric_no_group, metric_no_threshold, user_requested_cpu_list, system_wide, &metric_list, table); if (ret) @@ -1598,6 +1612,7 @@ int metricgroup__parse_groups(struct evlist *perf_evlist, const char *str, bool metric_no_group, bool metric_no_merge, + bool metric_no_threshold, const char *user_requested_cpu_list, bool system_wide, struct rblist *metric_events) @@ -1608,18 +1623,19 @@ int metricgroup__parse_groups(struct evlist *perf_evlist, return -EINVAL; return parse_groups(perf_evlist, str, metric_no_group, metric_no_merge, - user_requested_cpu_list, system_wide, + metric_no_threshold, user_requested_cpu_list, system_wide, /*fake_pmu=*/NULL, metric_events, table); } int metricgroup__parse_groups_test(struct evlist *evlist, const struct pmu_metrics_table *table, const char *str, - bool metric_no_group, - bool metric_no_merge, struct rblist *metric_events) { - return parse_groups(evlist, str, metric_no_group, metric_no_merge, + return parse_groups(evlist, str, + /*metric_no_group=*/false, + /*metric_no_merge=*/false, + /*metric_no_threshold=*/false, /*user_requested_cpu_list=*/NULL, /*system_wide=*/false, &perf_pmu__fake, metric_events, table); diff --git a/tools/perf/util/metricgroup.h b/tools/perf/util/metricgroup.h index 32eb3a5381fb..8d50052c5b4c 100644 --- a/tools/perf/util/metricgroup.h +++ b/tools/perf/util/metricgroup.h @@ -70,14 +70,13 @@ int metricgroup__parse_groups(struct evlist *perf_evlist, const char *str, bool metric_no_group, bool metric_no_merge, + bool metric_no_threshold, const char *user_requested_cpu_list, bool system_wide, struct rblist *metric_events); int metricgroup__parse_groups_test(struct evlist *evlist, const struct pmu_metrics_table *table, const char *str, - bool metric_no_group, - bool metric_no_merge, struct rblist *metric_events); void metricgroup__print(const struct print_callbacks *print_cb, void *print_state); diff --git a/tools/perf/util/stat-shadow.c b/tools/perf/util/stat-shadow.c index a41f186c6ec8..77483eeda0d8 100644 --- a/tools/perf/util/stat-shadow.c +++ b/tools/perf/util/stat-shadow.c @@ -814,7 +814,8 @@ static void generic_metric(struct perf_stat_config *config, char metric_bf[64]; if (metric_threshold && - expr__parse(&threshold, pctx, metric_threshold) == 0) { + expr__parse(&threshold, pctx, metric_threshold) == 0 && + !isnan(threshold)) { color = fpclassify(threshold) == FP_ZERO ? PERF_COLOR_GREEN : PERF_COLOR_RED; } diff --git a/tools/perf/util/stat.h b/tools/perf/util/stat.h index b1c29156c560..cf2d8aa445f3 100644 --- a/tools/perf/util/stat.h +++ b/tools/perf/util/stat.h @@ -159,6 +159,7 @@ struct perf_stat_config { bool no_csv_summary; bool metric_no_group; bool metric_no_merge; + bool metric_no_threshold; bool stop_read_counter; bool iostat_run; char *user_requested_cpu_list; -- cgit v1.2.3-58-ga151 From 94b1a603fca78388ef7575411aed4b1fabd843f9 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:36 -0800 Subject: perf stat: Add TopdownL1 metric as a default if present When there are no events and on Intel, the topdown events will be added by default if present. To display the metrics associated with these request special handling in stat-shadow.c. To more easily update these metrics use the json metric version via the TopdownL1 group. This makes the handling less platform specific. Modify the metricgroup__has_metric code to also cover metric groups. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-40-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/x86/util/evlist.c | 6 +++--- tools/perf/arch/x86/util/topdown.c | 30 ------------------------------ tools/perf/arch/x86/util/topdown.h | 1 - tools/perf/builtin-stat.c | 14 ++++++++++++++ tools/perf/util/metricgroup.c | 6 ++---- 5 files changed, 19 insertions(+), 38 deletions(-) (limited to 'tools') diff --git a/tools/perf/arch/x86/util/evlist.c b/tools/perf/arch/x86/util/evlist.c index cb59ce9b9638..8a7ae4162563 100644 --- a/tools/perf/arch/x86/util/evlist.c +++ b/tools/perf/arch/x86/util/evlist.c @@ -59,10 +59,10 @@ int arch_evlist__add_default_attrs(struct evlist *evlist, struct perf_event_attr *attrs, size_t nr_attrs) { - if (nr_attrs) - return ___evlist__add_default_attrs(evlist, attrs, nr_attrs); + if (!nr_attrs) + return 0; - return topdown_parse_events(evlist); + return ___evlist__add_default_attrs(evlist, attrs, nr_attrs); } struct evsel *arch_evlist__leader(struct list_head *list) diff --git a/tools/perf/arch/x86/util/topdown.c b/tools/perf/arch/x86/util/topdown.c index 54810f9acd6f..eb3a7d9652ab 100644 --- a/tools/perf/arch/x86/util/topdown.c +++ b/tools/perf/arch/x86/util/topdown.c @@ -9,11 +9,6 @@ #include "topdown.h" #include "evsel.h" -#define TOPDOWN_L1_EVENTS "{slots,topdown-retiring,topdown-bad-spec,topdown-fe-bound,topdown-be-bound}" -#define TOPDOWN_L1_EVENTS_CORE "{slots,cpu_core/topdown-retiring/,cpu_core/topdown-bad-spec/,cpu_core/topdown-fe-bound/,cpu_core/topdown-be-bound/}" -#define TOPDOWN_L2_EVENTS "{slots,topdown-retiring,topdown-bad-spec,topdown-fe-bound,topdown-be-bound,topdown-heavy-ops,topdown-br-mispredict,topdown-fetch-lat,topdown-mem-bound}" -#define TOPDOWN_L2_EVENTS_CORE "{slots,cpu_core/topdown-retiring/,cpu_core/topdown-bad-spec/,cpu_core/topdown-fe-bound/,cpu_core/topdown-be-bound/,cpu_core/topdown-heavy-ops/,cpu_core/topdown-br-mispredict/,cpu_core/topdown-fetch-lat/,cpu_core/topdown-mem-bound/}" - /* Check whether there is a PMU which supports the perf metrics. */ bool topdown_sys_has_perf_metrics(void) { @@ -99,28 +94,3 @@ const char *arch_get_topdown_pmu_name(struct evlist *evlist, bool warn) return pmu_name; } - -int topdown_parse_events(struct evlist *evlist) -{ - const char *topdown_events; - const char *pmu_name; - - if (!topdown_sys_has_perf_metrics()) - return 0; - - pmu_name = arch_get_topdown_pmu_name(evlist, false); - - if (pmu_have_event(pmu_name, "topdown-heavy-ops")) { - if (!strcmp(pmu_name, "cpu_core")) - topdown_events = TOPDOWN_L2_EVENTS_CORE; - else - topdown_events = TOPDOWN_L2_EVENTS; - } else { - if (!strcmp(pmu_name, "cpu_core")) - topdown_events = TOPDOWN_L1_EVENTS_CORE; - else - topdown_events = TOPDOWN_L1_EVENTS; - } - - return parse_event(evlist, topdown_events); -} diff --git a/tools/perf/arch/x86/util/topdown.h b/tools/perf/arch/x86/util/topdown.h index 7eb81f042838..46bf9273e572 100644 --- a/tools/perf/arch/x86/util/topdown.h +++ b/tools/perf/arch/x86/util/topdown.h @@ -3,6 +3,5 @@ #define _TOPDOWN_H 1 bool topdown_sys_has_perf_metrics(void); -int topdown_parse_events(struct evlist *evlist); #endif diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index 5e13171a7bba..796e98e453f6 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -1996,6 +1996,7 @@ setup_metrics: stat_config.topdown_level = TOPDOWN_MAX_LEVEL; if (!evsel_list->core.nr_entries) { + /* No events so add defaults. */ if (target__has_cpu(&target)) default_attrs0[0].config = PERF_COUNT_SW_CPU_CLOCK; @@ -2011,6 +2012,19 @@ setup_metrics: } if (evlist__add_default_attrs(evsel_list, default_attrs1) < 0) return -1; + /* + * Add TopdownL1 metrics if they exist. To minimize + * multiplexing, don't request threshold computation. + */ + if (metricgroup__has_metric("TopdownL1") && + metricgroup__parse_groups(evsel_list, "TopdownL1", + /*metric_no_group=*/false, + /*metric_no_merge=*/false, + /*metric_no_threshold=*/true, + stat_config.user_requested_cpu_list, + stat_config.system_wide, + &stat_config.metric_events) < 0) + return -1; /* Platform specific attrs */ if (evlist__add_default_attrs(evsel_list, default_null_attrs) < 0) return -1; diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index afb6f2fdc24e..64a35f2787dc 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -1647,10 +1647,8 @@ static int metricgroup__has_metric_callback(const struct pmu_metric *pm, { const char *metric = vdata; - if (!pm->metric_expr) - return 0; - - if (match_metric(pm->metric_name, metric)) + if (match_metric(pm->metric_name, metric) || + match_metric(pm->metric_group, metric)) return 1; return 0; -- cgit v1.2.3-58-ga151 From 1647cd5b8802698fb49ccb851b07b098520b5092 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:37 -0800 Subject: perf stat: Implement --topdown using json metrics Request the topdown metric group of a level with the metrics in the group 'TopdownL' rather than through specific events. As more topdown levels are supported this way, such as 6 on Intel Ice Lake, default to just showing the level 1 metrics. This can be overridden using '--td-level'. Rather than determine the maximum topdown level from sysfs, use the metric group names. Remove some now unused topdown code. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-41-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/x86/util/topdown.c | 48 +-------------- tools/perf/builtin-stat.c | 118 +++++++------------------------------ tools/perf/util/metricgroup.c | 31 ++++++++++ tools/perf/util/metricgroup.h | 1 + tools/perf/util/topdown.c | 68 +-------------------- tools/perf/util/topdown.h | 11 ++-- 6 files changed, 58 insertions(+), 219 deletions(-) (limited to 'tools') diff --git a/tools/perf/arch/x86/util/topdown.c b/tools/perf/arch/x86/util/topdown.c index eb3a7d9652ab..9ad5e5c7bd27 100644 --- a/tools/perf/arch/x86/util/topdown.c +++ b/tools/perf/arch/x86/util/topdown.c @@ -1,11 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 -#include #include "api/fs/fs.h" +#include "util/evsel.h" #include "util/pmu.h" #include "util/topdown.h" -#include "util/evlist.h" -#include "util/debug.h" -#include "util/pmu-hybrid.h" #include "topdown.h" #include "evsel.h" @@ -33,30 +30,6 @@ bool topdown_sys_has_perf_metrics(void) return has_perf_metrics; } -/* - * Check whether we can use a group for top down. - * Without a group may get bad results due to multiplexing. - */ -bool arch_topdown_check_group(bool *warn) -{ - int n; - - if (sysctl__read_int("kernel/nmi_watchdog", &n) < 0) - return false; - if (n > 0) { - *warn = true; - return false; - } - return true; -} - -void arch_topdown_group_warn(void) -{ - fprintf(stderr, - "nmi_watchdog enabled with topdown. May give wrong results.\n" - "Disable with echo 0 > /proc/sys/kernel/nmi_watchdog\n"); -} - #define TOPDOWN_SLOTS 0x0400 /* @@ -65,7 +38,6 @@ void arch_topdown_group_warn(void) * Only Topdown metric supports sample-read. The slots * event must be the leader of the topdown group. */ - bool arch_topdown_sample_read(struct evsel *leader) { if (!evsel__sys_has_perf_metrics(leader)) @@ -76,21 +48,3 @@ bool arch_topdown_sample_read(struct evsel *leader) return false; } - -const char *arch_get_topdown_pmu_name(struct evlist *evlist, bool warn) -{ - const char *pmu_name; - - if (!perf_pmu__has_hybrid()) - return "cpu"; - - if (!evlist->hybrid_pmu_name) { - if (warn) - pr_warning("WARNING: default to use cpu_core topdown events\n"); - evlist->hybrid_pmu_name = perf_pmu__hybrid_type_to_pmu("core"); - } - - pmu_name = evlist->hybrid_pmu_name; - - return pmu_name; -} diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index 796e98e453f6..bdb1ef4fc6ad 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -124,39 +124,6 @@ static const char * transaction_limited_attrs = { "}" }; -static const char * topdown_attrs[] = { - "topdown-total-slots", - "topdown-slots-retired", - "topdown-recovery-bubbles", - "topdown-fetch-bubbles", - "topdown-slots-issued", - NULL, -}; - -static const char *topdown_metric_attrs[] = { - "slots", - "topdown-retiring", - "topdown-bad-spec", - "topdown-fe-bound", - "topdown-be-bound", - NULL, -}; - -static const char *topdown_metric_L2_attrs[] = { - "slots", - "topdown-retiring", - "topdown-bad-spec", - "topdown-fe-bound", - "topdown-be-bound", - "topdown-heavy-ops", - "topdown-br-mispredict", - "topdown-fetch-lat", - "topdown-mem-bound", - NULL, -}; - -#define TOPDOWN_MAX_LEVEL 2 - static const char *smi_cost_attrs = { "{" "msr/aperf/," @@ -1914,86 +1881,41 @@ static int add_default_attributes(void) } if (topdown_run) { - const char **metric_attrs = topdown_metric_attrs; - unsigned int max_level = 1; - char *str = NULL; - bool warn = false; - const char *pmu_name = arch_get_topdown_pmu_name(evsel_list, true); + unsigned int max_level = metricgroups__topdown_max_level(); + char str[] = "TopdownL1"; if (!force_metric_only) stat_config.metric_only = true; - if (pmu_have_event(pmu_name, topdown_metric_L2_attrs[5])) { - metric_attrs = topdown_metric_L2_attrs; - max_level = 2; + if (!max_level) { + pr_err("Topdown requested but the topdown metric groups aren't present.\n" + "(See perf list the metric groups have names like TopdownL1)"); + return -1; } - if (stat_config.topdown_level > max_level) { pr_err("Invalid top-down metrics level. The max level is %u.\n", max_level); return -1; } else if (!stat_config.topdown_level) - stat_config.topdown_level = max_level; + stat_config.topdown_level = 1; - if (topdown_filter_events(metric_attrs, &str, 1, pmu_name) < 0) { - pr_err("Out of memory\n"); - return -1; - } - - if (metric_attrs[0] && str) { - if (!stat_config.interval && !stat_config.metric_only) { - fprintf(stat_config.output, - "Topdown accuracy may decrease when measuring long periods.\n" - "Please print the result regularly, e.g. -I1000\n"); - } - goto setup_metrics; - } - - zfree(&str); - - if (stat_config.aggr_mode != AGGR_GLOBAL && - stat_config.aggr_mode != AGGR_CORE) { - pr_err("top down event configuration requires --per-core mode\n"); - return -1; - } - stat_config.aggr_mode = AGGR_CORE; - if (nr_cgroups || !target__has_cpu(&target)) { - pr_err("top down event configuration requires system-wide mode (-a)\n"); - return -1; - } - - if (topdown_filter_events(topdown_attrs, &str, - arch_topdown_check_group(&warn), - pmu_name) < 0) { - pr_err("Out of memory\n"); - return -1; + if (!stat_config.interval && !stat_config.metric_only) { + fprintf(stat_config.output, + "Topdown accuracy may decrease when measuring long periods.\n" + "Please print the result regularly, e.g. -I1000\n"); } - - if (topdown_attrs[0] && str) { - struct parse_events_error errinfo; - if (warn) - arch_topdown_group_warn(); -setup_metrics: - parse_events_error__init(&errinfo); - err = parse_events(evsel_list, str, &errinfo); - if (err) { - fprintf(stderr, - "Cannot set up top down events %s: %d\n", - str, err); - parse_events_error__print(&errinfo, str); - parse_events_error__exit(&errinfo); - free(str); - return -1; - } - parse_events_error__exit(&errinfo); - } else { - fprintf(stderr, "System does not support topdown\n"); + str[8] = stat_config.topdown_level + '0'; + if (metricgroup__parse_groups(evsel_list, str, + /*metric_no_group=*/false, + /*metric_no_merge=*/false, + /*metric_no_threshold=*/true, + stat_config.user_requested_cpu_list, + stat_config.system_wide, + &stat_config.metric_events) < 0) return -1; - } - free(str); } if (!stat_config.topdown_level) - stat_config.topdown_level = TOPDOWN_MAX_LEVEL; + stat_config.topdown_level = 1; if (!evsel_list->core.nr_entries) { /* No events so add defaults. */ diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index 64a35f2787dc..de6dd527a2ba 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -1665,6 +1665,37 @@ bool metricgroup__has_metric(const char *metric) (void *)metric) ? true : false; } +static int metricgroup__topdown_max_level_callback(const struct pmu_metric *pm, + const struct pmu_metrics_table *table __maybe_unused, + void *data) +{ + unsigned int *max_level = data; + unsigned int level; + const char *p = strstr(pm->metric_group, "TopdownL"); + + if (!p || p[8] == '\0') + return 0; + + level = p[8] - '0'; + if (level > *max_level) + *max_level = level; + + return 0; +} + +unsigned int metricgroups__topdown_max_level(void) +{ + unsigned int max_level = 0; + const struct pmu_metrics_table *table = pmu_metrics_table__find(); + + if (!table) + return false; + + pmu_metrics_table_for_each_metric(table, metricgroup__topdown_max_level_callback, + &max_level); + return max_level; +} + int metricgroup__copy_metric_events(struct evlist *evlist, struct cgroup *cgrp, struct rblist *new_metric_events, struct rblist *old_metric_events) diff --git a/tools/perf/util/metricgroup.h b/tools/perf/util/metricgroup.h index 8d50052c5b4c..77472e35705e 100644 --- a/tools/perf/util/metricgroup.h +++ b/tools/perf/util/metricgroup.h @@ -81,6 +81,7 @@ int metricgroup__parse_groups_test(struct evlist *evlist, void metricgroup__print(const struct print_callbacks *print_cb, void *print_state); bool metricgroup__has_metric(const char *metric); +unsigned int metricgroups__topdown_max_level(void); int arch_get_runtimeparam(const struct pmu_metric *pm); void metricgroup__rblist_exit(struct rblist *metric_events); diff --git a/tools/perf/util/topdown.c b/tools/perf/util/topdown.c index 1090841550f7..18fd5fed5d1a 100644 --- a/tools/perf/util/topdown.c +++ b/tools/perf/util/topdown.c @@ -1,74 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 -#include -#include "pmu.h" -#include "pmu-hybrid.h" #include "topdown.h" - -int topdown_filter_events(const char **attr, char **str, bool use_group, - const char *pmu_name) -{ - int off = 0; - int i; - int len = 0; - char *s; - bool is_hybrid = perf_pmu__is_hybrid(pmu_name); - - for (i = 0; attr[i]; i++) { - if (pmu_have_event(pmu_name, attr[i])) { - if (is_hybrid) - len += strlen(attr[i]) + strlen(pmu_name) + 3; - else - len += strlen(attr[i]) + 1; - attr[i - off] = attr[i]; - } else - off++; - } - attr[i - off] = NULL; - - *str = malloc(len + 1 + 2); - if (!*str) - return -1; - s = *str; - if (i - off == 0) { - *s = 0; - return 0; - } - if (use_group) - *s++ = '{'; - for (i = 0; attr[i]; i++) { - if (!is_hybrid) - strcpy(s, attr[i]); - else - sprintf(s, "%s/%s/", pmu_name, attr[i]); - s += strlen(s); - *s++ = ','; - } - if (use_group) { - s[-1] = '}'; - *s = 0; - } else - s[-1] = 0; - return 0; -} - -__weak bool arch_topdown_check_group(bool *warn) -{ - *warn = false; - return false; -} - -__weak void arch_topdown_group_warn(void) -{ -} +#include __weak bool arch_topdown_sample_read(struct evsel *leader __maybe_unused) { return false; } - -__weak const char *arch_get_topdown_pmu_name(struct evlist *evlist - __maybe_unused, - bool warn __maybe_unused) -{ - return "cpu"; -} diff --git a/tools/perf/util/topdown.h b/tools/perf/util/topdown.h index f9531528c559..1996c5fedcd7 100644 --- a/tools/perf/util/topdown.h +++ b/tools/perf/util/topdown.h @@ -1,14 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0 */ #ifndef TOPDOWN_H #define TOPDOWN_H 1 -#include "evsel.h" -#include "evlist.h" -bool arch_topdown_check_group(bool *warn); -void arch_topdown_group_warn(void); +#include + +struct evsel; + bool arch_topdown_sample_read(struct evsel *leader); -const char *arch_get_topdown_pmu_name(struct evlist *evlist, bool warn); -int topdown_filter_events(const char **attr, char **str, bool use_group, - const char *pmu_name); #endif -- cgit v1.2.3-58-ga151 From 7b86475f02ac7d198fc52cfa780f8b93b17321ad Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:38 -0800 Subject: perf stat: Remove topdown event special handling Now the events are computed from json metrics, the hard coded logic can be removed. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-42-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/stat-shadow.c | 346 ------------------------------------------ tools/perf/util/stat.c | 13 -- tools/perf/util/stat.h | 26 ---- 3 files changed, 385 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/stat-shadow.c b/tools/perf/util/stat-shadow.c index 77483eeda0d8..5189756bf16d 100644 --- a/tools/perf/util/stat-shadow.c +++ b/tools/perf/util/stat-shadow.c @@ -241,45 +241,6 @@ void perf_stat__update_shadow_stats(struct evsel *counter, u64 count, update_runtime_stat(st, STAT_TRANSACTION, map_idx, count, &rsd); else if (perf_stat_evsel__is(counter, ELISION_START)) update_runtime_stat(st, STAT_ELISION, map_idx, count, &rsd); - else if (perf_stat_evsel__is(counter, TOPDOWN_TOTAL_SLOTS)) - update_runtime_stat(st, STAT_TOPDOWN_TOTAL_SLOTS, - map_idx, count, &rsd); - else if (perf_stat_evsel__is(counter, TOPDOWN_SLOTS_ISSUED)) - update_runtime_stat(st, STAT_TOPDOWN_SLOTS_ISSUED, - map_idx, count, &rsd); - else if (perf_stat_evsel__is(counter, TOPDOWN_SLOTS_RETIRED)) - update_runtime_stat(st, STAT_TOPDOWN_SLOTS_RETIRED, - map_idx, count, &rsd); - else if (perf_stat_evsel__is(counter, TOPDOWN_FETCH_BUBBLES)) - update_runtime_stat(st, STAT_TOPDOWN_FETCH_BUBBLES, - map_idx, count, &rsd); - else if (perf_stat_evsel__is(counter, TOPDOWN_RECOVERY_BUBBLES)) - update_runtime_stat(st, STAT_TOPDOWN_RECOVERY_BUBBLES, - map_idx, count, &rsd); - else if (perf_stat_evsel__is(counter, TOPDOWN_RETIRING)) - update_runtime_stat(st, STAT_TOPDOWN_RETIRING, - map_idx, count, &rsd); - else if (perf_stat_evsel__is(counter, TOPDOWN_BAD_SPEC)) - update_runtime_stat(st, STAT_TOPDOWN_BAD_SPEC, - map_idx, count, &rsd); - else if (perf_stat_evsel__is(counter, TOPDOWN_FE_BOUND)) - update_runtime_stat(st, STAT_TOPDOWN_FE_BOUND, - map_idx, count, &rsd); - else if (perf_stat_evsel__is(counter, TOPDOWN_BE_BOUND)) - update_runtime_stat(st, STAT_TOPDOWN_BE_BOUND, - map_idx, count, &rsd); - else if (perf_stat_evsel__is(counter, TOPDOWN_HEAVY_OPS)) - update_runtime_stat(st, STAT_TOPDOWN_HEAVY_OPS, - map_idx, count, &rsd); - else if (perf_stat_evsel__is(counter, TOPDOWN_BR_MISPREDICT)) - update_runtime_stat(st, STAT_TOPDOWN_BR_MISPREDICT, - map_idx, count, &rsd); - else if (perf_stat_evsel__is(counter, TOPDOWN_FETCH_LAT)) - update_runtime_stat(st, STAT_TOPDOWN_FETCH_LAT, - map_idx, count, &rsd); - else if (perf_stat_evsel__is(counter, TOPDOWN_MEM_BOUND)) - update_runtime_stat(st, STAT_TOPDOWN_MEM_BOUND, - map_idx, count, &rsd); else if (evsel__match(counter, HARDWARE, HW_STALLED_CYCLES_FRONTEND)) update_runtime_stat(st, STAT_STALLED_CYCLES_FRONT, map_idx, count, &rsd); @@ -524,156 +485,6 @@ static void print_ll_cache_misses(struct perf_stat_config *config, out->print_metric(config, out->ctx, color, "%7.2f%%", "of all LL-cache accesses", ratio); } -/* - * High level "TopDown" CPU core pipe line bottleneck break down. - * - * Basic concept following - * Yasin, A Top Down Method for Performance analysis and Counter architecture - * ISPASS14 - * - * The CPU pipeline is divided into 4 areas that can be bottlenecks: - * - * Frontend -> Backend -> Retiring - * BadSpeculation in addition means out of order execution that is thrown away - * (for example branch mispredictions) - * Frontend is instruction decoding. - * Backend is execution, like computation and accessing data in memory - * Retiring is good execution that is not directly bottlenecked - * - * The formulas are computed in slots. - * A slot is an entry in the pipeline each for the pipeline width - * (for example a 4-wide pipeline has 4 slots for each cycle) - * - * Formulas: - * BadSpeculation = ((SlotsIssued - SlotsRetired) + RecoveryBubbles) / - * TotalSlots - * Retiring = SlotsRetired / TotalSlots - * FrontendBound = FetchBubbles / TotalSlots - * BackendBound = 1.0 - BadSpeculation - Retiring - FrontendBound - * - * The kernel provides the mapping to the low level CPU events and any scaling - * needed for the CPU pipeline width, for example: - * - * TotalSlots = Cycles * 4 - * - * The scaling factor is communicated in the sysfs unit. - * - * In some cases the CPU may not be able to measure all the formulas due to - * missing events. In this case multiple formulas are combined, as possible. - * - * Full TopDown supports more levels to sub-divide each area: for example - * BackendBound into computing bound and memory bound. For now we only - * support Level 1 TopDown. - */ - -static double sanitize_val(double x) -{ - if (x < 0 && x >= -0.02) - return 0.0; - return x; -} - -static double td_total_slots(int map_idx, struct runtime_stat *st, - struct runtime_stat_data *rsd) -{ - return runtime_stat_avg(st, STAT_TOPDOWN_TOTAL_SLOTS, map_idx, rsd); -} - -static double td_bad_spec(int map_idx, struct runtime_stat *st, - struct runtime_stat_data *rsd) -{ - double bad_spec = 0; - double total_slots; - double total; - - total = runtime_stat_avg(st, STAT_TOPDOWN_SLOTS_ISSUED, map_idx, rsd) - - runtime_stat_avg(st, STAT_TOPDOWN_SLOTS_RETIRED, map_idx, rsd) + - runtime_stat_avg(st, STAT_TOPDOWN_RECOVERY_BUBBLES, map_idx, rsd); - - total_slots = td_total_slots(map_idx, st, rsd); - if (total_slots) - bad_spec = total / total_slots; - return sanitize_val(bad_spec); -} - -static double td_retiring(int map_idx, struct runtime_stat *st, - struct runtime_stat_data *rsd) -{ - double retiring = 0; - double total_slots = td_total_slots(map_idx, st, rsd); - double ret_slots = runtime_stat_avg(st, STAT_TOPDOWN_SLOTS_RETIRED, - map_idx, rsd); - - if (total_slots) - retiring = ret_slots / total_slots; - return retiring; -} - -static double td_fe_bound(int map_idx, struct runtime_stat *st, - struct runtime_stat_data *rsd) -{ - double fe_bound = 0; - double total_slots = td_total_slots(map_idx, st, rsd); - double fetch_bub = runtime_stat_avg(st, STAT_TOPDOWN_FETCH_BUBBLES, - map_idx, rsd); - - if (total_slots) - fe_bound = fetch_bub / total_slots; - return fe_bound; -} - -static double td_be_bound(int map_idx, struct runtime_stat *st, - struct runtime_stat_data *rsd) -{ - double sum = (td_fe_bound(map_idx, st, rsd) + - td_bad_spec(map_idx, st, rsd) + - td_retiring(map_idx, st, rsd)); - if (sum == 0) - return 0; - return sanitize_val(1.0 - sum); -} - -/* - * Kernel reports metrics multiplied with slots. To get back - * the ratios we need to recreate the sum. - */ - -static double td_metric_ratio(int map_idx, enum stat_type type, - struct runtime_stat *stat, - struct runtime_stat_data *rsd) -{ - double sum = runtime_stat_avg(stat, STAT_TOPDOWN_RETIRING, map_idx, rsd) + - runtime_stat_avg(stat, STAT_TOPDOWN_FE_BOUND, map_idx, rsd) + - runtime_stat_avg(stat, STAT_TOPDOWN_BE_BOUND, map_idx, rsd) + - runtime_stat_avg(stat, STAT_TOPDOWN_BAD_SPEC, map_idx, rsd); - double d = runtime_stat_avg(stat, type, map_idx, rsd); - - if (sum) - return d / sum; - return 0; -} - -/* - * ... but only if most of the values are actually available. - * We allow two missing. - */ - -static bool full_td(int map_idx, struct runtime_stat *stat, - struct runtime_stat_data *rsd) -{ - int c = 0; - - if (runtime_stat_avg(stat, STAT_TOPDOWN_RETIRING, map_idx, rsd) > 0) - c++; - if (runtime_stat_avg(stat, STAT_TOPDOWN_BE_BOUND, map_idx, rsd) > 0) - c++; - if (runtime_stat_avg(stat, STAT_TOPDOWN_FE_BOUND, map_idx, rsd) > 0) - c++; - if (runtime_stat_avg(stat, STAT_TOPDOWN_BAD_SPEC, map_idx, rsd) > 0) - c++; - return c >= 2; -} - static void print_smi_cost(struct perf_stat_config *config, int map_idx, struct perf_stat_output_ctx *out, struct runtime_stat *st, @@ -885,7 +696,6 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, void *ctxp = out->ctx; print_metric_t print_metric = out->print_metric; double total, ratio = 0.0, total2; - const char *color = NULL; struct runtime_stat_data rsd = { .ctx = evsel_context(evsel), .cgrp = evsel->cgrp, @@ -1044,162 +854,6 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, avg / (ratio * evsel->scale)); else print_metric(config, ctxp, NULL, NULL, "CPUs utilized", 0); - } else if (perf_stat_evsel__is(evsel, TOPDOWN_FETCH_BUBBLES)) { - double fe_bound = td_fe_bound(map_idx, st, &rsd); - - if (fe_bound > 0.2) - color = PERF_COLOR_RED; - print_metric(config, ctxp, color, "%8.1f%%", "frontend bound", - fe_bound * 100.); - } else if (perf_stat_evsel__is(evsel, TOPDOWN_SLOTS_RETIRED)) { - double retiring = td_retiring(map_idx, st, &rsd); - - if (retiring > 0.7) - color = PERF_COLOR_GREEN; - print_metric(config, ctxp, color, "%8.1f%%", "retiring", - retiring * 100.); - } else if (perf_stat_evsel__is(evsel, TOPDOWN_RECOVERY_BUBBLES)) { - double bad_spec = td_bad_spec(map_idx, st, &rsd); - - if (bad_spec > 0.1) - color = PERF_COLOR_RED; - print_metric(config, ctxp, color, "%8.1f%%", "bad speculation", - bad_spec * 100.); - } else if (perf_stat_evsel__is(evsel, TOPDOWN_SLOTS_ISSUED)) { - double be_bound = td_be_bound(map_idx, st, &rsd); - const char *name = "backend bound"; - static int have_recovery_bubbles = -1; - - /* In case the CPU does not support topdown-recovery-bubbles */ - if (have_recovery_bubbles < 0) - have_recovery_bubbles = pmu_have_event("cpu", - "topdown-recovery-bubbles"); - if (!have_recovery_bubbles) - name = "backend bound/bad spec"; - - if (be_bound > 0.2) - color = PERF_COLOR_RED; - if (td_total_slots(map_idx, st, &rsd) > 0) - print_metric(config, ctxp, color, "%8.1f%%", name, - be_bound * 100.); - else - print_metric(config, ctxp, NULL, NULL, name, 0); - } else if (perf_stat_evsel__is(evsel, TOPDOWN_RETIRING) && - full_td(map_idx, st, &rsd)) { - double retiring = td_metric_ratio(map_idx, - STAT_TOPDOWN_RETIRING, st, - &rsd); - if (retiring > 0.7) - color = PERF_COLOR_GREEN; - print_metric(config, ctxp, color, "%8.1f%%", "Retiring", - retiring * 100.); - } else if (perf_stat_evsel__is(evsel, TOPDOWN_FE_BOUND) && - full_td(map_idx, st, &rsd)) { - double fe_bound = td_metric_ratio(map_idx, - STAT_TOPDOWN_FE_BOUND, st, - &rsd); - if (fe_bound > 0.2) - color = PERF_COLOR_RED; - print_metric(config, ctxp, color, "%8.1f%%", "Frontend Bound", - fe_bound * 100.); - } else if (perf_stat_evsel__is(evsel, TOPDOWN_BE_BOUND) && - full_td(map_idx, st, &rsd)) { - double be_bound = td_metric_ratio(map_idx, - STAT_TOPDOWN_BE_BOUND, st, - &rsd); - if (be_bound > 0.2) - color = PERF_COLOR_RED; - print_metric(config, ctxp, color, "%8.1f%%", "Backend Bound", - be_bound * 100.); - } else if (perf_stat_evsel__is(evsel, TOPDOWN_BAD_SPEC) && - full_td(map_idx, st, &rsd)) { - double bad_spec = td_metric_ratio(map_idx, - STAT_TOPDOWN_BAD_SPEC, st, - &rsd); - if (bad_spec > 0.1) - color = PERF_COLOR_RED; - print_metric(config, ctxp, color, "%8.1f%%", "Bad Speculation", - bad_spec * 100.); - } else if (perf_stat_evsel__is(evsel, TOPDOWN_HEAVY_OPS) && - full_td(map_idx, st, &rsd) && (config->topdown_level > 1)) { - double retiring = td_metric_ratio(map_idx, - STAT_TOPDOWN_RETIRING, st, - &rsd); - double heavy_ops = td_metric_ratio(map_idx, - STAT_TOPDOWN_HEAVY_OPS, st, - &rsd); - double light_ops = retiring - heavy_ops; - - if (retiring > 0.7 && heavy_ops > 0.1) - color = PERF_COLOR_GREEN; - print_metric(config, ctxp, color, "%8.1f%%", "Heavy Operations", - heavy_ops * 100.); - if (retiring > 0.7 && light_ops > 0.6) - color = PERF_COLOR_GREEN; - else - color = NULL; - print_metric(config, ctxp, color, "%8.1f%%", "Light Operations", - light_ops * 100.); - } else if (perf_stat_evsel__is(evsel, TOPDOWN_BR_MISPREDICT) && - full_td(map_idx, st, &rsd) && (config->topdown_level > 1)) { - double bad_spec = td_metric_ratio(map_idx, - STAT_TOPDOWN_BAD_SPEC, st, - &rsd); - double br_mis = td_metric_ratio(map_idx, - STAT_TOPDOWN_BR_MISPREDICT, st, - &rsd); - double m_clears = bad_spec - br_mis; - - if (bad_spec > 0.1 && br_mis > 0.05) - color = PERF_COLOR_RED; - print_metric(config, ctxp, color, "%8.1f%%", "Branch Mispredict", - br_mis * 100.); - if (bad_spec > 0.1 && m_clears > 0.05) - color = PERF_COLOR_RED; - else - color = NULL; - print_metric(config, ctxp, color, "%8.1f%%", "Machine Clears", - m_clears * 100.); - } else if (perf_stat_evsel__is(evsel, TOPDOWN_FETCH_LAT) && - full_td(map_idx, st, &rsd) && (config->topdown_level > 1)) { - double fe_bound = td_metric_ratio(map_idx, - STAT_TOPDOWN_FE_BOUND, st, - &rsd); - double fetch_lat = td_metric_ratio(map_idx, - STAT_TOPDOWN_FETCH_LAT, st, - &rsd); - double fetch_bw = fe_bound - fetch_lat; - - if (fe_bound > 0.2 && fetch_lat > 0.15) - color = PERF_COLOR_RED; - print_metric(config, ctxp, color, "%8.1f%%", "Fetch Latency", - fetch_lat * 100.); - if (fe_bound > 0.2 && fetch_bw > 0.1) - color = PERF_COLOR_RED; - else - color = NULL; - print_metric(config, ctxp, color, "%8.1f%%", "Fetch Bandwidth", - fetch_bw * 100.); - } else if (perf_stat_evsel__is(evsel, TOPDOWN_MEM_BOUND) && - full_td(map_idx, st, &rsd) && (config->topdown_level > 1)) { - double be_bound = td_metric_ratio(map_idx, - STAT_TOPDOWN_BE_BOUND, st, - &rsd); - double mem_bound = td_metric_ratio(map_idx, - STAT_TOPDOWN_MEM_BOUND, st, - &rsd); - double core_bound = be_bound - mem_bound; - - if (be_bound > 0.2 && mem_bound > 0.2) - color = PERF_COLOR_RED; - print_metric(config, ctxp, color, "%8.1f%%", "Memory Bound", - mem_bound * 100.); - if (be_bound > 0.2 && core_bound > 0.1) - color = PERF_COLOR_RED; - else - color = NULL; - print_metric(config, ctxp, color, "%8.1f%%", "Core Bound", - core_bound * 100.); } else if (runtime_stat_n(st, STAT_NSECS, map_idx, &rsd) != 0) { char unit = ' '; char unit_buf[10] = "/sec"; diff --git a/tools/perf/util/stat.c b/tools/perf/util/stat.c index 534d36d26fc3..0b8c91ca13cd 100644 --- a/tools/perf/util/stat.c +++ b/tools/perf/util/stat.c @@ -91,19 +91,6 @@ static const char *id_str[PERF_STAT_EVSEL_ID__MAX] = { ID(TRANSACTION_START, cpu/tx-start/), ID(ELISION_START, cpu/el-start/), ID(CYCLES_IN_TX_CP, cpu/cycles-ct/), - ID(TOPDOWN_TOTAL_SLOTS, topdown-total-slots), - ID(TOPDOWN_SLOTS_ISSUED, topdown-slots-issued), - ID(TOPDOWN_SLOTS_RETIRED, topdown-slots-retired), - ID(TOPDOWN_FETCH_BUBBLES, topdown-fetch-bubbles), - ID(TOPDOWN_RECOVERY_BUBBLES, topdown-recovery-bubbles), - ID(TOPDOWN_RETIRING, topdown-retiring), - ID(TOPDOWN_BAD_SPEC, topdown-bad-spec), - ID(TOPDOWN_FE_BOUND, topdown-fe-bound), - ID(TOPDOWN_BE_BOUND, topdown-be-bound), - ID(TOPDOWN_HEAVY_OPS, topdown-heavy-ops), - ID(TOPDOWN_BR_MISPREDICT, topdown-br-mispredict), - ID(TOPDOWN_FETCH_LAT, topdown-fetch-lat), - ID(TOPDOWN_MEM_BOUND, topdown-mem-bound), ID(SMI_NUM, msr/smi/), ID(APERF, msr/aperf/), }; diff --git a/tools/perf/util/stat.h b/tools/perf/util/stat.h index cf2d8aa445f3..42af350a96d9 100644 --- a/tools/perf/util/stat.h +++ b/tools/perf/util/stat.h @@ -25,19 +25,6 @@ enum perf_stat_evsel_id { PERF_STAT_EVSEL_ID__TRANSACTION_START, PERF_STAT_EVSEL_ID__ELISION_START, PERF_STAT_EVSEL_ID__CYCLES_IN_TX_CP, - PERF_STAT_EVSEL_ID__TOPDOWN_TOTAL_SLOTS, - PERF_STAT_EVSEL_ID__TOPDOWN_SLOTS_ISSUED, - PERF_STAT_EVSEL_ID__TOPDOWN_SLOTS_RETIRED, - PERF_STAT_EVSEL_ID__TOPDOWN_FETCH_BUBBLES, - PERF_STAT_EVSEL_ID__TOPDOWN_RECOVERY_BUBBLES, - PERF_STAT_EVSEL_ID__TOPDOWN_RETIRING, - PERF_STAT_EVSEL_ID__TOPDOWN_BAD_SPEC, - PERF_STAT_EVSEL_ID__TOPDOWN_FE_BOUND, - PERF_STAT_EVSEL_ID__TOPDOWN_BE_BOUND, - PERF_STAT_EVSEL_ID__TOPDOWN_HEAVY_OPS, - PERF_STAT_EVSEL_ID__TOPDOWN_BR_MISPREDICT, - PERF_STAT_EVSEL_ID__TOPDOWN_FETCH_LAT, - PERF_STAT_EVSEL_ID__TOPDOWN_MEM_BOUND, PERF_STAT_EVSEL_ID__SMI_NUM, PERF_STAT_EVSEL_ID__APERF, PERF_STAT_EVSEL_ID__MAX, @@ -108,19 +95,6 @@ enum stat_type { STAT_CYCLES_IN_TX, STAT_TRANSACTION, STAT_ELISION, - STAT_TOPDOWN_TOTAL_SLOTS, - STAT_TOPDOWN_SLOTS_ISSUED, - STAT_TOPDOWN_SLOTS_RETIRED, - STAT_TOPDOWN_FETCH_BUBBLES, - STAT_TOPDOWN_RECOVERY_BUBBLES, - STAT_TOPDOWN_RETIRING, - STAT_TOPDOWN_BAD_SPEC, - STAT_TOPDOWN_FE_BOUND, - STAT_TOPDOWN_BE_BOUND, - STAT_TOPDOWN_HEAVY_OPS, - STAT_TOPDOWN_BR_MISPREDICT, - STAT_TOPDOWN_FETCH_LAT, - STAT_TOPDOWN_MEM_BOUND, STAT_SMI_NUM, STAT_APERF, STAT_MAX -- cgit v1.2.3-58-ga151 From 20cb10eadbddcacda277f471c32000da9ae60d41 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:39 -0800 Subject: perf doc: Refresh topdown documentation perf stat now supports --topdown for any platform with the TopdownL1 metric group including Intel before Icelake. Tweak the documentation to reflect this. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-43-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Documentation/perf-stat.txt | 27 +++++++------ tools/perf/Documentation/topdown.txt | 70 ++++++++++++++-------------------- 2 files changed, 44 insertions(+), 53 deletions(-) (limited to 'tools') diff --git a/tools/perf/Documentation/perf-stat.txt b/tools/perf/Documentation/perf-stat.txt index 18abdc1dce05..29bdcfa93f04 100644 --- a/tools/perf/Documentation/perf-stat.txt +++ b/tools/perf/Documentation/perf-stat.txt @@ -394,10 +394,10 @@ See perf list output for the possible metrics and metricgroups. Do not aggregate counts across all monitored CPUs. --topdown:: -Print complete top-down metrics supported by the CPU. This allows to -determine bottle necks in the CPU pipeline for CPU bound workloads, -by breaking the cycles consumed down into frontend bound, backend bound, -bad speculation and retiring. +Print top-down metrics supported by the CPU. This allows to determine +bottle necks in the CPU pipeline for CPU bound workloads, by breaking +the cycles consumed down into frontend bound, backend bound, bad +speculation and retiring. Frontend bound means that the CPU cannot fetch and decode instructions fast enough. Backend bound means that computation or memory access is the bottle @@ -430,15 +430,18 @@ CPUs the workload runs on. If needed the CPUs can be forced using taskset. --td-level:: -Print the top-down statistics that equal to or lower than the input level. -It allows users to print the interested top-down metrics level instead of -the complete top-down metrics. +Print the top-down statistics that equal the input level. It allows +users to print the interested top-down metrics level instead of the +level 1 top-down metrics. + +As the higher levels gather more metrics and use more counters they +will be less accurate. By convention a metric can be examined by +appending '_group' to it and this will increase accuracy compared to +gathering all metrics for a level. For example, level 1 analysis may +highlight 'tma_frontend_bound'. This metric may be drilled into with +'tma_frontend_bound_group' with +'perf stat -M tma_frontend_bound_group...'. -The availability of the top-down metrics level depends on the hardware. For -example, Ice Lake only supports L1 top-down metrics. The Sapphire Rapids -supports both L1 and L2 top-down metrics. - -Default: 0 means the max level that the current hardware support. Error out if the input is higher than the supported max level. --no-merge:: diff --git a/tools/perf/Documentation/topdown.txt b/tools/perf/Documentation/topdown.txt index a15b93fdcf50..ae0aee86844f 100644 --- a/tools/perf/Documentation/topdown.txt +++ b/tools/perf/Documentation/topdown.txt @@ -1,46 +1,35 @@ -Using TopDown metrics in user space ------------------------------------ +Using TopDown metrics +--------------------- -Intel CPUs (since Sandy Bridge and Silvermont) support a TopDown -methodology to break down CPU pipeline execution into 4 bottlenecks: -frontend bound, backend bound, bad speculation, retiring. +TopDown metrics break apart performance bottlenecks. Starting at level +1 it is typical to get metrics on retiring, bad speculation, frontend +bound, and backend bound. Higher levels provide more detail in to the +level 1 bottlenecks, such as at level 2: core bound, memory bound, +heavy operations, light operations, branch mispredicts, machine +clears, fetch latency and fetch bandwidth. For more details see [1][2][3]. -For more details on Topdown see [1][5] +perf stat --topdown implements this using available metrics that vary +per architecture. -Traditionally this was implemented by events in generic counters -and specific formulas to compute the bottlenecks. - -perf stat --topdown implements this. - -Full Top Down includes more levels that can break down the -bottlenecks further. This is not directly implemented in perf, -but available in other tools that can run on top of perf, -such as toplev[2] or vtune[3] +% perf stat -a --topdown -I1000 +# time % tma_retiring % tma_backend_bound % tma_frontend_bound % tma_bad_speculation + 1.001141351 11.5 34.9 46.9 6.7 + 2.006141972 13.4 28.1 50.4 8.1 + 3.010162040 12.9 28.1 51.1 8.0 + 4.014009311 12.5 28.6 51.8 7.2 + 5.017838554 11.8 33.0 48.0 7.2 + 5.704818971 14.0 27.5 51.3 7.3 +... -New Topdown features in Ice Lake -=============================== +New Topdown features in Intel Ice Lake +====================================== With Ice Lake CPUs the TopDown metrics are directly available as fixed counters and do not require generic counters. This allows to collect TopDown always in addition to other events. -% perf stat -a --topdown -I1000 -# time retiring bad speculation frontend bound backend bound - 1.001281330 23.0% 15.3% 29.6% 32.1% - 2.003009005 5.0% 6.8% 46.6% 41.6% - 3.004646182 6.7% 6.7% 46.0% 40.6% - 4.006326375 5.0% 6.4% 47.6% 41.0% - 5.007991804 5.1% 6.3% 46.3% 42.3% - 6.009626773 6.2% 7.1% 47.3% 39.3% - 7.011296356 4.7% 6.7% 46.2% 42.4% - 8.012951831 4.7% 6.7% 47.5% 41.1% -... - -This also enables measuring TopDown per thread/process instead -of only per core. - -Using TopDown through RDPMC in applications on Ice Lake -====================================================== +Using TopDown through RDPMC in applications on Intel Ice Lake +============================================================= For more fine grained measurements it can be useful to access the new directly from user space. This is more complicated, @@ -301,8 +290,8 @@ This "opens" a new measurement period. A program using RDPMC for TopDown should schedule such a reset regularly, as in every few seconds. -Limits on Ice Lake -================== +Limits on Intel Ice Lake +======================== Four pseudo TopDown metric events are exposed for the end-users, topdown-retiring, topdown-bad-spec, topdown-fe-bound and topdown-be-bound. @@ -318,8 +307,8 @@ a sampling read group. Since the SLOTS event must be the leader of a TopDown group, the second event of the group is the sampling event. For example, perf record -e '{slots, $sampling_event, topdown-retiring}:S' -Extension on Sapphire Rapids Server -=================================== +Extension on Intel Sapphire Rapids Server +========================================= The metrics counter is extended to support TMA method level 2 metrics. The lower half of the register is the TMA level 1 metrics (legacy). The upper half is also divided into four 8-bit fields for the new level 2 @@ -338,7 +327,6 @@ other four level 2 metrics by subtracting corresponding metrics as below. [1] https://software.intel.com/en-us/top-down-microarchitecture-analysis-method-win -[2] https://github.com/andikleen/pmu-tools/wiki/toplev-manual -[3] https://software.intel.com/en-us/intel-vtune-amplifier-xe +[2] https://sites.google.com/site/analysismethods/yasin-pubs +[3] https://perf.wiki.kernel.org/index.php/Top-Down_Analysis [4] https://github.com/andikleen/pmu-tools/tree/master/jevents -[5] https://sites.google.com/site/analysismethods/yasin-pubs -- cgit v1.2.3-58-ga151 From d6964c5b1f76518e425f9aef05670a0933903207 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:40 -0800 Subject: perf stat: Remove hard coded transaction events The metric group "transaction" is now present for Intel architectures so the legacy hard coded approach won't be used. Remove the associated logic. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-44-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-stat.c | 59 ++++++++----------------------------------- tools/perf/util/stat-shadow.c | 48 +---------------------------------- tools/perf/util/stat.c | 4 --- tools/perf/util/stat.h | 7 ----- 4 files changed, 11 insertions(+), 107 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index bdb1ef4fc6ad..e6b60b058257 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -100,30 +100,6 @@ static void print_counters(struct timespec *ts, int argc, const char **argv); -/* Default events used for perf stat -T */ -static const char *transaction_attrs = { - "task-clock," - "{" - "instructions," - "cycles," - "cpu/cycles-t/," - "cpu/tx-start/," - "cpu/el-start/," - "cpu/cycles-ct/" - "}" -}; - -/* More limited version when the CPU does not have all events. */ -static const char * transaction_limited_attrs = { - "task-clock," - "{" - "instructions," - "cycles," - "cpu/cycles-t/," - "cpu/tx-start/" - "}" -}; - static const char *smi_cost_attrs = { "{" "msr/aperf/," @@ -1811,37 +1787,22 @@ static int add_default_attributes(void) return 0; if (transaction_run) { - struct parse_events_error errinfo; /* Handle -T as -M transaction. Once platform specific metrics * support has been added to the json files, all architectures * will use this approach. To determine transaction support * on an architecture test for such a metric name. */ - if (metricgroup__has_metric("transaction")) { - return metricgroup__parse_groups(evsel_list, "transaction", - stat_config.metric_no_group, - stat_config.metric_no_merge, - stat_config.metric_no_threshold, - stat_config.user_requested_cpu_list, - stat_config.system_wide, - &stat_config.metric_events); - } - - parse_events_error__init(&errinfo); - if (pmu_have_event("cpu", "cycles-ct") && - pmu_have_event("cpu", "el-start")) - err = parse_events(evsel_list, transaction_attrs, - &errinfo); - else - err = parse_events(evsel_list, - transaction_limited_attrs, - &errinfo); - if (err) { - fprintf(stderr, "Cannot set up transaction events\n"); - parse_events_error__print(&errinfo, transaction_attrs); + if (!metricgroup__has_metric("transaction")) { + pr_err("Missing transaction metrics"); + return -1; } - parse_events_error__exit(&errinfo); - return err ? -1 : 0; + return metricgroup__parse_groups(evsel_list, "transaction", + stat_config.metric_no_group, + stat_config.metric_no_merge, + stat_config.metric_no_threshold, + stat_config.user_requested_cpu_list, + stat_config.system_wide, + &stat_config.metric_events); } if (smi_cost) { diff --git a/tools/perf/util/stat-shadow.c b/tools/perf/util/stat-shadow.c index 5189756bf16d..3cfe4b4eb3de 100644 --- a/tools/perf/util/stat-shadow.c +++ b/tools/perf/util/stat-shadow.c @@ -235,12 +235,6 @@ void perf_stat__update_shadow_stats(struct evsel *counter, u64 count, update_runtime_stat(st, STAT_NSECS, map_idx, count_ns, &rsd); else if (evsel__match(counter, HARDWARE, HW_CPU_CYCLES)) update_runtime_stat(st, STAT_CYCLES, map_idx, count, &rsd); - else if (perf_stat_evsel__is(counter, CYCLES_IN_TX)) - update_runtime_stat(st, STAT_CYCLES_IN_TX, map_idx, count, &rsd); - else if (perf_stat_evsel__is(counter, TRANSACTION_START)) - update_runtime_stat(st, STAT_TRANSACTION, map_idx, count, &rsd); - else if (perf_stat_evsel__is(counter, ELISION_START)) - update_runtime_stat(st, STAT_ELISION, map_idx, count, &rsd); else if (evsel__match(counter, HARDWARE, HW_STALLED_CYCLES_FRONTEND)) update_runtime_stat(st, STAT_STALLED_CYCLES_FRONT, map_idx, count, &rsd); @@ -695,7 +689,7 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, { void *ctxp = out->ctx; print_metric_t print_metric = out->print_metric; - double total, ratio = 0.0, total2; + double total, ratio = 0.0; struct runtime_stat_data rsd = { .ctx = evsel_context(evsel), .cgrp = evsel->cgrp, @@ -808,46 +802,6 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, } else { print_metric(config, ctxp, NULL, NULL, "Ghz", 0); } - } else if (perf_stat_evsel__is(evsel, CYCLES_IN_TX)) { - total = runtime_stat_avg(st, STAT_CYCLES, map_idx, &rsd); - - if (total) - print_metric(config, ctxp, NULL, - "%7.2f%%", "transactional cycles", - 100.0 * (avg / total)); - else - print_metric(config, ctxp, NULL, NULL, "transactional cycles", - 0); - } else if (perf_stat_evsel__is(evsel, CYCLES_IN_TX_CP)) { - total = runtime_stat_avg(st, STAT_CYCLES, map_idx, &rsd); - total2 = runtime_stat_avg(st, STAT_CYCLES_IN_TX, map_idx, &rsd); - - if (total2 < avg) - total2 = avg; - if (total) - print_metric(config, ctxp, NULL, "%7.2f%%", "aborted cycles", - 100.0 * ((total2-avg) / total)); - else - print_metric(config, ctxp, NULL, NULL, "aborted cycles", 0); - } else if (perf_stat_evsel__is(evsel, TRANSACTION_START)) { - total = runtime_stat_avg(st, STAT_CYCLES_IN_TX, map_idx, &rsd); - - if (avg) - ratio = total / avg; - - if (runtime_stat_n(st, STAT_CYCLES_IN_TX, map_idx, &rsd) != 0) - print_metric(config, ctxp, NULL, "%8.0f", - "cycles / transaction", ratio); - else - print_metric(config, ctxp, NULL, NULL, "cycles / transaction", - 0); - } else if (perf_stat_evsel__is(evsel, ELISION_START)) { - total = runtime_stat_avg(st, STAT_CYCLES_IN_TX, map_idx, &rsd); - - if (avg) - ratio = total / avg; - - print_metric(config, ctxp, NULL, "%8.0f", "cycles / elision", ratio); } else if (evsel__is_clock(evsel)) { if ((ratio = avg_stats(&walltime_nsecs_stats)) != 0) print_metric(config, ctxp, NULL, "%8.3f", "CPUs utilized", diff --git a/tools/perf/util/stat.c b/tools/perf/util/stat.c index 0b8c91ca13cd..b5b18d457254 100644 --- a/tools/perf/util/stat.c +++ b/tools/perf/util/stat.c @@ -87,10 +87,6 @@ bool __perf_stat_evsel__is(struct evsel *evsel, enum perf_stat_evsel_id id) #define ID(id, name) [PERF_STAT_EVSEL_ID__##id] = #name static const char *id_str[PERF_STAT_EVSEL_ID__MAX] = { ID(NONE, x), - ID(CYCLES_IN_TX, cpu/cycles-t/), - ID(TRANSACTION_START, cpu/tx-start/), - ID(ELISION_START, cpu/el-start/), - ID(CYCLES_IN_TX_CP, cpu/cycles-ct/), ID(SMI_NUM, msr/smi/), ID(APERF, msr/aperf/), }; diff --git a/tools/perf/util/stat.h b/tools/perf/util/stat.h index 42af350a96d9..c5fe847dd344 100644 --- a/tools/perf/util/stat.h +++ b/tools/perf/util/stat.h @@ -21,10 +21,6 @@ struct stats { enum perf_stat_evsel_id { PERF_STAT_EVSEL_ID__NONE = 0, - PERF_STAT_EVSEL_ID__CYCLES_IN_TX, - PERF_STAT_EVSEL_ID__TRANSACTION_START, - PERF_STAT_EVSEL_ID__ELISION_START, - PERF_STAT_EVSEL_ID__CYCLES_IN_TX_CP, PERF_STAT_EVSEL_ID__SMI_NUM, PERF_STAT_EVSEL_ID__APERF, PERF_STAT_EVSEL_ID__MAX, @@ -92,9 +88,6 @@ enum stat_type { STAT_LL_CACHE, STAT_ITLB_CACHE, STAT_DTLB_CACHE, - STAT_CYCLES_IN_TX, - STAT_TRANSACTION, - STAT_ELISION, STAT_SMI_NUM, STAT_APERF, STAT_MAX -- cgit v1.2.3-58-ga151 From c23f5cc06ac5dc556fccd2c9ac648fa84fb876fd Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:41 -0800 Subject: perf stat: Use metrics for --smi-cost Rather than parsing events for --smi-cost, use the json metric group 'smi'. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-45-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-stat.c | 34 +++++++++++----------------------- tools/perf/util/stat-shadow.c | 30 ------------------------------ tools/perf/util/stat.c | 2 -- tools/perf/util/stat.h | 4 ---- 4 files changed, 11 insertions(+), 59 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index e6b60b058257..9c1fbf154ee3 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -100,14 +100,6 @@ static void print_counters(struct timespec *ts, int argc, const char **argv); -static const char *smi_cost_attrs = { - "{" - "msr/aperf/," - "msr/smi/," - "cycles" - "}" -}; - static struct evlist *evsel_list; static bool all_counters_use_bpf = true; @@ -1666,7 +1658,6 @@ static int perf_stat_init_aggr_mode_file(struct perf_stat *st) */ static int add_default_attributes(void) { - int err; struct perf_event_attr default_attrs0[] = { { .type = PERF_TYPE_SOFTWARE, .config = PERF_COUNT_SW_TASK_CLOCK }, @@ -1806,11 +1797,10 @@ static int add_default_attributes(void) } if (smi_cost) { - struct parse_events_error errinfo; int smi; if (sysfs__read_int(FREEZE_ON_SMI_PATH, &smi) < 0) { - fprintf(stderr, "freeze_on_smi is not supported.\n"); + pr_err("freeze_on_smi is not supported."); return -1; } @@ -1822,23 +1812,21 @@ static int add_default_attributes(void) smi_reset = true; } - if (!pmu_have_event("msr", "aperf") || - !pmu_have_event("msr", "smi")) { - fprintf(stderr, "To measure SMI cost, it needs " - "msr/aperf/, msr/smi/ and cpu/cycles/ support\n"); + if (!metricgroup__has_metric("smi")) { + pr_err("Missing smi metrics"); return -1; } + if (!force_metric_only) stat_config.metric_only = true; - parse_events_error__init(&errinfo); - err = parse_events(evsel_list, smi_cost_attrs, &errinfo); - if (err) { - parse_events_error__print(&errinfo, smi_cost_attrs); - fprintf(stderr, "Cannot set up SMI cost events\n"); - } - parse_events_error__exit(&errinfo); - return err ? -1 : 0; + return metricgroup__parse_groups(evsel_list, "smi", + stat_config.metric_no_group, + stat_config.metric_no_merge, + stat_config.metric_no_threshold, + stat_config.user_requested_cpu_list, + stat_config.system_wide, + &stat_config.metric_events); } if (topdown_run) { diff --git a/tools/perf/util/stat-shadow.c b/tools/perf/util/stat-shadow.c index 3cfe4b4eb3de..d14fa531ee27 100644 --- a/tools/perf/util/stat-shadow.c +++ b/tools/perf/util/stat-shadow.c @@ -255,10 +255,6 @@ void perf_stat__update_shadow_stats(struct evsel *counter, u64 count, update_runtime_stat(st, STAT_DTLB_CACHE, map_idx, count, &rsd); else if (evsel__match(counter, HW_CACHE, HW_CACHE_ITLB)) update_runtime_stat(st, STAT_ITLB_CACHE, map_idx, count, &rsd); - else if (perf_stat_evsel__is(counter, SMI_NUM)) - update_runtime_stat(st, STAT_SMI_NUM, map_idx, count, &rsd); - else if (perf_stat_evsel__is(counter, APERF)) - update_runtime_stat(st, STAT_APERF, map_idx, count, &rsd); if (counter->collect_stat) { v = saved_value_lookup(counter, map_idx, true, STAT_NONE, 0, st, @@ -479,30 +475,6 @@ static void print_ll_cache_misses(struct perf_stat_config *config, out->print_metric(config, out->ctx, color, "%7.2f%%", "of all LL-cache accesses", ratio); } -static void print_smi_cost(struct perf_stat_config *config, int map_idx, - struct perf_stat_output_ctx *out, - struct runtime_stat *st, - struct runtime_stat_data *rsd) -{ - double smi_num, aperf, cycles, cost = 0.0; - const char *color = NULL; - - smi_num = runtime_stat_avg(st, STAT_SMI_NUM, map_idx, rsd); - aperf = runtime_stat_avg(st, STAT_APERF, map_idx, rsd); - cycles = runtime_stat_avg(st, STAT_CYCLES, map_idx, rsd); - - if ((cycles == 0) || (aperf == 0)) - return; - - if (smi_num) - cost = (aperf - cycles) / aperf * 100.00; - - if (cost > 10) - color = PERF_COLOR_RED; - out->print_metric(config, out->ctx, color, "%8.1f%%", "SMI cycles%", cost); - out->print_metric(config, out->ctx, NULL, "%4.0f", "SMI#", smi_num); -} - static int prepare_metric(struct evsel **metric_events, struct metric_ref *metric_refs, struct expr_parse_ctx *pctx, @@ -819,8 +791,6 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, if (unit != ' ') snprintf(unit_buf, sizeof(unit_buf), "%c/sec", unit); print_metric(config, ctxp, NULL, "%8.3f", unit_buf, ratio); - } else if (perf_stat_evsel__is(evsel, SMI_NUM)) { - print_smi_cost(config, map_idx, out, st, &rsd); } else { num = 0; } diff --git a/tools/perf/util/stat.c b/tools/perf/util/stat.c index b5b18d457254..d51d7457f12d 100644 --- a/tools/perf/util/stat.c +++ b/tools/perf/util/stat.c @@ -87,8 +87,6 @@ bool __perf_stat_evsel__is(struct evsel *evsel, enum perf_stat_evsel_id id) #define ID(id, name) [PERF_STAT_EVSEL_ID__##id] = #name static const char *id_str[PERF_STAT_EVSEL_ID__MAX] = { ID(NONE, x), - ID(SMI_NUM, msr/smi/), - ID(APERF, msr/aperf/), }; #undef ID diff --git a/tools/perf/util/stat.h b/tools/perf/util/stat.h index c5fe847dd344..9af4af3bc3f2 100644 --- a/tools/perf/util/stat.h +++ b/tools/perf/util/stat.h @@ -21,8 +21,6 @@ struct stats { enum perf_stat_evsel_id { PERF_STAT_EVSEL_ID__NONE = 0, - PERF_STAT_EVSEL_ID__SMI_NUM, - PERF_STAT_EVSEL_ID__APERF, PERF_STAT_EVSEL_ID__MAX, }; @@ -88,8 +86,6 @@ enum stat_type { STAT_LL_CACHE, STAT_ITLB_CACHE, STAT_DTLB_CACHE, - STAT_SMI_NUM, - STAT_APERF, STAT_MAX }; -- cgit v1.2.3-58-ga151 From d74192c7478e7fe90c2897b9237098283573f443 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:42 -0800 Subject: perf stat: Remove perf_stat_evsel_id perf_stat_evsel_id was used for hard coded metrics. These have now migrated to json metrics and so the id values are no longer necessary. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-46-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/stat.c | 31 ------------------------------- tools/perf/util/stat.h | 12 ------------ 2 files changed, 43 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/stat.c b/tools/perf/util/stat.c index d51d7457f12d..8d83d2f4a082 100644 --- a/tools/perf/util/stat.c +++ b/tools/perf/util/stat.c @@ -77,36 +77,6 @@ double rel_stddev_stats(double stddev, double avg) return pct; } -bool __perf_stat_evsel__is(struct evsel *evsel, enum perf_stat_evsel_id id) -{ - struct perf_stat_evsel *ps = evsel->stats; - - return ps->id == id; -} - -#define ID(id, name) [PERF_STAT_EVSEL_ID__##id] = #name -static const char *id_str[PERF_STAT_EVSEL_ID__MAX] = { - ID(NONE, x), -}; -#undef ID - -static void perf_stat_evsel_id_init(struct evsel *evsel) -{ - struct perf_stat_evsel *ps = evsel->stats; - int i; - - /* ps->id is 0 hence PERF_STAT_EVSEL_ID__NONE by default */ - - for (i = 0; i < PERF_STAT_EVSEL_ID__MAX; i++) { - if (!strcmp(evsel__name(evsel), id_str[i]) || - (strstr(evsel__name(evsel), id_str[i]) && evsel->pmu_name - && strstr(evsel__name(evsel), evsel->pmu_name))) { - ps->id = i; - break; - } - } -} - static void evsel__reset_aggr_stats(struct evsel *evsel) { struct perf_stat_evsel *ps = evsel->stats; @@ -166,7 +136,6 @@ static int evsel__alloc_stat_priv(struct evsel *evsel, int nr_aggr) return -ENOMEM; } - perf_stat_evsel_id_init(evsel); evsel__reset_stat_priv(evsel); return 0; } diff --git a/tools/perf/util/stat.h b/tools/perf/util/stat.h index 9af4af3bc3f2..df6068a3f7bb 100644 --- a/tools/perf/util/stat.h +++ b/tools/perf/util/stat.h @@ -19,11 +19,6 @@ struct stats { u64 max, min; }; -enum perf_stat_evsel_id { - PERF_STAT_EVSEL_ID__NONE = 0, - PERF_STAT_EVSEL_ID__MAX, -}; - /* hold aggregated event info */ struct perf_stat_aggr { /* aggregated values */ @@ -40,8 +35,6 @@ struct perf_stat_aggr { struct perf_stat_evsel { /* used for repeated runs */ struct stats res_stats; - /* evsel id for quick check */ - enum perf_stat_evsel_id id; /* number of allocated 'aggr' */ int nr_aggr; /* aggregated event values */ @@ -187,11 +180,6 @@ static inline void update_rusage_stats(struct rusage_stats *ru_stats, struct rus struct evsel; struct evlist; -bool __perf_stat_evsel__is(struct evsel *evsel, enum perf_stat_evsel_id id); - -#define perf_stat_evsel__is(evsel, id) \ - __perf_stat_evsel__is(evsel, PERF_STAT_EVSEL_ID__ ## id) - extern struct runtime_stat rt_stat; extern struct stats walltime_nsecs_stats; extern struct rusage_stats ru_stats; -- cgit v1.2.3-58-ga151 From 758bc8e626b76b53ac643dae4128d6f617e24467 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:43 -0800 Subject: perf stat: Move enums from header The enums are only used in stat-shadow.c, so narrow their scope by moving to the C file. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-47-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/stat-shadow.c | 25 +++++++++++++++++++++++++ tools/perf/util/stat.h | 27 --------------------------- 2 files changed, 25 insertions(+), 27 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/stat-shadow.c b/tools/perf/util/stat-shadow.c index d14fa531ee27..fc948a7e83b7 100644 --- a/tools/perf/util/stat-shadow.c +++ b/tools/perf/util/stat-shadow.c @@ -29,6 +29,31 @@ struct runtime_stat rt_stat; struct stats walltime_nsecs_stats; struct rusage_stats ru_stats; +enum { + CTX_BIT_USER = 1 << 0, + CTX_BIT_KERNEL = 1 << 1, + CTX_BIT_HV = 1 << 2, + CTX_BIT_HOST = 1 << 3, + CTX_BIT_IDLE = 1 << 4, + CTX_BIT_MAX = 1 << 5, +}; + +enum stat_type { + STAT_NONE = 0, + STAT_NSECS, + STAT_CYCLES, + STAT_STALLED_CYCLES_FRONT, + STAT_STALLED_CYCLES_BACK, + STAT_BRANCHES, + STAT_CACHEREFS, + STAT_L1_DCACHE, + STAT_L1_ICACHE, + STAT_LL_CACHE, + STAT_ITLB_CACHE, + STAT_DTLB_CACHE, + STAT_MAX +}; + struct saved_value { struct rb_node rb_node; struct evsel *evsel; diff --git a/tools/perf/util/stat.h b/tools/perf/util/stat.h index df6068a3f7bb..215c0f5c4db7 100644 --- a/tools/perf/util/stat.h +++ b/tools/perf/util/stat.h @@ -55,33 +55,6 @@ enum aggr_mode { AGGR_MAX }; -enum { - CTX_BIT_USER = 1 << 0, - CTX_BIT_KERNEL = 1 << 1, - CTX_BIT_HV = 1 << 2, - CTX_BIT_HOST = 1 << 3, - CTX_BIT_IDLE = 1 << 4, - CTX_BIT_MAX = 1 << 5, -}; - -#define NUM_CTX CTX_BIT_MAX - -enum stat_type { - STAT_NONE = 0, - STAT_NSECS, - STAT_CYCLES, - STAT_STALLED_CYCLES_FRONT, - STAT_STALLED_CYCLES_BACK, - STAT_BRANCHES, - STAT_CACHEREFS, - STAT_L1_DCACHE, - STAT_L1_ICACHE, - STAT_LL_CACHE, - STAT_ITLB_CACHE, - STAT_DTLB_CACHE, - STAT_MAX -}; - struct runtime_stat { struct rblist value_list; }; -- cgit v1.2.3-58-ga151 From cc26ffaa01f04cbe5c958df5532f3c23599e7a04 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:44 -0800 Subject: perf stat: Hide runtime_stat runtime_stat is only shared for the sake of tests that don't care about its value. Move the definition into stat-shadow.c and have the tests also use the global version. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-48-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-script.c | 6 +- tools/perf/builtin-stat.c | 4 +- tools/perf/tests/parse-metric.c | 19 ++--- tools/perf/tests/pmu-events.c | 8 +- tools/perf/util/stat-display.c | 5 +- tools/perf/util/stat-shadow.c | 165 +++++++++++++++++----------------------- tools/perf/util/stat.c | 2 +- tools/perf/util/stat.h | 17 +---- 8 files changed, 90 insertions(+), 136 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index a792214d1af8..e9b5387161df 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -2074,8 +2074,7 @@ static void perf_sample__fprint_metric(struct perf_script *script, val = sample->period * evsel->scale; perf_stat__update_shadow_stats(evsel, val, - sample->cpu, - &rt_stat); + sample->cpu); evsel_script(evsel)->val = val; if (evsel_script(leader)->gnum == leader->core.nr_members) { for_each_group_member (ev2, leader) { @@ -2083,8 +2082,7 @@ static void perf_sample__fprint_metric(struct perf_script *script, evsel_script(ev2)->val, sample->cpu, &ctx, - NULL, - &rt_stat); + NULL); } evsel_script(leader)->gnum = 0; } diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index 9c1fbf154ee3..619387459914 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -434,7 +434,7 @@ static void process_interval(void) clock_gettime(CLOCK_MONOTONIC, &ts); diff_timespec(&rs, &ts, &ref_time); - perf_stat__reset_shadow_per_stat(&rt_stat); + perf_stat__reset_shadow_per_stat(); evlist__reset_aggr_stats(evsel_list); if (read_counters(&rs) == 0) @@ -910,7 +910,7 @@ try_again_reset: evlist__copy_prev_raw_counts(evsel_list); evlist__reset_prev_raw_counts(evsel_list); evlist__reset_aggr_stats(evsel_list); - perf_stat__reset_shadow_per_stat(&rt_stat); + perf_stat__reset_shadow_per_stat(); } else { update_stats(&walltime_nsecs_stats, t1 - t0); update_rusage_stats(&ru_stats, &stat_config.ru_data); diff --git a/tools/perf/tests/parse-metric.c b/tools/perf/tests/parse-metric.c index 132c9b945a42..37e3371d978e 100644 --- a/tools/perf/tests/parse-metric.c +++ b/tools/perf/tests/parse-metric.c @@ -30,8 +30,7 @@ static u64 find_value(const char *name, struct value *values) return 0; } -static void load_runtime_stat(struct runtime_stat *st, struct evlist *evlist, - struct value *vals) +static void load_runtime_stat(struct evlist *evlist, struct value *vals) { struct evsel *evsel; u64 count; @@ -39,14 +38,14 @@ static void load_runtime_stat(struct runtime_stat *st, struct evlist *evlist, perf_stat__reset_shadow_stats(); evlist__for_each_entry(evlist, evsel) { count = find_value(evsel->name, vals); - perf_stat__update_shadow_stats(evsel, count, 0, st); + perf_stat__update_shadow_stats(evsel, count, 0); if (!strcmp(evsel->name, "duration_time")) update_stats(&walltime_nsecs_stats, count); } } static double compute_single(struct rblist *metric_events, struct evlist *evlist, - struct runtime_stat *st, const char *name) + const char *name) { struct metric_expr *mexp; struct metric_event *me; @@ -58,7 +57,7 @@ static double compute_single(struct rblist *metric_events, struct evlist *evlist list_for_each_entry (mexp, &me->head, nd) { if (strcmp(mexp->metric_name, name)) continue; - return test_generic_metric(mexp, 0, st); + return test_generic_metric(mexp, 0); } } } @@ -74,7 +73,6 @@ static int __compute_metric(const char *name, struct value *vals, }; const struct pmu_metrics_table *pme_test; struct perf_cpu_map *cpus; - struct runtime_stat st; struct evlist *evlist; int err; @@ -93,7 +91,6 @@ static int __compute_metric(const char *name, struct value *vals, } perf_evlist__set_maps(&evlist->core, cpus, NULL); - runtime_stat__init(&st); /* Parse the metric into metric_events list. */ pme_test = find_core_metrics_table("testarch", "testcpu"); @@ -107,18 +104,17 @@ static int __compute_metric(const char *name, struct value *vals, goto out; /* Load the runtime stats with given numbers for events. */ - load_runtime_stat(&st, evlist, vals); + load_runtime_stat(evlist, vals); /* And execute the metric */ if (name1 && ratio1) - *ratio1 = compute_single(&metric_events, evlist, &st, name1); + *ratio1 = compute_single(&metric_events, evlist, name1); if (name2 && ratio2) - *ratio2 = compute_single(&metric_events, evlist, &st, name2); + *ratio2 = compute_single(&metric_events, evlist, name2); out: /* ... cleanup. */ metricgroup__rblist_exit(&metric_events); - runtime_stat__exit(&st); evlist__free_stats(evlist); perf_cpu_map__put(cpus); evlist__delete(evlist); @@ -300,6 +296,7 @@ static int test_metric_group(void) static int test__parse_metric(struct test_suite *test __maybe_unused, int subtest __maybe_unused) { + perf_stat__init_shadow_stats(); TEST_ASSERT_VAL("IPC failed", test_ipc() == 0); TEST_ASSERT_VAL("frontend failed", test_frontend() == 0); TEST_ASSERT_VAL("DCache_L2 failed", test_dcache_l2() == 0); diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c index 50b99a0f8f59..122e74c282a7 100644 --- a/tools/perf/tests/pmu-events.c +++ b/tools/perf/tests/pmu-events.c @@ -816,7 +816,6 @@ static int test__parsing_callback(const struct pmu_metric *pm, int k; struct evlist *evlist; struct perf_cpu_map *cpus; - struct runtime_stat st; struct evsel *evsel; struct rblist metric_events = { .nr_entries = 0, @@ -844,7 +843,6 @@ static int test__parsing_callback(const struct pmu_metric *pm, } perf_evlist__set_maps(&evlist->core, cpus, NULL); - runtime_stat__init(&st); err = metricgroup__parse_groups_test(evlist, table, pm->metric_name, &metric_events); if (err) { @@ -867,7 +865,7 @@ static int test__parsing_callback(const struct pmu_metric *pm, k = 1; perf_stat__reset_shadow_stats(); evlist__for_each_entry(evlist, evsel) { - perf_stat__update_shadow_stats(evsel, k, 0, &st); + perf_stat__update_shadow_stats(evsel, k, 0); if (!strcmp(evsel->name, "duration_time")) update_stats(&walltime_nsecs_stats, k); k++; @@ -881,7 +879,7 @@ static int test__parsing_callback(const struct pmu_metric *pm, list_for_each_entry (mexp, &me->head, nd) { if (strcmp(mexp->metric_name, pm->metric_name)) continue; - pr_debug("Result %f\n", test_generic_metric(mexp, 0, &st)); + pr_debug("Result %f\n", test_generic_metric(mexp, 0)); err = 0; (*failures)--; goto out_err; @@ -896,7 +894,6 @@ out_err: /* ... cleanup. */ metricgroup__rblist_exit(&metric_events); - runtime_stat__exit(&st); evlist__free_stats(evlist); perf_cpu_map__put(cpus); evlist__delete(evlist); @@ -908,6 +905,7 @@ static int test__parsing(struct test_suite *test __maybe_unused, { int failures = 0; + perf_stat__init_shadow_stats(); pmu_for_each_core_metric(test__parsing_callback, &failures); pmu_for_each_sys_metric(test__parsing_callback, &failures); diff --git a/tools/perf/util/stat-display.c b/tools/perf/util/stat-display.c index 1b5cb20efd23..6c065d0624c3 100644 --- a/tools/perf/util/stat-display.c +++ b/tools/perf/util/stat-display.c @@ -729,7 +729,7 @@ static void printout(struct perf_stat_config *config, struct outstate *os, if (ok) { perf_stat__print_shadow_stats(config, counter, uval, map_idx, - &out, &config->metric_events, &rt_stat); + &out, &config->metric_events); } else { pm(config, os, /*color=*/NULL, /*format=*/NULL, /*unit=*/"", /*val=*/0); } @@ -1089,8 +1089,7 @@ static void print_metric_headers(struct perf_stat_config *config, perf_stat__print_shadow_stats(config, counter, 0, 0, &out, - &config->metric_events, - &rt_stat); + &config->metric_events); } if (!config->json_output) diff --git a/tools/perf/util/stat-shadow.c b/tools/perf/util/stat-shadow.c index fc948a7e83b7..f80be6abac90 100644 --- a/tools/perf/util/stat-shadow.c +++ b/tools/perf/util/stat-shadow.c @@ -25,10 +25,13 @@ * AGGR_THREAD: Not supported? */ -struct runtime_stat rt_stat; struct stats walltime_nsecs_stats; struct rusage_stats ru_stats; +static struct runtime_stat { + struct rblist value_list; +} rt_stat; + enum { CTX_BIT_USER = 1 << 0, CTX_BIT_KERNEL = 1 << 1, @@ -125,7 +128,6 @@ static struct saved_value *saved_value_lookup(struct evsel *evsel, bool create, enum stat_type type, int ctx, - struct runtime_stat *st, struct cgroup *cgrp) { struct rblist *rblist; @@ -138,7 +140,7 @@ static struct saved_value *saved_value_lookup(struct evsel *evsel, .cgrp = cgrp, }; - rblist = &st->value_list; + rblist = &rt_stat.value_list; /* don't use context info for clock events */ if (type == STAT_NSECS) @@ -156,9 +158,9 @@ static struct saved_value *saved_value_lookup(struct evsel *evsel, return NULL; } -void runtime_stat__init(struct runtime_stat *st) +void perf_stat__init_shadow_stats(void) { - struct rblist *rblist = &st->value_list; + struct rblist *rblist = &rt_stat.value_list; rblist__init(rblist); rblist->node_cmp = saved_value_cmp; @@ -166,16 +168,6 @@ void runtime_stat__init(struct runtime_stat *st) rblist->node_delete = saved_value_delete; } -void runtime_stat__exit(struct runtime_stat *st) -{ - rblist__exit(&st->value_list); -} - -void perf_stat__init_shadow_stats(void) -{ - runtime_stat__init(&rt_stat); -} - static int evsel_context(struct evsel *evsel) { int ctx = 0; @@ -194,12 +186,12 @@ static int evsel_context(struct evsel *evsel) return ctx; } -static void reset_stat(struct runtime_stat *st) +void perf_stat__reset_shadow_per_stat(void) { struct rblist *rblist; struct rb_node *pos, *next; - rblist = &st->value_list; + rblist = &rt_stat.value_list; next = rb_first_cached(&rblist->entries); while (next) { pos = next; @@ -212,28 +204,22 @@ static void reset_stat(struct runtime_stat *st) void perf_stat__reset_shadow_stats(void) { - reset_stat(&rt_stat); + perf_stat__reset_shadow_per_stat(); memset(&walltime_nsecs_stats, 0, sizeof(walltime_nsecs_stats)); memset(&ru_stats, 0, sizeof(ru_stats)); } -void perf_stat__reset_shadow_per_stat(struct runtime_stat *st) -{ - reset_stat(st); -} - struct runtime_stat_data { int ctx; struct cgroup *cgrp; }; -static void update_runtime_stat(struct runtime_stat *st, - enum stat_type type, +static void update_runtime_stat(enum stat_type type, int map_idx, u64 count, struct runtime_stat_data *rsd) { struct saved_value *v = saved_value_lookup(NULL, map_idx, true, type, - rsd->ctx, st, rsd->cgrp); + rsd->ctx, rsd->cgrp); if (v) update_stats(&v->stats, count); @@ -245,7 +231,7 @@ static void update_runtime_stat(struct runtime_stat *st, * instruction rates, etc: */ void perf_stat__update_shadow_stats(struct evsel *counter, u64 count, - int map_idx, struct runtime_stat *st) + int map_idx) { u64 count_ns = count; struct saved_value *v; @@ -253,43 +239,42 @@ void perf_stat__update_shadow_stats(struct evsel *counter, u64 count, .ctx = evsel_context(counter), .cgrp = counter->cgrp, }; - count *= counter->scale; if (evsel__is_clock(counter)) - update_runtime_stat(st, STAT_NSECS, map_idx, count_ns, &rsd); + update_runtime_stat(STAT_NSECS, map_idx, count_ns, &rsd); else if (evsel__match(counter, HARDWARE, HW_CPU_CYCLES)) - update_runtime_stat(st, STAT_CYCLES, map_idx, count, &rsd); + update_runtime_stat(STAT_CYCLES, map_idx, count, &rsd); else if (evsel__match(counter, HARDWARE, HW_STALLED_CYCLES_FRONTEND)) - update_runtime_stat(st, STAT_STALLED_CYCLES_FRONT, + update_runtime_stat(STAT_STALLED_CYCLES_FRONT, map_idx, count, &rsd); else if (evsel__match(counter, HARDWARE, HW_STALLED_CYCLES_BACKEND)) - update_runtime_stat(st, STAT_STALLED_CYCLES_BACK, + update_runtime_stat(STAT_STALLED_CYCLES_BACK, map_idx, count, &rsd); else if (evsel__match(counter, HARDWARE, HW_BRANCH_INSTRUCTIONS)) - update_runtime_stat(st, STAT_BRANCHES, map_idx, count, &rsd); + update_runtime_stat(STAT_BRANCHES, map_idx, count, &rsd); else if (evsel__match(counter, HARDWARE, HW_CACHE_REFERENCES)) - update_runtime_stat(st, STAT_CACHEREFS, map_idx, count, &rsd); + update_runtime_stat(STAT_CACHEREFS, map_idx, count, &rsd); else if (evsel__match(counter, HW_CACHE, HW_CACHE_L1D)) - update_runtime_stat(st, STAT_L1_DCACHE, map_idx, count, &rsd); + update_runtime_stat(STAT_L1_DCACHE, map_idx, count, &rsd); else if (evsel__match(counter, HW_CACHE, HW_CACHE_L1I)) - update_runtime_stat(st, STAT_L1_ICACHE, map_idx, count, &rsd); + update_runtime_stat(STAT_L1_ICACHE, map_idx, count, &rsd); else if (evsel__match(counter, HW_CACHE, HW_CACHE_LL)) - update_runtime_stat(st, STAT_LL_CACHE, map_idx, count, &rsd); + update_runtime_stat(STAT_LL_CACHE, map_idx, count, &rsd); else if (evsel__match(counter, HW_CACHE, HW_CACHE_DTLB)) - update_runtime_stat(st, STAT_DTLB_CACHE, map_idx, count, &rsd); + update_runtime_stat(STAT_DTLB_CACHE, map_idx, count, &rsd); else if (evsel__match(counter, HW_CACHE, HW_CACHE_ITLB)) - update_runtime_stat(st, STAT_ITLB_CACHE, map_idx, count, &rsd); + update_runtime_stat(STAT_ITLB_CACHE, map_idx, count, &rsd); if (counter->collect_stat) { - v = saved_value_lookup(counter, map_idx, true, STAT_NONE, 0, st, + v = saved_value_lookup(counter, map_idx, true, STAT_NONE, 0, rsd.cgrp); update_stats(&v->stats, count); if (counter->metric_leader) v->metric_total += count; } else if (counter->metric_leader && !counter->merged_stat) { v = saved_value_lookup(counter->metric_leader, - map_idx, true, STAT_NONE, 0, st, rsd.cgrp); + map_idx, true, STAT_NONE, 0, rsd.cgrp); v->metric_total += count; v->metric_other++; } @@ -322,26 +307,24 @@ static const char *get_ratio_color(enum grc_type type, double ratio) return color; } -static double runtime_stat_avg(struct runtime_stat *st, - enum stat_type type, int map_idx, +static double runtime_stat_avg(enum stat_type type, int map_idx, struct runtime_stat_data *rsd) { struct saved_value *v; - v = saved_value_lookup(NULL, map_idx, false, type, rsd->ctx, st, rsd->cgrp); + v = saved_value_lookup(NULL, map_idx, false, type, rsd->ctx, rsd->cgrp); if (!v) return 0.0; return avg_stats(&v->stats); } -static double runtime_stat_n(struct runtime_stat *st, - enum stat_type type, int map_idx, +static double runtime_stat_n(enum stat_type type, int map_idx, struct runtime_stat_data *rsd) { struct saved_value *v; - v = saved_value_lookup(NULL, map_idx, false, type, rsd->ctx, st, rsd->cgrp); + v = saved_value_lookup(NULL, map_idx, false, type, rsd->ctx, rsd->cgrp); if (!v) return 0.0; @@ -351,13 +334,12 @@ static double runtime_stat_n(struct runtime_stat *st, static void print_stalled_cycles_frontend(struct perf_stat_config *config, int map_idx, double avg, struct perf_stat_output_ctx *out, - struct runtime_stat *st, struct runtime_stat_data *rsd) { double total, ratio = 0.0; const char *color; - total = runtime_stat_avg(st, STAT_CYCLES, map_idx, rsd); + total = runtime_stat_avg(STAT_CYCLES, map_idx, rsd); if (total) ratio = avg / total * 100.0; @@ -374,13 +356,12 @@ static void print_stalled_cycles_frontend(struct perf_stat_config *config, static void print_stalled_cycles_backend(struct perf_stat_config *config, int map_idx, double avg, struct perf_stat_output_ctx *out, - struct runtime_stat *st, struct runtime_stat_data *rsd) { double total, ratio = 0.0; const char *color; - total = runtime_stat_avg(st, STAT_CYCLES, map_idx, rsd); + total = runtime_stat_avg(STAT_CYCLES, map_idx, rsd); if (total) ratio = avg / total * 100.0; @@ -393,13 +374,12 @@ static void print_stalled_cycles_backend(struct perf_stat_config *config, static void print_branch_misses(struct perf_stat_config *config, int map_idx, double avg, struct perf_stat_output_ctx *out, - struct runtime_stat *st, struct runtime_stat_data *rsd) { double total, ratio = 0.0; const char *color; - total = runtime_stat_avg(st, STAT_BRANCHES, map_idx, rsd); + total = runtime_stat_avg(STAT_BRANCHES, map_idx, rsd); if (total) ratio = avg / total * 100.0; @@ -412,13 +392,12 @@ static void print_branch_misses(struct perf_stat_config *config, static void print_l1_dcache_misses(struct perf_stat_config *config, int map_idx, double avg, struct perf_stat_output_ctx *out, - struct runtime_stat *st, struct runtime_stat_data *rsd) { double total, ratio = 0.0; const char *color; - total = runtime_stat_avg(st, STAT_L1_DCACHE, map_idx, rsd); + total = runtime_stat_avg(STAT_L1_DCACHE, map_idx, rsd); if (total) ratio = avg / total * 100.0; @@ -431,13 +410,12 @@ static void print_l1_dcache_misses(struct perf_stat_config *config, static void print_l1_icache_misses(struct perf_stat_config *config, int map_idx, double avg, struct perf_stat_output_ctx *out, - struct runtime_stat *st, struct runtime_stat_data *rsd) { double total, ratio = 0.0; const char *color; - total = runtime_stat_avg(st, STAT_L1_ICACHE, map_idx, rsd); + total = runtime_stat_avg(STAT_L1_ICACHE, map_idx, rsd); if (total) ratio = avg / total * 100.0; @@ -449,13 +427,12 @@ static void print_l1_icache_misses(struct perf_stat_config *config, static void print_dtlb_cache_misses(struct perf_stat_config *config, int map_idx, double avg, struct perf_stat_output_ctx *out, - struct runtime_stat *st, struct runtime_stat_data *rsd) { double total, ratio = 0.0; const char *color; - total = runtime_stat_avg(st, STAT_DTLB_CACHE, map_idx, rsd); + total = runtime_stat_avg(STAT_DTLB_CACHE, map_idx, rsd); if (total) ratio = avg / total * 100.0; @@ -467,13 +444,12 @@ static void print_dtlb_cache_misses(struct perf_stat_config *config, static void print_itlb_cache_misses(struct perf_stat_config *config, int map_idx, double avg, struct perf_stat_output_ctx *out, - struct runtime_stat *st, struct runtime_stat_data *rsd) { double total, ratio = 0.0; const char *color; - total = runtime_stat_avg(st, STAT_ITLB_CACHE, map_idx, rsd); + total = runtime_stat_avg(STAT_ITLB_CACHE, map_idx, rsd); if (total) ratio = avg / total * 100.0; @@ -485,13 +461,12 @@ static void print_itlb_cache_misses(struct perf_stat_config *config, static void print_ll_cache_misses(struct perf_stat_config *config, int map_idx, double avg, struct perf_stat_output_ctx *out, - struct runtime_stat *st, struct runtime_stat_data *rsd) { double total, ratio = 0.0; const char *color; - total = runtime_stat_avg(st, STAT_LL_CACHE, map_idx, rsd); + total = runtime_stat_avg(STAT_LL_CACHE, map_idx, rsd); if (total) ratio = avg / total * 100.0; @@ -503,8 +478,7 @@ static void print_ll_cache_misses(struct perf_stat_config *config, static int prepare_metric(struct evsel **metric_events, struct metric_ref *metric_refs, struct expr_parse_ctx *pctx, - int map_idx, - struct runtime_stat *st) + int map_idx) { double scale; char *n; @@ -543,7 +517,7 @@ static int prepare_metric(struct evsel **metric_events, } } else { v = saved_value_lookup(metric_events[i], map_idx, false, - STAT_NONE, 0, st, + STAT_NONE, 0, metric_events[i]->cgrp); if (!v) break; @@ -587,8 +561,7 @@ static void generic_metric(struct perf_stat_config *config, const char *metric_unit, int runtime, int map_idx, - struct perf_stat_output_ctx *out, - struct runtime_stat *st) + struct perf_stat_output_ctx *out) { print_metric_t print_metric = out->print_metric; struct expr_parse_ctx *pctx; @@ -605,7 +578,7 @@ static void generic_metric(struct perf_stat_config *config, pctx->sctx.user_requested_cpu_list = strdup(config->user_requested_cpu_list); pctx->sctx.runtime = runtime; pctx->sctx.system_wide = config->system_wide; - i = prepare_metric(metric_events, metric_refs, pctx, map_idx, st); + i = prepare_metric(metric_events, metric_refs, pctx, map_idx); if (i < 0) { expr__ctx_free(pctx); return; @@ -657,7 +630,7 @@ static void generic_metric(struct perf_stat_config *config, expr__ctx_free(pctx); } -double test_generic_metric(struct metric_expr *mexp, int map_idx, struct runtime_stat *st) +double test_generic_metric(struct metric_expr *mexp, int map_idx) { struct expr_parse_ctx *pctx; double ratio = 0.0; @@ -666,7 +639,7 @@ double test_generic_metric(struct metric_expr *mexp, int map_idx, struct runtime if (!pctx) return NAN; - if (prepare_metric(mexp->metric_events, mexp->metric_refs, pctx, map_idx, st) < 0) + if (prepare_metric(mexp->metric_events, mexp->metric_refs, pctx, map_idx) < 0) goto out; if (expr__parse(&ratio, pctx, mexp->metric_expr)) @@ -681,8 +654,7 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, struct evsel *evsel, double avg, int map_idx, struct perf_stat_output_ctx *out, - struct rblist *metric_events, - struct runtime_stat *st) + struct rblist *metric_events) { void *ctxp = out->ctx; print_metric_t print_metric = out->print_metric; @@ -697,7 +669,7 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, if (config->iostat_run) { iostat_print_metric(config, evsel, out); } else if (evsel__match(evsel, HARDWARE, HW_INSTRUCTIONS)) { - total = runtime_stat_avg(st, STAT_CYCLES, map_idx, &rsd); + total = runtime_stat_avg(STAT_CYCLES, map_idx, &rsd); if (total) { ratio = avg / total; @@ -707,10 +679,9 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, print_metric(config, ctxp, NULL, NULL, "insn per cycle", 0); } - total = runtime_stat_avg(st, STAT_STALLED_CYCLES_FRONT, map_idx, &rsd); + total = runtime_stat_avg(STAT_STALLED_CYCLES_FRONT, map_idx, &rsd); - total = max(total, runtime_stat_avg(st, - STAT_STALLED_CYCLES_BACK, + total = max(total, runtime_stat_avg(STAT_STALLED_CYCLES_BACK, map_idx, &rsd)); if (total && avg) { @@ -721,8 +692,8 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, ratio); } } else if (evsel__match(evsel, HARDWARE, HW_BRANCH_MISSES)) { - if (runtime_stat_n(st, STAT_BRANCHES, map_idx, &rsd) != 0) - print_branch_misses(config, map_idx, avg, out, st, &rsd); + if (runtime_stat_n(STAT_BRANCHES, map_idx, &rsd) != 0) + print_branch_misses(config, map_idx, avg, out, &rsd); else print_metric(config, ctxp, NULL, NULL, "of all branches", 0); } else if ( @@ -731,8 +702,8 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) { - if (runtime_stat_n(st, STAT_L1_DCACHE, map_idx, &rsd) != 0) - print_l1_dcache_misses(config, map_idx, avg, out, st, &rsd); + if (runtime_stat_n(STAT_L1_DCACHE, map_idx, &rsd) != 0) + print_l1_dcache_misses(config, map_idx, avg, out, &rsd); else print_metric(config, ctxp, NULL, NULL, "of all L1-dcache accesses", 0); } else if ( @@ -741,8 +712,8 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) { - if (runtime_stat_n(st, STAT_L1_ICACHE, map_idx, &rsd) != 0) - print_l1_icache_misses(config, map_idx, avg, out, st, &rsd); + if (runtime_stat_n(STAT_L1_ICACHE, map_idx, &rsd) != 0) + print_l1_icache_misses(config, map_idx, avg, out, &rsd); else print_metric(config, ctxp, NULL, NULL, "of all L1-icache accesses", 0); } else if ( @@ -751,8 +722,8 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) { - if (runtime_stat_n(st, STAT_DTLB_CACHE, map_idx, &rsd) != 0) - print_dtlb_cache_misses(config, map_idx, avg, out, st, &rsd); + if (runtime_stat_n(STAT_DTLB_CACHE, map_idx, &rsd) != 0) + print_dtlb_cache_misses(config, map_idx, avg, out, &rsd); else print_metric(config, ctxp, NULL, NULL, "of all dTLB cache accesses", 0); } else if ( @@ -761,8 +732,8 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) { - if (runtime_stat_n(st, STAT_ITLB_CACHE, map_idx, &rsd) != 0) - print_itlb_cache_misses(config, map_idx, avg, out, st, &rsd); + if (runtime_stat_n(STAT_ITLB_CACHE, map_idx, &rsd) != 0) + print_itlb_cache_misses(config, map_idx, avg, out, &rsd); else print_metric(config, ctxp, NULL, NULL, "of all iTLB cache accesses", 0); } else if ( @@ -771,27 +742,27 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) { - if (runtime_stat_n(st, STAT_LL_CACHE, map_idx, &rsd) != 0) - print_ll_cache_misses(config, map_idx, avg, out, st, &rsd); + if (runtime_stat_n(STAT_LL_CACHE, map_idx, &rsd) != 0) + print_ll_cache_misses(config, map_idx, avg, out, &rsd); else print_metric(config, ctxp, NULL, NULL, "of all LL-cache accesses", 0); } else if (evsel__match(evsel, HARDWARE, HW_CACHE_MISSES)) { - total = runtime_stat_avg(st, STAT_CACHEREFS, map_idx, &rsd); + total = runtime_stat_avg(STAT_CACHEREFS, map_idx, &rsd); if (total) ratio = avg * 100 / total; - if (runtime_stat_n(st, STAT_CACHEREFS, map_idx, &rsd) != 0) + if (runtime_stat_n(STAT_CACHEREFS, map_idx, &rsd) != 0) print_metric(config, ctxp, NULL, "%8.3f %%", "of all cache refs", ratio); else print_metric(config, ctxp, NULL, NULL, "of all cache refs", 0); } else if (evsel__match(evsel, HARDWARE, HW_STALLED_CYCLES_FRONTEND)) { - print_stalled_cycles_frontend(config, map_idx, avg, out, st, &rsd); + print_stalled_cycles_frontend(config, map_idx, avg, out, &rsd); } else if (evsel__match(evsel, HARDWARE, HW_STALLED_CYCLES_BACKEND)) { - print_stalled_cycles_backend(config, map_idx, avg, out, st, &rsd); + print_stalled_cycles_backend(config, map_idx, avg, out, &rsd); } else if (evsel__match(evsel, HARDWARE, HW_CPU_CYCLES)) { - total = runtime_stat_avg(st, STAT_NSECS, map_idx, &rsd); + total = runtime_stat_avg(STAT_NSECS, map_idx, &rsd); if (total) { ratio = avg / total; @@ -805,11 +776,11 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, avg / (ratio * evsel->scale)); else print_metric(config, ctxp, NULL, NULL, "CPUs utilized", 0); - } else if (runtime_stat_n(st, STAT_NSECS, map_idx, &rsd) != 0) { + } else if (runtime_stat_n(STAT_NSECS, map_idx, &rsd) != 0) { char unit = ' '; char unit_buf[10] = "/sec"; - total = runtime_stat_avg(st, STAT_NSECS, map_idx, &rsd); + total = runtime_stat_avg(STAT_NSECS, map_idx, &rsd); if (total) ratio = convert_unit_double(1000000000.0 * avg / total, &unit); @@ -829,7 +800,7 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, generic_metric(config, mexp->metric_expr, mexp->metric_threshold, mexp->metric_events, mexp->metric_refs, evsel->name, mexp->metric_name, mexp->metric_unit, mexp->runtime, - map_idx, out, st); + map_idx, out); } } if (num == 0) diff --git a/tools/perf/util/stat.c b/tools/perf/util/stat.c index 8d83d2f4a082..0d7538670d67 100644 --- a/tools/perf/util/stat.c +++ b/tools/perf/util/stat.c @@ -659,7 +659,7 @@ static void evsel__update_shadow_stats(struct evsel *evsel) for (i = 0; i < ps->nr_aggr; i++) { struct perf_counts_values *aggr_counts = &ps->aggr[i].counts; - perf_stat__update_shadow_stats(evsel, aggr_counts->val, i, &rt_stat); + perf_stat__update_shadow_stats(evsel, aggr_counts->val, i); } } diff --git a/tools/perf/util/stat.h b/tools/perf/util/stat.h index 215c0f5c4db7..09975e098bd0 100644 --- a/tools/perf/util/stat.h +++ b/tools/perf/util/stat.h @@ -55,10 +55,6 @@ enum aggr_mode { AGGR_MAX }; -struct runtime_stat { - struct rblist value_list; -}; - struct rusage_stats { struct stats ru_utime_usec_stat; struct stats ru_stime_usec_stat; @@ -153,7 +149,6 @@ static inline void update_rusage_stats(struct rusage_stats *ru_stats, struct rus struct evsel; struct evlist; -extern struct runtime_stat rt_stat; extern struct stats walltime_nsecs_stats; extern struct rusage_stats ru_stats; @@ -162,13 +157,10 @@ typedef void (*print_metric_t)(struct perf_stat_config *config, const char *fmt, double val); typedef void (*new_line_t)(struct perf_stat_config *config, void *ctx); -void runtime_stat__init(struct runtime_stat *st); -void runtime_stat__exit(struct runtime_stat *st); void perf_stat__init_shadow_stats(void); void perf_stat__reset_shadow_stats(void); -void perf_stat__reset_shadow_per_stat(struct runtime_stat *st); -void perf_stat__update_shadow_stats(struct evsel *counter, u64 count, - int map_idx, struct runtime_stat *st); +void perf_stat__reset_shadow_per_stat(void); +void perf_stat__update_shadow_stats(struct evsel *counter, u64 count, int map_idx); struct perf_stat_output_ctx { void *ctx; print_metric_t print_metric; @@ -180,8 +172,7 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, struct evsel *evsel, double avg, int map_idx, struct perf_stat_output_ctx *out, - struct rblist *metric_events, - struct runtime_stat *st); + struct rblist *metric_events); int evlist__alloc_stats(struct perf_stat_config *config, struct evlist *evlist, bool alloc_raw); @@ -220,5 +211,5 @@ void evlist__print_counters(struct evlist *evlist, struct perf_stat_config *conf struct target *_target, struct timespec *ts, int argc, const char **argv); struct metric_expr; -double test_generic_metric(struct metric_expr *mexp, int map_idx, struct runtime_stat *st); +double test_generic_metric(struct metric_expr *mexp, int map_idx); #endif -- cgit v1.2.3-58-ga151 From 8945bef30684b5ffb6778de1e979a7fcef6a760b Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:45 -0800 Subject: perf stat: Add cpu_aggr_map for loop Rename variables, add a comment and add a cpu_aggr_map__for_each_idx to aid the readability of the stat-display code. In particular, try to make sure aggr_idx is used consistently to differentiate from other kinds of index. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-49-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/cpumap.h | 3 + tools/perf/util/stat-display.c | 112 +++++++++++++++++++----------------- tools/perf/util/stat-shadow.c | 128 ++++++++++++++++++++--------------------- tools/perf/util/stat.c | 8 +-- tools/perf/util/stat.h | 6 +- 5 files changed, 132 insertions(+), 125 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/cpumap.h b/tools/perf/util/cpumap.h index c2f5824a3a22..e3426541e0aa 100644 --- a/tools/perf/util/cpumap.h +++ b/tools/perf/util/cpumap.h @@ -35,6 +35,9 @@ struct cpu_aggr_map { struct aggr_cpu_id map[]; }; +#define cpu_aggr_map__for_each_idx(idx, aggr_map) \ + for ((idx) = 0; (idx) < aggr_map->nr; (idx)++) + struct perf_record_cpu_map_data; bool perf_record_cpu_map_data__test_bit(int i, const struct perf_record_cpu_map_data *data); diff --git a/tools/perf/util/stat-display.c b/tools/perf/util/stat-display.c index 6c065d0624c3..e6035ecbeee8 100644 --- a/tools/perf/util/stat-display.c +++ b/tools/perf/util/stat-display.c @@ -183,7 +183,7 @@ static void print_cgroup(struct perf_stat_config *config, struct cgroup *cgrp) } static void print_aggr_id_std(struct perf_stat_config *config, - struct evsel *evsel, struct aggr_cpu_id id, int nr) + struct evsel *evsel, struct aggr_cpu_id id, int aggr_nr) { FILE *output = config->output; int idx = config->aggr_mode; @@ -225,11 +225,11 @@ static void print_aggr_id_std(struct perf_stat_config *config, return; } - fprintf(output, "%-*s %*d ", aggr_header_lens[idx], buf, 4, nr); + fprintf(output, "%-*s %*d ", aggr_header_lens[idx], buf, 4, aggr_nr); } static void print_aggr_id_csv(struct perf_stat_config *config, - struct evsel *evsel, struct aggr_cpu_id id, int nr) + struct evsel *evsel, struct aggr_cpu_id id, int aggr_nr) { FILE *output = config->output; const char *sep = config->csv_sep; @@ -237,19 +237,19 @@ static void print_aggr_id_csv(struct perf_stat_config *config, switch (config->aggr_mode) { case AGGR_CORE: fprintf(output, "S%d-D%d-C%d%s%d%s", - id.socket, id.die, id.core, sep, nr, sep); + id.socket, id.die, id.core, sep, aggr_nr, sep); break; case AGGR_DIE: fprintf(output, "S%d-D%d%s%d%s", - id.socket, id.die, sep, nr, sep); + id.socket, id.die, sep, aggr_nr, sep); break; case AGGR_SOCKET: fprintf(output, "S%d%s%d%s", - id.socket, sep, nr, sep); + id.socket, sep, aggr_nr, sep); break; case AGGR_NODE: fprintf(output, "N%d%s%d%s", - id.node, sep, nr, sep); + id.node, sep, aggr_nr, sep); break; case AGGR_NONE: if (evsel->percore && !config->percore_show_thread) { @@ -275,26 +275,26 @@ static void print_aggr_id_csv(struct perf_stat_config *config, } static void print_aggr_id_json(struct perf_stat_config *config, - struct evsel *evsel, struct aggr_cpu_id id, int nr) + struct evsel *evsel, struct aggr_cpu_id id, int aggr_nr) { FILE *output = config->output; switch (config->aggr_mode) { case AGGR_CORE: fprintf(output, "\"core\" : \"S%d-D%d-C%d\", \"aggregate-number\" : %d, ", - id.socket, id.die, id.core, nr); + id.socket, id.die, id.core, aggr_nr); break; case AGGR_DIE: fprintf(output, "\"die\" : \"S%d-D%d\", \"aggregate-number\" : %d, ", - id.socket, id.die, nr); + id.socket, id.die, aggr_nr); break; case AGGR_SOCKET: fprintf(output, "\"socket\" : \"S%d\", \"aggregate-number\" : %d, ", - id.socket, nr); + id.socket, aggr_nr); break; case AGGR_NODE: fprintf(output, "\"node\" : \"N%d\", \"aggregate-number\" : %d, ", - id.node, nr); + id.node, aggr_nr); break; case AGGR_NONE: if (evsel->percore && !config->percore_show_thread) { @@ -319,14 +319,14 @@ static void print_aggr_id_json(struct perf_stat_config *config, } static void aggr_printout(struct perf_stat_config *config, - struct evsel *evsel, struct aggr_cpu_id id, int nr) + struct evsel *evsel, struct aggr_cpu_id id, int aggr_nr) { if (config->json_output) - print_aggr_id_json(config, evsel, id, nr); + print_aggr_id_json(config, evsel, id, aggr_nr); else if (config->csv_output) - print_aggr_id_csv(config, evsel, id, nr); + print_aggr_id_csv(config, evsel, id, aggr_nr); else - print_aggr_id_std(config, evsel, id, nr); + print_aggr_id_std(config, evsel, id, aggr_nr); } struct outstate { @@ -335,7 +335,7 @@ struct outstate { bool first; const char *prefix; int nfields; - int nr; + int aggr_nr; struct aggr_cpu_id id; struct evsel *evsel; struct cgroup *cgrp; @@ -355,7 +355,7 @@ static void do_new_line_std(struct perf_stat_config *config, fputc('\n', os->fh); if (os->prefix) fputs(os->prefix, os->fh); - aggr_printout(config, os->evsel, os->id, os->nr); + aggr_printout(config, os->evsel, os->id, os->aggr_nr); if (config->aggr_mode == AGGR_NONE) fprintf(os->fh, " "); fprintf(os->fh, " "); @@ -396,7 +396,7 @@ static void new_line_csv(struct perf_stat_config *config, void *ctx) fputc('\n', os->fh); if (os->prefix) fprintf(os->fh, "%s", os->prefix); - aggr_printout(config, os->evsel, os->id, os->nr); + aggr_printout(config, os->evsel, os->id, os->aggr_nr); for (i = 0; i < os->nfields; i++) fputs(config->csv_sep, os->fh); } @@ -444,7 +444,7 @@ static void new_line_json(struct perf_stat_config *config, void *ctx) fputs("\n{", os->fh); if (os->prefix) fprintf(os->fh, "%s", os->prefix); - aggr_printout(config, os->evsel, os->id, os->nr); + aggr_printout(config, os->evsel, os->id, os->aggr_nr); } /* Filter out some columns that don't work well in metrics only mode */ @@ -645,10 +645,10 @@ static void print_counter_value(struct perf_stat_config *config, } static void abs_printout(struct perf_stat_config *config, - struct aggr_cpu_id id, int nr, + struct aggr_cpu_id id, int aggr_nr, struct evsel *evsel, double avg, bool ok) { - aggr_printout(config, evsel, id, nr); + aggr_printout(config, evsel, id, aggr_nr); print_counter_value(config, evsel, avg, ok); print_cgroup(config, evsel->cgrp); } @@ -678,7 +678,7 @@ static bool is_mixed_hw_group(struct evsel *counter) } static void printout(struct perf_stat_config *config, struct outstate *os, - double uval, u64 run, u64 ena, double noise, int map_idx) + double uval, u64 run, u64 ena, double noise, int aggr_idx) { struct perf_stat_output_ctx out; print_metric_t pm; @@ -721,14 +721,14 @@ static void printout(struct perf_stat_config *config, struct outstate *os, out.force_header = false; if (!config->metric_only) { - abs_printout(config, os->id, os->nr, counter, uval, ok); + abs_printout(config, os->id, os->aggr_nr, counter, uval, ok); print_noise(config, counter, noise, /*before_metric=*/true); print_running(config, run, ena, /*before_metric=*/true); } if (ok) { - perf_stat__print_shadow_stats(config, counter, uval, map_idx, + perf_stat__print_shadow_stats(config, counter, uval, aggr_idx, &out, &config->metric_events); } else { pm(config, os, /*color=*/NULL, /*format=*/NULL, /*unit=*/"", /*val=*/0); @@ -833,20 +833,20 @@ static bool should_skip_zero_counter(struct perf_stat_config *config, } static void print_counter_aggrdata(struct perf_stat_config *config, - struct evsel *counter, int s, + struct evsel *counter, int aggr_idx, struct outstate *os) { FILE *output = config->output; u64 ena, run, val; double uval; struct perf_stat_evsel *ps = counter->stats; - struct perf_stat_aggr *aggr = &ps->aggr[s]; - struct aggr_cpu_id id = config->aggr_map->map[s]; + struct perf_stat_aggr *aggr = &ps->aggr[aggr_idx]; + struct aggr_cpu_id id = config->aggr_map->map[aggr_idx]; double avg = aggr->counts.val; bool metric_only = config->metric_only; os->id = id; - os->nr = aggr->nr; + os->aggr_nr = aggr->nr; os->evsel = counter; /* Skip already merged uncore/hybrid events */ @@ -874,7 +874,7 @@ static void print_counter_aggrdata(struct perf_stat_config *config, uval = val * counter->scale; - printout(config, os, uval, run, ena, avg, s); + printout(config, os, uval, run, ena, avg, aggr_idx); if (!metric_only) fputc('\n', output); @@ -925,7 +925,7 @@ static void print_aggr(struct perf_stat_config *config, struct outstate *os) { struct evsel *counter; - int s; + int aggr_idx; if (!config->aggr_map || !config->aggr_get_id) return; @@ -934,11 +934,11 @@ static void print_aggr(struct perf_stat_config *config, * With metric_only everything is on a single line. * Without each counter has its own line. */ - for (s = 0; s < config->aggr_map->nr; s++) { - print_metric_begin(config, evlist, os, s); + cpu_aggr_map__for_each_idx(aggr_idx, config->aggr_map) { + print_metric_begin(config, evlist, os, aggr_idx); evlist__for_each_entry(evlist, counter) { - print_counter_aggrdata(config, counter, s, os); + print_counter_aggrdata(config, counter, aggr_idx, os); } print_metric_end(config, os); } @@ -949,7 +949,7 @@ static void print_aggr_cgroup(struct perf_stat_config *config, struct outstate *os) { struct evsel *counter, *evsel; - int s; + int aggr_idx; if (!config->aggr_map || !config->aggr_get_id) return; @@ -960,14 +960,14 @@ static void print_aggr_cgroup(struct perf_stat_config *config, os->cgrp = evsel->cgrp; - for (s = 0; s < config->aggr_map->nr; s++) { - print_metric_begin(config, evlist, os, s); + cpu_aggr_map__for_each_idx(aggr_idx, config->aggr_map) { + print_metric_begin(config, evlist, os, aggr_idx); evlist__for_each_entry(evlist, counter) { if (counter->cgrp != os->cgrp) continue; - print_counter_aggrdata(config, counter, s, os); + print_counter_aggrdata(config, counter, aggr_idx, os); } print_metric_end(config, os); } @@ -977,14 +977,14 @@ static void print_aggr_cgroup(struct perf_stat_config *config, static void print_counter(struct perf_stat_config *config, struct evsel *counter, struct outstate *os) { - int s; + int aggr_idx; /* AGGR_THREAD doesn't have config->aggr_get_id */ if (!config->aggr_map) return; - for (s = 0; s < config->aggr_map->nr; s++) { - print_counter_aggrdata(config, counter, s, os); + cpu_aggr_map__for_each_idx(aggr_idx, config->aggr_map) { + print_counter_aggrdata(config, counter, aggr_idx, os); } } @@ -1003,23 +1003,23 @@ static void print_no_aggr_metric(struct perf_stat_config *config, u64 ena, run, val; double uval; struct perf_stat_evsel *ps = counter->stats; - int counter_idx = perf_cpu_map__idx(evsel__cpus(counter), cpu); + int aggr_idx = perf_cpu_map__idx(evsel__cpus(counter), cpu); - if (counter_idx < 0) + if (aggr_idx < 0) continue; os->evsel = counter; os->id = aggr_cpu_id__cpu(cpu, /*data=*/NULL); if (first) { - print_metric_begin(config, evlist, os, counter_idx); + print_metric_begin(config, evlist, os, aggr_idx); first = false; } - val = ps->aggr[counter_idx].counts.val; - ena = ps->aggr[counter_idx].counts.ena; - run = ps->aggr[counter_idx].counts.run; + val = ps->aggr[aggr_idx].counts.val; + ena = ps->aggr[aggr_idx].counts.ena; + run = ps->aggr[aggr_idx].counts.run; uval = val * counter->scale; - printout(config, os, uval, run, ena, 1.0, counter_idx); + printout(config, os, uval, run, ena, 1.0, aggr_idx); } if (!first) print_metric_end(config, os); @@ -1338,7 +1338,7 @@ static void print_percore(struct perf_stat_config *config, bool metric_only = config->metric_only; FILE *output = config->output; struct cpu_aggr_map *core_map; - int s, c, i; + int aggr_idx, core_map_len = 0; if (!config->aggr_map || !config->aggr_get_id) return; @@ -1346,18 +1346,22 @@ static void print_percore(struct perf_stat_config *config, if (config->percore_show_thread) return print_counter(config, counter, os); + /* + * core_map will hold the aggr_cpu_id for the cores that have been + * printed so that each core is printed just once. + */ core_map = cpu_aggr_map__empty_new(config->aggr_map->nr); if (core_map == NULL) { fprintf(output, "Cannot allocate per-core aggr map for display\n"); return; } - for (s = 0, c = 0; s < config->aggr_map->nr; s++) { - struct perf_cpu curr_cpu = config->aggr_map->map[s].cpu; + cpu_aggr_map__for_each_idx(aggr_idx, config->aggr_map) { + struct perf_cpu curr_cpu = config->aggr_map->map[aggr_idx].cpu; struct aggr_cpu_id core_id = aggr_cpu_id__core(curr_cpu, NULL); bool found = false; - for (i = 0; i < c; i++) { + for (int i = 0; i < core_map_len; i++) { if (aggr_cpu_id__equal(&core_map->map[i], &core_id)) { found = true; break; @@ -1366,9 +1370,9 @@ static void print_percore(struct perf_stat_config *config, if (found) continue; - print_counter_aggrdata(config, counter, s, os); + print_counter_aggrdata(config, counter, aggr_idx, os); - core_map->map[c++] = core_id; + core_map->map[core_map_len++] = core_id; } free(core_map); diff --git a/tools/perf/util/stat-shadow.c b/tools/perf/util/stat-shadow.c index f80be6abac90..7b48e2bd3ba1 100644 --- a/tools/perf/util/stat-shadow.c +++ b/tools/perf/util/stat-shadow.c @@ -231,7 +231,7 @@ static void update_runtime_stat(enum stat_type type, * instruction rates, etc: */ void perf_stat__update_shadow_stats(struct evsel *counter, u64 count, - int map_idx) + int aggr_idx) { u64 count_ns = count; struct saved_value *v; @@ -242,39 +242,39 @@ void perf_stat__update_shadow_stats(struct evsel *counter, u64 count, count *= counter->scale; if (evsel__is_clock(counter)) - update_runtime_stat(STAT_NSECS, map_idx, count_ns, &rsd); + update_runtime_stat(STAT_NSECS, aggr_idx, count_ns, &rsd); else if (evsel__match(counter, HARDWARE, HW_CPU_CYCLES)) - update_runtime_stat(STAT_CYCLES, map_idx, count, &rsd); + update_runtime_stat(STAT_CYCLES, aggr_idx, count, &rsd); else if (evsel__match(counter, HARDWARE, HW_STALLED_CYCLES_FRONTEND)) update_runtime_stat(STAT_STALLED_CYCLES_FRONT, - map_idx, count, &rsd); + aggr_idx, count, &rsd); else if (evsel__match(counter, HARDWARE, HW_STALLED_CYCLES_BACKEND)) update_runtime_stat(STAT_STALLED_CYCLES_BACK, - map_idx, count, &rsd); + aggr_idx, count, &rsd); else if (evsel__match(counter, HARDWARE, HW_BRANCH_INSTRUCTIONS)) - update_runtime_stat(STAT_BRANCHES, map_idx, count, &rsd); + update_runtime_stat(STAT_BRANCHES, aggr_idx, count, &rsd); else if (evsel__match(counter, HARDWARE, HW_CACHE_REFERENCES)) - update_runtime_stat(STAT_CACHEREFS, map_idx, count, &rsd); + update_runtime_stat(STAT_CACHEREFS, aggr_idx, count, &rsd); else if (evsel__match(counter, HW_CACHE, HW_CACHE_L1D)) - update_runtime_stat(STAT_L1_DCACHE, map_idx, count, &rsd); + update_runtime_stat(STAT_L1_DCACHE, aggr_idx, count, &rsd); else if (evsel__match(counter, HW_CACHE, HW_CACHE_L1I)) - update_runtime_stat(STAT_L1_ICACHE, map_idx, count, &rsd); + update_runtime_stat(STAT_L1_ICACHE, aggr_idx, count, &rsd); else if (evsel__match(counter, HW_CACHE, HW_CACHE_LL)) - update_runtime_stat(STAT_LL_CACHE, map_idx, count, &rsd); + update_runtime_stat(STAT_LL_CACHE, aggr_idx, count, &rsd); else if (evsel__match(counter, HW_CACHE, HW_CACHE_DTLB)) - update_runtime_stat(STAT_DTLB_CACHE, map_idx, count, &rsd); + update_runtime_stat(STAT_DTLB_CACHE, aggr_idx, count, &rsd); else if (evsel__match(counter, HW_CACHE, HW_CACHE_ITLB)) - update_runtime_stat(STAT_ITLB_CACHE, map_idx, count, &rsd); + update_runtime_stat(STAT_ITLB_CACHE, aggr_idx, count, &rsd); if (counter->collect_stat) { - v = saved_value_lookup(counter, map_idx, true, STAT_NONE, 0, + v = saved_value_lookup(counter, aggr_idx, true, STAT_NONE, 0, rsd.cgrp); update_stats(&v->stats, count); if (counter->metric_leader) v->metric_total += count; } else if (counter->metric_leader && !counter->merged_stat) { v = saved_value_lookup(counter->metric_leader, - map_idx, true, STAT_NONE, 0, rsd.cgrp); + aggr_idx, true, STAT_NONE, 0, rsd.cgrp); v->metric_total += count; v->metric_other++; } @@ -307,24 +307,24 @@ static const char *get_ratio_color(enum grc_type type, double ratio) return color; } -static double runtime_stat_avg(enum stat_type type, int map_idx, +static double runtime_stat_avg(enum stat_type type, int aggr_idx, struct runtime_stat_data *rsd) { struct saved_value *v; - v = saved_value_lookup(NULL, map_idx, false, type, rsd->ctx, rsd->cgrp); + v = saved_value_lookup(NULL, aggr_idx, false, type, rsd->ctx, rsd->cgrp); if (!v) return 0.0; return avg_stats(&v->stats); } -static double runtime_stat_n(enum stat_type type, int map_idx, +static double runtime_stat_n(enum stat_type type, int aggr_idx, struct runtime_stat_data *rsd) { struct saved_value *v; - v = saved_value_lookup(NULL, map_idx, false, type, rsd->ctx, rsd->cgrp); + v = saved_value_lookup(NULL, aggr_idx, false, type, rsd->ctx, rsd->cgrp); if (!v) return 0.0; @@ -332,14 +332,14 @@ static double runtime_stat_n(enum stat_type type, int map_idx, } static void print_stalled_cycles_frontend(struct perf_stat_config *config, - int map_idx, double avg, + int aggr_idx, double avg, struct perf_stat_output_ctx *out, struct runtime_stat_data *rsd) { double total, ratio = 0.0; const char *color; - total = runtime_stat_avg(STAT_CYCLES, map_idx, rsd); + total = runtime_stat_avg(STAT_CYCLES, aggr_idx, rsd); if (total) ratio = avg / total * 100.0; @@ -354,14 +354,14 @@ static void print_stalled_cycles_frontend(struct perf_stat_config *config, } static void print_stalled_cycles_backend(struct perf_stat_config *config, - int map_idx, double avg, + int aggr_idx, double avg, struct perf_stat_output_ctx *out, struct runtime_stat_data *rsd) { double total, ratio = 0.0; const char *color; - total = runtime_stat_avg(STAT_CYCLES, map_idx, rsd); + total = runtime_stat_avg(STAT_CYCLES, aggr_idx, rsd); if (total) ratio = avg / total * 100.0; @@ -372,14 +372,14 @@ static void print_stalled_cycles_backend(struct perf_stat_config *config, } static void print_branch_misses(struct perf_stat_config *config, - int map_idx, double avg, + int aggr_idx, double avg, struct perf_stat_output_ctx *out, struct runtime_stat_data *rsd) { double total, ratio = 0.0; const char *color; - total = runtime_stat_avg(STAT_BRANCHES, map_idx, rsd); + total = runtime_stat_avg(STAT_BRANCHES, aggr_idx, rsd); if (total) ratio = avg / total * 100.0; @@ -390,14 +390,14 @@ static void print_branch_misses(struct perf_stat_config *config, } static void print_l1_dcache_misses(struct perf_stat_config *config, - int map_idx, double avg, + int aggr_idx, double avg, struct perf_stat_output_ctx *out, struct runtime_stat_data *rsd) { double total, ratio = 0.0; const char *color; - total = runtime_stat_avg(STAT_L1_DCACHE, map_idx, rsd); + total = runtime_stat_avg(STAT_L1_DCACHE, aggr_idx, rsd); if (total) ratio = avg / total * 100.0; @@ -408,14 +408,14 @@ static void print_l1_dcache_misses(struct perf_stat_config *config, } static void print_l1_icache_misses(struct perf_stat_config *config, - int map_idx, double avg, + int aggr_idx, double avg, struct perf_stat_output_ctx *out, struct runtime_stat_data *rsd) { double total, ratio = 0.0; const char *color; - total = runtime_stat_avg(STAT_L1_ICACHE, map_idx, rsd); + total = runtime_stat_avg(STAT_L1_ICACHE, aggr_idx, rsd); if (total) ratio = avg / total * 100.0; @@ -425,14 +425,14 @@ static void print_l1_icache_misses(struct perf_stat_config *config, } static void print_dtlb_cache_misses(struct perf_stat_config *config, - int map_idx, double avg, + int aggr_idx, double avg, struct perf_stat_output_ctx *out, struct runtime_stat_data *rsd) { double total, ratio = 0.0; const char *color; - total = runtime_stat_avg(STAT_DTLB_CACHE, map_idx, rsd); + total = runtime_stat_avg(STAT_DTLB_CACHE, aggr_idx, rsd); if (total) ratio = avg / total * 100.0; @@ -442,14 +442,14 @@ static void print_dtlb_cache_misses(struct perf_stat_config *config, } static void print_itlb_cache_misses(struct perf_stat_config *config, - int map_idx, double avg, + int aggr_idx, double avg, struct perf_stat_output_ctx *out, struct runtime_stat_data *rsd) { double total, ratio = 0.0; const char *color; - total = runtime_stat_avg(STAT_ITLB_CACHE, map_idx, rsd); + total = runtime_stat_avg(STAT_ITLB_CACHE, aggr_idx, rsd); if (total) ratio = avg / total * 100.0; @@ -459,14 +459,14 @@ static void print_itlb_cache_misses(struct perf_stat_config *config, } static void print_ll_cache_misses(struct perf_stat_config *config, - int map_idx, double avg, + int aggr_idx, double avg, struct perf_stat_output_ctx *out, struct runtime_stat_data *rsd) { double total, ratio = 0.0; const char *color; - total = runtime_stat_avg(STAT_LL_CACHE, map_idx, rsd); + total = runtime_stat_avg(STAT_LL_CACHE, aggr_idx, rsd); if (total) ratio = avg / total * 100.0; @@ -478,7 +478,7 @@ static void print_ll_cache_misses(struct perf_stat_config *config, static int prepare_metric(struct evsel **metric_events, struct metric_ref *metric_refs, struct expr_parse_ctx *pctx, - int map_idx) + int aggr_idx) { double scale; char *n; @@ -516,7 +516,7 @@ static int prepare_metric(struct evsel **metric_events, abort(); } } else { - v = saved_value_lookup(metric_events[i], map_idx, false, + v = saved_value_lookup(metric_events[i], aggr_idx, false, STAT_NONE, 0, metric_events[i]->cgrp); if (!v) @@ -560,7 +560,7 @@ static void generic_metric(struct perf_stat_config *config, const char *metric_name, const char *metric_unit, int runtime, - int map_idx, + int aggr_idx, struct perf_stat_output_ctx *out) { print_metric_t print_metric = out->print_metric; @@ -578,7 +578,7 @@ static void generic_metric(struct perf_stat_config *config, pctx->sctx.user_requested_cpu_list = strdup(config->user_requested_cpu_list); pctx->sctx.runtime = runtime; pctx->sctx.system_wide = config->system_wide; - i = prepare_metric(metric_events, metric_refs, pctx, map_idx); + i = prepare_metric(metric_events, metric_refs, pctx, aggr_idx); if (i < 0) { expr__ctx_free(pctx); return; @@ -630,7 +630,7 @@ static void generic_metric(struct perf_stat_config *config, expr__ctx_free(pctx); } -double test_generic_metric(struct metric_expr *mexp, int map_idx) +double test_generic_metric(struct metric_expr *mexp, int aggr_idx) { struct expr_parse_ctx *pctx; double ratio = 0.0; @@ -639,7 +639,7 @@ double test_generic_metric(struct metric_expr *mexp, int map_idx) if (!pctx) return NAN; - if (prepare_metric(mexp->metric_events, mexp->metric_refs, pctx, map_idx) < 0) + if (prepare_metric(mexp->metric_events, mexp->metric_refs, pctx, aggr_idx) < 0) goto out; if (expr__parse(&ratio, pctx, mexp->metric_expr)) @@ -652,7 +652,7 @@ out: void perf_stat__print_shadow_stats(struct perf_stat_config *config, struct evsel *evsel, - double avg, int map_idx, + double avg, int aggr_idx, struct perf_stat_output_ctx *out, struct rblist *metric_events) { @@ -669,7 +669,7 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, if (config->iostat_run) { iostat_print_metric(config, evsel, out); } else if (evsel__match(evsel, HARDWARE, HW_INSTRUCTIONS)) { - total = runtime_stat_avg(STAT_CYCLES, map_idx, &rsd); + total = runtime_stat_avg(STAT_CYCLES, aggr_idx, &rsd); if (total) { ratio = avg / total; @@ -679,10 +679,10 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, print_metric(config, ctxp, NULL, NULL, "insn per cycle", 0); } - total = runtime_stat_avg(STAT_STALLED_CYCLES_FRONT, map_idx, &rsd); + total = runtime_stat_avg(STAT_STALLED_CYCLES_FRONT, aggr_idx, &rsd); total = max(total, runtime_stat_avg(STAT_STALLED_CYCLES_BACK, - map_idx, &rsd)); + aggr_idx, &rsd)); if (total && avg) { out->new_line(config, ctxp); @@ -692,8 +692,8 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, ratio); } } else if (evsel__match(evsel, HARDWARE, HW_BRANCH_MISSES)) { - if (runtime_stat_n(STAT_BRANCHES, map_idx, &rsd) != 0) - print_branch_misses(config, map_idx, avg, out, &rsd); + if (runtime_stat_n(STAT_BRANCHES, aggr_idx, &rsd) != 0) + print_branch_misses(config, aggr_idx, avg, out, &rsd); else print_metric(config, ctxp, NULL, NULL, "of all branches", 0); } else if ( @@ -702,8 +702,8 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) { - if (runtime_stat_n(STAT_L1_DCACHE, map_idx, &rsd) != 0) - print_l1_dcache_misses(config, map_idx, avg, out, &rsd); + if (runtime_stat_n(STAT_L1_DCACHE, aggr_idx, &rsd) != 0) + print_l1_dcache_misses(config, aggr_idx, avg, out, &rsd); else print_metric(config, ctxp, NULL, NULL, "of all L1-dcache accesses", 0); } else if ( @@ -712,8 +712,8 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) { - if (runtime_stat_n(STAT_L1_ICACHE, map_idx, &rsd) != 0) - print_l1_icache_misses(config, map_idx, avg, out, &rsd); + if (runtime_stat_n(STAT_L1_ICACHE, aggr_idx, &rsd) != 0) + print_l1_icache_misses(config, aggr_idx, avg, out, &rsd); else print_metric(config, ctxp, NULL, NULL, "of all L1-icache accesses", 0); } else if ( @@ -722,8 +722,8 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) { - if (runtime_stat_n(STAT_DTLB_CACHE, map_idx, &rsd) != 0) - print_dtlb_cache_misses(config, map_idx, avg, out, &rsd); + if (runtime_stat_n(STAT_DTLB_CACHE, aggr_idx, &rsd) != 0) + print_dtlb_cache_misses(config, aggr_idx, avg, out, &rsd); else print_metric(config, ctxp, NULL, NULL, "of all dTLB cache accesses", 0); } else if ( @@ -732,8 +732,8 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) { - if (runtime_stat_n(STAT_ITLB_CACHE, map_idx, &rsd) != 0) - print_itlb_cache_misses(config, map_idx, avg, out, &rsd); + if (runtime_stat_n(STAT_ITLB_CACHE, aggr_idx, &rsd) != 0) + print_itlb_cache_misses(config, aggr_idx, avg, out, &rsd); else print_metric(config, ctxp, NULL, NULL, "of all iTLB cache accesses", 0); } else if ( @@ -742,27 +742,27 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) { - if (runtime_stat_n(STAT_LL_CACHE, map_idx, &rsd) != 0) - print_ll_cache_misses(config, map_idx, avg, out, &rsd); + if (runtime_stat_n(STAT_LL_CACHE, aggr_idx, &rsd) != 0) + print_ll_cache_misses(config, aggr_idx, avg, out, &rsd); else print_metric(config, ctxp, NULL, NULL, "of all LL-cache accesses", 0); } else if (evsel__match(evsel, HARDWARE, HW_CACHE_MISSES)) { - total = runtime_stat_avg(STAT_CACHEREFS, map_idx, &rsd); + total = runtime_stat_avg(STAT_CACHEREFS, aggr_idx, &rsd); if (total) ratio = avg * 100 / total; - if (runtime_stat_n(STAT_CACHEREFS, map_idx, &rsd) != 0) + if (runtime_stat_n(STAT_CACHEREFS, aggr_idx, &rsd) != 0) print_metric(config, ctxp, NULL, "%8.3f %%", "of all cache refs", ratio); else print_metric(config, ctxp, NULL, NULL, "of all cache refs", 0); } else if (evsel__match(evsel, HARDWARE, HW_STALLED_CYCLES_FRONTEND)) { - print_stalled_cycles_frontend(config, map_idx, avg, out, &rsd); + print_stalled_cycles_frontend(config, aggr_idx, avg, out, &rsd); } else if (evsel__match(evsel, HARDWARE, HW_STALLED_CYCLES_BACKEND)) { - print_stalled_cycles_backend(config, map_idx, avg, out, &rsd); + print_stalled_cycles_backend(config, aggr_idx, avg, out, &rsd); } else if (evsel__match(evsel, HARDWARE, HW_CPU_CYCLES)) { - total = runtime_stat_avg(STAT_NSECS, map_idx, &rsd); + total = runtime_stat_avg(STAT_NSECS, aggr_idx, &rsd); if (total) { ratio = avg / total; @@ -776,11 +776,11 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, avg / (ratio * evsel->scale)); else print_metric(config, ctxp, NULL, NULL, "CPUs utilized", 0); - } else if (runtime_stat_n(STAT_NSECS, map_idx, &rsd) != 0) { + } else if (runtime_stat_n(STAT_NSECS, aggr_idx, &rsd) != 0) { char unit = ' '; char unit_buf[10] = "/sec"; - total = runtime_stat_avg(STAT_NSECS, map_idx, &rsd); + total = runtime_stat_avg(STAT_NSECS, aggr_idx, &rsd); if (total) ratio = convert_unit_double(1000000000.0 * avg / total, &unit); @@ -800,7 +800,7 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, generic_metric(config, mexp->metric_expr, mexp->metric_threshold, mexp->metric_events, mexp->metric_refs, evsel->name, mexp->metric_name, mexp->metric_unit, mexp->runtime, - map_idx, out); + aggr_idx, out); } } if (num == 0) diff --git a/tools/perf/util/stat.c b/tools/perf/util/stat.c index 0d7538670d67..83dc4c1f4b12 100644 --- a/tools/perf/util/stat.c +++ b/tools/perf/util/stat.c @@ -651,15 +651,15 @@ void perf_stat_process_percore(struct perf_stat_config *config, struct evlist *e static void evsel__update_shadow_stats(struct evsel *evsel) { struct perf_stat_evsel *ps = evsel->stats; - int i; + int aggr_idx; if (ps->aggr == NULL) return; - for (i = 0; i < ps->nr_aggr; i++) { - struct perf_counts_values *aggr_counts = &ps->aggr[i].counts; + for (aggr_idx = 0; aggr_idx < ps->nr_aggr; aggr_idx++) { + struct perf_counts_values *aggr_counts = &ps->aggr[aggr_idx].counts; - perf_stat__update_shadow_stats(evsel, aggr_counts->val, i); + perf_stat__update_shadow_stats(evsel, aggr_counts->val, aggr_idx); } } diff --git a/tools/perf/util/stat.h b/tools/perf/util/stat.h index 09975e098bd0..b01c828c3799 100644 --- a/tools/perf/util/stat.h +++ b/tools/perf/util/stat.h @@ -160,7 +160,7 @@ typedef void (*new_line_t)(struct perf_stat_config *config, void *ctx); void perf_stat__init_shadow_stats(void); void perf_stat__reset_shadow_stats(void); void perf_stat__reset_shadow_per_stat(void); -void perf_stat__update_shadow_stats(struct evsel *counter, u64 count, int map_idx); +void perf_stat__update_shadow_stats(struct evsel *counter, u64 count, int aggr_idx); struct perf_stat_output_ctx { void *ctx; print_metric_t print_metric; @@ -170,7 +170,7 @@ struct perf_stat_output_ctx { void perf_stat__print_shadow_stats(struct perf_stat_config *config, struct evsel *evsel, - double avg, int map_idx, + double avg, int aggr_idx, struct perf_stat_output_ctx *out, struct rblist *metric_events); @@ -211,5 +211,5 @@ void evlist__print_counters(struct evlist *evlist, struct perf_stat_config *conf struct target *_target, struct timespec *ts, int argc, const char **argv); struct metric_expr; -double test_generic_metric(struct metric_expr *mexp, int map_idx); +double test_generic_metric(struct metric_expr *mexp, int aggr_idx); #endif -- cgit v1.2.3-58-ga151 From 37cc8ad77cf81f3ffd226856c367b0e15333a738 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:46 -0800 Subject: perf metric: Directly use counts rather than saved_value Bugs with double aggregation have been introduced because of aggregation of counters and again with saved_value. Remove the generic metric use-case. Update parse-metric and pmu-events tests to update aggregate rather than saved_value counts. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-50-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/parse-metric.c | 4 +-- tools/perf/tests/pmu-events.c | 4 +-- tools/perf/util/stat-shadow.c | 56 ++++++++++++++--------------------------- 3 files changed, 23 insertions(+), 41 deletions(-) (limited to 'tools') diff --git a/tools/perf/tests/parse-metric.c b/tools/perf/tests/parse-metric.c index 37e3371d978e..b9b8a48289c4 100644 --- a/tools/perf/tests/parse-metric.c +++ b/tools/perf/tests/parse-metric.c @@ -35,10 +35,10 @@ static void load_runtime_stat(struct evlist *evlist, struct value *vals) struct evsel *evsel; u64 count; - perf_stat__reset_shadow_stats(); + evlist__alloc_aggr_stats(evlist, 1); evlist__for_each_entry(evlist, evsel) { count = find_value(evsel->name, vals); - perf_stat__update_shadow_stats(evsel, count, 0); + evsel->stats->aggr->counts.val = count; if (!strcmp(evsel->name, "duration_time")) update_stats(&walltime_nsecs_stats, count); } diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c index 122e74c282a7..4ec2a4ca1a82 100644 --- a/tools/perf/tests/pmu-events.c +++ b/tools/perf/tests/pmu-events.c @@ -863,9 +863,9 @@ static int test__parsing_callback(const struct pmu_metric *pm, * zero when subtracted and so try to make them unique. */ k = 1; - perf_stat__reset_shadow_stats(); + evlist__alloc_aggr_stats(evlist, 1); evlist__for_each_entry(evlist, evsel) { - perf_stat__update_shadow_stats(evsel, k, 0); + evsel->stats->aggr->counts.val = k; if (!strcmp(evsel->name, "duration_time")) update_stats(&walltime_nsecs_stats, k); k++; diff --git a/tools/perf/util/stat-shadow.c b/tools/perf/util/stat-shadow.c index 7b48e2bd3ba1..eba98520cea2 100644 --- a/tools/perf/util/stat-shadow.c +++ b/tools/perf/util/stat-shadow.c @@ -234,7 +234,6 @@ void perf_stat__update_shadow_stats(struct evsel *counter, u64 count, int aggr_idx) { u64 count_ns = count; - struct saved_value *v; struct runtime_stat_data rsd = { .ctx = evsel_context(counter), .cgrp = counter->cgrp, @@ -265,19 +264,6 @@ void perf_stat__update_shadow_stats(struct evsel *counter, u64 count, update_runtime_stat(STAT_DTLB_CACHE, aggr_idx, count, &rsd); else if (evsel__match(counter, HW_CACHE, HW_CACHE_ITLB)) update_runtime_stat(STAT_ITLB_CACHE, aggr_idx, count, &rsd); - - if (counter->collect_stat) { - v = saved_value_lookup(counter, aggr_idx, true, STAT_NONE, 0, - rsd.cgrp); - update_stats(&v->stats, count); - if (counter->metric_leader) - v->metric_total += count; - } else if (counter->metric_leader && !counter->merged_stat) { - v = saved_value_lookup(counter->metric_leader, - aggr_idx, true, STAT_NONE, 0, rsd.cgrp); - v->metric_total += count; - v->metric_other++; - } } /* used for get_ratio_color() */ @@ -480,18 +466,17 @@ static int prepare_metric(struct evsel **metric_events, struct expr_parse_ctx *pctx, int aggr_idx) { - double scale; - char *n; - int i, j, ret; + int i; for (i = 0; metric_events[i]; i++) { - struct saved_value *v; - struct stats *stats; - u64 metric_total = 0; - int source_count; + char *n; + double val; + int source_count = 0; if (evsel__is_tool(metric_events[i])) { - source_count = 1; + struct stats *stats; + double scale; + switch (metric_events[i]->tool_event) { case PERF_TOOL_DURATION_TIME: stats = &walltime_nsecs_stats; @@ -515,35 +500,32 @@ static int prepare_metric(struct evsel **metric_events, pr_err("Unknown tool event '%s'", evsel__name(metric_events[i])); abort(); } + val = avg_stats(stats) * scale; + source_count = 1; } else { - v = saved_value_lookup(metric_events[i], aggr_idx, false, - STAT_NONE, 0, - metric_events[i]->cgrp); - if (!v) + struct perf_stat_evsel *ps = metric_events[i]->stats; + struct perf_stat_aggr *aggr = &ps->aggr[aggr_idx]; + + if (!aggr) break; - stats = &v->stats; + /* * If an event was scaled during stat gathering, reverse * the scale before computing the metric. */ - scale = 1.0 / metric_events[i]->scale; - + val = aggr->counts.val * (1.0 / metric_events[i]->scale); source_count = evsel__source_count(metric_events[i]); - - if (v->metric_other) - metric_total = v->metric_total * scale; } n = strdup(evsel__metric_id(metric_events[i])); if (!n) return -ENOMEM; - expr__add_id_val_source_count(pctx, n, - metric_total ? : avg_stats(stats) * scale, - source_count); + expr__add_id_val_source_count(pctx, n, val, source_count); } - for (j = 0; metric_refs && metric_refs[j].metric_name; j++) { - ret = expr__add_ref(pctx, &metric_refs[j]); + for (int j = 0; metric_refs && metric_refs[j].metric_name; j++) { + int ret = expr__add_ref(pctx, &metric_refs[j]); + if (ret) return ret; } -- cgit v1.2.3-58-ga151 From 0a57b910807ad16381d39578ffc51a7055e4dfd6 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:47 -0800 Subject: perf stat: Use counts rather than saved_value Switch the hard coded metrics to use the aggregate value rather than from saved_value. When computing a metric like IPC the aggregate count comes from instructions then cycles is looked up and if present IPC computed. Rather than lookup from the saved_value rbtree, search the counter's evlist for the desired counter. A new helper evsel__stat_type is used to both quickly find a metric function and to identify when a counter is the one being sought. So that both total and miss counts can be sought, the stat_type enum is expanded. The ratio functions are rewritten to share a common helper with the ratios being directly passed rather than computed from an enum value. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-51-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/evsel.h | 2 +- tools/perf/util/stat-shadow.c | 534 +++++++++++++++++++++--------------------- 2 files changed, 270 insertions(+), 266 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h index 24cb807ef6ce..814a49ebb7e3 100644 --- a/tools/perf/util/evsel.h +++ b/tools/perf/util/evsel.h @@ -436,7 +436,7 @@ static inline bool evsel__is_bpf_output(struct evsel *evsel) return evsel__match(evsel, SOFTWARE, SW_BPF_OUTPUT); } -static inline bool evsel__is_clock(struct evsel *evsel) +static inline bool evsel__is_clock(const struct evsel *evsel) { return evsel__match(evsel, SOFTWARE, SW_CPU_CLOCK) || evsel__match(evsel, SOFTWARE, SW_TASK_CLOCK); diff --git a/tools/perf/util/stat-shadow.c b/tools/perf/util/stat-shadow.c index eba98520cea2..9d22cde09dc9 100644 --- a/tools/perf/util/stat-shadow.c +++ b/tools/perf/util/stat-shadow.c @@ -45,15 +45,23 @@ enum stat_type { STAT_NONE = 0, STAT_NSECS, STAT_CYCLES, + STAT_INSTRUCTIONS, STAT_STALLED_CYCLES_FRONT, STAT_STALLED_CYCLES_BACK, STAT_BRANCHES, - STAT_CACHEREFS, + STAT_BRANCH_MISS, + STAT_CACHE_REFS, + STAT_CACHE_MISSES, STAT_L1_DCACHE, STAT_L1_ICACHE, STAT_LL_CACHE, STAT_ITLB_CACHE, STAT_DTLB_CACHE, + STAT_L1D_MISS, + STAT_L1I_MISS, + STAT_LL_MISS, + STAT_DTLB_MISS, + STAT_ITLB_MISS, STAT_MAX }; @@ -168,7 +176,7 @@ void perf_stat__init_shadow_stats(void) rblist->node_delete = saved_value_delete; } -static int evsel_context(struct evsel *evsel) +static int evsel_context(const struct evsel *evsel) { int ctx = 0; @@ -253,7 +261,7 @@ void perf_stat__update_shadow_stats(struct evsel *counter, u64 count, else if (evsel__match(counter, HARDWARE, HW_BRANCH_INSTRUCTIONS)) update_runtime_stat(STAT_BRANCHES, aggr_idx, count, &rsd); else if (evsel__match(counter, HARDWARE, HW_CACHE_REFERENCES)) - update_runtime_stat(STAT_CACHEREFS, aggr_idx, count, &rsd); + update_runtime_stat(STAT_CACHE_REFS, aggr_idx, count, &rsd); else if (evsel__match(counter, HW_CACHE, HW_CACHE_L1D)) update_runtime_stat(STAT_L1_DCACHE, aggr_idx, count, &rsd); else if (evsel__match(counter, HW_CACHE, HW_CACHE_L1I)) @@ -266,199 +274,283 @@ void perf_stat__update_shadow_stats(struct evsel *counter, u64 count, update_runtime_stat(STAT_ITLB_CACHE, aggr_idx, count, &rsd); } -/* used for get_ratio_color() */ -enum grc_type { - GRC_STALLED_CYCLES_FE, - GRC_STALLED_CYCLES_BE, - GRC_CACHE_MISSES, - GRC_MAX_NR -}; +static enum stat_type evsel__stat_type(const struct evsel *evsel) +{ + /* Fake perf_hw_cache_op_id values for use with evsel__match. */ + u64 PERF_COUNT_hw_cache_l1d_miss = PERF_COUNT_HW_CACHE_L1D | + ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | + ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16); + u64 PERF_COUNT_hw_cache_l1i_miss = PERF_COUNT_HW_CACHE_L1I | + ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | + ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16); + u64 PERF_COUNT_hw_cache_ll_miss = PERF_COUNT_HW_CACHE_LL | + ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | + ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16); + u64 PERF_COUNT_hw_cache_dtlb_miss = PERF_COUNT_HW_CACHE_DTLB | + ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | + ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16); + u64 PERF_COUNT_hw_cache_itlb_miss = PERF_COUNT_HW_CACHE_ITLB | + ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | + ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16); + + if (evsel__is_clock(evsel)) + return STAT_NSECS; + else if (evsel__match(evsel, HARDWARE, HW_CPU_CYCLES)) + return STAT_CYCLES; + else if (evsel__match(evsel, HARDWARE, HW_INSTRUCTIONS)) + return STAT_INSTRUCTIONS; + else if (evsel__match(evsel, HARDWARE, HW_STALLED_CYCLES_FRONTEND)) + return STAT_STALLED_CYCLES_FRONT; + else if (evsel__match(evsel, HARDWARE, HW_STALLED_CYCLES_BACKEND)) + return STAT_STALLED_CYCLES_BACK; + else if (evsel__match(evsel, HARDWARE, HW_BRANCH_INSTRUCTIONS)) + return STAT_BRANCHES; + else if (evsel__match(evsel, HARDWARE, HW_BRANCH_MISSES)) + return STAT_BRANCH_MISS; + else if (evsel__match(evsel, HARDWARE, HW_CACHE_REFERENCES)) + return STAT_CACHE_REFS; + else if (evsel__match(evsel, HARDWARE, HW_CACHE_MISSES)) + return STAT_CACHE_MISSES; + else if (evsel__match(evsel, HW_CACHE, HW_CACHE_L1D)) + return STAT_L1_DCACHE; + else if (evsel__match(evsel, HW_CACHE, HW_CACHE_L1I)) + return STAT_L1_ICACHE; + else if (evsel__match(evsel, HW_CACHE, HW_CACHE_LL)) + return STAT_LL_CACHE; + else if (evsel__match(evsel, HW_CACHE, HW_CACHE_DTLB)) + return STAT_DTLB_CACHE; + else if (evsel__match(evsel, HW_CACHE, HW_CACHE_ITLB)) + return STAT_ITLB_CACHE; + else if (evsel__match(evsel, HW_CACHE, hw_cache_l1d_miss)) + return STAT_L1D_MISS; + else if (evsel__match(evsel, HW_CACHE, hw_cache_l1i_miss)) + return STAT_L1I_MISS; + else if (evsel__match(evsel, HW_CACHE, hw_cache_ll_miss)) + return STAT_LL_MISS; + else if (evsel__match(evsel, HW_CACHE, hw_cache_dtlb_miss)) + return STAT_DTLB_MISS; + else if (evsel__match(evsel, HW_CACHE, hw_cache_itlb_miss)) + return STAT_ITLB_MISS; + return STAT_NONE; +} -static const char *get_ratio_color(enum grc_type type, double ratio) +static const char *get_ratio_color(const double ratios[3], double val) { - static const double grc_table[GRC_MAX_NR][3] = { - [GRC_STALLED_CYCLES_FE] = { 50.0, 30.0, 10.0 }, - [GRC_STALLED_CYCLES_BE] = { 75.0, 50.0, 20.0 }, - [GRC_CACHE_MISSES] = { 20.0, 10.0, 5.0 }, - }; const char *color = PERF_COLOR_NORMAL; - if (ratio > grc_table[type][0]) + if (val > ratios[0]) color = PERF_COLOR_RED; - else if (ratio > grc_table[type][1]) + else if (val > ratios[1]) color = PERF_COLOR_MAGENTA; - else if (ratio > grc_table[type][2]) + else if (val > ratios[2]) color = PERF_COLOR_YELLOW; return color; } -static double runtime_stat_avg(enum stat_type type, int aggr_idx, - struct runtime_stat_data *rsd) +static double find_stat(const struct evsel *evsel, int aggr_idx, enum stat_type type) { - struct saved_value *v; - - v = saved_value_lookup(NULL, aggr_idx, false, type, rsd->ctx, rsd->cgrp); - if (!v) - return 0.0; - - return avg_stats(&v->stats); + const struct evsel *cur; + int evsel_ctx = evsel_context(evsel); + + evlist__for_each_entry(evsel->evlist, cur) { + struct perf_stat_aggr *aggr; + + /* Ignore the evsel that is being searched from. */ + if (evsel == cur) + continue; + + /* Ignore evsels that are part of different groups. */ + if (evsel->core.leader->nr_members && + evsel->core.leader != cur->core.leader) + continue; + /* Ignore evsels with mismatched modifiers. */ + if (evsel_ctx != evsel_context(cur)) + continue; + /* Ignore if not the cgroup we're looking for. */ + if (evsel->cgrp != cur->cgrp) + continue; + /* Ignore if not the stat we're looking for. */ + if (type != evsel__stat_type(cur)) + continue; + + aggr = &cur->stats->aggr[aggr_idx]; + if (type == STAT_NSECS) + return aggr->counts.val; + return aggr->counts.val * cur->scale; + } + return 0.0; } -static double runtime_stat_n(enum stat_type type, int aggr_idx, - struct runtime_stat_data *rsd) +static void print_ratio(struct perf_stat_config *config, + const struct evsel *evsel, int aggr_idx, + double numerator, struct perf_stat_output_ctx *out, + enum stat_type denominator_type, + const double color_ratios[3], const char *unit) { - struct saved_value *v; + double denominator = find_stat(evsel, aggr_idx, denominator_type); - v = saved_value_lookup(NULL, aggr_idx, false, type, rsd->ctx, rsd->cgrp); - if (!v) - return 0.0; + if (numerator && denominator) { + double ratio = numerator / denominator * 100.0; + const char *color = get_ratio_color(color_ratios, ratio); - return v->stats.n; + out->print_metric(config, out->ctx, color, "%7.2f%%", unit, ratio); + } else + out->print_metric(config, out->ctx, NULL, NULL, unit, 0); } -static void print_stalled_cycles_frontend(struct perf_stat_config *config, - int aggr_idx, double avg, - struct perf_stat_output_ctx *out, - struct runtime_stat_data *rsd) +static void print_stalled_cycles_front(struct perf_stat_config *config, + const struct evsel *evsel, + int aggr_idx, double stalled, + struct perf_stat_output_ctx *out) { - double total, ratio = 0.0; - const char *color; - - total = runtime_stat_avg(STAT_CYCLES, aggr_idx, rsd); - - if (total) - ratio = avg / total * 100.0; + static const double color_ratios[3] = {50.0, 30.0, 10.0}; - color = get_ratio_color(GRC_STALLED_CYCLES_FE, ratio); - - if (ratio) - out->print_metric(config, out->ctx, color, "%7.2f%%", "frontend cycles idle", - ratio); - else - out->print_metric(config, out->ctx, NULL, NULL, "frontend cycles idle", 0); + print_ratio(config, evsel, aggr_idx, stalled, out, STAT_CYCLES, color_ratios, + "frontend cycles idle"); } -static void print_stalled_cycles_backend(struct perf_stat_config *config, - int aggr_idx, double avg, - struct perf_stat_output_ctx *out, - struct runtime_stat_data *rsd) +static void print_stalled_cycles_back(struct perf_stat_config *config, + const struct evsel *evsel, + int aggr_idx, double stalled, + struct perf_stat_output_ctx *out) { - double total, ratio = 0.0; - const char *color; - - total = runtime_stat_avg(STAT_CYCLES, aggr_idx, rsd); - - if (total) - ratio = avg / total * 100.0; + static const double color_ratios[3] = {75.0, 50.0, 20.0}; - color = get_ratio_color(GRC_STALLED_CYCLES_BE, ratio); - - out->print_metric(config, out->ctx, color, "%7.2f%%", "backend cycles idle", ratio); + print_ratio(config, evsel, aggr_idx, stalled, out, STAT_CYCLES, color_ratios, + "backend cycles idle"); } -static void print_branch_misses(struct perf_stat_config *config, - int aggr_idx, double avg, - struct perf_stat_output_ctx *out, - struct runtime_stat_data *rsd) +static void print_branch_miss(struct perf_stat_config *config, + const struct evsel *evsel, + int aggr_idx, double misses, + struct perf_stat_output_ctx *out) { - double total, ratio = 0.0; - const char *color; - - total = runtime_stat_avg(STAT_BRANCHES, aggr_idx, rsd); - - if (total) - ratio = avg / total * 100.0; + static const double color_ratios[3] = {20.0, 10.0, 5.0}; - color = get_ratio_color(GRC_CACHE_MISSES, ratio); - - out->print_metric(config, out->ctx, color, "%7.2f%%", "of all branches", ratio); + print_ratio(config, evsel, aggr_idx, misses, out, STAT_BRANCHES, color_ratios, + "of all branches"); } -static void print_l1_dcache_misses(struct perf_stat_config *config, - int aggr_idx, double avg, - struct perf_stat_output_ctx *out, - struct runtime_stat_data *rsd) +static void print_l1d_miss(struct perf_stat_config *config, + const struct evsel *evsel, + int aggr_idx, double misses, + struct perf_stat_output_ctx *out) { - double total, ratio = 0.0; - const char *color; - - total = runtime_stat_avg(STAT_L1_DCACHE, aggr_idx, rsd); + static const double color_ratios[3] = {20.0, 10.0, 5.0}; - if (total) - ratio = avg / total * 100.0; + print_ratio(config, evsel, aggr_idx, misses, out, STAT_L1_DCACHE, color_ratios, + "of all L1-dcache accesses"); +} - color = get_ratio_color(GRC_CACHE_MISSES, ratio); +static void print_l1i_miss(struct perf_stat_config *config, + const struct evsel *evsel, + int aggr_idx, double misses, + struct perf_stat_output_ctx *out) +{ + static const double color_ratios[3] = {20.0, 10.0, 5.0}; - out->print_metric(config, out->ctx, color, "%7.2f%%", "of all L1-dcache accesses", ratio); + print_ratio(config, evsel, aggr_idx, misses, out, STAT_L1_ICACHE, color_ratios, + "of all L1-icache accesses"); } -static void print_l1_icache_misses(struct perf_stat_config *config, - int aggr_idx, double avg, - struct perf_stat_output_ctx *out, - struct runtime_stat_data *rsd) +static void print_ll_miss(struct perf_stat_config *config, + const struct evsel *evsel, + int aggr_idx, double misses, + struct perf_stat_output_ctx *out) { - double total, ratio = 0.0; - const char *color; + static const double color_ratios[3] = {20.0, 10.0, 5.0}; - total = runtime_stat_avg(STAT_L1_ICACHE, aggr_idx, rsd); + print_ratio(config, evsel, aggr_idx, misses, out, STAT_LL_CACHE, color_ratios, + "of all L1-icache accesses"); +} - if (total) - ratio = avg / total * 100.0; +static void print_dtlb_miss(struct perf_stat_config *config, + const struct evsel *evsel, + int aggr_idx, double misses, + struct perf_stat_output_ctx *out) +{ + static const double color_ratios[3] = {20.0, 10.0, 5.0}; - color = get_ratio_color(GRC_CACHE_MISSES, ratio); - out->print_metric(config, out->ctx, color, "%7.2f%%", "of all L1-icache accesses", ratio); + print_ratio(config, evsel, aggr_idx, misses, out, STAT_DTLB_CACHE, color_ratios, + "of all dTLB cache accesses"); } -static void print_dtlb_cache_misses(struct perf_stat_config *config, - int aggr_idx, double avg, - struct perf_stat_output_ctx *out, - struct runtime_stat_data *rsd) +static void print_itlb_miss(struct perf_stat_config *config, + const struct evsel *evsel, + int aggr_idx, double misses, + struct perf_stat_output_ctx *out) { - double total, ratio = 0.0; - const char *color; + static const double color_ratios[3] = {20.0, 10.0, 5.0}; - total = runtime_stat_avg(STAT_DTLB_CACHE, aggr_idx, rsd); + print_ratio(config, evsel, aggr_idx, misses, out, STAT_ITLB_CACHE, color_ratios, + "of all iTLB cache accesses"); +} - if (total) - ratio = avg / total * 100.0; +static void print_cache_miss(struct perf_stat_config *config, + const struct evsel *evsel, + int aggr_idx, double misses, + struct perf_stat_output_ctx *out) +{ + static const double color_ratios[3] = {20.0, 10.0, 5.0}; - color = get_ratio_color(GRC_CACHE_MISSES, ratio); - out->print_metric(config, out->ctx, color, "%7.2f%%", "of all dTLB cache accesses", ratio); + print_ratio(config, evsel, aggr_idx, misses, out, STAT_CACHE_REFS, color_ratios, + "of all cache refs"); } -static void print_itlb_cache_misses(struct perf_stat_config *config, - int aggr_idx, double avg, - struct perf_stat_output_ctx *out, - struct runtime_stat_data *rsd) +static void print_instructions(struct perf_stat_config *config, + const struct evsel *evsel, + int aggr_idx, double instructions, + struct perf_stat_output_ctx *out) { - double total, ratio = 0.0; - const char *color; + print_metric_t print_metric = out->print_metric; + void *ctxp = out->ctx; + double cycles = find_stat(evsel, aggr_idx, STAT_CYCLES); + double max_stalled = max(find_stat(evsel, aggr_idx, STAT_STALLED_CYCLES_FRONT), + find_stat(evsel, aggr_idx, STAT_STALLED_CYCLES_BACK)); + + if (cycles) { + print_metric(config, ctxp, NULL, "%7.2f ", "insn per cycle", + instructions / cycles); + } else + print_metric(config, ctxp, NULL, NULL, "insn per cycle", 0); + + if (max_stalled && instructions) { + out->new_line(config, ctxp); + print_metric(config, ctxp, NULL, "%7.2f ", "stalled cycles per insn", + max_stalled / instructions); + } +} - total = runtime_stat_avg(STAT_ITLB_CACHE, aggr_idx, rsd); +static void print_cycles(struct perf_stat_config *config, + const struct evsel *evsel, + int aggr_idx, double cycles, + struct perf_stat_output_ctx *out) +{ + double nsecs = find_stat(evsel, aggr_idx, STAT_NSECS); - if (total) - ratio = avg / total * 100.0; + if (cycles && nsecs) { + double ratio = cycles / nsecs; - color = get_ratio_color(GRC_CACHE_MISSES, ratio); - out->print_metric(config, out->ctx, color, "%7.2f%%", "of all iTLB cache accesses", ratio); + out->print_metric(config, out->ctx, NULL, "%8.3f", "GHz", ratio); + } else + out->print_metric(config, out->ctx, NULL, NULL, "GHz", 0); } -static void print_ll_cache_misses(struct perf_stat_config *config, - int aggr_idx, double avg, - struct perf_stat_output_ctx *out, - struct runtime_stat_data *rsd) +static void print_nsecs(struct perf_stat_config *config, + const struct evsel *evsel, + int aggr_idx __maybe_unused, double nsecs, + struct perf_stat_output_ctx *out) { - double total, ratio = 0.0; - const char *color; - - total = runtime_stat_avg(STAT_LL_CACHE, aggr_idx, rsd); - - if (total) - ratio = avg / total * 100.0; + print_metric_t print_metric = out->print_metric; + void *ctxp = out->ctx; + double wall_time = avg_stats(&walltime_nsecs_stats); - color = get_ratio_color(GRC_CACHE_MISSES, ratio); - out->print_metric(config, out->ctx, color, "%7.2f%%", "of all LL-cache accesses", ratio); + if (wall_time) { + print_metric(config, ctxp, NULL, "%8.3f", "CPUs utilized", + nsecs / (wall_time * evsel->scale)); + } else + print_metric(config, ctxp, NULL, NULL, "CPUs utilized", 0); } static int prepare_metric(struct evsel **metric_events, @@ -638,139 +730,51 @@ void perf_stat__print_shadow_stats(struct perf_stat_config *config, struct perf_stat_output_ctx *out, struct rblist *metric_events) { - void *ctxp = out->ctx; - print_metric_t print_metric = out->print_metric; - double total, ratio = 0.0; - struct runtime_stat_data rsd = { - .ctx = evsel_context(evsel), - .cgrp = evsel->cgrp, + typedef void (*stat_print_function_t)(struct perf_stat_config *config, + const struct evsel *evsel, + int aggr_idx, double misses, + struct perf_stat_output_ctx *out); + static const stat_print_function_t stat_print_function[STAT_MAX] = { + [STAT_INSTRUCTIONS] = print_instructions, + [STAT_BRANCH_MISS] = print_branch_miss, + [STAT_L1D_MISS] = print_l1d_miss, + [STAT_L1I_MISS] = print_l1i_miss, + [STAT_DTLB_MISS] = print_dtlb_miss, + [STAT_ITLB_MISS] = print_itlb_miss, + [STAT_LL_MISS] = print_ll_miss, + [STAT_CACHE_MISSES] = print_cache_miss, + [STAT_STALLED_CYCLES_FRONT] = print_stalled_cycles_front, + [STAT_STALLED_CYCLES_BACK] = print_stalled_cycles_back, + [STAT_CYCLES] = print_cycles, + [STAT_NSECS] = print_nsecs, }; + print_metric_t print_metric = out->print_metric; + void *ctxp = out->ctx; struct metric_event *me; int num = 1; if (config->iostat_run) { iostat_print_metric(config, evsel, out); - } else if (evsel__match(evsel, HARDWARE, HW_INSTRUCTIONS)) { - total = runtime_stat_avg(STAT_CYCLES, aggr_idx, &rsd); - - if (total) { - ratio = avg / total; - print_metric(config, ctxp, NULL, "%7.2f ", - "insn per cycle", ratio); - } else { - print_metric(config, ctxp, NULL, NULL, "insn per cycle", 0); - } - - total = runtime_stat_avg(STAT_STALLED_CYCLES_FRONT, aggr_idx, &rsd); - - total = max(total, runtime_stat_avg(STAT_STALLED_CYCLES_BACK, - aggr_idx, &rsd)); - - if (total && avg) { - out->new_line(config, ctxp); - ratio = total / avg; - print_metric(config, ctxp, NULL, "%7.2f ", - "stalled cycles per insn", - ratio); - } - } else if (evsel__match(evsel, HARDWARE, HW_BRANCH_MISSES)) { - if (runtime_stat_n(STAT_BRANCHES, aggr_idx, &rsd) != 0) - print_branch_misses(config, aggr_idx, avg, out, &rsd); - else - print_metric(config, ctxp, NULL, NULL, "of all branches", 0); - } else if ( - evsel->core.attr.type == PERF_TYPE_HW_CACHE && - evsel->core.attr.config == ( PERF_COUNT_HW_CACHE_L1D | - ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | - ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) { - - if (runtime_stat_n(STAT_L1_DCACHE, aggr_idx, &rsd) != 0) - print_l1_dcache_misses(config, aggr_idx, avg, out, &rsd); - else - print_metric(config, ctxp, NULL, NULL, "of all L1-dcache accesses", 0); - } else if ( - evsel->core.attr.type == PERF_TYPE_HW_CACHE && - evsel->core.attr.config == ( PERF_COUNT_HW_CACHE_L1I | - ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | - ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) { - - if (runtime_stat_n(STAT_L1_ICACHE, aggr_idx, &rsd) != 0) - print_l1_icache_misses(config, aggr_idx, avg, out, &rsd); - else - print_metric(config, ctxp, NULL, NULL, "of all L1-icache accesses", 0); - } else if ( - evsel->core.attr.type == PERF_TYPE_HW_CACHE && - evsel->core.attr.config == ( PERF_COUNT_HW_CACHE_DTLB | - ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | - ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) { - - if (runtime_stat_n(STAT_DTLB_CACHE, aggr_idx, &rsd) != 0) - print_dtlb_cache_misses(config, aggr_idx, avg, out, &rsd); - else - print_metric(config, ctxp, NULL, NULL, "of all dTLB cache accesses", 0); - } else if ( - evsel->core.attr.type == PERF_TYPE_HW_CACHE && - evsel->core.attr.config == ( PERF_COUNT_HW_CACHE_ITLB | - ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | - ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) { - - if (runtime_stat_n(STAT_ITLB_CACHE, aggr_idx, &rsd) != 0) - print_itlb_cache_misses(config, aggr_idx, avg, out, &rsd); - else - print_metric(config, ctxp, NULL, NULL, "of all iTLB cache accesses", 0); - } else if ( - evsel->core.attr.type == PERF_TYPE_HW_CACHE && - evsel->core.attr.config == ( PERF_COUNT_HW_CACHE_LL | - ((PERF_COUNT_HW_CACHE_OP_READ) << 8) | - ((PERF_COUNT_HW_CACHE_RESULT_MISS) << 16))) { - - if (runtime_stat_n(STAT_LL_CACHE, aggr_idx, &rsd) != 0) - print_ll_cache_misses(config, aggr_idx, avg, out, &rsd); - else - print_metric(config, ctxp, NULL, NULL, "of all LL-cache accesses", 0); - } else if (evsel__match(evsel, HARDWARE, HW_CACHE_MISSES)) { - total = runtime_stat_avg(STAT_CACHEREFS, aggr_idx, &rsd); - - if (total) - ratio = avg * 100 / total; - - if (runtime_stat_n(STAT_CACHEREFS, aggr_idx, &rsd) != 0) - print_metric(config, ctxp, NULL, "%8.3f %%", - "of all cache refs", ratio); - else - print_metric(config, ctxp, NULL, NULL, "of all cache refs", 0); - } else if (evsel__match(evsel, HARDWARE, HW_STALLED_CYCLES_FRONTEND)) { - print_stalled_cycles_frontend(config, aggr_idx, avg, out, &rsd); - } else if (evsel__match(evsel, HARDWARE, HW_STALLED_CYCLES_BACKEND)) { - print_stalled_cycles_backend(config, aggr_idx, avg, out, &rsd); - } else if (evsel__match(evsel, HARDWARE, HW_CPU_CYCLES)) { - total = runtime_stat_avg(STAT_NSECS, aggr_idx, &rsd); - - if (total) { - ratio = avg / total; - print_metric(config, ctxp, NULL, "%8.3f", "GHz", ratio); - } else { - print_metric(config, ctxp, NULL, NULL, "Ghz", 0); - } - } else if (evsel__is_clock(evsel)) { - if ((ratio = avg_stats(&walltime_nsecs_stats)) != 0) - print_metric(config, ctxp, NULL, "%8.3f", "CPUs utilized", - avg / (ratio * evsel->scale)); - else - print_metric(config, ctxp, NULL, NULL, "CPUs utilized", 0); - } else if (runtime_stat_n(STAT_NSECS, aggr_idx, &rsd) != 0) { - char unit = ' '; - char unit_buf[10] = "/sec"; - - total = runtime_stat_avg(STAT_NSECS, aggr_idx, &rsd); - if (total) - ratio = convert_unit_double(1000000000.0 * avg / total, &unit); - - if (unit != ' ') - snprintf(unit_buf, sizeof(unit_buf), "%c/sec", unit); - print_metric(config, ctxp, NULL, "%8.3f", unit_buf, ratio); } else { - num = 0; + stat_print_function_t fn = stat_print_function[evsel__stat_type(evsel)]; + + if (fn) + fn(config, evsel, aggr_idx, avg, out); + else { + double nsecs = find_stat(evsel, aggr_idx, STAT_NSECS); + + if (nsecs) { + char unit = ' '; + char unit_buf[10] = "/sec"; + double ratio = convert_unit_double(1000000000.0 * avg / nsecs, + &unit); + + if (unit != ' ') + snprintf(unit_buf, sizeof(unit_buf), "%c/sec", unit); + print_metric(config, ctxp, NULL, "%8.3f", unit_buf, ratio); + } else + num = 0; + } } if ((me = metricgroup__lookup(metric_events, evsel, false)) != NULL) { -- cgit v1.2.3-58-ga151 From aa0964e3ecebe92243bac30f9317117037adecb9 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Feb 2023 01:28:48 -0800 Subject: perf stat: Remove saved_value/runtime_stat As saved_value/runtime_stat are only written to and not read, remove the associated logic and writes. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexandre Torgue Cc: Andrii Nakryiko Cc: Athira Rajeev Cc: Caleb Biggers Cc: Eduard Zingerman Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Maxime Coquelin Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sandipan Das Cc: Sean Christopherson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-52-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-script.c | 5 - tools/perf/builtin-stat.c | 6 -- tools/perf/tests/parse-metric.c | 1 - tools/perf/tests/pmu-events.c | 1 - tools/perf/util/stat-shadow.c | 198 ---------------------------------------- tools/perf/util/stat.c | 24 ----- tools/perf/util/stat.h | 4 - 7 files changed, 239 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index e9b5387161df..522226114263 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -2072,9 +2072,6 @@ static void perf_sample__fprint_metric(struct perf_script *script, if (evsel_script(leader)->gnum++ == 0) perf_stat__reset_shadow_stats(); val = sample->period * evsel->scale; - perf_stat__update_shadow_stats(evsel, - val, - sample->cpu); evsel_script(evsel)->val = val; if (evsel_script(leader)->gnum == leader->core.nr_members) { for_each_group_member (ev2, leader) { @@ -2792,8 +2789,6 @@ static int __cmd_script(struct perf_script *script) signal(SIGINT, sig_handler); - perf_stat__init_shadow_stats(); - /* override event processing functions */ if (script->show_task_events) { script->tool.comm = process_comm_event; diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index 619387459914..d70b1ec88594 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -424,7 +424,6 @@ static void process_counters(void) perf_stat_merge_counters(&stat_config, evsel_list); perf_stat_process_percore(&stat_config, evsel_list); - perf_stat_process_shadow_stats(&stat_config, evsel_list); } static void process_interval(void) @@ -434,7 +433,6 @@ static void process_interval(void) clock_gettime(CLOCK_MONOTONIC, &ts); diff_timespec(&rs, &ts, &ref_time); - perf_stat__reset_shadow_per_stat(); evlist__reset_aggr_stats(evsel_list); if (read_counters(&rs) == 0) @@ -910,7 +908,6 @@ try_again_reset: evlist__copy_prev_raw_counts(evsel_list); evlist__reset_prev_raw_counts(evsel_list); evlist__reset_aggr_stats(evsel_list); - perf_stat__reset_shadow_per_stat(); } else { update_stats(&walltime_nsecs_stats, t1 - t0); update_rusage_stats(&ru_stats, &stat_config.ru_data); @@ -2132,8 +2129,6 @@ static int __cmd_report(int argc, const char **argv) input_name = "perf.data"; } - perf_stat__init_shadow_stats(); - perf_stat.data.path = input_name; perf_stat.data.mode = PERF_DATA_MODE_READ; @@ -2413,7 +2408,6 @@ int cmd_stat(int argc, const char **argv) &stat_config.metric_events); zfree(&metrics); } - perf_stat__init_shadow_stats(); if (add_default_attributes()) goto out; diff --git a/tools/perf/tests/parse-metric.c b/tools/perf/tests/parse-metric.c index b9b8a48289c4..c43b056f9fa3 100644 --- a/tools/perf/tests/parse-metric.c +++ b/tools/perf/tests/parse-metric.c @@ -296,7 +296,6 @@ static int test_metric_group(void) static int test__parse_metric(struct test_suite *test __maybe_unused, int subtest __maybe_unused) { - perf_stat__init_shadow_stats(); TEST_ASSERT_VAL("IPC failed", test_ipc() == 0); TEST_ASSERT_VAL("frontend failed", test_frontend() == 0); TEST_ASSERT_VAL("DCache_L2 failed", test_dcache_l2() == 0); diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c index 4ec2a4ca1a82..6ccd413b5983 100644 --- a/tools/perf/tests/pmu-events.c +++ b/tools/perf/tests/pmu-events.c @@ -905,7 +905,6 @@ static int test__parsing(struct test_suite *test __maybe_unused, { int failures = 0; - perf_stat__init_shadow_stats(); pmu_for_each_core_metric(test__parsing_callback, &failures); pmu_for_each_sys_metric(test__parsing_callback, &failures); diff --git a/tools/perf/util/stat-shadow.c b/tools/perf/util/stat-shadow.c index 9d22cde09dc9..ef85f1ae1ab2 100644 --- a/tools/perf/util/stat-shadow.c +++ b/tools/perf/util/stat-shadow.c @@ -16,22 +16,9 @@ #include "iostat.h" #include "util/hashmap.h" -/* - * AGGR_GLOBAL: Use CPU 0 - * AGGR_SOCKET: Use first CPU of socket - * AGGR_DIE: Use first CPU of die - * AGGR_CORE: Use first CPU of core - * AGGR_NONE: Use matching CPU - * AGGR_THREAD: Not supported? - */ - struct stats walltime_nsecs_stats; struct rusage_stats ru_stats; -static struct runtime_stat { - struct rblist value_list; -} rt_stat; - enum { CTX_BIT_USER = 1 << 0, CTX_BIT_KERNEL = 1 << 1, @@ -65,117 +52,6 @@ enum stat_type { STAT_MAX }; -struct saved_value { - struct rb_node rb_node; - struct evsel *evsel; - enum stat_type type; - int ctx; - int map_idx; /* cpu or thread map index */ - struct cgroup *cgrp; - struct stats stats; - u64 metric_total; - int metric_other; -}; - -static int saved_value_cmp(struct rb_node *rb_node, const void *entry) -{ - struct saved_value *a = container_of(rb_node, - struct saved_value, - rb_node); - const struct saved_value *b = entry; - - if (a->map_idx != b->map_idx) - return a->map_idx - b->map_idx; - - /* - * Previously the rbtree was used to link generic metrics. - * The keys were evsel/cpu. Now the rbtree is extended to support - * per-thread shadow stats. For shadow stats case, the keys - * are cpu/type/ctx/stat (evsel is NULL). For generic metrics - * case, the keys are still evsel/cpu (type/ctx/stat are 0 or NULL). - */ - if (a->type != b->type) - return a->type - b->type; - - if (a->ctx != b->ctx) - return a->ctx - b->ctx; - - if (a->cgrp != b->cgrp) - return (char *)a->cgrp < (char *)b->cgrp ? -1 : +1; - - if (a->evsel == b->evsel) - return 0; - if ((char *)a->evsel < (char *)b->evsel) - return -1; - return +1; -} - -static struct rb_node *saved_value_new(struct rblist *rblist __maybe_unused, - const void *entry) -{ - struct saved_value *nd = malloc(sizeof(struct saved_value)); - - if (!nd) - return NULL; - memcpy(nd, entry, sizeof(struct saved_value)); - return &nd->rb_node; -} - -static void saved_value_delete(struct rblist *rblist __maybe_unused, - struct rb_node *rb_node) -{ - struct saved_value *v; - - BUG_ON(!rb_node); - v = container_of(rb_node, struct saved_value, rb_node); - free(v); -} - -static struct saved_value *saved_value_lookup(struct evsel *evsel, - int map_idx, - bool create, - enum stat_type type, - int ctx, - struct cgroup *cgrp) -{ - struct rblist *rblist; - struct rb_node *nd; - struct saved_value dm = { - .map_idx = map_idx, - .evsel = evsel, - .type = type, - .ctx = ctx, - .cgrp = cgrp, - }; - - rblist = &rt_stat.value_list; - - /* don't use context info for clock events */ - if (type == STAT_NSECS) - dm.ctx = 0; - - nd = rblist__find(rblist, &dm); - if (nd) - return container_of(nd, struct saved_value, rb_node); - if (create) { - rblist__add_node(rblist, &dm); - nd = rblist__find(rblist, &dm); - if (nd) - return container_of(nd, struct saved_value, rb_node); - } - return NULL; -} - -void perf_stat__init_shadow_stats(void) -{ - struct rblist *rblist = &rt_stat.value_list; - - rblist__init(rblist); - rblist->node_cmp = saved_value_cmp; - rblist->node_new = saved_value_new; - rblist->node_delete = saved_value_delete; -} - static int evsel_context(const struct evsel *evsel) { int ctx = 0; @@ -194,86 +70,12 @@ static int evsel_context(const struct evsel *evsel) return ctx; } -void perf_stat__reset_shadow_per_stat(void) -{ - struct rblist *rblist; - struct rb_node *pos, *next; - - rblist = &rt_stat.value_list; - next = rb_first_cached(&rblist->entries); - while (next) { - pos = next; - next = rb_next(pos); - memset(&container_of(pos, struct saved_value, rb_node)->stats, - 0, - sizeof(struct stats)); - } -} - void perf_stat__reset_shadow_stats(void) { - perf_stat__reset_shadow_per_stat(); memset(&walltime_nsecs_stats, 0, sizeof(walltime_nsecs_stats)); memset(&ru_stats, 0, sizeof(ru_stats)); } -struct runtime_stat_data { - int ctx; - struct cgroup *cgrp; -}; - -static void update_runtime_stat(enum stat_type type, - int map_idx, u64 count, - struct runtime_stat_data *rsd) -{ - struct saved_value *v = saved_value_lookup(NULL, map_idx, true, type, - rsd->ctx, rsd->cgrp); - - if (v) - update_stats(&v->stats, count); -} - -/* - * Update various tracking values we maintain to print - * more semantic information such as miss/hit ratios, - * instruction rates, etc: - */ -void perf_stat__update_shadow_stats(struct evsel *counter, u64 count, - int aggr_idx) -{ - u64 count_ns = count; - struct runtime_stat_data rsd = { - .ctx = evsel_context(counter), - .cgrp = counter->cgrp, - }; - count *= counter->scale; - - if (evsel__is_clock(counter)) - update_runtime_stat(STAT_NSECS, aggr_idx, count_ns, &rsd); - else if (evsel__match(counter, HARDWARE, HW_CPU_CYCLES)) - update_runtime_stat(STAT_CYCLES, aggr_idx, count, &rsd); - else if (evsel__match(counter, HARDWARE, HW_STALLED_CYCLES_FRONTEND)) - update_runtime_stat(STAT_STALLED_CYCLES_FRONT, - aggr_idx, count, &rsd); - else if (evsel__match(counter, HARDWARE, HW_STALLED_CYCLES_BACKEND)) - update_runtime_stat(STAT_STALLED_CYCLES_BACK, - aggr_idx, count, &rsd); - else if (evsel__match(counter, HARDWARE, HW_BRANCH_INSTRUCTIONS)) - update_runtime_stat(STAT_BRANCHES, aggr_idx, count, &rsd); - else if (evsel__match(counter, HARDWARE, HW_CACHE_REFERENCES)) - update_runtime_stat(STAT_CACHE_REFS, aggr_idx, count, &rsd); - else if (evsel__match(counter, HW_CACHE, HW_CACHE_L1D)) - update_runtime_stat(STAT_L1_DCACHE, aggr_idx, count, &rsd); - else if (evsel__match(counter, HW_CACHE, HW_CACHE_L1I)) - update_runtime_stat(STAT_L1_ICACHE, aggr_idx, count, &rsd); - else if (evsel__match(counter, HW_CACHE, HW_CACHE_LL)) - update_runtime_stat(STAT_LL_CACHE, aggr_idx, count, &rsd); - else if (evsel__match(counter, HW_CACHE, HW_CACHE_DTLB)) - update_runtime_stat(STAT_DTLB_CACHE, aggr_idx, count, &rsd); - else if (evsel__match(counter, HW_CACHE, HW_CACHE_ITLB)) - update_runtime_stat(STAT_ITLB_CACHE, aggr_idx, count, &rsd); -} - static enum stat_type evsel__stat_type(const struct evsel *evsel) { /* Fake perf_hw_cache_op_id values for use with evsel__match. */ diff --git a/tools/perf/util/stat.c b/tools/perf/util/stat.c index 83dc4c1f4b12..4abfd87c5352 100644 --- a/tools/perf/util/stat.c +++ b/tools/perf/util/stat.c @@ -648,30 +648,6 @@ void perf_stat_process_percore(struct perf_stat_config *config, struct evlist *e evsel__process_percore(evsel); } -static void evsel__update_shadow_stats(struct evsel *evsel) -{ - struct perf_stat_evsel *ps = evsel->stats; - int aggr_idx; - - if (ps->aggr == NULL) - return; - - for (aggr_idx = 0; aggr_idx < ps->nr_aggr; aggr_idx++) { - struct perf_counts_values *aggr_counts = &ps->aggr[aggr_idx].counts; - - perf_stat__update_shadow_stats(evsel, aggr_counts->val, aggr_idx); - } -} - -void perf_stat_process_shadow_stats(struct perf_stat_config *config __maybe_unused, - struct evlist *evlist) -{ - struct evsel *evsel; - - evlist__for_each_entry(evlist, evsel) - evsel__update_shadow_stats(evsel); -} - int perf_event__process_stat_event(struct perf_session *session, union perf_event *event) { diff --git a/tools/perf/util/stat.h b/tools/perf/util/stat.h index b01c828c3799..41204547b76b 100644 --- a/tools/perf/util/stat.h +++ b/tools/perf/util/stat.h @@ -157,10 +157,7 @@ typedef void (*print_metric_t)(struct perf_stat_config *config, const char *fmt, double val); typedef void (*new_line_t)(struct perf_stat_config *config, void *ctx); -void perf_stat__init_shadow_stats(void); void perf_stat__reset_shadow_stats(void); -void perf_stat__reset_shadow_per_stat(void); -void perf_stat__update_shadow_stats(struct evsel *counter, u64 count, int aggr_idx); struct perf_stat_output_ctx { void *ctx; print_metric_t print_metric; @@ -189,7 +186,6 @@ int perf_stat_process_counter(struct perf_stat_config *config, struct evsel *counter); void perf_stat_merge_counters(struct perf_stat_config *config, struct evlist *evlist); void perf_stat_process_percore(struct perf_stat_config *config, struct evlist *evlist); -void perf_stat_process_shadow_stats(struct perf_stat_config *config, struct evlist *evlist); struct perf_tool; union perf_event; -- cgit v1.2.3-58-ga151 From b0365c147f7b2aeb500456601bf6a3e08133b178 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Wed, 22 Feb 2023 21:53:04 -0800 Subject: perf vendor events intel: Update alderlake to v1.19 Update alderlake perf json from v1.18 to v1.19. Based on: https://github.com/intel/perfmon/pull/58 perf JSON files created using: https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230223055306.296179-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/alderlake/memory.json | 8 ++++++++ tools/perf/pmu-events/arch/x86/alderlake/pipeline.json | 10 ++++++++++ tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 3 files changed, 19 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/alderlake/memory.json b/tools/perf/pmu-events/arch/x86/alderlake/memory.json index 37f3d062a788..55827b276e6e 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/memory.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/memory.json @@ -24,6 +24,14 @@ "UMask": "0xf4", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.", + "EventCode": "0x05", + "EventName": "LD_HEAD.L1_MISS_AT_RET", + "SampleAfterValue": "1000003", + "UMask": "0x81", + "Unit": "cpu_atom" + }, { "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.", "EventCode": "0x05", diff --git a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json b/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json index 2dba3a115f97..f848530fbf07 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json @@ -361,6 +361,16 @@ "UMask": "0xeb", "Unit": "cpu_atom" }, + { + "BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.INDIRECT", + "PEBS": "1", + "PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.", + "SampleAfterValue": "100003", + "UMask": "0x80", + "Unit": "cpu_core" + }, { "BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.", "EventCode": "0xc5", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 1c6eef118e61..e69b29123327 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -1,5 +1,5 @@ Family-model,Version,Filename,EventType -GenuineIntel-6-(97|9A|B7|BA|BF),v1.18,alderlake,core +GenuineIntel-6-(97|9A|B7|BA|BF),v1.19,alderlake,core GenuineIntel-6-BE,v1.18,alderlaken,core GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core GenuineIntel-6-(3D|47),v26,broadwell,core -- cgit v1.2.3-58-ga151 From b42d103bc02de484dc4aefe457ffcc35637b6754 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Wed, 22 Feb 2023 21:53:05 -0800 Subject: perf vendor events intel: Update alderlaken to v1.19 Update alderlaken perf json from v1.18 to v1.19. Based on: https://github.com/intel/perfmon/pull/58 perf JSON files created using: https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230223055306.296179-3-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/alderlaken/memory.json | 7 +++++++ tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/memory.json b/tools/perf/pmu-events/arch/x86/alderlaken/memory.json index f84bf8c43495..37259d38a222 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/memory.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/memory.json @@ -13,6 +13,13 @@ "SampleAfterValue": "1000003", "UMask": "0xf4" }, + { + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.", + "EventCode": "0x05", + "EventName": "LD_HEAD.L1_MISS_AT_RET", + "SampleAfterValue": "1000003", + "UMask": "0x81" + }, { "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.", "EventCode": "0x05", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index e69b29123327..1c5776e37120 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -1,6 +1,6 @@ Family-model,Version,Filename,EventType GenuineIntel-6-(97|9A|B7|BA|BF),v1.19,alderlake,core -GenuineIntel-6-BE,v1.18,alderlaken,core +GenuineIntel-6-BE,v1.19,alderlaken,core GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core GenuineIntel-6-(3D|47),v26,broadwell,core GenuineIntel-6-56,v7,broadwellde,core -- cgit v1.2.3-58-ga151 From 0ec73817ca21f6ed4f2cca44b63e81a688c0ba0b Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Wed, 22 Feb 2023 21:53:06 -0800 Subject: perf vendor events intel: Update icelakex to v1.19 Update icelakex perf json from v1.18 to v1.19. Based on: https://github.com/intel/perfmon/pull/58 perf JSON files created using: https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230223055306.296179-4-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/icelakex/cache.json | 8 ++++++ .../arch/x86/icelakex/floating-point.json | 31 ++++++++++++++++++++++ .../pmu-events/arch/x86/icelakex/pipeline.json | 10 +++++++ tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 4 files changed, 50 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/icelakex/cache.json b/tools/perf/pmu-events/arch/x86/icelakex/cache.json index d6463c8d9462..3bdc56a75097 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/cache.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/cache.json @@ -825,6 +825,14 @@ "SampleAfterValue": "1000003", "UMask": "0x1" }, + { + "BriefDescription": "Counts bus locks, accounts for cache line split locks and UC locks.", + "EventCode": "0xF4", + "EventName": "SQ_MISC.BUS_LOCK", + "PublicDescription": "Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically. Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, { "BriefDescription": "Cycles the queue waiting for offcore responses is full.", "EventCode": "0xf4", diff --git a/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json b/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json index 655342dadac6..85c26c889088 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json @@ -39,6 +39,14 @@ "SampleAfterValue": "100003", "UMask": "0x20" }, + { + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x18" + }, { "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "EventCode": "0xc7", @@ -55,6 +63,22 @@ "SampleAfterValue": "100003", "UMask": "0x80" }, + { + "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x60" + }, + { + "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "1000003", + "UMask": "0x3" + }, { "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "EventCode": "0xc7", @@ -70,5 +94,12 @@ "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x2" + }, + { + "BriefDescription": "Number of any Vector retired FP arithmetic instructions", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.VECTOR", + "SampleAfterValue": "1000003", + "UMask": "0xfc" } ] diff --git a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json index 4cf16a1fcad4..442a4c7539dd 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json @@ -374,6 +374,16 @@ "SampleAfterValue": "2000003", "UMask": "0x3" }, + { + "BriefDescription": "Clears speculative count", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.CLEARS_COUNT", + "PublicDescription": "Counts the number of speculative clears due to any type of branch misprediction or machine clears", + "SampleAfterValue": "500009", + "UMask": "0x1" + }, { "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", "EventCode": "0x0d", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 1c5776e37120..bb4e545fa100 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -13,7 +13,7 @@ GenuineIntel-6-A[DE],v1.00,graniterapids,core GenuineIntel-6-(3C|45|46),v32,haswell,core GenuineIntel-6-3F,v26,haswellx,core GenuineIntel-6-(7D|7E|A7),v1.17,icelake,core -GenuineIntel-6-6[AC],v1.18,icelakex,core +GenuineIntel-6-6[AC],v1.19,icelakex,core GenuineIntel-6-3A,v23,ivybridge,core GenuineIntel-6-3E,v22,ivytown,core GenuineIntel-6-2D,v22,jaketown,core -- cgit v1.2.3-58-ga151 From 07d85ba9d04e1ebd282f656a29ddf08c5b7b32a2 Mon Sep 17 00:00:00 2001 From: Kan Liang Date: Wed, 1 Mar 2023 07:04:13 -0800 Subject: perf record: Fix "read LOST count failed" msg with sample read Hundreds of "read LOST count failed" error messages may be displayed, when the below command is launched. perf record -e '{cpu/mem-loads-aux/,cpu/event=0xcd,umask=0x1/}:S' -a According to the commit 89e3106fa25fb1b6 ("libperf: Handle read format in perf_evsel__read()"), the PERF_FORMAT_GROUP is only available for the leader. However, the record__read_lost_samples() goes through every entry of an evlist, which includes both leader and member. The member event errors out and triggers the error message. Since there may be hundreds of CPUs on a server, the message will be printed hundreds of times, which is very annoying. The message itself is correct, but the pr_err is a overkill. Other error messages in the record__read_lost_samples() are all pr_debug. To make the output format consistent, change the pr_err("read LOST count failed\n"); to pr_debug("read LOST count failed\n");. User can still get the message via -v option. Fixes: e3a23261ad06d598 ("perf record: Read and inject LOST_SAMPLES events") Signed-off-by: Kan Liang Acked-by: Namhyung Kim Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230301150413.27011-1-kan.liang@linux.intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-record.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c index 8374117e66f6..be7c0c29d15b 100644 --- a/tools/perf/builtin-record.c +++ b/tools/perf/builtin-record.c @@ -1866,7 +1866,7 @@ static void __record__read_lost_samples(struct record *rec, struct evsel *evsel, int id_hdr_size; if (perf_evsel__read(&evsel->core, cpu_idx, thread_idx, &count) < 0) { - pr_err("read LOST count failed\n"); + pr_debug("read LOST count failed\n"); return; } -- cgit v1.2.3-58-ga151 From cb4b9e6813f9243095932c867ff16a7dffa02102 Mon Sep 17 00:00:00 2001 From: Changbin Du Date: Thu, 2 Mar 2023 11:11:45 +0800 Subject: perf record: Reuse target::initial_delay This just simply replace record_opts::initial_delay with target::initial_delay. Nothing else is changed. Signed-off-by: Changbin Du Acked-by: Namhyung Kim Cc: Alexander Shishkin Cc: Hui Wang Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230302031146.2801588-3-changbin.du@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-record.c | 12 ++++++------ tools/perf/builtin-trace.c | 8 ++++---- tools/perf/util/evlist.c | 6 +++--- tools/perf/util/evsel.c | 2 +- tools/perf/util/record.h | 1 - 5 files changed, 14 insertions(+), 15 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c index be7c0c29d15b..fb8aab0cedd0 100644 --- a/tools/perf/builtin-record.c +++ b/tools/perf/builtin-record.c @@ -1292,7 +1292,7 @@ static int record__open(struct record *rec) * dummy event so that we can track PERF_RECORD_MMAP to cover the delay * of waiting or event synthesis. */ - if (opts->initial_delay || target__has_cpu(&opts->target) || + if (opts->target.initial_delay || target__has_cpu(&opts->target) || perf_pmu__has_hybrid()) { pos = evlist__get_tracking_event(evlist); if (!evsel__is_dummy_event(pos)) { @@ -1307,7 +1307,7 @@ static int record__open(struct record *rec) * Enable the dummy event when the process is forked for * initial_delay, immediately for system wide. */ - if (opts->initial_delay && !pos->immediate && + if (opts->target.initial_delay && !pos->immediate && !target__has_cpu(&opts->target)) pos->core.attr.enable_on_exec = 1; else @@ -2522,7 +2522,7 @@ static int __cmd_record(struct record *rec, int argc, const char **argv) * (apart from group members) have enable_on_exec=1 set, * so don't spoil it by prematurely enabling them. */ - if (!target__none(&opts->target) && !opts->initial_delay) + if (!target__none(&opts->target) && !opts->target.initial_delay) evlist__enable(rec->evlist); /* @@ -2574,10 +2574,10 @@ static int __cmd_record(struct record *rec, int argc, const char **argv) evlist__start_workload(rec->evlist); } - if (opts->initial_delay) { + if (opts->target.initial_delay) { pr_info(EVLIST_DISABLED_MSG); - if (opts->initial_delay > 0) { - usleep(opts->initial_delay * USEC_PER_MSEC); + if (opts->target.initial_delay > 0) { + usleep(opts->target.initial_delay * USEC_PER_MSEC); evlist__enable(rec->evlist); pr_info(EVLIST_ENABLED_MSG); } diff --git a/tools/perf/builtin-trace.c b/tools/perf/builtin-trace.c index 610fb60b1c0d..b363c609818b 100644 --- a/tools/perf/builtin-trace.c +++ b/tools/perf/builtin-trace.c @@ -3993,14 +3993,14 @@ static int trace__run(struct trace *trace, int argc, const char **argv) if (err < 0) goto out_error_mmap; - if (!target__none(&trace->opts.target) && !trace->opts.initial_delay) + if (!target__none(&trace->opts.target) && !trace->opts.target.initial_delay) evlist__enable(evlist); if (forks) evlist__start_workload(evlist); - if (trace->opts.initial_delay) { - usleep(trace->opts.initial_delay * 1000); + if (trace->opts.target.initial_delay) { + usleep(trace->opts.target.initial_delay * 1000); evlist__enable(evlist); } @@ -4788,7 +4788,7 @@ int cmd_trace(int argc, const char **argv) "per thread proc mmap processing timeout in ms"), OPT_CALLBACK('G', "cgroup", &trace, "name", "monitor event in cgroup name only", trace__parse_cgroups), - OPT_INTEGER('D', "delay", &trace.opts.initial_delay, + OPT_INTEGER('D', "delay", &trace.opts.target.initial_delay, "ms to wait before starting measurement after program " "start"), OPTS_EVSWITCH(&trace.evswitch), diff --git a/tools/perf/util/evlist.c b/tools/perf/util/evlist.c index 817df2504a1e..9e4b2bb0e6fa 100644 --- a/tools/perf/util/evlist.c +++ b/tools/perf/util/evlist.c @@ -2262,8 +2262,8 @@ int evlist__parse_event_enable_time(struct evlist *evlist, struct record_opts *o if (unset) return 0; - opts->initial_delay = str_to_delay(str); - if (opts->initial_delay) + opts->target.initial_delay = str_to_delay(str); + if (opts->target.initial_delay) return 0; ret = parse_event_enable_times(str, NULL); @@ -2306,7 +2306,7 @@ int evlist__parse_event_enable_time(struct evlist *evlist, struct record_opts *o eet->evlist = evlist; evlist->eet = eet; - opts->initial_delay = eet->times[0].start; + opts->target.initial_delay = eet->times[0].start; return 0; diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index 51e8ce6edddc..462cc0673cee 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -1334,7 +1334,7 @@ void evsel__config(struct evsel *evsel, struct record_opts *opts, * group leaders for traced executed by perf. */ if (target__none(&opts->target) && evsel__is_group_leader(evsel) && - !opts->initial_delay) + !opts->target.initial_delay) attr->enable_on_exec = 1; if (evsel->immediate) { diff --git a/tools/perf/util/record.h b/tools/perf/util/record.h index 46212bf020cf..a6566134e09e 100644 --- a/tools/perf/util/record.h +++ b/tools/perf/util/record.h @@ -65,7 +65,6 @@ struct record_opts { const char *auxtrace_snapshot_opts; const char *auxtrace_sample_opts; bool sample_transaction; - int initial_delay; bool use_clockid; clockid_t clockid; u64 clockid_res_ns; -- cgit v1.2.3-58-ga151 From f9f60efbfc98a9b228d35a1a98fee0528c1fd3ae Mon Sep 17 00:00:00 2001 From: Changbin Du Date: Thu, 2 Mar 2023 11:11:46 +0800 Subject: perf ftrace: Reuse target::initial_delay Replace perf_ftrace::initial_delay with target::initial_delay. Specifying a negative initial_delay is meaningless for ftrace in practice but allowed here. Signed-off-by: Changbin Du Acked-by: Namhyung Kim Cc: Alexander Shishkin Cc: Hui Wang Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230302031146.2801588-4-changbin.du@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-ftrace.c | 10 +++++----- tools/perf/util/ftrace.h | 1 - 2 files changed, 5 insertions(+), 6 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-ftrace.c b/tools/perf/builtin-ftrace.c index d7fe00f66b83..73d51ce84c3a 100644 --- a/tools/perf/builtin-ftrace.c +++ b/tools/perf/builtin-ftrace.c @@ -623,7 +623,7 @@ static int __cmd_ftrace(struct perf_ftrace *ftrace) /* display column headers */ read_tracing_file_to_stdout("trace"); - if (!ftrace->initial_delay) { + if (!ftrace->target.initial_delay) { if (write_tracing_file("tracing_on", "1") < 0) { pr_err("can't enable tracing\n"); goto out_close_fd; @@ -632,8 +632,8 @@ static int __cmd_ftrace(struct perf_ftrace *ftrace) evlist__start_workload(ftrace->evlist); - if (ftrace->initial_delay) { - usleep(ftrace->initial_delay * 1000); + if (ftrace->target.initial_delay > 0) { + usleep(ftrace->target.initial_delay * 1000); if (write_tracing_file("tracing_on", "1") < 0) { pr_err("can't enable tracing\n"); goto out_close_fd; @@ -1164,8 +1164,8 @@ int cmd_ftrace(int argc, const char **argv) "Size of per cpu buffer, needs to use a B, K, M or G suffix.", parse_buffer_size), OPT_BOOLEAN(0, "inherit", &ftrace.inherit, "Trace children processes"), - OPT_UINTEGER('D', "delay", &ftrace.initial_delay, - "Number of milliseconds to wait before starting tracing after program start"), + OPT_INTEGER('D', "delay", &ftrace.target.initial_delay, + "Number of milliseconds to wait before starting tracing after program start"), OPT_PARENT(common_options), }; const struct option latency_options[] = { diff --git a/tools/perf/util/ftrace.h b/tools/perf/util/ftrace.h index a34cd15733b8..558efcb98d25 100644 --- a/tools/perf/util/ftrace.h +++ b/tools/perf/util/ftrace.h @@ -25,7 +25,6 @@ struct perf_ftrace { int graph_noirqs; int graph_verbose; int graph_thresh; - unsigned int initial_delay; }; struct filter_entry { -- cgit v1.2.3-58-ga151 From 5dd827e0fa586521416730e2bb8c3846f6dd91fc Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sat, 11 Mar 2023 18:15:33 -0800 Subject: libperf evlist: Avoid a use of evsel idx Setting the leader iterates the list, so rather than use idx (which may be changed through list reordering) just count the elements and set afterwards. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Kim Phillips Cc: Leo Yan Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sean Christopherson Cc: Steinar H. Gunderson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230312021543.3060328-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/lib/perf/evlist.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) (limited to 'tools') diff --git a/tools/lib/perf/evlist.c b/tools/lib/perf/evlist.c index 61b637f29b82..2d6121e89ccb 100644 --- a/tools/lib/perf/evlist.c +++ b/tools/lib/perf/evlist.c @@ -687,15 +687,14 @@ perf_evlist__next_mmap(struct perf_evlist *evlist, struct perf_mmap *map, void __perf_evlist__set_leader(struct list_head *list, struct perf_evsel *leader) { - struct perf_evsel *first, *last, *evsel; - - first = list_first_entry(list, struct perf_evsel, node); - last = list_last_entry(list, struct perf_evsel, node); - - leader->nr_members = last->idx - first->idx + 1; + struct perf_evsel *evsel; + int n = 0; - __perf_evlist__for_each_entry(list, evsel) + __perf_evlist__for_each_entry(list, evsel) { evsel->leader = leader; + n++; + } + leader->nr_members = n; } void perf_evlist__set_leader(struct perf_evlist *evlist) -- cgit v1.2.3-58-ga151 From bc6c6cdc7d927322461eb95601013524931d2ad6 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sat, 11 Mar 2023 18:15:34 -0800 Subject: perf stat: Don't remove all grouped events when CPU maps disagree If the events in an evlist's CPU map differ then the entire group is removed. For example: ``` $ perf stat -e '{imc_free_running/data_read/,imc_free_running/data_write/,cs}' -a sleep 1 WARNING: grouped events cpus do not match, disabling group: anon group { imc_free_running/data_read/, imc_free_running/data_write/, cs } ``` Change the behavior so that just the events not matching the leader are removed. So in the example above, just 'cs' will be removed. Modify the warning so that it is produced once for each group, rather than once for the entire evlist. Shrink the scope and size of the warning text buffer. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Kim Phillips Cc: Leo Yan Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sean Christopherson Cc: Steinar H. Gunderson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230312021543.3060328-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-stat.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index cfc75517e143..7ef565ae7265 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -181,14 +181,13 @@ static bool cpus_map_matched(struct evsel *a, struct evsel *b) static void evlist__check_cpu_maps(struct evlist *evlist) { - struct evsel *evsel, *pos, *leader; - char buf[1024]; + struct evsel *evsel, *warned_leader = NULL; if (evlist__has_hybrid(evlist)) evlist__warn_hybrid_group(evlist); evlist__for_each_entry(evlist, evsel) { - leader = evsel__leader(evsel); + struct evsel *leader = evsel__leader(evsel); /* Check that leader matches cpus with each member. */ if (leader == evsel) @@ -197,19 +196,26 @@ static void evlist__check_cpu_maps(struct evlist *evlist) continue; /* If there's mismatch disable the group and warn user. */ - WARN_ONCE(1, "WARNING: grouped events cpus do not match, disabling group:\n"); - evsel__group_desc(leader, buf, sizeof(buf)); - pr_warning(" %s\n", buf); - + if (warned_leader != leader) { + char buf[200]; + + pr_warning("WARNING: grouped events cpus do not match.\n" + "Events with CPUs not matching the leader will " + "be removed from the group.\n"); + evsel__group_desc(leader, buf, sizeof(buf)); + pr_warning(" %s\n", buf); + warned_leader = leader; + } if (verbose > 0) { + char buf[200]; + cpu_map__snprint(leader->core.cpus, buf, sizeof(buf)); pr_warning(" %s: %s\n", leader->name, buf); cpu_map__snprint(evsel->core.cpus, buf, sizeof(buf)); pr_warning(" %s: %s\n", evsel->name, buf); } - for_each_group_evsel(pos, leader) - evsel__remove_from_group(pos, leader); + evsel__remove_from_group(evsel, leader); } } -- cgit v1.2.3-58-ga151 From 3c7b84d419c2a85069292d1df0695236f99c52df Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sat, 11 Mar 2023 18:15:35 -0800 Subject: perf pmu: Earlier PMU auxtrace initialization This allows event parsing to use the evsel__is_aux_event function, which is important when determining event grouping. Suggested-by: Adrian Hunter Signed-off-by: Ian Rogers Acked-by: Adrian Hunter Cc: Alexander Shishkin Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Kim Phillips Cc: Leo Yan Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sean Christopherson Cc: Steinar H. Gunderson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230312021543.3060328-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/x86/util/auxtrace.c | 4 ---- tools/perf/arch/x86/util/pmu.c | 8 ++++++-- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'tools') diff --git a/tools/perf/arch/x86/util/auxtrace.c b/tools/perf/arch/x86/util/auxtrace.c index 3da506e13f49..330d03216b0e 100644 --- a/tools/perf/arch/x86/util/auxtrace.c +++ b/tools/perf/arch/x86/util/auxtrace.c @@ -26,11 +26,7 @@ struct auxtrace_record *auxtrace_record__init_intel(struct evlist *evlist, bool found_bts = false; intel_pt_pmu = perf_pmu__find(INTEL_PT_PMU_NAME); - if (intel_pt_pmu) - intel_pt_pmu->auxtrace = true; intel_bts_pmu = perf_pmu__find(INTEL_BTS_PMU_NAME); - if (intel_bts_pmu) - intel_bts_pmu->auxtrace = true; evlist__for_each_entry(evlist, evsel) { if (intel_pt_pmu && evsel->core.attr.type == intel_pt_pmu->type) diff --git a/tools/perf/arch/x86/util/pmu.c b/tools/perf/arch/x86/util/pmu.c index 358340b34243..f73b80dcd8bd 100644 --- a/tools/perf/arch/x86/util/pmu.c +++ b/tools/perf/arch/x86/util/pmu.c @@ -27,10 +27,14 @@ static bool cached_list; struct perf_event_attr *perf_pmu__get_default_config(struct perf_pmu *pmu __maybe_unused) { #ifdef HAVE_AUXTRACE_SUPPORT - if (!strcmp(pmu->name, INTEL_PT_PMU_NAME)) + if (!strcmp(pmu->name, INTEL_PT_PMU_NAME)) { + pmu->auxtrace = true; return intel_pt_pmu_default_config(pmu); - if (!strcmp(pmu->name, INTEL_BTS_PMU_NAME)) + } + if (!strcmp(pmu->name, INTEL_BTS_PMU_NAME)) { + pmu->auxtrace = true; pmu->selectable = true; + } #endif return NULL; } -- cgit v1.2.3-58-ga151 From ce5b85906cd6a14b00f6b2c09d066554d2c13abd Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sat, 11 Mar 2023 18:15:36 -0800 Subject: perf stat: Modify the group test Currently nr_members is 0 for an event with no group, however, they are always a leader of their own group. A later change will make that count 1 because the event is its own leader. Make the find_stat logic consistent with this, an improvement suggested by Namhyung Kim. Suggested-by: Namhyung Kim Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Kim Phillips Cc: Leo Yan Cc: Mark Rutland Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sean Christopherson Cc: Steinar H. Gunderson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230312021543.3060328-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/stat-shadow.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/stat-shadow.c b/tools/perf/util/stat-shadow.c index ef85f1ae1ab2..eeccab6751d7 100644 --- a/tools/perf/util/stat-shadow.c +++ b/tools/perf/util/stat-shadow.c @@ -163,7 +163,7 @@ static double find_stat(const struct evsel *evsel, int aggr_idx, enum stat_type continue; /* Ignore evsels that are part of different groups. */ - if (evsel->core.leader->nr_members && + if (evsel->core.leader->nr_members > 1 && evsel->core.leader != cur->core.leader) continue; /* Ignore evsels with mismatched modifiers. */ -- cgit v1.2.3-58-ga151 From c6d616fe10c62f528c8c52663aec338d2f4ee4c3 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sat, 11 Mar 2023 18:15:37 -0800 Subject: perf evsel: Allow const evsel for certain accesses List sorting, added later to evlist, passes const elements requiring helper functions to also be const. Make the argument to evsel__find_pmu, evsel__is_aux_event and evsel__leader const. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Kim Phillips Cc: Leo Yan Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sean Christopherson Cc: Steinar H. Gunderson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230312021543.3060328-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/evsel.c | 2 +- tools/perf/util/evsel.h | 6 +++--- tools/perf/util/pmu.c | 6 +++--- tools/perf/util/python.c | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index 462cc0673cee..798f072b2763 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -3139,7 +3139,7 @@ bool evsel__is_hybrid(const struct evsel *evsel) return evsel->pmu_name && perf_pmu__is_hybrid(evsel->pmu_name); } -struct evsel *evsel__leader(struct evsel *evsel) +struct evsel *evsel__leader(const struct evsel *evsel) { return container_of(evsel->core.leader, struct evsel, core); } diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h index 814a49ebb7e3..676c499323e9 100644 --- a/tools/perf/util/evsel.h +++ b/tools/perf/util/evsel.h @@ -212,8 +212,8 @@ int evsel__object_config(size_t object_size, int (*init)(struct evsel *evsel), void (*fini)(struct evsel *evsel)); -struct perf_pmu *evsel__find_pmu(struct evsel *evsel); -bool evsel__is_aux_event(struct evsel *evsel); +struct perf_pmu *evsel__find_pmu(const struct evsel *evsel); +bool evsel__is_aux_event(const struct evsel *evsel); struct evsel *evsel__new_idx(struct perf_event_attr *attr, int idx); @@ -505,7 +505,7 @@ int evsel__store_ids(struct evsel *evsel, struct evlist *evlist); void evsel__zero_per_pkg(struct evsel *evsel); bool evsel__is_hybrid(const struct evsel *evsel); -struct evsel *evsel__leader(struct evsel *evsel); +struct evsel *evsel__leader(const struct evsel *evsel); bool evsel__has_leader(struct evsel *evsel, struct evsel *leader); bool evsel__is_leader(struct evsel *evsel); void evsel__set_leader(struct evsel *evsel, struct evsel *leader); diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 43b6182d96b7..45d9b8e28e16 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -988,7 +988,7 @@ struct perf_pmu *perf_pmu__scan(struct perf_pmu *pmu) return NULL; } -struct perf_pmu *evsel__find_pmu(struct evsel *evsel) +struct perf_pmu *evsel__find_pmu(const struct evsel *evsel) { struct perf_pmu *pmu = NULL; @@ -1000,11 +1000,11 @@ struct perf_pmu *evsel__find_pmu(struct evsel *evsel) break; } - evsel->pmu = pmu; + ((struct evsel *)evsel)->pmu = pmu; return pmu; } -bool evsel__is_aux_event(struct evsel *evsel) +bool evsel__is_aux_event(const struct evsel *evsel) { struct perf_pmu *pmu = evsel__find_pmu(evsel); diff --git a/tools/perf/util/python.c b/tools/perf/util/python.c index 42e8b813d010..ab48ffbb6448 100644 --- a/tools/perf/util/python.c +++ b/tools/perf/util/python.c @@ -83,7 +83,7 @@ const char *perf_env__arch(struct perf_env *env __maybe_unused) * far, for the perf python binding known usecases, revisit if this become * necessary. */ -struct perf_pmu *evsel__find_pmu(struct evsel *evsel __maybe_unused) +struct perf_pmu *evsel__find_pmu(const struct evsel *evsel __maybe_unused) { return NULL; } -- cgit v1.2.3-58-ga151 From 7abf0bccaaec77043358ee07e694d31cf9a7dd76 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sat, 11 Mar 2023 18:15:38 -0800 Subject: perf evsel: Add function to compute group PMU name The computed name respects software events and aux event groups, such that the pmu_name is changed to be that of the aux event leader or group leader for software events. This is done as a later change will split events that are in different PMUs into different groups. Committer notes: Added a stub for this new function so that 'perf test python' passes. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Kim Phillips Cc: Leo Yan Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sean Christopherson Cc: Steinar H. Gunderson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230312021543.3060328-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/evsel.c | 24 ++++++++++++++++++++++++ tools/perf/util/evsel.h | 1 + tools/perf/util/python.c | 5 +++++ 3 files changed, 30 insertions(+) (limited to 'tools') diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index 798f072b2763..3dda8a25cf50 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -821,6 +821,30 @@ out_unknown: return "unknown"; } +const char *evsel__group_pmu_name(const struct evsel *evsel) +{ + const struct evsel *leader; + + /* If the pmu_name is set use it. pmu_name isn't set for CPU and software events. */ + if (evsel->pmu_name) + return evsel->pmu_name; + /* + * Software events may be in a group with other uncore PMU events. Use + * the pmu_name of the group leader to avoid breaking the software event + * out of the group. + * + * Aux event leaders, like intel_pt, expect a group with events from + * other PMUs, so substitute the AUX event's PMU in this case. + */ + leader = evsel__leader(evsel); + if ((evsel->core.attr.type == PERF_TYPE_SOFTWARE || evsel__is_aux_event(leader)) && + leader->pmu_name) { + return leader->pmu_name; + } + + return "cpu"; +} + const char *evsel__metric_id(const struct evsel *evsel) { if (evsel->metric_id) diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h index 676c499323e9..d26745ca6147 100644 --- a/tools/perf/util/evsel.h +++ b/tools/perf/util/evsel.h @@ -280,6 +280,7 @@ int arch_evsel__hw_name(struct evsel *evsel, char *bf, size_t size); int __evsel__hw_cache_type_op_res_name(u8 type, u8 op, u8 result, char *bf, size_t size); const char *evsel__name(struct evsel *evsel); +const char *evsel__group_pmu_name(const struct evsel *evsel); const char *evsel__metric_id(const struct evsel *evsel); static inline bool evsel__is_tool(const struct evsel *evsel) diff --git a/tools/perf/util/python.c b/tools/perf/util/python.c index ab48ffbb6448..be336f1b2b68 100644 --- a/tools/perf/util/python.c +++ b/tools/perf/util/python.c @@ -93,6 +93,11 @@ int perf_pmu__scan_file(struct perf_pmu *pmu, const char *name, const char *fmt, return EOF; } +bool evsel__is_aux_event(const struct evsel *evsel __maybe_unused) +{ + return false; +} + /* * Add this one here not to drag util/metricgroup.c */ -- cgit v1.2.3-58-ga151 From 4bb311b29e82c795340a6e4a5db83d8ccbe2dc49 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sat, 11 Mar 2023 18:15:39 -0800 Subject: perf parse-events: Pass ownership of the group name Pass ownership of the group name rather than copying and freeing the original. This saves a memory allocation and copy. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Kim Phillips Cc: Leo Yan Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sean Christopherson Cc: Steinar H. Gunderson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230312021543.3060328-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/parse-events.c | 3 ++- tools/perf/util/parse-events.y | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 0336ff27c15f..1be454697d57 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -1761,6 +1761,7 @@ parse_events__set_leader_for_uncore_aliase(char *name, struct list_head *list, handled: ret = 1; + free(name); out: free(leaders); return ret; @@ -1786,7 +1787,7 @@ void parse_events__set_leader(char *name, struct list_head *list, leader = arch_evlist__leader(list); __perf_evlist__set_leader(list, &leader->core); - leader->group_name = name ? strdup(name) : NULL; + leader->group_name = name; list_move(&leader->core.node, list); } diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index be8c51770051..541b8dde2063 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -202,8 +202,8 @@ PE_NAME '{' events '}' struct list_head *list = $3; inc_group_count(list, _parse_state); + /* Takes ownership of $1. */ parse_events__set_leader($1, list, _parse_state); - free($1); $$ = list; } | -- cgit v1.2.3-58-ga151 From 347c2f0a0988c59c402148054ef54648853fa669 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sat, 11 Mar 2023 18:15:40 -0800 Subject: perf parse-events: Sort and group parsed events This change is intended to be a no-op for most current cases, the default sort order is the order the events were parsed. Where it varies is in how groups are handled. Previously an uncore and core event that are grouped would most often cause the group to be removed: ``` $ perf stat -e '{instructions,uncore_imc_free_running_0/data_total/}' -a sleep 1 WARNING: grouped events cpus do not match, disabling group: anon group { instructions, uncore_imc_free_running_0/data_total/ } ... ``` However, when wildcards are used the events should be re-sorted and re-grouped in parse_events__set_leader, but this currently fails for simple examples: ``` $ perf stat -e '{uncore_imc_free_running/data_read/,uncore_imc_free_running/data_write/}' -a sleep 1 Performance counter stats for 'system wide': MiB uncore_imc_free_running/data_read/ MiB uncore_imc_free_running/data_write/ 1.000996992 seconds time elapsed ``` A futher failure mode, fixed in this patch, is to force topdown events into a group. This change moves sorting the evsels in the evlist after parsing. It requires parsing to set up groups. First the evsels are sorted respecting the existing groupings and parse order, but also reordering to ensure evsels of the same PMU and group appear together. So that software and aux events respect groups, their pmu_name is taken from the group leader. The sorting is done with list_sort removing a memory allocation. After sorting a pass is done to correct the group leaders and for topdown events ensuring they have a group leader. This fixes the problems seen before: ``` $ perf stat -e '{uncore_imc_free_running/data_read/,uncore_imc_free_running/data_write/}' -a sleep 1 Performance counter stats for 'system wide': 727.42 MiB uncore_imc_free_running/data_read/ 81.84 MiB uncore_imc_free_running/data_write/ 1.000948615 seconds time elapsed ``` As well as making groups not fail for cases like: ``` $ perf stat -e '{imc_free_running_0/data_total/,imc_free_running_1/data_total/}' -a sleep 1 Performance counter stats for 'system wide': 256.47 MiB imc_free_running_0/data_total/ 256.48 MiB imc_free_running_1/data_total/ 1.001165442 seconds time elapsed ``` Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Kim Phillips Cc: Leo Yan Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sean Christopherson Cc: Steinar H. Gunderson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230312021543.3060328-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/x86/util/evlist.c | 39 +++---- tools/perf/util/evlist.h | 2 +- tools/perf/util/parse-events.c | 240 ++++++++++++++++++-------------------- tools/perf/util/parse-events.h | 3 +- tools/perf/util/parse-events.y | 4 +- 5 files changed, 136 insertions(+), 152 deletions(-) (limited to 'tools') diff --git a/tools/perf/arch/x86/util/evlist.c b/tools/perf/arch/x86/util/evlist.c index 8a7ae4162563..d4193479a364 100644 --- a/tools/perf/arch/x86/util/evlist.c +++ b/tools/perf/arch/x86/util/evlist.c @@ -65,29 +65,22 @@ int arch_evlist__add_default_attrs(struct evlist *evlist, return ___evlist__add_default_attrs(evlist, attrs, nr_attrs); } -struct evsel *arch_evlist__leader(struct list_head *list) +int arch_evlist__cmp(const struct evsel *lhs, const struct evsel *rhs) { - struct evsel *evsel, *first, *slots = NULL; - bool has_topdown = false; - - first = list_first_entry(list, struct evsel, core.node); - - if (!topdown_sys_has_perf_metrics()) - return first; - - /* If there is a slots event and a topdown event then the slots event comes first. */ - __evlist__for_each_entry(list, evsel) { - if (evsel->pmu_name && !strncmp(evsel->pmu_name, "cpu", 3) && evsel->name) { - if (strcasestr(evsel->name, "slots")) { - slots = evsel; - if (slots == first) - return first; - } - if (strcasestr(evsel->name, "topdown")) - has_topdown = true; - if (slots && has_topdown) - return slots; - } + if (topdown_sys_has_perf_metrics() && + (!lhs->pmu_name || !strncmp(lhs->pmu_name, "cpu", 3))) { + /* Ensure the topdown slots comes first. */ + if (strcasestr(lhs->name, "slots")) + return -1; + if (strcasestr(rhs->name, "slots")) + return 1; + /* Followed by topdown events. */ + if (strcasestr(lhs->name, "topdown") && !strcasestr(rhs->name, "topdown")) + return -1; + if (!strcasestr(lhs->name, "topdown") && strcasestr(rhs->name, "topdown")) + return 1; } - return first; + + /* Default ordering by insertion index. */ + return lhs->core.idx - rhs->core.idx; } diff --git a/tools/perf/util/evlist.h b/tools/perf/util/evlist.h index 01fa9d592c5a..d89d8f92802b 100644 --- a/tools/perf/util/evlist.h +++ b/tools/perf/util/evlist.h @@ -119,7 +119,7 @@ int arch_evlist__add_default_attrs(struct evlist *evlist, #define evlist__add_default_attrs(evlist, array) \ arch_evlist__add_default_attrs(evlist, array, ARRAY_SIZE(array)) -struct evsel *arch_evlist__leader(struct list_head *list); +int arch_evlist__cmp(const struct evsel *lhs, const struct evsel *rhs); int evlist__add_dummy(struct evlist *evlist); struct evsel *evlist__add_aux_dummy(struct evlist *evlist, bool system_wide); diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 1be454697d57..394ab23089d0 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include #include +#include #include #include #include @@ -1655,125 +1656,7 @@ int parse_events__modifier_group(struct list_head *list, return parse_events__modifier_event(list, event_mod, true); } -/* - * Check if the two uncore PMUs are from the same uncore block - * The format of the uncore PMU name is uncore_#blockname_#pmuidx - */ -static bool is_same_uncore_block(const char *pmu_name_a, const char *pmu_name_b) -{ - char *end_a, *end_b; - - end_a = strrchr(pmu_name_a, '_'); - end_b = strrchr(pmu_name_b, '_'); - - if (!end_a || !end_b) - return false; - - if ((end_a - pmu_name_a) != (end_b - pmu_name_b)) - return false; - - return (strncmp(pmu_name_a, pmu_name_b, end_a - pmu_name_a) == 0); -} - -static int -parse_events__set_leader_for_uncore_aliase(char *name, struct list_head *list, - struct parse_events_state *parse_state) -{ - struct evsel *evsel, *leader; - uintptr_t *leaders; - bool is_leader = true; - int i, nr_pmu = 0, total_members, ret = 0; - - leader = list_first_entry(list, struct evsel, core.node); - evsel = list_last_entry(list, struct evsel, core.node); - total_members = evsel->core.idx - leader->core.idx + 1; - - leaders = calloc(total_members, sizeof(uintptr_t)); - if (WARN_ON(!leaders)) - return 0; - - /* - * Going through the whole group and doing sanity check. - * All members must use alias, and be from the same uncore block. - * Also, storing the leader events in an array. - */ - __evlist__for_each_entry(list, evsel) { - - /* Only split the uncore group which members use alias */ - if (!evsel->use_uncore_alias) - goto out; - - /* The events must be from the same uncore block */ - if (!is_same_uncore_block(leader->pmu_name, evsel->pmu_name)) - goto out; - - if (!is_leader) - continue; - /* - * If the event's PMU name starts to repeat, it must be a new - * event. That can be used to distinguish the leader from - * other members, even they have the same event name. - */ - if ((leader != evsel) && - !strcmp(leader->pmu_name, evsel->pmu_name)) { - is_leader = false; - continue; - } - - /* Store the leader event for each PMU */ - leaders[nr_pmu++] = (uintptr_t) evsel; - } - - /* only one event alias */ - if (nr_pmu == total_members) { - parse_state->nr_groups--; - goto handled; - } - - /* - * An uncore event alias is a joint name which means the same event - * runs on all PMUs of a block. - * Perf doesn't support mixed events from different PMUs in the same - * group. The big group has to be split into multiple small groups - * which only include the events from the same PMU. - * - * Here the uncore event aliases must be from the same uncore block. - * The number of PMUs must be same for each alias. The number of new - * small groups equals to the number of PMUs. - * Setting the leader event for corresponding members in each group. - */ - i = 0; - __evlist__for_each_entry(list, evsel) { - if (i >= nr_pmu) - i = 0; - evsel__set_leader(evsel, (struct evsel *) leaders[i++]); - } - - /* The number of members and group name are same for each group */ - for (i = 0; i < nr_pmu; i++) { - evsel = (struct evsel *) leaders[i]; - evsel->core.nr_members = total_members / nr_pmu; - evsel->group_name = name ? strdup(name) : NULL; - } - - /* Take the new small groups into account */ - parse_state->nr_groups += nr_pmu - 1; - -handled: - ret = 1; - free(name); -out: - free(leaders); - return ret; -} - -__weak struct evsel *arch_evlist__leader(struct list_head *list) -{ - return list_first_entry(list, struct evsel, core.node); -} - -void parse_events__set_leader(char *name, struct list_head *list, - struct parse_events_state *parse_state) +void parse_events__set_leader(char *name, struct list_head *list) { struct evsel *leader; @@ -1782,13 +1665,9 @@ void parse_events__set_leader(char *name, struct list_head *list, return; } - if (parse_events__set_leader_for_uncore_aliase(name, list, parse_state)) - return; - - leader = arch_evlist__leader(list); + leader = list_first_entry(list, struct evsel, core.node); __perf_evlist__set_leader(list, &leader->core); leader->group_name = name; - list_move(&leader->core.node, list); } /* list_event is assumed to point to malloc'ed memory */ @@ -2245,6 +2124,117 @@ static int parse_events__with_hybrid_pmu(struct parse_events_state *parse_state, return ret; } +__weak int arch_evlist__cmp(const struct evsel *lhs, const struct evsel *rhs) +{ + /* Order by insertion index. */ + return lhs->core.idx - rhs->core.idx; +} + +static int evlist__cmp(void *state, const struct list_head *l, const struct list_head *r) +{ + const struct perf_evsel *lhs_core = container_of(l, struct perf_evsel, node); + const struct evsel *lhs = container_of(lhs_core, struct evsel, core); + const struct perf_evsel *rhs_core = container_of(r, struct perf_evsel, node); + const struct evsel *rhs = container_of(rhs_core, struct evsel, core); + int *leader_idx = state; + int lhs_leader_idx = *leader_idx, rhs_leader_idx = *leader_idx, ret; + const char *lhs_pmu_name, *rhs_pmu_name; + + /* + * First sort by grouping/leader. Read the leader idx only if the evsel + * is part of a group, as -1 indicates no group. + */ + if (lhs_core->leader != lhs_core || lhs_core->nr_members > 1) + lhs_leader_idx = lhs_core->leader->idx; + if (rhs_core->leader != rhs_core || rhs_core->nr_members > 1) + rhs_leader_idx = rhs_core->leader->idx; + + if (lhs_leader_idx != rhs_leader_idx) + return lhs_leader_idx - rhs_leader_idx; + + /* Group by PMU. Groups can't span PMUs. */ + lhs_pmu_name = evsel__group_pmu_name(lhs); + rhs_pmu_name = evsel__group_pmu_name(rhs); + ret = strcmp(lhs_pmu_name, rhs_pmu_name); + if (ret) + return ret; + + /* Architecture specific sorting. */ + return arch_evlist__cmp(lhs, rhs); +} + +static void parse_events__sort_events_and_fix_groups(struct list_head *list) +{ + int idx = -1; + struct evsel *pos, *cur_leader = NULL; + struct perf_evsel *cur_leaders_grp = NULL; + + /* + * Compute index to insert ungrouped events at. Place them where the + * first ungrouped event appears. + */ + list_for_each_entry(pos, list, core.node) { + const struct evsel *pos_leader = evsel__leader(pos); + + if (pos != pos_leader || pos->core.nr_members > 1) + continue; + + idx = pos->core.idx; + break; + } + + /* Sort events. */ + list_sort(&idx, list, evlist__cmp); + + /* + * Recompute groups, splitting for PMUs and adding groups for events + * that require them. + */ + idx = 0; + list_for_each_entry(pos, list, core.node) { + const struct evsel *pos_leader = evsel__leader(pos); + const char *pos_pmu_name = evsel__group_pmu_name(pos); + const char *cur_leader_pmu_name, *pos_leader_pmu_name; + bool force_grouped = arch_evsel__must_be_in_group(pos); + + /* Reset index and nr_members. */ + pos->core.idx = idx++; + pos->core.nr_members = 0; + + /* + * Set the group leader respecting the given groupings and that + * groups can't span PMUs. + */ + if (!cur_leader) + cur_leader = pos; + + cur_leader_pmu_name = evsel__group_pmu_name(cur_leader); + if ((cur_leaders_grp != pos->core.leader && !force_grouped) || + strcmp(cur_leader_pmu_name, pos_pmu_name)) { + /* Event is for a different group/PMU than last. */ + cur_leader = pos; + /* + * Remember the leader's group before it is overwritten, + * so that later events match as being in the same + * group. + */ + cur_leaders_grp = pos->core.leader; + } + pos_leader_pmu_name = evsel__group_pmu_name(pos_leader); + if (strcmp(pos_leader_pmu_name, pos_pmu_name) || force_grouped) { + /* + * Event's PMU differs from its leader's. Groups can't + * span PMUs, so update leader from the group/PMU + * tracker. + */ + evsel__set_leader(pos, cur_leader); + } + } + list_for_each_entry(pos, list, core.node) { + pos->core.leader->nr_members++; + } +} + int __parse_events(struct evlist *evlist, const char *str, struct parse_events_error *err, struct perf_pmu *fake_pmu) { @@ -2266,6 +2256,8 @@ int __parse_events(struct evlist *evlist, const char *str, return -1; } + parse_events__sort_events_and_fix_groups(&parse_state.list); + /* * Add list to the evlist even with errors to allow callers to clean up. */ diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index 428e72eaafcc..22fc11b0bd59 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -200,8 +200,7 @@ int parse_events_copy_term_list(struct list_head *old, enum perf_pmu_event_symbol_type perf_pmu__parse_check(const char *name); -void parse_events__set_leader(char *name, struct list_head *list, - struct parse_events_state *parse_state); +void parse_events__set_leader(char *name, struct list_head *list); void parse_events_update_lists(struct list_head *list_event, struct list_head *list_all); void parse_events_evlist_error(struct parse_events_state *parse_state, diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index 541b8dde2063..90d12f2bc8be 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -203,7 +203,7 @@ PE_NAME '{' events '}' inc_group_count(list, _parse_state); /* Takes ownership of $1. */ - parse_events__set_leader($1, list, _parse_state); + parse_events__set_leader($1, list); $$ = list; } | @@ -212,7 +212,7 @@ PE_NAME '{' events '}' struct list_head *list = $2; inc_group_count(list, _parse_state); - parse_events__set_leader(NULL, list, _parse_state); + parse_events__set_leader(NULL, list); $$ = list; } -- cgit v1.2.3-58-ga151 From e733f87e8c77751a00a538627eab1ac05e77cf0d Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sat, 11 Mar 2023 18:15:41 -0800 Subject: perf evsel: Remove use_uncore_alias This flag used to be used when regrouping uncore events in particular due to wildcard matches. This is now handled by sorting evlist and so the flag is redundant. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Kim Phillips Cc: Leo Yan Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sean Christopherson Cc: Steinar H. Gunderson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230312021543.3060328-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/evsel.c | 1 - tools/perf/util/evsel.h | 1 - tools/perf/util/parse-events.c | 12 +++--------- tools/perf/util/parse-events.h | 3 +-- tools/perf/util/parse-events.y | 11 +++++++---- 5 files changed, 11 insertions(+), 17 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index 3dda8a25cf50..a83d8cd5eb51 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -458,7 +458,6 @@ struct evsel *evsel__clone(struct evsel *orig) evsel->per_pkg = orig->per_pkg; evsel->percore = orig->percore; evsel->precise_max = orig->precise_max; - evsel->use_uncore_alias = orig->use_uncore_alias; evsel->is_libpfm_event = orig->is_libpfm_event; evsel->exclude_GH = orig->exclude_GH; diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h index d26745ca6147..c272c06565c0 100644 --- a/tools/perf/util/evsel.h +++ b/tools/perf/util/evsel.h @@ -89,7 +89,6 @@ struct evsel { bool per_pkg; bool percore; bool precise_max; - bool use_uncore_alias; bool is_libpfm_event; bool auto_merge_stats; bool collect_stat; diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 394ab23089d0..93a90651266f 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -1445,15 +1445,13 @@ static int parse_events__inside_hybrid_pmu(struct parse_events_state *parse_stat int parse_events_add_pmu(struct parse_events_state *parse_state, struct list_head *list, char *name, struct list_head *head_config, - bool auto_merge_stats, - bool use_alias) + bool auto_merge_stats) { struct perf_event_attr attr; struct perf_pmu_info info; struct perf_pmu *pmu; struct evsel *evsel; struct parse_events_error *err = parse_state->error; - bool use_uncore_alias; LIST_HEAD(config_terms); pmu = parse_state->fake_pmu ?: perf_pmu__find(name); @@ -1488,8 +1486,6 @@ int parse_events_add_pmu(struct parse_events_state *parse_state, memset(&attr, 0, sizeof(attr)); } - use_uncore_alias = (pmu->is_uncore && use_alias); - if (!head_config) { attr.type = pmu->type; evsel = __add_event(list, &parse_state->idx, &attr, @@ -1499,7 +1495,6 @@ int parse_events_add_pmu(struct parse_events_state *parse_state, /*cpu_list=*/NULL); if (evsel) { evsel->pmu_name = name ? strdup(name) : NULL; - evsel->use_uncore_alias = use_uncore_alias; return 0; } else { return -ENOMEM; @@ -1560,7 +1555,6 @@ int parse_events_add_pmu(struct parse_events_state *parse_state, evsel->use_config_name = true; evsel->pmu_name = name ? strdup(name) : NULL; - evsel->use_uncore_alias = use_uncore_alias; evsel->percore = config_term_percore(&evsel->config_terms); if (parse_state->fake_pmu) @@ -1622,7 +1616,7 @@ int parse_events_multi_pmu_add(struct parse_events_state *parse_state, parse_events_copy_term_list(head, &orig_head); if (!parse_events_add_pmu(parse_state, list, pmu->name, orig_head, - true, true)) { + /*auto_merge_stats=*/true)) { pr_debug("%s -> %s/%s/\n", str, pmu->name, alias->str); ok++; @@ -1634,7 +1628,7 @@ int parse_events_multi_pmu_add(struct parse_events_state *parse_state, if (parse_state->fake_pmu) { if (!parse_events_add_pmu(parse_state, list, str, head, - true, true)) { + /*auto_merge_stats=*/true)) { pr_debug("%s -> %s/%s/\n", str, "fake_pmu", str); ok++; } diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index 22fc11b0bd59..fdac44dc696b 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -183,8 +183,7 @@ int parse_events_add_breakpoint(struct list_head *list, int *idx, int parse_events_add_pmu(struct parse_events_state *parse_state, struct list_head *list, char *name, struct list_head *head_config, - bool auto_merge_stats, - bool use_alias); + bool auto_merge_stats); struct evsel *parse_events__add_event(int idx, struct perf_event_attr *attr, const char *name, const char *metric_id, diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index 90d12f2bc8be..f1b153c72d67 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -313,7 +313,7 @@ event_pmu_name opt_pmu_config list = alloc_list(); if (!list) CLEANUP_YYABORT; - if (parse_events_add_pmu(_parse_state, list, $1, $2, false, false)) { + if (parse_events_add_pmu(_parse_state, list, $1, $2, /*auto_merge_stats=*/false)) { struct perf_pmu *pmu = NULL; int ok = 0; @@ -330,8 +330,10 @@ event_pmu_name opt_pmu_config !perf_pmu__match(pattern, pmu->alias_name, $1)) { if (parse_events_copy_term_list(orig_terms, &terms)) CLEANUP_YYABORT; - if (!parse_events_add_pmu(_parse_state, list, pmu->name, terms, true, false)) + if (!parse_events_add_pmu(_parse_state, list, pmu->name, terms, + /*auto_merge_stats=*/true)) { ok++; + } parse_events_terms__delete(terms); } } @@ -407,7 +409,8 @@ PE_PMU_EVENT_FAKE sep_dc if (!list) YYABORT; - err = parse_events_add_pmu(_parse_state, list, $1, NULL, false, false); + err = parse_events_add_pmu(_parse_state, list, $1, /*head_config=*/NULL, + /*auto_merge_stats=*/false); free($1); if (err < 0) { free(list); @@ -425,7 +428,7 @@ PE_PMU_EVENT_FAKE opt_pmu_config if (!list) YYABORT; - err = parse_events_add_pmu(_parse_state, list, $1, $2, false, false); + err = parse_events_add_pmu(_parse_state, list, $1, $2, /*auto_merge_stats=*/false); free($1); parse_events_terms__delete($2); if (err < 0) { -- cgit v1.2.3-58-ga151 From 9d2dc632e09c0fe3a8a5890845bbd65b211fd662 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sat, 11 Mar 2023 18:15:42 -0800 Subject: perf evlist: Remove nr_groups Maintaining the number of groups during event parsing is problematic and since changing to sort/regroup events can only be computed by a linear pass over the evlist. As the value is generally only used in tests, rather than hold it in a variable compute it by passing over the evlist when necessary. This change highlights that libpfm's counting of groups with a single entry disagreed with regular event parsing. The libpfm tests are updated accordingly. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Kim Phillips Cc: Leo Yan Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sean Christopherson Cc: Steinar H. Gunderson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230312021543.3060328-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/lib/perf/evlist.c | 18 +++++++++++++++++- tools/lib/perf/include/internal/evlist.h | 1 - tools/lib/perf/include/perf/evlist.h | 1 + tools/perf/builtin-record.c | 2 +- tools/perf/builtin-report.c | 2 +- tools/perf/tests/bpf.c | 1 - tools/perf/tests/parse-events.c | 22 +++++++++++----------- tools/perf/tests/pfm.c | 12 ++++++------ tools/perf/util/evlist.c | 2 +- tools/perf/util/evlist.h | 6 ++++++ tools/perf/util/header.c | 3 +-- tools/perf/util/parse-events.c | 1 - tools/perf/util/parse-events.h | 1 - tools/perf/util/parse-events.y | 10 ---------- tools/perf/util/pfm.c | 1 - 15 files changed, 45 insertions(+), 38 deletions(-) (limited to 'tools') diff --git a/tools/lib/perf/evlist.c b/tools/lib/perf/evlist.c index 2d6121e89ccb..81e8b5fcd8ba 100644 --- a/tools/lib/perf/evlist.c +++ b/tools/lib/perf/evlist.c @@ -703,7 +703,23 @@ void perf_evlist__set_leader(struct perf_evlist *evlist) struct perf_evsel *first = list_entry(evlist->entries.next, struct perf_evsel, node); - evlist->nr_groups = evlist->nr_entries > 1 ? 1 : 0; __perf_evlist__set_leader(&evlist->entries, first); } } + +int perf_evlist__nr_groups(struct perf_evlist *evlist) +{ + struct perf_evsel *evsel; + int nr_groups = 0; + + perf_evlist__for_each_evsel(evlist, evsel) { + /* + * evsels by default have a nr_members of 1, and they are their + * own leader. If the nr_members is >1 then this is an + * indication of a group. + */ + if (evsel->leader == evsel && evsel->nr_members > 1) + nr_groups++; + } + return nr_groups; +} diff --git a/tools/lib/perf/include/internal/evlist.h b/tools/lib/perf/include/internal/evlist.h index 850f07070036..3339bc2f1765 100644 --- a/tools/lib/perf/include/internal/evlist.h +++ b/tools/lib/perf/include/internal/evlist.h @@ -17,7 +17,6 @@ struct perf_mmap_param; struct perf_evlist { struct list_head entries; int nr_entries; - int nr_groups; bool has_user_cpus; bool needs_map_propagation; /** diff --git a/tools/lib/perf/include/perf/evlist.h b/tools/lib/perf/include/perf/evlist.h index 9ca399d49bb4..e894b770779e 100644 --- a/tools/lib/perf/include/perf/evlist.h +++ b/tools/lib/perf/include/perf/evlist.h @@ -47,4 +47,5 @@ LIBPERF_API struct perf_mmap *perf_evlist__next_mmap(struct perf_evlist *evlist, (pos) = perf_evlist__next_mmap((evlist), (pos), overwrite)) LIBPERF_API void perf_evlist__set_leader(struct perf_evlist *evlist); +LIBPERF_API int perf_evlist__nr_groups(struct perf_evlist *evlist); #endif /* __LIBPERF_EVLIST_H */ diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c index fb8aab0cedd0..74388164a571 100644 --- a/tools/perf/builtin-record.c +++ b/tools/perf/builtin-record.c @@ -2474,7 +2474,7 @@ static int __cmd_record(struct record *rec, int argc, const char **argv) rec->tool.ordered_events = false; } - if (!rec->evlist->core.nr_groups) + if (evlist__nr_groups(rec->evlist) == 0) perf_header__clear_feat(&session->header, HEADER_GROUP_DESC); if (data->is_pipe) { diff --git a/tools/perf/builtin-report.c b/tools/perf/builtin-report.c index 2ee2ecca208e..6400615b5e98 100644 --- a/tools/perf/builtin-report.c +++ b/tools/perf/builtin-report.c @@ -1481,7 +1481,7 @@ repeat: setup_forced_leader(&report, session->evlist); - if (symbol_conf.group_sort_idx && !session->evlist->core.nr_groups) { + if (symbol_conf.group_sort_idx && evlist__nr_groups(session->evlist) == 0) { parse_options_usage(NULL, options, "group-sort-idx", 0); ret = -EINVAL; goto error; diff --git a/tools/perf/tests/bpf.c b/tools/perf/tests/bpf.c index ae9223f27cfb..8beb46066034 100644 --- a/tools/perf/tests/bpf.c +++ b/tools/perf/tests/bpf.c @@ -153,7 +153,6 @@ static int do_test(struct bpf_object *obj, int (*func)(void), } evlist__splice_list_tail(evlist, &parse_state.list); - evlist->core.nr_groups = parse_state.nr_groups; evlist__config(evlist, &opts, NULL); diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-events.c index 71a5cb343311..ffa6f0a90741 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -53,7 +53,7 @@ static int test__checkevent_tracepoint(struct evlist *evlist) struct evsel *evsel = evlist__first(evlist); TEST_ASSERT_VAL("wrong number of entries", 1 == evlist->core.nr_entries); - TEST_ASSERT_VAL("wrong number of groups", 0 == evlist->core.nr_groups); + TEST_ASSERT_VAL("wrong number of groups", 0 == evlist__nr_groups(evlist)); TEST_ASSERT_VAL("wrong type", PERF_TYPE_TRACEPOINT == evsel->core.attr.type); TEST_ASSERT_VAL("wrong sample_type", PERF_TP_SAMPLE_TYPE == evsel->core.attr.sample_type); @@ -66,7 +66,7 @@ static int test__checkevent_tracepoint_multi(struct evlist *evlist) struct evsel *evsel; TEST_ASSERT_VAL("wrong number of entries", evlist->core.nr_entries > 1); - TEST_ASSERT_VAL("wrong number of groups", 0 == evlist->core.nr_groups); + TEST_ASSERT_VAL("wrong number of groups", 0 == evlist__nr_groups(evlist)); evlist__for_each_entry(evlist, evsel) { TEST_ASSERT_VAL("wrong type", @@ -677,7 +677,7 @@ static int test__group1(struct evlist *evlist) struct evsel *evsel, *leader; TEST_ASSERT_VAL("wrong number of entries", 2 == evlist->core.nr_entries); - TEST_ASSERT_VAL("wrong number of groups", 1 == evlist->core.nr_groups); + TEST_ASSERT_VAL("wrong number of groups", 1 == evlist__nr_groups(evlist)); /* instructions:k */ evsel = leader = evlist__first(evlist); @@ -719,7 +719,7 @@ static int test__group2(struct evlist *evlist) struct evsel *evsel, *leader; TEST_ASSERT_VAL("wrong number of entries", 3 == evlist->core.nr_entries); - TEST_ASSERT_VAL("wrong number of groups", 1 == evlist->core.nr_groups); + TEST_ASSERT_VAL("wrong number of groups", 1 == evlist__nr_groups(evlist)); /* faults + :ku modifier */ evsel = leader = evlist__first(evlist); @@ -775,7 +775,7 @@ static int test__group3(struct evlist *evlist __maybe_unused) struct evsel *evsel, *leader; TEST_ASSERT_VAL("wrong number of entries", 5 == evlist->core.nr_entries); - TEST_ASSERT_VAL("wrong number of groups", 2 == evlist->core.nr_groups); + TEST_ASSERT_VAL("wrong number of groups", 2 == evlist__nr_groups(evlist)); /* group1 syscalls:sys_enter_openat:H */ evsel = leader = evlist__first(evlist); @@ -868,7 +868,7 @@ static int test__group4(struct evlist *evlist __maybe_unused) struct evsel *evsel, *leader; TEST_ASSERT_VAL("wrong number of entries", 2 == evlist->core.nr_entries); - TEST_ASSERT_VAL("wrong number of groups", 1 == evlist->core.nr_groups); + TEST_ASSERT_VAL("wrong number of groups", 1 == evlist__nr_groups(evlist)); /* cycles:u + p */ evsel = leader = evlist__first(evlist); @@ -912,7 +912,7 @@ static int test__group5(struct evlist *evlist __maybe_unused) struct evsel *evsel, *leader; TEST_ASSERT_VAL("wrong number of entries", 5 == evlist->core.nr_entries); - TEST_ASSERT_VAL("wrong number of groups", 2 == evlist->core.nr_groups); + TEST_ASSERT_VAL("wrong number of groups", 2 == evlist__nr_groups(evlist)); /* cycles + G */ evsel = leader = evlist__first(evlist); @@ -998,7 +998,7 @@ static int test__group_gh1(struct evlist *evlist) struct evsel *evsel, *leader; TEST_ASSERT_VAL("wrong number of entries", 2 == evlist->core.nr_entries); - TEST_ASSERT_VAL("wrong number of groups", 1 == evlist->core.nr_groups); + TEST_ASSERT_VAL("wrong number of groups", 1 == evlist__nr_groups(evlist)); /* cycles + :H group modifier */ evsel = leader = evlist__first(evlist); @@ -1038,7 +1038,7 @@ static int test__group_gh2(struct evlist *evlist) struct evsel *evsel, *leader; TEST_ASSERT_VAL("wrong number of entries", 2 == evlist->core.nr_entries); - TEST_ASSERT_VAL("wrong number of groups", 1 == evlist->core.nr_groups); + TEST_ASSERT_VAL("wrong number of groups", 1 == evlist__nr_groups(evlist)); /* cycles + :G group modifier */ evsel = leader = evlist__first(evlist); @@ -1078,7 +1078,7 @@ static int test__group_gh3(struct evlist *evlist) struct evsel *evsel, *leader; TEST_ASSERT_VAL("wrong number of entries", 2 == evlist->core.nr_entries); - TEST_ASSERT_VAL("wrong number of groups", 1 == evlist->core.nr_groups); + TEST_ASSERT_VAL("wrong number of groups", 1 == evlist__nr_groups(evlist)); /* cycles:G + :u group modifier */ evsel = leader = evlist__first(evlist); @@ -1118,7 +1118,7 @@ static int test__group_gh4(struct evlist *evlist) struct evsel *evsel, *leader; TEST_ASSERT_VAL("wrong number of entries", 2 == evlist->core.nr_entries); - TEST_ASSERT_VAL("wrong number of groups", 1 == evlist->core.nr_groups); + TEST_ASSERT_VAL("wrong number of groups", 1 == evlist__nr_groups(evlist)); /* cycles:G + :uG group modifier */ evsel = leader = evlist__first(evlist); diff --git a/tools/perf/tests/pfm.c b/tools/perf/tests/pfm.c index 71b76deb1f92..2e38dfa34b6c 100644 --- a/tools/perf/tests/pfm.c +++ b/tools/perf/tests/pfm.c @@ -76,7 +76,7 @@ static int test__pfm_events(struct test_suite *test __maybe_unused, count_pfm_events(&evlist->core), table[i].nr_events); TEST_ASSERT_EQUAL(table[i].events, - evlist->core.nr_groups, + evlist__nr_groups(evlist), 0); evlist__delete(evlist); @@ -103,22 +103,22 @@ static int test__pfm_group(struct test_suite *test __maybe_unused, { .events = "{instructions}", .nr_events = 1, - .nr_groups = 1, + .nr_groups = 0, }, { .events = "{instructions},{}", .nr_events = 1, - .nr_groups = 1, + .nr_groups = 0, }, { .events = "{},{instructions}", .nr_events = 1, - .nr_groups = 1, + .nr_groups = 0, }, { .events = "{instructions},{instructions}", .nr_events = 2, - .nr_groups = 2, + .nr_groups = 0, }, { .events = "{instructions,cycles},{instructions,cycles}", @@ -161,7 +161,7 @@ static int test__pfm_group(struct test_suite *test __maybe_unused, count_pfm_events(&evlist->core), table[i].nr_events); TEST_ASSERT_EQUAL(table[i].events, - evlist->core.nr_groups, + evlist__nr_groups(evlist), table[i].nr_groups); evlist__delete(evlist); diff --git a/tools/perf/util/evlist.c b/tools/perf/util/evlist.c index 9e4b2bb0e6fa..b74e12239aec 100644 --- a/tools/perf/util/evlist.c +++ b/tools/perf/util/evlist.c @@ -1777,7 +1777,7 @@ bool evlist__exclude_kernel(struct evlist *evlist) */ void evlist__force_leader(struct evlist *evlist) { - if (!evlist->core.nr_groups) { + if (evlist__nr_groups(evlist) == 0) { struct evsel *leader = evlist__first(evlist); evlist__set_leader(evlist); diff --git a/tools/perf/util/evlist.h b/tools/perf/util/evlist.h index d89d8f92802b..46cf402add93 100644 --- a/tools/perf/util/evlist.h +++ b/tools/perf/util/evlist.h @@ -9,6 +9,7 @@ #include #include #include +#include #include "events_stats.h" #include "evsel.h" #include @@ -255,6 +256,11 @@ static inline struct evsel *evlist__last(struct evlist *evlist) return container_of(evsel, struct evsel, core); } +static inline int evlist__nr_groups(struct evlist *evlist) +{ + return perf_evlist__nr_groups(&evlist->core); +} + int evlist__strerror_open(struct evlist *evlist, int err, char *buf, size_t size); int evlist__strerror_mmap(struct evlist *evlist, int err, char *buf, size_t size); diff --git a/tools/perf/util/header.c b/tools/perf/util/header.c index 404d816ca124..276870221ce0 100644 --- a/tools/perf/util/header.c +++ b/tools/perf/util/header.c @@ -786,7 +786,7 @@ static int write_pmu_mappings(struct feat_fd *ff, static int write_group_desc(struct feat_fd *ff, struct evlist *evlist) { - u32 nr_groups = evlist->core.nr_groups; + u32 nr_groups = evlist__nr_groups(evlist); struct evsel *evsel; int ret; @@ -2807,7 +2807,6 @@ static int process_group_desc(struct feat_fd *ff, void *data __maybe_unused) * Rebuild group relationship based on the group_desc */ session = container_of(ff->ph, struct perf_session, header); - session->evlist->core.nr_groups = nr_groups; i = nr = 0; evlist__for_each_entry(session->evlist, evsel) { diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 93a90651266f..9ec3c1dc81e0 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -2260,7 +2260,6 @@ int __parse_events(struct evlist *evlist, const char *str, if (!ret) { struct evsel *last; - evlist->core.nr_groups += parse_state.nr_groups; last = evlist__last(evlist); last->cmdline_group_boundary = true; diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index fdac44dc696b..767ad1729228 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -122,7 +122,6 @@ struct parse_events_error { struct parse_events_state { struct list_head list; int idx; - int nr_groups; struct parse_events_error *error; struct evlist *evlist; struct list_head *terms; diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index f1b153c72d67..3a04602d2982 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -49,14 +49,6 @@ static void free_list_evsel(struct list_head* list_evsel) free(list_evsel); } -static void inc_group_count(struct list_head *list, - struct parse_events_state *parse_state) -{ - /* Count groups only have more than 1 members */ - if (!list_is_last(list->next, list)) - parse_state->nr_groups++; -} - %} %token PE_START_EVENTS PE_START_TERMS @@ -201,7 +193,6 @@ PE_NAME '{' events '}' { struct list_head *list = $3; - inc_group_count(list, _parse_state); /* Takes ownership of $1. */ parse_events__set_leader($1, list); $$ = list; @@ -211,7 +202,6 @@ PE_NAME '{' events '}' { struct list_head *list = $2; - inc_group_count(list, _parse_state); parse_events__set_leader(NULL, list); $$ = list; } diff --git a/tools/perf/util/pfm.c b/tools/perf/util/pfm.c index b59ba825ddc9..6c11914c179f 100644 --- a/tools/perf/util/pfm.c +++ b/tools/perf/util/pfm.c @@ -112,7 +112,6 @@ int parse_libpfm_events_option(const struct option *opt, const char *str, "cannot close a non-existing event group\n"); goto error; } - evlist->core.nr_groups++; grp_leader = NULL; grp_evt = -1; } -- cgit v1.2.3-58-ga151 From a4c7d7c502b935f3a8324d954de78aecf6940897 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sat, 11 Mar 2023 18:15:43 -0800 Subject: perf parse-events: Warn when events are regrouped Use if an event is reordered or the number of groups increases to signal that regrouping has happened and warn about it. Disable the warning in the case wild card PMU names are used and for metrics. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Kim Phillips Cc: Leo Yan Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Sean Christopherson Cc: Steinar H. Gunderson Cc: Stephane Eranian Cc: Suzuki Poulouse Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230312021543.3060328-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/parse-events.c | 2 +- tools/perf/tests/pmu-events.c | 2 +- tools/perf/util/metricgroup.c | 3 ++- tools/perf/util/parse-events.c | 39 +++++++++++++++++++++++++++++---------- tools/perf/util/parse-events.h | 7 ++++--- tools/perf/util/parse-events.y | 1 + 6 files changed, 38 insertions(+), 16 deletions(-) (limited to 'tools') diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-events.c index ffa6f0a90741..b1c2f0a20306 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -2103,7 +2103,7 @@ static int test_event_fake_pmu(const char *str) parse_events_error__init(&err); perf_pmu__test_parse_init(); - ret = __parse_events(evlist, str, &err, &perf_pmu__fake); + ret = __parse_events(evlist, str, &err, &perf_pmu__fake, /*warn_if_reordered=*/true); if (ret) { pr_debug("failed to parse event '%s', err %d, str '%s'\n", str, ret, err.str); diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c index 6ccd413b5983..7f8e86452527 100644 --- a/tools/perf/tests/pmu-events.c +++ b/tools/perf/tests/pmu-events.c @@ -785,7 +785,7 @@ static int check_parse_id(const char *id, struct parse_events_error *error, */ perf_pmu__test_parse_init(); } - ret = __parse_events(evlist, dup, error, fake_pmu); + ret = __parse_events(evlist, dup, error, fake_pmu, /*warn_if_reordered=*/true); free(dup); evlist__delete(evlist); diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index de6dd527a2ba..5783f4c2d1ef 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -1441,7 +1441,8 @@ static int parse_ids(bool metric_no_merge, struct perf_pmu *fake_pmu, } pr_debug("Parsing metric events '%s'\n", events.buf); parse_events_error__init(&parse_error); - ret = __parse_events(parsed_evlist, events.buf, &parse_error, fake_pmu); + ret = __parse_events(parsed_evlist, events.buf, &parse_error, fake_pmu, + /*warn_if_reordered=*/false); if (ret) { parse_events_error__print(&parse_error, events.buf); goto err_out; diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 9ec3c1dc81e0..3b2e5bb3e852 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -2157,11 +2157,13 @@ static int evlist__cmp(void *state, const struct list_head *l, const struct list return arch_evlist__cmp(lhs, rhs); } -static void parse_events__sort_events_and_fix_groups(struct list_head *list) +static bool parse_events__sort_events_and_fix_groups(struct list_head *list) { - int idx = -1; + int idx = 0, unsorted_idx = -1; struct evsel *pos, *cur_leader = NULL; struct perf_evsel *cur_leaders_grp = NULL; + bool idx_changed = false; + int orig_num_leaders = 0, num_leaders = 0; /* * Compute index to insert ungrouped events at. Place them where the @@ -2170,15 +2172,22 @@ static void parse_events__sort_events_and_fix_groups(struct list_head *list) list_for_each_entry(pos, list, core.node) { const struct evsel *pos_leader = evsel__leader(pos); - if (pos != pos_leader || pos->core.nr_members > 1) - continue; + if (pos == pos_leader) + orig_num_leaders++; - idx = pos->core.idx; - break; + /* + * Ensure indexes are sequential, in particular for multiple + * event lists being merged. The indexes are used to detect when + * the user order is modified. + */ + pos->core.idx = idx++; + + if (unsorted_idx == -1 && pos == pos_leader && pos->core.nr_members < 2) + unsorted_idx = pos->core.idx; } /* Sort events. */ - list_sort(&idx, list, evlist__cmp); + list_sort(&unsorted_idx, list, evlist__cmp); /* * Recompute groups, splitting for PMUs and adding groups for events @@ -2192,6 +2201,8 @@ static void parse_events__sort_events_and_fix_groups(struct list_head *list) bool force_grouped = arch_evsel__must_be_in_group(pos); /* Reset index and nr_members. */ + if (pos->core.idx != idx) + idx_changed = true; pos->core.idx = idx++; pos->core.nr_members = 0; @@ -2225,12 +2236,18 @@ static void parse_events__sort_events_and_fix_groups(struct list_head *list) } } list_for_each_entry(pos, list, core.node) { - pos->core.leader->nr_members++; + struct evsel *pos_leader = evsel__leader(pos); + + if (pos == pos_leader) + num_leaders++; + pos_leader->core.nr_members++; } + return idx_changed || num_leaders != orig_num_leaders; } int __parse_events(struct evlist *evlist, const char *str, - struct parse_events_error *err, struct perf_pmu *fake_pmu) + struct parse_events_error *err, struct perf_pmu *fake_pmu, + bool warn_if_reordered) { struct parse_events_state parse_state = { .list = LIST_HEAD_INIT(parse_state.list), @@ -2250,7 +2267,9 @@ int __parse_events(struct evlist *evlist, const char *str, return -1; } - parse_events__sort_events_and_fix_groups(&parse_state.list); + if (parse_events__sort_events_and_fix_groups(&parse_state.list) && + warn_if_reordered && !parse_state.wild_card_pmus) + pr_warning("WARNING: events were regrouped to match PMUs\n"); /* * Add list to the evlist even with errors to allow callers to clean up. diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index 767ad1729228..46204c1a7916 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -26,13 +26,13 @@ int parse_events_option(const struct option *opt, const char *str, int unset); int parse_events_option_new_evlist(const struct option *opt, const char *str, int unset); __attribute__((nonnull(1, 2, 3))) int __parse_events(struct evlist *evlist, const char *str, struct parse_events_error *error, - struct perf_pmu *fake_pmu); + struct perf_pmu *fake_pmu, bool warn_if_reordered); -__attribute__((nonnull)) +__attribute__((nonnull(1, 2, 3))) static inline int parse_events(struct evlist *evlist, const char *str, struct parse_events_error *err) { - return __parse_events(evlist, str, err, NULL); + return __parse_events(evlist, str, err, /*fake_pmu=*/NULL, /*warn_if_reordered=*/true); } int parse_event(struct evlist *evlist, const char *str); @@ -128,6 +128,7 @@ struct parse_events_state { int stoken; struct perf_pmu *fake_pmu; char *hybrid_pmu_name; + bool wild_card_pmus; }; void parse_events__shrink_config_terms(void); diff --git a/tools/perf/util/parse-events.y b/tools/perf/util/parse-events.y index 3a04602d2982..4488443e506e 100644 --- a/tools/perf/util/parse-events.y +++ b/tools/perf/util/parse-events.y @@ -323,6 +323,7 @@ event_pmu_name opt_pmu_config if (!parse_events_add_pmu(_parse_state, list, pmu->name, terms, /*auto_merge_stats=*/true)) { ok++; + parse_state->wild_card_pmus = true; } parse_events_terms__delete(terms); } -- cgit v1.2.3-58-ga151 From 74395567a3011a07f51cf959be96c1eecb3e6df8 Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Mon, 13 Mar 2023 09:01:56 +0100 Subject: perf vendor events s390: Add common metrics Add 3 metrics for s390 machines: - Cycles per instruction: Amount of CPU cycles used per instructions, named cpi. - Problem state ratio: Ratio of instructions executed in problem state compared to total number of instructions, named prbstate. - Level one instruction and data cache misses per 100 instructions, named l1mp. For details about the formulas see this documentation: https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf Output after: # ./perf stat -M cpi -- dd if=/dev/zero of=/dev/null bs=1M count=10K 10240+0 records in 10240+0 records out 10737418240 bytes (11 GB, 10 GiB) copied, 1.30151 s, 8.2 GB/s Performance counter stats for 'dd if=/dev/zero of=/dev/null .....': 6,779,778,802 CPU_CYCLES # 1.96 cpi 3,461,975,090 INSTRUCTIONS 1.306873021 seconds time elapsed 0.001034000 seconds user 1.305677000 seconds sys # Signed-off-by: Thomas Richter Acked-by: Ian Rogers Acked-By: Sumanth Korikkar Cc: Heiko Carstens Cc: Sven Schnelle Cc: Vasily Gorbik Link: https://lore.kernel.org/r/20230313080201.2440201-1-tmricht@linux.ibm.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/s390/cf_z13/transaction.json | 15 +++++++++++++++ tools/perf/pmu-events/arch/s390/cf_z14/transaction.json | 15 +++++++++++++++ tools/perf/pmu-events/arch/s390/cf_z15/transaction.json | 15 +++++++++++++++ tools/perf/pmu-events/arch/s390/cf_z16/transaction.json | 15 +++++++++++++++ 4 files changed, 60 insertions(+) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json index 1a0034f79f73..86bf83b4504e 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json @@ -3,5 +3,20 @@ "BriefDescription": "Transaction count", "MetricName": "transaction", "MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL" + }, + { + "BriefDescription": "Cycles per Instruction", + "MetricName": "cpi", + "MetricExpr": "CPU_CYCLES / INSTRUCTIONS" + }, + { + "BriefDescription": "Problem State Instruction Ratio", + "MetricName": "prbstate", + "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100" + }, + { + "BriefDescription": "Level One Miss per 100 Instructions", + "MetricName": "l1mp", + "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100" } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json index 1a0034f79f73..86bf83b4504e 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json @@ -3,5 +3,20 @@ "BriefDescription": "Transaction count", "MetricName": "transaction", "MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL" + }, + { + "BriefDescription": "Cycles per Instruction", + "MetricName": "cpi", + "MetricExpr": "CPU_CYCLES / INSTRUCTIONS" + }, + { + "BriefDescription": "Problem State Instruction Ratio", + "MetricName": "prbstate", + "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100" + }, + { + "BriefDescription": "Level One Miss per 100 Instructions", + "MetricName": "l1mp", + "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100" } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json index 1a0034f79f73..86bf83b4504e 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json @@ -3,5 +3,20 @@ "BriefDescription": "Transaction count", "MetricName": "transaction", "MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL" + }, + { + "BriefDescription": "Cycles per Instruction", + "MetricName": "cpi", + "MetricExpr": "CPU_CYCLES / INSTRUCTIONS" + }, + { + "BriefDescription": "Problem State Instruction Ratio", + "MetricName": "prbstate", + "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100" + }, + { + "BriefDescription": "Level One Miss per 100 Instructions", + "MetricName": "l1mp", + "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100" } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json index 1a0034f79f73..86bf83b4504e 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json @@ -3,5 +3,20 @@ "BriefDescription": "Transaction count", "MetricName": "transaction", "MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL" + }, + { + "BriefDescription": "Cycles per Instruction", + "MetricName": "cpi", + "MetricExpr": "CPU_CYCLES / INSTRUCTIONS" + }, + { + "BriefDescription": "Problem State Instruction Ratio", + "MetricName": "prbstate", + "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100" + }, + { + "BriefDescription": "Level One Miss per 100 Instructions", + "MetricName": "l1mp", + "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100" } ] -- cgit v1.2.3-58-ga151 From f8a6cea4839bc8c76804b301dbb5522a6cacf6d5 Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Mon, 13 Mar 2023 09:01:57 +0100 Subject: perf vendor events s390: Add cache metrics for z16 Add metrics for s390 z16 - Percentage sourced from Level 2 cache - Percentage sourced from Level 3 on same chip cache - Percentage sourced from Level 4 Local cache on same book - Percentage sourced from Level 4 Remote cache on different book - Percentage sourced from memory For details about the formulas see this documentation: https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf Output after: # ./perf stat -M l4rp -- dd if=/dev/zero of=/dev/null bs=10M count=10K .... dd output deleted Performance counter stats for 'dd if=/dev/zero of=/dev/null bs=10M count=10K': 0 IDCW_OFF_DRAWER_CHIP_HIT # 0.00 l4rp 431,866 L1I_DIR_WRITES 2,395 IDCW_OFF_DRAWER_IV 0 ICW_OFF_DRAWER 0 IDCW_OFF_DRAWER_DRAWER_HIT 1,437 DCW_OFF_DRAWER 425,960,793 L1D_DIR_WRITES 12.165030699 seconds time elapsed 0.001037000 seconds user 12.162140000 seconds sys # Signed-off-by: Thomas Richter Acked-by: Ian Rogers Acked-By: Sumanth Korikkar Cc: Heiko Carstens Cc: Sven Schnelle Cc: Vasily Gorbik Link: https://lore.kernel.org/r/20230313080201.2440201-1-tmricht@linux.ibm.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/s390/cf_z16/transaction.json | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json index 86bf83b4504e..dde0735a7d22 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json @@ -18,5 +18,30 @@ "BriefDescription": "Level One Miss per 100 Instructions", "MetricName": "l1mp", "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 2 cache", + "MetricName": "l2p", + "MetricExpr": "((DCW_REQ + DCW_REQ_IV + ICW_REQ + ICW_REQ_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 3 on same chip cache", + "MetricName": "l3p", + "MetricExpr": "((DCW_REQ_CHIP_HIT + DCW_ON_CHIP + DCW_ON_CHIP_IV + DCW_ON_CHIP_CHIP_HIT + ICW_REQ_CHIP_HIT + ICW_ON_CHIP + ICW_ON_CHIP_IV + ICW_ON_CHIP_CHIP_HIT) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 4 Local cache on same book", + "MetricName": "l4lp", + "MetricExpr": "((DCW_REQ_DRAWER_HIT + DCW_ON_CHIP_DRAWER_HIT + DCW_ON_MODULE + DCW_ON_DRAWER + IDCW_ON_MODULE_IV + IDCW_ON_MODULE_CHIP_HIT + IDCW_ON_MODULE_DRAWER_HIT + IDCW_ON_DRAWER_IV + IDCW_ON_DRAWER_CHIP_HIT + IDCW_ON_DRAWER_DRAWER_HIT + ICW_REQ_DRAWER_HIT + ICW_ON_CHIP_DRAWER_HIT + ICW_ON_MODULE + ICW_ON_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 4 Remote cache on different book", + "MetricName": "l4rp", + "MetricExpr": "((DCW_OFF_DRAWER + IDCW_OFF_DRAWER_IV + IDCW_OFF_DRAWER_CHIP_HIT + IDCW_OFF_DRAWER_DRAWER_HIT + ICW_OFF_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from memory", + "MetricName": "memp", + "MetricExpr": "((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" } ] -- cgit v1.2.3-58-ga151 From d30baf2c376f3920e99d3c2c86a1a1b805a3c74c Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Wed, 8 Mar 2023 13:53:26 +0100 Subject: perf list: Add PMU pai_ext event description for IBM z16 Add the event description for the IBM z16 pai_ext PMU released with commit c432fefe8e6262bf ("s390/pai: Add support for PAI Extension 1 NNPA counters") The document SA22-7832-13 "z/Architecture Principles of Operation", published May, 2022, contains the description of the Processor Activity Instrumentation Facility and the NNPA counter set., See Pages 5-113 to 5-116 and chapter 26 for details. Signed-off-by: Thomas Richter Acked-by: Ian Rogers Acked-by: Sumanth Korikkar Cc: Heiko Carstens Cc: Sven Schnelle Cc: Vasily Gorbik Link: https://lore.kernel.org/r/20230308125326.2195613-1-tmricht@linux.ibm.com Signed-off-by: Arnaldo Carvalho de Melo --- .../perf/pmu-events/arch/s390/cf_z16/pai_ext.json | 178 +++++++++++++++++++++ tools/perf/pmu-events/jevents.py | 1 + 2 files changed, 179 insertions(+) create mode 100644 tools/perf/pmu-events/arch/s390/cf_z16/pai_ext.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/pai_ext.json b/tools/perf/pmu-events/arch/s390/cf_z16/pai_ext.json new file mode 100644 index 000000000000..7ccbded95dc9 --- /dev/null +++ b/tools/perf/pmu-events/arch/s390/cf_z16/pai_ext.json @@ -0,0 +1,178 @@ +[ + { + "Unit": "PAI-EXT", + "EventCode": "6144", + "EventName": "NNPA_ALL", + "BriefDescription": "NNPA ALL Sum of all non zero counters", + "PublicDescription": "Sum of all non zero NNPA (Neural Networks Processing Assist) counters" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6145", + "EventName": "NNPA_ADD", + "BriefDescription": "NNPA ADD function ending with CC=0" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6146", + "EventName": "NNPA_SUB", + "BriefDescription": "NNPA SUB function ending with CC=0" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6147", + "EventName": "NNPA_MUL", + "BriefDescription": "NNPA MUL function ending with CC=0" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6148", + "EventName": "NNPA_DIV", + "BriefDescription": "NNPA DIV function ending with CC=0" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6149", + "EventName": "NNPA_MIN", + "BriefDescription": "NNPA MIN function ending with CC=0" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6150", + "EventName": "NNPA_MAX", + "BriefDescription": "NNPA MAX function ending with CC=0" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6151", + "EventName": "NNPA_LOG", + "BriefDescription": "NNPA LOG function ending with CC=0" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6152", + "EventName": "NNPA_EXP", + "BriefDescription": "NNPA EXP function ending with CC=0" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6153", + "EventName": "NNPA_IBM_RESERVED_9", + "BriefDescription": "Reserved for IBM use", + "PublicDescription": "Reserved for IBM use" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6154", + "EventName": "NNPA_RELU", + "BriefDescription": "NNPA RELU function ending with CC=0" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6155", + "EventName": "NNPA_TANH", + "BriefDescription": "NNPA TANH function ending with CC=0" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6156", + "EventName": "NNPA_SIGMOID", + "BriefDescription": "NNPA SIGMOID function ending with CC=0" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6157", + "EventName": "NNPA_SOFTMAX", + "BriefDescription": "NNPA SOFTMAX function ending with CC=0" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6158", + "EventName": "NNPA_BATCHNORM", + "BriefDescription": "NNPA BATCHNORM function ending with CC=0" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6159", + "EventName": "NNPA_MAXPOOL2D", + "BriefDescription": "NNPA MAXPOOL2D function ending with CC=0" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6160", + "EventName": "NNPA_AVGPOOL2D", + "BriefDescription": "NNPA AVGPOOL2D function ending with CC=0" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6161", + "EventName": "NNPA_LSTMACT", + "BriefDescription": "NNPA LSTMACT function ending with CC=0" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6162", + "EventName": "NNPA_GRUACT", + "BriefDescription": "NNPA GRUACT function ending with CC=0" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6163", + "EventName": "NNPA_CONVOLUTION", + "BriefDescription": "NNPA CONVOLUTION function ending with CC=0" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6164", + "EventName": "NNPA_MATMUL_OP", + "BriefDescription": "NNPA MATMUL OP function ending with CC=0" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6165", + "EventName": "NNPA_MATMUL_OP_BCAST23", + "BriefDescription": "NNPA NNPA MATMUL OP BCAST23 function ending with CC=0" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6166", + "EventName": "NNPA_SMALLBATCH", + "BriefDescription": "NNPA SMALLBATCH OP function ending with CC=0", + "PublicDescription": "NNPA function with conditions as described in Common Operation" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6167", + "EventName": "NNPA_LARGEDIM", + "BriefDescription": "NNPA LARGEDIM OP function ending with CC=0", + "PublicDescription": "NNPA function with conditions as described in Common Operation" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6168", + "EventName": "NNPA_SMALLTENSOR", + "BriefDescription": "NNPA SMALLTENSOR OP function ending with CC=0", + "PublicDescription": "NNPA function with conditions as described in Common Operation" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6169", + "EventName": "NNPA_1MFRAME", + "BriefDescription": "NNPA 1MFRAME OP function ending with CC=0", + "PublicDescription": "NNPA function with conditions as described in Common Operation" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6170", + "EventName": "NNPA_2GFRAME", + "BriefDescription": "NNPA 2GFRAME OP function ending with CC=0", + "PublicDescription": "NNPA function with conditions as described in Common Operation" + }, + { + "Unit": "PAI-EXT", + "EventCode": "6171", + "EventName": "NNPA_ACCESSEXCEPT", + "BriefDescription": "NNPA ACCESSEXCEPT OP function ending with CC=0", + "PublicDescription": "NNPA function with conditions as described in Common Operation" + } +] diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index 40b9e626fc15..533071a014d7 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -260,6 +260,7 @@ class JsonEvent: 'CPU-M-CF': 'cpum_cf', 'CPU-M-SF': 'cpum_sf', 'PAI-CRYPTO' : 'pai_crypto', + 'PAI-EXT' : 'pai_ext', 'UPI LL': 'uncore_upi', 'hisi_sicl,cpa': 'hisi_sicl,cpa', 'hisi_sccl,ddrc': 'hisi_sccl,ddrc', -- cgit v1.2.3-58-ga151 From 5f968d289b8eae1017e8d465570b444a7021212c Mon Sep 17 00:00:00 2001 From: James Clark Date: Wed, 8 Mar 2023 09:48:42 +0000 Subject: perf cs-etm: Reduce verbosity of ts_source warning This is printed as a warning but it is normal behavior that users shouldn't be expected to do anything about. Reduce the warning level to debug3 so it's only seen in verbose mode to avoid confusion. Reviewed-by: Leo Yan Cc: Al Grant Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: John Garry Cc: Mark Rutland Cc: Mathieu Poirier Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Suzuki Poulouse Cc: Will Deacon Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230308094843.287093-1-james.clark@arm.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/arm/util/cs-etm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'tools') diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c index 7f71c8a237ff..59b50dd70330 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -694,8 +694,8 @@ static void cs_etm_save_etmv4_header(__u64 data[], struct auxtrace_record *itr, data[CS_ETMV4_TS_SOURCE] = (__u64) cs_etm_get_ro_signed(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TS_SOURCE]); else { - pr_warning("[%03d] pmu file 'ts_source' not found. Fallback to safe value (-1)\n", - cpu); + pr_debug3("[%03d] pmu file 'ts_source' not found. Fallback to safe value (-1)\n", + cpu); data[CS_ETMV4_TS_SOURCE] = (__u64) -1; } } @@ -729,8 +729,8 @@ static void cs_etm_save_ete_header(__u64 data[], struct auxtrace_record *itr, in data[CS_ETE_TS_SOURCE] = (__u64) cs_etm_get_ro_signed(cs_etm_pmu, cpu, metadata_ete_ro[CS_ETE_TS_SOURCE]); else { - pr_warning("[%03d] pmu file 'ts_source' not found. Fallback to safe value (-1)\n", - cpu); + pr_debug3("[%03d] pmu file 'ts_source' not found. Fallback to safe value (-1)\n", + cpu); data[CS_ETE_TS_SOURCE] = (__u64) -1; } } -- cgit v1.2.3-58-ga151 From e5af139715aaf17f25bc50638a7ca67973fce2af Mon Sep 17 00:00:00 2001 From: James Clark Date: Wed, 8 Mar 2023 09:48:43 +0000 Subject: perf cs-etm: Avoid printing warning in cs_etm_is_ete() check When checking for the presence of ETE, a register is read that may not be present on older kernels or if ETE isn't available. cs_etm_get_ro() will print a warning if it doesn't exist, so check for the existence first before accessing it. Reviewed-by: Leo Yan Signed-off-by: James Clark Cc: Al Grant Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: John Garry Cc: Mark Rutland Cc: Mathieu Poirier Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Suzuki Poulouse Cc: Will Deacon Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230308094843.287093-1-james.clark@arm.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/arm/util/cs-etm.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c index 59b50dd70330..86b61ad74f90 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -659,8 +659,12 @@ static bool cs_etm_is_ete(struct auxtrace_record *itr, int cpu) { struct cs_etm_recording *ptr = container_of(itr, struct cs_etm_recording, itr); struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu; - int trcdevarch = cs_etm_get_ro(cs_etm_pmu, cpu, metadata_ete_ro[CS_ETE_TRCDEVARCH]); + int trcdevarch; + if (!cs_etm_pmu_path_exists(cs_etm_pmu, cpu, metadata_ete_ro[CS_ETE_TRCDEVARCH])) + return false; + + trcdevarch = cs_etm_get_ro(cs_etm_pmu, cpu, metadata_ete_ro[CS_ETE_TRCDEVARCH]); /* * ETE if ARCHVER is 5 (ARCHVER is 4 for ETM) and ARCHPART is 0xA13. * See ETM_DEVARCH_ETE_ARCH in coresight-etm4x.h -- cgit v1.2.3-58-ga151 From 17535a33a9c1e4fb52f3db1d72a7ddbe4cea1a2e Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Tue, 7 Mar 2023 16:30:20 -0800 Subject: perf lock contention: Fix compiler builtin detection __has_builtin was passed the macro rather than the actual builtin feature. The builtin test isn't sufficient and a clang version test also needs to be performed. Fixes: 1bece1351c653c3d ("perf lock contention: Support old rw_semaphore type") Reviewed-by: Namhyung Kim Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Martin KaFai Lau Cc: Namhyung Kim Cc: Peter Zijlstra Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230308003020.3653271-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/bpf_skel/lock_contention.bpf.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/bpf_skel/lock_contention.bpf.c b/tools/perf/util/bpf_skel/lock_contention.bpf.c index e6007eaeda1a..141b36d13b19 100644 --- a/tools/perf/util/bpf_skel/lock_contention.bpf.c +++ b/tools/perf/util/bpf_skel/lock_contention.bpf.c @@ -182,7 +182,13 @@ static inline struct task_struct *get_lock_owner(__u64 lock, __u32 flags) struct mutex *mutex = (void *)lock; owner = BPF_CORE_READ(mutex, owner.counter); } else if (flags == LCB_F_READ || flags == LCB_F_WRITE) { -#if __has_builtin(bpf_core_type_matches) + /* + * Support for the BPF_TYPE_MATCHES argument to the + * __builtin_preserve_type_info builtin was added at some point during + * development of clang 15 and it's what is needed for + * bpf_core_type_matches. + */ +#if __has_builtin(__builtin_preserve_type_info) && __clang_major__ >= 15 if (bpf_core_type_matches(struct rw_semaphore___old)) { struct rw_semaphore___old *rwsem = (void *)lock; owner = (unsigned long)BPF_CORE_READ(rwsem, owner); -- cgit v1.2.3-58-ga151 From 56d5229471ee1634bd0eb029f1aa82a8d87c6fed Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 15 Jan 2023 17:01:13 -0800 Subject: tools build: Pass libbpf feature only if libbpf 1.0+ libbpf 1.0 represented a cleanup and stabilization of APIs. Simplify development by only passing the feature test if libbpf 1.0 is installed. Committer notes: Change 'make -C tools/perf build-test' so that the LIBBPF_DYNAMIC=1 test runs only if libbpf is >= 1.0. Signed-off-by: Ian Rogers Tested-by: Jiri Olsa Acked-by: Jiri Olsa Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andres Freund Cc: Andrii Nakryiko Cc: Christy Lee Cc: Ingo Molnar Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Quentin Monnet Cc: Roberto Sassu Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230116010115.490713-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/build/feature/test-libbpf.c | 4 ++++ tools/perf/tests/make | 7 ++++++- 2 files changed, 10 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/build/feature/test-libbpf.c b/tools/build/feature/test-libbpf.c index a508756cf4cc..cd9989f52119 100644 --- a/tools/build/feature/test-libbpf.c +++ b/tools/build/feature/test-libbpf.c @@ -1,6 +1,10 @@ // SPDX-License-Identifier: GPL-2.0 #include +#if !defined(LIBBPF_MAJOR_VERSION) || (LIBBPF_MAJOR_VERSION < 1) +#error At least libbpf 1.0 is required for Linux tools. +#endif + int main(void) { return bpf_object__open("test") ? 0 : -1; diff --git a/tools/perf/tests/make b/tools/perf/tests/make index 009d6efb673c..b4d64fdf4aef 100644 --- a/tools/perf/tests/make +++ b/tools/perf/tests/make @@ -150,7 +150,6 @@ run += make_no_libaudit run += make_no_libbionic run += make_no_auxtrace run += make_no_libbpf -run += make_libbpf_dynamic run += make_no_libbpf_DEBUG run += make_no_libcrypto run += make_no_sdt @@ -176,6 +175,12 @@ run += make_install_prefix_slash # run += make_install_pdf run += make_minimal +old_libbpf := $(shell echo "#include " | $(CC) -E -dM -x c -| egrep -q "define[[:space:]]+LIBBPF_MAJOR_VERSION[[:space:]]+0{1}") + +ifneq ($(old_libbpf),) +run += make_libbpf_dynamic +endif + ifneq ($(call has,ctags),) run += make_tags endif -- cgit v1.2.3-58-ga151 From 76a97cf2e169851ff8e3fd9d27028168eff81e37 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 15 Jan 2023 17:01:14 -0800 Subject: perf build: Remove libbpf pre-1.0 feature tests The feature tests were necessary for libbpf pre-1.0, but as the libbpf implies at least 1.0 we can remove these now. Committer notes: Modified tools/perf/Makefile.config to better reflect the reason for failure when the libbpf present is < 1.0 and LIBBPF_DYNAMIC=1 was asked for. Signed-off-by: Ian Rogers Acked-by: Jiri Olsa Tested-by: Jiri Olsa Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andres Freund Cc: Andrii Nakryiko Cc: Christy Lee Cc: Ingo Molnar Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Quentin Monnet Cc: Roberto Sassu Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230116010115.490713-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/build/feature/Makefile | 7 --- tools/build/feature/test-libbpf-bpf_map_create.c | 8 ---- .../feature/test-libbpf-bpf_object__next_map.c | 8 ---- .../feature/test-libbpf-bpf_object__next_program.c | 8 ---- tools/build/feature/test-libbpf-bpf_prog_load.c | 9 ---- .../feature/test-libbpf-bpf_program__set_insns.c | 8 ---- .../test-libbpf-btf__load_from_kernel_by_id.c | 8 ---- tools/build/feature/test-libbpf-btf__raw_data.c | 8 ---- tools/perf/Makefile.config | 50 +++++----------------- 9 files changed, 11 insertions(+), 103 deletions(-) delete mode 100644 tools/build/feature/test-libbpf-bpf_map_create.c delete mode 100644 tools/build/feature/test-libbpf-bpf_object__next_map.c delete mode 100644 tools/build/feature/test-libbpf-bpf_object__next_program.c delete mode 100644 tools/build/feature/test-libbpf-bpf_prog_load.c delete mode 100644 tools/build/feature/test-libbpf-bpf_program__set_insns.c delete mode 100644 tools/build/feature/test-libbpf-btf__load_from_kernel_by_id.c delete mode 100644 tools/build/feature/test-libbpf-btf__raw_data.c (limited to 'tools') diff --git a/tools/build/feature/Makefile b/tools/build/feature/Makefile index 690fe97be190..dc9323e01e42 100644 --- a/tools/build/feature/Makefile +++ b/tools/build/feature/Makefile @@ -58,13 +58,6 @@ FILES= \ test-lzma.bin \ test-bpf.bin \ test-libbpf.bin \ - test-libbpf-btf__load_from_kernel_by_id.bin \ - test-libbpf-bpf_prog_load.bin \ - test-libbpf-bpf_map_create.bin \ - test-libbpf-bpf_object__next_program.bin \ - test-libbpf-bpf_object__next_map.bin \ - test-libbpf-bpf_program__set_insns.bin \ - test-libbpf-btf__raw_data.bin \ test-get_cpuid.bin \ test-sdt.bin \ test-cxx.bin \ diff --git a/tools/build/feature/test-libbpf-bpf_map_create.c b/tools/build/feature/test-libbpf-bpf_map_create.c deleted file mode 100644 index b9f550e332c8..000000000000 --- a/tools/build/feature/test-libbpf-bpf_map_create.c +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include - -int main(void) -{ - return bpf_map_create(0 /* map_type */, NULL /* map_name */, 0, /* key_size */, - 0 /* value_size */, 0 /* max_entries */, NULL /* opts */); -} diff --git a/tools/build/feature/test-libbpf-bpf_object__next_map.c b/tools/build/feature/test-libbpf-bpf_object__next_map.c deleted file mode 100644 index 64adb519e97e..000000000000 --- a/tools/build/feature/test-libbpf-bpf_object__next_map.c +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include - -int main(void) -{ - bpf_object__next_map(NULL /* obj */, NULL /* prev */); - return 0; -} diff --git a/tools/build/feature/test-libbpf-bpf_object__next_program.c b/tools/build/feature/test-libbpf-bpf_object__next_program.c deleted file mode 100644 index 8bf4fd26b545..000000000000 --- a/tools/build/feature/test-libbpf-bpf_object__next_program.c +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include - -int main(void) -{ - bpf_object__next_program(NULL /* obj */, NULL /* prev */); - return 0; -} diff --git a/tools/build/feature/test-libbpf-bpf_prog_load.c b/tools/build/feature/test-libbpf-bpf_prog_load.c deleted file mode 100644 index 47f516d63ebc..000000000000 --- a/tools/build/feature/test-libbpf-bpf_prog_load.c +++ /dev/null @@ -1,9 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include - -int main(void) -{ - return bpf_prog_load(0 /* prog_type */, NULL /* prog_name */, - NULL /* license */, NULL /* insns */, - 0 /* insn_cnt */, NULL /* opts */); -} diff --git a/tools/build/feature/test-libbpf-bpf_program__set_insns.c b/tools/build/feature/test-libbpf-bpf_program__set_insns.c deleted file mode 100644 index f3b7f18c8f49..000000000000 --- a/tools/build/feature/test-libbpf-bpf_program__set_insns.c +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include - -int main(void) -{ - bpf_program__set_insns(NULL /* prog */, NULL /* new_insns */, 0 /* new_insn_cnt */); - return 0; -} diff --git a/tools/build/feature/test-libbpf-btf__load_from_kernel_by_id.c b/tools/build/feature/test-libbpf-btf__load_from_kernel_by_id.c deleted file mode 100644 index a17647f7d5a4..000000000000 --- a/tools/build/feature/test-libbpf-btf__load_from_kernel_by_id.c +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include - -int main(void) -{ - btf__load_from_kernel_by_id(20151128); - return 0; -} diff --git a/tools/build/feature/test-libbpf-btf__raw_data.c b/tools/build/feature/test-libbpf-btf__raw_data.c deleted file mode 100644 index 57da31dd7581..000000000000 --- a/tools/build/feature/test-libbpf-btf__raw_data.c +++ /dev/null @@ -1,8 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -#include - -int main(void) -{ - btf__raw_data(NULL /* btf_ro */, NULL /* size */); - return 0; -} diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index 3519a0139026..b715cd4f43f4 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -565,54 +565,26 @@ ifndef NO_LIBELF # detecting libbpf without LIBBPF_DYNAMIC, so make VF=1 shows libbpf detection status $(call feature_check,libbpf) + + # Feature test requires libbpf 1.0 so we can assume the following: + CFLAGS += -DHAVE_LIBBPF_BTF__LOAD_FROM_KERNEL_BY_ID + CFLAGS += -DHAVE_LIBBPF_BPF_PROG_LOAD + CFLAGS += -DHAVE_LIBBPF_BPF_OBJECT__NEXT_PROGRAM + CFLAGS += -DHAVE_LIBBPF_BPF_OBJECT__NEXT_MAP + CFLAGS += -DHAVE_LIBBPF_BPF_PROGRAM__SET_INSNS + CFLAGS += -DHAVE_LIBBPF_BTF__RAW_DATA + CFLAGS += -DHAVE_LIBBPF_BPF_MAP_CREATE + ifdef LIBBPF_DYNAMIC ifeq ($(feature-libbpf), 1) EXTLIBS += -lbpf $(call detected,CONFIG_LIBBPF_DYNAMIC) - - $(call feature_check,libbpf-btf__load_from_kernel_by_id) - ifeq ($(feature-libbpf-btf__load_from_kernel_by_id), 1) - CFLAGS += -DHAVE_LIBBPF_BTF__LOAD_FROM_KERNEL_BY_ID - endif - $(call feature_check,libbpf-bpf_prog_load) - ifeq ($(feature-libbpf-bpf_prog_load), 1) - CFLAGS += -DHAVE_LIBBPF_BPF_PROG_LOAD - endif - $(call feature_check,libbpf-bpf_object__next_program) - ifeq ($(feature-libbpf-bpf_object__next_program), 1) - CFLAGS += -DHAVE_LIBBPF_BPF_OBJECT__NEXT_PROGRAM - endif - $(call feature_check,libbpf-bpf_object__next_map) - ifeq ($(feature-libbpf-bpf_object__next_map), 1) - CFLAGS += -DHAVE_LIBBPF_BPF_OBJECT__NEXT_MAP - endif - $(call feature_check,libbpf-bpf_program__set_insns) - ifeq ($(feature-libbpf-bpf_program__set_insns), 1) - CFLAGS += -DHAVE_LIBBPF_BPF_PROGRAM__SET_INSNS - else - dummy := $(error Error: libbpf devel library needs to be >= 0.8.0 to build with LIBBPF_DYNAMIC, update or build statically with the version that comes with the kernel sources); - endif - $(call feature_check,libbpf-btf__raw_data) - ifeq ($(feature-libbpf-btf__raw_data), 1) - CFLAGS += -DHAVE_LIBBPF_BTF__RAW_DATA - endif - $(call feature_check,libbpf-bpf_map_create) - ifeq ($(feature-libbpf-bpf_map_create), 1) - CFLAGS += -DHAVE_LIBBPF_BPF_MAP_CREATE - endif else - dummy := $(error Error: No libbpf devel library found, please install libbpf-devel); + dummy := $(error Error: No libbpf devel library found or older than v1.0, please install/update libbpf-devel); endif else # Libbpf will be built as a static library from tools/lib/bpf. LIBBPF_STATIC := 1 - CFLAGS += -DHAVE_LIBBPF_BTF__LOAD_FROM_KERNEL_BY_ID - CFLAGS += -DHAVE_LIBBPF_BPF_PROG_LOAD - CFLAGS += -DHAVE_LIBBPF_BPF_OBJECT__NEXT_PROGRAM - CFLAGS += -DHAVE_LIBBPF_BPF_OBJECT__NEXT_MAP - CFLAGS += -DHAVE_LIBBPF_BPF_PROGRAM__SET_INSNS - CFLAGS += -DHAVE_LIBBPF_BTF__RAW_DATA - CFLAGS += -DHAVE_LIBBPF_BPF_MAP_CREATE endif endif -- cgit v1.2.3-58-ga151 From 6bebc06d544ddf7d4ca17ac3a1b94f4728a3cb7f Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 15 Jan 2023 17:01:15 -0800 Subject: perf bpf: Remove pre libbpf 1.0 conditional logic Tests are no longer applicable as libbpf 1.0 can be assumed. Signed-off-by: Ian Rogers Acked/Tested-by: Jiri Olsa Acked/Tested-by: Jiri Olsa Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andres Freund Cc: Andrii Nakryiko Cc: Christy Lee Cc: Ingo Molnar Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Quentin Monnet Cc: Roberto Sassu Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230116010115.490713-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Makefile.config | 9 ------ tools/perf/util/bpf-event.c | 66 ------------------------------------------- tools/perf/util/bpf-loader.c | 18 ------------ tools/perf/util/bpf_counter.c | 18 ------------ 4 files changed, 111 deletions(-) (limited to 'tools') diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index b715cd4f43f4..51a4e26bd030 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -566,15 +566,6 @@ ifndef NO_LIBELF # detecting libbpf without LIBBPF_DYNAMIC, so make VF=1 shows libbpf detection status $(call feature_check,libbpf) - # Feature test requires libbpf 1.0 so we can assume the following: - CFLAGS += -DHAVE_LIBBPF_BTF__LOAD_FROM_KERNEL_BY_ID - CFLAGS += -DHAVE_LIBBPF_BPF_PROG_LOAD - CFLAGS += -DHAVE_LIBBPF_BPF_OBJECT__NEXT_PROGRAM - CFLAGS += -DHAVE_LIBBPF_BPF_OBJECT__NEXT_MAP - CFLAGS += -DHAVE_LIBBPF_BPF_PROGRAM__SET_INSNS - CFLAGS += -DHAVE_LIBBPF_BTF__RAW_DATA - CFLAGS += -DHAVE_LIBBPF_BPF_MAP_CREATE - ifdef LIBBPF_DYNAMIC ifeq ($(feature-libbpf), 1) EXTLIBS += -lbpf diff --git a/tools/perf/util/bpf-event.c b/tools/perf/util/bpf-event.c index cc7c1f90cf62..025f331b3867 100644 --- a/tools/perf/util/bpf-event.c +++ b/tools/perf/util/bpf-event.c @@ -22,72 +22,6 @@ #include "record.h" #include "util/synthetic-events.h" -#ifndef HAVE_LIBBPF_BTF__LOAD_FROM_KERNEL_BY_ID -struct btf *btf__load_from_kernel_by_id(__u32 id) -{ - struct btf *btf; -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wdeprecated-declarations" - int err = btf__get_from_id(id, &btf); -#pragma GCC diagnostic pop - - return err ? ERR_PTR(err) : btf; -} -#endif - -#ifndef HAVE_LIBBPF_BPF_PROG_LOAD -LIBBPF_API int bpf_load_program(enum bpf_prog_type type, - const struct bpf_insn *insns, size_t insns_cnt, - const char *license, __u32 kern_version, - char *log_buf, size_t log_buf_sz); - -int bpf_prog_load(enum bpf_prog_type prog_type, - const char *prog_name __maybe_unused, - const char *license, - const struct bpf_insn *insns, size_t insn_cnt, - const struct bpf_prog_load_opts *opts) -{ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wdeprecated-declarations" - return bpf_load_program(prog_type, insns, insn_cnt, license, - opts->kern_version, opts->log_buf, opts->log_size); -#pragma GCC diagnostic pop -} -#endif - -#ifndef HAVE_LIBBPF_BPF_OBJECT__NEXT_PROGRAM -struct bpf_program * -bpf_object__next_program(const struct bpf_object *obj, struct bpf_program *prev) -{ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wdeprecated-declarations" - return bpf_program__next(prev, obj); -#pragma GCC diagnostic pop -} -#endif - -#ifndef HAVE_LIBBPF_BPF_OBJECT__NEXT_MAP -struct bpf_map * -bpf_object__next_map(const struct bpf_object *obj, const struct bpf_map *prev) -{ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wdeprecated-declarations" - return bpf_map__next(prev, obj); -#pragma GCC diagnostic pop -} -#endif - -#ifndef HAVE_LIBBPF_BTF__RAW_DATA -const void * -btf__raw_data(const struct btf *btf_ro, __u32 *size) -{ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wdeprecated-declarations" - return btf__get_raw_data(btf_ro, size); -#pragma GCC diagnostic pop -} -#endif - static int snprintf_hex(char *buf, size_t size, unsigned char *data, size_t len) { int ret = 0; diff --git a/tools/perf/util/bpf-loader.c b/tools/perf/util/bpf-loader.c index 6e9b06cf06ee..44cde27d6389 100644 --- a/tools/perf/util/bpf-loader.c +++ b/tools/perf/util/bpf-loader.c @@ -32,24 +32,6 @@ #include -#ifndef HAVE_LIBBPF_BPF_PROGRAM__SET_INSNS -int bpf_program__set_insns(struct bpf_program *prog __maybe_unused, - struct bpf_insn *new_insns __maybe_unused, size_t new_insn_cnt __maybe_unused) -{ - pr_err("%s: not support, update libbpf\n", __func__); - return -ENOTSUP; -} - -int libbpf_register_prog_handler(const char *sec __maybe_unused, - enum bpf_prog_type prog_type __maybe_unused, - enum bpf_attach_type exp_attach_type __maybe_unused, - const struct libbpf_prog_handler_opts *opts __maybe_unused) -{ - pr_err("%s: not support, update libbpf\n", __func__); - return -ENOTSUP; -} -#endif - /* temporarily disable libbpf deprecation warnings */ #pragma GCC diagnostic ignored "-Wdeprecated-declarations" diff --git a/tools/perf/util/bpf_counter.c b/tools/perf/util/bpf_counter.c index eeee899fcf34..aa78a15a6f0a 100644 --- a/tools/perf/util/bpf_counter.c +++ b/tools/perf/util/bpf_counter.c @@ -312,24 +312,6 @@ static bool bperf_attr_map_compatible(int attr_map_fd) (map_info.value_size == sizeof(struct perf_event_attr_map_entry)); } -#ifndef HAVE_LIBBPF_BPF_MAP_CREATE -LIBBPF_API int bpf_create_map(enum bpf_map_type map_type, int key_size, - int value_size, int max_entries, __u32 map_flags); -int -bpf_map_create(enum bpf_map_type map_type, - const char *map_name __maybe_unused, - __u32 key_size, - __u32 value_size, - __u32 max_entries, - const struct bpf_map_create_opts *opts __maybe_unused) -{ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wdeprecated-declarations" - return bpf_create_map(map_type, key_size, value_size, max_entries, 0); -#pragma GCC diagnostic pop -} -#endif - static int bperf_lock_attr_map(struct target *target) { char path[PATH_MAX]; -- cgit v1.2.3-58-ga151 From 7a9b223ca0761a7c7c72e569b86b84a907aa0f92 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 10 Mar 2023 22:57:41 -0800 Subject: perf build: Support python/perf.so testing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a build target to echo the python/perf.so's name from Makefile.perf. Use it in tests/make so the correct target is built and tested for. Fixes: caec54705adb73b0 ("perf build: Fix python/perf.so library's name") Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andres Freund Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Leo Yan Cc: Mark Rutland Cc: Martin Liška Cc: Namhyung Kim Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Pavithra Gurushankar Cc: Peter Zijlstra Cc: Quentin Monnet Cc: Roberto Sassu Cc: Stephane Eranian Cc: Tiezhu Yang Cc: Tom Rix Cc: Yang Jihong Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20230311065753.3012826-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Makefile.perf | 7 +++++-- tools/perf/tests/make | 5 +++-- 2 files changed, 8 insertions(+), 4 deletions(-) (limited to 'tools') diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf index bac9272682b7..2fcee585b225 100644 --- a/tools/perf/Makefile.perf +++ b/tools/perf/Makefile.perf @@ -647,13 +647,16 @@ all: shell_compatibility_test $(ALL_PROGRAMS) $(LANG_BINDINGS) $(OTHER_PROGRAMS) # Create python binding output directory if not already present _dummy := $(shell [ -d '$(OUTPUT)python' ] || mkdir -p '$(OUTPUT)python') -$(OUTPUT)python/perf$(PYTHON_EXTENSION_SUFFIX): $(PYTHON_EXT_SRCS) $(PYTHON_EXT_DEPS) $(LIBPERF) +$(OUTPUT)python/perf$(PYTHON_EXTENSION_SUFFIX): $(PYTHON_EXT_SRCS) $(PYTHON_EXT_DEPS) $(LIBPERF) $(LIBSUBCMD) $(QUIET_GEN)LDSHARED="$(CC) -pthread -shared" \ CFLAGS='$(CFLAGS)' LDFLAGS='$(LDFLAGS)' \ $(PYTHON_WORD) util/setup.py \ --quiet build_ext; \ cp $(PYTHON_EXTBUILD_LIB)perf*.so $(OUTPUT)python/ +python_perf_target: + @echo "Target is: $(OUTPUT)python/perf$(PYTHON_EXTENSION_SUFFIX)" + please_set_SHELL_PATH_to_a_more_modern_shell: $(Q)$$(:) @@ -1152,7 +1155,7 @@ FORCE: .PHONY: all install clean config-clean strip install-gtk .PHONY: shell_compatibility_test please_set_SHELL_PATH_to_a_more_modern_shell .PHONY: .FORCE-PERF-VERSION-FILE TAGS tags cscope FORCE prepare -.PHONY: archheaders +.PHONY: archheaders python_perf_target endif # force_fixdep diff --git a/tools/perf/tests/make b/tools/perf/tests/make index b4d64fdf4aef..f9f826c0df47 100644 --- a/tools/perf/tests/make +++ b/tools/perf/tests/make @@ -62,10 +62,11 @@ lib = lib endif has = $(shell which $1 2>/dev/null) +python_perf_so := $(shell $(MAKE) python_perf_target|grep "Target is:"|awk '{print $$3}') # standard single make variable specified make_clean_all := clean all -make_python_perf_so := python/perf.so +make_python_perf_so := $(python_perf_so) make_debug := DEBUG=1 make_no_libperl := NO_LIBPERL=1 make_no_libpython := NO_LIBPYTHON=1 @@ -209,7 +210,7 @@ test_make_doc := $(test_ok) test_make_help_O := $(test_ok) test_make_doc_O := $(test_ok) -test_make_python_perf_so := test -f $(PERF_O)/python/perf.so +test_make_python_perf_so := test -f $(PERF_O)/$(python_perf_so) test_make_perf_o := test -f $(PERF_O)/perf.o test_make_util_map_o := test -f $(PERF_O)/util/map.o -- cgit v1.2.3-58-ga151 From a980755beb5aca9002e1c95ba519b83a44242b5b Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 10 Mar 2023 22:57:42 -0800 Subject: perf build: Make BUILD_BPF_SKEL default, rename to NO_BPF_SKEL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit BPF skeleton support is now key to a number of perf features. Rather than making it so that BPF support must be enabled for the build, make this the default and error if the build lacks a clang and libbpf that are sufficient. To avoid the error and build without BPF skeletons the NO_BPF_SKEL=1 flag can be used. Add a build-options flag to 'perf version' to enable detection of the BPF skeleton support and use this in the offcpu shell test. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andres Freund Cc: Ingo Molnar Cc: Jiri Olsa Cc: Leo Yan Cc: Mark Rutland Cc: Martin Liška Cc: Namhyung Kim Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Pavithra Gurushankar Cc: Peter Zijlstra Cc: Quentin Monnet Cc: Roberto Sassu Cc: Stephane Eranian Cc: Tiezhu Yang Cc: Tom Rix Cc: Yang Jihong Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20230311065753.3012826-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Makefile.config | 19 ++++++++++++------- tools/perf/Makefile.perf | 8 ++++---- tools/perf/builtin-lock.c | 2 +- tools/perf/builtin-record.c | 2 +- tools/perf/builtin-version.c | 1 + tools/perf/tests/shell/record_offcpu.sh | 2 +- 6 files changed, 20 insertions(+), 14 deletions(-) (limited to 'tools') diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index 51a4e26bd030..318af7657225 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -415,6 +415,7 @@ ifdef NO_LIBELF NO_LIBUNWIND := 1 NO_LIBDW_DWARF_UNWIND := 1 NO_LIBBPF := 1 + NO_BPF_SKEL := 1 NO_JVMTI := 1 else ifeq ($(feature-libelf), 0) @@ -662,18 +663,22 @@ ifndef NO_LIBBPF msg := $(warning BPF API too old. Please install recent kernel headers. BPF support in 'perf record' is disabled.) NO_LIBBPF := 1 endif +else + NO_BPF_SKEL := 1 endif -ifdef BUILD_BPF_SKEL +ifndef NO_BPF_SKEL $(call feature_check,clang-bpf-co-re) ifeq ($(feature-clang-bpf-co-re), 0) - dummy := $(error Error: clang too old/not installed. Please install recent clang to build with BUILD_BPF_SKEL) - endif - ifeq ($(filter -DHAVE_LIBBPF_SUPPORT, $(CFLAGS)),) - dummy := $(error Error: BPF skeleton support requires libbpf) + dummy := $(error: ERROR: BPF skeletons unsupported. clang too old/not installed or build with NO_BPF_SKEL=1.) + else + ifeq ($(filter -DHAVE_LIBBPF_SUPPORT, $(CFLAGS)),) + dummy := $(error: ERROR: BPF skeletons unsupported. BPF skeleton support requires libbpf or build with NO_BPF_SKEL=1.) + else + $(call detected,CONFIG_PERF_BPF_SKEL) + CFLAGS += -DHAVE_BPF_SKEL + endif endif - $(call detected,CONFIG_PERF_BPF_SKEL) - CFLAGS += -DHAVE_BPF_SKEL endif dwarf-post-unwind := 1 diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf index 2fcee585b225..283ee4f56234 100644 --- a/tools/perf/Makefile.perf +++ b/tools/perf/Makefile.perf @@ -126,7 +126,7 @@ include ../scripts/utilities.mak # # Define NO_LIBDEBUGINFOD if you do not want support debuginfod # -# Define BUILD_BPF_SKEL to enable BPF skeletons +# Define NO_BPF_SKEL to disable BPF skeletons # # As per kernel Makefile, avoid funny character set dependencies @@ -1055,7 +1055,7 @@ SKELETONS += $(SKEL_OUT)/kwork_trace.skel.h $(SKEL_TMP_OUT) $(LIBAPI_OUTPUT) $(LIBBPF_OUTPUT) $(LIBPERF_OUTPUT) $(LIBSUBCMD_OUTPUT) $(LIBSYMBOL_OUTPUT): $(Q)$(MKDIR) -p $@ -ifdef BUILD_BPF_SKEL +ifndef NO_BPF_SKEL BPFTOOL := $(SKEL_TMP_OUT)/bootstrap/bpftool BPF_INCLUDE := -I$(SKEL_TMP_OUT)/.. -I$(LIBBPF_INCLUDE) @@ -1088,11 +1088,11 @@ bpf-skel: $(SKELETONS) .PRECIOUS: $(SKEL_TMP_OUT)/%.bpf.o -else # BUILD_BPF_SKEL +else # NO_BPF_SKEL bpf-skel: -endif # BUILD_BPF_SKEL +endif # NO_BPF_SKEL bpf-skel-clean: $(call QUIET_CLEAN, bpf-skel) $(RM) -r $(SKEL_TMP_OUT) $(SKELETONS) diff --git a/tools/perf/builtin-lock.c b/tools/perf/builtin-lock.c index 054997edd98b..240d49a85524 100644 --- a/tools/perf/builtin-lock.c +++ b/tools/perf/builtin-lock.c @@ -2371,7 +2371,7 @@ int cmd_lock(int argc, const char **argv) #ifndef HAVE_BPF_SKEL set_option_nobuild(contention_options, 'b', "use-bpf", - "no BUILD_BPF_SKEL=1", false); + "NO_BPF_SKEL=1", false); #endif if (argc) { argc = parse_options(argc, argv, contention_options, diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c index 74388164a571..33ebe42b025e 100644 --- a/tools/perf/builtin-record.c +++ b/tools/perf/builtin-record.c @@ -3971,7 +3971,7 @@ int cmd_record(int argc, const char **argv) #ifndef HAVE_BPF_SKEL # define set_nobuild(s, l, m, c) set_option_nobuild(record_options, s, l, m, c) - set_nobuild('\0', "off-cpu", "no BUILD_BPF_SKEL=1", true); + set_nobuild('\0', "off-cpu", "NO_BPF_SKEL=1", true); # undef set_nobuild #endif diff --git a/tools/perf/builtin-version.c b/tools/perf/builtin-version.c index a886929ec6e5..0d9cda238c07 100644 --- a/tools/perf/builtin-version.c +++ b/tools/perf/builtin-version.c @@ -83,6 +83,7 @@ static void library_status(void) STATUS(HAVE_ZSTD_SUPPORT, zstd); STATUS(HAVE_LIBPFM, libpfm4); STATUS(HAVE_LIBTRACEEVENT, libtraceevent); + STATUS(HAVE_BPF_SKEL, BPF skeletons); } int cmd_version(int argc, const char **argv) diff --git a/tools/perf/tests/shell/record_offcpu.sh b/tools/perf/tests/shell/record_offcpu.sh index e01973d4e0fb..24f81ff85793 100755 --- a/tools/perf/tests/shell/record_offcpu.sh +++ b/tools/perf/tests/shell/record_offcpu.sh @@ -28,7 +28,7 @@ test_offcpu_priv() { err=2 return fi - if perf record --off-cpu -o /dev/null --quiet true 2>&1 | grep BUILD_BPF_SKEL + if perf version --build-options 2>&1 | grep HAVE_BPF_SKEL | grep -q OFF then echo "off-cpu test [Skipped missing BPF support]" err=2 -- cgit v1.2.3-58-ga151 From 7bafa03f21a6eebfce306ce32635c3adc13815f6 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 10 Mar 2023 22:57:43 -0800 Subject: perf build: Remove unused HAVE_GLIBC_SUPPORT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit HAVE_GLIBC_SUPPORT is only used in `perf version --build-options` but doesn't control any behavior. Remove from the build to simplify it. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andres Freund Cc: Ingo Molnar Cc: Jiri Olsa Cc: Leo Yan Cc: Mark Rutland Cc: Martin Liška Cc: Namhyung Kim Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Pavithra Gurushankar Cc: Peter Zijlstra Cc: Quentin Monnet Cc: Roberto Sassu Cc: Stephane Eranian Cc: Tiezhu Yang Cc: Tom Rix Cc: Yang Jihong Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20230311065753.3012826-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Makefile.config | 4 ---- tools/perf/builtin-version.c | 1 - 2 files changed, 5 deletions(-) (limited to 'tools') diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index 318af7657225..eb7a3aa58639 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -476,10 +476,6 @@ else endif # libelf support endif # NO_LIBELF -ifeq ($(feature-glibc), 1) - CFLAGS += -DHAVE_GLIBC_SUPPORT -endif - ifeq ($(feature-libaio), 1) ifndef NO_AIO CFLAGS += -DHAVE_AIO_SUPPORT diff --git a/tools/perf/builtin-version.c b/tools/perf/builtin-version.c index 0d9cda238c07..c5d03a11e565 100644 --- a/tools/perf/builtin-version.c +++ b/tools/perf/builtin-version.c @@ -59,7 +59,6 @@ static void library_status(void) { STATUS(HAVE_DWARF_SUPPORT, dwarf); STATUS(HAVE_DWARF_GETLOCATIONS_SUPPORT, dwarf_getlocations); - STATUS(HAVE_GLIBC_SUPPORT, glibc); #ifndef HAVE_SYSCALL_TABLE_SUPPORT STATUS(HAVE_LIBAUDIT_SUPPORT, libaudit); #endif -- cgit v1.2.3-58-ga151 From 0cd3142f6b238981ed4855217cfa4ee0aa899181 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 10 Mar 2023 22:57:45 -0800 Subject: perf util: Remove weak sched_getcpu MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit sched_getcpu may not be present and so a feature test and definition exist to workaround this in the build. The feature test is used to define HAVE_SCHED_GETCPU_SUPPORT and so this is sufficient to know whether the local sched_getcpu is needed and a weak symbol can be avoided. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andres Freund Cc: Ingo Molnar Cc: Jiri Olsa Cc: Leo Yan Cc: Mark Rutland Cc: Martin Liška Cc: Namhyung Kim Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Pavithra Gurushankar Cc: Peter Zijlstra Cc: Quentin Monnet Cc: Roberto Sassu Cc: Stephane Eranian Cc: Tiezhu Yang Cc: Tom Rix Cc: Yang Jihong Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20230311065753.3012826-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/cloexec.c | 13 ------------- tools/perf/util/util.c | 16 ++++++++++++++++ 2 files changed, 16 insertions(+), 13 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/cloexec.c b/tools/perf/util/cloexec.c index fa8248aadb59..8830604c3a8d 100644 --- a/tools/perf/util/cloexec.c +++ b/tools/perf/util/cloexec.c @@ -13,19 +13,6 @@ static unsigned long flag = PERF_FLAG_FD_CLOEXEC; -int __weak sched_getcpu(void) -{ -#ifdef __NR_getcpu - unsigned cpu; - int err = syscall(__NR_getcpu, &cpu, NULL, NULL); - if (!err) - return cpu; -#else - errno = ENOSYS; -#endif - return -1; -} - static int perf_flag_probe(void) { /* use 'safest' configuration as used in evsel__fallback() */ diff --git a/tools/perf/util/util.c b/tools/perf/util/util.c index 391c1e928bd7..b356c9f7f0c3 100644 --- a/tools/perf/util/util.c +++ b/tools/perf/util/util.c @@ -533,3 +533,19 @@ int do_realloc_array_as_needed(void **arr, size_t *arr_sz, size_t x, size_t msz, *arr_sz = new_sz; return 0; } + +#ifndef HAVE_SCHED_GETCPU_SUPPORT +int sched_getcpu(void) +{ +#ifdef __NR_getcpu + unsigned int cpu; + int err = syscall(__NR_getcpu, &cpu, NULL, NULL); + + if (!err) + return cpu; +#else + errno = ENOSYS; +#endif + return -1; +} +#endif -- cgit v1.2.3-58-ga151 From 175f9315f76345e88e3abdc947c1e0030ab99da3 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 10 Mar 2023 22:57:46 -0800 Subject: perf build: Error if jevents won't work and NO_JEVENTS=1 isn't set MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rather than disabling jevents if a sufficient python isn't present error in the build. This avoids the build progressing but the binary being degraded. The build can still succeed by specifying NO_JEVENTS=1 to the build and this is conveyed in the error message. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andres Freund Cc: Ingo Molnar Cc: Jiri Olsa Cc: Leo Yan Cc: Mark Rutland Cc: Martin Liška Cc: Namhyung Kim Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Pavithra Gurushankar Cc: Peter Zijlstra Cc: Quentin Monnet Cc: Roberto Sassu Cc: Stephane Eranian Cc: Tiezhu Yang Cc: Tom Rix Cc: Yang Jihong Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20230311065753.3012826-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Makefile.config | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'tools') diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index eb7a3aa58639..f882ce2e25b3 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -880,14 +880,12 @@ endif ifneq ($(NO_JEVENTS),1) NO_JEVENTS := 0 ifndef PYTHON - $(warning No python interpreter disabling jevent generation) - NO_JEVENTS := 1 + $(error ERROR: No python interpreter needed for jevents generation. Install python or build with NO_JEVENTS=1.) else # jevents.py uses f-strings present in Python 3.6 released in Dec. 2016. JEVENTS_PYTHON_GOOD := $(shell $(PYTHON) -c 'import sys;print("1" if(sys.version_info.major >= 3 and sys.version_info.minor >= 6) else "0")' 2> /dev/null) ifneq ($(JEVENTS_PYTHON_GOOD), 1) - $(warning Python interpreter too old (older than 3.6) disabling jevent generation) - NO_JEVENTS := 1 + $(error ERROR: Python interpreter needed for jevents generation too old (older than 3.6). Install a newer python or build with NO_JEVENTS=1.) endif endif endif -- cgit v1.2.3-58-ga151 From dd317df072071903031ab5f91b4823858445c4a0 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 10 Mar 2023 22:57:47 -0800 Subject: perf build: Make binutil libraries opt in MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit binutils is GPLv3 so distributions cannot ship perf linked against libbfd and libiberty as the licenses are incompatible. Rather than defaulting the build to opting in to libbfd and libiberty support and opting out via NO_LIBBFD=1 and NO_DEMANGLE=1, make building against the libraries optional and enabled with BUILD_NONDISTRO=1. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andres Freund Cc: Ingo Molnar Cc: Jiri Olsa Cc: Leo Yan Cc: Mark Rutland Cc: Martin Liška Cc: Namhyung Kim Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Pavithra Gurushankar Cc: Peter Zijlstra Cc: Quentin Monnet Cc: Roberto Sassu Cc: Stephane Eranian Cc: Tiezhu Yang Cc: Tom Rix Cc: Yang Jihong Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20230311065753.3012826-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Makefile.config | 25 ++++++++++--------------- tools/perf/Makefile.perf | 2 ++ tools/perf/tests/make | 2 ++ 3 files changed, 14 insertions(+), 15 deletions(-) (limited to 'tools') diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index f882ce2e25b3..c4ae70c643b9 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -890,7 +890,7 @@ ifneq ($(NO_JEVENTS),1) endif endif -ifndef NO_LIBBFD +ifdef BUILD_NONDISTRO ifeq ($(feature-libbfd), 1) EXTLIBS += -lbfd -lopcodes else @@ -913,6 +913,7 @@ ifndef NO_LIBBFD $(call feature_check,disassembler-init-styled) endif + CFLAGS += -DHAVE_LIBBFD_SUPPORT ifeq ($(feature-libbfd-buildid), 1) CFLAGS += -DHAVE_LIBBFD_BUILDID_SUPPORT else @@ -923,32 +924,26 @@ endif ifdef NO_DEMANGLE CFLAGS += -DNO_DEMANGLE else - ifdef HAVE_CPLUS_DEMANGLE_SUPPORT - EXTLIBS += -liberty - else + ifdef BUILD_NONDISTRO ifeq ($(filter -liberty,$(EXTLIBS)),) - $(call feature_check,cplus-demangle) - - # we dont have neither HAVE_CPLUS_DEMANGLE_SUPPORT - # or any of 'bfd iberty z' trinity - ifeq ($(feature-cplus-demangle), 1) + ifdef HAVE_CPLUS_DEMANGLE_SUPPORT EXTLIBS += -liberty else - msg := $(warning No bfd.h/libbfd found, please install binutils-dev[el]/zlib-static/libiberty-dev to gain symbol demangling) - CFLAGS += -DNO_DEMANGLE + $(call feature_check,cplus-demangle) + ifeq ($(feature-cplus-demangle), 1) + EXTLIBS += -liberty + endif endif endif endif ifneq ($(filter -liberty,$(EXTLIBS)),) CFLAGS += -DHAVE_CPLUS_DEMANGLE_SUPPORT + else + CFLAGS += -DNO_DEMANGLE endif endif -ifneq ($(filter -lbfd,$(EXTLIBS)),) - CFLAGS += -DHAVE_LIBBFD_SUPPORT -endif - ifndef NO_ZLIB ifeq ($(feature-zlib), 1) CFLAGS += -DHAVE_ZLIB_SUPPORT diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf index 283ee4f56234..a35bc995d5d8 100644 --- a/tools/perf/Makefile.perf +++ b/tools/perf/Makefile.perf @@ -128,6 +128,8 @@ include ../scripts/utilities.mak # # Define NO_BPF_SKEL to disable BPF skeletons # +# Define BUILD_NONDISTRO to enable building an linking against libbfd and +# libiberty distribution license incompatible libraries. # As per kernel Makefile, avoid funny character set dependencies unexport LC_ALL diff --git a/tools/perf/tests/make b/tools/perf/tests/make index f9f826c0df47..52b9b6895da5 100644 --- a/tools/perf/tests/make +++ b/tools/perf/tests/make @@ -68,6 +68,7 @@ python_perf_so := $(shell $(MAKE) python_perf_target|grep "Target is:"|awk '{pri make_clean_all := clean all make_python_perf_so := $(python_perf_so) make_debug := DEBUG=1 +make_nondistro := BUILD_NONDISTRO=1 make_no_libperl := NO_LIBPERL=1 make_no_libpython := NO_LIBPYTHON=1 make_no_scripts := NO_LIBPYTHON=1 NO_LIBPERL=1 @@ -134,6 +135,7 @@ MAKE_F := $(MAKE) -f $(MK) endif run += make_python_perf_so run += make_debug +run += make_nondistro run += make_no_libperl run += make_no_libpython run += make_no_scripts -- cgit v1.2.3-58-ga151 From 4c72e2b35afc414140a59fb3c06ebc54e506c245 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 10 Mar 2023 22:57:48 -0800 Subject: tools build: Add feature test for abi::__cxa_demangle MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit cxxabi.h is part of libsdtc++ and LLVM's libcxx, providing abi::__cxa_demangle a portable C++ demangler. Add a feature test to detect that the function is available. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andres Freund Cc: Ingo Molnar Cc: Jiri Olsa Cc: Leo Yan Cc: Mark Rutland Cc: Martin Liška Cc: Namhyung Kim Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Pavithra Gurushankar Cc: Peter Zijlstra Cc: Quentin Monnet Cc: Roberto Sassu Cc: Stephane Eranian Cc: Tiezhu Yang Cc: Tom Rix Cc: Yang Jihong Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20230311065753.3012826-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/build/Makefile.feature | 1 + tools/build/feature/Makefile | 4 ++++ tools/build/feature/test-cxa-demangle.cpp | 17 +++++++++++++++++ 3 files changed, 22 insertions(+) create mode 100644 tools/build/feature/test-cxa-demangle.cpp (limited to 'tools') diff --git a/tools/build/Makefile.feature b/tools/build/Makefile.feature index 38f8851bd7cb..214622d7537c 100644 --- a/tools/build/Makefile.feature +++ b/tools/build/Makefile.feature @@ -80,6 +80,7 @@ FEATURE_TESTS_EXTRA := \ compile-32 \ compile-x32 \ cplus-demangle \ + cxa-demangle \ gtk2 \ gtk2-infobar \ hello \ diff --git a/tools/build/feature/Makefile b/tools/build/feature/Makefile index dc9323e01e42..0a3b9281f8b0 100644 --- a/tools/build/feature/Makefile +++ b/tools/build/feature/Makefile @@ -23,6 +23,7 @@ FILES= \ test-libbfd-liberty.bin \ test-libbfd-liberty-z.bin \ test-cplus-demangle.bin \ + test-cxa-demangle.bin \ test-libcap.bin \ test-libelf.bin \ test-libelf-getphdrnum.bin \ @@ -262,6 +263,9 @@ $(OUTPUT)test-libbfd-liberty-z.bin: $(OUTPUT)test-cplus-demangle.bin: $(BUILD) -liberty +$(OUTPUT)test-cxa-demangle.bin: + $(BUILDXX) + $(OUTPUT)test-backtrace.bin: $(BUILD) diff --git a/tools/build/feature/test-cxa-demangle.cpp b/tools/build/feature/test-cxa-demangle.cpp new file mode 100644 index 000000000000..a3e712f65c37 --- /dev/null +++ b/tools/build/feature/test-cxa-demangle.cpp @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include + +int main(void) +{ + size_t len = 256; + char *output = (char*)malloc(len); + int status; + + output = abi::__cxa_demangle("FieldName__9ClassNameFd", output, &len, &status); + + printf("demangled symbol: {%s}\n", output); + + return 0; +} -- cgit v1.2.3-58-ga151 From 3b4e4efe88f615f160a6c9319a9392d8410f742c Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 10 Mar 2023 22:57:49 -0800 Subject: perf symbol: Add abi::__cxa_demangle C++ demangling support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Refactor C++ demangling out of symbol-elf into its own files similar to other languages. Add abi::__cxa_demangle support. As the other demanglers are not shippable with distributions, this brings back C++ demangling in a common case. It isn't perfect as the support for optionally demangling arguments and modifiers isn't present. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andres Freund Cc: Ingo Molnar Cc: Jiri Olsa Cc: Leo Yan Cc: Mark Rutland Cc: Martin Liška Cc: Namhyung Kim Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Pavithra Gurushankar Cc: Peter Zijlstra Cc: Quentin Monnet Cc: Roberto Sassu Cc: Stephane Eranian Cc: Tiezhu Yang Cc: Tom Rix Cc: Yang Jihong Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20230311065753.3012826-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Makefile.config | 29 +++++++++++------------ tools/perf/util/Build | 1 + tools/perf/util/demangle-cxx.cpp | 50 ++++++++++++++++++++++++++++++++++++++++ tools/perf/util/demangle-cxx.h | 16 +++++++++++++ tools/perf/util/symbol-elf.c | 37 ++++++----------------------- 5 files changed, 88 insertions(+), 45 deletions(-) create mode 100644 tools/perf/util/demangle-cxx.cpp create mode 100644 tools/perf/util/demangle-cxx.h (limited to 'tools') diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index c4ae70c643b9..ac8a206acf87 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -914,6 +914,7 @@ ifdef BUILD_NONDISTRO endif CFLAGS += -DHAVE_LIBBFD_SUPPORT + CXXFLAGS += -DHAVE_LIBBFD_SUPPORT ifeq ($(feature-libbfd-buildid), 1) CFLAGS += -DHAVE_LIBBFD_BUILDID_SUPPORT else @@ -921,26 +922,24 @@ ifdef BUILD_NONDISTRO endif endif -ifdef NO_DEMANGLE - CFLAGS += -DNO_DEMANGLE -else +ifndef NO_DEMANGLE + $(call feature_check,cxa-demangle) + ifeq ($(feature-cxa-demangle), 1) + EXTLIBS += -lstdc++ + CFLAGS += -DHAVE_CXA_DEMANGLE_SUPPORT + CXXFLAGS += -DHAVE_CXA_DEMANGLE_SUPPORT + endif ifdef BUILD_NONDISTRO ifeq ($(filter -liberty,$(EXTLIBS)),) - ifdef HAVE_CPLUS_DEMANGLE_SUPPORT + $(call feature_check,cplus-demangle) + ifeq ($(feature-cplus-demangle), 1) EXTLIBS += -liberty - else - $(call feature_check,cplus-demangle) - ifeq ($(feature-cplus-demangle), 1) - EXTLIBS += -liberty - endif endif endif - endif - - ifneq ($(filter -liberty,$(EXTLIBS)),) - CFLAGS += -DHAVE_CPLUS_DEMANGLE_SUPPORT - else - CFLAGS += -DNO_DEMANGLE + ifneq ($(filter -liberty,$(EXTLIBS)),) + CFLAGS += -DHAVE_CPLUS_DEMANGLE_SUPPORT + CXXFLAGS += -DHAVE_CPLUS_DEMANGLE_SUPPORT + endif endif endif diff --git a/tools/perf/util/Build b/tools/perf/util/Build index 918b501f9bd8..8607575183a9 100644 --- a/tools/perf/util/Build +++ b/tools/perf/util/Build @@ -211,6 +211,7 @@ perf-$(CONFIG_ZSTD) += zstd.o perf-$(CONFIG_LIBCAP) += cap.o +perf-y += demangle-cxx.o perf-y += demangle-ocaml.o perf-y += demangle-java.o perf-y += demangle-rust.o diff --git a/tools/perf/util/demangle-cxx.cpp b/tools/perf/util/demangle-cxx.cpp new file mode 100644 index 000000000000..8708bcafd370 --- /dev/null +++ b/tools/perf/util/demangle-cxx.cpp @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "demangle-cxx.h" +#include +#include +#include + +#ifdef HAVE_LIBBFD_SUPPORT +#define PACKAGE 'perf' +#include +#endif + +#ifdef HAVE_CXA_DEMANGLE_SUPPORT +#include +#endif + +#if defined(HAVE_LIBBFD_SUPPORT) || defined(HAVE_CPLUS_DEMANGLE_SUPPORT) +#ifndef DMGL_PARAMS +#define DMGL_PARAMS (1 << 0) /* Include function args */ +#define DMGL_ANSI (1 << 1) /* Include const, volatile, etc */ +#endif +#endif + +/* + * Demangle C++ function signature + * + * Note: caller is responsible for freeing demangled string + */ +extern "C" +char *cxx_demangle_sym(const char *str, bool params __maybe_unused, + bool modifiers __maybe_unused) +{ +#ifdef HAVE_LIBBFD_SUPPORT + int flags = (params ? DMGL_PARAMS : 0) | (modifiers ? DMGL_ANSI : 0); + + return bfd_demangle(NULL, str, flags); +#elif defined(HAVE_CPLUS_DEMANGLE_SUPPORT) + int flags = (params ? DMGL_PARAMS : 0) | (modifiers ? DMGL_ANSI : 0); + + return cplus_demangle(str, flags); +#elif defined(HAVE_CXA_DEMANGLE_SUPPORT) + size_t len = strlen(str); + char *output = (char*)malloc(len); + int status; + + output = abi::__cxa_demangle(str, output, &len, &status); + return output; +#else + return NULL; +#endif +} diff --git a/tools/perf/util/demangle-cxx.h b/tools/perf/util/demangle-cxx.h new file mode 100644 index 000000000000..26b5b66c0b4e --- /dev/null +++ b/tools/perf/util/demangle-cxx.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __PERF_DEMANGLE_CXX +#define __PERF_DEMANGLE_CXX 1 + +#ifdef __cplusplus +extern "C" { +#endif + +char *cxx_demangle_sym(const char *str, bool params, bool modifiers); + +#ifdef __cplusplus +} +#endif + + +#endif /* __PERF_DEMANGLE_CXX */ diff --git a/tools/perf/util/symbol-elf.c b/tools/perf/util/symbol-elf.c index 41882ae8452e..c0a2de42c51b 100644 --- a/tools/perf/util/symbol-elf.c +++ b/tools/perf/util/symbol-elf.c @@ -12,6 +12,7 @@ #include "maps.h" #include "symbol.h" #include "symsrc.h" +#include "demangle-cxx.h" #include "demangle-ocaml.h" #include "demangle-java.h" #include "demangle-rust.h" @@ -25,6 +26,11 @@ #include #include +#ifdef HAVE_LIBBFD_SUPPORT +#define PACKAGE 'perf' +#include +#endif + #ifndef EM_AARCH64 #define EM_AARCH64 183 /* ARM 64 bit */ #endif @@ -45,34 +51,6 @@ typedef Elf64_Nhdr GElf_Nhdr; -#ifndef DMGL_PARAMS -#define DMGL_NO_OPTS 0 /* For readability... */ -#define DMGL_PARAMS (1 << 0) /* Include function args */ -#define DMGL_ANSI (1 << 1) /* Include const, volatile, etc */ -#endif - -#ifdef HAVE_LIBBFD_SUPPORT -#define PACKAGE 'perf' -#include -#else -#ifdef HAVE_CPLUS_DEMANGLE_SUPPORT -extern char *cplus_demangle(const char *, int); - -static inline char *bfd_demangle(void __maybe_unused *v, const char *c, int i) -{ - return cplus_demangle(c, i); -} -#else -#ifdef NO_DEMANGLE -static inline char *bfd_demangle(void __maybe_unused *v, - const char __maybe_unused *c, - int __maybe_unused i) -{ - return NULL; -} -#endif -#endif -#endif #ifndef HAVE_ELF_GETPHDRNUM_SUPPORT static int elf_getphdrnum(Elf *elf, size_t *dst) @@ -295,7 +273,6 @@ static bool want_demangle(bool is_kernel_sym) static char *demangle_sym(struct dso *dso, int kmodule, const char *elf_name) { - int demangle_flags = verbose > 0 ? (DMGL_PARAMS | DMGL_ANSI) : DMGL_NO_OPTS; char *demangled = NULL; /* @@ -306,7 +283,7 @@ static char *demangle_sym(struct dso *dso, int kmodule, const char *elf_name) if (!want_demangle(dso->kernel || kmodule)) return demangled; - demangled = bfd_demangle(NULL, elf_name, demangle_flags); + demangled = cxx_demangle_sym(elf_name, verbose > 0, verbose > 0); if (demangled == NULL) { demangled = ocaml_demangle_sym(elf_name); if (demangled == NULL) { -- cgit v1.2.3-58-ga151 From d7c4f89af1611530562554a237069deb2b03b312 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 10 Mar 2023 22:57:50 -0800 Subject: perf build: Switch libpfm4 to opt-out rather than opt-in MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If libpfm4 passes the feature test, it would be nice to have it enabled rather than also requiring the LIBPFM4=1 build flag. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andres Freund Cc: Ingo Molnar Cc: Jiri Olsa Cc: Leo Yan Cc: Mark Rutland Cc: Martin Liška Cc: Namhyung Kim Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Pavithra Gurushankar Cc: Peter Zijlstra Cc: Quentin Monnet Cc: Roberto Sassu Cc: Stephane Eranian Cc: Tiezhu Yang Cc: Tom Rix Cc: Yang Jihong Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20230311065753.3012826-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Makefile.config | 3 +-- tools/perf/Makefile.perf | 2 +- tools/perf/tests/make | 4 ++-- 3 files changed, 4 insertions(+), 5 deletions(-) (limited to 'tools') diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index ac8a206acf87..2caee19e3e9a 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -1138,7 +1138,7 @@ ifdef LIBCLANGLLVM endif endif -ifdef LIBPFM4 +ifndef NO_LIBPFM4 $(call feature_check,libpfm4) ifeq ($(feature-libpfm4), 1) CFLAGS += -DHAVE_LIBPFM @@ -1147,7 +1147,6 @@ ifdef LIBPFM4 $(call detected,CONFIG_LIBPFM4) else msg := $(warning libpfm4 not found, disables libpfm4 support. Please install libpfm4-dev); - NO_LIBPFM4 := 1 endif endif diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf index a35bc995d5d8..3e06915f6bd0 100644 --- a/tools/perf/Makefile.perf +++ b/tools/perf/Makefile.perf @@ -122,7 +122,7 @@ include ../scripts/utilities.mak # generated from the kernel .tbl or unistd.h files and use, if available, libaudit # for doing the conversions to/from strings/id. # -# Define LIBPFM4 to enable libpfm4 events extension. +# Define NO_LIBPFM4 to disable libpfm4 events extension. # # Define NO_LIBDEBUGINFOD if you do not want support debuginfod # diff --git a/tools/perf/tests/make b/tools/perf/tests/make index 52b9b6895da5..ba09a8b4ffb4 100644 --- a/tools/perf/tests/make +++ b/tools/perf/tests/make @@ -94,7 +94,7 @@ make_with_coresight := CORESIGHT=1 make_no_sdt := NO_SDT=1 make_no_syscall_tbl := NO_SYSCALL_TABLE=1 make_with_clangllvm := LIBCLANGLLVM=1 -make_with_libpfm4 := LIBPFM4=1 +make_no_libpfm4 := NO_LIBPFM4=1 make_with_gtk2 := GTK2=1 make_tags := tags make_cscope := cscope @@ -160,7 +160,7 @@ run += make_no_syscall_tbl run += make_with_babeltrace run += make_with_coresight run += make_with_clangllvm -run += make_with_libpfm4 +run += make_no_libpfm4 run += make_help run += make_doc run += make_perf_o -- cgit v1.2.3-58-ga151 From 6898e60f709b0047206110d3ec9f4612210e3ff7 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 10 Mar 2023 22:57:51 -0800 Subject: perf build: If libtraceevent isn't present error the build MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If libtraceevent isn't present, the build will warn and continue. This disables a number of features and so isn't desirable. This change makes the build error for this case. The build can still be made to happen by adding NO_LIBTRACEEVENT=1. Committer notes: Add NO_LIBTRACEEVENT=1 to the 'make_static' target in tools/perf/tests/make so that 'make -C tools/perf build-test' works. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andres Freund Cc: Ingo Molnar Cc: Jiri Olsa Cc: Leo Yan Cc: Mark Rutland Cc: Martin Liška Cc: Namhyung Kim Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Pavithra Gurushankar Cc: Peter Zijlstra Cc: Quentin Monnet Cc: Roberto Sassu Cc: Stephane Eranian Cc: Tiezhu Yang Cc: Tom Rix Cc: Yang Jihong Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20230311065753.3012826-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Makefile.config | 2 +- tools/perf/tests/make | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index 2caee19e3e9a..da0b13e819ee 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -1164,7 +1164,7 @@ ifneq ($(NO_LIBTRACEEVENT),1) CFLAGS += -DLIBTRACEEVENT_VERSION=$(LIBTRACEEVENT_VERSION_CPP) $(call detected,CONFIG_LIBTRACEEVENT) else - dummy := $(warning Warning: libtraceevent is missing limiting functionality, please install libtraceevent-dev/libtraceevent-devel) + dummy := $(error ERROR: libtraceevent is missing. Please install libtraceevent-dev/libtraceevent-devel or build with NO_LIBTRACEEVENT=1) endif $(call feature_check,libtracefs) diff --git a/tools/perf/tests/make b/tools/perf/tests/make index ba09a8b4ffb4..55d0ef3a0cae 100644 --- a/tools/perf/tests/make +++ b/tools/perf/tests/make @@ -112,7 +112,7 @@ make_install_info := install-info make_install_pdf := install-pdf make_install_prefix := install prefix=/tmp/krava make_install_prefix_slash := install prefix=/tmp/krava/ -make_static := LDFLAGS=-static NO_PERF_READ_VDSO32=1 NO_PERF_READ_VDSOX32=1 NO_JVMTI=1 +make_static := LDFLAGS=-static NO_PERF_READ_VDSO32=1 NO_PERF_READ_VDSOX32=1 NO_JVMTI=1 NO_LIBTRACEEVENT=1 # all the NO_* variable combined make_minimal := NO_LIBPERL=1 NO_LIBPYTHON=1 NO_NEWT=1 NO_GTK2=1 -- cgit v1.2.3-58-ga151 From f1925bd588cfc3ea2e8624404027958955d39121 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 10 Mar 2023 22:57:53 -0800 Subject: perf build: Remove redundant NO_NEWT build option MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The option controlled nothing and no code depends, conditional or otherwise, on libnewt. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andres Freund Cc: Ingo Molnar Cc: Jiri Olsa Cc: Leo Yan Cc: Mark Rutland Cc: Martin Liška Cc: Namhyung Kim Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Pavithra Gurushankar Cc: Peter Zijlstra Cc: Quentin Monnet Cc: Roberto Sassu Cc: Stephane Eranian Cc: Tiezhu Yang Cc: Tom Rix Cc: Yang Jihong Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20230311065753.3012826-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Makefile.config | 4 ---- tools/perf/Makefile.perf | 2 -- tools/perf/tests/make | 6 ++---- 3 files changed, 2 insertions(+), 10 deletions(-) (limited to 'tools') diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index da0b13e819ee..0959714a89ed 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -760,10 +760,6 @@ ifndef NO_LIBCRYPTO endif endif -ifdef NO_NEWT - NO_SLANG=1 -endif - ifndef NO_SLANG ifneq ($(feature-libslang), 1) ifneq ($(feature-libslang-include-subdir), 1) diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf index 3e06915f6bd0..dc9dda09b076 100644 --- a/tools/perf/Makefile.perf +++ b/tools/perf/Makefile.perf @@ -44,8 +44,6 @@ include ../scripts/utilities.mak # # Define WERROR=0 to disable treating any warnings as errors. # -# Define NO_NEWT if you do not want TUI support. (deprecated) -# # Define NO_SLANG if you do not want TUI support. # # Define GTK2 if you want GTK+ GUI support. diff --git a/tools/perf/tests/make b/tools/perf/tests/make index 55d0ef3a0cae..0b92fa1863f6 100644 --- a/tools/perf/tests/make +++ b/tools/perf/tests/make @@ -72,10 +72,9 @@ make_nondistro := BUILD_NONDISTRO=1 make_no_libperl := NO_LIBPERL=1 make_no_libpython := NO_LIBPYTHON=1 make_no_scripts := NO_LIBPYTHON=1 NO_LIBPERL=1 -make_no_newt := NO_NEWT=1 make_no_slang := NO_SLANG=1 make_no_gtk2 := NO_GTK2=1 -make_no_ui := NO_NEWT=1 NO_SLANG=1 NO_GTK2=1 +make_no_ui := NO_SLANG=1 NO_GTK2=1 make_no_demangle := NO_DEMANGLE=1 make_no_libelf := NO_LIBELF=1 make_no_libunwind := NO_LIBUNWIND=1 @@ -115,7 +114,7 @@ make_install_prefix_slash := install prefix=/tmp/krava/ make_static := LDFLAGS=-static NO_PERF_READ_VDSO32=1 NO_PERF_READ_VDSOX32=1 NO_JVMTI=1 NO_LIBTRACEEVENT=1 # all the NO_* variable combined -make_minimal := NO_LIBPERL=1 NO_LIBPYTHON=1 NO_NEWT=1 NO_GTK2=1 +make_minimal := NO_LIBPERL=1 NO_LIBPYTHON=1 NO_GTK2=1 make_minimal += NO_DEMANGLE=1 NO_LIBELF=1 NO_LIBUNWIND=1 NO_BACKTRACE=1 make_minimal += NO_LIBNUMA=1 NO_LIBAUDIT=1 NO_LIBBIONIC=1 make_minimal += NO_LIBDW_DWARF_UNWIND=1 NO_AUXTRACE=1 NO_LIBBPF=1 @@ -139,7 +138,6 @@ run += make_nondistro run += make_no_libperl run += make_no_libpython run += make_no_scripts -run += make_no_newt run += make_no_slang run += make_no_gtk2 run += make_no_ui -- cgit v1.2.3-58-ga151 From 8d98ca5c02df13c1f750953bca2e308a41df08a9 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 10 Mar 2023 22:57:44 -0800 Subject: perf build: Error if no libelf and NO_LIBELF isn't set MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Building without libelf support is going disable a lot of functionality. Require that the NO_LIBELF=1 build option is passed if this is intentional. Committer notes: Add NO_LIBELF=1 to the 'make_static' target in tools/perf/tests/make so that 'make -C tools/perf build-test' works. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andres Freund Cc: Ingo Molnar Cc: Jiri Olsa Cc: Leo Yan Cc: Mark Rutland Cc: Martin Liška Cc: Namhyung Kim Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Pavithra Gurushankar Cc: Peter Zijlstra Cc: Quentin Monnet Cc: Roberto Sassu Cc: Stephane Eranian Cc: Tiezhu Yang Cc: Tom Rix Cc: Yang Jihong Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20230311065753.3012826-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Makefile.config | 10 +--------- tools/perf/tests/make | 2 +- 2 files changed, 2 insertions(+), 10 deletions(-) (limited to 'tools') diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index 0959714a89ed..3066d0c318c3 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -426,15 +426,7 @@ else LIBC_SUPPORT := 1 endif ifeq ($(LIBC_SUPPORT),1) - msg := $(warning No libelf found. Disables 'probe' tool, jvmti and BPF support in 'perf record'. Please install libelf-dev, libelf-devel or elfutils-libelf-devel); - - NO_LIBELF := 1 - NO_DWARF := 1 - NO_DEMANGLE := 1 - NO_LIBUNWIND := 1 - NO_LIBDW_DWARF_UNWIND := 1 - NO_LIBBPF := 1 - NO_JVMTI := 1 + msg := $(error ERROR: No libelf found. Disables 'probe' tool, jvmti and BPF support. Please install libelf-dev, libelf-devel, elfutils-libelf-devel or build with NO_LIBELF=1.) else ifneq ($(filter s% -fsanitize=address%,$(EXTRA_CFLAGS),),) ifneq ($(shell ldconfig -p | grep libasan >/dev/null 2>&1; echo $$?), 0) diff --git a/tools/perf/tests/make b/tools/perf/tests/make index 0b92fa1863f6..96896d498641 100644 --- a/tools/perf/tests/make +++ b/tools/perf/tests/make @@ -111,7 +111,7 @@ make_install_info := install-info make_install_pdf := install-pdf make_install_prefix := install prefix=/tmp/krava make_install_prefix_slash := install prefix=/tmp/krava/ -make_static := LDFLAGS=-static NO_PERF_READ_VDSO32=1 NO_PERF_READ_VDSOX32=1 NO_JVMTI=1 NO_LIBTRACEEVENT=1 +make_static := LDFLAGS=-static NO_PERF_READ_VDSO32=1 NO_PERF_READ_VDSOX32=1 NO_JVMTI=1 NO_LIBTRACEEVENT=1 NO_LIBELF=1 # all the NO_* variable combined make_minimal := NO_LIBPERL=1 NO_LIBPYTHON=1 NO_GTK2=1 -- cgit v1.2.3-58-ga151 From 3ace2435bb93445e7713d69336011c46558a18af Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Mon, 13 Mar 2023 13:48:22 -0700 Subject: perf lock contention: Track and show mmap_lock with address Sometimes there are severe contentions on the mmap_lock and we want see it in the -l/--lock-addr output. However it cannot symbolize the mmap_lock because it's allocated dynamically without symbols. Stephane and Hao gave me an idea separately to display mmap_lock by following the current->mm pointer. I added a flag to mark mmap_lock after comparing the lock address so that it can show them differently. With this change it can show mmap_lock like below: $ sudo ./perf lock con -abl -- sleep 10 contended total wait max wait avg wait address symbol ... 16344 312.30 ms 2.22 ms 19.11 us ffff8cc702595640 17686 310.08 ms 1.49 ms 17.53 us ffff8cc7025952c0 3 84.14 ms 45.79 ms 28.05 ms ffff8cc78114c478 mmap_lock 3557 76.80 ms 68.75 us 21.59 us ffff8cc77ca3af58 1 68.27 ms 68.27 ms 68.27 ms ffff8cda745dfd70 9 54.53 ms 7.96 ms 6.06 ms ffff8cc7642a48b8 mmap_lock 14629 44.01 ms 60.00 us 3.01 us ffff8cc7625f9ca0 3481 42.63 ms 140.71 us 12.24 us ffffffff937906ac vmap_area_lock 16194 38.73 ms 42.15 us 2.39 us ffff8cd397cbc560 11 38.44 ms 10.39 ms 3.49 ms ffff8ccd6d12fbb8 mmap_lock 1 5.43 ms 5.43 ms 5.43 ms ffff8cd70018f0d8 1674 5.38 ms 422.93 us 3.21 us ffffffff92e06080 tasklist_lock 581 4.51 ms 130.68 us 7.75 us ffff8cc9b1259058 5 3.52 ms 1.27 ms 703.23 us ffff8cc754510070 112 3.47 ms 56.47 us 31.02 us ffff8ccee38b3120 381 3.31 ms 73.44 us 8.69 us ffffffff93790690 purge_vmap_area_lock 255 3.19 ms 36.35 us 12.49 us ffff8d053ce30c80 Note that mmap_lock was renamed some time ago and it needs to support old kernels with a different name 'mmap_sem'. Suggested-by: Hao Luo Suggested-by: Stephane Eranian Signed-off-by: Namhyung Kim Cc: Boqun Feng Cc: Ingo Molnar Cc: Jiri Olsa Cc: Juri Lelli Cc: Peter Zijlstra Cc: Song Liu Cc: Suren Baghdasaryan Cc: Waiman Long Cc: Will Deacon Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230313204825.2665483-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-lock.c | 2 +- tools/perf/util/bpf_skel/lock_contention.bpf.c | 41 ++++++++++++++++++++++++++ tools/perf/util/bpf_skel/lock_data.h | 6 ++++ 3 files changed, 48 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/builtin-lock.c b/tools/perf/builtin-lock.c index 240d49a85524..1b0dc946fe85 100644 --- a/tools/perf/builtin-lock.c +++ b/tools/perf/builtin-lock.c @@ -1663,7 +1663,7 @@ static void print_contention_result(struct lock_contention *con) break; case LOCK_AGGR_ADDR: pr_info(" %016llx %s\n", (unsigned long long)st->addr, - st->name ? : ""); + (st->flags & LCD_F_MMAP_LOCK) ? "mmap_lock" : st->name); break; default: break; diff --git a/tools/perf/util/bpf_skel/lock_contention.bpf.c b/tools/perf/util/bpf_skel/lock_contention.bpf.c index 141b36d13b19..40ee3dffb35a 100644 --- a/tools/perf/util/bpf_skel/lock_contention.bpf.c +++ b/tools/perf/util/bpf_skel/lock_contention.bpf.c @@ -92,6 +92,14 @@ struct rw_semaphore___new { atomic_long_t owner; } __attribute__((preserve_access_index)); +struct mm_struct___old { + struct rw_semaphore mmap_sem; +} __attribute__((preserve_access_index)); + +struct mm_struct___new { + struct rw_semaphore mmap_lock; +} __attribute__((preserve_access_index)); + /* control flags */ int enabled; int has_cpu; @@ -210,6 +218,36 @@ static inline struct task_struct *get_lock_owner(__u64 lock, __u32 flags) return task; } +static inline __u32 check_lock_type(__u64 lock, __u32 flags) +{ + struct task_struct *curr; + struct mm_struct___old *mm_old; + struct mm_struct___new *mm_new; + + switch (flags) { + case LCB_F_READ: /* rwsem */ + case LCB_F_WRITE: + curr = bpf_get_current_task_btf(); + if (curr->mm == NULL) + break; + mm_new = (void *)curr->mm; + if (bpf_core_field_exists(mm_new->mmap_lock)) { + if (&mm_new->mmap_lock == (void *)lock) + return LCD_F_MMAP_LOCK; + break; + } + mm_old = (void *)curr->mm; + if (bpf_core_field_exists(mm_old->mmap_sem)) { + if (&mm_old->mmap_sem == (void *)lock) + return LCD_F_MMAP_LOCK; + } + break; + default: + break; + } + return 0; +} + SEC("tp_btf/contention_begin") int contention_begin(u64 *ctx) { @@ -320,6 +358,9 @@ int contention_end(u64 *ctx) .flags = pelem->flags, }; + if (aggr_mode == LOCK_AGGR_ADDR) + first.flags |= check_lock_type(pelem->lock, pelem->flags); + bpf_map_update_elem(&lock_stat, &key, &first, BPF_NOEXIST); bpf_map_delete_elem(&tstamp, &pid); return 0; diff --git a/tools/perf/util/bpf_skel/lock_data.h b/tools/perf/util/bpf_skel/lock_data.h index 3d35fd4407ac..789f20833798 100644 --- a/tools/perf/util/bpf_skel/lock_data.h +++ b/tools/perf/util/bpf_skel/lock_data.h @@ -15,6 +15,12 @@ struct contention_task_data { char comm[TASK_COMM_LEN]; }; +/* + * Upper bits of the flags in the contention_data are used to identify + * some well-known locks which do not have symbols (non-global locks). + */ +#define LCD_F_MMAP_LOCK (1U << 31) + struct contention_data { u64 total_time; u64 min_time; -- cgit v1.2.3-58-ga151 From 1811e82767dcc6ebfdb2a57877f1756f067990b8 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Mon, 13 Mar 2023 13:48:23 -0700 Subject: perf lock contention: Track and show siglock with address Likewise, we can display siglock by following the pointer like current->sighand->siglock. $ sudo ./perf lock con -abl -- sleep 1 contended total wait max wait avg wait address symbol 16 2.18 ms 305.35 us 136.34 us ffffffff92e06080 tasklist_lock 28 521.78 us 31.16 us 18.63 us ffff8cc703783ec4 7 119.03 us 23.55 us 17.00 us ffff8ccb92479440 15 88.29 us 10.06 us 5.89 us ffff8cd560b5f380 siglock 7 37.67 us 9.16 us 5.38 us ffff8d053daf0c80 5 8.81 us 4.92 us 1.76 us ffff8d053d6b0c80 Signed-off-by: Namhyung Kim Cc: Boqun Feng Cc: Hao Luo Cc: Ingo Molnar Cc: Jiri Olsa Cc: Juri Lelli Cc: Peter Zijlstra Cc: Song Liu Cc: Stephane Eranian Cc: Waiman Long Cc: Will Deacon Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230313204825.2665483-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-lock.c | 3 +-- tools/perf/util/bpf_lock_contention.c | 8 ++++++-- tools/perf/util/bpf_skel/lock_contention.bpf.c | 5 +++++ tools/perf/util/bpf_skel/lock_data.h | 3 ++- 4 files changed, 14 insertions(+), 5 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-lock.c b/tools/perf/builtin-lock.c index 1b0dc946fe85..28fa0d0dc276 100644 --- a/tools/perf/builtin-lock.c +++ b/tools/perf/builtin-lock.c @@ -1662,8 +1662,7 @@ static void print_contention_result(struct lock_contention *con) pid, pid == -1 ? "Unknown" : thread__comm_str(t)); break; case LOCK_AGGR_ADDR: - pr_info(" %016llx %s\n", (unsigned long long)st->addr, - (st->flags & LCD_F_MMAP_LOCK) ? "mmap_lock" : st->name); + pr_info(" %016llx %s\n", (unsigned long long)st->addr, st->name); break; default: break; diff --git a/tools/perf/util/bpf_lock_contention.c b/tools/perf/util/bpf_lock_contention.c index fadcacb9d501..51631af3b4d6 100644 --- a/tools/perf/util/bpf_lock_contention.c +++ b/tools/perf/util/bpf_lock_contention.c @@ -169,7 +169,7 @@ int lock_contention_stop(void) static const char *lock_contention_get_name(struct lock_contention *con, struct contention_key *key, - u64 *stack_trace) + u64 *stack_trace, u32 flags) { int idx = 0; u64 addr; @@ -198,6 +198,10 @@ static const char *lock_contention_get_name(struct lock_contention *con, } if (con->aggr_mode == LOCK_AGGR_ADDR) { + if (flags & LCD_F_MMAP_LOCK) + return "mmap_lock"; + if (flags & LCD_F_SIGHAND_LOCK) + return "siglock"; sym = machine__find_kernel_symbol(machine, key->lock_addr, &kmap); if (sym) name = sym->name; @@ -301,7 +305,7 @@ int lock_contention_read(struct lock_contention *con) goto next; } - name = lock_contention_get_name(con, &key, stack_trace); + name = lock_contention_get_name(con, &key, stack_trace, data.flags); st = lock_stat_findnew(ls_key, name, data.flags); if (st == NULL) break; diff --git a/tools/perf/util/bpf_skel/lock_contention.bpf.c b/tools/perf/util/bpf_skel/lock_contention.bpf.c index 40ee3dffb35a..f76cde065c5d 100644 --- a/tools/perf/util/bpf_skel/lock_contention.bpf.c +++ b/tools/perf/util/bpf_skel/lock_contention.bpf.c @@ -242,6 +242,11 @@ static inline __u32 check_lock_type(__u64 lock, __u32 flags) return LCD_F_MMAP_LOCK; } break; + case LCB_F_SPIN: /* spinlock */ + curr = bpf_get_current_task_btf(); + if (&curr->sighand->siglock == (void *)lock) + return LCD_F_SIGHAND_LOCK; + break; default: break; } diff --git a/tools/perf/util/bpf_skel/lock_data.h b/tools/perf/util/bpf_skel/lock_data.h index 789f20833798..5ed1a0955015 100644 --- a/tools/perf/util/bpf_skel/lock_data.h +++ b/tools/perf/util/bpf_skel/lock_data.h @@ -19,7 +19,8 @@ struct contention_task_data { * Upper bits of the flags in the contention_data are used to identify * some well-known locks which do not have symbols (non-global locks). */ -#define LCD_F_MMAP_LOCK (1U << 31) +#define LCD_F_MMAP_LOCK (1U << 31) +#define LCD_F_SIGHAND_LOCK (1U << 30) struct contention_data { u64 total_time; -- cgit v1.2.3-58-ga151 From d24c0144b1dde00f6e7283df3708fcc62dddbaa9 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Mon, 13 Mar 2023 13:48:24 -0700 Subject: perf lock contention: Show per-cpu rq_lock with address Using the BPF_PROG_RUN mechanism, we can run a raw_tp BPF program to collect some semi-global locks like per-cpu locks. Let's add runqueue locks using bpf_per_cpu_ptr() helper. $ sudo ./perf lock con -abl -- sleep 1 contended total wait max wait avg wait address symbol 248 3.25 ms 32.23 us 13.10 us ffff8cc75cfd2940 siglock 60 217.91 us 9.69 us 3.63 us ffff8cc700061c00 8 70.23 us 13.86 us 8.78 us ffff8cc703629484 4 56.32 us 35.81 us 14.08 us ffff8cc78b66f778 mmap_lock 4 16.70 us 5.18 us 4.18 us ffff8cc7036a0684 3 4.99 us 2.65 us 1.66 us ffff8d053da30c80 rq_lock 2 3.44 us 2.28 us 1.72 us ffff8d053dcf0c80 rq_lock 9 2.51 us 371 ns 278 ns ffff8ccb92479440 2 2.11 us 1.24 us 1.06 us ffff8d053db30c80 rq_lock 2 2.06 us 1.69 us 1.03 us ffff8d053d970c80 rq_lock Signed-off-by: Namhyung Kim Cc: Boqun Feng Cc: Hao Luo Cc: Ingo Molnar Cc: Jiri Olsa Cc: Juri Lelli Cc: Peter Zijlstra Cc: Song Liu Cc: Stephane Eranian Cc: Waiman Long Cc: Will Deacon Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230313204825.2665483-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/bpf_lock_contention.c | 27 ++++++++++++++++++++-- tools/perf/util/bpf_skel/lock_contention.bpf.c | 31 ++++++++++++++++++++++++++ tools/perf/util/bpf_skel/lock_data.h | 5 +++++ 3 files changed, 61 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/bpf_lock_contention.c b/tools/perf/util/bpf_lock_contention.c index 51631af3b4d6..235fc7150545 100644 --- a/tools/perf/util/bpf_lock_contention.c +++ b/tools/perf/util/bpf_lock_contention.c @@ -151,6 +151,8 @@ int lock_contention_prepare(struct lock_contention *con) skel->bss->needs_callstack = con->save_callstack; skel->bss->lock_owner = con->owner; + bpf_program__set_autoload(skel->progs.collect_lock_syms, false); + lock_contention_bpf__attach(skel); return 0; } @@ -198,14 +200,26 @@ static const char *lock_contention_get_name(struct lock_contention *con, } if (con->aggr_mode == LOCK_AGGR_ADDR) { + int lock_fd = bpf_map__fd(skel->maps.lock_syms); + + /* per-process locks set upper bits of the flags */ if (flags & LCD_F_MMAP_LOCK) return "mmap_lock"; if (flags & LCD_F_SIGHAND_LOCK) return "siglock"; + + /* global locks with symbols */ sym = machine__find_kernel_symbol(machine, key->lock_addr, &kmap); if (sym) - name = sym->name; - return name; + return sym->name; + + /* try semi-global locks collected separately */ + if (!bpf_map_lookup_elem(lock_fd, &key->lock_addr, &flags)) { + if (flags == LOCK_CLASS_RQLOCK) + return "rq_lock"; + } + + return ""; } /* LOCK_AGGR_CALLER: skip lock internal functions */ @@ -258,6 +272,15 @@ int lock_contention_read(struct lock_contention *con) thread__set_comm(idle, "swapper", /*timestamp=*/0); } + if (con->aggr_mode == LOCK_AGGR_ADDR) { + DECLARE_LIBBPF_OPTS(bpf_test_run_opts, opts, + .flags = BPF_F_TEST_RUN_ON_CPU, + ); + int prog_fd = bpf_program__fd(skel->progs.collect_lock_syms); + + bpf_prog_test_run_opts(prog_fd, &opts); + } + /* make sure it loads the kernel map */ map__load(maps__first(machine->kmaps)); diff --git a/tools/perf/util/bpf_skel/lock_contention.bpf.c b/tools/perf/util/bpf_skel/lock_contention.bpf.c index f76cde065c5d..ed9160999c32 100644 --- a/tools/perf/util/bpf_skel/lock_contention.bpf.c +++ b/tools/perf/util/bpf_skel/lock_contention.bpf.c @@ -10,6 +10,9 @@ /* default buffer size */ #define MAX_ENTRIES 10240 +/* for collect_lock_syms(). 4096 was rejected by the verifier */ +#define MAX_CPUS 1024 + /* lock contention flags from include/trace/events/lock.h */ #define LCB_F_SPIN (1U << 0) #define LCB_F_READ (1U << 1) @@ -56,6 +59,13 @@ struct { __uint(max_entries, MAX_ENTRIES); } task_data SEC(".maps"); +struct { + __uint(type, BPF_MAP_TYPE_HASH); + __uint(key_size, sizeof(__u64)); + __uint(value_size, sizeof(__u32)); + __uint(max_entries, 16384); +} lock_syms SEC(".maps"); + struct { __uint(type, BPF_MAP_TYPE_HASH); __uint(key_size, sizeof(__u32)); @@ -384,4 +394,25 @@ int contention_end(u64 *ctx) return 0; } +extern struct rq runqueues __ksym; + +SEC("raw_tp/bpf_test_finish") +int BPF_PROG(collect_lock_syms) +{ + __u64 lock_addr; + __u32 lock_flag; + + for (int i = 0; i < MAX_CPUS; i++) { + struct rq *rq = bpf_per_cpu_ptr(&runqueues, i); + + if (rq == NULL) + break; + + lock_addr = (__u64)&rq->__lock; + lock_flag = LOCK_CLASS_RQLOCK; + bpf_map_update_elem(&lock_syms, &lock_addr, &lock_flag, BPF_ANY); + } + return 0; +} + char LICENSE[] SEC("license") = "Dual BSD/GPL"; diff --git a/tools/perf/util/bpf_skel/lock_data.h b/tools/perf/util/bpf_skel/lock_data.h index 5ed1a0955015..e59366f2dba3 100644 --- a/tools/perf/util/bpf_skel/lock_data.h +++ b/tools/perf/util/bpf_skel/lock_data.h @@ -36,4 +36,9 @@ enum lock_aggr_mode { LOCK_AGGR_CALLER, }; +enum lock_class_sym { + LOCK_CLASS_NONE, + LOCK_CLASS_RQLOCK, +}; + #endif /* UTIL_BPF_SKEL_LOCK_DATA_H */ -- cgit v1.2.3-58-ga151 From 4f701063bfa24ca3da050104cc757dfc3b252355 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Mon, 13 Mar 2023 13:48:25 -0700 Subject: perf lock contention: Show lock type with address Show lock type names after the symbol of locks if any. This can be useful especially when it doesn't show the lock symbols. The indentation before the lock type parenthesis is to recognize lock symbols more easily. $ sudo ./perf lock con -abl -- sleep 1 contended total wait max wait avg wait address symbol 44 6.13 ms 284.49 us 139.28 us ffffffff92e06080 tasklist_lock (rwlock) 159 983.38 us 12.38 us 6.18 us ffff8cc717c90000 siglock (spinlock) 10 679.90 us 153.35 us 67.99 us ffff8cdc2872aaf8 mmap_lock (rwsem) 9 558.11 us 180.67 us 62.01 us ffff8cd647914038 mmap_lock (rwsem) 78 228.56 us 7.82 us 2.93 us ffff8cc700061c00 (spinlock) 5 41.60 us 16.93 us 8.32 us ffffd853acb41468 (spinlock) 10 37.24 us 5.87 us 3.72 us ffff8cd560b5c200 siglock (spinlock) 4 11.17 us 3.97 us 2.79 us ffff8d053ddf0c80 rq_lock (spinlock) 1 7.86 us 7.86 us 7.86 us ffff8cd64791404c (spinlock) 1 4.13 us 4.13 us 4.13 us ffff8d053d930c80 rq_lock (spinlock) 7 3.98 us 1.67 us 568 ns ffff8ccb92479440 (mutex) 2 2.62 us 2.33 us 1.31 us ffff8cc702e6ede0 (rwlock) Signed-off-by: Namhyung Kim Cc: Boqun Feng Cc: Hao Luo Cc: Ingo Molnar Cc: Jiri Olsa Cc: Juri Lelli Cc: Peter Zijlstra Cc: Song Liu Cc: Stephane Eranian Cc: Waiman Long Cc: Will Deacon Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230313204825.2665483-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-lock.c | 45 ++++++++++++++++++++++++------------ tools/perf/util/bpf_skel/lock_data.h | 2 ++ 2 files changed, 32 insertions(+), 15 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-lock.c b/tools/perf/builtin-lock.c index 28fa0d0dc276..3c8a19ebc496 100644 --- a/tools/perf/builtin-lock.c +++ b/tools/perf/builtin-lock.c @@ -1548,27 +1548,41 @@ static void sort_result(void) static const struct { unsigned int flags; + const char *str; const char *name; } lock_type_table[] = { - { 0, "semaphore" }, - { LCB_F_SPIN, "spinlock" }, - { LCB_F_SPIN | LCB_F_READ, "rwlock:R" }, - { LCB_F_SPIN | LCB_F_WRITE, "rwlock:W"}, - { LCB_F_READ, "rwsem:R" }, - { LCB_F_WRITE, "rwsem:W" }, - { LCB_F_RT, "rtmutex" }, - { LCB_F_RT | LCB_F_READ, "rwlock-rt:R" }, - { LCB_F_RT | LCB_F_WRITE, "rwlock-rt:W"}, - { LCB_F_PERCPU | LCB_F_READ, "pcpu-sem:R" }, - { LCB_F_PERCPU | LCB_F_WRITE, "pcpu-sem:W" }, - { LCB_F_MUTEX, "mutex" }, - { LCB_F_MUTEX | LCB_F_SPIN, "mutex" }, + { 0, "semaphore", "semaphore" }, + { LCB_F_SPIN, "spinlock", "spinlock" }, + { LCB_F_SPIN | LCB_F_READ, "rwlock:R", "rwlock" }, + { LCB_F_SPIN | LCB_F_WRITE, "rwlock:W", "rwlock" }, + { LCB_F_READ, "rwsem:R", "rwsem" }, + { LCB_F_WRITE, "rwsem:W", "rwsem" }, + { LCB_F_RT, "rt=mutex", "rt-mutex" }, + { LCB_F_RT | LCB_F_READ, "rwlock-rt:R", "rwlock-rt" }, + { LCB_F_RT | LCB_F_WRITE, "rwlock-rt:W", "rwlock-rt" }, + { LCB_F_PERCPU | LCB_F_READ, "pcpu-sem:R", "percpu-rwsem" }, + { LCB_F_PERCPU | LCB_F_WRITE, "pcpu-sem:W", "percpu-rwsem" }, + { LCB_F_MUTEX, "mutex", "mutex" }, + { LCB_F_MUTEX | LCB_F_SPIN, "mutex", "mutex" }, /* alias for get_type_flag() */ - { LCB_F_MUTEX | LCB_F_SPIN, "mutex-spin" }, + { LCB_F_MUTEX | LCB_F_SPIN, "mutex-spin", "mutex" }, }; static const char *get_type_str(unsigned int flags) { + flags &= LCB_F_MAX_FLAGS - 1; + + for (unsigned int i = 0; i < ARRAY_SIZE(lock_type_table); i++) { + if (lock_type_table[i].flags == flags) + return lock_type_table[i].str; + } + return "unknown"; +} + +static const char *get_type_name(unsigned int flags) +{ + flags &= LCB_F_MAX_FLAGS - 1; + for (unsigned int i = 0; i < ARRAY_SIZE(lock_type_table); i++) { if (lock_type_table[i].flags == flags) return lock_type_table[i].name; @@ -1662,7 +1676,8 @@ static void print_contention_result(struct lock_contention *con) pid, pid == -1 ? "Unknown" : thread__comm_str(t)); break; case LOCK_AGGR_ADDR: - pr_info(" %016llx %s\n", (unsigned long long)st->addr, st->name); + pr_info(" %016llx %s (%s)\n", (unsigned long long)st->addr, + st->name, get_type_name(st->flags)); break; default: break; diff --git a/tools/perf/util/bpf_skel/lock_data.h b/tools/perf/util/bpf_skel/lock_data.h index e59366f2dba3..1ba61cb4d480 100644 --- a/tools/perf/util/bpf_skel/lock_data.h +++ b/tools/perf/util/bpf_skel/lock_data.h @@ -22,6 +22,8 @@ struct contention_task_data { #define LCD_F_MMAP_LOCK (1U << 31) #define LCD_F_SIGHAND_LOCK (1U << 30) +#define LCB_F_MAX_FLAGS (1U << 7) + struct contention_data { u64 total_time; u64 min_time; -- cgit v1.2.3-58-ga151 From 07fc5921a014e227bd3b622d31a8a35ff3f19afb Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Tue, 7 Mar 2023 16:27:14 -0800 Subject: perf test: Fix "PMU event table sanity" for NO_JEVENTS=1 A table was renamed and needed to be renamed in the empty case. Fixes: 62774db2a05dc878 ("perf jevents: Generate metrics and events as separate tables") Reviewed-by: John Garry Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kajol Jain Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230308002714.1755698-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/empty-pmu-events.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/empty-pmu-events.c b/tools/perf/pmu-events/empty-pmu-events.c index a938b74cf487..e74defb5284f 100644 --- a/tools/perf/pmu-events/empty-pmu-events.c +++ b/tools/perf/pmu-events/empty-pmu-events.c @@ -227,7 +227,7 @@ static const struct pmu_events_map pmu_events_map[] = { }, }; -static const struct pmu_event pme_test_soc_sys[] = { +static const struct pmu_event pmu_events__test_soc_sys[] = { { .name = "sys_ddr_pmu.write_cycles", .event = "event=0x2b", @@ -258,8 +258,8 @@ struct pmu_sys_events { static const struct pmu_sys_events pmu_sys_event_tables[] = { { - .table = { pme_test_soc_sys }, - .name = "pme_test_soc_sys", + .table = { pmu_events__test_soc_sys }, + .name = "pmu_events__test_soc_sys", }, { .table = { 0 } -- cgit v1.2.3-58-ga151 From 0e70f50e72860f84759b62dae877c48523d33255 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Tue, 14 Mar 2023 08:41:36 -0300 Subject: perf tools bpf: Add vmlinux.h to .gitignore Now that BPF skel based tools will be built by default if the toolchain pieces that are needed are available, building directly on the source tree will produce a vmlinux.h from the BTF info that needs to get ignored. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/bpf_skel/.gitignore | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/bpf_skel/.gitignore b/tools/perf/util/bpf_skel/.gitignore index 5263e9e6c5d8..cd01455e1b53 100644 --- a/tools/perf/util/bpf_skel/.gitignore +++ b/tools/perf/util/bpf_skel/.gitignore @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only .tmp -*.skel.h \ No newline at end of file +*.skel.h +vmlinux.h -- cgit v1.2.3-58-ga151 From 1f64cfdebfe0494264271e8d7a3a47faf5f58ec7 Mon Sep 17 00:00:00 2001 From: Roman Lozko Date: Fri, 10 Mar 2023 15:04:45 +0000 Subject: perf scripts intel-pt-events.py: Fix IPC output for Python 2 Integers are not converted to floats during division in Python 2 which results in incorrect IPC values. Fix by switching to new division behavior. Fixes: a483e64c0b62e93a ("perf scripting python: intel-pt-events.py: Add --insn-trace and --src-trace") Signed-off-by: Roman Lozko Acked-by: Adrian Hunter Cc: Adrian Hunter Link: https://lore.kernel.org/r/20230310150445.2925841-1-lozko.roma@gmail.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/scripts/python/intel-pt-events.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/scripts/python/intel-pt-events.py b/tools/perf/scripts/python/intel-pt-events.py index 08862a2582f4..1c76368f13c1 100644 --- a/tools/perf/scripts/python/intel-pt-events.py +++ b/tools/perf/scripts/python/intel-pt-events.py @@ -11,7 +11,7 @@ # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for # more details. -from __future__ import print_function +from __future__ import division, print_function import io import os -- cgit v1.2.3-58-ga151 From b720bf90339742ef32b8add76f131f812ed1228a Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 13 Mar 2023 22:33:10 -0700 Subject: perf vendor events intel: Update graniterapids events Update from 1.00 to 1.01, some event description updates. Signed-off-by: Ian Rogers Reviewed-by: Kan Liang Cc: Alexander Shishkin Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230314053312.3237390-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/graniterapids/frontend.json | 2 +- tools/perf/pmu-events/arch/x86/graniterapids/pipeline.json | 4 ++-- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/frontend.json b/tools/perf/pmu-events/arch/x86/graniterapids/frontend.json index dfd9c5ea1584..c6d5016e7337 100644 --- a/tools/perf/pmu-events/arch/x86/graniterapids/frontend.json +++ b/tools/perf/pmu-events/arch/x86/graniterapids/frontend.json @@ -3,7 +3,7 @@ "BriefDescription": "This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations.", "EventCode": "0x9c", "EventName": "IDQ_BUBBLES.CORE", - "PublicDescription": "This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations.\nThe count may be distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the nominator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.", + "PublicDescription": "This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations.\nThe count may be distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.", "SampleAfterValue": "1000003", "UMask": "0x1" } diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/pipeline.json b/tools/perf/pmu-events/arch/x86/graniterapids/pipeline.json index d6aafb258708..764c0435d1d2 100644 --- a/tools/perf/pmu-events/arch/x86/graniterapids/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/graniterapids/pipeline.json @@ -72,7 +72,7 @@ "BriefDescription": "This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions.", "EventCode": "0xa4", "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", - "PublicDescription": "This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions.\nThe count is distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the nominator for the Backend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.", + "PublicDescription": "This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions.\nThe count is distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Backend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.", "SampleAfterValue": "10000003", "UMask": "0x2" }, @@ -95,7 +95,7 @@ "BriefDescription": "This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric.", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.SLOTS", - "PublicDescription": "This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric.\nSoftware can use this event as the nominator for the Retiring metric (or top-level category) of the Top-down Microarchitecture Analysis method.", + "PublicDescription": "This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric.\nSoftware can use this event as the numerator for the Retiring metric (or top-level category) of the Top-down Microarchitecture Analysis method.", "SampleAfterValue": "2000003", "UMask": "0x2" } diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index bb4e545fa100..210dd9b2004f 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -9,7 +9,7 @@ GenuineIntel-6-55-[56789ABCDEF],v1.17,cascadelakex,core GenuineIntel-6-9[6C],v1.03,elkhartlake,core GenuineIntel-6-5[CF],v13,goldmont,core GenuineIntel-6-7A,v1.01,goldmontplus,core -GenuineIntel-6-A[DE],v1.00,graniterapids,core +GenuineIntel-6-A[DE],v1.01,graniterapids,core GenuineIntel-6-(3C|45|46),v32,haswell,core GenuineIntel-6-3F,v26,haswellx,core GenuineIntel-6-(7D|7E|A7),v1.17,icelake,core -- cgit v1.2.3-58-ga151 From 591530c0f5644d5fa8549ab4a738916cb6779dbf Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 13 Mar 2023 22:33:11 -0700 Subject: perf vendor events intel: Update meteorlake events Update from 1.00 to 1.01. Event description updates. Addition of IDQ_BUBBLES.CORE, TOPDOWN.BACKEND_BOUND_SLOTS, UOPS_RETIRED.SLOTS. Signed-off-by: Ian Rogers Reviewed-by: Kan Liang Cc: Alexander Shishkin Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230314053312.3237390-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- .../perf/pmu-events/arch/x86/meteorlake/cache.json | 8 +++++ .../pmu-events/arch/x86/meteorlake/frontend.json | 9 ++++++ .../pmu-events/arch/x86/meteorlake/memory.json | 13 ++++++-- .../perf/pmu-events/arch/x86/meteorlake/other.json | 4 +-- .../pmu-events/arch/x86/meteorlake/pipeline.json | 36 ++++++++++++++++++++-- .../arch/x86/meteorlake/virtual-memory.json | 4 +++ 7 files changed, 69 insertions(+), 7 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 210dd9b2004f..34431709f7d0 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -18,7 +18,7 @@ GenuineIntel-6-3A,v23,ivybridge,core GenuineIntel-6-3E,v22,ivytown,core GenuineIntel-6-2D,v22,jaketown,core GenuineIntel-6-(57|85),v10,knightslanding,core -GenuineIntel-6-A[AC],v1.00,meteorlake,core +GenuineIntel-6-A[AC],v1.01,meteorlake,core GenuineIntel-6-1[AEF],v3,nehalemep,core GenuineIntel-6-2E,v3,nehalemex,core GenuineIntel-6-2A,v18,sandybridge,core diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/cache.json b/tools/perf/pmu-events/arch/x86/meteorlake/cache.json index 0970724a2984..bf24d3f25a3d 100644 --- a/tools/perf/pmu-events/arch/x86/meteorlake/cache.json +++ b/tools/perf/pmu-events/arch/x86/meteorlake/cache.json @@ -3,6 +3,7 @@ "BriefDescription": "L2 code requests", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", + "PublicDescription": "Counts the total number of L2 code requests.", "SampleAfterValue": "200003", "UMask": "0xe4", "Unit": "cpu_core" @@ -11,6 +12,7 @@ "BriefDescription": "Demand Data Read access L2 cache", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.", "SampleAfterValue": "200003", "UMask": "0xe1", "Unit": "cpu_core" @@ -19,6 +21,7 @@ "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", "SampleAfterValue": "200003", "UMask": "0x41", "Unit": "cpu_atom" @@ -27,6 +30,7 @@ "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", "SampleAfterValue": "100003", "UMask": "0x41", "Unit": "cpu_core" @@ -35,6 +39,7 @@ "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", "SampleAfterValue": "200003", "UMask": "0x4f", "Unit": "cpu_atom" @@ -43,6 +48,7 @@ "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", "SampleAfterValue": "100003", "UMask": "0x4f", "Unit": "cpu_core" @@ -53,6 +59,7 @@ "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ALL_LOADS", "PEBS": "1", + "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.", "SampleAfterValue": "1000003", "UMask": "0x81", "Unit": "cpu_core" @@ -63,6 +70,7 @@ "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ALL_STORES", "PEBS": "1", + "PublicDescription": "Counts all retired store instructions.", "SampleAfterValue": "1000003", "UMask": "0x82", "Unit": "cpu_core" diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json b/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json index 7de11819dd0d..66e5609699ea 100644 --- a/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json +++ b/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json @@ -14,5 +14,14 @@ "SampleAfterValue": "200003", "UMask": "0x2", "Unit": "cpu_atom" + }, + { + "BriefDescription": "This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations.", + "EventCode": "0x9c", + "EventName": "IDQ_BUBBLES.CORE", + "PublicDescription": "This event counts a subset of the Topdown Slots event that were no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations.\nThe count may be distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_core" } ] diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/memory.json b/tools/perf/pmu-events/arch/x86/meteorlake/memory.json index b7715cec1dbc..20c2efe70eeb 100644 --- a/tools/perf/pmu-events/arch/x86/meteorlake/memory.json +++ b/tools/perf/pmu-events/arch/x86/meteorlake/memory.json @@ -7,6 +7,7 @@ "MSRIndex": "0x3F6", "MSRValue": "0x80", "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", "SampleAfterValue": "1009", "UMask": "0x1", "Unit": "cpu_core" @@ -19,6 +20,7 @@ "MSRIndex": "0x3F6", "MSRValue": "0x10", "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", "SampleAfterValue": "20011", "UMask": "0x1", "Unit": "cpu_core" @@ -31,6 +33,7 @@ "MSRIndex": "0x3F6", "MSRValue": "0x100", "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", "SampleAfterValue": "503", "UMask": "0x1", "Unit": "cpu_core" @@ -43,6 +46,7 @@ "MSRIndex": "0x3F6", "MSRValue": "0x20", "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", "SampleAfterValue": "100007", "UMask": "0x1", "Unit": "cpu_core" @@ -55,6 +59,7 @@ "MSRIndex": "0x3F6", "MSRValue": "0x4", "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", "SampleAfterValue": "100003", "UMask": "0x1", "Unit": "cpu_core" @@ -67,6 +72,7 @@ "MSRIndex": "0x3F6", "MSRValue": "0x200", "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", "SampleAfterValue": "101", "UMask": "0x1", "Unit": "cpu_core" @@ -79,6 +85,7 @@ "MSRIndex": "0x3F6", "MSRValue": "0x40", "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", "SampleAfterValue": "2003", "UMask": "0x1", "Unit": "cpu_core" @@ -91,6 +98,7 @@ "MSRIndex": "0x3F6", "MSRValue": "0x8", "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", "SampleAfterValue": "50021", "UMask": "0x1", "Unit": "cpu_core" @@ -101,12 +109,13 @@ "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE", "PEBS": "2", + "PublicDescription": "Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8", "SampleAfterValue": "1000003", "UMask": "0x2", "Unit": "cpu_core" }, { - "BriefDescription": "Counts cacheable demand data reads were not supplied by the L3 cache.", + "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -126,7 +135,7 @@ "Unit": "cpu_core" }, { - "BriefDescription": "Counts demand reads for ownership, including SWPREFETCHW which is an RFO were not supplied by the L3 cache.", + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/other.json b/tools/perf/pmu-events/arch/x86/meteorlake/other.json index ae98e3d0e149..14e648bf11c5 100644 --- a/tools/perf/pmu-events/arch/x86/meteorlake/other.json +++ b/tools/perf/pmu-events/arch/x86/meteorlake/other.json @@ -1,6 +1,6 @@ [ { - "BriefDescription": "Counts cacheable demand data reads Catch all value for any response types - this includes response types not define in the OCR. If this is set all other response types will be ignored", + "BriefDescription": "Counts demand data reads that have any type of response.", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -20,7 +20,7 @@ "Unit": "cpu_core" }, { - "BriefDescription": "Counts demand reads for ownership, including SWPREFETCHW which is an RFO Catch all value for any response types - this includes response types not define in the OCR. If this is set all other response types will be ignored", + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json b/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json index 7be7e40c03ac..639789478073 100644 --- a/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json @@ -4,6 +4,7 @@ "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", + "PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for.", "SampleAfterValue": "200003", "Unit": "cpu_atom" }, @@ -12,6 +13,7 @@ "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", + "PublicDescription": "Counts all branch instructions retired.", "SampleAfterValue": "400009", "Unit": "cpu_core" }, @@ -20,6 +22,7 @@ "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", + "PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.", "SampleAfterValue": "200003", "Unit": "cpu_atom" }, @@ -28,6 +31,7 @@ "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", + "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", "SampleAfterValue": "400009", "Unit": "cpu_core" }, @@ -39,7 +43,7 @@ "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of unhalted core clock cycles[This event is alias to CPU_CLK_UNHALTED.THREAD_P]", + "BriefDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.THREAD_P]", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.CORE_P", "SampleAfterValue": "2000003", @@ -55,6 +59,7 @@ { "BriefDescription": "Reference cycles when the core is not in halt state.", "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", "SampleAfterValue": "2000003", "UMask": "0x3", "Unit": "cpu_core" @@ -63,6 +68,7 @@ "BriefDescription": "Reference cycles when the core is not in halt state.", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", + "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", "SampleAfterValue": "2000003", "UMask": "0x1", "Unit": "cpu_core" @@ -77,12 +83,13 @@ { "BriefDescription": "Core cycles when the thread is not in halt state", "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.", "SampleAfterValue": "2000003", "UMask": "0x2", "Unit": "cpu_core" }, { - "BriefDescription": "Counts the number of unhalted core clock cycles[This event is alias to CPU_CLK_UNHALTED.CORE_P]", + "BriefDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.CORE_P]", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000003", @@ -92,6 +99,7 @@ "BriefDescription": "Thread cycles when thread is not in halt state", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", "SampleAfterValue": "2000003", "Unit": "cpu_core" }, @@ -107,6 +115,7 @@ "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", "EventName": "INST_RETIRED.ANY", "PEBS": "1", + "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", "SampleAfterValue": "2000003", "UMask": "0x1", "Unit": "cpu_core" @@ -124,6 +133,7 @@ "EventCode": "0xc0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", + "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", "SampleAfterValue": "2000003", "Unit": "cpu_core" }, @@ -131,13 +141,24 @@ "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", "SampleAfterValue": "100003", "UMask": "0x82", "Unit": "cpu_core" }, + { + "BriefDescription": "This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions.", + "EventCode": "0xa4", + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", + "PublicDescription": "This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions.\nThe count is distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Backend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.", + "SampleAfterValue": "10000003", + "UMask": "0x2", + "Unit": "cpu_core" + }, { "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", "EventName": "TOPDOWN.SLOTS", + "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", "SampleAfterValue": "10000003", "UMask": "0x4", "Unit": "cpu_core" @@ -146,6 +167,7 @@ "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", "EventCode": "0xa4", "EventName": "TOPDOWN.SLOTS_P", + "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", "SampleAfterValue": "10000003", "UMask": "0x1", "Unit": "cpu_core" @@ -154,6 +176,7 @@ "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.ALL", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", "SampleAfterValue": "1000003", "Unit": "cpu_atom" }, @@ -178,5 +201,14 @@ "PEBS": "1", "SampleAfterValue": "1000003", "Unit": "cpu_atom" + }, + { + "BriefDescription": "This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric.", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.SLOTS", + "PublicDescription": "This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric.\nSoftware can use this event as the numerator for the Retiring metric (or top-level category) of the Top-down Microarchitecture Analysis method.", + "SampleAfterValue": "2000003", + "UMask": "0x2", + "Unit": "cpu_core" } ] diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/virtual-memory.json b/tools/perf/pmu-events/arch/x86/meteorlake/virtual-memory.json index 0ee62378bf22..556e4292fcc8 100644 --- a/tools/perf/pmu-events/arch/x86/meteorlake/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/meteorlake/virtual-memory.json @@ -3,6 +3,7 @@ "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "SampleAfterValue": "100003", "UMask": "0xe", "Unit": "cpu_core" @@ -11,6 +12,7 @@ "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "SampleAfterValue": "100003", "UMask": "0xe", "Unit": "cpu_core" @@ -19,6 +21,7 @@ "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.", "SampleAfterValue": "200003", "UMask": "0xe", "Unit": "cpu_atom" @@ -27,6 +30,7 @@ "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", "EventCode": "0x11", "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", "SampleAfterValue": "100003", "UMask": "0xe", "Unit": "cpu_core" -- cgit v1.2.3-58-ga151 From 3da9559e4131a38ab9c38add53d496bc4c7aea27 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 13 Mar 2023 22:33:12 -0700 Subject: perf vendor events intel: Update skylake events Update from v54 to v55. Addition of OFFCORE_RESPONSE, FP_ARITH_INST_RETIRED.SCALAR, FP_ARITH_INST_RETIRED.VECTOR and INT_MISC.CLEARS_COUNT. Signed-off-by: Ian Rogers Reviewed-by: Kan Liang Cc: Alexander Shishkin Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230314053312.3237390-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- tools/perf/pmu-events/arch/x86/skylake/cache.json | 8 ++++++++ .../perf/pmu-events/arch/x86/skylake/floating-point.json | 15 +++++++++++++++ tools/perf/pmu-events/arch/x86/skylake/pipeline.json | 10 ++++++++++ 4 files changed, 34 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 34431709f7d0..9abebe50ae0d 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -24,7 +24,7 @@ GenuineIntel-6-2E,v3,nehalemex,core GenuineIntel-6-2A,v18,sandybridge,core GenuineIntel-6-(8F|CF),v1.11,sapphirerapids,core GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core -GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v54,skylake,core +GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v55,skylake,core GenuineIntel-6-55-[01234],v1.29,skylakex,core GenuineIntel-6-86,v1.20,snowridgex,core GenuineIntel-6-8[CD],v1.10,tigerlake,core diff --git a/tools/perf/pmu-events/arch/x86/skylake/cache.json b/tools/perf/pmu-events/arch/x86/skylake/cache.json index 0080ac27b899..ce592d871949 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/cache.json +++ b/tools/perf/pmu-events/arch/x86/skylake/cache.json @@ -553,6 +553,14 @@ "SampleAfterValue": "2000003", "UMask": "0x4" }, + { + "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts all demand code reads have any response type.", "EventCode": "0xB7, 0xBB", diff --git a/tools/perf/pmu-events/arch/x86/skylake/floating-point.json b/tools/perf/pmu-events/arch/x86/skylake/floating-point.json index eb83fa537e7d..4d494a5cabbf 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/skylake/floating-point.json @@ -31,6 +31,14 @@ "SampleAfterValue": "2000003", "UMask": "0x20" }, + { + "BriefDescription": "Counts once for most SIMD scalar computational floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", + "EventCode": "0xC7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "PublicDescription": "Counts once for most SIMD scalar computational single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, { "BriefDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "EventCode": "0xC7", @@ -47,6 +55,13 @@ "SampleAfterValue": "2000003", "UMask": "0x2" }, + { + "BriefDescription": "Number of any Vector retired FP arithmetic instructions", + "EventCode": "0xC7", + "EventName": "FP_ARITH_INST_RETIRED.VECTOR", + "SampleAfterValue": "2000003", + "UMask": "0xfc" + }, { "BriefDescription": "Cycles with any input/output SSE or FP assist", "CounterMask": "1", diff --git a/tools/perf/pmu-events/arch/x86/skylake/pipeline.json b/tools/perf/pmu-events/arch/x86/skylake/pipeline.json index 2c827d806554..2dfc3af08eff 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/skylake/pipeline.json @@ -404,6 +404,16 @@ "SampleAfterValue": "2000003", "UMask": "0x1" }, + { + "AnyThread": "1", + "BriefDescription": "Clears speculative count", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.CLEARS_COUNT", + "PublicDescription": "Counts the number of speculative clears due to any type of branch misprediction or machine clears", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, { "BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.", "EventCode": "0x0D", -- cgit v1.2.3-58-ga151 From bdecfecac8aba6ca5e2fde8f09b4fba1d1326997 Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Mon, 13 Mar 2023 09:01:58 +0100 Subject: perf vendor events s390: Add cache metrics for z15 Add metrics for s390 z15 - Percentage sourced from Level 2 cache - Percentage sourced from Level 3 on same chip cache - Percentage sourced from Level 4 Local cache on same book - Percentage sourced from Level 4 Remote cache on different book - Percentage sourced from memory For details about the formulas see this documentation: https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf Outpuf after: # ./perf stat -M l4rp -- find / .... find output deleted Performance counter stats for 'find /': 5 L1I_OFFDRAWER_L4_SOURCED_WRITES # 0.01 l4rp 187 L1D_OFFDRAWER_L4_SOURCED_WRITES 0 L1I_OFFDRAWER_L3_SOURCED_WRITES 231,333,165 L1I_DIR_WRITES 3,303 L1D_OFFDRAWER_L3_SOURCED_WRITES 47,461 L1D_OFFDRAWER_L3_SOURCED_WRITES_IV 0 L1I_OFFDRAWER_L3_SOURCED_WRITES_IV 126,706,244 L1D_DIR_WRITES 27.870355461 seconds time elapsed 0.521562000 seconds user 12.494503000 seconds sys # Signed-off-by: Thomas Richter Acked-By: Sumanth Korikkar Acked-by: Ian Rogers Cc: Heiko Carstens Cc: Sven Schnelle Cc: Vasily Gorbik Link: https://lore.kernel.org/r/20230313080201.2440201-3-tmricht@linux.ibm.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/s390/cf_z15/transaction.json | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json index 86bf83b4504e..cca237bdb7ba 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json @@ -18,5 +18,30 @@ "BriefDescription": "Level One Miss per 100 Instructions", "MetricName": "l1mp", "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 2 cache", + "MetricName": "l2p", + "MetricExpr": "((L1D_L2D_SOURCED_WRITES + L1I_L2I_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 3 on same chip cache", + "MetricName": "l3p", + "MetricExpr": "((L1D_ONCHIP_L3_SOURCED_WRITES + L1D_ONCHIP_L3_SOURCED_WRITES_IV + L1I_ONCHIP_L3_SOURCED_WRITES + L1I_ONCHIP_L3_SOURCED_WRITES_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 4 Local cache on same book", + "MetricName": "l4lp", + "MetricExpr": "((L1D_ONCLUSTER_L3_SOURCED_WRITES + L1D_ONCLUSTER_L3_SOURCED_WRITES_IV + L1D_ONDRAWER_L4_SOURCED_WRITES + L1I_ONCLUSTER_L3_SOURCED_WRITES + L1I_ONCLUSTER_L3_SOURCED_WRITES_IV + L1I_ONDRAWER_L4_SOURCED_WRITES + L1D_OFFCLUSTER_L3_SOURCED_WRITES + L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV + L1D_ONCHIP_L3_SOURCED_WRITES_RO + L1I_OFFCLUSTER_L3_SOURCED_WRITES + L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 4 Remote cache on different book", + "MetricName": "l4rp", + "MetricExpr": "((L1D_OFFDRAWER_L3_SOURCED_WRITES + L1D_OFFDRAWER_L3_SOURCED_WRITES_IV + L1D_OFFDRAWER_L4_SOURCED_WRITES + L1I_OFFDRAWER_L3_SOURCED_WRITES + L1I_OFFDRAWER_L3_SOURCED_WRITES_IV + L1I_OFFDRAWER_L4_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from memory", + "MetricName": "memp", + "MetricExpr": "((L1D_ONCHIP_MEMORY_SOURCED_WRITES + L1D_ONCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFDRAWER_MEMORY_SOURCED_WRITES + L1I_ONCHIP_MEMORY_SOURCED_WRITES + L1I_ONCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFDRAWER_MEMORY_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" } ] -- cgit v1.2.3-58-ga151 From add7894a25d1c572b2e472557f2b1150dbc991ee Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Mon, 13 Mar 2023 09:01:59 +0100 Subject: perf vendor events s390: Add cache metrics for z14 Add metrics for s390 z14 - Percentage sourced from Level 2 cache - Percentage sourced from Level 3 on same chip cache - Percentage sourced from Level 4 Local cache on same book - Percentage sourced from Level 4 Remote cache on different book - Percentage sourced from memory For details about the formulas see this documentation: https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf Output after: # ./perf stat -M l4rp -- find / .... find output deleted Performance counter stats for 'find /': 0 L1I_OFFDRAWER_L4_SOURCED_WRITES # 0.01 l4rp 84 L1D_OFFDRAWER_L4_SOURCED_WRITES 0 L1I_OFFDRAWER_L3_SOURCED_WRITES 71,535,353 L1I_DIR_WRITES 219 L1D_OFFDRAWER_L3_SOURCED_WRITES 16,436 L1D_OFFDRAWER_L3_SOURCED_WRITES_IV 0 L1I_OFFDRAWER_L3_SOURCED_WRITES_IV 46,343,940 L1D_DIR_WRITES 10.530805537 seconds time elapsed 0.774396000 seconds user 1.602714000 seconds sys # Signed-off-by: Thomas Richter Acked-by: Ian Rogers Acked-By: Sumanth Korikkar Cc: Heiko Carstens Cc: Sven Schnelle Cc: Vasily Gorbik Link: https://lore.kernel.org/r/20230313080201.2440201-3-tmricht@linux.ibm.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/s390/cf_z14/transaction.json | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json index 86bf83b4504e..cca237bdb7ba 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json @@ -18,5 +18,30 @@ "BriefDescription": "Level One Miss per 100 Instructions", "MetricName": "l1mp", "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 2 cache", + "MetricName": "l2p", + "MetricExpr": "((L1D_L2D_SOURCED_WRITES + L1I_L2I_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 3 on same chip cache", + "MetricName": "l3p", + "MetricExpr": "((L1D_ONCHIP_L3_SOURCED_WRITES + L1D_ONCHIP_L3_SOURCED_WRITES_IV + L1I_ONCHIP_L3_SOURCED_WRITES + L1I_ONCHIP_L3_SOURCED_WRITES_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 4 Local cache on same book", + "MetricName": "l4lp", + "MetricExpr": "((L1D_ONCLUSTER_L3_SOURCED_WRITES + L1D_ONCLUSTER_L3_SOURCED_WRITES_IV + L1D_ONDRAWER_L4_SOURCED_WRITES + L1I_ONCLUSTER_L3_SOURCED_WRITES + L1I_ONCLUSTER_L3_SOURCED_WRITES_IV + L1I_ONDRAWER_L4_SOURCED_WRITES + L1D_OFFCLUSTER_L3_SOURCED_WRITES + L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV + L1D_ONCHIP_L3_SOURCED_WRITES_RO + L1I_OFFCLUSTER_L3_SOURCED_WRITES + L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 4 Remote cache on different book", + "MetricName": "l4rp", + "MetricExpr": "((L1D_OFFDRAWER_L3_SOURCED_WRITES + L1D_OFFDRAWER_L3_SOURCED_WRITES_IV + L1D_OFFDRAWER_L4_SOURCED_WRITES + L1I_OFFDRAWER_L3_SOURCED_WRITES + L1I_OFFDRAWER_L3_SOURCED_WRITES_IV + L1I_OFFDRAWER_L4_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from memory", + "MetricName": "memp", + "MetricExpr": "((L1D_ONCHIP_MEMORY_SOURCED_WRITES + L1D_ONCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFDRAWER_MEMORY_SOURCED_WRITES + L1I_ONCHIP_MEMORY_SOURCED_WRITES + L1I_ONCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFDRAWER_MEMORY_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" } ] -- cgit v1.2.3-58-ga151 From 850eea236f8ad4a648cb7997eed8a3c616cc0678 Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Mon, 13 Mar 2023 09:02:00 +0100 Subject: perf vendor events s390: Add cache metrics for z13 Add metrics for s390 z13 - Percentage sourced from Level 2 cache - Percentage sourced from Level 3 on same chip cache - Percentage sourced from Level 4 Local cache on same book - Percentage sourced from Level 4 Remote cache on different book - Percentage sourced from memory For details about the formulas see this documentation: https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf Output after: # ./perf stat -M l4rp -- find / ...find output deleted Performance counter stats for 'find /': 2 L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES # 0.02 l4rp 252 L1D_ONDRAWER_L4_SOURCED_WRITES 3,465 L1D_ONDRAWER_L3_SOURCED_WRITES_IV 80 L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES 761 L1D_ONDRAWER_L3_SOURCED_WRITES 0 L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES 131,817,067 L1I_DIR_WRITES 1 L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES 447 L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES 22 L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES 7 L1I_ONDRAWER_L4_SOURCED_WRITES 0 L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES 1,071 L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES 3 L1I_ONDRAWER_L3_SOURCED_WRITES 13,352 L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV 15,252 L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV 0 L1I_ONDRAWER_L3_SOURCED_WRITES_IV 0 L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV 57,431,083 L1D_DIR_WRITES 0 L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV 15.386502874 seconds time elapsed 0.647348000 seconds user 3.537041000 seconds sys # Signed-off-by: Thomas Richter Acked-By: Sumanth Korikkar Cc: Heiko Carstens Cc: Sven Schnelle Cc: Vasily Gorbik Link: https://lore.kernel.org/r/20230313080201.2440201-3-tmricht@linux.ibm.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/s390/cf_z13/transaction.json | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json index 86bf83b4504e..71e2c7fa734c 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json @@ -18,5 +18,30 @@ "BriefDescription": "Level One Miss per 100 Instructions", "MetricName": "l1mp", "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 2 cache", + "MetricName": "l2p", + "MetricExpr": "((L1D_L2D_SOURCED_WRITES + L1I_L2I_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 3 on same chip cache", + "MetricName": "l3p", + "MetricExpr": "((L1D_ONCHIP_L3_SOURCED_WRITES + L1D_ONCHIP_L3_SOURCED_WRITES_IV + L1I_ONCHIP_L3_SOURCED_WRITES + L1I_ONCHIP_L3_SOURCED_WRITES_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 4 Local cache on same book", + "MetricName": "l4lp", + "MetricExpr": "((L1D_ONNODE_L4_SOURCED_WRITES + L1D_ONNODE_L3_SOURCED_WRITES_IV + L1D_ONNODE_L3_SOURCED_WRITES + L1I_ONNODE_L4_SOURCED_WRITES + L1I_ONNODE_L3_SOURCED_WRITES_IV + L1I_ONNODE_L3_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 4 Remote cache on different book", + "MetricName": "l4rp", + "MetricExpr": "((L1D_ONDRAWER_L4_SOURCED_WRITES + L1D_ONDRAWER_L3_SOURCED_WRITES_IV + L1D_ONDRAWER_L3_SOURCED_WRITES + L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES + L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV + L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES + L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES + L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV + L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES + L1I_ONDRAWER_L4_SOURCED_WRITES + L1I_ONDRAWER_L3_SOURCED_WRITES_IV + L1I_ONDRAWER_L3_SOURCED_WRITES + L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES + L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV + L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES + L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES + L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV + L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from memory", + "MetricName": "memp", + "MetricExpr": "((L1D_ONNODE_MEM_SOURCED_WRITES + L1D_ONDRAWER_MEM_SOURCED_WRITES + L1D_OFFDRAWER_MEM_SOURCED_WRITES + L1D_ONCHIP_MEM_SOURCED_WRITES + L1I_ONNODE_MEM_SOURCED_WRITES + L1I_ONDRAWER_MEM_SOURCED_WRITES + L1I_OFFDRAWER_MEM_SOURCED_WRITES + L1I_ONCHIP_MEM_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" } ] -- cgit v1.2.3-58-ga151 From 4c290d4fa3aeed74e37637acaa1a787f194fe43d Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Mon, 13 Mar 2023 09:02:01 +0100 Subject: perf vendor events s390: Add metric for TLB and cache Add metrics for tlb and cache statistics: - finite_cpi: Cycles per Instructions from Finite cache/memory - est_cpi: Estimated Instruction Complexity CPI infinite Level 1 - scpl1m: Estimated Sourcing Cycles per Level 1 Miss - tlb_percent: Estimated TLB CPU percentage of Total CPU - tlb_miss: Estimated Cycles per TLB Miss For details about the formulas see this documentation: https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf Output after: # ./perf stat -M tlb_miss -- dd if=/dev/zero of=/dev/null bs=1M count=10K ... dd output removed Performance counter stats for 'dd if=/dev/zero of=/dev/null bs=1M count=10K': 667,726 DTLB2_MISSES # 440.96 tlb_miss 198 ITLB2_WRITES 795,170,260 L1C_TLB2_MISSES 9,478 ITLB2_MISSES 820 DTLB2_WRITES 1,197,126,869 L1D_PENALTY_CYCLES 2,457,447 L1I_PENALTY_CYCLES 1.249342187 seconds time elapsed 0.001030000 seconds user 1.248105000 seconds sys # Signed-off-by: Thomas Richter Acked-by: Ian Rogers Acked-By: Sumanth Korikkar Cc: Heiko Carstens Cc: Sven Schnelle Cc: Vasily Gorbik Link: https://lore.kernel.org/r/20230313080201.2440201-3-tmricht@linux.ibm.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/s390/cf_z13/transaction.json | 30 ++++++++++++++++++++++ .../pmu-events/arch/s390/cf_z14/transaction.json | 25 ++++++++++++++++++ .../pmu-events/arch/s390/cf_z15/transaction.json | 25 ++++++++++++++++++ .../pmu-events/arch/s390/cf_z16/transaction.json | 25 ++++++++++++++++++ 4 files changed, 105 insertions(+) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json index 71e2c7fa734c..b941a7212a4d 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json @@ -43,5 +43,35 @@ "BriefDescription": "Percentage sourced from memory", "MetricName": "memp", "MetricExpr": "((L1D_ONNODE_MEM_SOURCED_WRITES + L1D_ONDRAWER_MEM_SOURCED_WRITES + L1D_OFFDRAWER_MEM_SOURCED_WRITES + L1D_ONCHIP_MEM_SOURCED_WRITES + L1I_ONNODE_MEM_SOURCED_WRITES + L1I_ONDRAWER_MEM_SOURCED_WRITES + L1I_OFFDRAWER_MEM_SOURCED_WRITES + L1I_ONCHIP_MEM_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Cycles per Instructions from Finite cache/memory", + "MetricName": "finite_cpi", + "MetricExpr": "L1C_TLB1_MISSES / INSTRUCTIONS" + }, + { + "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1", + "MetricName": "est_cpi", + "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB1_MISSES / INSTRUCTIONS)" + }, + { + "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss", + "MetricName": "scpl1m", + "MetricExpr": "L1C_TLB1_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)" + }, + { + "BriefDescription": "Estimated TLB CPU percentage of Total CPU", + "MetricName": "tlb_percent", + "MetricExpr": "((DTLB1_MISSES + ITLB1_MISSES) / CPU_CYCLES) * (L1C_TLB1_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100" + }, + { + "BriefDescription": "Estimated Cycles per TLB Miss", + "MetricName": "tlb_miss", + "MetricExpr": "((DTLB1_MISSES + ITLB1_MISSES) / (DTLB1_WRITES + ITLB1_WRITES)) * (L1C_TLB1_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))" + }, + { + "BriefDescription": "Page Table Entry misses", + "MetricName": "pte_miss", + "MetricExpr": "(TLB2_PTE_WRITES / (DTLB1_WRITES + ITLB1_WRITES)) * 100" } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json index cca237bdb7ba..ce814ea93396 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json @@ -43,5 +43,30 @@ "BriefDescription": "Percentage sourced from memory", "MetricName": "memp", "MetricExpr": "((L1D_ONCHIP_MEMORY_SOURCED_WRITES + L1D_ONCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFDRAWER_MEMORY_SOURCED_WRITES + L1I_ONCHIP_MEMORY_SOURCED_WRITES + L1I_ONCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFDRAWER_MEMORY_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Cycles per Instructions from Finite cache/memory", + "MetricName": "finite_cpi", + "MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS" + }, + { + "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1", + "MetricName": "est_cpi", + "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)" + }, + { + "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss", + "MetricName": "scpl1m", + "MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)" + }, + { + "BriefDescription": "Estimated TLB CPU percentage of Total CPU", + "MetricName": "tlb_percent", + "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100" + }, + { + "BriefDescription": "Estimated Cycles per TLB Miss", + "MetricName": "tlb_miss", + "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))" } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json index cca237bdb7ba..ce814ea93396 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json @@ -43,5 +43,30 @@ "BriefDescription": "Percentage sourced from memory", "MetricName": "memp", "MetricExpr": "((L1D_ONCHIP_MEMORY_SOURCED_WRITES + L1D_ONCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFDRAWER_MEMORY_SOURCED_WRITES + L1I_ONCHIP_MEMORY_SOURCED_WRITES + L1I_ONCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFDRAWER_MEMORY_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Cycles per Instructions from Finite cache/memory", + "MetricName": "finite_cpi", + "MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS" + }, + { + "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1", + "MetricName": "est_cpi", + "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)" + }, + { + "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss", + "MetricName": "scpl1m", + "MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)" + }, + { + "BriefDescription": "Estimated TLB CPU percentage of Total CPU", + "MetricName": "tlb_percent", + "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100" + }, + { + "BriefDescription": "Estimated Cycles per TLB Miss", + "MetricName": "tlb_miss", + "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))" } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json index dde0735a7d22..ec2ff78e2b5f 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json @@ -43,5 +43,30 @@ "BriefDescription": "Percentage sourced from memory", "MetricName": "memp", "MetricExpr": "((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Cycles per Instructions from Finite cache/memory", + "MetricName": "finite_cpi", + "MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS" + }, + { + "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1", + "MetricName": "est_cpi", + "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)" + }, + { + "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss", + "MetricName": "scpl1m", + "MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)" + }, + { + "BriefDescription": "Estimated TLB CPU percentage of Total CPU", + "MetricName": "tlb_percent", + "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100" + }, + { + "BriefDescription": "Estimated Cycles per TLB Miss", + "MetricName": "tlb_miss", + "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))" } ] -- cgit v1.2.3-58-ga151 From 80c3a7d9f20401169283b5670dbb8d7ac07a1d55 Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Wed, 15 Mar 2023 10:43:21 +0200 Subject: perf script: Fix Python support when no libtraceevent Python scripting can be used without libtraceevent. In particular, scripting for Intel PT does not use tracepoints, and so does not need libtraceevent support. Alter the build and employ conditional compilation to allow Python scripting without libtraceevent. Example: Before: $ ldd `which perf` | grep -i python $ ldd `which perf` | grep -i libtraceevent $ perf record -e intel_pt//u uname Linux [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.031 MB perf.data ] $ perf script intel-pt-events.py |& head -3 Error: Couldn't find script `intel-pt-events.py' See perf script -l for available scripts. After: $ ldd `which perf` | grep -i python libpython3.10.so.1.0 => /lib/x86_64-linux-gnu/libpython3.10.so.1.0 (0x00007f4bac400000) $ ldd `which perf` | grep -i libtraceevent $ perf script intel-pt-events.py | head Intel PT Branch Trace, Power Events, Event Trace and PTWRITE Switch In 8021/8021 [000] 11234.097713404 0/0 perf-exec 8021/8021 [000] 11234.098041726 psb offset: 0x0 0 [unknown] ([unknown]) perf-exec 8021/8021 [000] 11234.098041726 cbr 45 freq: 4505 MHz (161%) 0 [unknown] ([unknown]) uname 8021/8021 [000] 11234.098082170 branches:uH tr strt 0 [unknown] ([unknown]) => 7f3a8b9422b0 _start+0x0 (/usr/lib/x86_64-linux-gnu/ld-linux-x86-64.so.2) uname 8021/8021 [000] 11234.098082379 branches:uH tr end 7f3a8b9422b0 _start+0x0 (/usr/lib/x86_64-linux-gnu/ld-linux-x86-64.so.2) => 0 [unknown] ([unknown]) uname 8021/8021 [000] 11234.098083629 branches:uH tr strt 0 [unknown] ([unknown]) => 7f3a8b9422b0 _start+0x0 (/usr/lib/x86_64-linux-gnu/ld-linux-x86-64.so.2) uname 8021/8021 [000] 11234.098083629 branches:uH call 7f3a8b9422b3 _start+0x3 (/usr/lib/x86_64-linux-gnu/ld-linux-x86-64.so.2) => 7f3a8b943050 _dl_start+0x0 (/usr/lib/x86_64-linux-gnu/ld-linux-x86-64.so.2) uname 8021/8021 [000] 11234.098083837 branches:uH tr end 7f3a8b943060 _dl_start+0x10 (/usr/lib/x86_64-linux-gnu/ld-linux-x86-64.so.2) => 0 [unknown] ([unknown]) IPC: 0.01 (9/938) uname 8021/8021 [000] 11234.098084670 branches:uH tr strt 0 [unknown] ([unknown]) => 7f3a8b943060 _dl_start+0x10 (/usr/lib/x86_64-linux-gnu/ld-linux-x86-64.so.2) Fixes: 378ef0f5d9d7f465 ("perf build: Use libtraceevent from the system") Signed-off-by: Adrian Hunter Cc: Ian Rogers Cc: Jiri Olsa Cc: Namhyung Kim Link: https://lore.kernel.org/r/20230315084321.14563-1-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Build | 2 +- tools/perf/builtin-script.c | 2 +- tools/perf/scripts/Build | 4 +- tools/perf/scripts/python/Perf-Trace-Util/Build | 2 +- .../perf/scripts/python/Perf-Trace-Util/Context.c | 4 ++ tools/perf/util/Build | 2 +- tools/perf/util/scripting-engines/Build | 2 +- .../util/scripting-engines/trace-event-python.c | 75 +++++++++++++++------- tools/perf/util/trace-event-scripting.c | 9 ++- 9 files changed, 72 insertions(+), 30 deletions(-) (limited to 'tools') diff --git a/tools/perf/Build b/tools/perf/Build index 6dd67e502295..aa7623622834 100644 --- a/tools/perf/Build +++ b/tools/perf/Build @@ -56,6 +56,6 @@ CFLAGS_builtin-report.o += -DDOCDIR="BUILD_STR($(srcdir_SQ)/Documentation)" perf-y += util/ perf-y += arch/ perf-y += ui/ -perf-$(CONFIG_LIBTRACEEVENT) += scripts/ +perf-y += scripts/ gtk-y += ui/gtk/ diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index 522226114263..976f8bfe099c 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -2313,8 +2313,8 @@ static void setup_scripting(void) { #ifdef HAVE_LIBTRACEEVENT setup_perl_scripting(); - setup_python_scripting(); #endif + setup_python_scripting(); } static int flush_scripting(void) diff --git a/tools/perf/scripts/Build b/tools/perf/scripts/Build index 68d4b54574ad..7d8e2e57faac 100644 --- a/tools/perf/scripts/Build +++ b/tools/perf/scripts/Build @@ -1,2 +1,4 @@ -perf-$(CONFIG_LIBPERL) += perl/Perf-Trace-Util/ +ifeq ($(CONFIG_LIBTRACEEVENT),y) + perf-$(CONFIG_LIBPERL) += perl/Perf-Trace-Util/ +endif perf-$(CONFIG_LIBPYTHON) += python/Perf-Trace-Util/ diff --git a/tools/perf/scripts/python/Perf-Trace-Util/Build b/tools/perf/scripts/python/Perf-Trace-Util/Build index d5fed4e42617..7d0e33ce6aba 100644 --- a/tools/perf/scripts/python/Perf-Trace-Util/Build +++ b/tools/perf/scripts/python/Perf-Trace-Util/Build @@ -1,3 +1,3 @@ -perf-$(CONFIG_LIBTRACEEVENT) += Context.o +perf-y += Context.o CFLAGS_Context.o += $(PYTHON_EMBED_CCOPTS) -Wno-redundant-decls -Wno-strict-prototypes -Wno-unused-parameter -Wno-nested-externs diff --git a/tools/perf/scripts/python/Perf-Trace-Util/Context.c b/tools/perf/scripts/python/Perf-Trace-Util/Context.c index 895f5fc23965..b0d449f41650 100644 --- a/tools/perf/scripts/python/Perf-Trace-Util/Context.c +++ b/tools/perf/scripts/python/Perf-Trace-Util/Context.c @@ -59,6 +59,7 @@ static struct scripting_context *get_scripting_context(PyObject *args) return get_args(args, "context", NULL); } +#ifdef HAVE_LIBTRACEEVENT static PyObject *perf_trace_context_common_pc(PyObject *obj, PyObject *args) { struct scripting_context *c = get_scripting_context(args); @@ -90,6 +91,7 @@ static PyObject *perf_trace_context_common_lock_depth(PyObject *obj, return Py_BuildValue("i", common_lock_depth(c)); } +#endif static PyObject *perf_sample_insn(PyObject *obj, PyObject *args) { @@ -178,12 +180,14 @@ static PyObject *perf_sample_srccode(PyObject *obj, PyObject *args) } static PyMethodDef ContextMethods[] = { +#ifdef HAVE_LIBTRACEEVENT { "common_pc", perf_trace_context_common_pc, METH_VARARGS, "Get the common preempt count event field value."}, { "common_flags", perf_trace_context_common_flags, METH_VARARGS, "Get the common flags event field value."}, { "common_lock_depth", perf_trace_context_common_lock_depth, METH_VARARGS, "Get the common lock depth event field value."}, +#endif { "perf_sample_insn", perf_sample_insn, METH_VARARGS, "Get the machine code instruction."}, { "perf_set_itrace_options", perf_set_itrace_options, diff --git a/tools/perf/util/Build b/tools/perf/util/Build index 8607575183a9..0806bc0361ad 100644 --- a/tools/perf/util/Build +++ b/tools/perf/util/Build @@ -78,7 +78,7 @@ perf-y += pmu-bison.o perf-y += pmu-hybrid.o perf-y += svghelper.o perf-$(CONFIG_LIBTRACEEVENT) += trace-event-info.o -perf-$(CONFIG_LIBTRACEEVENT) += trace-event-scripting.o +perf-y += trace-event-scripting.o perf-$(CONFIG_LIBTRACEEVENT) += trace-event.o perf-$(CONFIG_LIBTRACEEVENT) += trace-event-parse.o perf-$(CONFIG_LIBTRACEEVENT) += trace-event-read.o diff --git a/tools/perf/util/scripting-engines/Build b/tools/perf/util/scripting-engines/Build index 2c96aa3cc1ec..c220fec97032 100644 --- a/tools/perf/util/scripting-engines/Build +++ b/tools/perf/util/scripting-engines/Build @@ -1,7 +1,7 @@ ifeq ($(CONFIG_LIBTRACEEVENT),y) perf-$(CONFIG_LIBPERL) += trace-event-perl.o - perf-$(CONFIG_LIBPYTHON) += trace-event-python.o endif +perf-$(CONFIG_LIBPYTHON) += trace-event-python.o CFLAGS_trace-event-perl.o += $(PERL_EMBED_CCOPTS) -Wno-redundant-decls -Wno-strict-prototypes -Wno-unused-parameter -Wno-shadow -Wno-nested-externs -Wno-undef -Wno-switch-default -Wno-bad-function-cast -Wno-declaration-after-statement -Wno-switch-enum diff --git a/tools/perf/util/scripting-engines/trace-event-python.c b/tools/perf/util/scripting-engines/trace-event-python.c index 2c2697c5d025..0f4ef61f2ffa 100644 --- a/tools/perf/util/scripting-engines/trace-event-python.c +++ b/tools/perf/util/scripting-engines/trace-event-python.c @@ -30,7 +30,9 @@ #include #include #include +#ifdef HAVE_LIBTRACEEVENT #include +#endif #include "../build-id.h" #include "../counts.h" @@ -87,18 +89,21 @@ PyMODINIT_FUNC initperf_trace_context(void); PyMODINIT_FUNC PyInit_perf_trace_context(void); #endif +#ifdef HAVE_LIBTRACEEVENT #define TRACE_EVENT_TYPE_MAX \ ((1 << (sizeof(unsigned short) * 8)) - 1) static DECLARE_BITMAP(events_defined, TRACE_EVENT_TYPE_MAX); -#define MAX_FIELDS 64 #define N_COMMON_FIELDS 7 -extern struct scripting_context *scripting_context; - static char *cur_field_name; static int zero_flag_atom; +#endif + +#define MAX_FIELDS 64 + +extern struct scripting_context *scripting_context; static PyObject *main_module, *main_dict; @@ -153,6 +158,26 @@ static PyObject *get_handler(const char *handler_name) return handler; } +static void call_object(PyObject *handler, PyObject *args, const char *die_msg) +{ + PyObject *retval; + + retval = PyObject_CallObject(handler, args); + if (retval == NULL) + handler_call_die(die_msg); + Py_DECREF(retval); +} + +static void try_call_object(const char *handler_name, PyObject *args) +{ + PyObject *handler; + + handler = get_handler(handler_name); + if (handler) + call_object(handler, args, handler_name); +} + +#ifdef HAVE_LIBTRACEEVENT static int get_argument_count(PyObject *handler) { int arg_count = 0; @@ -181,25 +206,6 @@ static int get_argument_count(PyObject *handler) return arg_count; } -static void call_object(PyObject *handler, PyObject *args, const char *die_msg) -{ - PyObject *retval; - - retval = PyObject_CallObject(handler, args); - if (retval == NULL) - handler_call_die(die_msg); - Py_DECREF(retval); -} - -static void try_call_object(const char *handler_name, PyObject *args) -{ - PyObject *handler; - - handler = get_handler(handler_name); - if (handler) - call_object(handler, args, handler_name); -} - static void define_value(enum tep_print_arg_type field_type, const char *ev_name, const char *field_name, @@ -379,6 +385,7 @@ static PyObject *get_field_numeric_entry(struct tep_event *event, obj = list; return obj; } +#endif static const char *get_dsoname(struct map *map) { @@ -906,6 +913,7 @@ static PyObject *get_perf_sample_dict(struct perf_sample *sample, return dict; } +#ifdef HAVE_LIBTRACEEVENT static void python_process_tracepoint(struct perf_sample *sample, struct evsel *evsel, struct addr_location *al, @@ -1035,6 +1043,16 @@ static void python_process_tracepoint(struct perf_sample *sample, Py_DECREF(t); } +#else +static void python_process_tracepoint(struct perf_sample *sample __maybe_unused, + struct evsel *evsel __maybe_unused, + struct addr_location *al __maybe_unused, + struct addr_location *addr_al __maybe_unused) +{ + fprintf(stderr, "Tracepoint events are not supported because " + "perf is not linked with libtraceevent.\n"); +} +#endif static PyObject *tuple_new(unsigned int sz) { @@ -1965,6 +1983,7 @@ static int python_stop_script(void) return 0; } +#ifdef HAVE_LIBTRACEEVENT static int python_generate_script(struct tep_handle *pevent, const char *outfile) { int i, not_first, count, nr_events; @@ -2155,6 +2174,18 @@ static int python_generate_script(struct tep_handle *pevent, const char *outfile return 0; } +#else +static int python_generate_script(struct tep_handle *pevent __maybe_unused, + const char *outfile __maybe_unused) +{ + fprintf(stderr, "Generating Python perf-script is not supported." + " Install libtraceevent and rebuild perf to enable it.\n" + "For example:\n # apt install libtraceevent-dev (ubuntu)" + "\n # yum install libtraceevent-devel (Fedora)" + "\n etc.\n"); + return -1; +} +#endif struct scripting_ops python_scripting_ops = { .name = "Python", diff --git a/tools/perf/util/trace-event-scripting.c b/tools/perf/util/trace-event-scripting.c index 56175c53f9af..bd0000300c77 100644 --- a/tools/perf/util/trace-event-scripting.c +++ b/tools/perf/util/trace-event-scripting.c @@ -9,7 +9,9 @@ #include #include #include +#ifdef HAVE_LIBTRACEEVENT #include +#endif #include "debug.h" #include "trace-event.h" @@ -27,10 +29,11 @@ void scripting_context__update(struct scripting_context *c, struct addr_location *addr_al) { c->event_data = sample->raw_data; + c->pevent = NULL; +#ifdef HAVE_LIBTRACEEVENT if (evsel->tp_format) c->pevent = evsel->tp_format->tep; - else - c->pevent = NULL; +#endif c->event = event; c->sample = sample; c->evsel = evsel; @@ -122,6 +125,7 @@ void setup_python_scripting(void) } #endif +#ifdef HAVE_LIBTRACEEVENT static void print_perl_unsupported_msg(void) { fprintf(stderr, "Perl scripting not supported." @@ -186,3 +190,4 @@ void setup_perl_scripting(void) register_perl_scripting(&perl_scripting_ops); } #endif +#endif -- cgit v1.2.3-58-ga151 From 6e57f69f23d02b8c67d7428ee708b7d903ed22b2 Mon Sep 17 00:00:00 2001 From: liuwenyu Date: Wed, 15 Mar 2023 14:42:17 +0800 Subject: perf top: Fix rare segfault in thread__comm_len() In thread__comm_len(),strlen() is called outside of the thread->comm_lock critical section,which may cause a UAF problems if comm__free() is called by the process_thread concurrently. backtrace of the core file is as follows: (gdb) bt #0 __strlen_evex () at ../sysdeps/x86_64/multiarch/strlen-evex.S:77 #1 0x000055ad15d31de5 in thread__comm_len (thread=0x7f627d20e300) at util/thread.c:320 #2 0x000055ad15d4fade in hists__calc_col_len (h=0x7f627d295940, hists=0x55ad1772bfe0) at util/hist.c:103 #3 hists__calc_col_len (hists=0x55ad1772bfe0, h=0x7f627d295940) at util/hist.c:79 #4 0x000055ad15d52c8c in output_resort (hists=hists@entry=0x55ad1772bfe0, prog=0x0, use_callchain=false, cb=cb@entry=0x0, cb_arg=0x0) at util/hist.c:1926 #5 0x000055ad15d530a4 in evsel__output_resort_cb (evsel=evsel@entry=0x55ad1772bde0, prog=prog@entry=0x0, cb=cb@entry=0x0, cb_arg=cb_arg@entry=0x0) at util/hist.c:1945 #6 0x000055ad15d53110 in evsel__output_resort (evsel=evsel@entry=0x55ad1772bde0, prog=prog@entry=0x0) at util/hist.c:1950 #7 0x000055ad15c6ae9a in perf_top__resort_hists (t=t@entry=0x7ffcd9cbf4f0) at builtin-top.c:311 #8 0x000055ad15c6cc6d in perf_top__print_sym_table (top=0x7ffcd9cbf4f0) at builtin-top.c:346 #9 display_thread (arg=0x7ffcd9cbf4f0) at builtin-top.c:700 #10 0x00007f6282fab4fa in start_thread (arg=) at pthread_create.c:443 #11 0x00007f628302e200 in clone3 () at ../sysdeps/unix/sysv/linux/x86_64/clone3.S:81 The reason is that strlen() get a pointer to a memory that has been freed. The string pointer is stored in the structure comm_str, which corresponds to a rb_tree node,when the node is erased, the memory of the string is also freed. In thread__comm_len(),it gets the pointer within the thread->comm_lock critical section, but passed to strlen() outside of the thread->comm_lock critical section, and the perf process_thread may called comm__free() concurrently, cause this segfault problem. The process is as follows: display_thread process_thread -------------- -------------- thread__comm_len -> thread__comm_str # held the comm read lock -> __thread__comm_str(thread) # release the comm read lock thread__delete # held the comm write lock -> comm__free -> comm_str__put(comm->comm_str) -> zfree(&cs->str) # release the comm write lock # The memory of the string pointed to by comm has been free. -> thread->comm_len = strlen(comm); This patch expand the critical section range of thread->comm_lock in thread__comm_len(), to make strlen() called safe. Signed-off-by: Wenyu Liu Acked-by: Namhyung Kim Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Christian Brauner Cc: Feilong Lin Cc: Hewenliang Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Yunfeng Ye Link: https://lore.kernel.org/r/322bfb49-840b-f3b6-9ef1-f9ec3435b07e@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/thread.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/thread.c b/tools/perf/util/thread.c index e3e5427e1c3c..a2490a20eb56 100644 --- a/tools/perf/util/thread.c +++ b/tools/perf/util/thread.c @@ -311,17 +311,30 @@ const char *thread__comm_str(struct thread *thread) return str; } +static int __thread__comm_len(struct thread *thread, const char *comm) +{ + if (!comm) + return 0; + thread->comm_len = strlen(comm); + + return thread->comm_len; +} + /* CHECKME: it should probably better return the max comm len from its comm list */ int thread__comm_len(struct thread *thread) { - if (!thread->comm_len) { - const char *comm = thread__comm_str(thread); - if (!comm) - return 0; - thread->comm_len = strlen(comm); + int comm_len = thread->comm_len; + + if (!comm_len) { + const char *comm; + + down_read(&thread->comm_lock); + comm = __thread__comm_str(thread); + comm_len = __thread__comm_len(thread, comm); + up_read(&thread->comm_lock); } - return thread->comm_len; + return comm_len; } size_t thread__fprintf(struct thread *thread, FILE *fp) -- cgit v1.2.3-58-ga151 From 990a71e904f6ec2d7d84eecb37e5127b75721985 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Tue, 14 Mar 2023 16:42:28 -0700 Subject: perf bpf filter: Introduce basic BPF filter expression This implements a tiny parser for the filter expressions used for BPF. Each expression will be converted to struct perf_bpf_filter_expr and be passed to a BPF map. For now, I'd like to start with the very basic comparisons like EQ or GT. The LHS should be a term for sample data and the RHS is a number. The expressions are connected by a comma. For example, period > 10000 ip < 0x1000000000000, cpu == 3 Signed-off-by: Namhyung Kim Acked-by: Jiri Olsa Cc: Adrian Hunter Cc: Andi Kleen Cc: Hao Luo Cc: Ian Rogers Cc: Ingo Molnar Cc: James Clark Cc: Kan Liang Cc: Leo Yan Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Song Liu Cc: Stephane Eranian Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230314234237.3008956-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/Build | 16 +++++++++ tools/perf/util/bpf-filter.c | 37 ++++++++++++++++++++ tools/perf/util/bpf-filter.h | 36 +++++++++++++++++++ tools/perf/util/bpf-filter.l | 82 ++++++++++++++++++++++++++++++++++++++++++++ tools/perf/util/bpf-filter.y | 54 +++++++++++++++++++++++++++++ 5 files changed, 225 insertions(+) create mode 100644 tools/perf/util/bpf-filter.c create mode 100644 tools/perf/util/bpf-filter.h create mode 100644 tools/perf/util/bpf-filter.l create mode 100644 tools/perf/util/bpf-filter.y (limited to 'tools') diff --git a/tools/perf/util/Build b/tools/perf/util/Build index 0806bc0361ad..bd18fe5f2719 100644 --- a/tools/perf/util/Build +++ b/tools/perf/util/Build @@ -154,6 +154,9 @@ perf-$(CONFIG_PERF_BPF_SKEL) += bpf_counter.o perf-$(CONFIG_PERF_BPF_SKEL) += bpf_counter_cgroup.o perf-$(CONFIG_PERF_BPF_SKEL) += bpf_ftrace.o perf-$(CONFIG_PERF_BPF_SKEL) += bpf_off_cpu.o +perf-$(CONFIG_PERF_BPF_SKEL) += bpf-filter.o +perf-$(CONFIG_PERF_BPF_SKEL) += bpf-filter-flex.o +perf-$(CONFIG_PERF_BPF_SKEL) += bpf-filter-bison.o ifeq ($(CONFIG_LIBTRACEEVENT),y) perf-$(CONFIG_PERF_BPF_SKEL) += bpf_lock_contention.o @@ -267,6 +270,16 @@ $(OUTPUT)util/pmu-bison.c $(OUTPUT)util/pmu-bison.h: util/pmu.y $(Q)$(call echo-cmd,bison)$(BISON) -v $< -d $(PARSER_DEBUG_BISON) $(BISON_FILE_PREFIX_MAP) \ -o $(OUTPUT)util/pmu-bison.c -p perf_pmu_ +$(OUTPUT)util/bpf-filter-flex.c $(OUTPUT)util/bpf-filter-flex.h: util/bpf-filter.l $(OUTPUT)util/bpf-filter-bison.c + $(call rule_mkdir) + $(Q)$(call echo-cmd,flex)$(FLEX) -o $(OUTPUT)util/bpf-filter-flex.c \ + --header-file=$(OUTPUT)util/bpf-filter-flex.h $(PARSER_DEBUG_FLEX) $< + +$(OUTPUT)util/bpf-filter-bison.c $(OUTPUT)util/bpf-filter-bison.h: util/bpf-filter.y + $(call rule_mkdir) + $(Q)$(call echo-cmd,bison)$(BISON) -v $< -d $(PARSER_DEBUG_BISON) $(BISON_FILE_PREFIX_MAP) \ + -o $(OUTPUT)util/bpf-filter-bison.c -p perf_bpf_filter_ + FLEX_GE_26 := $(shell expr $(shell $(FLEX) --version | sed -e 's/flex \([0-9]\+\).\([0-9]\+\)/\1\2/g') \>\= 26) ifeq ($(FLEX_GE_26),1) flex_flags := -Wno-switch-enum -Wno-switch-default -Wno-unused-function -Wno-redundant-decls -Wno-sign-compare -Wno-unused-parameter -Wno-missing-prototypes -Wno-missing-declarations @@ -280,6 +293,7 @@ endif CFLAGS_parse-events-flex.o += $(flex_flags) CFLAGS_pmu-flex.o += $(flex_flags) CFLAGS_expr-flex.o += $(flex_flags) +CFLAGS_bpf-filter-flex.o += $(flex_flags) bison_flags := -DYYENABLE_NLS=0 BISON_GE_35 := $(shell expr $(shell $(BISON) --version | grep bison | sed -e 's/.\+ \([0-9]\+\).\([0-9]\+\)/\1\2/g') \>\= 35) @@ -291,10 +305,12 @@ endif CFLAGS_parse-events-bison.o += $(bison_flags) CFLAGS_pmu-bison.o += -DYYLTYPE_IS_TRIVIAL=0 $(bison_flags) CFLAGS_expr-bison.o += -DYYLTYPE_IS_TRIVIAL=0 $(bison_flags) +CFLAGS_bpf-filter-bison.o += -DYYLTYPE_IS_TRIVIAL=0 $(bison_flags) $(OUTPUT)util/parse-events.o: $(OUTPUT)util/parse-events-flex.c $(OUTPUT)util/parse-events-bison.c $(OUTPUT)util/pmu.o: $(OUTPUT)util/pmu-flex.c $(OUTPUT)util/pmu-bison.c $(OUTPUT)util/expr.o: $(OUTPUT)util/expr-flex.c $(OUTPUT)util/expr-bison.c +$(OUTPUT)util/bpf-filter.o: $(OUTPUT)util/bpf-filter-flex.c $(OUTPUT)util/bpf-filter-bison.c CFLAGS_bitmap.o += -Wno-unused-parameter -DETC_PERFCONFIG="BUILD_STR($(ETC_PERFCONFIG_SQ))" CFLAGS_find_bit.o += -Wno-unused-parameter -DETC_PERFCONFIG="BUILD_STR($(ETC_PERFCONFIG_SQ))" diff --git a/tools/perf/util/bpf-filter.c b/tools/perf/util/bpf-filter.c new file mode 100644 index 000000000000..c72e35d51240 --- /dev/null +++ b/tools/perf/util/bpf-filter.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include + +#include "util/bpf-filter.h" +#include "util/bpf-filter-flex.h" +#include "util/bpf-filter-bison.h" + +struct perf_bpf_filter_expr *perf_bpf_filter_expr__new(unsigned long sample_flags, + enum perf_bpf_filter_op op, + unsigned long val) +{ + struct perf_bpf_filter_expr *expr; + + expr = malloc(sizeof(*expr)); + if (expr != NULL) { + expr->sample_flags = sample_flags; + expr->op = op; + expr->val = val; + } + return expr; +} + +int perf_bpf_filter__parse(struct list_head *expr_head, const char *str) +{ + YY_BUFFER_STATE buffer; + int ret; + + buffer = perf_bpf_filter__scan_string(str); + + ret = perf_bpf_filter_parse(expr_head); + + perf_bpf_filter__flush_buffer(buffer); + perf_bpf_filter__delete_buffer(buffer); + perf_bpf_filter_lex_destroy(); + + return ret; +} diff --git a/tools/perf/util/bpf-filter.h b/tools/perf/util/bpf-filter.h new file mode 100644 index 000000000000..93a0d3de038c --- /dev/null +++ b/tools/perf/util/bpf-filter.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef PERF_UTIL_BPF_FILTER_H +#define PERF_UTIL_BPF_FILTER_H + +#include + +enum perf_bpf_filter_op { + PBF_OP_EQ, + PBF_OP_NEQ, + PBF_OP_GT, + PBF_OP_GE, + PBF_OP_LT, + PBF_OP_LE, + PBF_OP_AND, +}; + +struct perf_bpf_filter_expr { + struct list_head list; + enum perf_bpf_filter_op op; + unsigned long sample_flags; + unsigned long val; +}; + +#ifdef HAVE_BPF_SKEL +struct perf_bpf_filter_expr *perf_bpf_filter_expr__new(unsigned long sample_flags, + enum perf_bpf_filter_op op, + unsigned long val); +int perf_bpf_filter__parse(struct list_head *expr_head, const char *str); +#else /* !HAVE_BPF_SKEL */ +static inline int perf_bpf_filter__parse(struct list_head *expr_head __maybe_unused, + const char *str __maybe_unused) +{ + return -ENOSYS; +} +#endif /* HAVE_BPF_SKEL*/ +#endif /* PERF_UTIL_BPF_FILTER_H */ diff --git a/tools/perf/util/bpf-filter.l b/tools/perf/util/bpf-filter.l new file mode 100644 index 000000000000..f6c0b74ea285 --- /dev/null +++ b/tools/perf/util/bpf-filter.l @@ -0,0 +1,82 @@ +%option prefix="perf_bpf_filter_" +%option noyywrap + +%{ +#include +#include +#include + +#include "bpf-filter.h" +#include "bpf-filter-bison.h" + +static int sample(unsigned long sample_flag) +{ + perf_bpf_filter_lval.sample = sample_flag; + return BFT_SAMPLE; +} + +static int operator(enum perf_bpf_filter_op op) +{ + perf_bpf_filter_lval.op = op; + return BFT_OP; +} + +static int value(int base) +{ + long num; + + errno = 0; + num = strtoul(perf_bpf_filter_text, NULL, base); + if (errno) + return BFT_ERROR; + + perf_bpf_filter_lval.num = num; + return BFT_NUM; +} + +static int error(const char *str) +{ + printf("perf_bpf_filter: Unexpected filter %s: %s\n", str, perf_bpf_filter_text); + return BFT_ERROR; +} + +%} + +num_dec [0-9]+ +num_hex 0[Xx][0-9a-fA-F]+ +space [ \t]+ +ident [_a-zA-Z][_a-zA-Z0-9]+ + +%% + +{num_dec} { return value(10); } +{num_hex} { return value(16); } +{space} { } + +ip { return sample(PERF_SAMPLE_IP); } +id { return sample(PERF_SAMPLE_ID); } +tid { return sample(PERF_SAMPLE_TID); } +cpu { return sample(PERF_SAMPLE_CPU); } +time { return sample(PERF_SAMPLE_TIME); } +addr { return sample(PERF_SAMPLE_ADDR); } +period { return sample(PERF_SAMPLE_PERIOD); } +txn { return sample(PERF_SAMPLE_TRANSACTION); } +weight { return sample(PERF_SAMPLE_WEIGHT); } +phys_addr { return sample(PERF_SAMPLE_PHYS_ADDR); } +code_pgsz { return sample(PERF_SAMPLE_CODE_PAGE_SIZE); } +data_pgsz { return sample(PERF_SAMPLE_DATA_PAGE_SIZE); } + +"==" { return operator(PBF_OP_EQ); } +"!=" { return operator(PBF_OP_NEQ); } +">" { return operator(PBF_OP_GT); } +"<" { return operator(PBF_OP_LT); } +">=" { return operator(PBF_OP_GE); } +"<=" { return operator(PBF_OP_LE); } +"&" { return operator(PBF_OP_AND); } + +"," { return ','; } + +{ident} { return error("ident"); } +. { return error("input"); } + +%% diff --git a/tools/perf/util/bpf-filter.y b/tools/perf/util/bpf-filter.y new file mode 100644 index 000000000000..13eca612ecca --- /dev/null +++ b/tools/perf/util/bpf-filter.y @@ -0,0 +1,54 @@ +%parse-param {struct list_head *expr_head} +%define parse.error verbose + +%{ + +#include +#include +#include +#include +#include "bpf-filter.h" + +static void perf_bpf_filter_error(struct list_head *expr __maybe_unused, + char const *msg) +{ + printf("perf_bpf_filter: %s\n", msg); +} + +%} + +%union +{ + unsigned long num; + unsigned long sample; + enum perf_bpf_filter_op op; + struct perf_bpf_filter_expr *expr; +} + +%token BFT_SAMPLE BFT_OP BFT_ERROR BFT_NUM +%type filter_term +%destructor { free ($$); } +%type BFT_SAMPLE +%type BFT_OP +%type BFT_NUM + +%% + +filter: +filter ',' filter_term +{ + list_add_tail(&$3->list, expr_head); +} +| +filter_term +{ + list_add_tail(&$1->list, expr_head); +} + +filter_term: +BFT_SAMPLE BFT_OP BFT_NUM +{ + $$ = perf_bpf_filter_expr__new($1, $2, $3); +} + +%% -- cgit v1.2.3-58-ga151 From 56ec9457a4a20c5e07ad94bfb6e23077d54cb28e Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Tue, 14 Mar 2023 16:42:29 -0700 Subject: perf bpf filter: Implement event sample filtering The BPF program will be attached to a perf_event and be triggered when it overflows. It'd iterate the filters map and compare the sample value according to the expression. If any of them fails, the sample would be dropped. Also it needs to have the corresponding sample data for the expression so it compares data->sample_flags with the given value. To access the sample data, it uses the bpf_cast_to_kern_ctx() kfunc which was added in v6.2 kernel. Signed-off-by: Namhyung Kim Acked-by: Jiri Olsa Cc: Adrian Hunter Cc: Andi Kleen Cc: Hao Luo Cc: Ian Rogers Cc: Ingo Molnar Cc: James Clark Cc: Kan Liang Cc: Leo Yan Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Song Liu Cc: Stephane Eranian Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230314234237.3008956-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Makefile.perf | 2 +- tools/perf/util/bpf-filter.c | 64 ++++++++++++++ tools/perf/util/bpf-filter.h | 26 +++--- tools/perf/util/bpf_skel/sample-filter.h | 24 +++++ tools/perf/util/bpf_skel/sample_filter.bpf.c | 126 +++++++++++++++++++++++++++ tools/perf/util/evsel.h | 7 +- 6 files changed, 236 insertions(+), 13 deletions(-) create mode 100644 tools/perf/util/bpf_skel/sample-filter.h create mode 100644 tools/perf/util/bpf_skel/sample_filter.bpf.c (limited to 'tools') diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf index dc9dda09b076..ed6b6a070f79 100644 --- a/tools/perf/Makefile.perf +++ b/tools/perf/Makefile.perf @@ -1050,7 +1050,7 @@ SKELETONS := $(SKEL_OUT)/bpf_prog_profiler.skel.h SKELETONS += $(SKEL_OUT)/bperf_leader.skel.h $(SKEL_OUT)/bperf_follower.skel.h SKELETONS += $(SKEL_OUT)/bperf_cgroup.skel.h $(SKEL_OUT)/func_latency.skel.h SKELETONS += $(SKEL_OUT)/off_cpu.skel.h $(SKEL_OUT)/lock_contention.skel.h -SKELETONS += $(SKEL_OUT)/kwork_trace.skel.h +SKELETONS += $(SKEL_OUT)/kwork_trace.skel.h $(SKEL_OUT)/sample_filter.skel.h $(SKEL_TMP_OUT) $(LIBAPI_OUTPUT) $(LIBBPF_OUTPUT) $(LIBPERF_OUTPUT) $(LIBSUBCMD_OUTPUT) $(LIBSYMBOL_OUTPUT): $(Q)$(MKDIR) -p $@ diff --git a/tools/perf/util/bpf-filter.c b/tools/perf/util/bpf-filter.c index c72e35d51240..f20e1bc03778 100644 --- a/tools/perf/util/bpf-filter.c +++ b/tools/perf/util/bpf-filter.c @@ -1,10 +1,74 @@ /* SPDX-License-Identifier: GPL-2.0 */ #include +#include +#include +#include + +#include "util/debug.h" +#include "util/evsel.h" + #include "util/bpf-filter.h" #include "util/bpf-filter-flex.h" #include "util/bpf-filter-bison.h" +#include "bpf_skel/sample-filter.h" +#include "bpf_skel/sample_filter.skel.h" + +#define FD(e, x, y) (*(int *)xyarray__entry(e->core.fd, x, y)) + +int perf_bpf_filter__prepare(struct evsel *evsel) +{ + int i, x, y, fd; + struct sample_filter_bpf *skel; + struct bpf_program *prog; + struct bpf_link *link; + struct perf_bpf_filter_expr *expr; + + skel = sample_filter_bpf__open_and_load(); + if (!skel) { + pr_err("Failed to load perf sample-filter BPF skeleton\n"); + return -1; + } + + i = 0; + fd = bpf_map__fd(skel->maps.filters); + list_for_each_entry(expr, &evsel->bpf_filters, list) { + struct perf_bpf_filter_entry entry = { + .op = expr->op, + .flags = expr->sample_flags, + .value = expr->val, + }; + bpf_map_update_elem(fd, &i, &entry, BPF_ANY); + i++; + } + + prog = skel->progs.perf_sample_filter; + for (x = 0; x < xyarray__max_x(evsel->core.fd); x++) { + for (y = 0; y < xyarray__max_y(evsel->core.fd); y++) { + link = bpf_program__attach_perf_event(prog, FD(evsel, x, y)); + if (IS_ERR(link)) { + pr_err("Failed to attach perf sample-filter program\n"); + return PTR_ERR(link); + } + } + } + evsel->bpf_skel = skel; + return 0; +} + +int perf_bpf_filter__destroy(struct evsel *evsel) +{ + struct perf_bpf_filter_expr *expr, *tmp; + + list_for_each_entry_safe(expr, tmp, &evsel->bpf_filters, list) { + list_del(&expr->list); + free(expr); + } + sample_filter_bpf__destroy(evsel->bpf_skel); + return 0; +} + struct perf_bpf_filter_expr *perf_bpf_filter_expr__new(unsigned long sample_flags, enum perf_bpf_filter_op op, unsigned long val) diff --git a/tools/perf/util/bpf-filter.h b/tools/perf/util/bpf-filter.h index 93a0d3de038c..eb8e1ac43cdf 100644 --- a/tools/perf/util/bpf-filter.h +++ b/tools/perf/util/bpf-filter.h @@ -4,15 +4,7 @@ #include -enum perf_bpf_filter_op { - PBF_OP_EQ, - PBF_OP_NEQ, - PBF_OP_GT, - PBF_OP_GE, - PBF_OP_LT, - PBF_OP_LE, - PBF_OP_AND, -}; +#include "bpf_skel/sample-filter.h" struct perf_bpf_filter_expr { struct list_head list; @@ -21,16 +13,30 @@ struct perf_bpf_filter_expr { unsigned long val; }; +struct evsel; + #ifdef HAVE_BPF_SKEL struct perf_bpf_filter_expr *perf_bpf_filter_expr__new(unsigned long sample_flags, enum perf_bpf_filter_op op, unsigned long val); int perf_bpf_filter__parse(struct list_head *expr_head, const char *str); +int perf_bpf_filter__prepare(struct evsel *evsel); +int perf_bpf_filter__destroy(struct evsel *evsel); + #else /* !HAVE_BPF_SKEL */ + static inline int perf_bpf_filter__parse(struct list_head *expr_head __maybe_unused, const char *str __maybe_unused) { - return -ENOSYS; + return -EOPNOTSUPP; +} +static inline int perf_bpf_filter__prepare(struct evsel *evsel __maybe_unused) +{ + return -EOPNOTSUPP; +} +static inline int perf_bpf_filter__destroy(struct evsel *evsel __maybe_unused) +{ + return -EOPNOTSUPP; } #endif /* HAVE_BPF_SKEL*/ #endif /* PERF_UTIL_BPF_FILTER_H */ diff --git a/tools/perf/util/bpf_skel/sample-filter.h b/tools/perf/util/bpf_skel/sample-filter.h new file mode 100644 index 000000000000..862060bfda14 --- /dev/null +++ b/tools/perf/util/bpf_skel/sample-filter.h @@ -0,0 +1,24 @@ +#ifndef PERF_UTIL_BPF_SKEL_SAMPLE_FILTER_H +#define PERF_UTIL_BPF_SKEL_SAMPLE_FILTER_H + +#define MAX_FILTERS 32 + +/* supported filter operations */ +enum perf_bpf_filter_op { + PBF_OP_EQ, + PBF_OP_NEQ, + PBF_OP_GT, + PBF_OP_GE, + PBF_OP_LT, + PBF_OP_LE, + PBF_OP_AND +}; + +/* BPF map entry for filtering */ +struct perf_bpf_filter_entry { + enum perf_bpf_filter_op op; + __u64 flags; + __u64 value; +}; + +#endif /* PERF_UTIL_BPF_SKEL_SAMPLE_FILTER_H */ \ No newline at end of file diff --git a/tools/perf/util/bpf_skel/sample_filter.bpf.c b/tools/perf/util/bpf_skel/sample_filter.bpf.c new file mode 100644 index 000000000000..c07256279c3e --- /dev/null +++ b/tools/perf/util/bpf_skel/sample_filter.bpf.c @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +// Copyright (c) 2023 Google +#include "vmlinux.h" +#include +#include +#include + +#include "sample-filter.h" + +/* BPF map that will be filled by user space */ +struct filters { + __uint(type, BPF_MAP_TYPE_ARRAY); + __type(key, int); + __type(value, struct perf_bpf_filter_entry); + __uint(max_entries, MAX_FILTERS); +} filters SEC(".maps"); + +int dropped; + +void *bpf_cast_to_kern_ctx(void *) __ksym; + +/* new kernel perf_sample_data definition */ +struct perf_sample_data___new { + __u64 sample_flags; +} __attribute__((preserve_access_index)); + +/* helper function to return the given perf sample data */ +static inline __u64 perf_get_sample(struct bpf_perf_event_data_kern *kctx, + struct perf_bpf_filter_entry *entry) +{ + struct perf_sample_data___new *data = (void *)kctx->data; + + if (!bpf_core_field_exists(data->sample_flags) || + (data->sample_flags & entry->flags) == 0) + return 0; + + switch (entry->flags) { + case PERF_SAMPLE_IP: + return kctx->data->ip; + case PERF_SAMPLE_ID: + return kctx->data->id; + case PERF_SAMPLE_TID: + return kctx->data->tid_entry.tid; + case PERF_SAMPLE_CPU: + return kctx->data->cpu_entry.cpu; + case PERF_SAMPLE_TIME: + return kctx->data->time; + case PERF_SAMPLE_ADDR: + return kctx->data->addr; + case PERF_SAMPLE_PERIOD: + return kctx->data->period; + case PERF_SAMPLE_TRANSACTION: + return kctx->data->txn; + case PERF_SAMPLE_WEIGHT: + return kctx->data->weight.full; + case PERF_SAMPLE_PHYS_ADDR: + return kctx->data->phys_addr; + case PERF_SAMPLE_CODE_PAGE_SIZE: + return kctx->data->code_page_size; + case PERF_SAMPLE_DATA_PAGE_SIZE: + return kctx->data->data_page_size; + default: + break; + } + return 0; +} + +/* BPF program to be called from perf event overflow handler */ +SEC("perf_event") +int perf_sample_filter(void *ctx) +{ + struct bpf_perf_event_data_kern *kctx; + struct perf_bpf_filter_entry *entry; + __u64 sample_data; + int i; + + kctx = bpf_cast_to_kern_ctx(ctx); + + for (i = 0; i < MAX_FILTERS; i++) { + int key = i; /* needed for verifier :( */ + + entry = bpf_map_lookup_elem(&filters, &key); + if (entry == NULL) + break; + sample_data = perf_get_sample(kctx, entry); + + switch (entry->op) { + case PBF_OP_EQ: + if (!(sample_data == entry->value)) + goto drop; + break; + case PBF_OP_NEQ: + if (!(sample_data != entry->value)) + goto drop; + break; + case PBF_OP_GT: + if (!(sample_data > entry->value)) + goto drop; + break; + case PBF_OP_GE: + if (!(sample_data >= entry->value)) + goto drop; + break; + case PBF_OP_LT: + if (!(sample_data < entry->value)) + goto drop; + break; + case PBF_OP_LE: + if (!(sample_data <= entry->value)) + goto drop; + break; + case PBF_OP_AND: + if (!(sample_data & entry->value)) + goto drop; + break; + } + } + /* generate sample data */ + return 1; + +drop: + __sync_fetch_and_add(&dropped, 1); + return 0; +} + +char LICENSE[] SEC("license") = "Dual BSD/GPL"; diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h index c272c06565c0..68072ec655ce 100644 --- a/tools/perf/util/evsel.h +++ b/tools/perf/util/evsel.h @@ -150,8 +150,10 @@ struct evsel { */ struct bpf_counter_ops *bpf_counter_ops; - /* for perf-stat -b */ - struct list_head bpf_counter_list; + union { + struct list_head bpf_counter_list; /* for perf-stat -b */ + struct list_head bpf_filters; /* for perf-record --filter */ + }; /* for perf-stat --use-bpf */ int bperf_leader_prog_fd; @@ -159,6 +161,7 @@ struct evsel { union { struct bperf_leader_bpf *leader_skel; struct bperf_follower_bpf *follower_skel; + void *bpf_skel; }; unsigned long open_flags; int precise_ip_original; -- cgit v1.2.3-58-ga151 From d180aa56b50dd243dec89b24d23e0a59c3f0c0eb Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Tue, 14 Mar 2023 16:42:30 -0700 Subject: perf record: Add BPF event filter support Use --filter option to set BPF filter for generic events other than the tracepoints or Intel PT. The BPF program will check the sample data and filter according to the expression. For example, the below is the typical perf record for frequency mode. The sample period started from 1 and increased gradually. $ sudo ./perf record -e cycles true $ sudo ./perf script perf-exec 2272336 546683.916875: 1 cycles: ffffffff828499b8 perf_event_exec+0x298 ([kernel.kallsyms]) perf-exec 2272336 546683.916892: 1 cycles: ffffffff828499b8 perf_event_exec+0x298 ([kernel.kallsyms]) perf-exec 2272336 546683.916899: 3 cycles: ffffffff828499b8 perf_event_exec+0x298 ([kernel.kallsyms]) perf-exec 2272336 546683.916905: 17 cycles: ffffffff828499b8 perf_event_exec+0x298 ([kernel.kallsyms]) perf-exec 2272336 546683.916911: 100 cycles: ffffffff828499b8 perf_event_exec+0x298 ([kernel.kallsyms]) perf-exec 2272336 546683.916917: 589 cycles: ffffffff828499b8 perf_event_exec+0x298 ([kernel.kallsyms]) perf-exec 2272336 546683.916924: 3470 cycles: ffffffff828499b8 perf_event_exec+0x298 ([kernel.kallsyms]) perf-exec 2272336 546683.916930: 20465 cycles: ffffffff828499b8 perf_event_exec+0x298 ([kernel.kallsyms]) true 2272336 546683.916940: 119873 cycles: ffffffff8283afdd perf_iterate_ctx+0x2d ([kernel.kallsyms]) true 2272336 546683.917003: 461349 cycles: ffffffff82892517 vma_interval_tree_insert+0x37 ([kernel.kallsyms]) true 2272336 546683.917237: 635778 cycles: ffffffff82a11400 security_mmap_file+0x20 ([kernel.kallsyms]) When you add a BPF filter to get samples having periods greater than 1000, the output would look like below: $ sudo ./perf record -e cycles --filter 'period > 1000' true $ sudo ./perf script perf-exec 2273949 546850.708501: 5029 cycles: ffffffff826f9e25 finish_wait+0x5 ([kernel.kallsyms]) perf-exec 2273949 546850.708508: 32409 cycles: ffffffff826f9e25 finish_wait+0x5 ([kernel.kallsyms]) perf-exec 2273949 546850.708526: 143369 cycles: ffffffff82b4cdbf xas_start+0x5f ([kernel.kallsyms]) perf-exec 2273949 546850.708600: 372650 cycles: ffffffff8286b8f7 __pagevec_lru_add+0x117 ([kernel.kallsyms]) perf-exec 2273949 546850.708791: 482953 cycles: ffffffff829190de __mod_memcg_lruvec_state+0x4e ([kernel.kallsyms]) true 2273949 546850.709036: 501985 cycles: ffffffff828add7c tlb_gather_mmu+0x4c ([kernel.kallsyms]) true 2273949 546850.709292: 503065 cycles: 7f2446d97c03 _dl_map_object_deps+0x973 (/usr/lib/x86_64-linux-gnu/ld-linux-x86-64.so.2) Committer notes: Add stubs for perf_bpf_filter__prepare() and perf_bpf_filter__destroy() to tools/perf/util/python.c to keep it building. Signed-off-by: Namhyung Kim Acked-by: Jiri Olsa Cc: Adrian Hunter Cc: Andi Kleen Cc: Hao Luo Cc: Ian Rogers Cc: Ingo Molnar Cc: James Clark Cc: Kan Liang Cc: Leo Yan Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Song Liu Cc: Stephane Eranian Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230314234237.3008956-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Documentation/perf-record.txt | 15 ++++++++++++--- tools/perf/util/bpf_counter.c | 3 +-- tools/perf/util/evlist.c | 25 ++++++++++++++++++------- tools/perf/util/evsel.c | 2 ++ tools/perf/util/parse-events.c | 8 +++----- tools/perf/util/python.c | 14 ++++++++++++++ 6 files changed, 50 insertions(+), 17 deletions(-) (limited to 'tools') diff --git a/tools/perf/Documentation/perf-record.txt b/tools/perf/Documentation/perf-record.txt index ff815c2f67e8..122f71726eaa 100644 --- a/tools/perf/Documentation/perf-record.txt +++ b/tools/perf/Documentation/perf-record.txt @@ -119,9 +119,12 @@ OPTIONS "perf report" to view group events together. --filter=:: - Event filter. This option should follow an event selector (-e) which - selects either tracepoint event(s) or a hardware trace PMU - (e.g. Intel PT or CoreSight). + Event filter. This option should follow an event selector (-e). + If the event is a tracepoint, the filter string will be parsed by + the kernel. If the event is a hardware trace PMU (e.g. Intel PT + or CoreSight), it'll be processed as an address filter. Otherwise + it means a general filter using BPF which can be applied for any + kind of event. - tracepoint filters @@ -176,6 +179,12 @@ OPTIONS Multiple filters can be separated with space or comma. + - bpf filters + + A BPF filter can access the sample data and make a decision based on the + data. Users need to set an appropriate sample type to use the BPF + filter. + --exclude-perf:: Don't record events issued by perf itself. This option should follow an event selector (-e) which selects tracepoint event(s). It adds a diff --git a/tools/perf/util/bpf_counter.c b/tools/perf/util/bpf_counter.c index aa78a15a6f0a..1b77436e067e 100644 --- a/tools/perf/util/bpf_counter.c +++ b/tools/perf/util/bpf_counter.c @@ -763,8 +763,7 @@ extern struct bpf_counter_ops bperf_cgrp_ops; static inline bool bpf_counter_skip(struct evsel *evsel) { - return list_empty(&evsel->bpf_counter_list) && - evsel->follower_skel == NULL; + return evsel->bpf_counter_ops == NULL; } int bpf_counter__install_pe(struct evsel *evsel, int cpu_map_idx, int fd) diff --git a/tools/perf/util/evlist.c b/tools/perf/util/evlist.c index b74e12239aec..cc491a037836 100644 --- a/tools/perf/util/evlist.c +++ b/tools/perf/util/evlist.c @@ -31,6 +31,7 @@ #include "util/evlist-hybrid.h" #include "util/pmu.h" #include "util/sample.h" +#include "util/bpf-filter.h" #include #include #include @@ -1086,17 +1087,27 @@ int evlist__apply_filters(struct evlist *evlist, struct evsel **err_evsel) int err = 0; evlist__for_each_entry(evlist, evsel) { - if (evsel->filter == NULL) - continue; - /* * filters only work for tracepoint event, which doesn't have cpu limit. * So evlist and evsel should always be same. */ - err = perf_evsel__apply_filter(&evsel->core, evsel->filter); - if (err) { - *err_evsel = evsel; - break; + if (evsel->filter) { + err = perf_evsel__apply_filter(&evsel->core, evsel->filter); + if (err) { + *err_evsel = evsel; + break; + } + } + + /* + * non-tracepoint events can have BPF filters. + */ + if (!list_empty(&evsel->bpf_filters)) { + err = perf_bpf_filter__prepare(evsel); + if (err) { + *err_evsel = evsel; + break; + } } } diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index a83d8cd5eb51..dc3faf005c3b 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -50,6 +50,7 @@ #include "off_cpu.h" #include "../perf-sys.h" #include "util/parse-branch-options.h" +#include "util/bpf-filter.h" #include #include #include @@ -1517,6 +1518,7 @@ void evsel__exit(struct evsel *evsel) assert(list_empty(&evsel->core.node)); assert(evsel->evlist == NULL); bpf_counter__destroy(evsel); + perf_bpf_filter__destroy(evsel); evsel__free_counts(evsel); perf_evsel__free_fd(&evsel->core); perf_evsel__free_id(&evsel->core); diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 3b2e5bb3e852..6c5cf5244486 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -28,6 +28,7 @@ #include "perf.h" #include "util/parse-events-hybrid.h" #include "util/pmu-hybrid.h" +#include "util/bpf-filter.h" #include "tracepoint.h" #include "thread_map.h" @@ -2542,11 +2543,8 @@ static int set_filter(struct evsel *evsel, const void *arg) perf_pmu__scan_file(pmu, "nr_addr_filters", "%d", &nr_addr_filters); - if (!nr_addr_filters) { - fprintf(stderr, - "This CPU does not support address filtering\n"); - return -1; - } + if (!nr_addr_filters) + return perf_bpf_filter__parse(&evsel->bpf_filters, str); if (evsel__append_addr_filter(evsel, str) < 0) { fprintf(stderr, diff --git a/tools/perf/util/python.c b/tools/perf/util/python.c index be336f1b2b68..0faea4c75eed 100644 --- a/tools/perf/util/python.c +++ b/tools/perf/util/python.c @@ -19,6 +19,7 @@ #include "mmap.h" #include "stat.h" #include "metricgroup.h" +#include "util/bpf-filter.h" #include "util/env.h" #include "util/pmu.h" #include @@ -135,6 +136,19 @@ int bpf_counter__disable(struct evsel *evsel __maybe_unused) return 0; } +// not to drag util/bpf-filter.c +#ifdef HAVE_BPF_SKEL +int perf_bpf_filter__prepare(struct evsel *evsel __maybe_unused) +{ + return 0; +} + +int perf_bpf_filter__destroy(struct evsel *evsel __maybe_unused) +{ + return 0; +} +#endif + /* * Support debug printing even though util/debug.c is not linked. That means * implementing 'verbose' and 'eprintf'. -- cgit v1.2.3-58-ga151 From 27c6f2455b29f27c8daf209ec8bdf0ac2c567b74 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Tue, 14 Mar 2023 16:42:31 -0700 Subject: perf record: Record dropped sample count When it uses bpf filters, event might drop some samples. It'd be nice if it can report how many samples it lost. As LOST_SAMPLES event can carry the similar information, let's use it for bpf filters. To indicate it's from BPF filters, add a new misc flag for that and do not display cpu load warnings. Signed-off-by: Namhyung Kim Acked-by: Jiri Olsa Cc: Adrian Hunter Cc: Andi Kleen Cc: Hao Luo Cc: Ian Rogers Cc: Ingo Molnar Cc: James Clark Cc: Kan Liang Cc: Leo Yan Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Song Liu Cc: Stephane Eranian Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230314234237.3008956-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/lib/perf/include/perf/event.h | 2 ++ tools/perf/builtin-record.c | 38 +++++++++++++++++++++++-------------- tools/perf/util/bpf-filter.c | 7 +++++++ tools/perf/util/bpf-filter.h | 5 +++++ tools/perf/util/session.c | 3 ++- 5 files changed, 40 insertions(+), 15 deletions(-) (limited to 'tools') diff --git a/tools/lib/perf/include/perf/event.h b/tools/lib/perf/include/perf/event.h index ad47d7b31046..51b9338f4c11 100644 --- a/tools/lib/perf/include/perf/event.h +++ b/tools/lib/perf/include/perf/event.h @@ -70,6 +70,8 @@ struct perf_record_lost { __u64 lost; }; +#define PERF_RECORD_MISC_LOST_SAMPLES_BPF (1 << 15) + struct perf_record_lost_samples { struct perf_event_header header; __u64 lost; diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c index 33ebe42b025e..6df8b823859d 100644 --- a/tools/perf/builtin-record.c +++ b/tools/perf/builtin-record.c @@ -52,6 +52,7 @@ #include "util/pmu-hybrid.h" #include "util/evlist-hybrid.h" #include "util/off_cpu.h" +#include "util/bpf-filter.h" #include "asm/bug.h" #include "perf.h" #include "cputopo.h" @@ -1856,24 +1857,16 @@ record__switch_output(struct record *rec, bool at_exit) return fd; } -static void __record__read_lost_samples(struct record *rec, struct evsel *evsel, +static void __record__save_lost_samples(struct record *rec, struct evsel *evsel, struct perf_record_lost_samples *lost, - int cpu_idx, int thread_idx) + int cpu_idx, int thread_idx, u64 lost_count, + u16 misc_flag) { - struct perf_counts_values count; struct perf_sample_id *sid; struct perf_sample sample = {}; int id_hdr_size; - if (perf_evsel__read(&evsel->core, cpu_idx, thread_idx, &count) < 0) { - pr_debug("read LOST count failed\n"); - return; - } - - if (count.lost == 0) - return; - - lost->lost = count.lost; + lost->lost = lost_count; if (evsel->core.ids) { sid = xyarray__entry(evsel->core.sample_id, cpu_idx, thread_idx); sample.id = sid->id; @@ -1882,6 +1875,7 @@ static void __record__read_lost_samples(struct record *rec, struct evsel *evsel, id_hdr_size = perf_event__synthesize_id_sample((void *)(lost + 1), evsel->core.attr.sample_type, &sample); lost->header.size = sizeof(*lost) + id_hdr_size; + lost->header.misc = misc_flag; record__write(rec, NULL, lost, lost->header.size); } @@ -1905,6 +1899,7 @@ static void record__read_lost_samples(struct record *rec) evlist__for_each_entry(session->evlist, evsel) { struct xyarray *xy = evsel->core.sample_id; + u64 lost_count; if (xy == NULL || evsel->core.fd == NULL) continue; @@ -1916,12 +1911,27 @@ static void record__read_lost_samples(struct record *rec) for (int x = 0; x < xyarray__max_x(xy); x++) { for (int y = 0; y < xyarray__max_y(xy); y++) { - __record__read_lost_samples(rec, evsel, lost, x, y); + struct perf_counts_values count; + + if (perf_evsel__read(&evsel->core, x, y, &count) < 0) { + pr_debug("read LOST count failed\n"); + goto out; + } + + if (count.lost) { + __record__save_lost_samples(rec, evsel, lost, + x, y, count.lost, 0); + } } } + + lost_count = perf_bpf_filter__lost_count(evsel); + if (lost_count) + __record__save_lost_samples(rec, evsel, lost, 0, 0, lost_count, + PERF_RECORD_MISC_LOST_SAMPLES_BPF); } +out: free(lost); - } static volatile sig_atomic_t workload_exec_errno; diff --git a/tools/perf/util/bpf-filter.c b/tools/perf/util/bpf-filter.c index f20e1bc03778..7bd6f2e41513 100644 --- a/tools/perf/util/bpf-filter.c +++ b/tools/perf/util/bpf-filter.c @@ -69,6 +69,13 @@ int perf_bpf_filter__destroy(struct evsel *evsel) return 0; } +u64 perf_bpf_filter__lost_count(struct evsel *evsel) +{ + struct sample_filter_bpf *skel = evsel->bpf_skel; + + return skel ? skel->bss->dropped : 0; +} + struct perf_bpf_filter_expr *perf_bpf_filter_expr__new(unsigned long sample_flags, enum perf_bpf_filter_op op, unsigned long val) diff --git a/tools/perf/util/bpf-filter.h b/tools/perf/util/bpf-filter.h index eb8e1ac43cdf..f0c66764c6d0 100644 --- a/tools/perf/util/bpf-filter.h +++ b/tools/perf/util/bpf-filter.h @@ -22,6 +22,7 @@ struct perf_bpf_filter_expr *perf_bpf_filter_expr__new(unsigned long sample_flag int perf_bpf_filter__parse(struct list_head *expr_head, const char *str); int perf_bpf_filter__prepare(struct evsel *evsel); int perf_bpf_filter__destroy(struct evsel *evsel); +u64 perf_bpf_filter__lost_count(struct evsel *evsel); #else /* !HAVE_BPF_SKEL */ @@ -38,5 +39,9 @@ static inline int perf_bpf_filter__destroy(struct evsel *evsel __maybe_unused) { return -EOPNOTSUPP; } +static inline u64 perf_bpf_filter__lost_count(struct evsel *evsel __maybe_unused) +{ + return 0; +} #endif /* HAVE_BPF_SKEL*/ #endif /* PERF_UTIL_BPF_FILTER_H */ diff --git a/tools/perf/util/session.c b/tools/perf/util/session.c index 749d5b5c135b..7d8d057d1772 100644 --- a/tools/perf/util/session.c +++ b/tools/perf/util/session.c @@ -1582,7 +1582,8 @@ static int machines__deliver_event(struct machines *machines, evlist->stats.total_lost += event->lost.lost; return tool->lost(tool, event, sample, machine); case PERF_RECORD_LOST_SAMPLES: - if (tool->lost_samples == perf_event__process_lost_samples) + if (tool->lost_samples == perf_event__process_lost_samples && + !(event->header.misc & PERF_RECORD_MISC_LOST_SAMPLES_BPF)) evlist->stats.total_lost_samples += event->lost_samples.lost; return tool->lost_samples(tool, event, sample, machine); case PERF_RECORD_READ: -- cgit v1.2.3-58-ga151 From 335818470f558de5dc37bbcb31f97b303605a9df Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Tue, 14 Mar 2023 16:42:32 -0700 Subject: perf bpf filter: Add 'pid' sample data support The pid is special because it's saved in the PERF_SAMPLE_TID together. So it needs to differenciate tid and pid using the 'part' field in the perf bpf filter entry struct. Signed-off-by: Namhyung Kim Acked-by: Jiri Olsa Cc: Adrian Hunter Cc: Andi Kleen Cc: Hao Luo Cc: Ian Rogers Cc: Ingo Molnar Cc: James Clark Cc: Kan Liang Cc: Leo Yan Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Song Liu Cc: Stephane Eranian Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230314234237.3008956-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/bpf-filter.c | 4 +++- tools/perf/util/bpf-filter.h | 3 ++- tools/perf/util/bpf-filter.l | 11 ++++++++++- tools/perf/util/bpf-filter.y | 7 +++++-- tools/perf/util/bpf_skel/sample-filter.h | 3 ++- tools/perf/util/bpf_skel/sample_filter.bpf.c | 5 ++++- 6 files changed, 26 insertions(+), 7 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/bpf-filter.c b/tools/perf/util/bpf-filter.c index 7bd6f2e41513..743c69fd6cd4 100644 --- a/tools/perf/util/bpf-filter.c +++ b/tools/perf/util/bpf-filter.c @@ -36,6 +36,7 @@ int perf_bpf_filter__prepare(struct evsel *evsel) list_for_each_entry(expr, &evsel->bpf_filters, list) { struct perf_bpf_filter_entry entry = { .op = expr->op, + .part = expr->part, .flags = expr->sample_flags, .value = expr->val, }; @@ -76,7 +77,7 @@ u64 perf_bpf_filter__lost_count(struct evsel *evsel) return skel ? skel->bss->dropped : 0; } -struct perf_bpf_filter_expr *perf_bpf_filter_expr__new(unsigned long sample_flags, +struct perf_bpf_filter_expr *perf_bpf_filter_expr__new(unsigned long sample_flags, int part, enum perf_bpf_filter_op op, unsigned long val) { @@ -85,6 +86,7 @@ struct perf_bpf_filter_expr *perf_bpf_filter_expr__new(unsigned long sample_flag expr = malloc(sizeof(*expr)); if (expr != NULL) { expr->sample_flags = sample_flags; + expr->part = part; expr->op = op; expr->val = val; } diff --git a/tools/perf/util/bpf-filter.h b/tools/perf/util/bpf-filter.h index f0c66764c6d0..3f8827bd965f 100644 --- a/tools/perf/util/bpf-filter.h +++ b/tools/perf/util/bpf-filter.h @@ -9,6 +9,7 @@ struct perf_bpf_filter_expr { struct list_head list; enum perf_bpf_filter_op op; + int part; unsigned long sample_flags; unsigned long val; }; @@ -16,7 +17,7 @@ struct perf_bpf_filter_expr { struct evsel; #ifdef HAVE_BPF_SKEL -struct perf_bpf_filter_expr *perf_bpf_filter_expr__new(unsigned long sample_flags, +struct perf_bpf_filter_expr *perf_bpf_filter_expr__new(unsigned long sample_flags, int part, enum perf_bpf_filter_op op, unsigned long val); int perf_bpf_filter__parse(struct list_head *expr_head, const char *str); diff --git a/tools/perf/util/bpf-filter.l b/tools/perf/util/bpf-filter.l index f6c0b74ea285..ec12fc4d2ab8 100644 --- a/tools/perf/util/bpf-filter.l +++ b/tools/perf/util/bpf-filter.l @@ -11,7 +11,15 @@ static int sample(unsigned long sample_flag) { - perf_bpf_filter_lval.sample = sample_flag; + perf_bpf_filter_lval.sample.type = sample_flag; + perf_bpf_filter_lval.sample.part = 0; + return BFT_SAMPLE; +} + +static int sample_part(unsigned long sample_flag, int part) +{ + perf_bpf_filter_lval.sample.type = sample_flag; + perf_bpf_filter_lval.sample.part = part; return BFT_SAMPLE; } @@ -56,6 +64,7 @@ ident [_a-zA-Z][_a-zA-Z0-9]+ ip { return sample(PERF_SAMPLE_IP); } id { return sample(PERF_SAMPLE_ID); } tid { return sample(PERF_SAMPLE_TID); } +pid { return sample_part(PERF_SAMPLE_TID, 1); } cpu { return sample(PERF_SAMPLE_CPU); } time { return sample(PERF_SAMPLE_TIME); } addr { return sample(PERF_SAMPLE_ADDR); } diff --git a/tools/perf/util/bpf-filter.y b/tools/perf/util/bpf-filter.y index 13eca612ecca..0ca6532afd8d 100644 --- a/tools/perf/util/bpf-filter.y +++ b/tools/perf/util/bpf-filter.y @@ -20,7 +20,10 @@ static void perf_bpf_filter_error(struct list_head *expr __maybe_unused, %union { unsigned long num; - unsigned long sample; + struct { + unsigned long type; + int part; + } sample; enum perf_bpf_filter_op op; struct perf_bpf_filter_expr *expr; } @@ -48,7 +51,7 @@ filter_term filter_term: BFT_SAMPLE BFT_OP BFT_NUM { - $$ = perf_bpf_filter_expr__new($1, $2, $3); + $$ = perf_bpf_filter_expr__new($1.type, $1.part, $2, $3); } %% diff --git a/tools/perf/util/bpf_skel/sample-filter.h b/tools/perf/util/bpf_skel/sample-filter.h index 862060bfda14..6b9fd554ad7b 100644 --- a/tools/perf/util/bpf_skel/sample-filter.h +++ b/tools/perf/util/bpf_skel/sample-filter.h @@ -17,7 +17,8 @@ enum perf_bpf_filter_op { /* BPF map entry for filtering */ struct perf_bpf_filter_entry { enum perf_bpf_filter_op op; - __u64 flags; + __u32 part; /* sub-sample type info when it has multiple values */ + __u64 flags; /* perf sample type flags */ __u64 value; }; diff --git a/tools/perf/util/bpf_skel/sample_filter.bpf.c b/tools/perf/util/bpf_skel/sample_filter.bpf.c index c07256279c3e..dddf38c27bb7 100644 --- a/tools/perf/util/bpf_skel/sample_filter.bpf.c +++ b/tools/perf/util/bpf_skel/sample_filter.bpf.c @@ -40,7 +40,10 @@ static inline __u64 perf_get_sample(struct bpf_perf_event_data_kern *kctx, case PERF_SAMPLE_ID: return kctx->data->id; case PERF_SAMPLE_TID: - return kctx->data->tid_entry.tid; + if (entry->part) + return kctx->data->tid_entry.pid; + else + return kctx->data->tid_entry.tid; case PERF_SAMPLE_CPU: return kctx->data->cpu_entry.cpu; case PERF_SAMPLE_TIME: -- cgit v1.2.3-58-ga151 From 409bcd806749f23852581f54736a6206d1601248 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Tue, 14 Mar 2023 16:42:33 -0700 Subject: perf bpf filter: Add more weight sample data support The weight data consists of a couple of fields with the PERF_SAMPLE_WEIGHT_STRUCT. Add weight{1,2,3} term to select them separately. Also add their aliases like 'ins_lat', 'p_stage_cyc' and 'retire_lat'. Signed-off-by: Namhyung Kim Acked-by: Jiri Olsa Cc: Adrian Hunter Cc: Andi Kleen Cc: Hao Luo Cc: Ian Rogers Cc: Ingo Molnar Cc: James Clark Cc: Kan Liang Cc: Leo Yan Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Song Liu Cc: Stephane Eranian Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230314234237.3008956-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/bpf-filter.l | 6 ++++++ tools/perf/util/bpf_skel/sample_filter.bpf.c | 8 ++++++++ 2 files changed, 14 insertions(+) (limited to 'tools') diff --git a/tools/perf/util/bpf-filter.l b/tools/perf/util/bpf-filter.l index ec12fc4d2ab8..419f923b35c0 100644 --- a/tools/perf/util/bpf-filter.l +++ b/tools/perf/util/bpf-filter.l @@ -71,6 +71,12 @@ addr { return sample(PERF_SAMPLE_ADDR); } period { return sample(PERF_SAMPLE_PERIOD); } txn { return sample(PERF_SAMPLE_TRANSACTION); } weight { return sample(PERF_SAMPLE_WEIGHT); } +weight1 { return sample_part(PERF_SAMPLE_WEIGHT_STRUCT, 1); } +weight2 { return sample_part(PERF_SAMPLE_WEIGHT_STRUCT, 2); } +weight3 { return sample_part(PERF_SAMPLE_WEIGHT_STRUCT, 3); } +ins_lat { return sample_part(PERF_SAMPLE_WEIGHT_STRUCT, 2); } /* alias for weight2 */ +p_stage_cyc { return sample_part(PERF_SAMPLE_WEIGHT_STRUCT, 3); } /* alias for weight3 */ +retire_lat { return sample_part(PERF_SAMPLE_WEIGHT_STRUCT, 3); } /* alias for weight3 */ phys_addr { return sample(PERF_SAMPLE_PHYS_ADDR); } code_pgsz { return sample(PERF_SAMPLE_CODE_PAGE_SIZE); } data_pgsz { return sample(PERF_SAMPLE_DATA_PAGE_SIZE); } diff --git a/tools/perf/util/bpf_skel/sample_filter.bpf.c b/tools/perf/util/bpf_skel/sample_filter.bpf.c index dddf38c27bb7..d930401c5bfc 100644 --- a/tools/perf/util/bpf_skel/sample_filter.bpf.c +++ b/tools/perf/util/bpf_skel/sample_filter.bpf.c @@ -54,6 +54,14 @@ static inline __u64 perf_get_sample(struct bpf_perf_event_data_kern *kctx, return kctx->data->period; case PERF_SAMPLE_TRANSACTION: return kctx->data->txn; + case PERF_SAMPLE_WEIGHT_STRUCT: + if (entry->part == 1) + return kctx->data->weight.var1_dw; + if (entry->part == 2) + return kctx->data->weight.var2_w; + if (entry->part == 3) + return kctx->data->weight.var3_w; + /* fall through */ case PERF_SAMPLE_WEIGHT: return kctx->data->weight.full; case PERF_SAMPLE_PHYS_ADDR: -- cgit v1.2.3-58-ga151 From ff612055fb79e24c75f682f5b0e30cfc370ee59d Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Tue, 14 Mar 2023 16:42:34 -0700 Subject: perf bpf filter: Add data_src sample data support The data_src has many entries to express memory behaviors. Add each term separately so that users can combine them for their purpose. I didn't add prefix for the constants for simplicity as they are mostly distinguishable but I had to use l1_miss and l2_hit for mem_dtlb since mem_lvl has different values for the same names. Note that I decided mem_lvl to be used as an alias of mem_lvlnum as it's deprecated now. According to the comment in the UAPI header, users should use the mix of mem_lvlnum, mem_remote and mem_snoop. Also the SNOOPX bits are concatenated to mem_snoop for simplicity. The following terms are used for data_src and the corresponding perf sample data fields: * mem_op : { load, store, pfetch, exec } * mem_lvl: { l1, l2, l3, l4, cxl, io, any_cache, lfb, ram, pmem } * mem_snoop: { none, hit, miss, hitm, fwd, peer } * mem_remote: { remote } * mem_lock: { locked } * mem_dtlb { l1_hit, l1_miss, l2_hit, l2_miss, any_hit, any_miss, walk, fault } * mem_blk { by_data, by_addr } * mem_hops { hops0, hops1, hops2, hops3 } We can now use a filter expression like below: 'mem_op == load, mem_lvl <= l2, mem_dtlb == l1_hit' 'mem_dtlb == l2_miss, mem_hops > hops1' 'mem_lvl == ram, mem_remote == 1' Note that 'na' is shared among the terms as it has the same value except for mem_lvl. I don't have a good idea to handle that for now. Signed-off-by: Namhyung Kim Acked-by: Jiri Olsa Cc: Adrian Hunter Cc: Andi Kleen Cc: Hao Luo Cc: Ian Rogers Cc: Ingo Molnar Cc: James Clark Cc: Kan Liang Cc: Leo Yan Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Song Liu Cc: Stephane Eranian Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230314234237.3008956-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/bpf-filter.l | 61 ++++++++++++++++++++++++++++ tools/perf/util/bpf_skel/sample_filter.bpf.c | 23 +++++++++++ 2 files changed, 84 insertions(+) (limited to 'tools') diff --git a/tools/perf/util/bpf-filter.l b/tools/perf/util/bpf-filter.l index 419f923b35c0..3e66b7a0215e 100644 --- a/tools/perf/util/bpf-filter.l +++ b/tools/perf/util/bpf-filter.l @@ -42,6 +42,12 @@ static int value(int base) return BFT_NUM; } +static int constant(int val) +{ + perf_bpf_filter_lval.num = val; + return BFT_NUM; +} + static int error(const char *str) { printf("perf_bpf_filter: Unexpected filter %s: %s\n", str, perf_bpf_filter_text); @@ -80,6 +86,15 @@ retire_lat { return sample_part(PERF_SAMPLE_WEIGHT_STRUCT, 3); } /* alias for we phys_addr { return sample(PERF_SAMPLE_PHYS_ADDR); } code_pgsz { return sample(PERF_SAMPLE_CODE_PAGE_SIZE); } data_pgsz { return sample(PERF_SAMPLE_DATA_PAGE_SIZE); } +mem_op { return sample_part(PERF_SAMPLE_DATA_SRC, 1); } +mem_lvlnum { return sample_part(PERF_SAMPLE_DATA_SRC, 2); } +mem_lvl { return sample_part(PERF_SAMPLE_DATA_SRC, 2); } /* alias for mem_lvlnum */ +mem_snoop { return sample_part(PERF_SAMPLE_DATA_SRC, 3); } /* include snoopx */ +mem_remote { return sample_part(PERF_SAMPLE_DATA_SRC, 4); } +mem_lock { return sample_part(PERF_SAMPLE_DATA_SRC, 5); } +mem_dtlb { return sample_part(PERF_SAMPLE_DATA_SRC, 6); } +mem_blk { return sample_part(PERF_SAMPLE_DATA_SRC, 7); } +mem_hops { return sample_part(PERF_SAMPLE_DATA_SRC, 8); } "==" { return operator(PBF_OP_EQ); } "!=" { return operator(PBF_OP_NEQ); } @@ -89,6 +104,52 @@ data_pgsz { return sample(PERF_SAMPLE_DATA_PAGE_SIZE); } "<=" { return operator(PBF_OP_LE); } "&" { return operator(PBF_OP_AND); } +na { return constant(PERF_MEM_OP_NA); } +load { return constant(PERF_MEM_OP_LOAD); } +store { return constant(PERF_MEM_OP_STORE); } +pfetch { return constant(PERF_MEM_OP_PFETCH); } +exec { return constant(PERF_MEM_OP_EXEC); } + +l1 { return constant(PERF_MEM_LVLNUM_L1); } +l2 { return constant(PERF_MEM_LVLNUM_L2); } +l3 { return constant(PERF_MEM_LVLNUM_L3); } +l4 { return constant(PERF_MEM_LVLNUM_L4); } +cxl { return constant(PERF_MEM_LVLNUM_CXL); } +io { return constant(PERF_MEM_LVLNUM_IO); } +any_cache { return constant(PERF_MEM_LVLNUM_ANY_CACHE); } +lfb { return constant(PERF_MEM_LVLNUM_LFB); } +ram { return constant(PERF_MEM_LVLNUM_RAM); } +pmem { return constant(PERF_MEM_LVLNUM_PMEM); } + +none { return constant(PERF_MEM_SNOOP_NONE); } +hit { return constant(PERF_MEM_SNOOP_HIT); } +miss { return constant(PERF_MEM_SNOOP_MISS); } +hitm { return constant(PERF_MEM_SNOOP_HITM); } +fwd { return constant(PERF_MEM_SNOOPX_FWD); } +peer { return constant(PERF_MEM_SNOOPX_PEER); } + +remote { return constant(PERF_MEM_REMOTE_REMOTE); } + +locked { return constant(PERF_MEM_LOCK_LOCKED); } + +l1_hit { return constant(PERF_MEM_TLB_L1 | PERF_MEM_TLB_HIT); } +l1_miss { return constant(PERF_MEM_TLB_L1 | PERF_MEM_TLB_MISS); } +l2_hit { return constant(PERF_MEM_TLB_L2 | PERF_MEM_TLB_HIT); } +l2_miss { return constant(PERF_MEM_TLB_L2 | PERF_MEM_TLB_MISS); } +any_hit { return constant(PERF_MEM_TLB_HIT); } +any_miss { return constant(PERF_MEM_TLB_MISS); } +walk { return constant(PERF_MEM_TLB_WK); } +os { return constant(PERF_MEM_TLB_OS); } +fault { return constant(PERF_MEM_TLB_OS); } /* alias for os */ + +by_data { return constant(PERF_MEM_BLK_DATA); } +by_addr { return constant(PERF_MEM_BLK_ADDR); } + +hops0 { return constant(PERF_MEM_HOPS_0); } +hops1 { return constant(PERF_MEM_HOPS_1); } +hops2 { return constant(PERF_MEM_HOPS_2); } +hops3 { return constant(PERF_MEM_HOPS_3); } + "," { return ','; } {ident} { return error("ident"); } diff --git a/tools/perf/util/bpf_skel/sample_filter.bpf.c b/tools/perf/util/bpf_skel/sample_filter.bpf.c index d930401c5bfc..88dbc788d257 100644 --- a/tools/perf/util/bpf_skel/sample_filter.bpf.c +++ b/tools/perf/util/bpf_skel/sample_filter.bpf.c @@ -70,6 +70,29 @@ static inline __u64 perf_get_sample(struct bpf_perf_event_data_kern *kctx, return kctx->data->code_page_size; case PERF_SAMPLE_DATA_PAGE_SIZE: return kctx->data->data_page_size; + case PERF_SAMPLE_DATA_SRC: + if (entry->part == 1) + return kctx->data->data_src.mem_op; + if (entry->part == 2) + return kctx->data->data_src.mem_lvl_num; + if (entry->part == 3) { + __u32 snoop = kctx->data->data_src.mem_snoop; + __u32 snoopx = kctx->data->data_src.mem_snoopx; + + return (snoopx << 5) | snoop; + } + if (entry->part == 4) + return kctx->data->data_src.mem_remote; + if (entry->part == 5) + return kctx->data->data_src.mem_lock; + if (entry->part == 6) + return kctx->data->data_src.mem_dtlb; + if (entry->part == 7) + return kctx->data->data_src.mem_blk; + if (entry->part == 8) + return kctx->data->data_src.mem_hops; + /* return the whole word */ + return kctx->data->data_src.val; default: break; } -- cgit v1.2.3-58-ga151 From 46996dd7f655889a3dbbb514a0fa8bb614d6bd74 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Tue, 14 Mar 2023 16:42:35 -0700 Subject: perf bpf filter: Add logical OR operator It supports two or more expressions connected as a group and the group result is considered true when one of them returns true. The new group operators (GROUP_BEGIN and GROUP_END) are added to setup and check the condition. As it doesn't allow nested groups, the condition is saved in local variables. For example, the following is to get samples only if the data source memory level is L2 cache or the weight value is greater than 30. $ sudo ./perf record -adW -e cpu/mem-loads/pp \ > --filter 'mem_lvl == l2 || weight > 30' -- sleep 1 $ sudo ./perf script -F data_src,weight 10668100842 |OP LOAD|LVL L3 or L3 hit|SNP None|TLB L1 or L2 hit|LCK No|BLK N/A 47 11868100242 |OP LOAD|LVL LFB/MAB or LFB/MAB hit|SNP None|TLB L1 or L2 hit|LCK No|BLK N/A 57 10668100842 |OP LOAD|LVL L3 or L3 hit|SNP None|TLB L1 or L2 hit|LCK No|BLK N/A 56 10650100842 |OP LOAD|LVL L3 or L3 hit|SNP None|TLB L2 miss|LCK No|BLK N/A 144 10468100442 |OP LOAD|LVL L2 or L2 hit|SNP None|TLB L1 or L2 hit|LCK No|BLK N/A 16 10468100442 |OP LOAD|LVL L2 or L2 hit|SNP None|TLB L1 or L2 hit|LCK No|BLK N/A 20 11868100242 |OP LOAD|LVL LFB/MAB or LFB/MAB hit|SNP None|TLB L1 or L2 hit|LCK No|BLK N/A 189 1026a100142 |OP LOAD|LVL L1 or L1 hit|SNP None|TLB L1 or L2 hit|LCK Yes|BLK N/A 193 10468100442 |OP LOAD|LVL L2 or L2 hit|SNP None|TLB L1 or L2 hit|LCK No|BLK N/A 18 ... Signed-off-by: Namhyung Kim Acked-by: Jiri Olsa Cc: Adrian Hunter Cc: Andi Kleen Cc: Hao Luo Cc: Ian Rogers Cc: Ingo Molnar Cc: James Clark Cc: Kan Liang Cc: Leo Yan Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Song Liu Cc: Stephane Eranian Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230314234237.3008956-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/bpf-filter.c | 25 ++++++++++++++++++ tools/perf/util/bpf-filter.h | 1 + tools/perf/util/bpf-filter.l | 1 + tools/perf/util/bpf-filter.y | 25 ++++++++++++++++-- tools/perf/util/bpf_skel/sample-filter.h | 6 +++-- tools/perf/util/bpf_skel/sample_filter.bpf.c | 38 ++++++++++++++++++---------- 6 files changed, 79 insertions(+), 17 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/bpf-filter.c b/tools/perf/util/bpf-filter.c index 743c69fd6cd4..bd638737e12f 100644 --- a/tools/perf/util/bpf-filter.c +++ b/tools/perf/util/bpf-filter.c @@ -42,8 +42,32 @@ int perf_bpf_filter__prepare(struct evsel *evsel) }; bpf_map_update_elem(fd, &i, &entry, BPF_ANY); i++; + + if (expr->op == PBF_OP_GROUP_BEGIN) { + struct perf_bpf_filter_expr *group; + + list_for_each_entry(group, &expr->groups, list) { + struct perf_bpf_filter_entry group_entry = { + .op = group->op, + .part = group->part, + .flags = group->sample_flags, + .value = group->val, + }; + bpf_map_update_elem(fd, &i, &group_entry, BPF_ANY); + i++; + } + + memset(&entry, 0, sizeof(entry)); + entry.op = PBF_OP_GROUP_END; + bpf_map_update_elem(fd, &i, &entry, BPF_ANY); + i++; + } } + if (i > MAX_FILTERS) { + pr_err("Too many filters: %d (max = %d)\n", i, MAX_FILTERS); + return -1; + } prog = skel->progs.perf_sample_filter; for (x = 0; x < xyarray__max_x(evsel->core.fd); x++) { for (y = 0; y < xyarray__max_y(evsel->core.fd); y++) { @@ -89,6 +113,7 @@ struct perf_bpf_filter_expr *perf_bpf_filter_expr__new(unsigned long sample_flag expr->part = part; expr->op = op; expr->val = val; + INIT_LIST_HEAD(&expr->groups); } return expr; } diff --git a/tools/perf/util/bpf-filter.h b/tools/perf/util/bpf-filter.h index 3f8827bd965f..7afd159411b8 100644 --- a/tools/perf/util/bpf-filter.h +++ b/tools/perf/util/bpf-filter.h @@ -8,6 +8,7 @@ struct perf_bpf_filter_expr { struct list_head list; + struct list_head groups; enum perf_bpf_filter_op op; int part; unsigned long sample_flags; diff --git a/tools/perf/util/bpf-filter.l b/tools/perf/util/bpf-filter.l index 3e66b7a0215e..d4ff0f1345cd 100644 --- a/tools/perf/util/bpf-filter.l +++ b/tools/perf/util/bpf-filter.l @@ -151,6 +151,7 @@ hops2 { return constant(PERF_MEM_HOPS_2); } hops3 { return constant(PERF_MEM_HOPS_3); } "," { return ','; } +"||" { return BFT_LOGICAL_OR; } {ident} { return error("ident"); } . { return error("input"); } diff --git a/tools/perf/util/bpf-filter.y b/tools/perf/util/bpf-filter.y index 0ca6532afd8d..07d6c7926c13 100644 --- a/tools/perf/util/bpf-filter.y +++ b/tools/perf/util/bpf-filter.y @@ -28,8 +28,8 @@ static void perf_bpf_filter_error(struct list_head *expr __maybe_unused, struct perf_bpf_filter_expr *expr; } -%token BFT_SAMPLE BFT_OP BFT_ERROR BFT_NUM -%type filter_term +%token BFT_SAMPLE BFT_OP BFT_ERROR BFT_NUM BFT_LOGICAL_OR +%type filter_term filter_expr %destructor { free ($$); } %type BFT_SAMPLE %type BFT_OP @@ -49,6 +49,27 @@ filter_term } filter_term: +filter_term BFT_LOGICAL_OR filter_expr +{ + struct perf_bpf_filter_expr *expr; + + if ($1->op == PBF_OP_GROUP_BEGIN) { + expr = $1; + } else { + expr = perf_bpf_filter_expr__new(0, 0, PBF_OP_GROUP_BEGIN, 1); + list_add_tail(&$1->list, &expr->groups); + } + expr->val++; + list_add_tail(&$3->list, &expr->groups); + $$ = expr; +} +| +filter_expr +{ + $$ = $1; +} + +filter_expr: BFT_SAMPLE BFT_OP BFT_NUM { $$ = perf_bpf_filter_expr__new($1.type, $1.part, $2, $3); diff --git a/tools/perf/util/bpf_skel/sample-filter.h b/tools/perf/util/bpf_skel/sample-filter.h index 6b9fd554ad7b..2e96e1ab084a 100644 --- a/tools/perf/util/bpf_skel/sample-filter.h +++ b/tools/perf/util/bpf_skel/sample-filter.h @@ -1,7 +1,7 @@ #ifndef PERF_UTIL_BPF_SKEL_SAMPLE_FILTER_H #define PERF_UTIL_BPF_SKEL_SAMPLE_FILTER_H -#define MAX_FILTERS 32 +#define MAX_FILTERS 64 /* supported filter operations */ enum perf_bpf_filter_op { @@ -11,7 +11,9 @@ enum perf_bpf_filter_op { PBF_OP_GE, PBF_OP_LT, PBF_OP_LE, - PBF_OP_AND + PBF_OP_AND, + PBF_OP_GROUP_BEGIN, + PBF_OP_GROUP_END, }; /* BPF map entry for filtering */ diff --git a/tools/perf/util/bpf_skel/sample_filter.bpf.c b/tools/perf/util/bpf_skel/sample_filter.bpf.c index 88dbc788d257..57e3c67d6d37 100644 --- a/tools/perf/util/bpf_skel/sample_filter.bpf.c +++ b/tools/perf/util/bpf_skel/sample_filter.bpf.c @@ -99,6 +99,14 @@ static inline __u64 perf_get_sample(struct bpf_perf_event_data_kern *kctx, return 0; } +#define CHECK_RESULT(data, op, val) \ + if (!(data op val)) { \ + if (!in_group) \ + goto drop; \ + } else if (in_group) { \ + group_result = 1; \ + } + /* BPF program to be called from perf event overflow handler */ SEC("perf_event") int perf_sample_filter(void *ctx) @@ -106,6 +114,8 @@ int perf_sample_filter(void *ctx) struct bpf_perf_event_data_kern *kctx; struct perf_bpf_filter_entry *entry; __u64 sample_data; + int in_group = 0; + int group_result = 0; int i; kctx = bpf_cast_to_kern_ctx(ctx); @@ -120,32 +130,34 @@ int perf_sample_filter(void *ctx) switch (entry->op) { case PBF_OP_EQ: - if (!(sample_data == entry->value)) - goto drop; + CHECK_RESULT(sample_data, ==, entry->value) break; case PBF_OP_NEQ: - if (!(sample_data != entry->value)) - goto drop; + CHECK_RESULT(sample_data, !=, entry->value) break; case PBF_OP_GT: - if (!(sample_data > entry->value)) - goto drop; + CHECK_RESULT(sample_data, >, entry->value) break; case PBF_OP_GE: - if (!(sample_data >= entry->value)) - goto drop; + CHECK_RESULT(sample_data, >=, entry->value) break; case PBF_OP_LT: - if (!(sample_data < entry->value)) - goto drop; + CHECK_RESULT(sample_data, <, entry->value) break; case PBF_OP_LE: - if (!(sample_data <= entry->value)) - goto drop; + CHECK_RESULT(sample_data, <=, entry->value) break; case PBF_OP_AND: - if (!(sample_data & entry->value)) + CHECK_RESULT(sample_data, &, entry->value) + break; + case PBF_OP_GROUP_BEGIN: + in_group = 1; + group_result = 0; + break; + case PBF_OP_GROUP_END: + if (group_result == 0) goto drop; + in_group = 0; break; } } -- cgit v1.2.3-58-ga151 From 4310551b76e0d6762abb78fc23d50dcc3c608c33 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Tue, 14 Mar 2023 16:42:36 -0700 Subject: perf bpf filter: Show warning for missing sample flags For a BPF filter to work properly, users need to provide appropriate options to enable the sample types. Otherwise the BPF program would see an invalid value (i.e. always 0) and filter won't work well. Show a warning message if sample types are missing like below. $ sudo ./perf record -e cycles --filter 'addr < 100' true Error: cycles event does not have PERF_SAMPLE_ADDR Hint: please add -d option to perf record. failed to set filter "BPF" on event cycles with 22 (Invalid argument) Signed-off-by: Namhyung Kim Cc: Adrian Hunter Cc: Andi Kleen Cc: Hao Luo Cc: Ian Rogers Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: Kan Liang Cc: Leo Yan Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Song Liu Cc: Stephane Eranian Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230314234237.3008956-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-record.c | 2 +- tools/perf/util/bpf-filter.c | 62 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c index 6df8b823859d..7b7e74a56346 100644 --- a/tools/perf/builtin-record.c +++ b/tools/perf/builtin-record.c @@ -1353,7 +1353,7 @@ try_again: if (evlist__apply_filters(evlist, &pos)) { pr_err("failed to set filter \"%s\" on event %s with %d (%s)\n", - pos->filter, evsel__name(pos), errno, + pos->filter ?: "BPF", evsel__name(pos), errno, str_error_r(errno, msg, sizeof(msg))); rc = -1; goto out; diff --git a/tools/perf/util/bpf-filter.c b/tools/perf/util/bpf-filter.c index bd638737e12f..0b30688d78a7 100644 --- a/tools/perf/util/bpf-filter.c +++ b/tools/perf/util/bpf-filter.c @@ -17,6 +17,64 @@ #define FD(e, x, y) (*(int *)xyarray__entry(e->core.fd, x, y)) +#define __PERF_SAMPLE_TYPE(st, opt) { st, #st, opt } +#define PERF_SAMPLE_TYPE(_st, opt) __PERF_SAMPLE_TYPE(PERF_SAMPLE_##_st, opt) + +static const struct perf_sample_info { + u64 type; + const char *name; + const char *option; +} sample_table[] = { + /* default sample flags */ + PERF_SAMPLE_TYPE(IP, NULL), + PERF_SAMPLE_TYPE(TID, NULL), + PERF_SAMPLE_TYPE(PERIOD, NULL), + /* flags mostly set by default, but still have options */ + PERF_SAMPLE_TYPE(ID, "--sample-identifier"), + PERF_SAMPLE_TYPE(CPU, "--sample-cpu"), + PERF_SAMPLE_TYPE(TIME, "-T"), + /* optional sample flags */ + PERF_SAMPLE_TYPE(ADDR, "-d"), + PERF_SAMPLE_TYPE(DATA_SRC, "-d"), + PERF_SAMPLE_TYPE(PHYS_ADDR, "--phys-data"), + PERF_SAMPLE_TYPE(WEIGHT, "-W"), + PERF_SAMPLE_TYPE(WEIGHT_STRUCT, "-W"), + PERF_SAMPLE_TYPE(TRANSACTION, "--transaction"), + PERF_SAMPLE_TYPE(CODE_PAGE_SIZE, "--code-page-size"), + PERF_SAMPLE_TYPE(DATA_PAGE_SIZE, "--data-page-size"), +}; + +static const struct perf_sample_info *get_sample_info(u64 flags) +{ + size_t i; + + for (i = 0; i < ARRAY_SIZE(sample_table); i++) { + if (sample_table[i].type == flags) + return &sample_table[i]; + } + return NULL; +} + +static int check_sample_flags(struct evsel *evsel, struct perf_bpf_filter_expr *expr) +{ + const struct perf_sample_info *info; + + if (evsel->core.attr.sample_type & expr->sample_flags) + return 0; + + info = get_sample_info(expr->sample_flags); + if (info == NULL) { + pr_err("Error: %s event does not have sample flags %lx\n", + evsel__name(evsel), expr->sample_flags); + return -1; + } + + pr_err("Error: %s event does not have %s\n", evsel__name(evsel), info->name); + if (info->option) + pr_err(" Hint: please add %s option to perf record\n", info->option); + return -1; +} + int perf_bpf_filter__prepare(struct evsel *evsel) { int i, x, y, fd; @@ -40,6 +98,10 @@ int perf_bpf_filter__prepare(struct evsel *evsel) .flags = expr->sample_flags, .value = expr->val, }; + + if (check_sample_flags(evsel, expr) < 0) + return -1; + bpf_map_update_elem(fd, &i, &entry, BPF_ANY); i++; -- cgit v1.2.3-58-ga151 From c46bf3bd00167e09729f884dd479b0a8d1a63f95 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Tue, 14 Mar 2023 16:42:37 -0700 Subject: perf record: Update documentation for BPF filters Add more description and examples. Signed-off-by: Namhyung Kim Cc: Adrian Hunter Cc: Andi Kleen Cc: Hao Luo Cc: Ian Rogers Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: Kan Liang Cc: Leo Yan Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Song Liu Cc: Stephane Eranian Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230314234237.3008956-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Documentation/perf-record.txt | 47 +++++++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/Documentation/perf-record.txt b/tools/perf/Documentation/perf-record.txt index 122f71726eaa..680396c56bd1 100644 --- a/tools/perf/Documentation/perf-record.txt +++ b/tools/perf/Documentation/perf-record.txt @@ -183,7 +183,52 @@ OPTIONS A BPF filter can access the sample data and make a decision based on the data. Users need to set an appropriate sample type to use the BPF - filter. + filter. BPF filters need root privilege. + + The sample data field can be specified in lower case letter. Multiple + filters can be separated with comma. For example, + + --filter 'period > 1000, cpu == 1' + or + --filter 'mem_op == load || mem_op == store, mem_lvl > l1' + + The former filter only accept samples with period greater than 1000 AND + CPU number is 1. The latter one accepts either load and store memory + operations but it should have memory level above the L1. Since the + mem_op and mem_lvl fields come from the (memory) data_source, it'd only + work with some events which set the data_source field. + + Also user should request to collect that information (with -d option in + the above case). Otherwise, the following message will be shown. + + $ sudo perf record -e cycles --filter 'mem_op == load' + Error: cycles event does not have PERF_SAMPLE_DATA_SRC + Hint: please add -d option to perf record. + failed to set filter "BPF" on event cycles with 22 (Invalid argument) + + Essentially the BPF filter expression is: + + (("," | "||") )* + + The can be one of: + ip, id, tid, pid, cpu, time, addr, period, txn, weight, phys_addr, + code_pgsz, data_pgsz, weight1, weight2, weight3, ins_lat, retire_lat, + p_stage_cyc, mem_op, mem_lvl, mem_snoop, mem_remote, mem_lock, + mem_dtlb, mem_blk, mem_hops + + The can be one of: + ==, !=, >, >=, <, <=, & + + The can be one of: + (for any term) + na, load, store, pfetch, exec (for mem_op) + l1, l2, l3, l4, cxl, io, any_cache, lfb, ram, pmem (for mem_lvl) + na, none, hit, miss, hitm, fwd, peer (for mem_snoop) + remote (for mem_remote) + na, locked (for mem_locked) + na, l1_hit, l1_miss, l2_hit, l2_miss, any_hit, any_miss, walk, fault (for mem_dtlb) + na, by_data, by_addr (for mem_blk) + hops0, hops1, hops2, hops3 (for mem_hops) --exclude-perf:: Don't record events issued by perf itself. This option should follow -- cgit v1.2.3-58-ga151 From 9c3aa1f41178d75c7eabfa818bc02b698b5f152e Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Wed, 15 Mar 2023 22:50:57 +0800 Subject: perf kvm: Refactor overall statistics Currently the tool computes overall statistics when sort the results. This patch refactors overall statistics during events processing, therefore, the function update_total_coun() is not needed anymore, an extra benefit is we can de-couple code between the statistics and the sorting. This patch is not expected any functionality changes. Reviewed-by: James Clark Signed-off-by: Leo Yan Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: John Garry Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230315145112.186603-2-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-kvm.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-kvm.c b/tools/perf/builtin-kvm.c index 641e739c717c..0172e5b0d26e 100644 --- a/tools/perf/builtin-kvm.c +++ b/tools/perf/builtin-kvm.c @@ -278,9 +278,14 @@ static double kvm_event_rel_stddev(int vcpu_id, struct kvm_event *event) avg_stats(&kvm_stats->stats)); } -static bool update_kvm_event(struct kvm_event *event, int vcpu_id, +static bool update_kvm_event(struct perf_kvm_stat *kvm, + struct kvm_event *event, int vcpu_id, u64 time_diff) { + /* Update overall statistics */ + kvm->total_count++; + kvm->total_time += time_diff; + if (vcpu_id == -1) { kvm_update_event_stats(&event->total, time_diff); return true; @@ -399,7 +404,7 @@ static bool handle_end_event(struct perf_kvm_stat *kvm, } } - return update_kvm_event(event, vcpu, time_diff); + return update_kvm_event(kvm, event, vcpu, time_diff); } static @@ -526,15 +531,6 @@ static void insert_to_result(struct rb_root *result, struct kvm_event *event, rb_insert_color(&event->rb, result); } -static void -update_total_count(struct perf_kvm_stat *kvm, struct kvm_event *event) -{ - int vcpu = kvm->trace_vcpu; - - kvm->total_count += get_event_count(event, vcpu); - kvm->total_time += get_event_time(event, vcpu); -} - static bool event_is_valid(struct kvm_event *event, int vcpu) { return !!get_event_count(event, vcpu); @@ -549,7 +545,6 @@ static void sort_result(struct perf_kvm_stat *kvm) for (i = 0; i < EVENTS_CACHE_SIZE; i++) { list_for_each_entry(event, &kvm->kvm_events_cache[i], hash_entry) { if (event_is_valid(event, vcpu)) { - update_total_count(kvm, event); insert_to_result(&kvm->result, event, kvm->compare, vcpu); } -- cgit v1.2.3-58-ga151 From a7d451a8733c978848ede58333be25b10889df82 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Wed, 15 Mar 2023 22:50:58 +0800 Subject: perf kvm: Add pointer to 'perf_kvm_stat' in kvm event Sometimes, handling kvm events needs to base on global variables, e.g. when read event counts we need to know the target vcpu ID; the global variables are stored in structure perf_kvm_stat. This patch adds add a 'perf_kvm_stat' pointer in kvm event structure, it is to be used by later refactoring. Reviewed-by: James Clark Signed-off-by: Leo Yan Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: John Garry Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230315145112.186603-2-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-kvm.c | 6 ++++-- tools/perf/util/kvm-stat.h | 5 +++-- 2 files changed, 7 insertions(+), 4 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-kvm.c b/tools/perf/builtin-kvm.c index 0172e5b0d26e..3d2560ec6b37 100644 --- a/tools/perf/builtin-kvm.c +++ b/tools/perf/builtin-kvm.c @@ -209,7 +209,8 @@ static bool kvm_event_expand(struct kvm_event *event, int vcpu_id) return true; } -static struct kvm_event *kvm_alloc_init_event(struct event_key *key) +static struct kvm_event *kvm_alloc_init_event(struct perf_kvm_stat *kvm, + struct event_key *key) { struct kvm_event *event; @@ -219,6 +220,7 @@ static struct kvm_event *kvm_alloc_init_event(struct event_key *key) return NULL; } + event->perf_kvm = kvm; event->key = *key; init_stats(&event->total.stats); return event; @@ -238,7 +240,7 @@ static struct kvm_event *find_create_kvm_event(struct perf_kvm_stat *kvm, return event; } - event = kvm_alloc_init_event(key); + event = kvm_alloc_init_event(kvm, key); if (!event) return NULL; diff --git a/tools/perf/util/kvm-stat.h b/tools/perf/util/kvm-stat.h index 6f0fa05b62b6..40a4b66cfee6 100644 --- a/tools/perf/util/kvm-stat.h +++ b/tools/perf/util/kvm-stat.h @@ -24,10 +24,13 @@ struct kvm_event_stats { struct stats stats; }; +struct perf_kvm_stat; + struct kvm_event { struct list_head hash_entry; struct rb_node rb; + struct perf_kvm_stat *perf_kvm; struct event_key key; struct kvm_event_stats total; @@ -44,8 +47,6 @@ struct kvm_event_key { key_cmp_fun key; }; -struct perf_kvm_stat; - struct child_event_ops { void (*get_key)(struct evsel *evsel, struct perf_sample *sample, -- cgit v1.2.3-58-ga151 From f098376d16e94a0a14bd16264f28c72ee3b411c9 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Wed, 15 Mar 2023 22:50:59 +0800 Subject: perf kvm: Move up metrics helpers This patch moves up the helper functions of event's metrics for later adding code to call them. No any functionality changes, but has a function renaming from compare_kvm_event_{metric}() to cmp_event_{metric}(). Committer notes: Those helper functions are only used if this is true: if defined(HAVE_KVM_STAT_SUPPORT) && defined(HAVE_LIBTRACEEVENT) So keep them enclosed with that. Reviewed-by: James Clark Signed-off-by: Leo Yan Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: John Garry Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230315145112.186603-2-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-kvm.c | 74 +++++++++++++++++++++++++----------------------- 1 file changed, 38 insertions(+), 36 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-kvm.c b/tools/perf/builtin-kvm.c index 3d2560ec6b37..c11f5454f35c 100644 --- a/tools/perf/builtin-kvm.c +++ b/tools/perf/builtin-kvm.c @@ -49,6 +49,44 @@ #include #include +#if defined(HAVE_KVM_STAT_SUPPORT) && defined(HAVE_LIBTRACEEVENT) +#define GET_EVENT_KEY(func, field) \ +static u64 get_event_ ##func(struct kvm_event *event, int vcpu) \ +{ \ + if (vcpu == -1) \ + return event->total.field; \ + \ + if (vcpu >= event->max_vcpu) \ + return 0; \ + \ + return event->vcpu[vcpu].field; \ +} + +#define COMPARE_EVENT_KEY(func, field) \ +GET_EVENT_KEY(func, field) \ +static int cmp_event_ ## func(struct kvm_event *one, \ + struct kvm_event *two, int vcpu) \ +{ \ + return get_event_ ##func(one, vcpu) > \ + get_event_ ##func(two, vcpu); \ +} + +GET_EVENT_KEY(time, time); +GET_EVENT_KEY(max, stats.max); +GET_EVENT_KEY(min, stats.min); +COMPARE_EVENT_KEY(count, stats.n); +COMPARE_EVENT_KEY(mean, stats.mean); + +#define DEF_SORT_NAME_KEY(name, compare_key) \ + { #name, cmp_event_ ## compare_key } + +static struct kvm_event_key keys[] = { + DEF_SORT_NAME_KEY(sample, count), + DEF_SORT_NAME_KEY(time, mean), + { NULL, NULL } +}; +#endif // defined(HAVE_KVM_STAT_SUPPORT) && defined(HAVE_LIBTRACEEVENT) + static const char *get_filename_for_perf_kvm(void) { const char *filename; @@ -461,42 +499,6 @@ static bool handle_kvm_event(struct perf_kvm_stat *kvm, return true; } -#define GET_EVENT_KEY(func, field) \ -static u64 get_event_ ##func(struct kvm_event *event, int vcpu) \ -{ \ - if (vcpu == -1) \ - return event->total.field; \ - \ - if (vcpu >= event->max_vcpu) \ - return 0; \ - \ - return event->vcpu[vcpu].field; \ -} - -#define COMPARE_EVENT_KEY(func, field) \ -GET_EVENT_KEY(func, field) \ -static int compare_kvm_event_ ## func(struct kvm_event *one, \ - struct kvm_event *two, int vcpu)\ -{ \ - return get_event_ ##func(one, vcpu) > \ - get_event_ ##func(two, vcpu); \ -} - -GET_EVENT_KEY(time, time); -COMPARE_EVENT_KEY(count, stats.n); -COMPARE_EVENT_KEY(mean, stats.mean); -GET_EVENT_KEY(max, stats.max); -GET_EVENT_KEY(min, stats.min); - -#define DEF_SORT_NAME_KEY(name, compare_key) \ - { #name, compare_kvm_event_ ## compare_key } - -static struct kvm_event_key keys[] = { - DEF_SORT_NAME_KEY(sample, count), - DEF_SORT_NAME_KEY(time, mean), - { NULL, NULL } -}; - static bool select_key(struct perf_kvm_stat *kvm) { int i; -- cgit v1.2.3-58-ga151 From dd787ae4e8548a82350981b4b0046df6a92999f2 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Wed, 15 Mar 2023 22:51:00 +0800 Subject: perf kvm: Use subtraction for comparison metrics Currently the metrics comparison uses greater operator (>), it returns the boolean value (0 or 1). This patch changes to use subtraction as comparison result, which can be used by histograms sorting. Since the subtraction result is u64 type, we change key_cmp_fun's return type to int64_t to avoid overflow. Signed-off-by: Leo Yan Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230315145112.186603-2-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-kvm.c | 6 +++--- tools/perf/util/kvm-stat.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-kvm.c b/tools/perf/builtin-kvm.c index c11f5454f35c..fbdd46d38c13 100644 --- a/tools/perf/builtin-kvm.c +++ b/tools/perf/builtin-kvm.c @@ -64,10 +64,10 @@ static u64 get_event_ ##func(struct kvm_event *event, int vcpu) \ #define COMPARE_EVENT_KEY(func, field) \ GET_EVENT_KEY(func, field) \ -static int cmp_event_ ## func(struct kvm_event *one, \ +static int64_t cmp_event_ ## func(struct kvm_event *one, \ struct kvm_event *two, int vcpu) \ { \ - return get_event_ ##func(one, vcpu) > \ + return get_event_ ##func(one, vcpu) - \ get_event_ ##func(two, vcpu); \ } @@ -525,7 +525,7 @@ static void insert_to_result(struct rb_root *result, struct kvm_event *event, p = container_of(*rb, struct kvm_event, rb); parent = *rb; - if (bigger(event, p, vcpu)) + if (bigger(event, p, vcpu) > 0) rb = &(*rb)->rb_left; else rb = &(*rb)->rb_right; diff --git a/tools/perf/util/kvm-stat.h b/tools/perf/util/kvm-stat.h index 40a4b66cfee6..0c2400d9b227 100644 --- a/tools/perf/util/kvm-stat.h +++ b/tools/perf/util/kvm-stat.h @@ -40,7 +40,7 @@ struct kvm_event { struct kvm_event_stats *vcpu; }; -typedef int (*key_cmp_fun)(struct kvm_event*, struct kvm_event*, int); +typedef int64_t (*key_cmp_fun)(struct kvm_event*, struct kvm_event*, int); struct kvm_event_key { const char *name; -- cgit v1.2.3-58-ga151 From 2d31e0bff2f3dd5369a9b45e3d8c9ee325784e60 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Wed, 15 Mar 2023 22:51:01 +0800 Subject: perf kvm: Use macro to replace variable 'decode_str_len' The variable 'decode_str_len' defines the string length for KVM event name and every arch defines its own values. This introduces complexity that the variable definition are spreading in multiple source files under arch folder. This patch refactors code to use a macro KVM_EVENT_NAME_LEN to define event name length and thus remove the definitions in arch files. Signed-off-by: Leo Yan Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230315145112.186603-2-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/arm64/util/kvm-stat.c | 1 - tools/perf/arch/powerpc/util/kvm-stat.c | 3 +-- tools/perf/arch/s390/util/kvm-stat.c | 1 - tools/perf/arch/x86/util/kvm-stat.c | 7 +++---- tools/perf/builtin-kvm.c | 10 +++++----- tools/perf/util/kvm-stat.h | 3 ++- 6 files changed, 11 insertions(+), 14 deletions(-) (limited to 'tools') diff --git a/tools/perf/arch/arm64/util/kvm-stat.c b/tools/perf/arch/arm64/util/kvm-stat.c index 73d18e0ed6f6..72ca9bb45804 100644 --- a/tools/perf/arch/arm64/util/kvm-stat.c +++ b/tools/perf/arch/arm64/util/kvm-stat.c @@ -11,7 +11,6 @@ define_exit_reasons_table(arm64_trap_exit_reasons, kvm_arm_exception_class); const char *kvm_trap_exit_reason = "esr_ec"; const char *vcpu_id_str = "id"; -const int decode_str_len = 20; const char *kvm_exit_reason = "ret"; const char *kvm_entry_trace = "kvm:kvm_entry"; const char *kvm_exit_trace = "kvm:kvm_exit"; diff --git a/tools/perf/arch/powerpc/util/kvm-stat.c b/tools/perf/arch/powerpc/util/kvm-stat.c index 1a9b40ea92a5..d04a08c9fd19 100644 --- a/tools/perf/arch/powerpc/util/kvm-stat.c +++ b/tools/perf/arch/powerpc/util/kvm-stat.c @@ -14,7 +14,6 @@ #define NR_TPS 4 const char *vcpu_id_str = "vcpu_id"; -const int decode_str_len = 40; const char *kvm_entry_trace = "kvm_hv:kvm_guest_enter"; const char *kvm_exit_trace = "kvm_hv:kvm_guest_exit"; @@ -80,7 +79,7 @@ static void hcall_event_decode_key(struct perf_kvm_stat *kvm __maybe_unused, { const char *hcall_reason = get_hcall_exit_reason(key->key); - scnprintf(decode, decode_str_len, "%s", hcall_reason); + scnprintf(decode, KVM_EVENT_NAME_LEN, "%s", hcall_reason); } static struct kvm_events_ops hcall_events = { diff --git a/tools/perf/arch/s390/util/kvm-stat.c b/tools/perf/arch/s390/util/kvm-stat.c index 34da89ced29a..0aed92df51ba 100644 --- a/tools/perf/arch/s390/util/kvm-stat.c +++ b/tools/perf/arch/s390/util/kvm-stat.c @@ -19,7 +19,6 @@ define_exit_reasons_table(sie_diagnose_codes, diagnose_codes); define_exit_reasons_table(sie_icpt_prog_codes, icpt_prog_codes); const char *vcpu_id_str = "id"; -const int decode_str_len = 40; const char *kvm_exit_reason = "icptcode"; const char *kvm_entry_trace = "kvm:kvm_s390_sie_enter"; const char *kvm_exit_trace = "kvm:kvm_s390_sie_exit"; diff --git a/tools/perf/arch/x86/util/kvm-stat.c b/tools/perf/arch/x86/util/kvm-stat.c index c5dd54f6ef5e..ef513def03ba 100644 --- a/tools/perf/arch/x86/util/kvm-stat.c +++ b/tools/perf/arch/x86/util/kvm-stat.c @@ -18,7 +18,6 @@ static struct kvm_events_ops exit_events = { }; const char *vcpu_id_str = "vcpu_id"; -const int decode_str_len = 20; const char *kvm_exit_reason = "exit_reason"; const char *kvm_entry_trace = "kvm:kvm_entry"; const char *kvm_exit_trace = "kvm:kvm_exit"; @@ -77,7 +76,7 @@ static void mmio_event_decode_key(struct perf_kvm_stat *kvm __maybe_unused, struct event_key *key, char *decode) { - scnprintf(decode, decode_str_len, "%#lx:%s", + scnprintf(decode, KVM_EVENT_NAME_LEN, "%#lx:%s", (unsigned long)key->key, key->info == KVM_TRACE_MMIO_WRITE ? "W" : "R"); } @@ -121,7 +120,7 @@ static void ioport_event_decode_key(struct perf_kvm_stat *kvm __maybe_unused, struct event_key *key, char *decode) { - scnprintf(decode, decode_str_len, "%#llx:%s", + scnprintf(decode, KVM_EVENT_NAME_LEN, "%#llx:%s", (unsigned long long)key->key, key->info ? "POUT" : "PIN"); } @@ -165,7 +164,7 @@ static void msr_event_decode_key(struct perf_kvm_stat *kvm __maybe_unused, struct event_key *key, char *decode) { - scnprintf(decode, decode_str_len, "%#llx:%s", + scnprintf(decode, KVM_EVENT_NAME_LEN, "%#llx:%s", (unsigned long long)key->key, key->info ? "W" : "R"); } diff --git a/tools/perf/builtin-kvm.c b/tools/perf/builtin-kvm.c index fbdd46d38c13..286faf6774ff 100644 --- a/tools/perf/builtin-kvm.c +++ b/tools/perf/builtin-kvm.c @@ -161,7 +161,7 @@ void exit_event_decode_key(struct perf_kvm_stat *kvm, const char *exit_reason = get_exit_reason(kvm, key->exit_reasons, key->key); - scnprintf(decode, decode_str_len, "%s", exit_reason); + scnprintf(decode, KVM_EVENT_NAME_LEN, "%s", exit_reason); } static bool register_kvm_events_ops(struct perf_kvm_stat *kvm) @@ -434,7 +434,7 @@ static bool handle_end_event(struct perf_kvm_stat *kvm, time_diff = sample->time - time_begin; if (kvm->duration && time_diff > kvm->duration) { - char decode[decode_str_len]; + char decode[KVM_EVENT_NAME_LEN]; kvm->events_ops->decode_key(kvm, &event->key, decode); if (!skip_event(decode)) { @@ -605,7 +605,7 @@ static void show_timeofday(void) static void print_result(struct perf_kvm_stat *kvm) { - char decode[decode_str_len]; + char decode[KVM_EVENT_NAME_LEN]; struct kvm_event *event; int vcpu = kvm->trace_vcpu; @@ -616,7 +616,7 @@ static void print_result(struct perf_kvm_stat *kvm) pr_info("\n\n"); print_vcpu_info(kvm); - pr_info("%*s ", decode_str_len, kvm->events_ops->name); + pr_info("%*s ", KVM_EVENT_NAME_LEN, kvm->events_ops->name); pr_info("%10s ", "Samples"); pr_info("%9s ", "Samples%"); @@ -635,7 +635,7 @@ static void print_result(struct perf_kvm_stat *kvm) min = get_event_min(event, vcpu); kvm->events_ops->decode_key(kvm, &event->key, decode); - pr_info("%*s ", decode_str_len, decode); + pr_info("%*s ", KVM_EVENT_NAME_LEN, decode); pr_info("%10llu ", (unsigned long long)ecount); pr_info("%8.2f%% ", (double)ecount / kvm->total_count * 100); pr_info("%8.2f%% ", (double)etime / kvm->total_time * 100); diff --git a/tools/perf/util/kvm-stat.h b/tools/perf/util/kvm-stat.h index 0c2400d9b227..841b3174c211 100644 --- a/tools/perf/util/kvm-stat.h +++ b/tools/perf/util/kvm-stat.h @@ -8,6 +8,8 @@ #include "stat.h" #include "record.h" +#define KVM_EVENT_NAME_LEN 40 + struct evsel; struct evlist; struct perf_session; @@ -143,7 +145,6 @@ extern const char *kvm_events_tp[]; extern struct kvm_reg_events_ops kvm_reg_events_ops[]; extern const char * const kvm_skip_events[]; extern const char *vcpu_id_str; -extern const int decode_str_len; extern const char *kvm_exit_reason; extern const char *kvm_entry_trace; extern const char *kvm_exit_trace; -- cgit v1.2.3-58-ga151 From 2d08124b08631322303e365d422ead50ae1674b8 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Wed, 15 Mar 2023 22:51:02 +0800 Subject: perf kvm: Introduce histograms data structures This is a preparation to support histograms in perf kvm tool. As first step, this patch defines histograms data structures and initialize them. Committer notes: Those are only used by functions enclosed in: #if efined(HAVE_KVM_STAT_SUPPORT) && defined(HAVE_LIBTRACEEVENT) So do this for these new functions and struct as well. Reviewed-by: James Clark Signed-off-by: Leo Yan Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: John Garry Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230315145112.186603-2-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-kvm.c | 18 ++++++++++++++++++ tools/perf/util/kvm-stat.h | 1 + 2 files changed, 19 insertions(+) (limited to 'tools') diff --git a/tools/perf/builtin-kvm.c b/tools/perf/builtin-kvm.c index 286faf6774ff..b06c11d306a1 100644 --- a/tools/perf/builtin-kvm.c +++ b/tools/perf/builtin-kvm.c @@ -85,6 +85,20 @@ static struct kvm_event_key keys[] = { DEF_SORT_NAME_KEY(time, mean), { NULL, NULL } }; + +struct kvm_hists { + struct hists hists; + struct perf_hpp_list list; +}; + +static struct kvm_hists kvm_hists; + +static int kvm_hists__init(void) +{ + __hists__init(&kvm_hists.hists, &kvm_hists.list); + perf_hpp_list__init(&kvm_hists.list); + return 0; +} #endif // defined(HAVE_KVM_STAT_SUPPORT) && defined(HAVE_LIBTRACEEVENT) static const char *get_filename_for_perf_kvm(void) @@ -959,6 +973,8 @@ static int kvm_events_live_report(struct perf_kvm_stat *kvm) set_term_quiet_input(&save); init_kvm_event_record(kvm); + kvm_hists__init(); + signal(SIGINT, sig_handler); signal(SIGTERM, sig_handler); @@ -1154,6 +1170,8 @@ static int kvm_events_report_vcpu(struct perf_kvm_stat *kvm) init_kvm_event_record(kvm); setup_pager(); + kvm_hists__init(); + ret = read_events(kvm); if (ret) goto exit; diff --git a/tools/perf/util/kvm-stat.h b/tools/perf/util/kvm-stat.h index 841b3174c211..e2c17662bac7 100644 --- a/tools/perf/util/kvm-stat.h +++ b/tools/perf/util/kvm-stat.h @@ -5,6 +5,7 @@ #ifdef HAVE_KVM_STAT_SUPPORT #include "tool.h" +#include "sort.h" #include "stat.h" #include "record.h" -- cgit v1.2.3-58-ga151 From 730651f7177f473345ab470db212c7b5a18466f0 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Wed, 15 Mar 2023 22:51:03 +0800 Subject: perf kvm: Pass argument 'sample' to kvm_alloc_init_event() This patch adds an argument 'sample' for kvm_alloc_init_event(), and its caller functions are updated as well for passing down the 'sample' pointer. This is a preparation change to allow later patch to create histograms entries for kvm event, no any functionality changes. Reviewed-by: James Clark Signed-off-by: Leo Yan Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: John Garry Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230315145112.186603-2-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-kvm.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-kvm.c b/tools/perf/builtin-kvm.c index b06c11d306a1..ef502c19bc40 100644 --- a/tools/perf/builtin-kvm.c +++ b/tools/perf/builtin-kvm.c @@ -262,7 +262,8 @@ static bool kvm_event_expand(struct kvm_event *event, int vcpu_id) } static struct kvm_event *kvm_alloc_init_event(struct perf_kvm_stat *kvm, - struct event_key *key) + struct event_key *key, + struct perf_sample *sample __maybe_unused) { struct kvm_event *event; @@ -279,7 +280,8 @@ static struct kvm_event *kvm_alloc_init_event(struct perf_kvm_stat *kvm, } static struct kvm_event *find_create_kvm_event(struct perf_kvm_stat *kvm, - struct event_key *key) + struct event_key *key, + struct perf_sample *sample) { struct kvm_event *event; struct list_head *head; @@ -292,7 +294,7 @@ static struct kvm_event *find_create_kvm_event(struct perf_kvm_stat *kvm, return event; } - event = kvm_alloc_init_event(kvm, key); + event = kvm_alloc_init_event(kvm, key, sample); if (!event) return NULL; @@ -302,15 +304,16 @@ static struct kvm_event *find_create_kvm_event(struct perf_kvm_stat *kvm, static bool handle_begin_event(struct perf_kvm_stat *kvm, struct vcpu_event_record *vcpu_record, - struct event_key *key, u64 timestamp) + struct event_key *key, + struct perf_sample *sample) { struct kvm_event *event = NULL; if (key->key != INVALID_KEY) - event = find_create_kvm_event(kvm, key); + event = find_create_kvm_event(kvm, key, sample); vcpu_record->last_event = event; - vcpu_record->start_time = timestamp; + vcpu_record->start_time = sample->time; return true; } @@ -377,12 +380,12 @@ static bool is_child_event(struct perf_kvm_stat *kvm, static bool handle_child_event(struct perf_kvm_stat *kvm, struct vcpu_event_record *vcpu_record, struct event_key *key, - struct perf_sample *sample __maybe_unused) + struct perf_sample *sample) { struct kvm_event *event = NULL; if (key->key != INVALID_KEY) - event = find_create_kvm_event(kvm, key); + event = find_create_kvm_event(kvm, key, sample); vcpu_record->last_event = event; @@ -431,7 +434,7 @@ static bool handle_end_event(struct perf_kvm_stat *kvm, return true; if (!event) - event = find_create_kvm_event(kvm, key); + event = find_create_kvm_event(kvm, key, sample); if (!event) return false; @@ -502,7 +505,7 @@ static bool handle_kvm_event(struct perf_kvm_stat *kvm, return true; if (kvm->events_ops->is_begin_event(evsel, sample, &key)) - return handle_begin_event(kvm, vcpu_record, &key, sample->time); + return handle_begin_event(kvm, vcpu_record, &key, sample); if (is_child_event(kvm, evsel, sample, &key)) return handle_child_event(kvm, vcpu_record, &key, sample); -- cgit v1.2.3-58-ga151 From 001b08f4e2aab9748b5d5e49b68d5444715ffda9 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Wed, 15 Mar 2023 22:51:04 +0800 Subject: perf kvm: Parse address location for samples Parse address location for samples and save it into the structure 'perf_kvm_stat', it is to be used by histograms entry. Reviewed-by: James Clark Signed-off-by: Leo Yan Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: John Garry Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230315145112.186603-2-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-kvm.c | 5 +++++ tools/perf/util/kvm-stat.h | 4 ++++ 2 files changed, 9 insertions(+) (limited to 'tools') diff --git a/tools/perf/builtin-kvm.c b/tools/perf/builtin-kvm.c index ef502c19bc40..17a8219a702a 100644 --- a/tools/perf/builtin-kvm.c +++ b/tools/perf/builtin-kvm.c @@ -706,6 +706,11 @@ static int process_sample_event(struct perf_tool *tool, if (skip_sample(kvm, sample)) return 0; + if (machine__resolve(machine, &kvm->al, sample) < 0) { + pr_warning("Fail to resolve address location, skip sample.\n"); + return 0; + } + thread = machine__findnew_thread(machine, sample->pid, sample->tid); if (thread == NULL) { pr_debug("problem processing %d event, skipping it.\n", diff --git a/tools/perf/util/kvm-stat.h b/tools/perf/util/kvm-stat.h index e2c17662bac7..3b2eab91a9be 100644 --- a/tools/perf/util/kvm-stat.h +++ b/tools/perf/util/kvm-stat.h @@ -7,6 +7,7 @@ #include "tool.h" #include "sort.h" #include "stat.h" +#include "symbol.h" #include "record.h" #define KVM_EVENT_NAME_LEN 40 @@ -88,6 +89,9 @@ struct perf_kvm_stat { const char *sort_key; int trace_vcpu; + /* Used when process events */ + struct addr_location al; + struct exit_reasons_table *exit_reasons; const char *exit_reasons_isa; -- cgit v1.2.3-58-ga151 From ebf39d29b985b0c0f75c2e752781a9a80daadc0e Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Wed, 15 Mar 2023 22:51:05 +0800 Subject: perf hist: Add 'kvm_info' field in histograms entry __hists__add_entry() creates a temporary entry and compare it with existed histograms entries, if any existed entry equals to the temporary entry it skips to allocation to avoid duplication. The problem for support KVM event in histograms is it doesn't contain any info to identify KVM event and can be used for comparison entries. This patch adds 'kvm_info' field in the histograms entry which contains the KVM event's key, this identifier will be used for comparison histograms entries in later change. Signed-off-by: Leo Yan Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230315145112.186603-2-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-annotate.c | 2 +- tools/perf/builtin-c2c.c | 4 ++-- tools/perf/builtin-diff.c | 4 ++-- tools/perf/tests/hists_link.c | 4 ++-- tools/perf/util/hist.c | 19 ++++++++++++------- tools/perf/util/hist.h | 3 +++ tools/perf/util/kvm-stat.h | 4 ++++ tools/perf/util/sort.h | 1 + 8 files changed, 27 insertions(+), 14 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-annotate.c b/tools/perf/builtin-annotate.c index 90458ca6933f..4750fac7bf93 100644 --- a/tools/perf/builtin-annotate.c +++ b/tools/perf/builtin-annotate.c @@ -252,7 +252,7 @@ static int evsel__add_sample(struct evsel *evsel, struct perf_sample *sample, if (ann->has_br_stack && has_annotation(ann)) return process_branch_callback(evsel, sample, al, ann, machine); - he = hists__add_entry(hists, al, NULL, NULL, NULL, sample, true); + he = hists__add_entry(hists, al, NULL, NULL, NULL, NULL, sample, true); if (he == NULL) return -ENOMEM; diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c index 56974eae0638..d3181fee4d3d 100644 --- a/tools/perf/builtin-c2c.c +++ b/tools/perf/builtin-c2c.c @@ -315,7 +315,7 @@ static int process_sample_event(struct perf_tool *tool __maybe_unused, c2c_decode_stats(&stats, mi); he = hists__add_entry_ops(&c2c_hists->hists, &c2c_entry_ops, - &al, NULL, NULL, mi, + &al, NULL, NULL, mi, NULL, sample, true); if (he == NULL) goto free_mi; @@ -349,7 +349,7 @@ static int process_sample_event(struct perf_tool *tool __maybe_unused, goto free_mi; he = hists__add_entry_ops(&c2c_hists->hists, &c2c_entry_ops, - &al, NULL, NULL, mi, + &al, NULL, NULL, mi, NULL, sample, true); if (he == NULL) goto free_mi; diff --git a/tools/perf/builtin-diff.c b/tools/perf/builtin-diff.c index ed07cc6cca56..22b526766e14 100644 --- a/tools/perf/builtin-diff.c +++ b/tools/perf/builtin-diff.c @@ -423,7 +423,7 @@ static int diff__process_sample_event(struct perf_tool *tool, switch (compute) { case COMPUTE_CYCLES: if (!hists__add_entry_ops(hists, &block_hist_ops, &al, NULL, - NULL, NULL, sample, true)) { + NULL, NULL, NULL, sample, true)) { pr_warning("problem incrementing symbol period, " "skipping event\n"); goto out_put; @@ -442,7 +442,7 @@ static int diff__process_sample_event(struct perf_tool *tool, break; default: - if (!hists__add_entry(hists, &al, NULL, NULL, NULL, sample, + if (!hists__add_entry(hists, &al, NULL, NULL, NULL, NULL, sample, true)) { pr_warning("problem incrementing symbol period, " "skipping event\n"); diff --git a/tools/perf/tests/hists_link.c b/tools/perf/tests/hists_link.c index 14b2ff808b5e..e7e4ee57ce04 100644 --- a/tools/perf/tests/hists_link.c +++ b/tools/perf/tests/hists_link.c @@ -87,7 +87,7 @@ static int add_hist_entries(struct evlist *evlist, struct machine *machine) goto out; he = hists__add_entry(hists, &al, NULL, - NULL, NULL, &sample, true); + NULL, NULL, NULL, &sample, true); if (he == NULL) { addr_location__put(&al); goto out; @@ -106,7 +106,7 @@ static int add_hist_entries(struct evlist *evlist, struct machine *machine) goto out; he = hists__add_entry(hists, &al, NULL, - NULL, NULL, &sample, true); + NULL, NULL, NULL, &sample, true); if (he == NULL) { addr_location__put(&al); goto out; diff --git a/tools/perf/util/hist.c b/tools/perf/util/hist.c index b6e4b4edde43..3670136a0074 100644 --- a/tools/perf/util/hist.c +++ b/tools/perf/util/hist.c @@ -4,6 +4,7 @@ #include "dso.h" #include "build-id.h" #include "hist.h" +#include "kvm-stat.h" #include "map.h" #include "map_symbol.h" #include "branch.h" @@ -698,6 +699,7 @@ __hists__add_entry(struct hists *hists, struct symbol *sym_parent, struct branch_info *bi, struct mem_info *mi, + struct kvm_info *ki, struct block_info *block_info, struct perf_sample *sample, bool sample_self, @@ -733,6 +735,7 @@ __hists__add_entry(struct hists *hists, .hists = hists, .branch_info = bi, .mem_info = mi, + .kvm_info = ki, .block_info = block_info, .transaction = sample->transaction, .raw_data = sample->raw_data, @@ -756,10 +759,11 @@ struct hist_entry *hists__add_entry(struct hists *hists, struct symbol *sym_parent, struct branch_info *bi, struct mem_info *mi, + struct kvm_info *ki, struct perf_sample *sample, bool sample_self) { - return __hists__add_entry(hists, al, sym_parent, bi, mi, NULL, + return __hists__add_entry(hists, al, sym_parent, bi, mi, ki, NULL, sample, sample_self, NULL); } @@ -769,10 +773,11 @@ struct hist_entry *hists__add_entry_ops(struct hists *hists, struct symbol *sym_parent, struct branch_info *bi, struct mem_info *mi, + struct kvm_info *ki, struct perf_sample *sample, bool sample_self) { - return __hists__add_entry(hists, al, sym_parent, bi, mi, NULL, + return __hists__add_entry(hists, al, sym_parent, bi, mi, ki, NULL, sample, sample_self, ops); } @@ -846,7 +851,7 @@ iter_add_single_mem_entry(struct hist_entry_iter *iter, struct addr_location *al */ sample->period = cost; - he = hists__add_entry(hists, al, iter->parent, NULL, mi, + he = hists__add_entry(hists, al, iter->parent, NULL, mi, NULL, sample, true); if (!he) return -ENOMEM; @@ -949,7 +954,7 @@ iter_add_next_branch_entry(struct hist_entry_iter *iter, struct addr_location *a sample->period = 1; sample->weight = bi->flags.cycles ? bi->flags.cycles : 1; - he = hists__add_entry(hists, al, iter->parent, &bi[i], NULL, + he = hists__add_entry(hists, al, iter->parent, &bi[i], NULL, NULL, sample, true); if (he == NULL) return -ENOMEM; @@ -987,7 +992,7 @@ iter_add_single_normal_entry(struct hist_entry_iter *iter, struct addr_location struct hist_entry *he; he = hists__add_entry(evsel__hists(evsel), al, iter->parent, NULL, NULL, - sample, true); + NULL, sample, true); if (he == NULL) return -ENOMEM; @@ -1047,7 +1052,7 @@ iter_add_single_cumulative_entry(struct hist_entry_iter *iter, struct hist_entry *he; int err = 0; - he = hists__add_entry(hists, al, iter->parent, NULL, NULL, + he = hists__add_entry(hists, al, iter->parent, NULL, NULL, NULL, sample, true); if (he == NULL) return -ENOMEM; @@ -1148,7 +1153,7 @@ iter_add_next_cumulative_entry(struct hist_entry_iter *iter, } he = hists__add_entry(evsel__hists(evsel), al, iter->parent, NULL, NULL, - sample, false); + NULL, sample, false); if (he == NULL) return -ENOMEM; diff --git a/tools/perf/util/hist.h b/tools/perf/util/hist.h index d93a4e510dc7..86a677954279 100644 --- a/tools/perf/util/hist.h +++ b/tools/perf/util/hist.h @@ -14,6 +14,7 @@ struct hist_entry_ops; struct addr_location; struct map_symbol; struct mem_info; +struct kvm_info; struct branch_info; struct branch_stack; struct block_info; @@ -150,6 +151,7 @@ struct hist_entry *hists__add_entry(struct hists *hists, struct symbol *parent, struct branch_info *bi, struct mem_info *mi, + struct kvm_info *ki, struct perf_sample *sample, bool sample_self); @@ -159,6 +161,7 @@ struct hist_entry *hists__add_entry_ops(struct hists *hists, struct symbol *sym_parent, struct branch_info *bi, struct mem_info *mi, + struct kvm_info *ki, struct perf_sample *sample, bool sample_self); diff --git a/tools/perf/util/kvm-stat.h b/tools/perf/util/kvm-stat.h index 3b2eab91a9be..0cf704333c4c 100644 --- a/tools/perf/util/kvm-stat.h +++ b/tools/perf/util/kvm-stat.h @@ -23,6 +23,10 @@ struct event_key { struct exit_reasons_table *exit_reasons; }; +struct kvm_info { + char name[KVM_EVENT_NAME_LEN]; +}; + struct kvm_event_stats { u64 time; struct stats stats; diff --git a/tools/perf/util/sort.h b/tools/perf/util/sort.h index d79a100e5999..22f437c3476f 100644 --- a/tools/perf/util/sort.h +++ b/tools/perf/util/sort.h @@ -144,6 +144,7 @@ struct hist_entry { struct hists *hists; struct mem_info *mem_info; struct block_info *block_info; + struct kvm_info *kvm_info; void *raw_data; u32 raw_size; int num_res; -- cgit v1.2.3-58-ga151 From 41f1138e5c1cf11c5b469c3f891960b4ad05e886 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Wed, 15 Mar 2023 22:51:06 +0800 Subject: perf kvm: Add dimensions for KVM event statistics To support KVM event statistics, this patch firstly registers histograms columns and sorting fields; every column or field has its own format structure, the format structure is dereferenced to access the dimension, finally the dimension provides the comparison callback for sorting result. Signed-off-by: Leo Yan Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230315145112.186603-2-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-kvm.c | 232 ++++++++++++++++++++++++++++++++++++++++++++- tools/perf/util/kvm-stat.h | 2 + 2 files changed, 230 insertions(+), 4 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-kvm.c b/tools/perf/builtin-kvm.c index 17a8219a702a..899e331cf727 100644 --- a/tools/perf/builtin-kvm.c +++ b/tools/perf/builtin-kvm.c @@ -71,9 +71,9 @@ static int64_t cmp_event_ ## func(struct kvm_event *one, \ get_event_ ##func(two, vcpu); \ } -GET_EVENT_KEY(time, time); -GET_EVENT_KEY(max, stats.max); -GET_EVENT_KEY(min, stats.min); +COMPARE_EVENT_KEY(time, time); +COMPARE_EVENT_KEY(max, stats.max); +COMPARE_EVENT_KEY(min, stats.min); COMPARE_EVENT_KEY(count, stats.n); COMPARE_EVENT_KEY(mean, stats.mean); @@ -91,13 +91,237 @@ struct kvm_hists { struct perf_hpp_list list; }; +struct kvm_dimension { + const char *name; + int64_t (*cmp)(struct perf_hpp_fmt *fmt, struct hist_entry *left, + struct hist_entry *right); +}; + +struct kvm_fmt { + struct perf_hpp_fmt fmt; + struct kvm_dimension *dim; +}; + static struct kvm_hists kvm_hists; +static int64_t ev_name_cmp(struct perf_hpp_fmt *fmt __maybe_unused, + struct hist_entry *left, + struct hist_entry *right) +{ + /* Return opposite number for sorting in alphabetical order */ + return -strcmp(left->kvm_info->name, right->kvm_info->name); +} + +static struct kvm_dimension dim_event = { + .name = "ev_name", + .cmp = ev_name_cmp, +}; + +#define EV_METRIC_CMP(metric) \ +static int64_t ev_cmp_##metric(struct perf_hpp_fmt *fmt __maybe_unused, \ + struct hist_entry *left, \ + struct hist_entry *right) \ +{ \ + struct kvm_event *event_left; \ + struct kvm_event *event_right; \ + struct perf_kvm_stat *perf_kvm; \ + \ + event_left = container_of(left, struct kvm_event, he); \ + event_right = container_of(right, struct kvm_event, he); \ + \ + perf_kvm = event_left->perf_kvm; \ + return cmp_event_##metric(event_left, event_right, \ + perf_kvm->trace_vcpu); \ +} + +EV_METRIC_CMP(time) +EV_METRIC_CMP(count) +EV_METRIC_CMP(max) +EV_METRIC_CMP(min) +EV_METRIC_CMP(mean) + +static struct kvm_dimension dim_time = { + .name = "time", + .cmp = ev_cmp_time, +}; + +static struct kvm_dimension dim_count = { + .name = "sample", + .cmp = ev_cmp_count, +}; + +static struct kvm_dimension dim_max_time = { + .name = "max_t", + .cmp = ev_cmp_max, +}; + +static struct kvm_dimension dim_min_time = { + .name = "min_t", + .cmp = ev_cmp_min, +}; + +static struct kvm_dimension dim_mean_time = { + .name = "mean_t", + .cmp = ev_cmp_mean, +}; + +static struct kvm_dimension *dimensions[] = { + &dim_event, + &dim_time, + &dim_count, + &dim_max_time, + &dim_min_time, + &dim_mean_time, + NULL, +}; + +static bool fmt_equal(struct perf_hpp_fmt *a, struct perf_hpp_fmt *b) +{ + struct kvm_fmt *kvm_fmt_a = container_of(a, struct kvm_fmt, fmt); + struct kvm_fmt *kvm_fmt_b = container_of(b, struct kvm_fmt, fmt); + + return kvm_fmt_a->dim == kvm_fmt_b->dim; +} + +static void fmt_free(struct perf_hpp_fmt *fmt) +{ + struct kvm_fmt *kvm_fmt; + + kvm_fmt = container_of(fmt, struct kvm_fmt, fmt); + free(kvm_fmt); +} + +static struct kvm_dimension *get_dimension(const char *name) +{ + unsigned int i; + + for (i = 0; dimensions[i] != NULL; i++) { + if (!strcmp(dimensions[i]->name, name)) + return dimensions[i]; + } + + return NULL; +} + +static struct kvm_fmt *get_format(const char *name) +{ + struct kvm_dimension *dim = get_dimension(name); + struct kvm_fmt *kvm_fmt; + struct perf_hpp_fmt *fmt; + + if (!dim) + return NULL; + + kvm_fmt = zalloc(sizeof(*kvm_fmt)); + if (!kvm_fmt) + return NULL; + + kvm_fmt->dim = dim; + + fmt = &kvm_fmt->fmt; + INIT_LIST_HEAD(&fmt->list); + INIT_LIST_HEAD(&fmt->sort_list); + fmt->cmp = dim->cmp; + fmt->sort = dim->cmp; + fmt->color = NULL; + fmt->entry = NULL; + fmt->header = NULL; + fmt->width = NULL; + fmt->collapse = dim->cmp; + fmt->equal = fmt_equal; + fmt->free = fmt_free; + + return kvm_fmt; +} + +static int kvm_hists__init_output(struct perf_hpp_list *hpp_list, char *name) +{ + struct kvm_fmt *kvm_fmt = get_format(name); + + if (!kvm_fmt) { + pr_warning("Fail to find format for output field %s.\n", name); + return -EINVAL; + } + + perf_hpp_list__column_register(hpp_list, &kvm_fmt->fmt); + return 0; +} + +static int kvm_hists__init_sort(struct perf_hpp_list *hpp_list, char *name) +{ + struct kvm_fmt *kvm_fmt = get_format(name); + + if (!kvm_fmt) { + pr_warning("Fail to find format for sorting %s.\n", name); + return -EINVAL; + } + + perf_hpp_list__register_sort_field(hpp_list, &kvm_fmt->fmt); + return 0; +} + +static int kvm_hpp_list__init(char *list, + struct perf_hpp_list *hpp_list, + int (*fn)(struct perf_hpp_list *hpp_list, + char *name)) +{ + char *tmp, *tok; + int ret; + + if (!list || !fn) + return 0; + + for (tok = strtok_r(list, ", ", &tmp); tok; + tok = strtok_r(NULL, ", ", &tmp)) { + ret = fn(hpp_list, tok); + if (!ret) + continue; + + /* Handle errors */ + if (ret == -EINVAL) + pr_err("Invalid field key: '%s'", tok); + else if (ret == -ESRCH) + pr_err("Unknown field key: '%s'", tok); + else + pr_err("Fail to initialize for field key: '%s'", tok); + + break; + } + + return ret; +} + +static int kvm_hpp_list__parse(struct perf_hpp_list *hpp_list, + const char *output_, const char *sort_) +{ + char *output = output_ ? strdup(output_) : NULL; + char *sort = sort_ ? strdup(sort_) : NULL; + int ret; + + ret = kvm_hpp_list__init(output, hpp_list, kvm_hists__init_output); + if (ret) + goto out; + + ret = kvm_hpp_list__init(sort, hpp_list, kvm_hists__init_sort); + if (ret) + goto out; + + /* Copy sort keys to output fields */ + perf_hpp__setup_output_field(hpp_list); + + /* and then copy output fields to sort keys */ + perf_hpp__append_sort_keys(hpp_list); +out: + free(output); + free(sort); + return ret; +} + static int kvm_hists__init(void) { __hists__init(&kvm_hists.hists, &kvm_hists.list); perf_hpp_list__init(&kvm_hists.list); - return 0; + return kvm_hpp_list__parse(&kvm_hists.list, NULL, "ev_name"); } #endif // defined(HAVE_KVM_STAT_SUPPORT) && defined(HAVE_LIBTRACEEVENT) diff --git a/tools/perf/util/kvm-stat.h b/tools/perf/util/kvm-stat.h index 0cf704333c4c..fc30a72dfac1 100644 --- a/tools/perf/util/kvm-stat.h +++ b/tools/perf/util/kvm-stat.h @@ -46,6 +46,8 @@ struct kvm_event { #define DEFAULT_VCPU_NUM 8 int max_vcpu; struct kvm_event_stats *vcpu; + + struct hist_entry he; }; typedef int64_t (*key_cmp_fun)(struct kvm_event*, struct kvm_event*, int); -- cgit v1.2.3-58-ga151 From f57a64142c04b6cbbfb2ce6493f0aefc237c3106 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Wed, 15 Mar 2023 22:51:07 +0800 Subject: perf kvm: Use histograms list to replace cached list perf kvm tool defines its own cached list which is managed with RB tree, histograms also provide RB tree to manage data entries. Since now we have introduced histograms in the tool, it's not necessary to use the self defined list and we can directly use histograms list to manage KVM events. This patch changes to use histograms list to track KVM events, and it invokes the common function hists__output_resort_cb() to sort result, this also give us flexibility to extend more sorting key words easily. After histograms list supported, the cached list is redundant so remove the relevant code for it. Committer notes: kvm_hists__reinit() is only used by functions enclosed in: #if defined(HAVE_KVM_STAT_SUPPORT) && defined(HAVE_LIBTRACEEVENT) So do it with this new function as well. Signed-off-by: Leo Yan Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230315145112.186603-2-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-kvm.c | 189 +++++++++++++++++++++++---------------------- tools/perf/util/kvm-stat.h | 7 -- 2 files changed, 95 insertions(+), 101 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-kvm.c b/tools/perf/builtin-kvm.c index 899e331cf727..ae1c8c21cd1d 100644 --- a/tools/perf/builtin-kvm.c +++ b/tools/perf/builtin-kvm.c @@ -323,6 +323,12 @@ static int kvm_hists__init(void) perf_hpp_list__init(&kvm_hists.list); return kvm_hpp_list__parse(&kvm_hists.list, NULL, "ev_name"); } + +static int kvm_hists__reinit(const char *output, const char *sort) +{ + perf_hpp__reset_output_field(&kvm_hists.list); + return kvm_hpp_list__parse(&kvm_hists.list, output, sort); +} #endif // defined(HAVE_KVM_STAT_SUPPORT) && defined(HAVE_LIBTRACEEVENT) static const char *get_filename_for_perf_kvm(void) @@ -422,44 +428,37 @@ struct vcpu_event_record { struct kvm_event *last_event; }; - -static void init_kvm_event_record(struct perf_kvm_stat *kvm) -{ - unsigned int i; - - for (i = 0; i < EVENTS_CACHE_SIZE; i++) - INIT_LIST_HEAD(&kvm->kvm_events_cache[i]); -} - #ifdef HAVE_TIMERFD_SUPPORT -static void clear_events_cache_stats(struct list_head *kvm_events_cache) +static void clear_events_cache_stats(void) { - struct list_head *head; + struct rb_root_cached *root; + struct rb_node *nd; struct kvm_event *event; - unsigned int i; - int j; - - for (i = 0; i < EVENTS_CACHE_SIZE; i++) { - head = &kvm_events_cache[i]; - list_for_each_entry(event, head, hash_entry) { - /* reset stats for event */ - event->total.time = 0; - init_stats(&event->total.stats); - - for (j = 0; j < event->max_vcpu; ++j) { - event->vcpu[j].time = 0; - init_stats(&event->vcpu[j].stats); - } + int i; + + if (hists__has(&kvm_hists.hists, need_collapse)) + root = &kvm_hists.hists.entries_collapsed; + else + root = kvm_hists.hists.entries_in; + + for (nd = rb_first_cached(root); nd; nd = rb_next(nd)) { + struct hist_entry *he; + + he = rb_entry(nd, struct hist_entry, rb_node_in); + event = container_of(he, struct kvm_event, he); + + /* reset stats for event */ + event->total.time = 0; + init_stats(&event->total.stats); + + for (i = 0; i < event->max_vcpu; ++i) { + event->vcpu[i].time = 0; + init_stats(&event->vcpu[i].stats); } } } #endif -static int kvm_events_hash_fn(u64 key) -{ - return key & (EVENTS_CACHE_SIZE - 1); -} - static bool kvm_event_expand(struct kvm_event *event, int vcpu_id) { int old_max_vcpu = event->max_vcpu; @@ -485,44 +484,64 @@ static bool kvm_event_expand(struct kvm_event *event, int vcpu_id) return true; } -static struct kvm_event *kvm_alloc_init_event(struct perf_kvm_stat *kvm, - struct event_key *key, - struct perf_sample *sample __maybe_unused) +static void *kvm_he_zalloc(size_t size) { - struct kvm_event *event; + struct kvm_event *kvm_ev; - event = zalloc(sizeof(*event)); - if (!event) { - pr_err("Not enough memory\n"); + kvm_ev = zalloc(size + sizeof(*kvm_ev)); + if (!kvm_ev) return NULL; - } - event->perf_kvm = kvm; - event->key = *key; - init_stats(&event->total.stats); - return event; + init_stats(&kvm_ev->total.stats); + hists__inc_nr_samples(&kvm_hists.hists, 0); + return &kvm_ev->he; +} + +static void kvm_he_free(void *he) +{ + struct kvm_event *kvm_ev; + + free(((struct hist_entry *)he)->kvm_info); + kvm_ev = container_of(he, struct kvm_event, he); + free(kvm_ev); } +static struct hist_entry_ops kvm_ev_entry_ops = { + .new = kvm_he_zalloc, + .free = kvm_he_free, +}; + static struct kvm_event *find_create_kvm_event(struct perf_kvm_stat *kvm, struct event_key *key, struct perf_sample *sample) { struct kvm_event *event; - struct list_head *head; + struct hist_entry *he; + struct kvm_info *ki; BUG_ON(key->key == INVALID_KEY); - head = &kvm->kvm_events_cache[kvm_events_hash_fn(key->key)]; - list_for_each_entry(event, head, hash_entry) { - if (event->key.key == key->key && event->key.info == key->info) - return event; + ki = zalloc(sizeof(*ki)); + if (!ki) { + pr_err("Failed to allocate kvm info\n"); + return NULL; } - event = kvm_alloc_init_event(kvm, key, sample); - if (!event) + kvm->events_ops->decode_key(kvm, key, ki->name); + he = hists__add_entry_ops(&kvm_hists.hists, &kvm_ev_entry_ops, + &kvm->al, NULL, NULL, NULL, ki, sample, true); + if (he == NULL) { + pr_err("Failed to allocate hist entry\n"); + free(ki); return NULL; + } + + event = container_of(he, struct kvm_event, he); + if (!event->perf_kvm) { + event->perf_kvm = kvm; + event->key = *key; + } - list_add(&event->hash_entry, head); return event; } @@ -755,58 +774,32 @@ static bool select_key(struct perf_kvm_stat *kvm) return false; } -static void insert_to_result(struct rb_root *result, struct kvm_event *event, - key_cmp_fun bigger, int vcpu) -{ - struct rb_node **rb = &result->rb_node; - struct rb_node *parent = NULL; - struct kvm_event *p; - - while (*rb) { - p = container_of(*rb, struct kvm_event, rb); - parent = *rb; - - if (bigger(event, p, vcpu) > 0) - rb = &(*rb)->rb_left; - else - rb = &(*rb)->rb_right; - } - - rb_link_node(&event->rb, parent, rb); - rb_insert_color(&event->rb, result); -} - static bool event_is_valid(struct kvm_event *event, int vcpu) { return !!get_event_count(event, vcpu); } -static void sort_result(struct perf_kvm_stat *kvm) +static int filter_cb(struct hist_entry *he, void *arg __maybe_unused) { - unsigned int i; - int vcpu = kvm->trace_vcpu; struct kvm_event *event; + struct perf_kvm_stat *perf_kvm; - for (i = 0; i < EVENTS_CACHE_SIZE; i++) { - list_for_each_entry(event, &kvm->kvm_events_cache[i], hash_entry) { - if (event_is_valid(event, vcpu)) { - insert_to_result(&kvm->result, event, - kvm->compare, vcpu); - } - } - } + event = container_of(he, struct kvm_event, he); + perf_kvm = event->perf_kvm; + if (!event_is_valid(event, perf_kvm->trace_vcpu)) + he->filtered = 1; + else + he->filtered = 0; + return 0; } -/* returns left most element of result, and erase it */ -static struct kvm_event *pop_from_result(struct rb_root *result) +static void sort_result(struct perf_kvm_stat *kvm) { - struct rb_node *node = rb_first(result); - - if (!node) - return NULL; + const char *output_columns = "ev_name,sample,time,max_t,min_t,mean_t"; - rb_erase(node, result); - return container_of(node, struct kvm_event, rb); + kvm_hists__reinit(output_columns, kvm->sort_key); + hists__collapse_resort(&kvm_hists.hists, NULL); + hists__output_resort_cb(&kvm_hists.hists, NULL, filter_cb); } static void print_vcpu_info(struct perf_kvm_stat *kvm) @@ -849,6 +842,7 @@ static void print_result(struct perf_kvm_stat *kvm) char decode[KVM_EVENT_NAME_LEN]; struct kvm_event *event; int vcpu = kvm->trace_vcpu; + struct rb_node *nd; if (kvm->live) { puts(CONSOLE_CLEAR); @@ -867,9 +861,15 @@ static void print_result(struct perf_kvm_stat *kvm) pr_info("%16s ", "Avg time"); pr_info("\n\n"); - while ((event = pop_from_result(&kvm->result))) { + for (nd = rb_first_cached(&kvm_hists.hists.entries); nd; nd = rb_next(nd)) { + struct hist_entry *he; u64 ecount, etime, max, min; + he = rb_entry(nd, struct hist_entry, rb_node); + if (he->filtered) + continue; + + event = container_of(he, struct kvm_event, he); ecount = get_event_count(event, vcpu); etime = get_event_time(event, vcpu); max = get_event_max(event, vcpu); @@ -1146,8 +1146,11 @@ static int perf_kvm__handle_timerfd(struct perf_kvm_stat *kvm) sort_result(kvm); print_result(kvm); + /* Reset sort list to "ev_name" */ + kvm_hists__reinit(NULL, "ev_name"); + /* reset counts */ - clear_events_cache_stats(kvm->kvm_events_cache); + clear_events_cache_stats(); kvm->total_count = 0; kvm->total_time = 0; kvm->lost_events = 0; @@ -1203,7 +1206,6 @@ static int kvm_events_live_report(struct perf_kvm_stat *kvm) } set_term_quiet_input(&save); - init_kvm_event_record(kvm); kvm_hists__init(); @@ -1399,7 +1401,6 @@ static int kvm_events_report_vcpu(struct perf_kvm_stat *kvm) if (!register_kvm_events_ops(kvm)) goto exit; - init_kvm_event_record(kvm); setup_pager(); kvm_hists__init(); diff --git a/tools/perf/util/kvm-stat.h b/tools/perf/util/kvm-stat.h index fc30a72dfac1..3f0cbecb862c 100644 --- a/tools/perf/util/kvm-stat.h +++ b/tools/perf/util/kvm-stat.h @@ -36,7 +36,6 @@ struct perf_kvm_stat; struct kvm_event { struct list_head hash_entry; - struct rb_node rb; struct perf_kvm_stat *perf_kvm; struct event_key key; @@ -81,9 +80,6 @@ struct exit_reasons_table { const char *reason; }; -#define EVENTS_BITS 12 -#define EVENTS_CACHE_SIZE (1UL << EVENTS_BITS) - struct perf_kvm_stat { struct perf_tool tool; struct record_opts opts; @@ -103,7 +99,6 @@ struct perf_kvm_stat { struct kvm_events_ops *events_ops; key_cmp_fun compare; - struct list_head kvm_events_cache[EVENTS_CACHE_SIZE]; u64 total_time; u64 total_count; @@ -112,8 +107,6 @@ struct perf_kvm_stat { struct intlist *pid_list; - struct rb_root result; - int timerfd; unsigned int display_time; bool live; -- cgit v1.2.3-58-ga151 From c695d48a33e7185cf5c7a7e44a6e8fe640ea1a71 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Wed, 15 Mar 2023 22:51:08 +0800 Subject: perf kvm: Polish sorting key Since histograms supports sorting, the tool doesn't need to maintain the mapping between the sorting keys and the corresponding comparison callbacks, therefore, this patch removes structure kvm_event_key. But we still need to validate the sorting key, this patch uses an array for sorting keys and renames function select_key() to is_valid_key() to validate the sorting key passed by user. Signed-off-by: Leo Yan Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230315145112.186603-2-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-kvm.c | 29 ++++++++++------------------- tools/perf/util/kvm-stat.h | 8 -------- 2 files changed, 10 insertions(+), 27 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-kvm.c b/tools/perf/builtin-kvm.c index ae1c8c21cd1d..d102d3a146f9 100644 --- a/tools/perf/builtin-kvm.c +++ b/tools/perf/builtin-kvm.c @@ -77,15 +77,6 @@ COMPARE_EVENT_KEY(min, stats.min); COMPARE_EVENT_KEY(count, stats.n); COMPARE_EVENT_KEY(mean, stats.mean); -#define DEF_SORT_NAME_KEY(name, compare_key) \ - { #name, cmp_event_ ## compare_key } - -static struct kvm_event_key keys[] = { - DEF_SORT_NAME_KEY(sample, count), - DEF_SORT_NAME_KEY(time, mean), - { NULL, NULL } -}; - struct kvm_hists { struct hists hists; struct perf_hpp_list list; @@ -759,18 +750,18 @@ static bool handle_kvm_event(struct perf_kvm_stat *kvm, return true; } -static bool select_key(struct perf_kvm_stat *kvm) +static bool is_valid_key(struct perf_kvm_stat *kvm) { - int i; + static const char *key_array[] = { + "ev_name", "sample", "time", "max_t", "min_t", "mean_t", + }; + unsigned int i; - for (i = 0; keys[i].name; i++) { - if (!strcmp(keys[i].name, kvm->sort_key)) { - kvm->compare = keys[i].key; + for (i = 0; i < ARRAY_SIZE(key_array); i++) + if (!strcmp(key_array[i], kvm->sort_key)) return true; - } - } - pr_err("Unknown compare key:%s\n", kvm->sort_key); + pr_err("Unsupported sort key: %s\n", kvm->sort_key); return false; } @@ -1200,7 +1191,7 @@ static int kvm_events_live_report(struct perf_kvm_stat *kvm) return ret; if (!verify_vcpu(kvm->trace_vcpu) || - !select_key(kvm) || + !is_valid_key(kvm) || !register_kvm_events_ops(kvm)) { goto out; } @@ -1395,7 +1386,7 @@ static int kvm_events_report_vcpu(struct perf_kvm_stat *kvm) if (!verify_vcpu(vcpu)) goto exit; - if (!select_key(kvm)) + if (!is_valid_key(kvm)) goto exit; if (!register_kvm_events_ops(kvm)) diff --git a/tools/perf/util/kvm-stat.h b/tools/perf/util/kvm-stat.h index 3f0cbecb862c..35d03894fac3 100644 --- a/tools/perf/util/kvm-stat.h +++ b/tools/perf/util/kvm-stat.h @@ -49,13 +49,6 @@ struct kvm_event { struct hist_entry he; }; -typedef int64_t (*key_cmp_fun)(struct kvm_event*, struct kvm_event*, int); - -struct kvm_event_key { - const char *name; - key_cmp_fun key; -}; - struct child_event_ops { void (*get_key)(struct evsel *evsel, struct perf_sample *sample, @@ -98,7 +91,6 @@ struct perf_kvm_stat { const char *exit_reasons_isa; struct kvm_events_ops *events_ops; - key_cmp_fun compare; u64 total_time; u64 total_count; -- cgit v1.2.3-58-ga151 From fbb70bd3100527b9fea86c58e88a63a28f24f428 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Wed, 15 Mar 2023 22:51:09 +0800 Subject: perf kvm: Support printing attributions for dimensions This patch adds header, entry callback and width for every dimension, thus in TUI mode the tool can print items with the defined attributions. Reviewed-by: James Clark Signed-off-by: Leo Yan Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: John Garry Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230315145112.186603-2-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-kvm.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 94 insertions(+), 3 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-kvm.c b/tools/perf/builtin-kvm.c index d102d3a146f9..07f75663083a 100644 --- a/tools/perf/builtin-kvm.c +++ b/tools/perf/builtin-kvm.c @@ -84,8 +84,12 @@ struct kvm_hists { struct kvm_dimension { const char *name; + const char *header; + int width; int64_t (*cmp)(struct perf_hpp_fmt *fmt, struct hist_entry *left, struct hist_entry *right); + int (*entry)(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he); }; struct kvm_fmt { @@ -103,9 +107,24 @@ static int64_t ev_name_cmp(struct perf_hpp_fmt *fmt __maybe_unused, return -strcmp(left->kvm_info->name, right->kvm_info->name); } +static int fmt_width(struct perf_hpp_fmt *fmt, + struct perf_hpp *hpp __maybe_unused, + struct hists *hists __maybe_unused); + +static int ev_name_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + int width = fmt_width(fmt, hpp, he->hists); + + return scnprintf(hpp->buf, hpp->size, "%*s", width, he->kvm_info->name); +} + static struct kvm_dimension dim_event = { + .header = "Event name", .name = "ev_name", .cmp = ev_name_cmp, + .entry = ev_name_entry, + .width = 40, }; #define EV_METRIC_CMP(metric) \ @@ -131,29 +150,77 @@ EV_METRIC_CMP(max) EV_METRIC_CMP(min) EV_METRIC_CMP(mean) +#define EV_METRIC_ENTRY(metric) \ +static int ev_entry_##metric(struct perf_hpp_fmt *fmt, \ + struct perf_hpp *hpp, \ + struct hist_entry *he) \ +{ \ + struct kvm_event *event; \ + int width = fmt_width(fmt, hpp, he->hists); \ + struct perf_kvm_stat *perf_kvm; \ + \ + event = container_of(he, struct kvm_event, he); \ + perf_kvm = event->perf_kvm; \ + return scnprintf(hpp->buf, hpp->size, "%*lu", width, \ + get_event_##metric(event, perf_kvm->trace_vcpu)); \ +} + +EV_METRIC_ENTRY(time) +EV_METRIC_ENTRY(count) +EV_METRIC_ENTRY(max) +EV_METRIC_ENTRY(min) + static struct kvm_dimension dim_time = { + .header = "Time (ns)", .name = "time", .cmp = ev_cmp_time, + .entry = ev_entry_time, + .width = 12, }; static struct kvm_dimension dim_count = { + .header = "Samples", .name = "sample", .cmp = ev_cmp_count, + .entry = ev_entry_count, + .width = 12, }; static struct kvm_dimension dim_max_time = { + .header = "Max Time (ns)", .name = "max_t", .cmp = ev_cmp_max, + .entry = ev_entry_max, + .width = 14, }; static struct kvm_dimension dim_min_time = { + .header = "Min Time (ns)", .name = "min_t", .cmp = ev_cmp_min, + .entry = ev_entry_min, + .width = 14, }; +static int ev_entry_mean(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + struct kvm_event *event; + int width = fmt_width(fmt, hpp, he->hists); + struct perf_kvm_stat *perf_kvm; + + event = container_of(he, struct kvm_event, he); + perf_kvm = event->perf_kvm; + return scnprintf(hpp->buf, hpp->size, "%*lu", width, + get_event_mean(event, perf_kvm->trace_vcpu)); +} + static struct kvm_dimension dim_mean_time = { + .header = "Mean Time (ns)", .name = "mean_t", .cmp = ev_cmp_mean, + .entry = ev_entry_mean, + .width = 14, }; static struct kvm_dimension *dimensions[] = { @@ -166,6 +233,30 @@ static struct kvm_dimension *dimensions[] = { NULL, }; +static int fmt_width(struct perf_hpp_fmt *fmt, + struct perf_hpp *hpp __maybe_unused, + struct hists *hists __maybe_unused) +{ + struct kvm_fmt *kvm_fmt; + + kvm_fmt = container_of(fmt, struct kvm_fmt, fmt); + return kvm_fmt->dim->width; +} + +static int fmt_header(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hists *hists, int line __maybe_unused, + int *span __maybe_unused) +{ + struct kvm_fmt *kvm_fmt; + struct kvm_dimension *dim; + int width = fmt_width(fmt, hpp, hists); + + kvm_fmt = container_of(fmt, struct kvm_fmt, fmt); + dim = kvm_fmt->dim; + + return scnprintf(hpp->buf, hpp->size, "%*s", width, dim->header); +} + static bool fmt_equal(struct perf_hpp_fmt *a, struct perf_hpp_fmt *b) { struct kvm_fmt *kvm_fmt_a = container_of(a, struct kvm_fmt, fmt); @@ -215,9 +306,9 @@ static struct kvm_fmt *get_format(const char *name) fmt->cmp = dim->cmp; fmt->sort = dim->cmp; fmt->color = NULL; - fmt->entry = NULL; - fmt->header = NULL; - fmt->width = NULL; + fmt->entry = dim->entry; + fmt->header = fmt_header; + fmt->width = fmt_width; fmt->collapse = dim->cmp; fmt->equal = fmt_equal; fmt->free = fmt_free; -- cgit v1.2.3-58-ga151 From 32a5c2b84236d1eebf341ae4a90dd5e04aae97ae Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Wed, 15 Mar 2023 22:51:10 +0800 Subject: perf kvm: Add dimensions for percentages Add dimensions for count and time percentages, it would be useful for user to review percentage statistics. Reviewed-by: James Clark Signed-off-by: Leo Yan Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: John Garry Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230315145112.186603-2-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-kvm.c | 98 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 97 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/builtin-kvm.c b/tools/perf/builtin-kvm.c index 07f75663083a..9bfde8b7ac65 100644 --- a/tools/perf/builtin-kvm.c +++ b/tools/perf/builtin-kvm.c @@ -223,10 +223,105 @@ static struct kvm_dimension dim_mean_time = { .width = 14, }; +#define PERC_STR(__s, __v) \ +({ \ + scnprintf(__s, sizeof(__s), "%.2F%%", __v); \ + __s; \ +}) + +static double percent(u64 st, u64 tot) +{ + return tot ? 100. * (double) st / (double) tot : 0; +} + +#define EV_METRIC_PERCENT(metric) \ +static int ev_percent_##metric(struct hist_entry *he) \ +{ \ + struct kvm_event *event; \ + struct perf_kvm_stat *perf_kvm; \ + \ + event = container_of(he, struct kvm_event, he); \ + perf_kvm = event->perf_kvm; \ + \ + return percent(get_event_##metric(event, perf_kvm->trace_vcpu), \ + perf_kvm->total_##metric); \ +} + +EV_METRIC_PERCENT(time) +EV_METRIC_PERCENT(count) + +static int ev_entry_time_precent(struct perf_hpp_fmt *fmt, + struct perf_hpp *hpp, + struct hist_entry *he) +{ + int width = fmt_width(fmt, hpp, he->hists); + double per; + char buf[10]; + + per = ev_percent_time(he); + return scnprintf(hpp->buf, hpp->size, "%*s", width, PERC_STR(buf, per)); +} + +static int64_t +ev_cmp_time_precent(struct perf_hpp_fmt *fmt __maybe_unused, + struct hist_entry *left, struct hist_entry *right) +{ + double per_left; + double per_right; + + per_left = ev_percent_time(left); + per_right = ev_percent_time(right); + + return per_left - per_right; +} + +static struct kvm_dimension dim_time_percent = { + .header = "Time%", + .name = "percent_time", + .cmp = ev_cmp_time_precent, + .entry = ev_entry_time_precent, + .width = 12, +}; + +static int ev_entry_count_precent(struct perf_hpp_fmt *fmt, + struct perf_hpp *hpp, + struct hist_entry *he) +{ + int width = fmt_width(fmt, hpp, he->hists); + double per; + char buf[10]; + + per = ev_percent_count(he); + return scnprintf(hpp->buf, hpp->size, "%*s", width, PERC_STR(buf, per)); +} + +static int64_t +ev_cmp_count_precent(struct perf_hpp_fmt *fmt __maybe_unused, + struct hist_entry *left, struct hist_entry *right) +{ + double per_left; + double per_right; + + per_left = ev_percent_count(left); + per_right = ev_percent_count(right); + + return per_left - per_right; +} + +static struct kvm_dimension dim_count_percent = { + .header = "Sample%", + .name = "percent_sample", + .cmp = ev_cmp_count_precent, + .entry = ev_entry_count_precent, + .width = 12, +}; + static struct kvm_dimension *dimensions[] = { &dim_event, &dim_time, + &dim_time_percent, &dim_count, + &dim_count_percent, &dim_max_time, &dim_min_time, &dim_mean_time, @@ -877,7 +972,8 @@ static int filter_cb(struct hist_entry *he, void *arg __maybe_unused) static void sort_result(struct perf_kvm_stat *kvm) { - const char *output_columns = "ev_name,sample,time,max_t,min_t,mean_t"; + const char *output_columns = "ev_name,sample,percent_sample," + "time,percent_time,max_t,min_t,mean_t"; kvm_hists__reinit(output_columns, kvm->sort_key); hists__collapse_resort(&kvm_hists.hists, NULL); -- cgit v1.2.3-58-ga151 From 984f16cd602c82451b2e910ac58d7880bcb48b1a Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Wed, 15 Mar 2023 22:51:11 +0800 Subject: perf kvm: Add TUI mode for stat report Since we have supported histograms list and prepared the dimensions in the tool, this patch adds TUI mode for stat report. It also adds UI progress for sorting for better user experience. Committer notes: kvm_display() is only used by functions enclosed in: #if defined(HAVE_KVM_STAT_SUPPORT) && defined(HAVE_LIBTRACEEVENT) So do it with this new function as well. Signed-off-by: Leo Yan Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230315145112.186603-2-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-kvm.c | 109 ++++++++++++++++++++++++++++++++++++++++++++- tools/perf/util/kvm-stat.h | 1 + 2 files changed, 108 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-kvm.c b/tools/perf/builtin-kvm.c index 9bfde8b7ac65..4c205df5106f 100644 --- a/tools/perf/builtin-kvm.c +++ b/tools/perf/builtin-kvm.c @@ -23,6 +23,8 @@ #include "util/data.h" #include "util/ordered-events.h" #include "util/kvm-stat.h" +#include "ui/browsers/hists.h" +#include "ui/progress.h" #include "ui/ui.h" #include "util/string2.h" @@ -496,6 +498,7 @@ out: static int kvm_hists__init(void) { + kvm_hists.list.nr_header_lines = 1; __hists__init(&kvm_hists.hists, &kvm_hists.list); perf_hpp_list__init(&kvm_hists.list); return kvm_hpp_list__parse(&kvm_hists.list, NULL, "ev_name"); @@ -506,6 +509,93 @@ static int kvm_hists__reinit(const char *output, const char *sort) perf_hpp__reset_output_field(&kvm_hists.list); return kvm_hpp_list__parse(&kvm_hists.list, output, sort); } +static void print_result(struct perf_kvm_stat *kvm); + +#ifdef HAVE_SLANG_SUPPORT +static void kvm_browser__update_nr_entries(struct hist_browser *hb) +{ + struct rb_node *nd = rb_first_cached(&hb->hists->entries); + u64 nr_entries = 0; + + for (; nd; nd = rb_next(nd)) { + struct hist_entry *he = rb_entry(nd, struct hist_entry, + rb_node); + + if (!he->filtered) + nr_entries++; + } + + hb->nr_non_filtered_entries = nr_entries; +} + +static int kvm_browser__title(struct hist_browser *browser, + char *buf, size_t size) +{ + scnprintf(buf, size, "KVM event statistics (%lu entries)", + browser->nr_non_filtered_entries); + return 0; +} + +static struct hist_browser* +perf_kvm_browser__new(struct hists *hists) +{ + struct hist_browser *browser = hist_browser__new(hists); + + if (browser) + browser->title = kvm_browser__title; + + return browser; +} + +static int kvm__hists_browse(struct hists *hists) +{ + struct hist_browser *browser; + int key = -1; + + browser = perf_kvm_browser__new(hists); + if (browser == NULL) + return -1; + + /* reset abort key so that it can get Ctrl-C as a key */ + SLang_reset_tty(); + SLang_init_tty(0, 0, 0); + + kvm_browser__update_nr_entries(browser); + + while (1) { + key = hist_browser__run(browser, "? - help", true, 0); + + switch (key) { + case 'q': + goto out; + default: + break; + } + } + +out: + hist_browser__delete(browser); + return 0; +} + +static void kvm_display(struct perf_kvm_stat *kvm) +{ + if (!use_browser) + print_result(kvm); + else + kvm__hists_browse(&kvm_hists.hists); +} + +#else + +static void kvm_display(struct perf_kvm_stat *kvm) +{ + use_browser = 0; + print_result(kvm); +} + +#endif /* HAVE_SLANG_SUPPORT */ + #endif // defined(HAVE_KVM_STAT_SUPPORT) && defined(HAVE_LIBTRACEEVENT) static const char *get_filename_for_perf_kvm(void) @@ -972,12 +1062,15 @@ static int filter_cb(struct hist_entry *he, void *arg __maybe_unused) static void sort_result(struct perf_kvm_stat *kvm) { + struct ui_progress prog; const char *output_columns = "ev_name,sample,percent_sample," "time,percent_time,max_t,min_t,mean_t"; kvm_hists__reinit(output_columns, kvm->sort_key); + ui_progress__init(&prog, kvm_hists.hists.nr_entries, "Sorting..."); hists__collapse_resort(&kvm_hists.hists, NULL); hists__output_resort_cb(&kvm_hists.hists, NULL, filter_cb); + ui_progress__finish(); } static void print_vcpu_info(struct perf_kvm_stat *kvm) @@ -1579,7 +1672,14 @@ static int kvm_events_report_vcpu(struct perf_kvm_stat *kvm) if (!register_kvm_events_ops(kvm)) goto exit; - setup_pager(); + if (kvm->use_stdio) { + use_browser = 0; + setup_pager(); + } else { + use_browser = 1; + } + + setup_browser(false); kvm_hists__init(); @@ -1588,7 +1688,7 @@ static int kvm_events_report_vcpu(struct perf_kvm_stat *kvm) goto exit; sort_result(kvm); - print_result(kvm); + kvm_display(kvm); exit: return ret; @@ -1695,6 +1795,7 @@ kvm_events_report(struct perf_kvm_stat *kvm, int argc, const char **argv) OPT_STRING('p', "pid", &kvm->opts.target.pid, "pid", "analyze events only for given process id(s)"), OPT_BOOLEAN('f', "force", &kvm->force, "don't complain, do it"), + OPT_BOOLEAN(0, "stdio", &kvm->use_stdio, "use the stdio interface"), OPT_END() }; @@ -1712,6 +1813,10 @@ kvm_events_report(struct perf_kvm_stat *kvm, int argc, const char **argv) kvm_events_report_options); } +#ifndef HAVE_SLANG_SUPPORT + kvm->use_stdio = true; +#endif + if (!kvm->opts.target.pid) kvm->opts.target.system_wide = true; diff --git a/tools/perf/util/kvm-stat.h b/tools/perf/util/kvm-stat.h index 35d03894fac3..bc6c8e38ef50 100644 --- a/tools/perf/util/kvm-stat.h +++ b/tools/perf/util/kvm-stat.h @@ -103,6 +103,7 @@ struct perf_kvm_stat { unsigned int display_time; bool live; bool force; + bool use_stdio; }; struct kvm_reg_events_ops { -- cgit v1.2.3-58-ga151 From 96d541699e5c50b1bc2d50c83cd7145994d5f071 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Wed, 15 Mar 2023 22:51:12 +0800 Subject: perf kvm: Update documentation to reflect new changes Update documentation for new sorting and option '--stdio'. Reviewed-by: James Clark Signed-off-by: Leo Yan Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: John Garry Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230315145112.186603-2-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Documentation/perf-kvm.txt | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/Documentation/perf-kvm.txt b/tools/perf/Documentation/perf-kvm.txt index 2ad3f5d9f72b..b66be66fe836 100644 --- a/tools/perf/Documentation/perf-kvm.txt +++ b/tools/perf/Documentation/perf-kvm.txt @@ -58,7 +58,7 @@ There are a couple of variants of perf kvm: events. 'perf kvm stat report' reports statistical data which includes events - handled time, samples, and so on. + handled sample, percent_sample, time, percent_time, max_t, min_t, mean_t. 'perf kvm stat live' reports statistical data in a live mode (similar to record + report but with statistical data updated live at a given display @@ -82,6 +82,8 @@ OPTIONS :GMEXAMPLESUBCMD: top include::guest-files.txt[] +--stdio:: Use the stdio interface. + -v:: --verbose:: Be more verbose (show counter open errors, etc). @@ -97,7 +99,10 @@ STAT REPORT OPTIONS -k:: --key=:: Sorting key. Possible values: sample (default, sort by samples - number), time (sort by average time). + number), percent_sample (sort by sample percentage), time + (sort by average time), precent_time (sort by time percentage), + max_t (sort by maximum time), min_t (sort by minimum time), mean_t + (sort by mean time). -p:: --pid=:: Analyze events only for given process ID(s) (comma separated list). -- cgit v1.2.3-58-ga151 From c9602aa0469e19a84f9552a146ef87ec5dc7d576 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Mar 2023 20:37:49 -0700 Subject: perf symbol: Avoid memory leak from abi::__cxa_demangle MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rather than allocate memory, allow abi::__cxa_demangle to do that. This avoids a problem where on error NULL was returned triggering a memory leak. Fixes: 3b4e4efe88f615f1 ("perf symbol: Add abi::__cxa_demangle C++ demangling support") Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexey Bayduraev Cc: Andi Kleen Cc: Andrew Morton Cc: André Almeida Cc: Andy Shevchenko Cc: Darren Hart Cc: Davidlohr Bueso Cc: Dmitriy Vyukov Cc: Eric Dumazet Cc: German Gomez Cc: Hao Luo Cc: Ian Rogers Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Madhavan Srinivasan Cc: Mark Rutland Cc: Masami Hiramatsu Cc: Miaoqian Lin Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Riccardo Mancini Cc: Shunsuke Nakamura Cc: Song Liu Cc: Stephane Eranian Cc: Stephen Brennan Cc: Steven Rostedt (VMware) Cc: Thomas Gleixner Cc: Thomas Richter Cc: Yury Norov Link: https://lore.kernel.org/r/20230320033810.980165-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/demangle-cxx.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/demangle-cxx.cpp b/tools/perf/util/demangle-cxx.cpp index 8708bcafd370..85b706641837 100644 --- a/tools/perf/util/demangle-cxx.cpp +++ b/tools/perf/util/demangle-cxx.cpp @@ -38,11 +38,10 @@ char *cxx_demangle_sym(const char *str, bool params __maybe_unused, return cplus_demangle(str, flags); #elif defined(HAVE_CXA_DEMANGLE_SUPPORT) - size_t len = strlen(str); - char *output = (char*)malloc(len); + char *output; int status; - output = abi::__cxa_demangle(str, output, &len, &status); + output = abi::__cxa_demangle(str, /*output_buffer=*/NULL, /*length=*/NULL, &status); return output; #else return NULL; -- cgit v1.2.3-58-ga151 From 39b5e434fb3f06fae44c8a2df87eca036f9f9b5c Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Mar 2023 20:37:50 -0700 Subject: perf bpf_counter: Use public cpumap accessors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the use of internal apis via the cpumap accessor functions. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexey Bayduraev Cc: Andi Kleen Cc: Andrew Morton Cc: André Almeida Cc: Andy Shevchenko Cc: Darren Hart Cc: Davidlohr Bueso Cc: Dmitriy Vyukov Cc: Eric Dumazet Cc: German Gomez Cc: Hao Luo Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Madhavan Srinivasan Cc: Mark Rutland Cc: Masami Hiramatsu Cc: Miaoqian Lin Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Riccardo Mancini Cc: Shunsuke Nakamura Cc: Song Liu Cc: Stephane Eranian Cc: Stephen Brennan Cc: Steven Rostedt (VMware) Cc: Thomas Gleixner Cc: Thomas Richter Cc: Yury Norov Link: https://lore.kernel.org/r/20230320033810.980165-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/bpf_counter.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/bpf_counter.c b/tools/perf/util/bpf_counter.c index 1b77436e067e..76ee3e86824a 100644 --- a/tools/perf/util/bpf_counter.c +++ b/tools/perf/util/bpf_counter.c @@ -545,7 +545,7 @@ static int bperf__load(struct evsel *evsel, struct target *target) filter_type == BPERF_FILTER_TGID) key = perf_thread_map__pid(evsel->core.threads, i); else if (filter_type == BPERF_FILTER_CPU) - key = evsel->core.cpus->map[i].cpu; + key = perf_cpu_map__cpu(evsel->core.cpus, i).cpu; else break; @@ -587,9 +587,9 @@ static int bperf_sync_counters(struct evsel *evsel) { int num_cpu, i, cpu; - num_cpu = all_cpu_map->nr; + num_cpu = perf_cpu_map__nr(all_cpu_map); for (i = 0; i < num_cpu; i++) { - cpu = all_cpu_map->map[i].cpu; + cpu = perf_cpu_map__cpu(all_cpu_map, i).cpu; bperf_trigger_reading(evsel->bperf_leader_prog_fd, cpu); } return 0; -- cgit v1.2.3-58-ga151 From 9bb5e1f682d8391b7e9918b12d22af9492b74dad Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Mar 2023 20:37:51 -0700 Subject: perf tests: Add common error route for code-reading MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A later change will enforce that the map is put on this path regardless of success or error. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexey Bayduraev Cc: Andi Kleen Cc: Andrew Morton Cc: André Almeida Cc: Andy Shevchenko Cc: Darren Hart Cc: Davidlohr Bueso Cc: Dmitriy Vyukov Cc: Eric Dumazet Cc: German Gomez Cc: Hao Luo Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Madhavan Srinivasan Cc: Mark Rutland Cc: Masami Hiramatsu Cc: Miaoqian Lin Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Riccardo Mancini Cc: Shunsuke Nakamura Cc: Song Liu Cc: Stephane Eranian Cc: Stephen Brennan Cc: Steven Rostedt (VMware) Cc: Thomas Gleixner Cc: Thomas Richter Cc: Yury Norov Link: https://lore.kernel.org/r/20230320033810.980165-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/code-reading.c | 39 +++++++++++++++++++++++---------------- 1 file changed, 23 insertions(+), 16 deletions(-) (limited to 'tools') diff --git a/tools/perf/tests/code-reading.c b/tools/perf/tests/code-reading.c index cb8cd09938d5..fb67fd5ebd9f 100644 --- a/tools/perf/tests/code-reading.c +++ b/tools/perf/tests/code-reading.c @@ -236,18 +236,19 @@ static int read_object_code(u64 addr, size_t len, u8 cpumode, const char *objdump_name; char decomp_name[KMOD_DECOMP_LEN]; bool decomp = false; - int ret; + int ret, err = 0; pr_debug("Reading object code for memory address: %#"PRIx64"\n", addr); if (!thread__find_map(thread, cpumode, addr, &al) || !al.map->dso) { if (cpumode == PERF_RECORD_MISC_HYPERVISOR) { pr_debug("Hypervisor address can not be resolved - skipping\n"); - return 0; + goto out; } pr_debug("thread__find_map failed\n"); - return -1; + err = -1; + goto out; } pr_debug("File is: %s\n", al.map->dso->long_name); @@ -255,7 +256,7 @@ static int read_object_code(u64 addr, size_t len, u8 cpumode, if (al.map->dso->symtab_type == DSO_BINARY_TYPE__KALLSYMS && !dso__is_kcore(al.map->dso)) { pr_debug("Unexpected kernel address - skipping\n"); - return 0; + goto out; } pr_debug("On file address is: %#"PRIx64"\n", al.addr); @@ -272,15 +273,18 @@ static int read_object_code(u64 addr, size_t len, u8 cpumode, al.addr, buf1, len); if (ret_len != len) { pr_debug("dso__data_read_offset failed\n"); - return -1; + err = -1; + goto out; } /* * Converting addresses for use by objdump requires more information. * map__load() does that. See map__rip_2objdump() for details. */ - if (map__load(al.map)) - return -1; + if (map__load(al.map)) { + err = -1; + goto out; + } /* objdump struggles with kcore - try each map only once */ if (dso__is_kcore(al.map->dso)) { @@ -290,12 +294,12 @@ static int read_object_code(u64 addr, size_t len, u8 cpumode, if (state->done[d] == al.map->start) { pr_debug("kcore map tested already"); pr_debug(" - skipping\n"); - return 0; + goto out; } } if (state->done_cnt >= ARRAY_SIZE(state->done)) { pr_debug("Too many kcore maps - skipping\n"); - return 0; + goto out; } state->done[state->done_cnt++] = al.map->start; } @@ -306,7 +310,8 @@ static int read_object_code(u64 addr, size_t len, u8 cpumode, decomp_name, sizeof(decomp_name)) < 0) { pr_debug("decompression failed\n"); - return -1; + err = -1; + goto out; } decomp = true; @@ -337,15 +342,16 @@ static int read_object_code(u64 addr, size_t len, u8 cpumode, */ pr_debug("objdump failed for kcore"); pr_debug(" - skipping\n"); - return 0; } else { - return -1; + err = -1; } + goto out; } } if (ret < 0) { pr_debug("read_via_objdump failed\n"); - return -1; + err = -1; + goto out; } /* The results should be identical */ @@ -355,11 +361,12 @@ static int read_object_code(u64 addr, size_t len, u8 cpumode, dump_buf(buf1, len); pr_debug("buf2 (objdump):\n"); dump_buf(buf2, len); - return -1; + err = -1; + goto out; } pr_debug("Bytes read match those read by objdump\n"); - - return 0; +out: + return err; } static int process_sample_event(struct machine *machine, -- cgit v1.2.3-58-ga151 From 82c6d83bc1779cc306f78083fc79dc7ec7d9b18d Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Mar 2023 20:37:52 -0700 Subject: perf test: Fix memory leak in symbols MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit machine__delete() doesn't delete threads. Add call to delete threads ahead of deleting the machine. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexey Bayduraev Cc: Andi Kleen Cc: Andrew Morton Cc: André Almeida Cc: Andy Shevchenko Cc: Darren Hart Cc: Davidlohr Bueso Cc: Dmitriy Vyukov Cc: Eric Dumazet Cc: German Gomez Cc: Hao Luo Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Madhavan Srinivasan Cc: Mark Rutland Cc: Masami Hiramatsu Cc: Miaoqian Lin Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Riccardo Mancini Cc: Shunsuke Nakamura Cc: Song Liu Cc: Stephane Eranian Cc: Stephen Brennan Cc: Steven Rostedt (VMware) Cc: Thomas Gleixner Cc: Thomas Richter Cc: Yury Norov Link: https://lore.kernel.org/r/20230320033810.980165-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/symbols.c | 1 + 1 file changed, 1 insertion(+) (limited to 'tools') diff --git a/tools/perf/tests/symbols.c b/tools/perf/tests/symbols.c index 057b16df6416..0793f8f419e2 100644 --- a/tools/perf/tests/symbols.c +++ b/tools/perf/tests/symbols.c @@ -38,6 +38,7 @@ static int init_test_info(struct test_info *ti) static void exit_test_info(struct test_info *ti) { thread__put(ti->thread); + machine__delete_threads(ti->machine); machine__delete(ti->machine); } -- cgit v1.2.3-58-ga151 From ec9640f77d199c4ed78d7a00fbbaf78773c38d9d Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Sun, 19 Mar 2023 20:37:53 -0700 Subject: perf symbol: Sort names under write lock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If finding a name doesn't find the sorted names then they are allocated and sorted. This shouldn't be done under a read lock as another reader may access it. Release the read lock and acquire the write lock, then release the write lock and reacquire the read lock. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexey Bayduraev Cc: Andi Kleen Cc: Andrew Morton Cc: André Almeida Cc: Andy Shevchenko Cc: Darren Hart Cc: Davidlohr Bueso Cc: Dmitriy Vyukov Cc: Eric Dumazet Cc: German Gomez Cc: Hao Luo Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Madhavan Srinivasan Cc: Mark Rutland Cc: Masami Hiramatsu Cc: Miaoqian Lin Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Riccardo Mancini Cc: Shunsuke Nakamura Cc: Song Liu Cc: Stephane Eranian Cc: Stephen Brennan Cc: Steven Rostedt (VMware) Cc: Thomas Gleixner Cc: Thomas Richter Cc: Yury Norov Link: https://lore.kernel.org/r/20230320033810.980165-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/symbol.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'tools') diff --git a/tools/perf/util/symbol.c b/tools/perf/util/symbol.c index 317c0706852f..a458aa8b87bb 100644 --- a/tools/perf/util/symbol.c +++ b/tools/perf/util/symbol.c @@ -2018,6 +2018,9 @@ static int map__groups__sort_by_name_from_rbtree(struct maps *maps) if (maps_by_name == NULL) return -1; + up_read(&maps->lock); + down_write(&maps->lock); + maps->maps_by_name = maps_by_name; maps->nr_maps_allocated = maps->nr_maps; @@ -2025,6 +2028,10 @@ static int map__groups__sort_by_name_from_rbtree(struct maps *maps) maps_by_name[i++] = map; __maps__sort_by_name(maps); + + up_write(&maps->lock); + down_read(&maps->lock); + return 0; } -- cgit v1.2.3-58-ga151 From 34f576c95d1bd1be3f123c2d1f3db084e5e72583 Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Mon, 20 Mar 2023 20:35:16 +0200 Subject: perf intel-pt: Add event type names UINTR and UIRET UINTR and UIRET are listed in table 32-50 "CFE Packet Type and Vector Fields Details" in the Intel Processor Trace chapter of The Intel SDM Volume 3 version 078. The codes are for "User interrupt delivered" and "Exiting from user interrupt routine" respectively. Signed-off-by: Adrian Hunter Acked-by: Ian Rogers Cc: Jiri Olsa Cc: Namhyung Kim Link: https://lore.kernel.org/r/20230320183517.15099-2-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-script.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index 976f8bfe099c..c9296d8b33c0 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -1906,7 +1906,7 @@ static int perf_sample__fprintf_synth_evt(struct perf_sample *sample, FILE *fp) struct perf_synth_intel_evt *data = perf_sample__synth_ptr(sample); const char *cfe[32] = {NULL, "INTR", "IRET", "SMI", "RSM", "SIPI", "INIT", "VMENTRY", "VMEXIT", "VMEXIT_INTR", - "SHUTDOWN"}; + "SHUTDOWN", NULL, "UINTR", "UIRET"}; const char *evd[64] = {"PFA", "VMXQ", "VMXR"}; const char *s; int len, i; -- cgit v1.2.3-58-ga151 From 052072f69f28864cebaeb6ca9dc2c9825b72c834 Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Mon, 20 Mar 2023 20:35:17 +0200 Subject: perf intel-pt: Add support for new branch instructions ERETS and ERETU Intel Flexible Return and Event Delivery (FRED) adds instructions ERETS (return to supervisor) and ERETU (return to user). Intel PT instruction decoder needs to know about these instructions because they are branch instructions. Similar to IRET instructions, when the decoder encounters one of these instructions it will match it to a TIP (target instruction pointer) packet that informs what the branch destination is. The existing "x86 instruction decoder - new instructions" test can be used to test the result e.g. $ perf test -v ins |& grep eret Decoded ok: f2 0f 01 ca erets Decoded ok: f3 0f 01 ca eretu Signed-off-by: Adrian Hunter Acked-by: Ian Rogers Cc: Jiri Olsa Cc: Namhyung Kim Link: https://lore.kernel.org/r/20230320183517.15099-2-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/x86/tests/insn-x86.c | 4 ++++ .../perf/util/intel-pt-decoder/intel-pt-insn-decoder.c | 18 ++++++++++++++++++ .../perf/util/intel-pt-decoder/intel-pt-insn-decoder.h | 2 ++ 3 files changed, 24 insertions(+) (limited to 'tools') diff --git a/tools/perf/arch/x86/tests/insn-x86.c b/tools/perf/arch/x86/tests/insn-x86.c index 94b490c434d0..735257d205b5 100644 --- a/tools/perf/arch/x86/tests/insn-x86.c +++ b/tools/perf/arch/x86/tests/insn-x86.c @@ -29,6 +29,8 @@ struct test_data test_data_64[] = { #include "insn-x86-dat-64.c" {{0x0f, 0x01, 0xee}, 3, 0, NULL, NULL, "0f 01 ee \trdpkru"}, {{0x0f, 0x01, 0xef}, 3, 0, NULL, NULL, "0f 01 ef \twrpkru"}, + {{0xf2, 0x0f, 0x01, 0xca}, 4, 0, "erets", "indirect", "f2 0f 01 ca \terets"}, + {{0xf3, 0x0f, 0x01, 0xca}, 4, 0, "eretu", "indirect", "f3 0f 01 ca \teretu"}, {{0}, 0, 0, NULL, NULL, NULL}, }; @@ -49,6 +51,8 @@ static int get_op(const char *op_str) {"syscall", INTEL_PT_OP_SYSCALL}, {"sysret", INTEL_PT_OP_SYSRET}, {"vmentry", INTEL_PT_OP_VMENTRY}, + {"erets", INTEL_PT_OP_ERETS}, + {"eretu", INTEL_PT_OP_ERETU}, {NULL, 0}, }; struct val_data *val; diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.c b/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.c index 22308dd93010..c5d57027ec23 100644 --- a/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.c +++ b/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.c @@ -52,6 +52,20 @@ static void intel_pt_insn_decoder(struct insn *insn, op = INTEL_PT_OP_VMENTRY; branch = INTEL_PT_BR_INDIRECT; break; + case 0xca: + switch (insn->prefixes.bytes[3]) { + case 0xf2: /* erets */ + op = INTEL_PT_OP_ERETS; + branch = INTEL_PT_BR_INDIRECT; + break; + case 0xf3: /* eretu */ + op = INTEL_PT_OP_ERETU; + branch = INTEL_PT_BR_INDIRECT; + break; + default: + break; + } + break; default: break; } @@ -230,6 +244,8 @@ const char *branch_name[] = { [INTEL_PT_OP_SYSCALL] = "Syscall", [INTEL_PT_OP_SYSRET] = "Sysret", [INTEL_PT_OP_VMENTRY] = "VMentry", + [INTEL_PT_OP_ERETS] = "Erets", + [INTEL_PT_OP_ERETU] = "Eretu", }; const char *intel_pt_insn_name(enum intel_pt_insn_op op) @@ -273,6 +289,8 @@ int intel_pt_insn_type(enum intel_pt_insn_op op) case INTEL_PT_OP_LOOP: return PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CONDITIONAL; case INTEL_PT_OP_IRET: + case INTEL_PT_OP_ERETS: + case INTEL_PT_OP_ERETU: return PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_RETURN | PERF_IP_FLAG_INTERRUPT; case INTEL_PT_OP_INT: diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.h b/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.h index e3338b56a75f..7fb7fe3a1566 100644 --- a/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.h +++ b/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.h @@ -25,6 +25,8 @@ enum intel_pt_insn_op { INTEL_PT_OP_SYSCALL, INTEL_PT_OP_SYSRET, INTEL_PT_OP_VMENTRY, + INTEL_PT_OP_ERETS, + INTEL_PT_OP_ERETU, }; enum intel_pt_insn_branch { -- cgit v1.2.3-58-ga151 From f43cc1a9a8612ca591e4c205b9f503d63380eccc Mon Sep 17 00:00:00 2001 From: German Gomez Date: Mon, 20 Mar 2023 15:15:05 +0000 Subject: perf event: Add 'simd_flags' field to 'struct perf_sample' Add new field to 'struct perf_sample' to store flags related to SIMD ops. It will be used to store SIMD information from SVE and NEON when profiling using ARM SPE. Signed-off-by: German Gomez Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Anshuman.Khandual@arm.com Cc: Ingo Molnar Cc: Jiri Olsa Cc: John Garry Cc: Leo Yan Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230320151509.1137462-2-james.clark@arm.com Signed-off-by: James Clark Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/sample.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'tools') diff --git a/tools/perf/util/sample.h b/tools/perf/util/sample.h index 33b08e0ac746..c92ad0f51ecd 100644 --- a/tools/perf/util/sample.h +++ b/tools/perf/util/sample.h @@ -66,6 +66,18 @@ struct aux_sample { void *data; }; +struct simd_flags { + u64 arch:1, /* architecture (isa) */ + pred:2; /* predication */ +}; + +/* simd architecture flags */ +#define SIMD_OP_FLAGS_ARCH_SVE 0x01 /* ARM SVE */ + +/* simd predicate flags */ +#define SIMD_OP_FLAGS_PRED_PARTIAL 0x01 /* partial predicate */ +#define SIMD_OP_FLAGS_PRED_EMPTY 0x02 /* empty predicate */ + struct perf_sample { u64 ip; u32 pid, tid; @@ -106,6 +118,7 @@ struct perf_sample { struct stack_dump user_stack; struct sample_read read; struct aux_sample aux_sample; + struct simd_flags simd_flags; }; /* -- cgit v1.2.3-58-ga151 From 0066015a3d8f9c01a17eb04579edba7dac9510af Mon Sep 17 00:00:00 2001 From: German Gomez Date: Mon, 20 Mar 2023 15:15:06 +0000 Subject: perf arm-spe: Refactor arm-spe to support operation packet type Extend the decoder of Arm SPE records to support more fields from the operation packet type. Not all fields are being decoded by this commit. Only those needed to support the use-case SVE load/store/other operations. Suggested-by: Leo Yan Signed-off-by: German Gomez Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Anshuman.Khandual@arm.com Cc: Ingo Molnar Cc: Jiri Olsa Cc: John Garry Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230320151509.1137462-2-james.clark@arm.com Signed-off-by: James Clark Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/arm-spe-decoder/arm-spe-decoder.c | 30 +++++++++++++-- tools/perf/util/arm-spe-decoder/arm-spe-decoder.h | 47 ++++++++++++++++++----- tools/perf/util/arm-spe.c | 8 ++-- 3 files changed, 67 insertions(+), 18 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c index 40dcedfd75cd..f3918f290df5 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c +++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.c @@ -190,11 +190,27 @@ static int arm_spe_read_record(struct arm_spe_decoder *decoder) decoder->record.context_id = payload; break; case ARM_SPE_OP_TYPE: - if (idx == SPE_OP_PKT_HDR_CLASS_LD_ST_ATOMIC) { - if (payload & 0x1) - decoder->record.op = ARM_SPE_ST; + switch (idx) { + case SPE_OP_PKT_HDR_CLASS_LD_ST_ATOMIC: + decoder->record.op |= ARM_SPE_OP_LDST; + if (payload & SPE_OP_PKT_ST) + decoder->record.op |= ARM_SPE_OP_ST; else - decoder->record.op = ARM_SPE_LD; + decoder->record.op |= ARM_SPE_OP_LD; + if (SPE_OP_PKT_IS_LDST_SVE(payload)) + decoder->record.op |= ARM_SPE_OP_SVE_LDST; + break; + case SPE_OP_PKT_HDR_CLASS_OTHER: + decoder->record.op |= ARM_SPE_OP_OTHER; + if (SPE_OP_PKT_IS_OTHER_SVE_OP(payload)) + decoder->record.op |= ARM_SPE_OP_SVE_OTHER; + break; + case SPE_OP_PKT_HDR_CLASS_BR_ERET: + decoder->record.op |= ARM_SPE_OP_BRANCH_ERET; + break; + default: + pr_err("Get packet error!\n"); + return -1; } break; case ARM_SPE_EVENTS: @@ -222,6 +238,12 @@ static int arm_spe_read_record(struct arm_spe_decoder *decoder) if (payload & BIT(EV_MISPRED)) decoder->record.type |= ARM_SPE_BRANCH_MISS; + if (payload & BIT(EV_PARTIAL_PREDICATE)) + decoder->record.type |= ARM_SPE_SVE_PARTIAL_PRED; + + if (payload & BIT(EV_EMPTY_PREDICATE)) + decoder->record.type |= ARM_SPE_SVE_EMPTY_PRED; + break; case ARM_SPE_DATA_SOURCE: decoder->record.source = payload; diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h index 46a61df1145b..1443c28545a9 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h +++ b/tools/perf/util/arm-spe-decoder/arm-spe-decoder.h @@ -14,19 +14,46 @@ #include "arm-spe-pkt-decoder.h" enum arm_spe_sample_type { - ARM_SPE_L1D_ACCESS = 1 << 0, - ARM_SPE_L1D_MISS = 1 << 1, - ARM_SPE_LLC_ACCESS = 1 << 2, - ARM_SPE_LLC_MISS = 1 << 3, - ARM_SPE_TLB_ACCESS = 1 << 4, - ARM_SPE_TLB_MISS = 1 << 5, - ARM_SPE_BRANCH_MISS = 1 << 6, - ARM_SPE_REMOTE_ACCESS = 1 << 7, + ARM_SPE_L1D_ACCESS = 1 << 0, + ARM_SPE_L1D_MISS = 1 << 1, + ARM_SPE_LLC_ACCESS = 1 << 2, + ARM_SPE_LLC_MISS = 1 << 3, + ARM_SPE_TLB_ACCESS = 1 << 4, + ARM_SPE_TLB_MISS = 1 << 5, + ARM_SPE_BRANCH_MISS = 1 << 6, + ARM_SPE_REMOTE_ACCESS = 1 << 7, + ARM_SPE_SVE_PARTIAL_PRED = 1 << 8, + ARM_SPE_SVE_EMPTY_PRED = 1 << 9, }; enum arm_spe_op_type { - ARM_SPE_LD = 1 << 0, - ARM_SPE_ST = 1 << 1, + /* First level operation type */ + ARM_SPE_OP_OTHER = 1 << 0, + ARM_SPE_OP_LDST = 1 << 1, + ARM_SPE_OP_BRANCH_ERET = 1 << 2, + + /* Second level operation type for OTHER */ + ARM_SPE_OP_SVE_OTHER = 1 << 16, + ARM_SPE_OP_SVE_FP = 1 << 17, + ARM_SPE_OP_SVE_PRED_OTHER = 1 << 18, + + /* Second level operation type for LDST */ + ARM_SPE_OP_LD = 1 << 16, + ARM_SPE_OP_ST = 1 << 17, + ARM_SPE_OP_ATOMIC = 1 << 18, + ARM_SPE_OP_EXCL = 1 << 19, + ARM_SPE_OP_AR = 1 << 20, + ARM_SPE_OP_SIMD_FP = 1 << 21, + ARM_SPE_OP_GP_REG = 1 << 22, + ARM_SPE_OP_UNSPEC_REG = 1 << 23, + ARM_SPE_OP_NV_SYSREG = 1 << 24, + ARM_SPE_OP_SVE_LDST = 1 << 25, + ARM_SPE_OP_SVE_PRED_LDST = 1 << 26, + ARM_SPE_OP_SVE_SG = 1 << 27, + + /* Second level operation type for BRANCH_ERET */ + ARM_SPE_OP_BR_COND = 1 << 16, + ARM_SPE_OP_BR_INDIRECT = 1 << 17, }; enum arm_spe_neoverse_data_source { diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 906476a839e1..bfae4731a47a 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -411,7 +411,7 @@ static void arm_spe__synth_data_source_neoverse(const struct arm_spe_record *rec * We have no data on the hit level or data source for stores in the * Neoverse SPE records. */ - if (record->op & ARM_SPE_ST) { + if (record->op & ARM_SPE_OP_ST) { data_src->mem_lvl = PERF_MEM_LVL_NA; data_src->mem_lvl_num = PERF_MEM_LVLNUM_NA; data_src->mem_snoop = PERF_MEM_SNOOP_NA; @@ -497,12 +497,12 @@ static void arm_spe__synth_data_source_generic(const struct arm_spe_record *reco static u64 arm_spe__synth_data_source(const struct arm_spe_record *record, u64 midr) { - union perf_mem_data_src data_src = { 0 }; + union perf_mem_data_src data_src = { .mem_op = PERF_MEM_OP_NA }; bool is_neoverse = is_midr_in_range_list(midr, neoverse_spe); - if (record->op == ARM_SPE_LD) + if (record->op & ARM_SPE_OP_LD) data_src.mem_op = PERF_MEM_OP_LOAD; - else if (record->op == ARM_SPE_ST) + else if (record->op & ARM_SPE_OP_ST) data_src.mem_op = PERF_MEM_OP_STORE; else return 0; -- cgit v1.2.3-58-ga151 From 03a6c16ebf0162b57acd16c2dd2baa79d8db2a97 Mon Sep 17 00:00:00 2001 From: German Gomez Date: Mon, 20 Mar 2023 15:15:07 +0000 Subject: perf arm-spe: Add SVE flags to the SPE samples Add flags from the Scalable Vector Extension (SVE) to the SPE samples which are available from Armv8.3 (FEAT_SPEv1p1). These will be displayed in a new SIMD sort field in a later commit. Signed-off-by: German Gomez Signed-off-by: James Clark Acked-by: Ian Rogers Link: https://lore.kernel.org/r/20230320151509.1137462-2-james.clark@arm.com Cc: Anshuman.Khandual@arm.com Cc: Mark Rutland Cc: Peter Zijlstra Cc: Adrian Hunter Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Namhyung Kim Cc: Will Deacon Cc: Leo Yan Cc: Mike Leach Cc: Alexander Shishkin Cc: linux-arm-kernel@lists.infradead.org Cc: John Garry Cc: Ingo Molnar Cc: linux-kernel@vger.kernel.org Cc: linux-perf-users@vger.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/arm-spe.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'tools') diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index bfae4731a47a..7b36ba6b4079 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -273,6 +273,25 @@ static int arm_spe_set_tid(struct arm_spe_queue *speq, pid_t tid) return 0; } +static struct simd_flags arm_spe__synth_simd_flags(const struct arm_spe_record *record) +{ + struct simd_flags simd_flags = {}; + + if ((record->op & ARM_SPE_OP_LDST) && (record->op & ARM_SPE_OP_SVE_LDST)) + simd_flags.arch |= SIMD_OP_FLAGS_ARCH_SVE; + + if ((record->op & ARM_SPE_OP_OTHER) && (record->op & ARM_SPE_OP_SVE_OTHER)) + simd_flags.arch |= SIMD_OP_FLAGS_ARCH_SVE; + + if (record->type & ARM_SPE_SVE_PARTIAL_PRED) + simd_flags.pred |= SIMD_OP_FLAGS_PRED_PARTIAL; + + if (record->type & ARM_SPE_SVE_EMPTY_PRED) + simd_flags.pred |= SIMD_OP_FLAGS_PRED_EMPTY; + + return simd_flags; +} + static void arm_spe_prep_sample(struct arm_spe *spe, struct arm_spe_queue *speq, union perf_event *event, @@ -289,6 +308,7 @@ static void arm_spe_prep_sample(struct arm_spe *spe, sample->tid = speq->tid; sample->period = 1; sample->cpu = speq->cpu; + sample->simd_flags = arm_spe__synth_simd_flags(record); event->sample.header.type = PERF_RECORD_SAMPLE; event->sample.header.misc = sample->cpumode; -- cgit v1.2.3-58-ga151 From ea15483e7c55f73809cd9e208fff511966539ee5 Mon Sep 17 00:00:00 2001 From: German Gomez Date: Mon, 20 Mar 2023 15:15:08 +0000 Subject: perf report: Add 'simd' sort field Add 'simd' sort field to visualize SIMD ops in 'perf report'. Rows are labeled with the SIMD ISA, and the type of predicate (if any): - [p] partial predicate - [e] empty predicate (no elements in the vector being used) Example with Arm SPE and SVE (Scalable Vector Extension): #include double src[1025], dst[1025]; int main(void) { svfloat64_t vc = svdup_f64(1); for(;;) for(int i = 0; i < 1025; i += svcntd()) { svbool_t pg = svwhilelt_b64(i, 1025); svfloat64_t vsrc = svld1(pg, &src[i]); svfloat64_t vdst = svadd_x(pg, vsrc, vc); svst1(pg, &dst[i], vdst); } return 0; } ... compiled using "gcc-11 -march=armv8-a+sve -O3" Profiling on a platform that implements FEAT_SVE and FEAT_SPEv1p1: $ perf record -e arm_spe_0// -- ./a.out $ perf report --itrace=i1i -s overhead,pid,simd,sym Overhead Pid:Command Simd Symbol ........ ................ ....... ...................... 53.76% 10758:program [.] main 46.14% 10758:program [.] SVE [.] main 0.09% 10758:program [p] SVE [.] main The report shows 0.09% of the sampled SVE operations use partial predicates due to src and dst arrays not being multiples of the vector register lengths. Signed-off-by: German Gomez Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Anshuman.Khandual@arm.com Cc: Ingo Molnar Cc: Jiri Olsa Cc: John Garry Cc: Leo Yan Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230320151509.1137462-2-james.clark@arm.com Signed-off-by: James Clark Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Documentation/perf-report.txt | 1 + tools/perf/util/hist.c | 1 + tools/perf/util/hist.h | 1 + tools/perf/util/sort.c | 47 ++++++++++++++++++++++++++++++++ tools/perf/util/sort.h | 2 ++ 5 files changed, 52 insertions(+) (limited to 'tools') diff --git a/tools/perf/Documentation/perf-report.txt b/tools/perf/Documentation/perf-report.txt index c242e8da6b1a..cfd502f7e6da 100644 --- a/tools/perf/Documentation/perf-report.txt +++ b/tools/perf/Documentation/perf-report.txt @@ -117,6 +117,7 @@ OPTIONS - addr: (Full) virtual address of the sampled instruction - retire_lat: On X86, this reports pipeline stall of this instruction compared to the previous instruction in cycles. And currently supported only on X86 + - simd: Flags describing a SIMD operation. "e" for empty Arm SVE predicate. "p" for partial Arm SVE predicate By default, comm, dso and symbol keys are used. (i.e. --sort comm,dso,symbol) diff --git a/tools/perf/util/hist.c b/tools/perf/util/hist.c index 3670136a0074..0c11f50abfec 100644 --- a/tools/perf/util/hist.c +++ b/tools/perf/util/hist.c @@ -745,6 +745,7 @@ __hists__add_entry(struct hists *hists, .weight = sample->weight, .ins_lat = sample->ins_lat, .p_stage_cyc = sample->p_stage_cyc, + .simd_flags = sample->simd_flags, }, *he = hists__findnew_entry(hists, &entry, al, sample_self); if (!hists->has_callchains && he && he->callchain_size != 0) diff --git a/tools/perf/util/hist.h b/tools/perf/util/hist.h index 86a677954279..afc9f1c7f4dc 100644 --- a/tools/perf/util/hist.h +++ b/tools/perf/util/hist.h @@ -81,6 +81,7 @@ enum hist_column { HISTC_ADDR_FROM, HISTC_ADDR_TO, HISTC_ADDR, + HISTC_SIMD, HISTC_NR_COLS, /* Last entry */ }; diff --git a/tools/perf/util/sort.c b/tools/perf/util/sort.c index 093a0c8b2e3d..e11e68ecf0a2 100644 --- a/tools/perf/util/sort.c +++ b/tools/perf/util/sort.c @@ -139,6 +139,52 @@ struct sort_entry sort_thread = { .se_width_idx = HISTC_THREAD, }; +/* --sort simd */ + +static int64_t +sort__simd_cmp(struct hist_entry *left, struct hist_entry *right) +{ + if (left->simd_flags.arch != right->simd_flags.arch) + return (int64_t) left->simd_flags.arch - right->simd_flags.arch; + + return (int64_t) left->simd_flags.pred - right->simd_flags.pred; +} + +static const char *hist_entry__get_simd_name(struct simd_flags *simd_flags) +{ + u64 arch = simd_flags->arch; + + if (arch & SIMD_OP_FLAGS_ARCH_SVE) + return "SVE"; + else + return "n/a"; +} + +static int hist_entry__simd_snprintf(struct hist_entry *he, char *bf, + size_t size, unsigned int width __maybe_unused) +{ + const char *name; + + if (!he->simd_flags.arch) + return repsep_snprintf(bf, size, ""); + + name = hist_entry__get_simd_name(&he->simd_flags); + + if (he->simd_flags.pred & SIMD_OP_FLAGS_PRED_EMPTY) + return repsep_snprintf(bf, size, "[e] %s", name); + else if (he->simd_flags.pred & SIMD_OP_FLAGS_PRED_PARTIAL) + return repsep_snprintf(bf, size, "[p] %s", name); + + return repsep_snprintf(bf, size, "[.] %s", name); +} + +struct sort_entry sort_simd = { + .se_header = "Simd ", + .se_cmp = sort__simd_cmp, + .se_snprintf = hist_entry__simd_snprintf, + .se_width_idx = HISTC_SIMD, +}; + /* --sort comm */ /* @@ -2142,6 +2188,7 @@ static struct sort_dimension common_sort_dimensions[] = { DIM(SORT_ADDR, "addr", sort_addr), DIM(SORT_LOCAL_RETIRE_LAT, "local_retire_lat", sort_local_p_stage_cyc), DIM(SORT_GLOBAL_RETIRE_LAT, "retire_lat", sort_global_p_stage_cyc), + DIM(SORT_SIMD, "simd", sort_simd) }; #undef DIM diff --git a/tools/perf/util/sort.h b/tools/perf/util/sort.h index 22f437c3476f..ecfb7f1359d5 100644 --- a/tools/perf/util/sort.h +++ b/tools/perf/util/sort.h @@ -111,6 +111,7 @@ struct hist_entry { u64 p_stage_cyc; u8 cpumode; u8 depth; + struct simd_flags simd_flags; /* We are added by hists__add_dummy_entry. */ bool dummy; @@ -241,6 +242,7 @@ enum sort_type { SORT_ADDR, SORT_LOCAL_RETIRE_LAT, SORT_GLOBAL_RETIRE_LAT, + SORT_SIMD, /* branch stack specific sort keys */ __SORT_BRANCH_STACK, -- cgit v1.2.3-58-ga151 From f1e8f25980968f7c18f1eb977bd1d5fd716325a5 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Mon, 20 Mar 2023 14:16:18 +0800 Subject: perf kvm: Reference count 'struct kvm_info' hists__add_entry_ops() doesn't allocate a new histogram entry if it has an existing entry for a KVM event, in this case, find_create_kvm_event() allocates a 'struct kvm_info' but it's not used by any histograms and never freed. To fix the memory leak, this patch first introduces a refcnt and a set of functions for refcnt operations on 'struct kvm_info'. When the data structure is not anymore used (the refcnt hits zero) kvm_info__zput() will free the memory used. Committer: Provide a nop version of kvm_info__zput() to be used when HAVE_KVM_STAT_SUPPORT isn't defined as it is used unconditionally in hists__findnew_entry() and hist_entry__delete(). Signed-off-by: Leo Yan Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230320061619.29520-2-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-kvm.c | 3 +-- tools/perf/util/hist.c | 5 +++++ tools/perf/util/kvm-stat.h | 40 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 46 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-kvm.c b/tools/perf/builtin-kvm.c index 4c205df5106f..1e1cb5a9d0a2 100644 --- a/tools/perf/builtin-kvm.c +++ b/tools/perf/builtin-kvm.c @@ -768,7 +768,6 @@ static void kvm_he_free(void *he) { struct kvm_event *kvm_ev; - free(((struct hist_entry *)he)->kvm_info); kvm_ev = container_of(he, struct kvm_event, he); free(kvm_ev); } @@ -788,7 +787,7 @@ static struct kvm_event *find_create_kvm_event(struct perf_kvm_stat *kvm, BUG_ON(key->key == INVALID_KEY); - ki = zalloc(sizeof(*ki)); + ki = kvm_info__new(); if (!ki) { pr_err("Failed to allocate kvm info\n"); return NULL; diff --git a/tools/perf/util/hist.c b/tools/perf/util/hist.c index 0c11f50abfec..b339ff863fe2 100644 --- a/tools/perf/util/hist.c +++ b/tools/perf/util/hist.c @@ -628,6 +628,8 @@ static struct hist_entry *hists__findnew_entry(struct hists *hists, block_info__zput(entry->block_info); + kvm_info__zput(entry->kvm_info); + /* If the map of an existing hist_entry has * become out-of-date due to an exec() or * similar, update it. Otherwise we will @@ -1324,6 +1326,9 @@ void hist_entry__delete(struct hist_entry *he) if (he->block_info) block_info__zput(he->block_info); + if (he->kvm_info) + kvm_info__zput(he->kvm_info); + zfree(&he->res_samples); zfree(&he->stat_acc); free_srcline(he->srcline); diff --git a/tools/perf/util/kvm-stat.h b/tools/perf/util/kvm-stat.h index bc6c8e38ef50..3e9ac754c3d1 100644 --- a/tools/perf/util/kvm-stat.h +++ b/tools/perf/util/kvm-stat.h @@ -10,6 +10,9 @@ #include "symbol.h" #include "record.h" +#include +#include + #define KVM_EVENT_NAME_LEN 40 struct evsel; @@ -25,6 +28,7 @@ struct event_key { struct kvm_info { char name[KVM_EVENT_NAME_LEN]; + refcount_t refcnt; }; struct kvm_event_stats { @@ -145,6 +149,42 @@ extern const char *vcpu_id_str; extern const char *kvm_exit_reason; extern const char *kvm_entry_trace; extern const char *kvm_exit_trace; + +static inline struct kvm_info *kvm_info__get(struct kvm_info *ki) +{ + if (ki) + refcount_inc(&ki->refcnt); + return ki; +} + +static inline void kvm_info__put(struct kvm_info *ki) +{ + if (ki && refcount_dec_and_test(&ki->refcnt)) + free(ki); +} + +static inline void __kvm_info__zput(struct kvm_info **ki) +{ + kvm_info__put(*ki); + *ki = NULL; +} + +#define kvm_info__zput(ki) __kvm_info__zput(&ki) + +static inline struct kvm_info *kvm_info__new(void) +{ + struct kvm_info *ki; + + ki = zalloc(sizeof(*ki)); + if (ki) + refcount_set(&ki->refcnt, 1); + + return ki; +} + +#else /* HAVE_KVM_STAT_SUPPORT */ +// We use this unconditionally in hists__findnew_entry() and hist_entry__delete() +#define kvm_info__zput(ki) do { } while (0) #endif /* HAVE_KVM_STAT_SUPPORT */ extern int kvm_add_default_arch_event(int *argc, const char **argv); -- cgit v1.2.3-58-ga151 From 51b02a964728115761acc5baa5e67c8d0a9bc222 Mon Sep 17 00:00:00 2001 From: Leo Yan Date: Mon, 20 Mar 2023 14:16:19 +0800 Subject: perf kvm: Delete histograms entries before exiting It's good not to release resources for a program when kernel cleans up memory space, this patch explicitly releases histograms entries with hists__delete_entries(). Committer notice: This helps with memory leak checkers, but may delay exiting a tool by doing needless linked list traversals freeing lots of objects. Signed-off-by: Leo Yan Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230320061619.29520-2-leo.yan@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-kvm.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'tools') diff --git a/tools/perf/builtin-kvm.c b/tools/perf/builtin-kvm.c index 1e1cb5a9d0a2..fb9dc0dc46f9 100644 --- a/tools/perf/builtin-kvm.c +++ b/tools/perf/builtin-kvm.c @@ -1528,6 +1528,8 @@ static int kvm_events_live_report(struct perf_kvm_stat *kvm) } out: + hists__delete_entries(&kvm_hists.hists); + if (kvm->timerfd >= 0) close(kvm->timerfd); @@ -1690,6 +1692,7 @@ static int kvm_events_report_vcpu(struct perf_kvm_stat *kvm) kvm_display(kvm); exit: + hists__delete_entries(&kvm_hists.hists); return ret; } -- cgit v1.2.3-58-ga151 From 636203670716c2a8d76791d6b8f4c4cd76e8c701 Mon Sep 17 00:00:00 2001 From: "Bernhard M. Wiedemann" Date: Tue, 21 Mar 2023 07:30:32 +0100 Subject: perf jevents: Sort list of input files Without this, pmu-events.c would be generated with variations in ordering depending on non-deterministic filesystem readdir order. I tested that pmu-events.c still has the same number of lines and that perf list output works. This patch was done while working on reproducible builds for openSUSE, but also solves issues in Debian [1] and other distributions. [1] https://tests.reproducible-builds.org/debian/rb-pkg/unstable/i386/linux.html Signed-off-by: Bernhard M. Wiedemann Cc: Ian Rogers Link: https://lore.kernel.org/r/20230321063032.19804-1-bwiedemann@suse.de Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/jevents.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index 533071a014d7..ca99b9cfe4ad 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -922,7 +922,7 @@ def main() -> None: def ftw(path: str, parents: Sequence[str], action: Callable[[Sequence[str], os.DirEntry], None]) -> None: """Replicate the directory/file walking behavior of C's file tree walk.""" - for item in os.scandir(path): + for item in sorted(os.scandir(path), key=lambda e: e.name): if _args.model != 'all' and item.is_dir(): # Check if the model matches one in _args.model. if len(parents) == _args.model.split(',')[0].count('/'): -- cgit v1.2.3-58-ga151 From 7effbd18e496a954540fb6319db0d87d28a70496 Mon Sep 17 00:00:00 2001 From: James Clark Date: Mon, 20 Mar 2023 11:45:59 +0000 Subject: perf vendor events arm64: Add N1 metrics Generated from the telemetry solution repo[1] with this command: ./generate.py /tools/perf/ --telemetry-files \ ../../data/pmu/cpu/neoverse/neoverse-n1.json Since this data source now includes the SPE events for N1, it has diverged from A76 which means the folder has to be split. The new data also uses more fine grained grouping, but this will be consistent for all future products. Long PublicDescriptions are now included even for common events because this can include product specific details. For non verbose mode the common BriefDescriptions remain the same. [1]: https://gitlab.arm.com/telemetry-solution/telemetry-solution Signed-off-by: James Clark Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: John Garry Cc: Leo Yan Cc: Mark Rutland Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Will Deacon Cc: linux-arm-kernel@lists.infradead.org Cc: renyu.zj@linux.alibaba.com Link: https://lore.kernel.org/r/20230320114601.524958-1-james.clark@arm.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/arm64/arm/cortex-a76-n1/branch.json | 10 - .../arch/arm64/arm/cortex-a76-n1/bus.json | 21 -- .../arch/arm64/arm/cortex-a76-n1/cache.json | 169 ---------------- .../arch/arm64/arm/cortex-a76-n1/exception.json | 48 ----- .../arch/arm64/arm/cortex-a76-n1/instruction.json | 91 --------- .../arch/arm64/arm/cortex-a76-n1/memory.json | 24 --- .../arch/arm64/arm/cortex-a76-n1/pipeline.json | 10 - .../arch/arm64/arm/cortex-a76/branch.json | 10 + .../pmu-events/arch/arm64/arm/cortex-a76/bus.json | 21 ++ .../arch/arm64/arm/cortex-a76/cache.json | 169 ++++++++++++++++ .../arch/arm64/arm/cortex-a76/exception.json | 48 +++++ .../arch/arm64/arm/cortex-a76/instruction.json | 91 +++++++++ .../arch/arm64/arm/cortex-a76/memory.json | 24 +++ .../arch/arm64/arm/cortex-a76/pipeline.json | 10 + .../pmu-events/arch/arm64/arm/neoverse-n1/bus.json | 18 ++ .../arch/arm64/arm/neoverse-n1/exception.json | 62 ++++++ .../arch/arm64/arm/neoverse-n1/general.json | 6 + .../arch/arm64/arm/neoverse-n1/l1d_cache.json | 50 +++++ .../arch/arm64/arm/neoverse-n1/l1i_cache.json | 10 + .../arch/arm64/arm/neoverse-n1/l2_cache.json | 46 +++++ .../arch/arm64/arm/neoverse-n1/l3_cache.json | 18 ++ .../arch/arm64/arm/neoverse-n1/ll_cache.json | 10 + .../arch/arm64/arm/neoverse-n1/memory.json | 22 +++ .../arch/arm64/arm/neoverse-n1/metrics.json | 219 +++++++++++++++++++++ .../arch/arm64/arm/neoverse-n1/retired.json | 26 +++ .../pmu-events/arch/arm64/arm/neoverse-n1/spe.json | 18 ++ .../arch/arm64/arm/neoverse-n1/spec_operation.json | 102 ++++++++++ .../arch/arm64/arm/neoverse-n1/stall.json | 10 + .../pmu-events/arch/arm64/arm/neoverse-n1/tlb.json | 66 +++++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 4 +- 30 files changed, 1058 insertions(+), 375 deletions(-) delete mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/branch.json delete mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/bus.json delete mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/cache.json delete mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/exception.json delete mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/instruction.json delete mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/memory.json delete mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/pipeline.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a76/branch.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a76/bus.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a76/cache.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a76/exception.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a76/instruction.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a76/memory.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a76/pipeline.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/bus.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/exception.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/general.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/l1d_cache.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/l1i_cache.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/l2_cache.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/l3_cache.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ll_cache.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/memory.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/metrics.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/retired.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/spe.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/spec_operation.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/stall.json create mode 100644 tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/tlb.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/branch.json deleted file mode 100644 index db68de188390..000000000000 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/branch.json +++ /dev/null @@ -1,10 +0,0 @@ -[ - { - "PublicDescription": "This event counts any predictable branch instruction which is mispredicted either due to dynamic misprediction or because the MMU is off and the branches are statically predicted not taken", - "ArchStdEvent": "BR_MIS_PRED" - }, - { - "PublicDescription": "This event counts all predictable branches.", - "ArchStdEvent": "BR_PRED" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/bus.json deleted file mode 100644 index e0875d3a685d..000000000000 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/bus.json +++ /dev/null @@ -1,21 +0,0 @@ -[ - { - "PublicDescription": "The number of core clock cycles", - "ArchStdEvent": "CPU_CYCLES", - "BriefDescription": "The number of core clock cycles." - }, - { - "PublicDescription": "This event counts for every beat of data transferred over the data channels between the core and the SCU. If both read and write data beats are transferred on a given cycle, this event is counted twice on that cycle. This event counts the sum of BUS_ACCESS_RD and BUS_ACCESS_WR.", - "ArchStdEvent": "BUS_ACCESS" - }, - { - "PublicDescription": "This event duplicates CPU_CYCLES.", - "ArchStdEvent": "BUS_CYCLES" - }, - { - "ArchStdEvent": "BUS_ACCESS_RD" - }, - { - "ArchStdEvent": "BUS_ACCESS_WR" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/cache.json deleted file mode 100644 index fc448c2d5ea4..000000000000 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/cache.json +++ /dev/null @@ -1,169 +0,0 @@ -[ - { - "PublicDescription": "This event counts any instruction fetch which misses in the cache.", - "ArchStdEvent": "L1I_CACHE_REFILL" - }, - { - "PublicDescription": "This event counts any refill of the instruction L1 TLB from the L2 TLB. This includes refills that result in a translation fault.", - "ArchStdEvent": "L1I_TLB_REFILL" - }, - { - "PublicDescription": "This event counts any load or store operation or page table walk access which causes data to be read from outside the L1, including accesses which do not allocate into L1.", - "ArchStdEvent": "L1D_CACHE_REFILL" - }, - { - "PublicDescription": "This event counts any load or store operation or page table walk access which looks up in the L1 data cache. In particular, any access which could count the L1D_CACHE_REFILL event causes this event to count.", - "ArchStdEvent": "L1D_CACHE" - }, - { - "PublicDescription": "This event counts any refill of the data L1 TLB from the L2 TLB. This includes refills that result in a translation fault.", - "ArchStdEvent": "L1D_TLB_REFILL" - }, - { - "PublicDescription": "Level 1 instruction cache access or Level 0 Macro-op cache access. This event counts any instruction fetch which accesses the L1 instruction cache or L0 Macro-op cache.", - "ArchStdEvent": "L1I_CACHE" - }, - { - "PublicDescription": "This event counts any write-back of data from the L1 data cache to L2 or L3. This counts both victim line evictions and snoops, including cache maintenance operations.", - "ArchStdEvent": "L1D_CACHE_WB" - }, - { - "PublicDescription": "This event counts any transaction from L1 which looks up in the L2 cache, and any write-back from the L1 to the L2. Snoops from outside the core and cache maintenance operations are not counted.", - "ArchStdEvent": "L2D_CACHE" - }, - { - "PublicDescription": "L2 data cache refill. This event counts any cacheable transaction from L1 which causes data to be read from outside the core. L2 refills caused by stashes into L2 should not be counted", - "ArchStdEvent": "L2D_CACHE_REFILL" - }, - { - "PublicDescription": "This event counts any write-back of data from the L2 cache to outside the core. This includes snoops to the L2 which return data, regardless of whether they cause an invalidation. Invalidations from the L2 which do not write data outside of the core and snoops which return data from the L1 are not counted", - "ArchStdEvent": "L2D_CACHE_WB" - }, - { - "PublicDescription": "This event counts any full cache line write into the L2 cache which does not cause a linefill, including write-backs from L1 to L2 and full-line writes which do not allocate into L1.", - "ArchStdEvent": "L2D_CACHE_ALLOCATE" - }, - { - "PublicDescription": "This event counts any load or store operation which accesses the data L1 TLB. If both a load and a store are executed on a cycle, this event counts twice. This event counts regardless of whether the MMU is enabled.", - "ArchStdEvent": "L1D_TLB", - "BriefDescription": "Level 1 data TLB access." - }, - { - "PublicDescription": "This event counts any instruction fetch which accesses the instruction L1 TLB.This event counts regardless of whether the MMU is enabled.", - "ArchStdEvent": "L1I_TLB", - "BriefDescription": "Level 1 instruction TLB access" - }, - { - "PublicDescription": "This event counts any full cache line write into the L3 cache which does not cause a linefill, including write-backs from L2 to L3 and full-line writes which do not allocate into L2", - "ArchStdEvent": "L3D_CACHE_ALLOCATE", - "BriefDescription": "Allocation without refill" - }, - { - "PublicDescription": "This event counts for any cacheable read transaction returning datafrom the SCU for which the data source was outside the cluster. Transactions such as ReadUnique are counted here as 'read' transactions, even though they can be generated by store instructions.", - "ArchStdEvent": "L3D_CACHE_REFILL", - "BriefDescription": "Attributable Level 3 unified cache refill." - }, - { - "PublicDescription": "This event counts for any cacheable read transaction returning datafrom the SCU, or for any cacheable write to the SCU.", - "ArchStdEvent": "L3D_CACHE", - "BriefDescription": "Attributable Level 3 unified cache access." - }, - { - "PublicDescription": "This event counts on anyrefill of the L2 TLB, caused by either an instruction or data access.This event does not count if the MMU is disabled.", - "ArchStdEvent": "L2D_TLB_REFILL", - "BriefDescription": "Attributable L2 data or unified TLB refill" - }, - { - "PublicDescription": "This event counts on any access to the L2 TLB (caused by a refill of any of the L1 TLBs). This event does not count if the MMU is disabled.", - "ArchStdEvent": "L2D_TLB" - }, - { - "PublicDescription": "This event counts on any data access which causes L2D_TLB_REFILL to count.", - "ArchStdEvent": "DTLB_WALK" - }, - { - "PublicDescription": "This event counts on any instruction access which causes L2D_TLB_REFILL to count.", - "ArchStdEvent": "ITLB_WALK" - }, - { - "ArchStdEvent": "LL_CACHE_RD" - }, - { - "ArchStdEvent": "LL_CACHE_MISS_RD" - }, - { - "ArchStdEvent": "L1D_CACHE_INVAL" - }, - { - "ArchStdEvent": "L1D_CACHE_RD" - }, - { - "ArchStdEvent": "L1D_CACHE_REFILL_INNER" - }, - { - "ArchStdEvent": "L1D_CACHE_REFILL_OUTER" - }, - { - "ArchStdEvent": "L1D_CACHE_REFILL_RD" - }, - { - "ArchStdEvent": "L1D_CACHE_REFILL_WR" - }, - { - "ArchStdEvent": "L1D_CACHE_WB_CLEAN" - }, - { - "ArchStdEvent": "L1D_CACHE_WB_VICTIM" - }, - { - "ArchStdEvent": "L1D_CACHE_WR" - }, - { - "ArchStdEvent": "L1D_TLB_RD" - }, - { - "ArchStdEvent": "L1D_TLB_REFILL_RD" - }, - { - "ArchStdEvent": "L1D_TLB_REFILL_WR" - }, - { - "ArchStdEvent": "L1D_TLB_WR" - }, - { - "ArchStdEvent": "L2D_CACHE_INVAL" - }, - { - "ArchStdEvent": "L2D_CACHE_RD" - }, - { - "ArchStdEvent": "L2D_CACHE_REFILL_RD" - }, - { - "ArchStdEvent": "L2D_CACHE_REFILL_WR" - }, - { - "ArchStdEvent": "L2D_CACHE_WB_CLEAN" - }, - { - "ArchStdEvent": "L2D_CACHE_WB_VICTIM" - }, - { - "ArchStdEvent": "L2D_CACHE_WR" - }, - { - "ArchStdEvent": "L2D_TLB_RD" - }, - { - "ArchStdEvent": "L2D_TLB_REFILL_RD" - }, - { - "ArchStdEvent": "L2D_TLB_REFILL_WR" - }, - { - "ArchStdEvent": "L2D_TLB_WR" - }, - { - "ArchStdEvent": "L3D_CACHE_RD" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/exception.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/exception.json deleted file mode 100644 index ce942324ee60..000000000000 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/exception.json +++ /dev/null @@ -1,48 +0,0 @@ -[ - { - "ArchStdEvent": "EXC_TAKEN" - }, - { - "PublicDescription": "This event counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs", - "ArchStdEvent": "MEMORY_ERROR" - }, - { - "ArchStdEvent": "EXC_DABORT" - }, - { - "ArchStdEvent": "EXC_FIQ" - }, - { - "ArchStdEvent": "EXC_HVC" - }, - { - "ArchStdEvent": "EXC_IRQ" - }, - { - "ArchStdEvent": "EXC_PABORT" - }, - { - "ArchStdEvent": "EXC_SMC" - }, - { - "ArchStdEvent": "EXC_SVC" - }, - { - "ArchStdEvent": "EXC_TRAP_DABORT" - }, - { - "ArchStdEvent": "EXC_TRAP_FIQ" - }, - { - "ArchStdEvent": "EXC_TRAP_IRQ" - }, - { - "ArchStdEvent": "EXC_TRAP_OTHER" - }, - { - "ArchStdEvent": "EXC_TRAP_PABORT" - }, - { - "ArchStdEvent": "EXC_UNDEF" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/instruction.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/instruction.json deleted file mode 100644 index b0b439a36ae9..000000000000 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/instruction.json +++ /dev/null @@ -1,91 +0,0 @@ -[ - { - "ArchStdEvent": "SW_INCR" - }, - { - "PublicDescription": "This event counts all retired instructions, including those that fail their condition check.", - "ArchStdEvent": "INST_RETIRED" - }, - { - "ArchStdEvent": "EXC_RETURN" - }, - { - "PublicDescription": "This event only counts writes to CONTEXTIDR in AArch32 state, and via the CONTEXTIDR_EL1 mnemonic in AArch64 state.", - "ArchStdEvent": "CID_WRITE_RETIRED" - }, - { - "ArchStdEvent": "INST_SPEC" - }, - { - "PublicDescription": "This event only counts writes to TTBR0/TTBR1 in AArch32 state and TTBR0_EL1/TTBR1_EL1 in AArch64 state.", - "ArchStdEvent": "TTBR_WRITE_RETIRED" - }, - { - "PublicDescription": "This event counts all branches, taken or not. This excludes exception entries, debug entries and CCFAIL branches.", - "ArchStdEvent": "BR_RETIRED" - }, - { - "PublicDescription": "This event counts any branch counted by BR_RETIRED which is not correctly predicted and causes a pipeline flush.", - "ArchStdEvent": "BR_MIS_PRED_RETIRED" - }, - { - "ArchStdEvent": "ASE_SPEC" - }, - { - "ArchStdEvent": "BR_IMMED_SPEC" - }, - { - "ArchStdEvent": "BR_INDIRECT_SPEC" - }, - { - "ArchStdEvent": "BR_RETURN_SPEC" - }, - { - "ArchStdEvent": "CRYPTO_SPEC" - }, - { - "ArchStdEvent": "DMB_SPEC" - }, - { - "ArchStdEvent": "DP_SPEC" - }, - { - "ArchStdEvent": "DSB_SPEC" - }, - { - "ArchStdEvent": "ISB_SPEC" - }, - { - "ArchStdEvent": "LDREX_SPEC" - }, - { - "ArchStdEvent": "LDST_SPEC" - }, - { - "ArchStdEvent": "LD_SPEC" - }, - { - "ArchStdEvent": "PC_WRITE_SPEC" - }, - { - "ArchStdEvent": "RC_LD_SPEC" - }, - { - "ArchStdEvent": "RC_ST_SPEC" - }, - { - "ArchStdEvent": "STREX_FAIL_SPEC" - }, - { - "ArchStdEvent": "STREX_PASS_SPEC" - }, - { - "ArchStdEvent": "STREX_SPEC" - }, - { - "ArchStdEvent": "ST_SPEC" - }, - { - "ArchStdEvent": "VFP_SPEC" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/memory.json deleted file mode 100644 index 5bed2514b245..000000000000 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/memory.json +++ /dev/null @@ -1,24 +0,0 @@ -[ - { - "PublicDescription": "This event counts memory accesses due to load or store instructions. This event counts the sum of MEM_ACCESS_RD and MEM_ACCESS_WR.", - "ArchStdEvent": "MEM_ACCESS" - }, - { - "ArchStdEvent": "REMOTE_ACCESS" - }, - { - "ArchStdEvent": "MEM_ACCESS_RD" - }, - { - "ArchStdEvent": "MEM_ACCESS_WR" - }, - { - "ArchStdEvent": "UNALIGNED_LD_SPEC" - }, - { - "ArchStdEvent": "UNALIGNED_ST_SPEC" - }, - { - "ArchStdEvent": "UNALIGNED_LDST_SPEC" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/pipeline.json deleted file mode 100644 index b4e96551d51a..000000000000 --- a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/pipeline.json +++ /dev/null @@ -1,10 +0,0 @@ -[ - { - "PublicDescription": "The counter counts on any cycle when there are no fetched instructions available to dispatch.", - "ArchStdEvent": "STALL_FRONTEND" - }, - { - "PublicDescription": "The counter counts on any cycle fetched instructions are not dispatched due to resource constraints.", - "ArchStdEvent": "STALL_BACKEND" - } -] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/branch.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/branch.json new file mode 100644 index 000000000000..db68de188390 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/branch.json @@ -0,0 +1,10 @@ +[ + { + "PublicDescription": "This event counts any predictable branch instruction which is mispredicted either due to dynamic misprediction or because the MMU is off and the branches are statically predicted not taken", + "ArchStdEvent": "BR_MIS_PRED" + }, + { + "PublicDescription": "This event counts all predictable branches.", + "ArchStdEvent": "BR_PRED" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/bus.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/bus.json new file mode 100644 index 000000000000..e0875d3a685d --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/bus.json @@ -0,0 +1,21 @@ +[ + { + "PublicDescription": "The number of core clock cycles", + "ArchStdEvent": "CPU_CYCLES", + "BriefDescription": "The number of core clock cycles." + }, + { + "PublicDescription": "This event counts for every beat of data transferred over the data channels between the core and the SCU. If both read and write data beats are transferred on a given cycle, this event is counted twice on that cycle. This event counts the sum of BUS_ACCESS_RD and BUS_ACCESS_WR.", + "ArchStdEvent": "BUS_ACCESS" + }, + { + "PublicDescription": "This event duplicates CPU_CYCLES.", + "ArchStdEvent": "BUS_CYCLES" + }, + { + "ArchStdEvent": "BUS_ACCESS_RD" + }, + { + "ArchStdEvent": "BUS_ACCESS_WR" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/cache.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/cache.json new file mode 100644 index 000000000000..fc448c2d5ea4 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/cache.json @@ -0,0 +1,169 @@ +[ + { + "PublicDescription": "This event counts any instruction fetch which misses in the cache.", + "ArchStdEvent": "L1I_CACHE_REFILL" + }, + { + "PublicDescription": "This event counts any refill of the instruction L1 TLB from the L2 TLB. This includes refills that result in a translation fault.", + "ArchStdEvent": "L1I_TLB_REFILL" + }, + { + "PublicDescription": "This event counts any load or store operation or page table walk access which causes data to be read from outside the L1, including accesses which do not allocate into L1.", + "ArchStdEvent": "L1D_CACHE_REFILL" + }, + { + "PublicDescription": "This event counts any load or store operation or page table walk access which looks up in the L1 data cache. In particular, any access which could count the L1D_CACHE_REFILL event causes this event to count.", + "ArchStdEvent": "L1D_CACHE" + }, + { + "PublicDescription": "This event counts any refill of the data L1 TLB from the L2 TLB. This includes refills that result in a translation fault.", + "ArchStdEvent": "L1D_TLB_REFILL" + }, + { + "PublicDescription": "Level 1 instruction cache access or Level 0 Macro-op cache access. This event counts any instruction fetch which accesses the L1 instruction cache or L0 Macro-op cache.", + "ArchStdEvent": "L1I_CACHE" + }, + { + "PublicDescription": "This event counts any write-back of data from the L1 data cache to L2 or L3. This counts both victim line evictions and snoops, including cache maintenance operations.", + "ArchStdEvent": "L1D_CACHE_WB" + }, + { + "PublicDescription": "This event counts any transaction from L1 which looks up in the L2 cache, and any write-back from the L1 to the L2. Snoops from outside the core and cache maintenance operations are not counted.", + "ArchStdEvent": "L2D_CACHE" + }, + { + "PublicDescription": "L2 data cache refill. This event counts any cacheable transaction from L1 which causes data to be read from outside the core. L2 refills caused by stashes into L2 should not be counted", + "ArchStdEvent": "L2D_CACHE_REFILL" + }, + { + "PublicDescription": "This event counts any write-back of data from the L2 cache to outside the core. This includes snoops to the L2 which return data, regardless of whether they cause an invalidation. Invalidations from the L2 which do not write data outside of the core and snoops which return data from the L1 are not counted", + "ArchStdEvent": "L2D_CACHE_WB" + }, + { + "PublicDescription": "This event counts any full cache line write into the L2 cache which does not cause a linefill, including write-backs from L1 to L2 and full-line writes which do not allocate into L1.", + "ArchStdEvent": "L2D_CACHE_ALLOCATE" + }, + { + "PublicDescription": "This event counts any load or store operation which accesses the data L1 TLB. If both a load and a store are executed on a cycle, this event counts twice. This event counts regardless of whether the MMU is enabled.", + "ArchStdEvent": "L1D_TLB", + "BriefDescription": "Level 1 data TLB access." + }, + { + "PublicDescription": "This event counts any instruction fetch which accesses the instruction L1 TLB.This event counts regardless of whether the MMU is enabled.", + "ArchStdEvent": "L1I_TLB", + "BriefDescription": "Level 1 instruction TLB access" + }, + { + "PublicDescription": "This event counts any full cache line write into the L3 cache which does not cause a linefill, including write-backs from L2 to L3 and full-line writes which do not allocate into L2", + "ArchStdEvent": "L3D_CACHE_ALLOCATE", + "BriefDescription": "Allocation without refill" + }, + { + "PublicDescription": "This event counts for any cacheable read transaction returning datafrom the SCU for which the data source was outside the cluster. Transactions such as ReadUnique are counted here as 'read' transactions, even though they can be generated by store instructions.", + "ArchStdEvent": "L3D_CACHE_REFILL", + "BriefDescription": "Attributable Level 3 unified cache refill." + }, + { + "PublicDescription": "This event counts for any cacheable read transaction returning datafrom the SCU, or for any cacheable write to the SCU.", + "ArchStdEvent": "L3D_CACHE", + "BriefDescription": "Attributable Level 3 unified cache access." + }, + { + "PublicDescription": "This event counts on anyrefill of the L2 TLB, caused by either an instruction or data access.This event does not count if the MMU is disabled.", + "ArchStdEvent": "L2D_TLB_REFILL", + "BriefDescription": "Attributable L2 data or unified TLB refill" + }, + { + "PublicDescription": "This event counts on any access to the L2 TLB (caused by a refill of any of the L1 TLBs). This event does not count if the MMU is disabled.", + "ArchStdEvent": "L2D_TLB" + }, + { + "PublicDescription": "This event counts on any data access which causes L2D_TLB_REFILL to count.", + "ArchStdEvent": "DTLB_WALK" + }, + { + "PublicDescription": "This event counts on any instruction access which causes L2D_TLB_REFILL to count.", + "ArchStdEvent": "ITLB_WALK" + }, + { + "ArchStdEvent": "LL_CACHE_RD" + }, + { + "ArchStdEvent": "LL_CACHE_MISS_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_INVAL" + }, + { + "ArchStdEvent": "L1D_CACHE_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_INNER" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L1D_CACHE_WB_CLEAN" + }, + { + "ArchStdEvent": "L1D_CACHE_WB_VICTIM" + }, + { + "ArchStdEvent": "L1D_CACHE_WR" + }, + { + "ArchStdEvent": "L1D_TLB_RD" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_RD" + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_WR" + }, + { + "ArchStdEvent": "L1D_TLB_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_INVAL" + }, + { + "ArchStdEvent": "L2D_CACHE_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_RD" + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_WR" + }, + { + "ArchStdEvent": "L2D_CACHE_WB_CLEAN" + }, + { + "ArchStdEvent": "L2D_CACHE_WB_VICTIM" + }, + { + "ArchStdEvent": "L2D_CACHE_WR" + }, + { + "ArchStdEvent": "L2D_TLB_RD" + }, + { + "ArchStdEvent": "L2D_TLB_REFILL_RD" + }, + { + "ArchStdEvent": "L2D_TLB_REFILL_WR" + }, + { + "ArchStdEvent": "L2D_TLB_WR" + }, + { + "ArchStdEvent": "L3D_CACHE_RD" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/exception.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/exception.json new file mode 100644 index 000000000000..ce942324ee60 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/exception.json @@ -0,0 +1,48 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN" + }, + { + "PublicDescription": "This event counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs", + "ArchStdEvent": "MEMORY_ERROR" + }, + { + "ArchStdEvent": "EXC_DABORT" + }, + { + "ArchStdEvent": "EXC_FIQ" + }, + { + "ArchStdEvent": "EXC_HVC" + }, + { + "ArchStdEvent": "EXC_IRQ" + }, + { + "ArchStdEvent": "EXC_PABORT" + }, + { + "ArchStdEvent": "EXC_SMC" + }, + { + "ArchStdEvent": "EXC_SVC" + }, + { + "ArchStdEvent": "EXC_TRAP_DABORT" + }, + { + "ArchStdEvent": "EXC_TRAP_FIQ" + }, + { + "ArchStdEvent": "EXC_TRAP_IRQ" + }, + { + "ArchStdEvent": "EXC_TRAP_OTHER" + }, + { + "ArchStdEvent": "EXC_TRAP_PABORT" + }, + { + "ArchStdEvent": "EXC_UNDEF" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/instruction.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/instruction.json new file mode 100644 index 000000000000..b0b439a36ae9 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/instruction.json @@ -0,0 +1,91 @@ +[ + { + "ArchStdEvent": "SW_INCR" + }, + { + "PublicDescription": "This event counts all retired instructions, including those that fail their condition check.", + "ArchStdEvent": "INST_RETIRED" + }, + { + "ArchStdEvent": "EXC_RETURN" + }, + { + "PublicDescription": "This event only counts writes to CONTEXTIDR in AArch32 state, and via the CONTEXTIDR_EL1 mnemonic in AArch64 state.", + "ArchStdEvent": "CID_WRITE_RETIRED" + }, + { + "ArchStdEvent": "INST_SPEC" + }, + { + "PublicDescription": "This event only counts writes to TTBR0/TTBR1 in AArch32 state and TTBR0_EL1/TTBR1_EL1 in AArch64 state.", + "ArchStdEvent": "TTBR_WRITE_RETIRED" + }, + { + "PublicDescription": "This event counts all branches, taken or not. This excludes exception entries, debug entries and CCFAIL branches.", + "ArchStdEvent": "BR_RETIRED" + }, + { + "PublicDescription": "This event counts any branch counted by BR_RETIRED which is not correctly predicted and causes a pipeline flush.", + "ArchStdEvent": "BR_MIS_PRED_RETIRED" + }, + { + "ArchStdEvent": "ASE_SPEC" + }, + { + "ArchStdEvent": "BR_IMMED_SPEC" + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC" + }, + { + "ArchStdEvent": "BR_RETURN_SPEC" + }, + { + "ArchStdEvent": "CRYPTO_SPEC" + }, + { + "ArchStdEvent": "DMB_SPEC" + }, + { + "ArchStdEvent": "DP_SPEC" + }, + { + "ArchStdEvent": "DSB_SPEC" + }, + { + "ArchStdEvent": "ISB_SPEC" + }, + { + "ArchStdEvent": "LDREX_SPEC" + }, + { + "ArchStdEvent": "LDST_SPEC" + }, + { + "ArchStdEvent": "LD_SPEC" + }, + { + "ArchStdEvent": "PC_WRITE_SPEC" + }, + { + "ArchStdEvent": "RC_LD_SPEC" + }, + { + "ArchStdEvent": "RC_ST_SPEC" + }, + { + "ArchStdEvent": "STREX_FAIL_SPEC" + }, + { + "ArchStdEvent": "STREX_PASS_SPEC" + }, + { + "ArchStdEvent": "STREX_SPEC" + }, + { + "ArchStdEvent": "ST_SPEC" + }, + { + "ArchStdEvent": "VFP_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/memory.json new file mode 100644 index 000000000000..5bed2514b245 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/memory.json @@ -0,0 +1,24 @@ +[ + { + "PublicDescription": "This event counts memory accesses due to load or store instructions. This event counts the sum of MEM_ACCESS_RD and MEM_ACCESS_WR.", + "ArchStdEvent": "MEM_ACCESS" + }, + { + "ArchStdEvent": "REMOTE_ACCESS" + }, + { + "ArchStdEvent": "MEM_ACCESS_RD" + }, + { + "ArchStdEvent": "MEM_ACCESS_WR" + }, + { + "ArchStdEvent": "UNALIGNED_LD_SPEC" + }, + { + "ArchStdEvent": "UNALIGNED_ST_SPEC" + }, + { + "ArchStdEvent": "UNALIGNED_LDST_SPEC" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/pipeline.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/pipeline.json new file mode 100644 index 000000000000..b4e96551d51a --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/pipeline.json @@ -0,0 +1,10 @@ +[ + { + "PublicDescription": "The counter counts on any cycle when there are no fetched instructions available to dispatch.", + "ArchStdEvent": "STALL_FRONTEND" + }, + { + "PublicDescription": "The counter counts on any cycle fetched instructions are not dispatched due to resource constraints.", + "ArchStdEvent": "STALL_BACKEND" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/bus.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/bus.json new file mode 100644 index 000000000000..2e11a8c4a484 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/bus.json @@ -0,0 +1,18 @@ +[ + { + "ArchStdEvent": "BUS_ACCESS", + "PublicDescription": "Counts memory transactions issued by the CPU to the external bus, including snoop requests and snoop responses. Each beat of data is counted individually." + }, + { + "ArchStdEvent": "BUS_CYCLES", + "PublicDescription": "Counts bus cycles in the CPU. Bus cycles represent a clock cycle in which a transaction could be sent or received on the interface from the CPU to the external bus. Since that interface is driven at the same clock speed as the CPU, this event is a duplicate of CPU_CYCLES." + }, + { + "ArchStdEvent": "BUS_ACCESS_RD", + "PublicDescription": "Counts memory read transactions seen on the external bus. Each beat of data is counted individually." + }, + { + "ArchStdEvent": "BUS_ACCESS_WR", + "PublicDescription": "Counts memory write transactions seen on the external bus. Each beat of data is counted individually." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/exception.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/exception.json new file mode 100644 index 000000000000..4404b8e91690 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/exception.json @@ -0,0 +1,62 @@ +[ + { + "ArchStdEvent": "EXC_TAKEN", + "PublicDescription": "Counts any taken architecturally visible exceptions such as IRQ, FIQ, SError, and other synchronous exceptions. Exceptions are counted whether or not they are taken locally." + }, + { + "ArchStdEvent": "EXC_RETURN", + "PublicDescription": "Counts any architecturally executed exception return instructions. Eg: AArch64: ERET" + }, + { + "ArchStdEvent": "EXC_UNDEF", + "PublicDescription": "Counts the number of synchronous exceptions which are taken locally that are due to attempting to execute an instruction that is UNDEFINED. Attempting to execute instruction bit patterns that have not been allocated. Attempting to execute instructions when they are disabled. Attempting to execute instructions at an inappropriate Exception level. Attempting to execute an instruction when the value of PSTATE.IL is 1." + }, + { + "ArchStdEvent": "EXC_SVC", + "PublicDescription": "Counts SVC exceptions taken locally." + }, + { + "ArchStdEvent": "EXC_PABORT", + "PublicDescription": "Counts synchronous exceptions that are taken locally and caused by Instruction Aborts." + }, + { + "ArchStdEvent": "EXC_DABORT", + "PublicDescription": "Counts exceptions that are taken locally and are caused by data aborts or SErrors. Conditions that could cause those exceptions are attempting to read or write memory where the MMU generates a fault, attempting to read or write memory with a misaligned address, interrupts from the nSEI inputs and internally generated SErrors." + }, + { + "ArchStdEvent": "EXC_IRQ", + "PublicDescription": "Counts IRQ exceptions including the virtual IRQs that are taken locally." + }, + { + "ArchStdEvent": "EXC_FIQ", + "PublicDescription": "Counts FIQ exceptions including the virtual FIQs that are taken locally." + }, + { + "ArchStdEvent": "EXC_SMC", + "PublicDescription": "Counts SMC exceptions take to EL3." + }, + { + "ArchStdEvent": "EXC_HVC", + "PublicDescription": "Counts HVC exceptions taken to EL2." + }, + { + "ArchStdEvent": "EXC_TRAP_PABORT", + "PublicDescription": "Counts exceptions which are traps not taken locally and are caused by Instruction Aborts. For example, attempting to execute an instruction with a misaligned PC." + }, + { + "ArchStdEvent": "EXC_TRAP_DABORT", + "PublicDescription": "Counts exceptions which are traps not taken locally and are caused by Data Aborts or SError interrupts. Conditions that could cause those exceptions are:\n\n1. Attempting to read or write memory where the MMU generates a fault,\n2. Attempting to read or write memory with a misaligned address,\n3. Interrupts from the SEI input.\n4. internally generated SErrors." + }, + { + "ArchStdEvent": "EXC_TRAP_OTHER", + "PublicDescription": "Counts the number of synchronous trap exceptions which are not taken locally and are not SVC, SMC, HVC, data aborts, Instruction Aborts, or interrupts." + }, + { + "ArchStdEvent": "EXC_TRAP_IRQ", + "PublicDescription": "Counts IRQ exceptions including the virtual IRQs that are not taken locally." + }, + { + "ArchStdEvent": "EXC_TRAP_FIQ", + "PublicDescription": "Counts FIQs which are not taken locally but taken from EL0, EL1,\n or EL2 to EL3 (which would be the normal behavior for FIQs when not executing\n in EL3)." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/general.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/general.json new file mode 100644 index 000000000000..20fada95ef97 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/general.json @@ -0,0 +1,6 @@ +[ + { + "ArchStdEvent": "CPU_CYCLES", + "PublicDescription": "Counts CPU clock cycles (not timer cycles). The clock measured by this event is defined as the physical clock driving the CPU logic." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/l1d_cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/l1d_cache.json new file mode 100644 index 000000000000..6cd0b3ba5010 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/l1d_cache.json @@ -0,0 +1,50 @@ +[ + { + "ArchStdEvent": "L1D_CACHE_REFILL", + "PublicDescription": "Counts level 1 data cache refills caused by speculatively executed load or store operations that missed in the level 1 data cache. This event only counts one event per cache line. This event does not count cache line allocations from preload instructions or from hardware cache prefetching." + }, + { + "ArchStdEvent": "L1D_CACHE", + "PublicDescription": "Counts level 1 data cache accesses from any load/store operations. Atomic operations that resolve in the CPUs caches (near atomic operations) counts as both a write access and read access. Each access to a cache line is counted including the multiple accesses caused by single instructions such as LDM or STM. Each access to other level 1 data or unified memory structures, for example refill buffers, write buffers, and write-back buffers, are also counted." + }, + { + "ArchStdEvent": "L1D_CACHE_WB", + "PublicDescription": "Counts write-backs of dirty data from the L1 data cache to the L2 cache. This occurs when either a dirty cache line is evicted from L1 data cache and allocated in the L2 cache or dirty data is written to the L2 and possibly to the next level of cache. This event counts both victim cache line evictions and cache write-backs from snoops or cache maintenance operations. The following cache operations are not counted:\n\n1. Invalidations which do not result in data being transferred out of the L1 (such as evictions of clean data),\n2. Full line writes which write to L2 without writing L1, such as write streaming mode." + }, + { + "ArchStdEvent": "L1D_CACHE_RD", + "PublicDescription": "Counts level 1 data cache accesses from any load operation. Atomic load operations that resolve in the CPUs caches counts as both a write access and read access." + }, + { + "ArchStdEvent": "L1D_CACHE_WR", + "PublicDescription": "Counts level 1 data cache accesses generated by store operations. This event also counts accesses caused by a DC ZVA (data cache zero, specified by virtual address) instruction. Near atomic operations that resolve in the CPUs caches count as a write access and read access." + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_RD", + "PublicDescription": "Counts level 1 data cache refills caused by speculatively executed load instructions where the memory read operation misses in the level 1 data cache. This event only counts one event per cache line." + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_WR", + "PublicDescription": "Counts level 1 data cache refills caused by speculatively executed store instructions where the memory write operation misses in the level 1 data cache. This event only counts one event per cache line." + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_INNER", + "PublicDescription": "Counts level 1 data cache refills where the cache line data came from caches inside the immediate cluster of the core." + }, + { + "ArchStdEvent": "L1D_CACHE_REFILL_OUTER", + "PublicDescription": "Counts level 1 data cache refills for which the cache line data came from outside the immediate cluster of the core, like an SLC in the system interconnect or DRAM." + }, + { + "ArchStdEvent": "L1D_CACHE_WB_VICTIM", + "PublicDescription": "Counts dirty cache line evictions from the level 1 data cache caused by a new cache line allocation. This event does not count evictions caused by cache maintenance operations." + }, + { + "ArchStdEvent": "L1D_CACHE_WB_CLEAN", + "PublicDescription": "Counts write-backs from the level 1 data cache that are a result of a coherency operation made by another CPU. Event count includes cache maintenance operations." + }, + { + "ArchStdEvent": "L1D_CACHE_INVAL", + "PublicDescription": "Counts each explicit invalidation of a cache line in the level 1 data cache caused by:\n\n- Cache Maintenance Operations (CMO) that operate by a virtual address.\n- Broadcast cache coherency operations from another CPU in the system.\n\nThis event does not count for the following conditions:\n\n1. A cache refill invalidates a cache line.\n2. A CMO which is executed on that CPU and invalidates a cache line specified by set/way.\n\nNote that CMOs that operate by set/way cannot be broadcast from one CPU to another." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/l1i_cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/l1i_cache.json new file mode 100644 index 000000000000..e719b6e7fa77 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/l1i_cache.json @@ -0,0 +1,10 @@ +[ + { + "ArchStdEvent": "L1I_CACHE_REFILL", + "PublicDescription": "Counts cache line refills in the level 1 instruction cache caused by a missed instruction fetch. Instruction fetches may include accessing multiple instructions, but the single cache line allocation is counted once." + }, + { + "ArchStdEvent": "L1I_CACHE", + "PublicDescription": "Counts instruction fetches which access the level 1 instruction cache. Instruction cache accesses caused by cache maintenance operations are not counted." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/l2_cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/l2_cache.json new file mode 100644 index 000000000000..2f6099889de1 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/l2_cache.json @@ -0,0 +1,46 @@ +[ + { + "ArchStdEvent": "L2D_CACHE", + "PublicDescription": "Counts level 2 cache accesses. level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the first level caches or translation resolutions due to accesses. This event also counts write back of dirty data from level 1 data cache to the L2 cache." + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL", + "PublicDescription": "Counts cache line refills into the level 2 cache. level 2 cache is a unified cache for data and instruction accesses. Accesses are for misses in the level 1 caches or translation resolutions due to accesses." + }, + { + "ArchStdEvent": "L2D_CACHE_WB", + "PublicDescription": "Counts write-backs of data from the L2 cache to outside the CPU. This includes snoops to the L2 (from other CPUs) which return data even if the snoops cause an invalidation. L2 cache line invalidations which do not write data outside the CPU and snoops which return data from an L1 cache are not counted. Data would not be written outside the cache when invalidating a clean cache line." + }, + { + "ArchStdEvent": "L2D_CACHE_ALLOCATE", + "PublicDescription": "TBD" + }, + { + "ArchStdEvent": "L2D_CACHE_RD", + "PublicDescription": "Counts level 2 cache accesses due to memory read operations. level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due to accesses." + }, + { + "ArchStdEvent": "L2D_CACHE_WR", + "PublicDescription": "Counts level 2 cache accesses due to memory write operations. level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due to accesses." + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_RD", + "PublicDescription": "Counts refills for memory accesses due to memory read operation counted by L2D_CACHE_RD. level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due to accesses." + }, + { + "ArchStdEvent": "L2D_CACHE_REFILL_WR", + "PublicDescription": "Counts refills for memory accesses due to memory write operation counted by L2D_CACHE_WR. level 2 cache is a unified cache for data and instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due to accesses." + }, + { + "ArchStdEvent": "L2D_CACHE_WB_VICTIM", + "PublicDescription": "Counts evictions from the level 2 cache because of a line being allocated into the L2 cache." + }, + { + "ArchStdEvent": "L2D_CACHE_WB_CLEAN", + "PublicDescription": "Counts write-backs from the level 2 cache that are a result of either:\n\n1. Cache maintenance operations,\n\n2. Snoop responses or,\n\n3. Direct cache transfers to another CPU due to a forwarding snoop request." + }, + { + "ArchStdEvent": "L2D_CACHE_INVAL", + "PublicDescription": "Counts each explicit invalidation of a cache line in the level 2 cache by cache maintenance operations that operate by a virtual address, or by external coherency operations. This event does not count if either:\n\n1. A cache refill invalidates a cache line or,\n2. A Cache Maintenance Operation (CMO), which invalidates a cache line specified by set/way, is executed on that CPU.\n\nCMOs that operate by set/way cannot be broadcast from one CPU to another." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/l3_cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/l3_cache.json new file mode 100644 index 000000000000..f93e0c9f309a --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/l3_cache.json @@ -0,0 +1,18 @@ +[ + { + "ArchStdEvent": "L3D_CACHE_ALLOCATE", + "PublicDescription": "Counts level 3 cache line allocates that do not fetch data from outside the level 3 data or unified cache. For example, allocates due to streaming stores." + }, + { + "ArchStdEvent": "L3D_CACHE_REFILL", + "PublicDescription": "Counts level 3 accesses that receive data from outside the L3 cache." + }, + { + "ArchStdEvent": "L3D_CACHE", + "PublicDescription": "Counts level 3 cache accesses. level 3 cache is a unified cache for data and instruction accesses. Accesses are for misses in the lower level caches or translation resolutions due to accesses." + }, + { + "ArchStdEvent": "L3D_CACHE_RD", + "PublicDescription": "TBD" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ll_cache.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ll_cache.json new file mode 100644 index 000000000000..bb712d57d58a --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ll_cache.json @@ -0,0 +1,10 @@ +[ + { + "ArchStdEvent": "LL_CACHE_RD", + "PublicDescription": "Counts read transactions that were returned from outside the core cluster. This event counts when the system register CPUECTLR.EXTLLC bit is set. This event counts read transactions returned from outside the core if those transactions are either hit in the system level cache or missed in the SLC and are returned from any other external sources." + }, + { + "ArchStdEvent": "LL_CACHE_MISS_RD", + "PublicDescription": "Counts read transactions that were returned from outside the core cluster but missed in the system level cache. This event counts when the system register CPUECTLR.EXTLLC bit is set. This event counts read transactions returned from outside the core if those transactions are missed in the System level Cache. The data source of the transaction is indicated by a field in the CHI transaction returning to the CPU. This event does not count reads caused by cache maintenance operations." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/memory.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/memory.json new file mode 100644 index 000000000000..9041f6e0befb --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/memory.json @@ -0,0 +1,22 @@ +[ + { + "ArchStdEvent": "MEM_ACCESS", + "PublicDescription": "Counts memory accesses issued by the CPU load store unit, where those accesses are issued due to load or store operations. This event counts memory accesses no matter whether the data is received from any level of cache hierarchy or external memory. If memory accesses are broken up into smaller transactions than what were specified in the load or store instructions, then the event counts those smaller memory transactions." + }, + { + "ArchStdEvent": "MEMORY_ERROR", + "PublicDescription": "Counts any detected correctable or uncorrectable physical memory errors (ECC or parity) in protected CPUs RAMs. On the core, this event counts errors in the caches (including data and tag rams). Any detected memory error (from either a speculative and abandoned access, or an architecturally executed access) is counted. Note that errors are only detected when the actual protected memory is accessed by an operation." + }, + { + "ArchStdEvent": "REMOTE_ACCESS", + "PublicDescription": "Counts accesses to another chip, which is implemented as a different CMN mesh in the system. If the CHI bus response back to the core indicates that the data source is from another chip (mesh), then the counter is updated. If no data is returned, even if the system snoops another chip/mesh, then the counter is not updated." + }, + { + "ArchStdEvent": "MEM_ACCESS_RD", + "PublicDescription": "Counts memory accesses issued by the CPU due to load operations. The event counts any memory load access, no matter whether the data is received from any level of cache hierarchy or external memory. The event also counts atomic load operations. If memory accesses are broken up by the load/store unit into smaller transactions that are issued by the bus interface, then the event counts those smaller transactions." + }, + { + "ArchStdEvent": "MEM_ACCESS_WR", + "PublicDescription": "Counts memory accesses issued by the CPU due to store operations. The event counts any memory store access, no matter whether the data is located in any level of cache or external memory. The event also counts atomic load and store operations. If memory accesses are broken up by the load/store unit into smaller transactions that are issued by the bus interface, then the event counts those smaller transactions." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/metrics.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/metrics.json new file mode 100644 index 000000000000..dc0f8638f8f5 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/metrics.json @@ -0,0 +1,219 @@ +[ + { + "MetricName": "backend_stalled_cycles", + "MetricExpr": "((STALL_BACKEND / CPU_CYCLES) * 100)", + "BriefDescription": "This metric is the percentage of cycles that were stalled due to resource constraints in the backend unit of the processor.", + "MetricGroup": "Cycle_Accounting", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "branch_misprediction_ratio", + "MetricExpr": "(BR_MIS_PRED_RETIRED / BR_RETIRED)", + "BriefDescription": "This metric measures the ratio of branches mispredicted to the total number of branches architecturally executed. This gives an indication of the effectiveness of the branch prediction unit.", + "MetricGroup": "Miss_Ratio;Branch_Effectiveness", + "ScaleUnit": "1per branch" + }, + { + "MetricName": "branch_mpki", + "MetricExpr": "((BR_MIS_PRED_RETIRED / INST_RETIRED) * 1000)", + "BriefDescription": "This metric measures the number of branch mispredictions per thousand instructions executed.", + "MetricGroup": "MPKI;Branch_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "branch_percentage", + "MetricExpr": "(((BR_IMMED_SPEC + BR_INDIRECT_SPEC) / INST_SPEC) * 100)", + "BriefDescription": "This metric measures branch operations as a percentage of operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "crypto_percentage", + "MetricExpr": "((CRYPTO_SPEC / INST_SPEC) * 100)", + "BriefDescription": "This metric measures crypto operations as a percentage of operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "dtlb_mpki", + "MetricExpr": "((DTLB_WALK / INST_RETIRED) * 1000)", + "BriefDescription": "This metric measures the number of data TLB Walks per thousand instructions executed.", + "MetricGroup": "MPKI;DTLB_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "dtlb_walk_ratio", + "MetricExpr": "(DTLB_WALK / L1D_TLB)", + "BriefDescription": "This metric measures the ratio of instruction TLB Walks to the total number of data TLB accesses. This gives an indication of the effectiveness of the data TLB accesses.", + "MetricGroup": "Miss_Ratio;DTLB_Effectiveness", + "ScaleUnit": "1per TLB access" + }, + { + "MetricName": "frontend_stalled_cycles", + "MetricExpr": "((STALL_FRONTEND / CPU_CYCLES) * 100)", + "BriefDescription": "This metric is the percentage of cycles that were stalled due to resource constraints in the frontend unit of the processor.", + "MetricGroup": "Cycle_Accounting", + "ScaleUnit": "1percent of cycles" + }, + { + "MetricName": "integer_dp_percentage", + "MetricExpr": "((DP_SPEC / INST_SPEC) * 100)", + "BriefDescription": "This metric measures scalar integer operations as a percentage of operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "ipc", + "MetricExpr": "(INST_RETIRED / CPU_CYCLES)", + "BriefDescription": "This metric measures the number of instructions retired per cycle.", + "MetricGroup": "General", + "ScaleUnit": "1per cycle" + }, + { + "MetricName": "itlb_mpki", + "MetricExpr": "((ITLB_WALK / INST_RETIRED) * 1000)", + "BriefDescription": "This metric measures the number of instruction TLB Walks per thousand instructions executed.", + "MetricGroup": "MPKI;ITLB_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "itlb_walk_ratio", + "MetricExpr": "(ITLB_WALK / L1I_TLB)", + "BriefDescription": "This metric measures the ratio of instruction TLB Walks to the total number of instruction TLB accesses. This gives an indication of the effectiveness of the instruction TLB accesses.", + "MetricGroup": "Miss_Ratio;ITLB_Effectiveness", + "ScaleUnit": "1per TLB access" + }, + { + "MetricName": "l1d_cache_miss_ratio", + "MetricExpr": "(L1D_CACHE_REFILL / L1D_CACHE)", + "BriefDescription": "This metric measures the ratio of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gives an indication of the effectiveness of the level 1 data cache.", + "MetricGroup": "Miss_Ratio;L1D_Cache_Effectiveness", + "ScaleUnit": "1per cache access" + }, + { + "MetricName": "l1d_cache_mpki", + "MetricExpr": "((L1D_CACHE_REFILL / INST_RETIRED) * 1000)", + "BriefDescription": "This metric measures the number of level 1 data cache accesses missed per thousand instructions executed.", + "MetricGroup": "MPKI;L1D_Cache_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "l1d_tlb_miss_ratio", + "MetricExpr": "(L1D_TLB_REFILL / L1D_TLB)", + "BriefDescription": "This metric measures the ratio of level 1 data TLB accesses missed to the total number of level 1 data TLB accesses. This gives an indication of the effectiveness of the level 1 data TLB.", + "MetricGroup": "Miss_Ratio;DTLB_Effectiveness", + "ScaleUnit": "1per TLB access" + }, + { + "MetricName": "l1d_tlb_mpki", + "MetricExpr": "((L1D_TLB_REFILL / INST_RETIRED) * 1000)", + "BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed per thousand instructions executed.", + "MetricGroup": "MPKI;DTLB_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "l1i_cache_miss_ratio", + "MetricExpr": "(L1I_CACHE_REFILL / L1I_CACHE)", + "BriefDescription": "This metric measures the ratio of level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesses. This gives an indication of the effectiveness of the level 1 instruction cache.", + "MetricGroup": "Miss_Ratio;L1I_Cache_Effectiveness", + "ScaleUnit": "1per cache access" + }, + { + "MetricName": "l1i_cache_mpki", + "MetricExpr": "((L1I_CACHE_REFILL / INST_RETIRED) * 1000)", + "BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed per thousand instructions executed.", + "MetricGroup": "MPKI;L1I_Cache_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "l1i_tlb_miss_ratio", + "MetricExpr": "(L1I_TLB_REFILL / L1I_TLB)", + "BriefDescription": "This metric measures the ratio of level 1 instruction TLB accesses missed to the total number of level 1 instruction TLB accesses. This gives an indication of the effectiveness of the level 1 instruction TLB.", + "MetricGroup": "Miss_Ratio;ITLB_Effectiveness", + "ScaleUnit": "1per TLB access" + }, + { + "MetricName": "l1i_tlb_mpki", + "MetricExpr": "((L1I_TLB_REFILL / INST_RETIRED) * 1000)", + "BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed per thousand instructions executed.", + "MetricGroup": "MPKI;ITLB_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "l2_cache_miss_ratio", + "MetricExpr": "(L2D_CACHE_REFILL / L2D_CACHE)", + "BriefDescription": "This metric measures the ratio of level 2 cache accesses missed to the total number of level 2 cache accesses. This gives an indication of the effectiveness of the level 2 cache, which is a unified cache that stores both data and instruction. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a unified cache.", + "MetricGroup": "Miss_Ratio;L2_Cache_Effectiveness", + "ScaleUnit": "1per cache access" + }, + { + "MetricName": "l2_cache_mpki", + "MetricExpr": "((L2D_CACHE_REFILL / INST_RETIRED) * 1000)", + "BriefDescription": "This metric measures the number of level 2 unified cache accesses missed per thousand instructions executed. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a unified cache.", + "MetricGroup": "MPKI;L2_Cache_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "l2_tlb_miss_ratio", + "MetricExpr": "(L2D_TLB_REFILL / L2D_TLB)", + "BriefDescription": "This metric measures the ratio of level 2 unified TLB accesses missed to the total number of level 2 unified TLB accesses. This gives an indication of the effectiveness of the level 2 TLB.", + "MetricGroup": "Miss_Ratio;ITLB_Effectiveness;DTLB_Effectiveness", + "ScaleUnit": "1per TLB access" + }, + { + "MetricName": "l2_tlb_mpki", + "MetricExpr": "((L2D_TLB_REFILL / INST_RETIRED) * 1000)", + "BriefDescription": "This metric measures the number of level 2 unified TLB accesses missed per thousand instructions executed.", + "MetricGroup": "MPKI;ITLB_Effectiveness;DTLB_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "ll_cache_read_hit_ratio", + "MetricExpr": "((LL_CACHE_RD - LL_CACHE_MISS_RD) / LL_CACHE_RD)", + "BriefDescription": "This metric measures the ratio of last level cache read accesses hit in the cache to the total number of last level cache accesses. This gives an indication of the effectiveness of the last level cache for read traffic. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a system level cache.", + "MetricGroup": "LL_Cache_Effectiveness", + "ScaleUnit": "1per cache access" + }, + { + "MetricName": "ll_cache_read_miss_ratio", + "MetricExpr": "(LL_CACHE_MISS_RD / LL_CACHE_RD)", + "BriefDescription": "This metric measures the ratio of last level cache read accesses missed to the total number of last level cache accesses. This gives an indication of the effectiveness of the last level cache for read traffic. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a system level cache.", + "MetricGroup": "Miss_Ratio;LL_Cache_Effectiveness", + "ScaleUnit": "1per cache access" + }, + { + "MetricName": "ll_cache_read_mpki", + "MetricExpr": "((LL_CACHE_MISS_RD / INST_RETIRED) * 1000)", + "BriefDescription": "This metric measures the number of last level cache read accesses missed per thousand instructions executed.", + "MetricGroup": "MPKI;LL_Cache_Effectiveness", + "ScaleUnit": "1MPKI" + }, + { + "MetricName": "load_percentage", + "MetricExpr": "((LD_SPEC / INST_SPEC) * 100)", + "BriefDescription": "This metric measures load operations as a percentage of operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "scalar_fp_percentage", + "MetricExpr": "((VFP_SPEC / INST_SPEC) * 100)", + "BriefDescription": "This metric measures scalar floating point operations as a percentage of operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "simd_percentage", + "MetricExpr": "((ASE_SPEC / INST_SPEC) * 100)", + "BriefDescription": "This metric measures advanced SIMD operations as a percentage of total operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + }, + { + "MetricName": "store_percentage", + "MetricExpr": "((ST_SPEC / INST_SPEC) * 100)", + "BriefDescription": "This metric measures store operations as a percentage of operations speculatively executed.", + "MetricGroup": "Operation_Mix", + "ScaleUnit": "1percent of operations" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/retired.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/retired.json new file mode 100644 index 000000000000..0c7692ad5108 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/retired.json @@ -0,0 +1,26 @@ +[ + { + "ArchStdEvent": "SW_INCR", + "PublicDescription": "Counts software writes to the PMSWINC_EL0 (software PMU increment) register. The PMSWINC_EL0 register is a manually updated counter for use by application software.\n\nThis event could be used to measure any user program event, such as accesses to a particular data structure (by writing to the PMSWINC_EL0 register each time the data structure is accessed).\n\nTo use the PMSWINC_EL0 register and event, developers must insert instructions that write to the PMSWINC_EL0 register into the source code.\n\nSince the SW_INCR event records writes to the PMSWINC_EL0 register, there is no need to do a read/increment/write sequence to the PMSWINC_EL0 register." + }, + { + "ArchStdEvent": "INST_RETIRED", + "PublicDescription": "Counts instructions that have been architecturally executed." + }, + { + "ArchStdEvent": "CID_WRITE_RETIRED", + "PublicDescription": "Counts architecturally executed writes to the CONTEXTIDR register, which usually contain the kernel PID and can be output with hardware trace." + }, + { + "ArchStdEvent": "TTBR_WRITE_RETIRED", + "PublicDescription": "Counts architectural writes to TTBR0/1_EL1. If virtualization host extensions are enabled (by setting the HCR_EL2.E2H bit to 1), then accesses to TTBR0/1_EL1 that are redirected to TTBR0/1_EL2, or accesses to TTBR0/1_EL12, are counted. TTBRn registers are typically updated when the kernel is swapping user-space threads or applications." + }, + { + "ArchStdEvent": "BR_RETIRED", + "PublicDescription": "Counts architecturally executed branches, whether the branch is taken or not. Instructions that explicitly write to the PC are also counted." + }, + { + "ArchStdEvent": "BR_MIS_PRED_RETIRED", + "PublicDescription": "Counts branches counted by BR_RETIRED which were mispredicted and caused a pipeline flush." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/spe.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/spe.json new file mode 100644 index 000000000000..5de8b0f3a440 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/spe.json @@ -0,0 +1,18 @@ +[ + { + "ArchStdEvent": "SAMPLE_POP", + "PublicDescription": "Counts statistical profiling sample population, the count of all operations that could be sampled but may or may not be chosen for sampling." + }, + { + "ArchStdEvent": "SAMPLE_FEED", + "PublicDescription": "Counts statistical profiling samples taken for sampling." + }, + { + "ArchStdEvent": "SAMPLE_FILTRATE", + "PublicDescription": "Counts statistical profiling samples taken which are not removed by filtering." + }, + { + "ArchStdEvent": "SAMPLE_COLLISION", + "PublicDescription": "Counts statistical profiling samples that have collided with a previous sample and so therefore not taken." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/spec_operation.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/spec_operation.json new file mode 100644 index 000000000000..be8c0667f1d9 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/spec_operation.json @@ -0,0 +1,102 @@ +[ + { + "ArchStdEvent": "BR_MIS_PRED", + "PublicDescription": "Counts branches which are speculatively executed and mispredicted." + }, + { + "ArchStdEvent": "BR_PRED", + "PublicDescription": "Counts branches speculatively executed and were predicted right." + }, + { + "ArchStdEvent": "INST_SPEC", + "PublicDescription": "Counts operations that have been speculatively executed." + }, + { + "ArchStdEvent": "UNALIGNED_LD_SPEC", + "PublicDescription": "Counts unaligned memory read operations issued by the CPU. This event counts unaligned accesses (as defined by the actual instruction), even if they are subsequently issued as multiple aligned accesses. The event does not count preload operations (PLD, PLI)." + }, + { + "ArchStdEvent": "UNALIGNED_ST_SPEC", + "PublicDescription": "Counts unaligned memory write operations issued by the CPU. This event counts unaligned accesses (as defined by the actual instruction), even if they are subsequently issued as multiple aligned accesses." + }, + { + "ArchStdEvent": "UNALIGNED_LDST_SPEC", + "PublicDescription": "Counts unaligned memory operations issued by the CPU. This event counts unaligned accesses (as defined by the actual instruction), even if they are subsequently issued as multiple aligned accesses." + }, + { + "ArchStdEvent": "LDREX_SPEC", + "PublicDescription": "Counts Load-Exclusive operations that have been speculatively executed. Eg: LDREX, LDX" + }, + { + "ArchStdEvent": "STREX_PASS_SPEC", + "PublicDescription": "Counts store-exclusive operations that have been speculatively executed and have successfully completed the store operation." + }, + { + "ArchStdEvent": "STREX_FAIL_SPEC", + "PublicDescription": "Counts store-exclusive operations that have been speculatively executed and have not successfully completed the store operation." + }, + { + "ArchStdEvent": "STREX_SPEC", + "PublicDescription": "Counts store-exclusive operations that have been speculatively executed." + }, + { + "ArchStdEvent": "LD_SPEC", + "PublicDescription": "Counts speculatively executed load operations including Single Instruction Multiple Data (SIMD) load operations." + }, + { + "ArchStdEvent": "ST_SPEC", + "PublicDescription": "Counts speculatively executed store operations including Single Instruction Multiple Data (SIMD) store operations." + }, + { + "ArchStdEvent": "DP_SPEC", + "PublicDescription": "Counts speculatively executed logical or arithmetic instructions such as MOV/MVN operations." + }, + { + "ArchStdEvent": "ASE_SPEC", + "PublicDescription": "Counts speculatively executed Advanced SIMD operations excluding load, store and move micro-operations that move data to or from SIMD (vector) registers." + }, + { + "ArchStdEvent": "VFP_SPEC", + "PublicDescription": "Counts speculatively executed floating point operations. This event does not count operations that move data to or from floating point (vector) registers." + }, + { + "ArchStdEvent": "PC_WRITE_SPEC", + "PublicDescription": "Counts speculatively executed operations which cause software changes of the PC. Those operations include all taken branch operations." + }, + { + "ArchStdEvent": "CRYPTO_SPEC", + "PublicDescription": "Counts speculatively executed cryptographic operations except for PMULL and VMULL operations." + }, + { + "ArchStdEvent": "BR_IMMED_SPEC", + "PublicDescription": "Counts immediate branch operations which are speculatively executed." + }, + { + "ArchStdEvent": "BR_RETURN_SPEC", + "PublicDescription": "Counts procedure return operations (RET) which are speculatively executed." + }, + { + "ArchStdEvent": "BR_INDIRECT_SPEC", + "PublicDescription": "Counts indirect branch operations including procedure returns, which are speculatively executed. This includes operations that force a software change of the PC, other than exception-generating operations. Eg: BR Xn, RET" + }, + { + "ArchStdEvent": "ISB_SPEC", + "PublicDescription": "Counts ISB operations that are executed." + }, + { + "ArchStdEvent": "DSB_SPEC", + "PublicDescription": "Counts DSB operations that are speculatively issued to Load/Store unit in the CPU." + }, + { + "ArchStdEvent": "DMB_SPEC", + "PublicDescription": "Counts DMB operations that are speculatively issued to the Load/Store unit in the CPU. This event does not count implied barriers from load acquire/store release operations." + }, + { + "ArchStdEvent": "RC_LD_SPEC", + "PublicDescription": "Counts any load acquire operations that are speculatively executed. Eg: LDAR, LDARH, LDARB" + }, + { + "ArchStdEvent": "RC_ST_SPEC", + "PublicDescription": "Counts any store release operations that are speculatively executed. Eg: STLR, STLRH, STLRB'" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/stall.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/stall.json new file mode 100644 index 000000000000..688afd8a4061 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/stall.json @@ -0,0 +1,10 @@ +[ + { + "ArchStdEvent": "STALL_FRONTEND", + "PublicDescription": "Counts cycles when frontend could not send any micro-operations to the rename stage because of frontend resource stalls caused by fetch memory latency or branch prediction flow stalls. All the frontend slots were empty during the cycle when this event counts." + }, + { + "ArchStdEvent": "STALL_BACKEND", + "PublicDescription": "Counts cycles whenever the rename unit is unable to send any micro-operations to the backend of the pipeline because of backend resource constraints. Backend resource constraints can include issue stage fullness, execution stage fullness, or other internal pipeline resource fullness. All the backend slots were empty during the cycle when this event counts." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/tlb.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/tlb.json new file mode 100644 index 000000000000..b550af1831f5 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/tlb.json @@ -0,0 +1,66 @@ +[ + { + "ArchStdEvent": "L1I_TLB_REFILL", + "PublicDescription": "Counts level 1 instruction TLB refills from any Instruction fetch. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB." + }, + { + "ArchStdEvent": "L1D_TLB_REFILL", + "PublicDescription": "Counts level 1 data TLB accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event counts for refills caused by preload instructions or hardware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in a translation table walk. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB. This event will not count on an access from an AT(address translation) instruction." + }, + { + "ArchStdEvent": "L1D_TLB", + "PublicDescription": "Counts level 1 data TLB accesses caused by any memory load or store operation. Note that load or store instructions can be broken up into multiple memory operations. This event does not count TLB maintenance operations." + }, + { + "ArchStdEvent": "L1I_TLB", + "PublicDescription": "Counts level 1 instruction TLB accesses, whether the access hits or misses in the TLB. This event counts both demand accesses and prefetch or preload generated accesses." + }, + { + "ArchStdEvent": "L2D_TLB_REFILL", + "PublicDescription": "Counts level 2 TLB refills caused by memory operations from both data and instruction fetch, except for those caused by TLB maintenance operations and hardware prefetches." + }, + { + "ArchStdEvent": "L2D_TLB", + "PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operations." + }, + { + "ArchStdEvent": "DTLB_WALK", + "PublicDescription": "Counts data memory translation table walks caused by a miss in the L2 TLB driven by a memory access. Note that partial translations that also cause a table walk are counted. This event does not count table walks caused by TLB maintenance operations." + }, + { + "ArchStdEvent": "ITLB_WALK", + "PublicDescription": "Counts instruction memory translation table walks caused by a miss in the L2 TLB driven by a memory access. Partial translations that also cause a table walk are counted. This event does not count table walks caused by TLB maintenance operations." + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_RD", + "PublicDescription": "Counts level 1 data TLB refills caused by memory read operations. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event counts for refills caused by preload instructions or hardware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in a translation table walk. This event will not count if the translation table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB. This event will not count on an access from an Address Translation (AT) instruction." + }, + { + "ArchStdEvent": "L1D_TLB_REFILL_WR", + "PublicDescription": "Counts level 1 data TLB refills caused by data side memory write operations. If there are multiple misses in the TLB that are resolved by the refill, then this event only counts once. This event counts for refills caused by preload instructions or hardware prefetch accesses. This event counts regardless of whether the miss hits in L2 or results in a translation table walk. This event will not count if the table walk results in a fault (such as a translation or access fault), since there is no new translation created for the TLB. This event will not count with an access from an Address Translation (AT) instruction." + }, + { + "ArchStdEvent": "L1D_TLB_RD", + "PublicDescription": "Counts level 1 data TLB accesses caused by memory read operations. This event counts whether the access hits or misses in the TLB. This event does not count TLB maintenance operations." + }, + { + "ArchStdEvent": "L1D_TLB_WR", + "PublicDescription": "Counts any L1 data side TLB accesses caused by memory write operations. This event counts whether the access hits or misses in the TLB. This event does not count TLB maintenance operations." + }, + { + "ArchStdEvent": "L2D_TLB_REFILL_RD", + "PublicDescription": "Counts level 2 TLB refills caused by memory read operations from both data and instruction fetch except for those caused by TLB maintenance operations or hardware prefetches." + }, + { + "ArchStdEvent": "L2D_TLB_REFILL_WR", + "PublicDescription": "Counts level 2 TLB refills caused by memory write operations from both data and instruction fetch except for those caused by TLB maintenance operations." + }, + { + "ArchStdEvent": "L2D_TLB_RD", + "PublicDescription": "Counts level 2 TLB accesses caused by memory read operations from both data and instruction fetch except for those caused by TLB maintenance operations." + }, + { + "ArchStdEvent": "L2D_TLB_WR", + "PublicDescription": "Counts level 2 TLB accesses caused by memory write operations from both data and instruction fetch except for those caused by TLB maintenance operations." + } +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv index f134e833c069..9d400785d195 100644 --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -23,8 +23,8 @@ 0x00000000410fd080,v1,arm/cortex-a57-a72,core 0x00000000410fd090,v1,arm/cortex-a73,core 0x00000000410fd0a0,v1,arm/cortex-a75,core -0x00000000410fd0b0,v1,arm/cortex-a76-n1,core -0x00000000410fd0c0,v1,arm/cortex-a76-n1,core +0x00000000410fd0b0,v1,arm/cortex-a76,core +0x00000000410fd0c0,v1,arm/neoverse-n1,core 0x00000000410fd0d0,v1,arm/cortex-a77,core 0x00000000410fd400,v1,arm/neoverse-v1,core 0x00000000410fd410,v1,arm/cortex-a78,core -- cgit v1.2.3-58-ga151 From 204e7c499f5fa7732144ef9765c195982be72f31 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 17 Feb 2023 16:32:11 -0600 Subject: perf tools: Add support for perf_event_attr::config3 perf_event_attr has gained a new field, config3, so add support for it extending the existing configN support. Signed-off-by: Rob Herring Cc: Alexander Shishkin Cc: James Clark Cc: Jiri Olsa Cc: Leo Yan Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Link: http://lore.kernel.org/lkml/20220914-arm-perf-tool-spe1-2-v2-v5-2-2cf5210b2f77@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/parse-events.c | 13 ++++++++++++- tools/perf/util/parse-events.c | 6 ++++++ tools/perf/util/parse-events.h | 1 + tools/perf/util/parse-events.l | 1 + tools/perf/util/pmu.c | 3 +++ tools/perf/util/pmu.h | 1 + 6 files changed, 24 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-events.c index b1c2f0a20306..6eb1400443ad 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -449,6 +449,7 @@ static int test__checkevent_pmu(struct evlist *evlist) TEST_ASSERT_VAL("wrong config", 10 == evsel->core.attr.config); TEST_ASSERT_VAL("wrong config1", 1 == evsel->core.attr.config1); TEST_ASSERT_VAL("wrong config2", 3 == evsel->core.attr.config2); + TEST_ASSERT_VAL("wrong config3", 0 == evsel->core.attr.config3); /* * The period value gets configured within evlist__config, * while this test executes only parse events method. @@ -470,6 +471,7 @@ static int test__checkevent_list(struct evlist *evlist) TEST_ASSERT_VAL("wrong config", 1 == evsel->core.attr.config); TEST_ASSERT_VAL("wrong config1", 0 == evsel->core.attr.config1); TEST_ASSERT_VAL("wrong config2", 0 == evsel->core.attr.config2); + TEST_ASSERT_VAL("wrong config3", 0 == evsel->core.attr.config3); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -632,6 +634,15 @@ static int test__checkterms_simple(struct list_head *terms) TEST_ASSERT_VAL("wrong val", term->val.num == 3); TEST_ASSERT_VAL("wrong config", !strcmp(term->config, "config2")); + /* config3=4 */ + term = list_entry(term->list.next, struct parse_events_term, list); + TEST_ASSERT_VAL("wrong type term", + term->type_term == PARSE_EVENTS__TERM_TYPE_CONFIG3); + TEST_ASSERT_VAL("wrong type val", + term->type_val == PARSE_EVENTS__TERM_TYPE_NUM); + TEST_ASSERT_VAL("wrong val", term->val.num == 4); + TEST_ASSERT_VAL("wrong config", !strcmp(term->config, "config3")); + /* umask=1*/ term = list_entry(term->list.next, struct parse_events_term, list); TEST_ASSERT_VAL("wrong type term", @@ -2004,7 +2015,7 @@ struct terms_test { static const struct terms_test test__terms[] = { [0] = { - .str = "config=10,config1,config2=3,umask=1,read,r0xead", + .str = "config=10,config1,config2=3,config3=4,umask=1,read,r0xead", .check = test__checkterms_simple, }, }; diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 6c5cf5244486..cc8e8766ca30 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -949,6 +949,7 @@ static const char *config_term_names[__PARSE_EVENTS__TERM_TYPE_NR] = { [PARSE_EVENTS__TERM_TYPE_CONFIG] = "config", [PARSE_EVENTS__TERM_TYPE_CONFIG1] = "config1", [PARSE_EVENTS__TERM_TYPE_CONFIG2] = "config2", + [PARSE_EVENTS__TERM_TYPE_CONFIG3] = "config3", [PARSE_EVENTS__TERM_TYPE_NAME] = "name", [PARSE_EVENTS__TERM_TYPE_SAMPLE_PERIOD] = "period", [PARSE_EVENTS__TERM_TYPE_SAMPLE_FREQ] = "freq", @@ -988,6 +989,7 @@ config_term_avail(int term_type, struct parse_events_error *err) case PARSE_EVENTS__TERM_TYPE_CONFIG: case PARSE_EVENTS__TERM_TYPE_CONFIG1: case PARSE_EVENTS__TERM_TYPE_CONFIG2: + case PARSE_EVENTS__TERM_TYPE_CONFIG3: case PARSE_EVENTS__TERM_TYPE_NAME: case PARSE_EVENTS__TERM_TYPE_METRIC_ID: case PARSE_EVENTS__TERM_TYPE_SAMPLE_PERIOD: @@ -1033,6 +1035,10 @@ do { \ CHECK_TYPE_VAL(NUM); attr->config2 = term->val.num; break; + case PARSE_EVENTS__TERM_TYPE_CONFIG3: + CHECK_TYPE_VAL(NUM); + attr->config3 = term->val.num; + break; case PARSE_EVENTS__TERM_TYPE_SAMPLE_PERIOD: CHECK_TYPE_VAL(NUM); break; diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index 46204c1a7916..86ad4438a2aa 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -59,6 +59,7 @@ enum { PARSE_EVENTS__TERM_TYPE_CONFIG, PARSE_EVENTS__TERM_TYPE_CONFIG1, PARSE_EVENTS__TERM_TYPE_CONFIG2, + PARSE_EVENTS__TERM_TYPE_CONFIG3, PARSE_EVENTS__TERM_TYPE_NAME, PARSE_EVENTS__TERM_TYPE_SAMPLE_PERIOD, PARSE_EVENTS__TERM_TYPE_SAMPLE_FREQ, diff --git a/tools/perf/util/parse-events.l b/tools/perf/util/parse-events.l index 3a9ce96c8bce..51fe0a9fb3de 100644 --- a/tools/perf/util/parse-events.l +++ b/tools/perf/util/parse-events.l @@ -285,6 +285,7 @@ modifier_bp [rwx]{1,3} config { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_CONFIG); } config1 { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_CONFIG1); } config2 { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_CONFIG2); } +config3 { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_CONFIG3); } name { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_NAME); } period { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_SAMPLE_PERIOD); } freq { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_SAMPLE_FREQ); } diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 45d9b8e28e16..e3aae731bd6f 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -1209,6 +1209,9 @@ static int pmu_config_term(const char *pmu_name, case PERF_PMU_FORMAT_VALUE_CONFIG2: vp = &attr->config2; break; + case PERF_PMU_FORMAT_VALUE_CONFIG3: + vp = &attr->config3; + break; default: return -EINVAL; } diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h index 6b770f17eb86..24cf69ab32cd 100644 --- a/tools/perf/util/pmu.h +++ b/tools/perf/util/pmu.h @@ -19,6 +19,7 @@ enum { PERF_PMU_FORMAT_VALUE_CONFIG, PERF_PMU_FORMAT_VALUE_CONFIG1, PERF_PMU_FORMAT_VALUE_CONFIG2, + PERF_PMU_FORMAT_VALUE_CONFIG3, PERF_PMU_FORMAT_VALUE_CONFIG_END, }; -- cgit v1.2.3-58-ga151 From 46d21ec067490ab9cdcc89b9de5aae28786a8b8e Mon Sep 17 00:00:00 2001 From: Artem Savkov Date: Thu, 16 Mar 2023 14:35:57 +0100 Subject: perf report: Append inlines to non-DWARF callchains Append information about inlined functions to FP and LBR callchains from DWARF debuginfo when available. Do so by calling append_inlines() from add_callchain_ip(). Testing it: Frame-pointer mode recorded with 'perf record --call-graph=fp --freq=max -- ./a.out' #include #include static __attribute__((noinline)) uint32_t func5(uint32_t i) { return i + 10; } static uint32_t func4(uint32_t i) { return func5(i + 5); } static inline uint32_t func3(uint32_t i) { return func4(i + 4); } static __attribute__((noinline)) uint32_t func2(uint32_t i) { return func3(i + 3); } static uint32_t func1(uint32_t i) { return func2(i + 2); } __attribute__((noinline)) uint64_t entry(void) { uint64_t ret = 0; uint32_t i = 0; for (i = 0; i < 1000000; i++) { ret += func1(i); ret -= func2(i); ret += func3(i); ret += func4(i); ret -= func5(i); } return ret; } int main(int argc, char **argv) { printf("%s\n", __func__); return entry(); } ====== Here is the output I get with '--call-graph callee --no-children' ====== # To display the perf.data header info, please use --header/--header-only options. # # # Total Lost Samples: 0 # # Samples: 250 of event 'cycles:u' # Event count (approx.): 26819859 # # Overhead Command Shared Object Symbol # ........ ....... .................... ..................................... # 43.58% a.out a.out [.] func5 | |--28.93%--entry | main | __libc_start_call_main | --14.65%--func4 (inlined) | |--10.45%--entry | main | __libc_start_call_main | --4.20%--func3 (inlined) entry main __libc_start_call_main 38.80% a.out a.out [.] entry | |--23.27%--func4 (inlined) | | | |--20.28%--func3 (inlined) | | func2 | | main | | __libc_start_call_main | | | --2.99%--entry | main | __libc_start_call_main | |--8.17%--func5 | main | __libc_start_call_main | |--3.89%--func1 (inlined) | entry | main | __libc_start_call_main | --3.48%--entry main __libc_start_call_main 13.07% a.out a.out [.] func2 | ---func5 main __libc_start_call_main 1.54% a.out [unknown] [k] 0xffffffff81e011b7 1.16% a.out [unknown] [k] 0xffffffff81e00193 | --0.57%--__mmap64 (inlined) __mmap64 (inlined) 0.34% a.out ld-linux-x86-64.so.2 [.] __tunable_get_val 0.34% a.out ld-linux-x86-64.so.2 [.] strcmp 0.32% a.out libc.so.6 [.] strchr 0.31% a.out ld-linux-x86-64.so.2 [.] _dl_relocate_object 0.22% a.out ld-linux-x86-64.so.2 [.] _dl_init_paths 0.18% a.out ld-linux-x86-64.so.2 [.] get_common_cache_info.constprop.0 0.14% a.out ld-linux-x86-64.so.2 [.] __GI___tunables_init # # (Tip: Show individual samples with: perf script) # ====== It does not seem to be out of order, or at least it is consistent with what I get with dwarf unwinders. Committer notes: Adrian Hunter pointed out that this breaks --branch-history, so don't do it for branches, see the second Link below. Suggested-by: Andrii Nakryiko Signed-off-by: Acked-by: Namhyung Kim Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Masami Hiramatsu Cc: Milian Wolff Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230316133557.868731-2-asavkov@redhat.com Link: https://lore.kernel.org/r/54129783-2960-84e1-05e9-97ac70ffb432@intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/machine.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'tools') diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c index 803c9d1803dd..3182815c73c6 100644 --- a/tools/perf/util/machine.c +++ b/tools/perf/util/machine.c @@ -44,6 +44,7 @@ #include static void __machine__remove_thread(struct machine *machine, struct thread *th, bool lock); +static int append_inlines(struct callchain_cursor *cursor, struct map_symbol *ms, u64 ip); static struct dso *machine__kernel_dso(struct machine *machine) { @@ -2322,6 +2323,10 @@ static int add_callchain_ip(struct thread *thread, ms.maps = al.maps; ms.map = al.map; ms.sym = al.sym; + + if (!branch && append_inlines(cursor, &ms, ip) == 0) + return 0; + srcline = callchain_srcline(&ms, al.addr); return callchain_cursor_append(cursor, ip, &ms, branch, flags, nr_loop_iter, -- cgit v1.2.3-58-ga151 From 1d7966547e11b1355f88086c26eb2086f6ea4770 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Wed, 22 Mar 2023 11:31:08 -0700 Subject: perf build: Add warning for when vmlinux.h generation fails The warning advises on the NO_BPF_SKEL=1 option. Suggested-by: Stephen Rothwell Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230322183108.1380882-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Makefile.perf | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf index ed6b6a070f79..48aba186ceb5 100644 --- a/tools/perf/Makefile.perf +++ b/tools/perf/Makefile.perf @@ -1072,7 +1072,11 @@ VMLINUX_BTF ?= $(abspath $(firstword $(wildcard $(VMLINUX_BTF_PATHS)))) $(SKEL_OUT)/vmlinux.h: $(VMLINUX_BTF) $(BPFTOOL) ifeq ($(VMLINUX_H),) - $(QUIET_GEN)$(BPFTOOL) btf dump file $< format c > $@ + $(QUIET_GEN)$(BPFTOOL) btf dump file $< format c > $@ || \ + (echo "Failure to generate vmlinux.h needed for the recommended BPF skeleton support." && \ + echo "To disable this use the build option NO_BPF_SKEL=1." && \ + echo "Alternatively point at a pre-generated vmlinux.h with VMLINUX_H=." && \ + false) else $(Q)cp "$(VMLINUX_H)" $@ endif -- cgit v1.2.3-58-ga151 From 30df88a80f32ccca5c5cdcf2710d1fb2de5e314d Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Wed, 22 Mar 2023 10:47:31 +0100 Subject: perf test: Fix wrong size expectation for 'Setup struct perf_event_attr' The test case "perf test 'Setup struct perf_event_attr'" is failing. On s390 this output is observed: # ./perf test -Fvvvv 17 17: Setup struct perf_event_attr : --- start --- running './tests/attr/test-stat-C0' Using CPUID IBM,8561,703,T01,3.6,002f ..... Event event:base-stat fd = 1 group_fd = -1 flags = 0|8 cpu = * type = 0 size = 128 <<<--- wrong, specified in file base-stat config = 0 sample_period = 0 sample_type = 65536 ... 'PERF_TEST_ATTR=/tmp/tmpgw574wvg ./perf stat -o \ /tmp/tmpgw574wvg/perf.data -e cycles -C 0 kill >/dev/null \ 2>&1 ret '1', expected '1' loading result events Event event-0-0-4 fd = 4 group_fd = -1 cpu = 0 pid = -1 flags = 8 type = 0 size = 136 <<<--- actual size used in system call ..... compare matching [event-0-0-4] to [event:base-stat] [cpu] 0 * [flags] 8 0|8 [type] 0 0 [size] 136 128 ->FAIL match: [event-0-0-4] matches [] expected size=136, got 128 FAILED './tests/attr/test-stat-C0' - match failure This mismatch is caused by commit 09519ec3b19e ("perf: Add perf_event_attr::config3") which enlarges the structure perf_event_attr by 8 bytes. Fix this by adjusting the expected value of size. Output after: # ./perf test -Fvvvv 17 17: Setup struct perf_event_attr : --- start --- running './tests/attr/test-stat-C0' Using CPUID IBM,8561,703,T01,3.6,002f ... matched compare matching [event-0-0-4] to [event:base-stat] [cpu] 0 * [flags] 8 0|8 [type] 0 0 [size] 136 136 .... ->OK match: [event-0-0-4] matches ['event:base-stat'] matched Fixes: 09519ec3b19e4144 ("perf: Add perf_event_attr::config3") Signed-off-by: Thomas Richter Acked-by: Namhyung Kim Cc: Heiko Carstens Cc: Rob Herring Cc: Sumanth Korikkar Cc: Sven Schnelle Cc: Vasily Gorbik Cc: Will Deacon Link: https://lore.kernel.org/r/20230322094731.1768281-1-tmricht@linux.ibm.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/attr/base-record | 2 +- tools/perf/tests/attr/base-stat | 2 +- tools/perf/tests/attr/system-wide-dummy | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'tools') diff --git a/tools/perf/tests/attr/base-record b/tools/perf/tests/attr/base-record index 3ef07a12aa14..27c21271a16c 100644 --- a/tools/perf/tests/attr/base-record +++ b/tools/perf/tests/attr/base-record @@ -5,7 +5,7 @@ group_fd=-1 flags=0|8 cpu=* type=0|1 -size=128 +size=136 config=0 sample_period=* sample_type=263 diff --git a/tools/perf/tests/attr/base-stat b/tools/perf/tests/attr/base-stat index 408164456530..a21fb65bc012 100644 --- a/tools/perf/tests/attr/base-stat +++ b/tools/perf/tests/attr/base-stat @@ -5,7 +5,7 @@ group_fd=-1 flags=0|8 cpu=* type=0 -size=128 +size=136 config=0 sample_period=0 sample_type=65536 diff --git a/tools/perf/tests/attr/system-wide-dummy b/tools/perf/tests/attr/system-wide-dummy index 8fec06eda5f9..2f3e3eb728eb 100644 --- a/tools/perf/tests/attr/system-wide-dummy +++ b/tools/perf/tests/attr/system-wide-dummy @@ -7,7 +7,7 @@ cpu=* pid=-1 flags=8 type=1 -size=128 +size=136 config=9 sample_period=4000 sample_type=455 -- cgit v1.2.3-58-ga151 From 6094c7744bb0563e833e81d8df8513f9a4e7a257 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Wed, 22 Mar 2023 19:50:05 -0700 Subject: perf hist: Improve srcfile sort key performance (really) The earlier commit f0cdde28fecc0d7f ("perf hist: Improve srcfile sort key performance") updated the srcfile logic but missed to change the ->cmp() callback which is called for every sample. It should use the same logic like in the srcline to speed up the processing because it'd return the same information repeatedly for the same address. The real processing will be done in sort__srcfile_collapse(). Fixes: f0cdde28fecc0d7f ("perf hist: Improve srcfile sort key performance") Signed-off-by: Namhyung Kim Cc: Adrian Hunter Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230323025005.191239-1-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/sort.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/sort.c b/tools/perf/util/sort.c index e11e68ecf0a2..2b5cc8e4aa6e 100644 --- a/tools/perf/util/sort.c +++ b/tools/perf/util/sort.c @@ -657,12 +657,7 @@ static char *hist_entry__get_srcfile(struct hist_entry *e) static int64_t sort__srcfile_cmp(struct hist_entry *left, struct hist_entry *right) { - if (!left->srcfile) - left->srcfile = hist_entry__get_srcfile(left); - if (!right->srcfile) - right->srcfile = hist_entry__get_srcfile(right); - - return strcmp(right->srcfile, left->srcfile); + return sort__srcline_cmp(left, right); } static int64_t -- cgit v1.2.3-58-ga151 From eb2feb68cb7d404288493c41480843bc9f404789 Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Thu, 23 Mar 2023 13:25:32 +0100 Subject: perf vendor events s390: Remove UTF-8 characters from JSON file Commit 7f76b31130680fb3 ("perf list: Add IBM z16 event description for s390") contains the verbal description for z16 extended counter set. However some entries of the public description contain UTF-8 characters which breaks the build on some distros. Fix this and remove the UTF-8 characters. Fixes: 7f76b31130680fb3 ("perf list: Add IBM z16 event description for s390") Reported-by: Arnaldo Carvalho de Melo Suggested-by: Heiko Carstens Signed-off-by: Thomas Richter Tested-by: Arnaldo Carvalho de Melo Cc: Sumanth Korikkar Cc: Sven Schnelle Cc: Thomas Richter Cc: Vasily Gorbik Link: https://lore.kernel.org/r/ZBwkl77/I31AQk12@osiris Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/s390/cf_z16/extended.json | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/extended.json b/tools/perf/pmu-events/arch/s390/cf_z16/extended.json index c306190fc06f..c2b10ec1c6e0 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z16/extended.json +++ b/tools/perf/pmu-events/arch/s390/cf_z16/extended.json @@ -95,28 +95,28 @@ "EventCode": "145", "EventName": "DCW_REQ", "BriefDescription": "Directory Write Level 1 Data Cache from Cache", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache." + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache." }, { "Unit": "CPU-M-CF", "EventCode": "146", "EventName": "DCW_REQ_IV", "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Intervention", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache with intervention." + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention." }, { "Unit": "CPU-M-CF", "EventCode": "147", "EventName": "DCW_REQ_CHIP_HIT", "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Chip HP Hit", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache after using chip level horizontal persistence, Chip-HP hit." + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using chip level horizontal persistence, Chip-HP hit." }, { "Unit": "CPU-M-CF", "EventCode": "148", "EventName": "DCW_REQ_DRAWER_HIT", "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Drawer HP Hit", - "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit." + "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit." }, { "Unit": "CPU-M-CF", @@ -284,7 +284,7 @@ "EventCode": "172", "EventName": "ICW_REQ_DRAWER_HIT", "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache with Drawer HP Hit", - "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestor’s Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." + "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache using drawer level horizontal persistence, Drawer-HP hit." }, { "Unit": "CPU-M-CF", -- cgit v1.2.3-58-ga151 From 5d8c0f0e11852d22fc3464c82453ddd1286f5d72 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Thu, 23 Mar 2023 17:19:22 -0700 Subject: perf lock contention: Fix msan issue in lock_contention_read() I got a report of a msan failure like below: $ sudo perf lock con -ab -- sleep 1 ... ==224416==WARNING: MemorySanitizer: use-of-uninitialized-value #0 0x5651160d6c96 in lock_contention_read util/bpf_lock_contention.c:290:8 #1 0x565115f90870 in __cmd_contention builtin-lock.c:1919:3 #2 0x565115f90870 in cmd_lock builtin-lock.c:2385:8 #3 0x565115f03a83 in run_builtin perf.c:330:11 #4 0x565115f03756 in handle_internal_command perf.c:384:8 #5 0x565115f02d53 in run_argv perf.c:428:2 #6 0x565115f02d53 in main perf.c:562:3 #7 0x7f43553bc632 in __libc_start_main #8 0x565115e865a9 in _start It was because the 'key' variable is not initialized. Actually it'd be set by bpf_map_get_next_key() but msan didn't seem to understand it. Let's make msan happy by initializing the variable. Signed-off-by: Namhyung Kim Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Ingo Molnar Cc: Jiri Olsa Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230324001922.937634-1-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/bpf_lock_contention.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/bpf_lock_contention.c b/tools/perf/util/bpf_lock_contention.c index 235fc7150545..5927bf0bd92b 100644 --- a/tools/perf/util/bpf_lock_contention.c +++ b/tools/perf/util/bpf_lock_contention.c @@ -249,7 +249,7 @@ static const char *lock_contention_get_name(struct lock_contention *con, int lock_contention_read(struct lock_contention *con) { int fd, stack, err = 0; - struct contention_key *prev_key, key; + struct contention_key *prev_key, key = {}; struct contention_data data = {}; struct lock_stat *st = NULL; struct machine *machine = con->machine; -- cgit v1.2.3-58-ga151 From 7803654576db93c49be73ff02d53030558c971b7 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 24 Mar 2023 00:22:10 -0700 Subject: perf vendor events intel: Broadwell v27 events Description updates and formatting changes. Reviewed-by: Kan Liang Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Dan Williams Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Samantha Alt Cc: Weilin Wang Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230324072218.181880-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../perf/pmu-events/arch/x86/broadwell/cache.json | 296 ++++++++++----------- .../arch/x86/broadwell/floating-point.json | 7 + .../pmu-events/arch/x86/broadwell/frontend.json | 18 +- .../perf/pmu-events/arch/x86/broadwell/memory.json | 248 ++++++++--------- .../pmu-events/arch/x86/broadwell/pipeline.json | 22 +- .../arch/x86/broadwell/uncore-other.json | 2 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 7 files changed, 305 insertions(+), 290 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/broadwell/cache.json b/tools/perf/pmu-events/arch/x86/broadwell/cache.json index 26199d3ebb25..f8ee5aefccea 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/cache.json @@ -8,7 +8,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", @@ -16,7 +16,7 @@ "UMask": "0x2" }, { - "BriefDescription": "L1D miss oustandings duration in cycles", + "BriefDescription": "L1D miss outstandings duration in cycles", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", @@ -424,22 +424,22 @@ "UMask": "0x20" }, { - "BriefDescription": "All retired load uops.", + "BriefDescription": "Retired load uops.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "PEBS": "1", - "PublicDescription": "This event counts load uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.", + "PublicDescription": "Counts all retired load uops. This event accounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.", "SampleAfterValue": "2000003", "UMask": "0x81" }, { - "BriefDescription": "All retired store uops.", + "BriefDescription": "Retired store uops.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", "PEBS": "1", - "PublicDescription": "This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement.", + "PublicDescription": "Counts all retired store uops.", "SampleAfterValue": "2000003", "UMask": "0x82" }, @@ -511,10 +511,10 @@ "UMask": "0x80" }, { - "BriefDescription": "Cacheable and noncachaeble code read requests", + "BriefDescription": "Cacheable and non-cacheable code read requests", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.", + "PublicDescription": "This event counts both cacheable and non-cacheable code read requests.", "SampleAfterValue": "100003", "UMask": "0x2" }, @@ -629,7 +629,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010091", + "MSRValue": "0x10091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -656,7 +656,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0091", + "MSRValue": "0x4003C0091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -665,7 +665,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0091", + "MSRValue": "0x2003C0091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -674,7 +674,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0091", + "MSRValue": "0x803C0091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -683,7 +683,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0091", + "MSRValue": "0x1003C0091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -710,7 +710,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020091", + "MSRValue": "0x400020091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -719,7 +719,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020091", + "MSRValue": "0x200020091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -728,7 +728,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020091", + "MSRValue": "0x80020091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -737,7 +737,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020091", + "MSRValue": "0x100020091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -746,7 +746,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010240", + "MSRValue": "0x10240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -773,7 +773,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0240", + "MSRValue": "0x4003C0240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -782,7 +782,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0240", + "MSRValue": "0x2003C0240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -791,7 +791,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0240", + "MSRValue": "0x803C0240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -800,7 +800,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0240", + "MSRValue": "0x1003C0240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -827,7 +827,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020240", + "MSRValue": "0x400020240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -836,7 +836,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020240", + "MSRValue": "0x200020240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -845,7 +845,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020240", + "MSRValue": "0x80020240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -854,7 +854,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020240", + "MSRValue": "0x100020240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -863,7 +863,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010090", + "MSRValue": "0x10090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -890,7 +890,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0090", + "MSRValue": "0x4003C0090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -899,7 +899,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0090", + "MSRValue": "0x2003C0090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -908,7 +908,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0090", + "MSRValue": "0x803C0090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -917,7 +917,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0090", + "MSRValue": "0x1003C0090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -944,7 +944,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020090", + "MSRValue": "0x400020090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -953,7 +953,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020090", + "MSRValue": "0x200020090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -962,7 +962,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020090", + "MSRValue": "0x80020090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -971,7 +971,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020090", + "MSRValue": "0x100020090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -980,7 +980,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010120", + "MSRValue": "0x10120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1007,7 +1007,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0120", + "MSRValue": "0x4003C0120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1016,7 +1016,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0120", + "MSRValue": "0x2003C0120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1025,7 +1025,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0120", + "MSRValue": "0x803C0120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1034,7 +1034,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0120", + "MSRValue": "0x1003C0120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1061,7 +1061,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020120", + "MSRValue": "0x400020120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1070,7 +1070,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020120", + "MSRValue": "0x200020120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1079,7 +1079,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020120", + "MSRValue": "0x80020120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1088,7 +1088,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020120", + "MSRValue": "0x100020120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1097,7 +1097,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010122", + "MSRValue": "0x10122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1124,7 +1124,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0122", + "MSRValue": "0x4003C0122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1133,7 +1133,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0122", + "MSRValue": "0x2003C0122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1142,7 +1142,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0122", + "MSRValue": "0x803C0122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1151,7 +1151,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0122", + "MSRValue": "0x1003C0122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1178,7 +1178,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020122", + "MSRValue": "0x400020122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1187,7 +1187,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020122", + "MSRValue": "0x200020122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1196,7 +1196,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020122", + "MSRValue": "0x80020122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1205,7 +1205,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020122", + "MSRValue": "0x100020122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1214,7 +1214,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010008", + "MSRValue": "0x10008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1241,7 +1241,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0008", + "MSRValue": "0x4003C0008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1250,7 +1250,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0008", + "MSRValue": "0x2003C0008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1259,7 +1259,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0008", + "MSRValue": "0x803C0008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1268,7 +1268,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0008", + "MSRValue": "0x1003C0008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1295,7 +1295,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020008", + "MSRValue": "0x400020008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1304,7 +1304,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020008", + "MSRValue": "0x200020008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1313,7 +1313,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020008", + "MSRValue": "0x80020008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1322,7 +1322,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020008", + "MSRValue": "0x100020008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1331,7 +1331,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010004", + "MSRValue": "0x10004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1358,7 +1358,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0004", + "MSRValue": "0x4003C0004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1367,7 +1367,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0004", + "MSRValue": "0x2003C0004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1376,7 +1376,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0004", + "MSRValue": "0x803C0004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1385,7 +1385,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0004", + "MSRValue": "0x1003C0004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1412,7 +1412,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020004", + "MSRValue": "0x400020004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1421,7 +1421,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020004", + "MSRValue": "0x200020004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1430,7 +1430,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020004", + "MSRValue": "0x80020004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1439,7 +1439,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020004", + "MSRValue": "0x100020004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1448,7 +1448,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010001", + "MSRValue": "0x10001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1475,7 +1475,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0001", + "MSRValue": "0x4003C0001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1484,7 +1484,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0001", + "MSRValue": "0x2003C0001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1493,7 +1493,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0001", + "MSRValue": "0x803C0001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1502,7 +1502,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0001", + "MSRValue": "0x1003C0001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1529,7 +1529,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020001", + "MSRValue": "0x400020001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1538,7 +1538,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020001", + "MSRValue": "0x200020001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1547,7 +1547,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020001", + "MSRValue": "0x80020001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1556,7 +1556,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020001", + "MSRValue": "0x100020001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1565,7 +1565,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010002", + "MSRValue": "0x10002", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1592,7 +1592,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0002", + "MSRValue": "0x4003C0002", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1601,7 +1601,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0002", + "MSRValue": "0x2003C0002", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1610,7 +1610,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0002", + "MSRValue": "0x803C0002", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1619,7 +1619,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0002", + "MSRValue": "0x1003C0002", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1628,7 +1628,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000018000", + "MSRValue": "0x18000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1655,7 +1655,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C8000", + "MSRValue": "0x4003C8000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1664,7 +1664,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C8000", + "MSRValue": "0x2003C8000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1673,7 +1673,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C8000", + "MSRValue": "0x803C8000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1682,7 +1682,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C8000", + "MSRValue": "0x1003C8000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1709,7 +1709,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400028000", + "MSRValue": "0x400028000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1718,7 +1718,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200028000", + "MSRValue": "0x200028000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1727,7 +1727,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080028000", + "MSRValue": "0x80028000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1736,7 +1736,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100028000", + "MSRValue": "0x100028000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1745,7 +1745,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010040", + "MSRValue": "0x10040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1772,7 +1772,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0040", + "MSRValue": "0x4003C0040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1781,7 +1781,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0040", + "MSRValue": "0x2003C0040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1790,7 +1790,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0040", + "MSRValue": "0x803C0040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1799,7 +1799,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0040", + "MSRValue": "0x1003C0040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1826,7 +1826,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020040", + "MSRValue": "0x400020040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1835,7 +1835,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020040", + "MSRValue": "0x200020040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1844,7 +1844,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020040", + "MSRValue": "0x80020040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1853,7 +1853,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020040", + "MSRValue": "0x100020040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1862,7 +1862,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010010", + "MSRValue": "0x10010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1889,7 +1889,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0010", + "MSRValue": "0x4003C0010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1898,7 +1898,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0010", + "MSRValue": "0x2003C0010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1907,7 +1907,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0010", + "MSRValue": "0x803C0010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1916,7 +1916,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0010", + "MSRValue": "0x1003C0010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1943,7 +1943,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020010", + "MSRValue": "0x400020010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1952,7 +1952,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020010", + "MSRValue": "0x200020010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1961,7 +1961,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020010", + "MSRValue": "0x80020010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1970,7 +1970,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020010", + "MSRValue": "0x100020010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1979,7 +1979,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010020", + "MSRValue": "0x10020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2006,7 +2006,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0020", + "MSRValue": "0x4003C0020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2015,7 +2015,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0020", + "MSRValue": "0x2003C0020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2024,7 +2024,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0020", + "MSRValue": "0x803C0020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2033,7 +2033,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0020", + "MSRValue": "0x1003C0020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2060,7 +2060,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020020", + "MSRValue": "0x400020020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2069,7 +2069,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020020", + "MSRValue": "0x200020020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2078,7 +2078,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020020", + "MSRValue": "0x80020020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2087,7 +2087,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020020", + "MSRValue": "0x100020020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2096,7 +2096,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010200", + "MSRValue": "0x10200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2123,7 +2123,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0200", + "MSRValue": "0x4003C0200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2132,7 +2132,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0200", + "MSRValue": "0x2003C0200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2141,7 +2141,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0200", + "MSRValue": "0x803C0200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2150,7 +2150,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0200", + "MSRValue": "0x1003C0200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2177,7 +2177,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020200", + "MSRValue": "0x400020200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2186,7 +2186,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020200", + "MSRValue": "0x200020200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2195,7 +2195,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020200", + "MSRValue": "0x80020200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2204,7 +2204,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020200", + "MSRValue": "0x100020200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2213,7 +2213,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010080", + "MSRValue": "0x10080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2240,7 +2240,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0080", + "MSRValue": "0x4003C0080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2249,7 +2249,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0080", + "MSRValue": "0x2003C0080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2258,7 +2258,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0080", + "MSRValue": "0x803C0080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2267,7 +2267,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0080", + "MSRValue": "0x1003C0080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2294,7 +2294,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020080", + "MSRValue": "0x400020080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2303,7 +2303,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020080", + "MSRValue": "0x200020080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2312,7 +2312,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020080", + "MSRValue": "0x80020080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2321,7 +2321,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020080", + "MSRValue": "0x100020080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2330,7 +2330,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010100", + "MSRValue": "0x10100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2357,7 +2357,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0100", + "MSRValue": "0x4003C0100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2366,7 +2366,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0100", + "MSRValue": "0x2003C0100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2375,7 +2375,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0100", + "MSRValue": "0x803C0100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2384,7 +2384,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0100", + "MSRValue": "0x1003C0100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2411,7 +2411,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020100", + "MSRValue": "0x400020100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2420,7 +2420,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020100", + "MSRValue": "0x200020100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2429,7 +2429,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020100", + "MSRValue": "0x80020100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2438,7 +2438,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020100", + "MSRValue": "0x100020100", "SampleAfterValue": "100003", "UMask": "0x1" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json b/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json index 0de16d9a80da..e4826dc7f797 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json @@ -3,6 +3,7 @@ "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x4" }, @@ -10,6 +11,7 @@ "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x8" }, @@ -17,6 +19,7 @@ "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x10" }, @@ -24,6 +27,7 @@ "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x20" }, @@ -45,6 +49,7 @@ "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation. Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x3" }, @@ -52,6 +57,7 @@ "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x1" }, @@ -59,6 +65,7 @@ "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x2" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwell/frontend.json b/tools/perf/pmu-events/arch/x86/broadwell/frontend.json index d0f6678609ae..bd5da39564e1 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/frontend.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/frontend.json @@ -125,16 +125,16 @@ "UMask": "0x4" }, { - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", - "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", "SampleAfterValue": "2000003", "UMask": "0x30" }, { - "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -143,7 +143,7 @@ "UMask": "0x10" }, { - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -153,7 +153,7 @@ "UMask": "0x10" }, { - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_UOPS", "PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", @@ -161,10 +161,10 @@ "UMask": "0x10" }, { - "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", - "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.", + "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", "UMask": "0x20" }, @@ -178,10 +178,10 @@ "UMask": "0x30" }, { - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", - "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", "SampleAfterValue": "2000003", "UMask": "0x30" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwell/memory.json b/tools/perf/pmu-events/arch/x86/broadwell/memory.json index 394ed602fcb1..ac7cdb831960 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/memory.json @@ -206,7 +206,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000091", + "MSRValue": "0x43C000091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -215,7 +215,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000091", + "MSRValue": "0x23C000091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -224,7 +224,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000091", + "MSRValue": "0xBC000091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -233,7 +233,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000091", + "MSRValue": "0x13C000091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -260,7 +260,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000091", + "MSRValue": "0x404000091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -269,7 +269,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000091", + "MSRValue": "0x204000091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -278,7 +278,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000091", + "MSRValue": "0x84000091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -296,7 +296,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000091", + "MSRValue": "0x104000091", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -323,7 +323,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000240", + "MSRValue": "0x43C000240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -332,7 +332,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000240", + "MSRValue": "0x23C000240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -341,7 +341,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000240", + "MSRValue": "0xBC000240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -350,7 +350,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000240", + "MSRValue": "0x13C000240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -377,7 +377,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000240", + "MSRValue": "0x404000240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -386,7 +386,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000240", + "MSRValue": "0x204000240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -395,7 +395,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000240", + "MSRValue": "0x84000240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -413,7 +413,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000240", + "MSRValue": "0x104000240", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -440,7 +440,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000090", + "MSRValue": "0x43C000090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -449,7 +449,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000090", + "MSRValue": "0x23C000090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -458,7 +458,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000090", + "MSRValue": "0xBC000090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -467,7 +467,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000090", + "MSRValue": "0x13C000090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -494,7 +494,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000090", + "MSRValue": "0x404000090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -503,7 +503,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000090", + "MSRValue": "0x204000090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -512,7 +512,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000090", + "MSRValue": "0x84000090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -530,7 +530,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000090", + "MSRValue": "0x104000090", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -557,7 +557,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000120", + "MSRValue": "0x43C000120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -566,7 +566,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000120", + "MSRValue": "0x23C000120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -575,7 +575,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000120", + "MSRValue": "0xBC000120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -584,7 +584,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000120", + "MSRValue": "0x13C000120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -611,7 +611,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000120", + "MSRValue": "0x404000120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -620,7 +620,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000120", + "MSRValue": "0x204000120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -629,7 +629,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000120", + "MSRValue": "0x84000120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -647,7 +647,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000120", + "MSRValue": "0x104000120", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -674,7 +674,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000122", + "MSRValue": "0x43C000122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -683,7 +683,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000122", + "MSRValue": "0x23C000122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -692,7 +692,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000122", + "MSRValue": "0xBC000122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -701,7 +701,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000122", + "MSRValue": "0x13C000122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -728,7 +728,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000122", + "MSRValue": "0x404000122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -737,7 +737,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000122", + "MSRValue": "0x204000122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -746,7 +746,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000122", + "MSRValue": "0x84000122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -764,7 +764,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000122", + "MSRValue": "0x104000122", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -791,7 +791,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000008", + "MSRValue": "0x43C000008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -800,7 +800,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000008", + "MSRValue": "0x23C000008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -809,7 +809,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000008", + "MSRValue": "0xBC000008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -818,7 +818,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000008", + "MSRValue": "0x13C000008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -845,7 +845,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000008", + "MSRValue": "0x404000008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -854,7 +854,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000008", + "MSRValue": "0x204000008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -863,7 +863,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000008", + "MSRValue": "0x84000008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -881,7 +881,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000008", + "MSRValue": "0x104000008", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -908,7 +908,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000004", + "MSRValue": "0x43C000004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -917,7 +917,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000004", + "MSRValue": "0x23C000004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -926,7 +926,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000004", + "MSRValue": "0xBC000004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -935,7 +935,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000004", + "MSRValue": "0x13C000004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -962,7 +962,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000004", + "MSRValue": "0x404000004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -971,7 +971,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000004", + "MSRValue": "0x204000004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -980,7 +980,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000004", + "MSRValue": "0x84000004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -998,7 +998,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000004", + "MSRValue": "0x104000004", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1025,7 +1025,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000001", + "MSRValue": "0x43C000001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1034,7 +1034,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000001", + "MSRValue": "0x23C000001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1043,7 +1043,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000001", + "MSRValue": "0xBC000001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1052,7 +1052,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000001", + "MSRValue": "0x13C000001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1079,7 +1079,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000001", + "MSRValue": "0x404000001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1088,7 +1088,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000001", + "MSRValue": "0x204000001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1097,7 +1097,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000001", + "MSRValue": "0x84000001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1115,7 +1115,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000001", + "MSRValue": "0x104000001", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1142,7 +1142,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000002", + "MSRValue": "0x43C000002", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1151,7 +1151,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000002", + "MSRValue": "0x23C000002", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1160,7 +1160,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000002", + "MSRValue": "0xBC000002", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1169,7 +1169,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000002", + "MSRValue": "0x13C000002", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1196,7 +1196,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C008000", + "MSRValue": "0x43C008000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1205,7 +1205,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C008000", + "MSRValue": "0x23C008000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1214,7 +1214,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC008000", + "MSRValue": "0xBC008000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1223,7 +1223,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C008000", + "MSRValue": "0x13C008000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1250,7 +1250,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404008000", + "MSRValue": "0x404008000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1259,7 +1259,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204008000", + "MSRValue": "0x204008000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1268,7 +1268,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084008000", + "MSRValue": "0x84008000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1286,7 +1286,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104008000", + "MSRValue": "0x104008000", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1313,7 +1313,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000040", + "MSRValue": "0x43C000040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1322,7 +1322,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000040", + "MSRValue": "0x23C000040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1331,7 +1331,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000040", + "MSRValue": "0xBC000040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1340,7 +1340,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000040", + "MSRValue": "0x13C000040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1367,7 +1367,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000040", + "MSRValue": "0x404000040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1376,7 +1376,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000040", + "MSRValue": "0x204000040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1385,7 +1385,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000040", + "MSRValue": "0x84000040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1403,7 +1403,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000040", + "MSRValue": "0x104000040", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1430,7 +1430,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000010", + "MSRValue": "0x43C000010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1439,7 +1439,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000010", + "MSRValue": "0x23C000010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1448,7 +1448,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000010", + "MSRValue": "0xBC000010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1457,7 +1457,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000010", + "MSRValue": "0x13C000010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1484,7 +1484,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000010", + "MSRValue": "0x404000010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1493,7 +1493,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000010", + "MSRValue": "0x204000010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1502,7 +1502,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000010", + "MSRValue": "0x84000010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1520,7 +1520,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000010", + "MSRValue": "0x104000010", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1547,7 +1547,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000020", + "MSRValue": "0x43C000020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1556,7 +1556,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000020", + "MSRValue": "0x23C000020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1565,7 +1565,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000020", + "MSRValue": "0xBC000020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1574,7 +1574,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000020", + "MSRValue": "0x13C000020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1601,7 +1601,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000020", + "MSRValue": "0x404000020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1610,7 +1610,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000020", + "MSRValue": "0x204000020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1619,7 +1619,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000020", + "MSRValue": "0x84000020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1637,7 +1637,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000020", + "MSRValue": "0x104000020", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1664,7 +1664,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000200", + "MSRValue": "0x43C000200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1673,7 +1673,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000200", + "MSRValue": "0x23C000200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1682,7 +1682,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000200", + "MSRValue": "0xBC000200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1691,7 +1691,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000200", + "MSRValue": "0x13C000200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1718,7 +1718,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000200", + "MSRValue": "0x404000200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1727,7 +1727,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000200", + "MSRValue": "0x204000200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1736,7 +1736,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000200", + "MSRValue": "0x84000200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1754,7 +1754,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000200", + "MSRValue": "0x104000200", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1781,7 +1781,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000080", + "MSRValue": "0x43C000080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1790,7 +1790,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000080", + "MSRValue": "0x23C000080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1799,7 +1799,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000080", + "MSRValue": "0xBC000080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1808,7 +1808,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000080", + "MSRValue": "0x13C000080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1835,7 +1835,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000080", + "MSRValue": "0x404000080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1844,7 +1844,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000080", + "MSRValue": "0x204000080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1853,7 +1853,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000080", + "MSRValue": "0x84000080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1871,7 +1871,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000080", + "MSRValue": "0x104000080", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1898,7 +1898,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000100", + "MSRValue": "0x43C000100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1907,7 +1907,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000100", + "MSRValue": "0x23C000100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1916,7 +1916,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000100", + "MSRValue": "0xBC000100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1925,7 +1925,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000100", + "MSRValue": "0x13C000100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1952,7 +1952,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000100", + "MSRValue": "0x404000100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1961,7 +1961,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000100", + "MSRValue": "0x204000100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1970,7 +1970,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000100", + "MSRValue": "0x84000100", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -1988,7 +1988,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000100", + "MSRValue": "0x104000100", "SampleAfterValue": "100003", "UMask": "0x1" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json b/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json index 2f0fe6b35334..9a902d2160e6 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json @@ -214,6 +214,14 @@ "SampleAfterValue": "200003", "UMask": "0xc4" }, + { + "BriefDescription": "Speculative mispredicted indirect branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.INDIRECT", + "PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, { "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", "EventCode": "0x89", @@ -500,7 +508,7 @@ "BriefDescription": "Stalls caused by changing prefix length of the instruction.", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", - "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", + "PublicDescription": "This event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", "SampleAfterValue": "2000003", "UMask": "0x1" }, @@ -909,7 +917,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in port 0.", + "BriefDescription": "Cycles per core when uops are executed in port 0.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", "SampleAfterValue": "2000003", @@ -925,7 +933,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in port 1.", + "BriefDescription": "Cycles per core when uops are executed in port 1.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", "SampleAfterValue": "2000003", @@ -973,7 +981,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in port 4.", + "BriefDescription": "Cycles per core when uops are executed in port 4.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", "SampleAfterValue": "2000003", @@ -989,7 +997,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in port 5.", + "BriefDescription": "Cycles per core when uops are executed in port 5.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", "SampleAfterValue": "2000003", @@ -1005,7 +1013,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in port 6.", + "BriefDescription": "Cycles per core when uops are executed in port 6.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", "SampleAfterValue": "2000003", @@ -1097,7 +1105,7 @@ }, { "BriefDescription": "Cycles with less than 10 actually retired uops.", - "CounterMask": "10", + "CounterMask": "16", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", "Invert": "1", diff --git a/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json b/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json index ddcf7faa9d10..368a958a18a0 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json @@ -8,7 +8,7 @@ "Unit": "ARB" }, { - "BriefDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.", + "BriefDescription": "Each cycle counts number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 9abebe50ae0d..70be860bcb53 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -2,7 +2,7 @@ Family-model,Version,Filename,EventType GenuineIntel-6-(97|9A|B7|BA|BF),v1.19,alderlake,core GenuineIntel-6-BE,v1.19,alderlaken,core GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core -GenuineIntel-6-(3D|47),v26,broadwell,core +GenuineIntel-6-(3D|47),v27,broadwell,core GenuineIntel-6-56,v7,broadwellde,core GenuineIntel-6-4F,v19,broadwellx,core GenuineIntel-6-55-[56789ABCDEF],v1.17,cascadelakex,core -- cgit v1.2.3-58-ga151 From 8aae803f66aa070fc5062fdaabaeaddb4cf18bf8 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 24 Mar 2023 00:22:11 -0700 Subject: perf vendor events intel: Broadwellde v9 events Updates descriptions and encodings. Adds BR_MISP_EXEC.INDIRECT events. Reviewed-by: Kan Liang Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Dan Williams Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Samantha Alt Cc: Weilin Wang Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230324072218.181880-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/broadwellde/cache.json | 105 +++++---- .../arch/x86/broadwellde/floating-point.json | 45 ++-- .../pmu-events/arch/x86/broadwellde/frontend.json | 18 +- .../pmu-events/arch/x86/broadwellde/memory.json | 64 +++--- .../pmu-events/arch/x86/broadwellde/pipeline.json | 79 ++++--- .../arch/x86/broadwellde/uncore-cache.json | 72 +++--- .../arch/x86/broadwellde/uncore-memory.json | 256 ++++++++++++++++++++- .../arch/x86/broadwellde/uncore-other.json | 27 ++- .../arch/x86/broadwellde/uncore-power.json | 10 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 10 files changed, 495 insertions(+), 183 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/cache.json b/tools/perf/pmu-events/arch/x86/broadwellde/cache.json index fcc99fd22b0a..6784331ac1cb 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/cache.json @@ -8,7 +8,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", @@ -16,7 +16,7 @@ "UMask": "0x2" }, { - "BriefDescription": "L1D miss oustandings duration in cycles", + "BriefDescription": "L1D miss outstandings duration in cycles", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", @@ -139,7 +139,7 @@ "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "SampleAfterValue": "200003", - "UMask": "0x44" + "UMask": "0xc4" }, { "BriefDescription": "L2 cache misses when fetching instructions.", @@ -152,9 +152,9 @@ "BriefDescription": "Demand Data Read requests that hit L2 cache", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", - "PublicDescription": "This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted.", + "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache.", "SampleAfterValue": "200003", - "UMask": "0x41" + "UMask": "0xc1" }, { "BriefDescription": "Demand Data Read miss L2, no rejects", @@ -170,7 +170,7 @@ "EventName": "L2_RQSTS.L2_PF_HIT", "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.", "SampleAfterValue": "200003", - "UMask": "0x50" + "UMask": "0xd0" }, { "BriefDescription": "L2 prefetch requests that miss L2 cache", @@ -199,7 +199,7 @@ "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200003", - "UMask": "0x42" + "UMask": "0xc2" }, { "BriefDescription": "RFO requests that miss L2 cache.", @@ -297,61 +297,62 @@ "UMask": "0x4f" }, { - "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS)", + "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.", + "PublicDescription": "This event counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.", "SampleAfterValue": "20011", "UMask": "0x2" }, { - "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3. (Precise Event - PEBS)", + "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3).", + "PublicDescription": "This event counts retired load uops which data sources were HitM responses from a core on same socket (shared L3).", "SampleAfterValue": "20011", "UMask": "0x4" }, { - "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS)", + "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.", + "PublicDescription": "This event counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.", "SampleAfterValue": "20011", "UMask": "0x1" }, { - "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required. (Precise Event - PEBS)", + "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.", + "PublicDescription": "This event counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.", "SampleAfterValue": "100003", "UMask": "0x8" }, { + "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", "Data_LA": "1", "Errata": "BDE70, BDM100", "EventCode": "0xD3", "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", "PEBS": "1", - "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event.", + "PublicDescription": "Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI).", "SampleAfterValue": "100007", "UMask": "0x1" }, { - "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event)", + "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)", "Data_LA": "1", "Errata": "BDE70", "EventCode": "0xD3", @@ -361,7 +362,7 @@ "UMask": "0x4" }, { - "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache (Precise Event)", + "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache", "Data_LA": "1", "Errata": "BDE70", "EventCode": "0xD3", @@ -371,7 +372,7 @@ "UMask": "0x20" }, { - "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM (Precise Event)", + "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM", "Data_LA": "1", "Errata": "BDE70", "EventCode": "0xD3", @@ -381,69 +382,69 @@ "UMask": "0x10" }, { - "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS)", + "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.", + "PublicDescription": "This event counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.", "SampleAfterValue": "100003", "UMask": "0x40" }, { - "BriefDescription": "Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS)", + "BriefDescription": "Retired load uops with L1 cache hits as data sources.", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data source were hits in the nearest-level (L1) cache.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source.", + "PublicDescription": "This event counts retired load uops which data sources were hits in the nearest-level (L1) cache.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Retired load uops misses in L1 cache as data sources. Uses PEBS.", + "BriefDescription": "Retired load uops misses in L1 cache as data sources.", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.", + "PublicDescription": "This event counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.", "SampleAfterValue": "100003", "UMask": "0x8" }, { - "BriefDescription": "Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS)", + "BriefDescription": "Retired load uops with L2 cache hits as data sources.", "Data_LA": "1", "Errata": "BDM35", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache.", + "PublicDescription": "This event counts retired load uops which data sources were hits in the mid-level (L2) cache.", "SampleAfterValue": "100003", "UMask": "0x2" }, { - "BriefDescription": "Retired load uops with L2 cache misses as data sources. Uses PEBS.", + "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.", + "PublicDescription": "This event counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.", "SampleAfterValue": "50021", "UMask": "0x10" }, { - "BriefDescription": "Hit in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS)", + "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.", + "PublicDescription": "This event counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.", "SampleAfterValue": "50021", "UMask": "0x4" }, { - "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS).", + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", "Data_LA": "1", "Errata": "BDM100, BDE70", "EventCode": "0xD1", @@ -453,73 +454,73 @@ "UMask": "0x20" }, { - "BriefDescription": "All retired load uops. (Precise Event - PEBS)", + "BriefDescription": "Retired load uops.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts load uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.", + "PublicDescription": "Counts all retired load uops. This event accounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.", "SampleAfterValue": "2000003", "UMask": "0x81" }, { - "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)", + "BriefDescription": "Retired store uops.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement.", + "PublicDescription": "Counts all retired store uops.", "SampleAfterValue": "2000003", "UMask": "0x82" }, { - "BriefDescription": "Retired load uops with locked access. (Precise Event - PEBS)", + "BriefDescription": "Retired load uops with locked access.", "Data_LA": "1", "Errata": "BDM35", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts load uops with locked access retired to the architected path.", + "PublicDescription": "This event counts load uops with locked access retired to the architected path.", "SampleAfterValue": "100007", "UMask": "0x21" }, { - "BriefDescription": "Retired load uops that split across a cacheline boundary.(Precise Event - PEBS)", + "BriefDescription": "Retired load uops that split across a cacheline boundary.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "SampleAfterValue": "100003", "UMask": "0x41" }, { - "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)", + "BriefDescription": "Retired store uops that split across a cacheline boundary.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "SampleAfterValue": "100003", "UMask": "0x42" }, { - "BriefDescription": "Retired load uops that miss the STLB. (Precise Event - PEBS)", + "BriefDescription": "Retired load uops that miss the STLB.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", + "PublicDescription": "This event counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", "SampleAfterValue": "100003", "UMask": "0x11" }, { - "BriefDescription": "Retired store uops that miss the STLB. (Precise Event - PEBS)", + "BriefDescription": "Retired store uops that miss the STLB.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts store uops true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", + "PublicDescription": "This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", "SampleAfterValue": "100003", "UMask": "0x12" }, @@ -532,10 +533,18 @@ "UMask": "0x8" }, { - "BriefDescription": "Cacheable and noncachaeble code read requests", + "BriefDescription": "Any memory transaction that reached the SQ.", + "EventCode": "0xb0", + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "PublicDescription": "This event counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, and so on.", + "SampleAfterValue": "100003", + "UMask": "0x80" + }, + { + "BriefDescription": "Cacheable and non-cacheable code read requests", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.", + "PublicDescription": "This event counts both cacheable and non-cacheable code read requests.", "SampleAfterValue": "100003", "UMask": "0x2" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json b/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json index 0b3f026158e2..e4826dc7f797 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json @@ -1,70 +1,77 @@ [ { - "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x4" }, { - "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x8" }, { - "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x10" }, { - "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x20" }, { - "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.", - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.DOUBLE", "SampleAfterValue": "2000006", "UMask": "0x15" }, { - "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.PACKED", "SampleAfterValue": "2000004", "UMask": "0x3c" }, { - "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation. Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x3" }, { - "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x2" }, { - "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.", - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SINGLE", "SampleAfterValue": "2000005", "UMask": "0x2a" diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json b/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json index d0f6678609ae..bd5da39564e1 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json @@ -125,16 +125,16 @@ "UMask": "0x4" }, { - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", - "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", "SampleAfterValue": "2000003", "UMask": "0x30" }, { - "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -143,7 +143,7 @@ "UMask": "0x10" }, { - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -153,7 +153,7 @@ "UMask": "0x10" }, { - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_UOPS", "PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", @@ -161,10 +161,10 @@ "UMask": "0x10" }, { - "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", - "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.", + "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", "UMask": "0x20" }, @@ -178,10 +178,10 @@ "UMask": "0x30" }, { - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", - "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", "SampleAfterValue": "2000003", "UMask": "0x30" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/memory.json b/tools/perf/pmu-events/arch/x86/broadwellde/memory.json index 12cc384d7f18..041b6ff4062e 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/memory.json @@ -1,10 +1,10 @@ [ { - "BriefDescription": "Number of times HLE abort was triggered (PEBS)", + "BriefDescription": "Number of times HLE abort was triggered", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED", "PEBS": "1", - "PublicDescription": "Number of times HLE abort was triggered (PEBS).", + "PublicDescription": "Number of times HLE abort was triggered.", "SampleAfterValue": "2000003", "UMask": "0x4" }, @@ -73,98 +73,106 @@ "UMask": "0x2" }, { - "BriefDescription": "Loads with latency value being above 128", + "BriefDescription": "Randomly selected loads with latency value being above 128", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "EventCode": "0xCD", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "MSRIndex": "0x3F6", "MSRValue": "0x80", "PEBS": "2", - "PublicDescription": "This event counts loads with latency value being above 128.", + "PublicDescription": "Counts randomly selected loads with latency value being above 128.", "SampleAfterValue": "1009", "UMask": "0x1" }, { - "BriefDescription": "Loads with latency value being above 16", + "BriefDescription": "Randomly selected loads with latency value being above 16", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "EventCode": "0xCD", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "MSRIndex": "0x3F6", "MSRValue": "0x10", "PEBS": "2", - "PublicDescription": "This event counts loads with latency value being above 16.", + "PublicDescription": "Counts randomly selected loads with latency value being above 16.", "SampleAfterValue": "20011", "UMask": "0x1" }, { - "BriefDescription": "Loads with latency value being above 256", + "BriefDescription": "Randomly selected loads with latency value being above 256", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "EventCode": "0xCD", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", "MSRValue": "0x100", "PEBS": "2", - "PublicDescription": "This event counts loads with latency value being above 256.", + "PublicDescription": "Counts randomly selected loads with latency value being above 256.", "SampleAfterValue": "503", "UMask": "0x1" }, { - "BriefDescription": "Loads with latency value being above 32", + "BriefDescription": "Randomly selected loads with latency value being above 32", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "EventCode": "0xCD", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "MSRIndex": "0x3F6", "MSRValue": "0x20", "PEBS": "2", - "PublicDescription": "This event counts loads with latency value being above 32.", + "PublicDescription": "Counts randomly selected loads with latency value being above 32.", "SampleAfterValue": "100007", "UMask": "0x1" }, { - "BriefDescription": "Loads with latency value being above 4", + "BriefDescription": "Randomly selected loads with latency value being above 4", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "EventCode": "0xCD", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "MSRIndex": "0x3F6", "MSRValue": "0x4", "PEBS": "2", - "PublicDescription": "This event counts loads with latency value being above four.", + "PublicDescription": "Counts randomly selected loads with latency value being above four.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Loads with latency value being above 512", + "BriefDescription": "Randomly selected loads with latency value being above 512", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "EventCode": "0xCD", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "MSRIndex": "0x3F6", "MSRValue": "0x200", "PEBS": "2", - "PublicDescription": "This event counts loads with latency value being above 512.", + "PublicDescription": "Counts randomly selected loads with latency value being above 512.", "SampleAfterValue": "101", "UMask": "0x1" }, { - "BriefDescription": "Loads with latency value being above 64", + "BriefDescription": "Randomly selected loads with latency value being above 64", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "EventCode": "0xCD", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "MSRIndex": "0x3F6", "MSRValue": "0x40", "PEBS": "2", - "PublicDescription": "This event counts loads with latency value being above 64.", + "PublicDescription": "Counts randomly selected loads with latency value being above 64.", "SampleAfterValue": "2003", "UMask": "0x1" }, { - "BriefDescription": "Loads with latency value being above 8", + "BriefDescription": "Randomly selected loads with latency value being above 8", + "Data_LA": "1", "Errata": "BDM100, BDM35", - "EventCode": "0xCD", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "MSRIndex": "0x3F6", "MSRValue": "0x8", "PEBS": "2", - "PublicDescription": "This event counts loads with latency value being above eight.", + "PublicDescription": "Counts randomly selected loads with latency value being above eight.", "SampleAfterValue": "50021", "UMask": "0x1" }, @@ -185,11 +193,11 @@ "UMask": "0x2" }, { - "BriefDescription": "Number of times RTM abort was triggered (PEBS)", + "BriefDescription": "Number of times RTM abort was triggered", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED", "PEBS": "1", - "PublicDescription": "Number of times RTM abort was triggered (PEBS).", + "PublicDescription": "Number of times RTM abort was triggered .", "SampleAfterValue": "2000003", "UMask": "0x4" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json b/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json index 9e7d66b07f01..9a902d2160e6 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json @@ -129,11 +129,11 @@ "UMask": "0x4" }, { - "BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS)", + "BriefDescription": "Conditional branch instructions retired.", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts conditional branch instructions retired.", + "PublicDescription": "This event counts conditional branch instructions retired.", "SampleAfterValue": "400009", "UMask": "0x1" }, @@ -147,38 +147,38 @@ "UMask": "0x40" }, { - "BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS)", + "BriefDescription": "Direct and indirect near call instructions retired.", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect near call instructions retired.", + "PublicDescription": "This event counts both direct and indirect near call instructions retired.", "SampleAfterValue": "100007", "UMask": "0x2" }, { - "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS)", + "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect macro near call instructions retired (captured in ring 3).", + "PublicDescription": "This event counts both direct and indirect macro near call instructions retired (captured in ring 3).", "SampleAfterValue": "100007", "UMask": "0x2" }, { - "BriefDescription": "Return instructions retired. (Precise Event - PEBS)", + "BriefDescription": "Return instructions retired.", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts return instructions retired.", + "PublicDescription": "This event counts return instructions retired.", "SampleAfterValue": "100007", "UMask": "0x8" }, { - "BriefDescription": "Taken branch instructions retired. (Precise Event - PEBS)", + "BriefDescription": "Taken branch instructions retired.", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts taken branch instructions retired.", + "PublicDescription": "This event counts taken branch instructions retired.", "SampleAfterValue": "400009", "UMask": "0x20" }, @@ -214,6 +214,14 @@ "SampleAfterValue": "200003", "UMask": "0xc4" }, + { + "BriefDescription": "Speculative mispredicted indirect branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.INDIRECT", + "PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, { "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", "EventCode": "0x89", @@ -270,29 +278,29 @@ "UMask": "0x4" }, { - "BriefDescription": "Mispredicted conditional branch instructions retired. (Precise Event - PEBS)", + "BriefDescription": "Mispredicted conditional branch instructions retired.", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts mispredicted conditional branch instructions retired.", + "PublicDescription": "This event counts mispredicted conditional branch instructions retired.", "SampleAfterValue": "400009", "UMask": "0x1" }, { - "BriefDescription": "number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS).", + "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PEBS": "1", - "PublicDescription": "Number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS).", + "PublicDescription": "Number of near branch instructions retired that were mispredicted and taken.", "SampleAfterValue": "400009", "UMask": "0x20" }, { - "BriefDescription": "This event counts the number of mispredicted ret instructions retired.(Precise Event)", + "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.RET", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts mispredicted return instructions retired.", + "PublicDescription": "This event counts mispredicted return instructions retired.", "SampleAfterValue": "100007", "UMask": "0x8" }, @@ -300,7 +308,7 @@ "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", "EventCode": "0x3c", "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "UMask": "0x2" }, { @@ -308,7 +316,7 @@ "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", "PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "UMask": "0x1" }, { @@ -316,14 +324,14 @@ "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "UMask": "0x1" }, { "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "UMask": "0x2" }, { @@ -338,7 +346,7 @@ "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK", "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "UMask": "0x1" }, { @@ -346,7 +354,7 @@ "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "UMask": "0x1" }, { @@ -500,7 +508,7 @@ "BriefDescription": "Stalls caused by changing prefix length of the instruction.", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", - "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", + "PublicDescription": "This event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", "SampleAfterValue": "2000003", "UMask": "0x1" }, @@ -681,9 +689,9 @@ }, { "BriefDescription": "Resource-related stall cycles", - "EventCode": "0xA2", + "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.ANY", - "PublicDescription": "This event counts resource-related stall cycles. Reasons for stalls can be as follows:\n - *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots)\n - *any* u-arch structure got empty (like INT/SIMD FreeLists)\n - FPU control word (FPCW), MXCSR\nand others. This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "PublicDescription": "This event counts resource-related stall cycles.", "SampleAfterValue": "2000003", "UMask": "0x1" }, @@ -909,7 +917,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in port 0.", + "BriefDescription": "Cycles per core when uops are executed in port 0.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", "SampleAfterValue": "2000003", @@ -925,7 +933,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in port 1.", + "BriefDescription": "Cycles per core when uops are executed in port 1.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", "SampleAfterValue": "2000003", @@ -973,7 +981,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in port 4.", + "BriefDescription": "Cycles per core when uops are executed in port 4.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", "SampleAfterValue": "2000003", @@ -989,7 +997,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in port 5.", + "BriefDescription": "Cycles per core when uops are executed in port 5.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", "SampleAfterValue": "2000003", @@ -1005,7 +1013,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in port 6.", + "BriefDescription": "Cycles per core when uops are executed in port 6.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", "SampleAfterValue": "2000003", @@ -1068,21 +1076,20 @@ "UMask": "0x1" }, { - "BriefDescription": "Actually retired uops. (Precise Event - PEBS)", - "Data_LA": "1", + "BriefDescription": "Actually retired uops.", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ALL", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.", + "PublicDescription": "This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Retirement slots used. (Precise Event - PEBS)", + "BriefDescription": "Retirement slots used.", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts the number of retirement slots used.", + "PublicDescription": "This event counts the number of retirement slots used.", "SampleAfterValue": "2000003", "UMask": "0x2" }, @@ -1098,7 +1105,7 @@ }, { "BriefDescription": "Cycles with less than 10 actually retired uops.", - "CounterMask": "10", + "CounterMask": "16", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", "Invert": "1", diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json index b8c9845308b2..2bf23ef7bfac 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json @@ -78,7 +78,7 @@ "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.WRITE", "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cachable and UC.", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.", "UMask": "0x5", "Unit": "CBO" }, @@ -968,7 +968,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.ALL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.", "UMask": "0x8", "Unit": "CBO" }, @@ -977,7 +977,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.EVICTION", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Eviction transactions inserted into the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Eviction transactions inserted into the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).", "UMask": "0x4", "Unit": "CBO" }, @@ -986,7 +986,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOCAL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisifed by locally HOMed memory.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x28", "Unit": "CBO" }, @@ -995,7 +995,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisifed by an opcode, inserted into the TOR that are satisifed by locally HOMed memory.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisfied by an opcode, inserted into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x21", "Unit": "CBO" }, @@ -1004,7 +1004,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by locally HOMed memory.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x2a", "Unit": "CBO" }, @@ -1013,7 +1013,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisifed by an opcode, inserted into the TOR that are satisifed by locally HOMed memory.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisfied by an opcode, inserted into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x23", "Unit": "CBO" }, @@ -1022,7 +1022,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "UMask": "0x3", "Unit": "CBO" }, @@ -1031,7 +1031,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by remote caches or remote memory.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x8a", "Unit": "CBO" }, @@ -1040,7 +1040,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisifed by an opcode, inserted into the TOR that are satisifed by remote caches or remote memory.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisfied by an opcode, inserted into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x83", "Unit": "CBO" }, @@ -1049,7 +1049,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_ALL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x48", "Unit": "CBO" }, @@ -1058,7 +1058,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction transactions inserted into the TOR.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction transactions inserted into the TOR.", "UMask": "0x44", "Unit": "CBO" }, @@ -1067,7 +1067,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.", "UMask": "0x4a", "Unit": "CBO" }, @@ -1076,7 +1076,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode.", "UMask": "0x43", "Unit": "CBO" }, @@ -1085,7 +1085,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode.", "UMask": "0x41", "Unit": "CBO" }, @@ -1094,7 +1094,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_WB", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transactions inserted into the TOR.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transactions inserted into the TOR.", "UMask": "0x50", "Unit": "CBO" }, @@ -1103,7 +1103,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "UMask": "0x1", "Unit": "CBO" }, @@ -1112,7 +1112,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.REMOTE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisifed by remote caches or remote memory.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x88", "Unit": "CBO" }, @@ -1121,7 +1121,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisifed by an opcode, inserted into the TOR that are satisifed by remote caches or remote memory.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisfied by an opcode, inserted into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x81", "Unit": "CBO" }, @@ -1130,7 +1130,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.WB", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Write transactions inserted into the TOR. This does not include RFO, but actual operations that contain data being sent from the core.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Write transactions inserted into the TOR. This does not include RFO, but actual operations that contain data being sent from the core.", "UMask": "0x10", "Unit": "CBO" }, @@ -1166,7 +1166,7 @@ "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE", "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisifed by an opcode, in the TOR that are satisifed by locally HOMed memory.", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisfied by an opcode, in the TOR that are satisfied by locally HOMed memory.", "UMask": "0x21", "Unit": "CBO" }, @@ -1193,7 +1193,7 @@ "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE", "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by locally HOMed memory.", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisfied by an opcode, in the TOR that are satisfied by locally HOMed memory.", "UMask": "0x23", "Unit": "CBO" }, @@ -1220,7 +1220,7 @@ "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE", "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by remote caches or remote memory.", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisfied by an opcode, in the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x83", "Unit": "CBO" }, @@ -1301,7 +1301,7 @@ "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE", "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisifed by an opcode, in the TOR that are satisifed by remote caches or remote memory.", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisfied by an opcode, in the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x81", "Unit": "CBO" }, @@ -1388,7 +1388,7 @@ "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.BL_CORE", "PerPkg": "1", - "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring. This is commonly used for transfering writeback data to the cache.", + "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring. This is commonly used for transferring writeback data to the cache.", "UMask": "0x40", "Unit": "CBO" }, @@ -1535,7 +1535,7 @@ "EventCode": "0x41", "EventName": "UNC_H_DIRECTORY_LAT_OPT", "PerPkg": "1", - "PublicDescription": "Directory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory retuned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc).", + "PublicDescription": "Directory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory returned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc).", "Unit": "HA" }, { @@ -2647,7 +2647,7 @@ "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", "PerPkg": "1", - "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its currentl copy. This is common for data and code reads that hit in a remote socket in E or F state.", + "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state.", "UMask": "0x8", "Unit": "HA" }, @@ -2719,7 +2719,7 @@ "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD", "PerPkg": "1", - "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its currentl copy. This is common for data and code reads that hit in a remote socket in E or F state.", + "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state.", "UMask": "0x8", "Unit": "HA" }, @@ -2931,7 +2931,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Local InvItoE Requests", + "BriefDescription": "Tracker Occupancy Accumulator; Local InvItoE Requests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL", "PerPkg": "1", @@ -2940,7 +2940,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Remote InvItoE Requests", + "BriefDescription": "Tracker Occupancy Accumulator; Remote InvItoE Requests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE", "PerPkg": "1", @@ -2949,7 +2949,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Local Read Requests", + "BriefDescription": "Tracker Occupancy Accumulator; Local Read Requests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_LOCAL", "PerPkg": "1", @@ -2958,7 +2958,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Remote Read Requests", + "BriefDescription": "Tracker Occupancy Accumulator; Remote Read Requests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_REMOTE", "PerPkg": "1", @@ -2967,7 +2967,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Local Write Requests", + "BriefDescription": "Tracker Occupancy Accumulator; Local Write Requests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL", "PerPkg": "1", @@ -2976,7 +2976,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Remote Write Requests", + "BriefDescription": "Tracker Occupancy Accumulator; Remote Write Requests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE", "PerPkg": "1", @@ -2985,7 +2985,7 @@ "Unit": "HA" }, { - "BriefDescription": "Data Pending Occupancy Accumultor; Local Requests", + "BriefDescription": "Data Pending Occupancy Accumulator; Local Requests", "EventCode": "0x5", "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL", "PerPkg": "1", @@ -2994,7 +2994,7 @@ "Unit": "HA" }, { - "BriefDescription": "Data Pending Occupancy Accumultor; Remote Requests", + "BriefDescription": "Data Pending Occupancy Accumulator; Remote Requests", "EventCode": "0x5", "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json index c3f2f6c2ac74..a764234a3584 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json @@ -166,7 +166,7 @@ "EventCode": "0x9", "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", "PerPkg": "1", - "PublicDescription": "Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit erros in lockstep mode.", + "PublicDescription": "Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit errors in lockstep mode.", "Unit": "iMC" }, { @@ -302,6 +302,7 @@ "Unit": "iMC" }, { + "BriefDescription": "UNC_M_POWER_PCU_THROTTLING", "EventCode": "0x42", "EventName": "UNC_M_POWER_PCU_THROTTLING", "PerPkg": "1", @@ -487,6 +488,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -495,6 +497,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -502,6 +505,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK1", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -510,6 +514,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK10", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -518,6 +523,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK11", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -526,6 +532,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK12", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -534,6 +541,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK13", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -542,6 +550,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK14", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -550,6 +559,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK15", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -558,6 +568,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK2", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -566,6 +577,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK3", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -574,6 +586,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK4", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -582,6 +595,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK5", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -590,6 +604,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK6", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -598,6 +613,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK7", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -606,6 +622,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK8", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -614,6 +631,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK9", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -622,6 +640,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -630,6 +649,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG1", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -638,6 +658,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG2", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -646,6 +667,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG3", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -654,6 +676,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -662,6 +685,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -669,6 +693,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK1", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -677,6 +702,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK10", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -685,6 +711,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK11", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -693,6 +720,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK12", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -701,6 +729,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK13", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -709,6 +738,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK14", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -717,6 +747,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK15", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -725,6 +756,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK2", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -733,6 +765,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK3", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -741,6 +774,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK4", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -749,6 +783,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK5", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -757,6 +792,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK6", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -765,6 +801,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK7", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -773,6 +810,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK8", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -781,6 +819,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK9", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -789,6 +828,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -797,6 +837,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG1", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -805,6 +846,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG2", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -813,6 +855,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG3", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -821,6 +864,7 @@ "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -828,6 +872,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -836,6 +881,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -843,6 +889,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK1", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -851,6 +898,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK10", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -859,6 +907,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK11", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -867,6 +916,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK12", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -875,6 +925,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK13", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -883,6 +934,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK14", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -891,6 +943,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK15", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -899,6 +952,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK2", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -907,6 +961,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK3", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -915,6 +970,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK4", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -923,6 +979,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK5", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -931,6 +988,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK6", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -939,6 +997,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK7", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -947,6 +1006,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK8", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -955,6 +1015,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK9", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -963,6 +1024,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -971,6 +1033,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG1", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -979,6 +1042,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG2", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -987,6 +1051,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG3", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -995,6 +1060,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -1003,6 +1069,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -1010,6 +1077,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK1", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -1018,6 +1086,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK10", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -1026,6 +1095,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK11", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -1034,6 +1104,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK12", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -1042,6 +1113,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK13", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -1050,6 +1122,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK14", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -1058,6 +1131,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK15", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -1066,6 +1140,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK2", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -1074,6 +1149,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK3", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -1082,6 +1158,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK4", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -1090,6 +1167,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK5", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -1098,6 +1176,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK6", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -1106,6 +1185,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK7", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -1114,6 +1194,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK8", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -1122,6 +1203,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK9", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -1130,6 +1212,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -1138,6 +1221,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG1", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -1146,6 +1230,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG2", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -1154,6 +1239,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG3", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -1162,6 +1248,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -1170,6 +1257,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -1177,6 +1265,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK1", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -1185,6 +1274,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK10", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -1193,6 +1283,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK11", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -1201,6 +1292,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK12", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -1209,6 +1301,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK13", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -1217,6 +1310,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK14", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -1225,6 +1319,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK15", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -1233,6 +1328,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK2", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -1241,6 +1337,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK3", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -1249,6 +1346,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK4", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -1257,6 +1355,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK5", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -1265,6 +1364,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK6", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -1273,6 +1373,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK7", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -1281,6 +1382,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK8", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -1289,6 +1391,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK9", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -1297,6 +1400,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -1305,6 +1409,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG1", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -1313,6 +1418,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG2", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -1321,6 +1427,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG3", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -1329,6 +1436,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -1337,6 +1445,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -1344,6 +1453,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK1", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -1352,6 +1462,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK10", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -1360,6 +1471,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK11", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -1368,6 +1480,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK12", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -1376,6 +1489,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK13", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -1384,6 +1498,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK14", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -1392,6 +1507,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK15", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -1400,6 +1516,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK2", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -1408,6 +1525,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK3", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -1416,6 +1534,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK4", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -1424,6 +1543,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK5", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -1432,6 +1552,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK6", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -1440,6 +1561,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK7", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -1448,6 +1570,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK8", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -1456,6 +1579,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK9", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -1464,6 +1588,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG0", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -1472,6 +1597,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG1", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -1480,6 +1606,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG2", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -1488,6 +1615,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG3", "PerPkg": "1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -1598,6 +1726,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -1606,6 +1735,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK0", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -1613,6 +1743,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK1", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -1621,6 +1752,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK10", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -1629,6 +1761,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK11", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -1637,6 +1770,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK12", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -1645,6 +1779,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK13", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -1653,6 +1788,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK14", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -1661,6 +1797,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK15", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -1669,6 +1806,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK2", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -1677,6 +1815,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK3", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -1685,6 +1824,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK4", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -1693,6 +1833,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK5", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -1701,6 +1842,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK6", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -1709,6 +1851,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK7", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -1717,6 +1860,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK8", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -1725,6 +1869,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK9", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -1733,6 +1878,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG0", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -1741,6 +1887,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG1", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -1749,6 +1896,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG2", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -1757,6 +1905,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG3", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -1765,6 +1914,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -1773,6 +1923,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK0", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -1780,6 +1931,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK1", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -1788,6 +1940,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK10", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -1796,6 +1949,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK11", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -1804,6 +1958,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK12", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -1812,6 +1967,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK13", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -1820,6 +1976,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK14", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -1828,6 +1985,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK15", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -1836,6 +1994,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK2", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -1844,6 +2003,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK3", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -1852,6 +2012,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK4", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -1860,6 +2021,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK5", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -1868,6 +2030,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK6", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -1876,6 +2039,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK7", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -1884,6 +2048,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK8", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -1892,6 +2057,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK9", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -1900,6 +2066,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG0", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -1908,6 +2075,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG1", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -1916,6 +2084,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG2", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -1924,6 +2093,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG3", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -1932,6 +2102,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -1940,6 +2111,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK0", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -1947,6 +2119,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK1", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -1955,6 +2128,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK10", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -1963,6 +2137,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK11", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -1971,6 +2146,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK12", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -1979,6 +2155,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK13", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -1987,6 +2164,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK14", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -1995,6 +2173,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK15", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -2003,6 +2182,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK2", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -2011,6 +2191,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK3", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -2019,6 +2200,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK4", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -2027,6 +2209,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK5", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -2035,6 +2218,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK6", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -2043,6 +2227,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK7", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -2051,6 +2236,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK8", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -2059,6 +2245,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK9", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -2067,6 +2254,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG0", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -2075,6 +2263,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG1", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -2083,6 +2272,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG2", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -2091,6 +2281,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG3", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -2099,6 +2290,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -2107,6 +2299,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK0", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -2114,6 +2307,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK1", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -2122,6 +2316,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK10", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -2130,6 +2325,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK11", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -2138,6 +2334,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK12", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -2146,6 +2343,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK13", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -2154,6 +2352,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK14", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -2162,6 +2361,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK15", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -2170,6 +2370,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK2", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -2178,6 +2379,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK3", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -2186,6 +2388,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK4", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -2194,6 +2397,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK5", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -2202,6 +2406,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK6", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -2210,6 +2415,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK7", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -2218,6 +2424,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK8", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -2226,6 +2433,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK9", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -2234,6 +2442,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG0", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -2242,6 +2451,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG1", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -2250,6 +2460,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG2", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -2258,6 +2469,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG3", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -2266,6 +2478,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -2274,6 +2487,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK0", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -2281,6 +2495,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK1", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -2289,6 +2504,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK10", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -2297,6 +2513,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK11", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -2305,6 +2522,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK12", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -2313,6 +2531,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK13", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -2321,6 +2540,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK14", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -2329,6 +2549,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK15", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -2337,6 +2558,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK2", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -2345,6 +2567,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK3", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -2353,6 +2576,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK4", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -2361,6 +2585,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK5", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -2369,6 +2594,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK6", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -2377,6 +2603,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK7", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -2385,6 +2612,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK8", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -2393,6 +2621,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK9", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -2401,6 +2630,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG0", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -2409,6 +2639,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG1", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -2417,6 +2648,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG2", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -2425,6 +2657,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG3", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -2433,6 +2666,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -2441,6 +2675,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK0", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -2448,6 +2683,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK1", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -2456,6 +2692,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK10", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -2464,6 +2701,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK11", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -2472,6 +2710,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK12", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -2480,6 +2719,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK13", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -2488,6 +2728,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK14", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -2496,6 +2737,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK15", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -2504,6 +2746,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK2", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -2512,6 +2755,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK3", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -2520,6 +2764,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK4", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -2528,6 +2773,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK5", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -2536,6 +2782,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK6", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -2544,6 +2791,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK7", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -2552,6 +2800,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK8", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -2560,6 +2809,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK9", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -2568,6 +2818,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG0", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -2576,6 +2827,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG1", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -2584,6 +2836,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG2", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -2592,6 +2845,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG3", "PerPkg": "1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)", "UMask": "0x14", "Unit": "iMC" } diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json index 753b381b77fe..fea3dea67f38 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json @@ -101,6 +101,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", "PerPkg": "1", + "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary", "UMask": "0x10", "Unit": "IRP" }, @@ -109,6 +110,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.2ND_RD_INSERT", "PerPkg": "1", + "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary", "UMask": "0x4", "Unit": "IRP" }, @@ -117,6 +119,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.2ND_WR_INSERT", "PerPkg": "1", + "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary", "UMask": "0x8", "Unit": "IRP" }, @@ -125,6 +128,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.FAST_REJ", "PerPkg": "1", + "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", "UMask": "0x2", "Unit": "IRP" }, @@ -133,6 +137,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.FAST_REQ", "PerPkg": "1", + "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Requests", "UMask": "0x1", "Unit": "IRP" }, @@ -141,6 +146,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.FAST_XFER", "PerPkg": "1", + "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary", "UMask": "0x20", "Unit": "IRP" }, @@ -149,6 +155,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.PF_ACK_HINT", "PerPkg": "1", + "PublicDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary", "UMask": "0x40", "Unit": "IRP" }, @@ -175,6 +182,7 @@ "EventCode": "0x15", "EventName": "UNC_I_MISC1.LOST_FWD", "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed", "UMask": "0x10", "Unit": "IRP" }, @@ -241,6 +249,7 @@ "Unit": "IRP" }, { + "BriefDescription": "UNC_I_RxR_BL_DRS_CYCLES_FULL", "EventCode": "0x4", "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", "PerPkg": "1", @@ -256,6 +265,7 @@ "Unit": "IRP" }, { + "BriefDescription": "UNC_I_RxR_BL_DRS_OCCUPANCY", "EventCode": "0x7", "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", "PerPkg": "1", @@ -263,6 +273,7 @@ "Unit": "IRP" }, { + "BriefDescription": "UNC_I_RxR_BL_NCB_CYCLES_FULL", "EventCode": "0x5", "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", "PerPkg": "1", @@ -278,6 +289,7 @@ "Unit": "IRP" }, { + "BriefDescription": "UNC_I_RxR_BL_NCB_OCCUPANCY", "EventCode": "0x8", "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", "PerPkg": "1", @@ -285,6 +297,7 @@ "Unit": "IRP" }, { + "BriefDescription": "UNC_I_RxR_BL_NCS_CYCLES_FULL", "EventCode": "0x6", "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", "PerPkg": "1", @@ -300,6 +313,7 @@ "Unit": "IRP" }, { + "BriefDescription": "UNC_I_RxR_BL_NCS_OCCUPANCY", "EventCode": "0x9", "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", "PerPkg": "1", @@ -311,6 +325,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.HIT_ES", "PerPkg": "1", + "PublicDescription": "Snoop Responses : Hit E or S", "UMask": "0x4", "Unit": "IRP" }, @@ -319,6 +334,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.HIT_I", "PerPkg": "1", + "PublicDescription": "Snoop Responses : Hit I", "UMask": "0x2", "Unit": "IRP" }, @@ -327,6 +343,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.HIT_M", "PerPkg": "1", + "PublicDescription": "Snoop Responses : Hit M", "UMask": "0x8", "Unit": "IRP" }, @@ -335,6 +352,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.MISS", "PerPkg": "1", + "PublicDescription": "Snoop Responses : Miss", "UMask": "0x1", "Unit": "IRP" }, @@ -343,6 +361,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.SNPCODE", "PerPkg": "1", + "PublicDescription": "Snoop Responses : SnpCode", "UMask": "0x10", "Unit": "IRP" }, @@ -351,6 +370,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.SNPDATA", "PerPkg": "1", + "PublicDescription": "Snoop Responses : SnpData", "UMask": "0x20", "Unit": "IRP" }, @@ -359,6 +379,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.SNPINV", "PerPkg": "1", + "PublicDescription": "Snoop Responses : SnpInv", "UMask": "0x40", "Unit": "IRP" }, @@ -453,7 +474,7 @@ "EventCode": "0xD", "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.", + "PublicDescription": "Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.", "Unit": "IRP" }, { @@ -465,6 +486,7 @@ "Unit": "R2PCIe" }, { + "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI0", "EventCode": "0x2D", "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0", "PerPkg": "1", @@ -472,6 +494,7 @@ "Unit": "R2PCIe" }, { + "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI1", "EventCode": "0x2D", "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1", "PerPkg": "1", @@ -479,6 +502,7 @@ "Unit": "R2PCIe" }, { + "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI0", "EventCode": "0x2D", "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0", "PerPkg": "1", @@ -486,6 +510,7 @@ "Unit": "R2PCIe" }, { + "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI1", "EventCode": "0x2D", "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json index 124b3fe2e0e1..83d20130c217 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json @@ -395,7 +395,7 @@ "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", "PerPkg": "1", - "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", + "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", "Unit": "PCU" }, { @@ -403,7 +403,7 @@ "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", "PerPkg": "1", - "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", + "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", "Unit": "PCU" }, { @@ -411,7 +411,7 @@ "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", "PerPkg": "1", - "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", + "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", "Unit": "PCU" }, { @@ -427,7 +427,7 @@ "EventCode": "0x9", "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that we are in Interal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.", + "PublicDescription": "Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.", "Unit": "PCU" }, { @@ -439,6 +439,7 @@ "Unit": "PCU" }, { + "BriefDescription": "UNC_P_UFS_TRANSITIONS_RING_GV", "EventCode": "0x79", "EventName": "UNC_P_UFS_TRANSITIONS_RING_GV", "PerPkg": "1", @@ -450,6 +451,7 @@ "EventCode": "0x42", "EventName": "UNC_P_VR_HOT_CYCLES", "PerPkg": "1", + "PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR is hot. Does not cover DRAM VRs", "Unit": "PCU" } ] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 70be860bcb53..4fa827c7f719 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -3,7 +3,7 @@ GenuineIntel-6-(97|9A|B7|BA|BF),v1.19,alderlake,core GenuineIntel-6-BE,v1.19,alderlaken,core GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core GenuineIntel-6-(3D|47),v27,broadwell,core -GenuineIntel-6-56,v7,broadwellde,core +GenuineIntel-6-56,v9,broadwellde,core GenuineIntel-6-4F,v19,broadwellx,core GenuineIntel-6-55-[56789ABCDEF],v1.17,cascadelakex,core GenuineIntel-6-9[6C],v1.03,elkhartlake,core -- cgit v1.2.3-58-ga151 From 74a87b6aa275ced4908cd04ba443e49cda2294e1 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 24 Mar 2023 00:22:12 -0700 Subject: perf vendor events intel: Broadwellx v20 events Updates descriptions and encodings. Adds BR_MISP_EXEC.INDIRECT events. Reviewed-by: Kan Liang Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Dan Williams Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Samantha Alt Cc: Weilin Wang Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230324072218.181880-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../perf/pmu-events/arch/x86/broadwellx/cache.json | 16 +- .../pmu-events/arch/x86/broadwellx/frontend.json | 18 +- .../pmu-events/arch/x86/broadwellx/pipeline.json | 20 +- .../arch/x86/broadwellx/uncore-cache.json | 156 ++---- .../arch/x86/broadwellx/uncore-interconnect.json | 84 ++-- .../arch/x86/broadwellx/uncore-memory.json | 522 ++++++++++----------- .../arch/x86/broadwellx/uncore-other.json | 44 +- .../arch/x86/broadwellx/uncore-power.json | 10 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 9 files changed, 403 insertions(+), 469 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/cache.json b/tools/perf/pmu-events/arch/x86/broadwellx/cache.json index 6a134928b3f0..781e7c64e71f 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/cache.json @@ -8,7 +8,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", @@ -16,7 +16,7 @@ "UMask": "0x2" }, { - "BriefDescription": "L1D miss oustandings duration in cycles", + "BriefDescription": "L1D miss outstandings duration in cycles", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", @@ -454,22 +454,22 @@ "UMask": "0x20" }, { - "BriefDescription": "All retired load uops.", + "BriefDescription": "Retired load uops.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "PEBS": "1", - "PublicDescription": "This event counts load uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.", + "PublicDescription": "Counts all retired load uops. This event accounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.", "SampleAfterValue": "2000003", "UMask": "0x81" }, { - "BriefDescription": "All retired store uops.", + "BriefDescription": "Retired store uops.", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", "PEBS": "1", - "PublicDescription": "This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement.", + "PublicDescription": "Counts all retired store uops.", "SampleAfterValue": "2000003", "UMask": "0x82" }, @@ -541,10 +541,10 @@ "UMask": "0x80" }, { - "BriefDescription": "Cacheable and noncachaeble code read requests", + "BriefDescription": "Cacheable and non-cacheable code read requests", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.", + "PublicDescription": "This event counts both cacheable and non-cacheable code read requests.", "SampleAfterValue": "100003", "UMask": "0x2" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json b/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json index d0f6678609ae..bd5da39564e1 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json @@ -125,16 +125,16 @@ "UMask": "0x4" }, { - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", - "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", "SampleAfterValue": "2000003", "UMask": "0x30" }, { - "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -143,7 +143,7 @@ "UMask": "0x10" }, { - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -153,7 +153,7 @@ "UMask": "0x10" }, { - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_UOPS", "PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", @@ -161,10 +161,10 @@ "UMask": "0x10" }, { - "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", - "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.", + "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", "UMask": "0x20" }, @@ -178,10 +178,10 @@ "UMask": "0x30" }, { - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", - "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", "SampleAfterValue": "2000003", "UMask": "0x30" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json b/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json index 75233316640b..9a902d2160e6 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json @@ -214,6 +214,14 @@ "SampleAfterValue": "200003", "UMask": "0xc4" }, + { + "BriefDescription": "Speculative mispredicted indirect branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.INDIRECT", + "PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, { "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", "EventCode": "0x89", @@ -500,7 +508,7 @@ "BriefDescription": "Stalls caused by changing prefix length of the instruction.", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", - "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", + "PublicDescription": "This event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", "SampleAfterValue": "2000003", "UMask": "0x1" }, @@ -909,7 +917,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in port 0.", + "BriefDescription": "Cycles per core when uops are executed in port 0.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", "SampleAfterValue": "2000003", @@ -925,7 +933,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in port 1.", + "BriefDescription": "Cycles per core when uops are executed in port 1.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", "SampleAfterValue": "2000003", @@ -973,7 +981,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in port 4.", + "BriefDescription": "Cycles per core when uops are executed in port 4.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", "SampleAfterValue": "2000003", @@ -989,7 +997,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in port 5.", + "BriefDescription": "Cycles per core when uops are executed in port 5.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", "SampleAfterValue": "2000003", @@ -1005,7 +1013,7 @@ }, { "AnyThread": "1", - "BriefDescription": "Cycles per core when uops are exectuted in port 6.", + "BriefDescription": "Cycles per core when uops are executed in port 6.", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", "SampleAfterValue": "2000003", diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json index 746954775437..f794d2992323 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json @@ -5,7 +5,7 @@ "EventName": "LLC_MISSES.CODE_LLC_PREFETCH", "Filter": "filter_opc=0x191", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -16,7 +16,7 @@ "EventName": "LLC_MISSES.DATA_LLC_PREFETCH", "Filter": "filter_opc=0x192", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -27,7 +27,7 @@ "EventName": "LLC_MISSES.DATA_READ", "Filter": "filter_opc=0x182", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -38,7 +38,7 @@ "EventName": "LLC_MISSES.MMIO_READ", "Filter": "filter_opc=0x187,filter_nc=1", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -49,7 +49,7 @@ "EventName": "LLC_MISSES.MMIO_WRITE", "Filter": "filter_opc=0x18f,filter_nc=1", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -60,7 +60,7 @@ "EventName": "LLC_MISSES.PCIE_NON_SNOOP_WRITE", "Filter": "filter_opc=0x1c8,filter_tid=0x3e", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -71,7 +71,7 @@ "EventName": "LLC_MISSES.PCIE_READ", "Filter": "filter_opc=0x19e", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -82,7 +82,7 @@ "EventName": "LLC_MISSES.PCIE_WRITE", "Filter": "filter_opc=0x1c8", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -93,7 +93,7 @@ "EventName": "LLC_MISSES.RFO_LLC_PREFETCH", "Filter": "filter_opc=0x190", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -104,7 +104,7 @@ "EventName": "LLC_MISSES.UNCACHEABLE", "Filter": "filter_opc=0x187", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", "Unit": "CBO" @@ -115,7 +115,7 @@ "EventName": "LLC_REFERENCES.CODE_LLC_PREFETCH", "Filter": "filter_opc=0x181", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", "Unit": "CBO" @@ -126,7 +126,7 @@ "EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE", "Filter": "filter_opc=0x180,filter_tid=0x3e", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "UMask": "0x1", "Unit": "CBO" }, @@ -136,7 +136,7 @@ "EventName": "LLC_REFERENCES.PCIE_READ", "Filter": "filter_opc=0x19e", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", "Unit": "CBO" @@ -147,7 +147,7 @@ "EventName": "LLC_REFERENCES.PCIE_WRITE", "Filter": "filter_opc=0x1c8,filter_tid=0x3e", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", "Unit": "CBO" @@ -158,7 +158,7 @@ "EventName": "LLC_REFERENCES.STREAMING_FULL", "Filter": "filter_opc=0x18c", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", "Unit": "CBO" @@ -169,7 +169,7 @@ "EventName": "LLC_REFERENCES.STREAMING_PARTIAL", "Filter": "filter_opc=0x18d", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", "Unit": "CBO" @@ -179,14 +179,12 @@ "EventCode": "0xA", "EventName": "UNC_C_BOUNCE_CONTROL", "PerPkg": "1", - "PublicDescription": "UNC_C_BOUNCE_CONTROL", "Unit": "CBO" }, { "BriefDescription": "Uncore Clocks", "EventName": "UNC_C_CLOCKTICKS", "PerPkg": "1", - "PublicDescription": "UNC_C_CLOCKTICKS", "Unit": "CBO" }, { @@ -257,7 +255,7 @@ "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.WRITE", "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cachable and UC.", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.", "UMask": "0x5", "Unit": "CBO" }, @@ -618,7 +616,6 @@ "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.AD", "PerPkg": "1", - "PublicDescription": "UNC_C_RING_BOUNCES.AD", "UMask": "0x1", "Unit": "CBO" }, @@ -627,7 +624,6 @@ "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.AK", "PerPkg": "1", - "PublicDescription": "UNC_C_RING_BOUNCES.AK", "UMask": "0x2", "Unit": "CBO" }, @@ -636,7 +632,6 @@ "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.BL", "PerPkg": "1", - "PublicDescription": "UNC_C_RING_BOUNCES.BL", "UMask": "0x4", "Unit": "CBO" }, @@ -645,7 +640,6 @@ "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.IV", "PerPkg": "1", - "PublicDescription": "UNC_C_RING_BOUNCES.IV", "UMask": "0x10", "Unit": "CBO" }, @@ -690,7 +684,6 @@ "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.AD", "PerPkg": "1", - "PublicDescription": "UNC_C_RING_SINK_STARVED.AD", "UMask": "0x1", "Unit": "CBO" }, @@ -699,7 +692,6 @@ "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.AK", "PerPkg": "1", - "PublicDescription": "UNC_C_RING_SINK_STARVED.AK", "UMask": "0x2", "Unit": "CBO" }, @@ -708,7 +700,6 @@ "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.BL", "PerPkg": "1", - "PublicDescription": "UNC_C_RING_SINK_STARVED.BL", "UMask": "0x4", "Unit": "CBO" }, @@ -717,7 +708,6 @@ "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.IV", "PerPkg": "1", - "PublicDescription": "UNC_C_RING_SINK_STARVED.IV", "UMask": "0x8", "Unit": "CBO" }, @@ -726,7 +716,6 @@ "EventCode": "0x7", "EventName": "UNC_C_RING_SRC_THRTL", "PerPkg": "1", - "PublicDescription": "UNC_C_RING_SRC_THRTL", "Unit": "CBO" }, { @@ -1157,7 +1146,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.ALL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.", "UMask": "0x8", "Unit": "CBO" }, @@ -1166,7 +1155,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.EVICTION", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Eviction transactions inserted into the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Eviction transactions inserted into the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).", "UMask": "0x4", "Unit": "CBO" }, @@ -1175,7 +1164,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOCAL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisifed by locally HOMed memory.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x28", "Unit": "CBO" }, @@ -1184,7 +1173,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisifed by an opcode, inserted into the TOR that are satisifed by locally HOMed memory.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisfied by an opcode, inserted into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x21", "Unit": "CBO" }, @@ -1193,7 +1182,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by locally HOMed memory.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x2a", "Unit": "CBO" }, @@ -1202,7 +1191,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisifed by an opcode, inserted into the TOR that are satisifed by locally HOMed memory.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisfied by an opcode, inserted into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x23", "Unit": "CBO" }, @@ -1211,7 +1200,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "UMask": "0x3", "Unit": "CBO" }, @@ -1220,7 +1209,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by remote caches or remote memory.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x8a", "Unit": "CBO" }, @@ -1229,7 +1218,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisifed by an opcode, inserted into the TOR that are satisifed by remote caches or remote memory.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisfied by an opcode, inserted into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x83", "Unit": "CBO" }, @@ -1238,7 +1227,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_ALL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x48", "Unit": "CBO" }, @@ -1247,7 +1236,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction transactions inserted into the TOR.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction transactions inserted into the TOR.", "UMask": "0x44", "Unit": "CBO" }, @@ -1256,7 +1245,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.", "UMask": "0x4a", "Unit": "CBO" }, @@ -1265,7 +1254,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode.", "UMask": "0x43", "Unit": "CBO" }, @@ -1274,7 +1263,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode.", "UMask": "0x41", "Unit": "CBO" }, @@ -1283,7 +1272,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_WB", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transactions inserted into the TOR.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transactions inserted into the TOR.", "UMask": "0x50", "Unit": "CBO" }, @@ -1292,7 +1281,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "UMask": "0x1", "Unit": "CBO" }, @@ -1301,7 +1290,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.REMOTE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisifed by remote caches or remote memory.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x88", "Unit": "CBO" }, @@ -1310,7 +1299,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisifed by an opcode, inserted into the TOR that are satisifed by remote caches or remote memory.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisfied by an opcode, inserted into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x81", "Unit": "CBO" }, @@ -1319,7 +1308,7 @@ "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.WB", "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Write transactions inserted into the TOR. This does not include RFO, but actual operations that contain data being sent from the core.", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Write transactions inserted into the TOR. This does not include RFO, but actual operations that contain data being sent from the core.", "UMask": "0x10", "Unit": "CBO" }, @@ -1365,7 +1354,7 @@ "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE", "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisifed by an opcode, in the TOR that are satisifed by locally HOMed memory.", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisfied by an opcode, in the TOR that are satisfied by locally HOMed memory.", "UMask": "0x21", "Unit": "CBO" }, @@ -1392,7 +1381,7 @@ "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE", "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by locally HOMed memory.", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisfied by an opcode, in the TOR that are satisfied by locally HOMed memory.", "UMask": "0x23", "Unit": "CBO" }, @@ -1419,7 +1408,7 @@ "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE", "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by remote caches or remote memory.", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisfied by an opcode, in the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x83", "Unit": "CBO" }, @@ -1500,7 +1489,7 @@ "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE", "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisifed by an opcode, in the TOR that are satisifed by remote caches or remote memory.", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisfied by an opcode, in the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x81", "Unit": "CBO" }, @@ -1518,7 +1507,6 @@ "EventCode": "0x4", "EventName": "UNC_C_TxR_ADS_USED.AD", "PerPkg": "1", - "PublicDescription": "UNC_C_TxR_ADS_USED.AD", "UMask": "0x1", "Unit": "CBO" }, @@ -1527,7 +1515,6 @@ "EventCode": "0x4", "EventName": "UNC_C_TxR_ADS_USED.AK", "PerPkg": "1", - "PublicDescription": "UNC_C_TxR_ADS_USED.AK", "UMask": "0x2", "Unit": "CBO" }, @@ -1536,7 +1523,6 @@ "EventCode": "0x4", "EventName": "UNC_C_TxR_ADS_USED.BL", "PerPkg": "1", - "PublicDescription": "UNC_C_TxR_ADS_USED.BL", "UMask": "0x4", "Unit": "CBO" }, @@ -1590,7 +1576,7 @@ "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.BL_CORE", "PerPkg": "1", - "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring. This is commonly used for transfering writeback data to the cache.", + "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring. This is commonly used for transferring writeback data to the cache.", "UMask": "0x40", "Unit": "CBO" }, @@ -1737,7 +1723,7 @@ "EventCode": "0x41", "EventName": "UNC_H_DIRECTORY_LAT_OPT", "PerPkg": "1", - "PublicDescription": "Directory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory retuned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc).", + "PublicDescription": "Directory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory returned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc).", "Unit": "HA" }, { @@ -1790,7 +1776,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.ACKCNFLTWBI", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.ACKCNFLTWBI", "UMask": "0x4", "Unit": "HA" }, @@ -1799,7 +1784,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.ALL", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.ALL", "UMask": "0xff", "Unit": "HA" }, @@ -1808,7 +1792,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.ALLOCS", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.ALLOCS", "UMask": "0x70", "Unit": "HA" }, @@ -1817,7 +1800,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.EVICTS", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.EVICTS", "UMask": "0x42", "Unit": "HA" }, @@ -1826,7 +1808,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.HOM", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.HOM", "UMask": "0xf", "Unit": "HA" }, @@ -1835,7 +1816,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.INVALS", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.INVALS", "UMask": "0x26", "Unit": "HA" }, @@ -1844,7 +1824,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.READ_OR_INVITOE", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.READ_OR_INVITOE", "UMask": "0x1", "Unit": "HA" }, @@ -1853,7 +1832,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.RSP", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.RSP", "UMask": "0x80", "Unit": "HA" }, @@ -1862,7 +1840,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.RSPFWDI_LOCAL", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.RSPFWDI_LOCAL", "UMask": "0x20", "Unit": "HA" }, @@ -1871,7 +1848,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.RSPFWDI_REMOTE", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.RSPFWDI_REMOTE", "UMask": "0x10", "Unit": "HA" }, @@ -1880,7 +1856,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.RSPFWDS", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.RSPFWDS", "UMask": "0x40", "Unit": "HA" }, @@ -1889,7 +1864,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.WBMTOE_OR_S", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.WBMTOE_OR_S", "UMask": "0x8", "Unit": "HA" }, @@ -1898,7 +1872,6 @@ "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.WBMTOI", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT.WBMTOI", "UMask": "0x2", "Unit": "HA" }, @@ -1907,7 +1880,6 @@ "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI", "UMask": "0x4", "Unit": "HA" }, @@ -1916,7 +1888,6 @@ "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ALL", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.ALL", "UMask": "0xff", "Unit": "HA" }, @@ -1925,7 +1896,6 @@ "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.HOM", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.HOM", "UMask": "0xf", "Unit": "HA" }, @@ -1934,7 +1904,6 @@ "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE", "UMask": "0x1", "Unit": "HA" }, @@ -1943,7 +1912,6 @@ "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSP", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.RSP", "UMask": "0x80", "Unit": "HA" }, @@ -1952,7 +1920,6 @@ "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL", "UMask": "0x20", "Unit": "HA" }, @@ -1961,7 +1928,6 @@ "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE", "UMask": "0x10", "Unit": "HA" }, @@ -1970,7 +1936,6 @@ "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS", "UMask": "0x40", "Unit": "HA" }, @@ -1979,7 +1944,6 @@ "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S", "UMask": "0x8", "Unit": "HA" }, @@ -1988,7 +1952,6 @@ "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI", "UMask": "0x2", "Unit": "HA" }, @@ -1997,7 +1960,6 @@ "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI", "UMask": "0x4", "Unit": "HA" }, @@ -2006,7 +1968,6 @@ "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.ALL", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_LOOKUP.ALL", "UMask": "0xff", "Unit": "HA" }, @@ -2015,7 +1976,6 @@ "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.ALLOCS", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_LOOKUP.ALLOCS", "UMask": "0x70", "Unit": "HA" }, @@ -2024,7 +1984,6 @@ "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.HOM", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_LOOKUP.HOM", "UMask": "0xf", "Unit": "HA" }, @@ -2033,7 +1992,6 @@ "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.INVALS", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_LOOKUP.INVALS", "UMask": "0x26", "Unit": "HA" }, @@ -2042,7 +2000,6 @@ "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE", "UMask": "0x1", "Unit": "HA" }, @@ -2051,7 +2008,6 @@ "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.RSP", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_LOOKUP.RSP", "UMask": "0x80", "Unit": "HA" }, @@ -2060,7 +2016,6 @@ "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL", "UMask": "0x20", "Unit": "HA" }, @@ -2069,7 +2024,6 @@ "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE", "UMask": "0x10", "Unit": "HA" }, @@ -2078,7 +2032,6 @@ "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.RSPFWDS", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_LOOKUP.RSPFWDS", "UMask": "0x40", "Unit": "HA" }, @@ -2087,7 +2040,6 @@ "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S", "UMask": "0x8", "Unit": "HA" }, @@ -2096,7 +2048,6 @@ "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.WBMTOI", "PerPkg": "1", - "PublicDescription": "UNC_H_HITME_LOOKUP.WBMTOI", "UMask": "0x2", "Unit": "HA" }, @@ -2168,7 +2119,6 @@ "EventCode": "0x1E", "EventName": "UNC_H_IMC_RETRY", "PerPkg": "1", - "PublicDescription": "UNC_H_IMC_RETRY", "Unit": "HA" }, { @@ -2221,7 +2171,6 @@ "EventCode": "0x61", "EventName": "UNC_H_IOT_BACKPRESSURE.HUB", "PerPkg": "1", - "PublicDescription": "UNC_H_IOT_BACKPRESSURE.HUB", "UMask": "0x2", "Unit": "HA" }, @@ -2230,7 +2179,6 @@ "EventCode": "0x61", "EventName": "UNC_H_IOT_BACKPRESSURE.SAT", "PerPkg": "1", - "PublicDescription": "UNC_H_IOT_BACKPRESSURE.SAT", "UMask": "0x1", "Unit": "HA" }, @@ -2889,7 +2837,7 @@ "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", "PerPkg": "1", - "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its currentl copy. This is common for data and code reads that hit in a remote socket in E or F state.", + "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state.", "ScaleUnit": "64Bytes", "UMask": "0x8", "Unit": "HA" @@ -2963,7 +2911,7 @@ "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD", "PerPkg": "1", - "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its currentl copy. This is common for data and code reads that hit in a remote socket in E or F state.", + "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state.", "UMask": "0x8", "Unit": "HA" }, @@ -3175,7 +3123,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Local InvItoE Requests", + "BriefDescription": "Tracker Occupancy Accumulator; Local InvItoE Requests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL", "PerPkg": "1", @@ -3184,7 +3132,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Remote InvItoE Requests", + "BriefDescription": "Tracker Occupancy Accumulator; Remote InvItoE Requests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE", "PerPkg": "1", @@ -3193,7 +3141,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Local Read Requests", + "BriefDescription": "Tracker Occupancy Accumulator; Local Read Requests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_LOCAL", "PerPkg": "1", @@ -3202,7 +3150,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Remote Read Requests", + "BriefDescription": "Tracker Occupancy Accumulator; Remote Read Requests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_REMOTE", "PerPkg": "1", @@ -3211,7 +3159,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Local Write Requests", + "BriefDescription": "Tracker Occupancy Accumulator; Local Write Requests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL", "PerPkg": "1", @@ -3220,7 +3168,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Remote Write Requests", + "BriefDescription": "Tracker Occupancy Accumulator; Remote Write Requests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE", "PerPkg": "1", @@ -3229,7 +3177,7 @@ "Unit": "HA" }, { - "BriefDescription": "Data Pending Occupancy Accumultor; Local Requests", + "BriefDescription": "Data Pending Occupancy Accumulator; Local Requests", "EventCode": "0x5", "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL", "PerPkg": "1", @@ -3238,7 +3186,7 @@ "Unit": "HA" }, { - "BriefDescription": "Data Pending Occupancy Accumultor; Remote Requests", + "BriefDescription": "Data Pending Occupancy Accumulator; Remote Requests", "EventCode": "0x5", "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json index 489a3673323d..2819c6621089 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json @@ -3,7 +3,7 @@ "BriefDescription": "Number of non data (control) flits transmitted . Derived from unc_q_txl_flits_g0.non_data", "EventName": "QPI_CTL_BANDWIDTH_TX", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets.", "ScaleUnit": "8Bytes", "UMask": "0x4", "Unit": "QPI LL" @@ -12,7 +12,7 @@ "BriefDescription": "Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data", "EventName": "QPI_DATA_BANDWIDTH_TX", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets.", "ScaleUnit": "8Bytes", "UMask": "0x2", "Unit": "QPI LL" @@ -38,7 +38,7 @@ "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits. Had there been enough credits, the spawn would have worked as the RBT bit was set and the RBT tag matched.", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits. Had there been enough credits, the spawn would have worked as the RBT bit was set and the RBT tag matched.", "UMask": "0x2", "Unit": "QPI LL" }, @@ -47,7 +47,7 @@ "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and there weren't enough Egress credits. The valid bit was set.", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and there weren't enough Egress credits. The valid bit was set.", "UMask": "0x20", "Unit": "QPI LL" }, @@ -56,7 +56,7 @@ "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits AND the RBT bit was not set, but the RBT tag matched.", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits AND the RBT bit was not set, but the RBT tag matched.", "UMask": "0x8", "Unit": "QPI LL" }, @@ -65,7 +65,7 @@ "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match, the valid bit was not set and there weren't enough Egress credits.", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match, the valid bit was not set and there weren't enough Egress credits.", "UMask": "0x80", "Unit": "QPI LL" }, @@ -74,7 +74,7 @@ "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_MISS", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match although the valid bit was set and there were enough Egress credits.", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match although the valid bit was set and there were enough Egress credits.", "UMask": "0x10", "Unit": "QPI LL" }, @@ -83,7 +83,7 @@ "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the route-back table (RBT) specified that the transaction should not trigger a direct2core tranaction. This is common for IO transactions. There were enough Egress credits and the RBT tag matched but the valid bit was not set.", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the route-back table (RBT) specified that the transaction should not trigger a direct2core transaction. This is common for IO transactions. There were enough Egress credits and the RBT tag matched but the valid bit was not set.", "UMask": "0x4", "Unit": "QPI LL" }, @@ -92,7 +92,7 @@ "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and the valid bit was not set although there were enough Egress credits.", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and the valid bit was not set although there were enough Egress credits.", "UMask": "0x40", "Unit": "QPI LL" }, @@ -101,7 +101,7 @@ "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn was successful. There were sufficient credits, the RBT valid bit was set and there was an RBT tag match. The message was marked to spawn direct2core.", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn was successful. There were sufficient credits, the RBT valid bit was set and there was an RBT tag match. The message was marked to spawn direct2core.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -134,7 +134,7 @@ "EventCode": "0x9", "EventName": "UNC_Q_RxL_BYPASSED", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", "Unit": "QPI LL" }, { @@ -391,7 +391,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_RxL_FLITS_G0.IDLE", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits received over QPI that do not hold protocol payload. When QPI is not in a power saving state, it continuously transmits flits across the link. When there are no protocol flits to send, it will send IDLE and NULL flits across. These flits sometimes do carry a payload, such as credit returns, but are generall not considered part of the QPI bandwidth.", + "PublicDescription": "Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits received over QPI that do not hold protocol payload. When QPI is not in a power saving state, it continuously transmits flits across the link. When there are no protocol flits to send, it will send IDLE and NULL flits across. These flits sometimes do carry a payload, such as credit returns, but are generally not considered part of the QPI bandwidth.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -400,7 +400,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.DRS", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data.", "UMask": "0x18", "Unit": "QPI LL" }, @@ -409,7 +409,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).", "UMask": "0x8", "Unit": "QPI LL" }, @@ -418,7 +418,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.", "UMask": "0x10", "Unit": "QPI LL" }, @@ -427,7 +427,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.HOM", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits received over QPI on the home channel.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits received over QPI on the home channel.", "UMask": "0x6", "Unit": "QPI LL" }, @@ -436,7 +436,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits received over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits received over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.", "UMask": "0x4", "Unit": "QPI LL" }, @@ -445,7 +445,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request received over QPI on the home channel. This basically counts the number of remote memory requests received over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request received over QPI on the home channel. This basically counts the number of remote memory requests received over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.", "UMask": "0x2", "Unit": "QPI LL" }, @@ -454,7 +454,7 @@ "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.SNP", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits received over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are received on the home channel.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits received over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are received on the home channel.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -463,7 +463,7 @@ "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCB", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.", "UMask": "0xc", "Unit": "QPI LL" }, @@ -472,7 +472,7 @@ "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers.", "UMask": "0x4", "Unit": "QPI LL" }, @@ -481,7 +481,7 @@ "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.", "UMask": "0x8", "Unit": "QPI LL" }, @@ -490,7 +490,7 @@ "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCS", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits received over QPI. This includes extended headers.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits received over QPI. This includes extended headers.", "UMask": "0x10", "Unit": "QPI LL" }, @@ -499,7 +499,7 @@ "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -508,7 +508,7 @@ "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.", "UMask": "0x2", "Unit": "QPI LL" }, @@ -924,7 +924,7 @@ "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits", "EventName": "UNC_Q_TxL_FLITS_G0.DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets.", "UMask": "0x2", "Unit": "QPI LL" }, @@ -932,7 +932,7 @@ "BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits", "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets.", "UMask": "0x4", "Unit": "QPI LL" }, @@ -940,7 +940,7 @@ "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)", "EventName": "UNC_Q_TxL_FLITS_G1.DRS", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency.", "UMask": "0x18", "Unit": "QPI LL" }, @@ -948,7 +948,7 @@ "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits", "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).", "UMask": "0x8", "Unit": "QPI LL" }, @@ -956,7 +956,7 @@ "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits", "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.", "UMask": "0x10", "Unit": "QPI LL" }, @@ -964,7 +964,7 @@ "BriefDescription": "Flits Transferred - Group 1; HOM Flits", "EventName": "UNC_Q_TxL_FLITS_G1.HOM", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits transmitted over QPI on the home channel.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits transmitted over QPI on the home channel.", "UMask": "0x6", "Unit": "QPI LL" }, @@ -972,7 +972,7 @@ "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits", "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits transmitted over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits transmitted over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.", "UMask": "0x4", "Unit": "QPI LL" }, @@ -980,7 +980,7 @@ "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits", "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request transmitted over QPI on the home channel. This basically counts the number of remote memory requests transmitted over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request transmitted over QPI on the home channel. This basically counts the number of remote memory requests transmitted over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.", "UMask": "0x2", "Unit": "QPI LL" }, @@ -988,7 +988,7 @@ "BriefDescription": "Flits Transferred - Group 1; SNP Flits", "EventName": "UNC_Q_TxL_FLITS_G1.SNP", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits transmitted over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are transmitted on the home channel.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits transmitted over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are transmitted on the home channel.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -997,7 +997,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCB", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.", "UMask": "0xc", "Unit": "QPI LL" }, @@ -1006,7 +1006,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not te NCB headers.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers.", "UMask": "0x4", "Unit": "QPI LL" }, @@ -1015,7 +1015,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.", "UMask": "0x8", "Unit": "QPI LL" }, @@ -1024,7 +1024,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCS", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits transmitted over QPI. This includes extended headers.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits transmitted over QPI. This includes extended headers.", "UMask": "0x10", "Unit": "QPI LL" }, @@ -1033,7 +1033,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -1042,7 +1042,7 @@ "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK", "PerPkg": "1", - "PublicDescription": "Counts the number of flits trasmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.", "UMask": "0x2", "Unit": "QPI LL" }, @@ -1157,7 +1157,7 @@ "EventCode": "0x23", "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO fro Snoop messages on AD.", + "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for Snoop messages on AD.", "UMask": "0x1", "Unit": "QPI LL" }, @@ -1166,7 +1166,7 @@ "EventCode": "0x23", "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO fro Snoop messages on AD.", + "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for Snoop messages on AD.", "UMask": "0x2", "Unit": "QPI LL" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json index 34dfc3cf22ef..b5a33e7a68c6 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json @@ -51,7 +51,6 @@ "EventCode": "0xA1", "EventName": "UNC_M_BYP_CMDS.ACT", "PerPkg": "1", - "PublicDescription": "UNC_M_BYP_CMDS.ACT", "UMask": "0x1", "Unit": "iMC" }, @@ -60,7 +59,6 @@ "EventCode": "0xA1", "EventName": "UNC_M_BYP_CMDS.CAS", "PerPkg": "1", - "PublicDescription": "UNC_M_BYP_CMDS.CAS", "UMask": "0x2", "Unit": "iMC" }, @@ -69,7 +67,6 @@ "EventCode": "0xA1", "EventName": "UNC_M_BYP_CMDS.PRE", "PerPkg": "1", - "PublicDescription": "UNC_M_BYP_CMDS.PRE", "UMask": "0x4", "Unit": "iMC" }, @@ -202,7 +199,7 @@ "EventCode": "0x9", "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", "PerPkg": "1", - "PublicDescription": "Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit erros in lockstep mode.", + "PublicDescription": "Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit errors in lockstep mode.", "Unit": "iMC" }, { @@ -492,7 +489,6 @@ "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.HIGH", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_PRIO.HIGH", "UMask": "0x4", "Unit": "iMC" }, @@ -501,7 +497,6 @@ "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.LOW", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_PRIO.LOW", "UMask": "0x1", "Unit": "iMC" }, @@ -510,7 +505,6 @@ "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.MED", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_PRIO.MED", "UMask": "0x2", "Unit": "iMC" }, @@ -519,7 +513,6 @@ "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.PANIC", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_PRIO.PANIC", "UMask": "0x8", "Unit": "iMC" }, @@ -528,7 +521,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.ALLBANKS", + "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -537,7 +530,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -545,7 +538,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK1", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -554,7 +547,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK10", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK10", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -563,7 +556,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK11", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK11", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -572,7 +565,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK12", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK12", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -581,7 +574,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK13", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK13", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -590,7 +583,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK14", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK14", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -599,7 +592,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK15", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK15", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -608,7 +601,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK2", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK2", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -617,7 +610,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK3", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK3", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -626,7 +619,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK4", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK4", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -635,7 +628,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK5", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK5", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -644,7 +637,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK6", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK6", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -653,7 +646,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK7", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK7", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -662,7 +655,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK8", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK8", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -671,7 +664,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK9", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANK9", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -680,7 +673,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANKG0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -689,7 +682,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG1", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANKG1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -698,7 +691,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG2", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANKG2", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -707,7 +700,7 @@ "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG3", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK0.BANKG3", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -716,7 +709,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.ALLBANKS", + "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -725,7 +718,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -733,7 +726,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK1", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -742,7 +735,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK10", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK10", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -751,7 +744,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK11", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK11", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -760,7 +753,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK12", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK12", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -769,7 +762,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK13", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK13", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -778,7 +771,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK14", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK14", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -787,7 +780,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK15", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK15", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -796,7 +789,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK2", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK2", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -805,7 +798,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK3", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK3", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -814,7 +807,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK4", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK4", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -823,7 +816,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK5", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK5", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -832,7 +825,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK6", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK6", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -841,7 +834,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK7", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK7", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -850,7 +843,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK8", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK8", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -859,7 +852,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK9", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANK9", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -868,7 +861,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANKG0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -877,7 +870,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG1", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANKG1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -886,7 +879,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG2", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANKG2", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -895,7 +888,7 @@ "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG3", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK1.BANKG3", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -904,7 +897,7 @@ "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK2.BANK0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -912,7 +905,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.ALLBANKS", + "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -921,7 +914,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -929,7 +922,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK1", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -938,7 +931,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK10", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK10", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -947,7 +940,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK11", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK11", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -956,7 +949,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK12", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK12", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -965,7 +958,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK13", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK13", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -974,7 +967,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK14", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK14", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -983,7 +976,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK15", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK15", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -992,7 +985,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK2", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK2", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -1001,7 +994,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK3", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK3", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -1010,7 +1003,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK4", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK4", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -1019,7 +1012,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK5", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK5", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -1028,7 +1021,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK6", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK6", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -1037,7 +1030,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK7", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK7", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -1046,7 +1039,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK8", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK8", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -1055,7 +1048,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK9", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANK9", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -1064,7 +1057,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANKG0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -1073,7 +1066,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG1", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANKG1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -1082,7 +1075,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG2", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANKG2", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -1091,7 +1084,7 @@ "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG3", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK4.BANKG3", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -1100,7 +1093,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.ALLBANKS", + "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -1109,7 +1102,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -1117,7 +1110,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK1", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -1126,7 +1119,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK10", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK10", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -1135,7 +1128,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK11", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK11", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -1144,7 +1137,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK12", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK12", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -1153,7 +1146,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK13", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK13", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -1162,7 +1155,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK14", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK14", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -1171,7 +1164,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK15", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK15", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -1180,7 +1173,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK2", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK2", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -1189,7 +1182,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK3", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK3", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -1198,7 +1191,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK4", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK4", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -1207,7 +1200,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK5", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK5", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -1216,7 +1209,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK6", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK6", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -1225,7 +1218,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK7", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK7", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -1234,7 +1227,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK8", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK8", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -1243,7 +1236,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK9", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANK9", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -1252,7 +1245,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANKG0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -1261,7 +1254,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG1", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANKG1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -1270,7 +1263,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG2", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANKG2", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -1279,7 +1272,7 @@ "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG3", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK5.BANKG3", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -1288,7 +1281,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.ALLBANKS", + "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -1297,7 +1290,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -1305,7 +1298,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK1", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -1314,7 +1307,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK10", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK10", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -1323,7 +1316,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK11", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK11", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -1332,7 +1325,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK12", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK12", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -1341,7 +1334,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK13", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK13", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -1350,7 +1343,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK14", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK14", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -1359,7 +1352,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK15", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK15", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -1368,7 +1361,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK2", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK2", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -1377,7 +1370,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK3", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK3", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -1386,7 +1379,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK4", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK4", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -1395,7 +1388,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK5", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK5", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -1404,7 +1397,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK6", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK6", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -1413,7 +1406,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK7", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK7", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -1422,7 +1415,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK8", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK8", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -1431,7 +1424,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK9", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANK9", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -1440,7 +1433,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANKG0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -1449,7 +1442,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG1", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANKG1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -1458,7 +1451,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG2", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANKG2", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -1467,7 +1460,7 @@ "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG3", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK6.BANKG3", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -1476,7 +1469,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.ALLBANKS", + "PublicDescription": "RD_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -1485,7 +1478,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -1493,7 +1486,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK1", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -1502,7 +1495,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK10", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK10", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -1511,7 +1504,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK11", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK11", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -1520,7 +1513,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK12", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK12", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -1529,7 +1522,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK13", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK13", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -1538,7 +1531,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK14", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK14", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -1547,7 +1540,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK15", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK15", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -1556,7 +1549,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK2", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK2", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -1565,7 +1558,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK3", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK3", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -1574,7 +1567,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK4", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK4", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -1583,7 +1576,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK5", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK5", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -1592,7 +1585,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK6", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK6", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -1601,7 +1594,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK7", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK7", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -1610,7 +1603,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK8", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK8", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -1619,7 +1612,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK9", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANK9", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -1628,7 +1621,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG0", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANKG0", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -1637,7 +1630,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG1", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANKG1", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -1646,7 +1639,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG2", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANKG2", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -1655,7 +1648,7 @@ "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG3", "PerPkg": "1", - "PublicDescription": "UNC_M_RD_CAS_RANK7.BANKG3", + "PublicDescription": "RD_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -1680,7 +1673,6 @@ "EventCode": "0x91", "EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "UNC_M_VMSE_MXB_WR_OCCUPANCY", "Unit": "iMC" }, { @@ -1688,7 +1680,6 @@ "EventCode": "0x90", "EventName": "UNC_M_VMSE_WR_PUSH.RMM", "PerPkg": "1", - "PublicDescription": "UNC_M_VMSE_WR_PUSH.RMM", "UMask": "0x2", "Unit": "iMC" }, @@ -1697,7 +1688,6 @@ "EventCode": "0x90", "EventName": "UNC_M_VMSE_WR_PUSH.WMM", "PerPkg": "1", - "PublicDescription": "UNC_M_VMSE_WR_PUSH.WMM", "UMask": "0x1", "Unit": "iMC" }, @@ -1706,7 +1696,6 @@ "EventCode": "0xC0", "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH", "PerPkg": "1", - "PublicDescription": "UNC_M_WMM_TO_RMM.LOW_THRESH", "UMask": "0x1", "Unit": "iMC" }, @@ -1715,7 +1704,6 @@ "EventCode": "0xC0", "EventName": "UNC_M_WMM_TO_RMM.STARVE", "PerPkg": "1", - "PublicDescription": "UNC_M_WMM_TO_RMM.STARVE", "UMask": "0x2", "Unit": "iMC" }, @@ -1724,7 +1712,6 @@ "EventCode": "0xC0", "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY", "PerPkg": "1", - "PublicDescription": "UNC_M_WMM_TO_RMM.VMSE_RETRY", "UMask": "0x4", "Unit": "iMC" }, @@ -1765,7 +1752,6 @@ "EventCode": "0xC1", "EventName": "UNC_M_WRONG_MM", "PerPkg": "1", - "PublicDescription": "UNC_M_WRONG_MM", "Unit": "iMC" }, { @@ -1773,7 +1759,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.ALLBANKS", + "PublicDescription": "WR_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -1782,7 +1768,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK0", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -1790,7 +1776,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK1", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -1799,7 +1785,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK10", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK10", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -1808,7 +1794,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK11", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK11", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -1817,7 +1803,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK12", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK12", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -1826,7 +1812,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK13", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK13", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -1835,7 +1821,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK14", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK14", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -1844,7 +1830,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK15", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK15", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -1853,7 +1839,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK2", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK2", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -1862,7 +1848,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK3", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK3", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -1871,7 +1857,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK4", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK4", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -1880,7 +1866,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK5", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK5", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -1889,7 +1875,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK6", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK6", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -1898,7 +1884,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK7", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK7", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -1907,7 +1893,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK8", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK8", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -1916,7 +1902,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK9", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANK9", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -1925,7 +1911,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG0", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANKG0", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -1934,7 +1920,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG1", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANKG1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -1943,7 +1929,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG2", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANKG2", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -1952,7 +1938,7 @@ "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG3", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK0.BANKG3", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -1961,7 +1947,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.ALLBANKS", + "PublicDescription": "WR_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -1970,7 +1956,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK0", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -1978,7 +1964,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK1", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -1987,7 +1973,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK10", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK10", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -1996,7 +1982,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK11", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK11", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -2005,7 +1991,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK12", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK12", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -2014,7 +2000,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK13", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK13", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -2023,7 +2009,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK14", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK14", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -2032,7 +2018,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK15", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK15", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -2041,7 +2027,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK2", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK2", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -2050,7 +2036,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK3", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK3", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -2059,7 +2045,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK4", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK4", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -2068,7 +2054,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK5", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK5", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -2077,7 +2063,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK6", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK6", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -2086,7 +2072,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK7", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK7", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -2095,7 +2081,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK8", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK8", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -2104,7 +2090,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK9", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANK9", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -2113,7 +2099,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG0", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANKG0", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -2122,7 +2108,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG1", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANKG1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -2131,7 +2117,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG2", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANKG2", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -2140,7 +2126,7 @@ "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG3", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK1.BANKG3", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -2149,7 +2135,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.ALLBANKS", + "PublicDescription": "WR_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -2158,7 +2144,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK0", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -2166,7 +2152,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK1", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -2175,7 +2161,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK10", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK10", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -2184,7 +2170,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK11", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK11", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -2193,7 +2179,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK12", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK12", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -2202,7 +2188,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK13", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK13", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -2211,7 +2197,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK14", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK14", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -2220,7 +2206,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK15", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK15", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -2229,7 +2215,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK2", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK2", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -2238,7 +2224,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK3", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK3", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -2247,7 +2233,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK4", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK4", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -2256,7 +2242,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK5", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK5", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -2265,7 +2251,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK6", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK6", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -2274,7 +2260,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK7", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK7", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -2283,7 +2269,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK8", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK8", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -2292,7 +2278,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK9", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANK9", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -2301,7 +2287,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG0", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANKG0", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -2310,7 +2296,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG1", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANKG1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -2319,7 +2305,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG2", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANKG2", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -2328,7 +2314,7 @@ "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG3", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK4.BANKG3", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -2337,7 +2323,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.ALLBANKS", + "PublicDescription": "WR_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -2346,7 +2332,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK0", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -2354,7 +2340,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK1", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -2363,7 +2349,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK10", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK10", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -2372,7 +2358,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK11", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK11", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -2381,7 +2367,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK12", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK12", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -2390,7 +2376,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK13", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK13", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -2399,7 +2385,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK14", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK14", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -2408,7 +2394,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK15", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK15", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -2417,7 +2403,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK2", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK2", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -2426,7 +2412,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK3", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK3", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -2435,7 +2421,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK4", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK4", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -2444,7 +2430,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK5", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK5", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -2453,7 +2439,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK6", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK6", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -2462,7 +2448,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK7", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK7", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -2471,7 +2457,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK8", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK8", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -2480,7 +2466,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK9", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANK9", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -2489,7 +2475,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG0", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANKG0", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -2498,7 +2484,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG1", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANKG1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -2507,7 +2493,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG2", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANKG2", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -2516,7 +2502,7 @@ "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG3", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK5.BANKG3", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -2525,7 +2511,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.ALLBANKS", + "PublicDescription": "WR_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -2534,7 +2520,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK0", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -2542,7 +2528,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK1", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -2551,7 +2537,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK10", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK10", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -2560,7 +2546,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK11", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK11", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -2569,7 +2555,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK12", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK12", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -2578,7 +2564,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK13", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK13", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -2587,7 +2573,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK14", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK14", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -2596,7 +2582,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK15", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK15", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -2605,7 +2591,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK2", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK2", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -2614,7 +2600,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK3", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK3", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -2623,7 +2609,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK4", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK4", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -2632,7 +2618,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK5", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK5", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -2641,7 +2627,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK6", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK6", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -2650,7 +2636,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK7", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK7", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -2659,7 +2645,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK8", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK8", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -2668,7 +2654,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK9", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANK9", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -2677,7 +2663,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG0", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANKG0", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -2686,7 +2672,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG1", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANKG1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -2695,7 +2681,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG2", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANKG2", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -2704,7 +2690,7 @@ "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG3", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK6.BANKG3", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)", "UMask": "0x14", "Unit": "iMC" }, @@ -2713,7 +2699,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.ALLBANKS", + "PublicDescription": "WR_CAS Access to Rank 0 : All Banks", "UMask": "0x10", "Unit": "iMC" }, @@ -2722,7 +2708,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK0", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK0", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 0", "Unit": "iMC" }, { @@ -2730,7 +2716,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK1", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 1", "UMask": "0x1", "Unit": "iMC" }, @@ -2739,7 +2725,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK10", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK10", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 10", "UMask": "0xa", "Unit": "iMC" }, @@ -2748,7 +2734,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK11", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK11", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 11", "UMask": "0xb", "Unit": "iMC" }, @@ -2757,7 +2743,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK12", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK12", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 12", "UMask": "0xc", "Unit": "iMC" }, @@ -2766,7 +2752,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK13", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK13", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 13", "UMask": "0xd", "Unit": "iMC" }, @@ -2775,7 +2761,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK14", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK14", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 14", "UMask": "0xe", "Unit": "iMC" }, @@ -2784,7 +2770,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK15", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK15", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 15", "UMask": "0xf", "Unit": "iMC" }, @@ -2793,7 +2779,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK2", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK2", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 2", "UMask": "0x2", "Unit": "iMC" }, @@ -2802,7 +2788,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK3", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK3", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 3", "UMask": "0x3", "Unit": "iMC" }, @@ -2811,7 +2797,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK4", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK4", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 4", "UMask": "0x4", "Unit": "iMC" }, @@ -2820,7 +2806,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK5", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK5", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 5", "UMask": "0x5", "Unit": "iMC" }, @@ -2829,7 +2815,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK6", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK6", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 6", "UMask": "0x6", "Unit": "iMC" }, @@ -2838,7 +2824,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK7", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK7", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 7", "UMask": "0x7", "Unit": "iMC" }, @@ -2847,7 +2833,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK8", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK8", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 8", "UMask": "0x8", "Unit": "iMC" }, @@ -2856,7 +2842,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK9", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANK9", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank 9", "UMask": "0x9", "Unit": "iMC" }, @@ -2865,7 +2851,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG0", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANKG0", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 0 (Banks 0-3)", "UMask": "0x11", "Unit": "iMC" }, @@ -2874,7 +2860,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG1", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANKG1", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 1 (Banks 4-7)", "UMask": "0x12", "Unit": "iMC" }, @@ -2883,7 +2869,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG2", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANKG2", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 2 (Banks 8-11)", "UMask": "0x13", "Unit": "iMC" }, @@ -2892,7 +2878,7 @@ "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG3", "PerPkg": "1", - "PublicDescription": "UNC_M_WR_CAS_RANK7.BANKG3", + "PublicDescription": "WR_CAS Access to Rank 0 : Bank Group 3 (Banks 12-15)", "UMask": "0x14", "Unit": "iMC" } diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json index a80d931dc3d5..43def2582617 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json @@ -101,7 +101,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", "PerPkg": "1", - "PublicDescription": "UNC_I_MISC0.2ND_ATOMIC_INSERT", + "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary", "UMask": "0x10", "Unit": "IRP" }, @@ -110,7 +110,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.2ND_RD_INSERT", "PerPkg": "1", - "PublicDescription": "UNC_I_MISC0.2ND_RD_INSERT", + "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary", "UMask": "0x4", "Unit": "IRP" }, @@ -119,7 +119,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.2ND_WR_INSERT", "PerPkg": "1", - "PublicDescription": "UNC_I_MISC0.2ND_WR_INSERT", + "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary", "UMask": "0x8", "Unit": "IRP" }, @@ -128,7 +128,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.FAST_REJ", "PerPkg": "1", - "PublicDescription": "UNC_I_MISC0.FAST_REJ", + "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", "UMask": "0x2", "Unit": "IRP" }, @@ -137,7 +137,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.FAST_REQ", "PerPkg": "1", - "PublicDescription": "UNC_I_MISC0.FAST_REQ", + "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Requests", "UMask": "0x1", "Unit": "IRP" }, @@ -146,7 +146,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.FAST_XFER", "PerPkg": "1", - "PublicDescription": "UNC_I_MISC0.FAST_XFER", + "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary", "UMask": "0x20", "Unit": "IRP" }, @@ -155,7 +155,7 @@ "EventCode": "0x14", "EventName": "UNC_I_MISC0.PF_ACK_HINT", "PerPkg": "1", - "PublicDescription": "UNC_I_MISC0.PF_ACK_HINT", + "PublicDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary", "UMask": "0x40", "Unit": "IRP" }, @@ -182,7 +182,7 @@ "EventCode": "0x15", "EventName": "UNC_I_MISC1.LOST_FWD", "PerPkg": "1", - "PublicDescription": "UNC_I_MISC1.LOST_FWD", + "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed", "UMask": "0x10", "Unit": "IRP" }, @@ -325,7 +325,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.HIT_ES", "PerPkg": "1", - "PublicDescription": "UNC_I_SNOOP_RESP.HIT_ES", + "PublicDescription": "Snoop Responses : Hit E or S", "UMask": "0x4", "Unit": "IRP" }, @@ -334,7 +334,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.HIT_I", "PerPkg": "1", - "PublicDescription": "UNC_I_SNOOP_RESP.HIT_I", + "PublicDescription": "Snoop Responses : Hit I", "UMask": "0x2", "Unit": "IRP" }, @@ -343,7 +343,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.HIT_M", "PerPkg": "1", - "PublicDescription": "UNC_I_SNOOP_RESP.HIT_M", + "PublicDescription": "Snoop Responses : Hit M", "UMask": "0x8", "Unit": "IRP" }, @@ -352,7 +352,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.MISS", "PerPkg": "1", - "PublicDescription": "UNC_I_SNOOP_RESP.MISS", + "PublicDescription": "Snoop Responses : Miss", "UMask": "0x1", "Unit": "IRP" }, @@ -361,7 +361,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.SNPCODE", "PerPkg": "1", - "PublicDescription": "UNC_I_SNOOP_RESP.SNPCODE", + "PublicDescription": "Snoop Responses : SnpCode", "UMask": "0x10", "Unit": "IRP" }, @@ -370,7 +370,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.SNPDATA", "PerPkg": "1", - "PublicDescription": "UNC_I_SNOOP_RESP.SNPDATA", + "PublicDescription": "Snoop Responses : SnpData", "UMask": "0x20", "Unit": "IRP" }, @@ -379,7 +379,7 @@ "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.SNPINV", "PerPkg": "1", - "PublicDescription": "UNC_I_SNOOP_RESP.SNPINV", + "PublicDescription": "Snoop Responses : SnpInv", "UMask": "0x40", "Unit": "IRP" }, @@ -474,7 +474,7 @@ "EventCode": "0xD", "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.", + "PublicDescription": "Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.", "Unit": "IRP" }, { @@ -1223,7 +1223,6 @@ "EventCode": "0xB", "EventName": "UNC_R3_IOT_BACKPRESSURE.HUB", "PerPkg": "1", - "PublicDescription": "UNC_R3_IOT_BACKPRESSURE.HUB", "UMask": "0x2", "Unit": "R3QPI" }, @@ -1232,7 +1231,6 @@ "EventCode": "0xB", "EventName": "UNC_R3_IOT_BACKPRESSURE.SAT", "PerPkg": "1", - "PublicDescription": "UNC_R3_IOT_BACKPRESSURE.SAT", "UMask": "0x1", "Unit": "R3QPI" }, @@ -2312,7 +2310,7 @@ "EventCode": "0x33", "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD", "PerPkg": "1", - "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transfered). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transfered in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", + "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", "Unit": "R3QPI" }, @@ -2321,7 +2319,7 @@ "EventCode": "0x33", "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL", "PerPkg": "1", - "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transfered). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transfered in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", + "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", "UMask": "0x4", "Unit": "R3QPI" }, @@ -2384,14 +2382,12 @@ "EventCode": "0xA", "EventName": "UNC_S_BOUNCE_CONTROL", "PerPkg": "1", - "PublicDescription": "UNC_S_BOUNCE_CONTROL", "Unit": "SBO" }, { "BriefDescription": "Uncore Clocks", "EventName": "UNC_S_CLOCKTICKS", "PerPkg": "1", - "PublicDescription": "UNC_S_CLOCKTICKS", "Unit": "SBO" }, { @@ -2596,7 +2592,6 @@ "EventCode": "0x5", "EventName": "UNC_S_RING_BOUNCES.AD_CACHE", "PerPkg": "1", - "PublicDescription": "UNC_S_RING_BOUNCES.AD_CACHE", "UMask": "0x1", "Unit": "SBO" }, @@ -2605,7 +2600,6 @@ "EventCode": "0x5", "EventName": "UNC_S_RING_BOUNCES.AK_CORE", "PerPkg": "1", - "PublicDescription": "UNC_S_RING_BOUNCES.AK_CORE", "UMask": "0x2", "Unit": "SBO" }, @@ -2614,7 +2608,6 @@ "EventCode": "0x5", "EventName": "UNC_S_RING_BOUNCES.BL_CORE", "PerPkg": "1", - "PublicDescription": "UNC_S_RING_BOUNCES.BL_CORE", "UMask": "0x4", "Unit": "SBO" }, @@ -2623,7 +2616,6 @@ "EventCode": "0x5", "EventName": "UNC_S_RING_BOUNCES.IV_CORE", "PerPkg": "1", - "PublicDescription": "UNC_S_RING_BOUNCES.IV_CORE", "UMask": "0x8", "Unit": "SBO" }, diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json index e682eedf644a..83d20130c217 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json @@ -395,7 +395,7 @@ "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", "PerPkg": "1", - "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", + "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", "Unit": "PCU" }, { @@ -403,7 +403,7 @@ "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", "PerPkg": "1", - "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", + "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", "Unit": "PCU" }, { @@ -411,7 +411,7 @@ "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", "PerPkg": "1", - "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", + "PublicDescription": "This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details.", "Unit": "PCU" }, { @@ -427,7 +427,7 @@ "EventCode": "0x9", "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that we are in Interal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.", + "PublicDescription": "Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.", "Unit": "PCU" }, { @@ -451,7 +451,7 @@ "EventCode": "0x42", "EventName": "UNC_P_VR_HOT_CYCLES", "PerPkg": "1", - "PublicDescription": "UNC_P_VR_HOT_CYCLES", + "PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR is hot. Does not cover DRAM VRs", "Unit": "PCU" } ] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 4fa827c7f719..dfed265c95ab 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -4,7 +4,7 @@ GenuineIntel-6-BE,v1.19,alderlaken,core GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core GenuineIntel-6-(3D|47),v27,broadwell,core GenuineIntel-6-56,v9,broadwellde,core -GenuineIntel-6-4F,v19,broadwellx,core +GenuineIntel-6-4F,v20,broadwellx,core GenuineIntel-6-55-[56789ABCDEF],v1.17,cascadelakex,core GenuineIntel-6-9[6C],v1.03,elkhartlake,core GenuineIntel-6-5[CF],v13,goldmont,core -- cgit v1.2.3-58-ga151 From 67245a7eea604b61ce7973329c1bb99d5e35dcf7 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 24 Mar 2023 00:22:13 -0700 Subject: perf vendor events intel: Haswell v33 events Updates descriptions and encodings. Adds BR_MISP_EXEC.INDIRECT events. Reviewed-by: Kan Liang Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Dan Williams Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Samantha Alt Cc: Weilin Wang Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230324072218.181880-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/haswell/cache.json | 38 +++++++++++----------- tools/perf/pmu-events/arch/x86/haswell/memory.json | 38 +++++++++++----------- .../perf/pmu-events/arch/x86/haswell/pipeline.json | 8 +++++ tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 4 files changed, 47 insertions(+), 39 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/haswell/cache.json b/tools/perf/pmu-events/arch/x86/haswell/cache.json index 5a1489e79859..0831f14b3cc6 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/cache.json +++ b/tools/perf/pmu-events/arch/x86/haswell/cache.json @@ -8,7 +8,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", @@ -643,7 +643,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch code readshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -652,7 +652,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch data readshit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -661,7 +661,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch data readshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -688,7 +688,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all requestshit in the L3", + "BriefDescription": "Counts all requests hit in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -697,7 +697,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch RFOshit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -706,7 +706,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch RFOshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -715,7 +715,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code readshit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "BriefDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -724,7 +724,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code readshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "BriefDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -733,7 +733,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data readshit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "BriefDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -742,7 +742,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data readshit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "BriefDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -751,7 +751,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -760,7 +760,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -769,7 +769,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code readshit in the L3", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -778,7 +778,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts prefetch (that bring data to L2) data readshit in the L3", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -787,7 +787,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOshit in the L3", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -796,7 +796,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts prefetch (that bring data to LLC only) code readshit in the L3", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -805,7 +805,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data readshit in the L3", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -814,7 +814,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOshit in the L3", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/haswell/memory.json b/tools/perf/pmu-events/arch/x86/haswell/memory.json index 9fb63e1dab08..2fc25e22a42a 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/memory.json +++ b/tools/perf/pmu-events/arch/x86/haswell/memory.json @@ -179,7 +179,7 @@ "UMask": "0x2" }, { - "BriefDescription": "Counts all demand & prefetch code readsmiss in the L3", + "BriefDescription": "Counts all demand & prefetch code reads miss in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -188,7 +188,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch code readsmiss the L3 and the data is returned from local dram", + "BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -197,7 +197,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch data readsmiss in the L3", + "BriefDescription": "Counts all demand & prefetch data reads miss in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -206,7 +206,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch data readsmiss the L3 and the data is returned from local dram", + "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -233,7 +233,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all requestsmiss in the L3", + "BriefDescription": "Counts all requests miss in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -242,7 +242,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch RFOsmiss in the L3", + "BriefDescription": "Counts all demand & prefetch RFOs miss in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -251,7 +251,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand & prefetch RFOsmiss the L3 and the data is returned from local dram", + "BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -260,7 +260,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code readsmiss in the L3", + "BriefDescription": "Counts all demand code reads miss in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -269,7 +269,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code readsmiss the L3 and the data is returned from local dram", + "BriefDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -278,7 +278,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data readsmiss in the L3", + "BriefDescription": "Counts demand data reads miss in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -287,7 +287,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data readsmiss the L3 and the data is returned from local dram", + "BriefDescription": "Counts demand data reads miss the L3 and the data is returned from local dram", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -296,7 +296,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)miss in the L3", + "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -305,7 +305,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)miss the L3 and the data is returned from local dram", + "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -314,7 +314,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code readsmiss in the L3", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -323,7 +323,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts prefetch (that bring data to L2) data readsmiss in the L3", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -332,7 +332,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOsmiss in the L3", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -341,7 +341,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts prefetch (that bring data to LLC only) code readsmiss in the L3", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -350,7 +350,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data readsmiss in the L3", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -359,7 +359,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOsmiss in the L3", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/haswell/pipeline.json b/tools/perf/pmu-events/arch/x86/haswell/pipeline.json index 9ac36c1c24b6..540f4372623c 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/haswell/pipeline.json @@ -194,6 +194,14 @@ "SampleAfterValue": "200003", "UMask": "0xc4" }, + { + "BriefDescription": "Speculative mispredicted indirect branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.INDIRECT", + "PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, { "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.", "EventCode": "0x89", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index dfed265c95ab..927e60f3417d 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -10,7 +10,7 @@ GenuineIntel-6-9[6C],v1.03,elkhartlake,core GenuineIntel-6-5[CF],v13,goldmont,core GenuineIntel-6-7A,v1.01,goldmontplus,core GenuineIntel-6-A[DE],v1.01,graniterapids,core -GenuineIntel-6-(3C|45|46),v32,haswell,core +GenuineIntel-6-(3C|45|46),v33,haswell,core GenuineIntel-6-3F,v26,haswellx,core GenuineIntel-6-(7D|7E|A7),v1.17,icelake,core GenuineIntel-6-6[AC],v1.19,icelakex,core -- cgit v1.2.3-58-ga151 From 6e884dad09722abd6ea23a27acc041ba767bdb88 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 24 Mar 2023 00:22:14 -0700 Subject: perf vendor events intel: Haswellx v27 events Updates descriptions and encodings. Adds BR_MISP_EXEC.INDIRECT events. Reviewed-by: Kan Liang Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Dan Williams Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Samantha Alt Cc: Weilin Wang Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230324072218.181880-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/haswellx/cache.json | 2 +- tools/perf/pmu-events/arch/x86/haswellx/pipeline.json | 8 ++++++++ .../perf/pmu-events/arch/x86/haswellx/uncore-cache.json | 16 ++++++++-------- .../perf/pmu-events/arch/x86/haswellx/uncore-other.json | 6 +++--- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 5 files changed, 21 insertions(+), 13 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/haswellx/cache.json b/tools/perf/pmu-events/arch/x86/haswellx/cache.json index 1836ed62694e..a6c81010b394 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/cache.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/cache.json @@ -8,7 +8,7 @@ "UMask": "0x1" }, { - "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers unavailability.", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", diff --git a/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json b/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json index 9ac36c1c24b6..540f4372623c 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json @@ -194,6 +194,14 @@ "SampleAfterValue": "200003", "UMask": "0xc4" }, + { + "BriefDescription": "Speculative mispredicted indirect branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.INDIRECT", + "PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, { "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.", "EventCode": "0x89", diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json b/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json index 183bcac99642..e969dc71bea1 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json @@ -3114,7 +3114,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Local InvItoE Requests", + "BriefDescription": "Tracker Occupancy Accumulator; Local InvItoE Requests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL", "PerPkg": "1", @@ -3123,7 +3123,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Remote InvItoE Requests", + "BriefDescription": "Tracker Occupancy Accumulator; Remote InvItoE Requests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE", "PerPkg": "1", @@ -3132,7 +3132,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Local Read Requests", + "BriefDescription": "Tracker Occupancy Accumulator; Local Read Requests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_LOCAL", "PerPkg": "1", @@ -3141,7 +3141,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Remote Read Requests", + "BriefDescription": "Tracker Occupancy Accumulator; Remote Read Requests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_REMOTE", "PerPkg": "1", @@ -3150,7 +3150,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Local Write Requests", + "BriefDescription": "Tracker Occupancy Accumulator; Local Write Requests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL", "PerPkg": "1", @@ -3159,7 +3159,7 @@ "Unit": "HA" }, { - "BriefDescription": "Tracker Occupancy Accumultor; Remote Write Requests", + "BriefDescription": "Tracker Occupancy Accumulator; Remote Write Requests", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE", "PerPkg": "1", @@ -3168,7 +3168,7 @@ "Unit": "HA" }, { - "BriefDescription": "Data Pending Occupancy Accumultor; Local Requests", + "BriefDescription": "Data Pending Occupancy Accumulator; Local Requests", "EventCode": "0x5", "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL", "PerPkg": "1", @@ -3177,7 +3177,7 @@ "Unit": "HA" }, { - "BriefDescription": "Data Pending Occupancy Accumultor; Remote Requests", + "BriefDescription": "Data Pending Occupancy Accumulator; Remote Requests", "EventCode": "0x5", "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-other.json b/tools/perf/pmu-events/arch/x86/haswellx/uncore-other.json index 4c3e2a794117..d30e3b16c1af 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/uncore-other.json @@ -474,7 +474,7 @@ "EventCode": "0xD", "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.", + "PublicDescription": "Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.", "Unit": "IRP" }, { @@ -2256,7 +2256,7 @@ "EventCode": "0x33", "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD", "PerPkg": "1", - "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", + "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", "Unit": "R3QPI" }, @@ -2265,7 +2265,7 @@ "EventCode": "0x33", "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL", "PerPkg": "1", - "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", + "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", "UMask": "0x4", "Unit": "R3QPI" }, diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 927e60f3417d..e1a609401fff 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -11,7 +11,7 @@ GenuineIntel-6-5[CF],v13,goldmont,core GenuineIntel-6-7A,v1.01,goldmontplus,core GenuineIntel-6-A[DE],v1.01,graniterapids,core GenuineIntel-6-(3C|45|46),v33,haswell,core -GenuineIntel-6-3F,v26,haswellx,core +GenuineIntel-6-3F,v27,haswellx,core GenuineIntel-6-(7D|7E|A7),v1.17,icelake,core GenuineIntel-6-6[AC],v1.19,icelakex,core GenuineIntel-6-3A,v23,ivybridge,core -- cgit v1.2.3-58-ga151 From 101a25b5d96d5ca06e11d07bb83fd72886407fe4 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 24 Mar 2023 00:22:15 -0700 Subject: perf vendor events intel: Jaketown v23 events Adds BR_MISP_EXEC.INDIRECT event. Reviewed-by: Kan Liang Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Dan Williams Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Samantha Alt Cc: Weilin Wang Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230324072218.181880-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/jaketown/pipeline.json | 8 ++++++++ tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json b/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json index 85c04fe7632a..d0edfdec9f01 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json @@ -202,6 +202,14 @@ "SampleAfterValue": "200003", "UMask": "0xc4" }, + { + "BriefDescription": "Speculative mispredicted indirect branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.INDIRECT", + "PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, { "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.", "EventCode": "0x89", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index e1a609401fff..e41c289fa427 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -16,7 +16,7 @@ GenuineIntel-6-(7D|7E|A7),v1.17,icelake,core GenuineIntel-6-6[AC],v1.19,icelakex,core GenuineIntel-6-3A,v23,ivybridge,core GenuineIntel-6-3E,v22,ivytown,core -GenuineIntel-6-2D,v22,jaketown,core +GenuineIntel-6-2D,v23,jaketown,core GenuineIntel-6-(57|85),v10,knightslanding,core GenuineIntel-6-A[AC],v1.01,meteorlake,core GenuineIntel-6-1[AEF],v3,nehalemep,core -- cgit v1.2.3-58-ga151 From e559b6f53b1b36fd69291962104fa86edf3dadf4 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 24 Mar 2023 00:22:16 -0700 Subject: perf vendor events intel: Sandybridge v19 events Adds BR_MISP_EXEC.INDIRECT event. Reviewed-by: Kan Liang Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Dan Williams Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Samantha Alt Cc: Weilin Wang Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230324072218.181880-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json | 8 ++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index e41c289fa427..41d755d570e6 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -21,7 +21,7 @@ GenuineIntel-6-(57|85),v10,knightslanding,core GenuineIntel-6-A[AC],v1.01,meteorlake,core GenuineIntel-6-1[AEF],v3,nehalemep,core GenuineIntel-6-2E,v3,nehalemex,core -GenuineIntel-6-2A,v18,sandybridge,core +GenuineIntel-6-2A,v19,sandybridge,core GenuineIntel-6-(8F|CF),v1.11,sapphirerapids,core GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v55,skylake,core diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json b/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json index 54454e5e262c..ecaf94ccc9c7 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json @@ -210,6 +210,14 @@ "SampleAfterValue": "200003", "UMask": "0xc4" }, + { + "BriefDescription": "Speculative mispredicted indirect branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.INDIRECT", + "PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, { "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.", "EventCode": "0x89", -- cgit v1.2.3-58-ga151 From c3bf86f11dc9a11afb83b33f9640bf86adfb1b28 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 24 Mar 2023 00:22:17 -0700 Subject: perf metrics: Add has_pmem literal Add literal so that if nvdimms aren't installed we can record fewer events. The file detection mechanism was suggested by Dan Williams in: https://lore.kernel.org/linux-perf-users/641bbe1eced26_1b98bb29440@dwillia2-xfh.jf.intel.com.notmuch/ Reviewed-by: Kan Liang Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Dan Williams Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Samantha Alt Cc: Weilin Wang Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230324072218.181880-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/expr.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'tools') diff --git a/tools/perf/util/expr.c b/tools/perf/util/expr.c index d46a1878bc9e..bb6ddad7e021 100644 --- a/tools/perf/util/expr.c +++ b/tools/perf/util/expr.c @@ -14,6 +14,7 @@ #include "util/hashmap.h" #include "smt.h" #include "tsc.h" +#include #include #include #include @@ -400,6 +401,20 @@ double arch_get_tsc_freq(void) } #endif +static double has_pmem(void) +{ + static bool has_pmem, cached; + const char *sysfs = sysfs__mountpoint(); + char path[PATH_MAX]; + + if (!cached) { + snprintf(path, sizeof(path), "%s/firmware/acpi/tables/NFIT", sysfs); + has_pmem = access(path, F_OK) == 0; + cached = true; + } + return has_pmem ? 1.0 : 0.0; +} + double expr__get_literal(const char *literal, const struct expr_scanner_ctx *ctx) { const struct cpu_topology *topology; @@ -449,6 +464,10 @@ double expr__get_literal(const char *literal, const struct expr_scanner_ctx *ctx result = perf_pmu__cpu_slots_per_cycle(); goto out; } + if (!strcmp("#has_pmem", literal)) { + result = has_pmem(); + goto out; + } pr_err("Unrecognized literal '%s'", literal); out: -- cgit v1.2.3-58-ga151 From 31c5ba6c2556f80842d464ed743aff50890c8208 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 24 Mar 2023 00:22:18 -0700 Subject: perf vendor events intel: Update metrics to detect pmem at runtime By detecting whether nvdimms are installed at runtime the number of events can be reduced if it isn't. These changes come from this PR: https://github.com/intel/perfmon/pull/63 Reviewed-by: Kan Liang Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Dan Williams Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Samantha Alt Cc: Weilin Wang Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230324072218.181880-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json | 10 +++++----- tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json | 10 +++++----- tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json | 10 +++++----- 3 files changed, 15 insertions(+), 15 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json b/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json index 4e993a3220e3..8f7dc72accd0 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json @@ -201,7 +201,7 @@ { "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks - tma_l2_bound - tma_pmm_bound", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks - tma_l2_bound - tma_pmm_bound if #has_pmem > 0 else CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks - tma_l2_bound)", "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_dram_bound", "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", @@ -933,7 +933,7 @@ }, { "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]", - "MetricExpr": "1e9 * (UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS) / imc_0@event\\=0x0@", + "MetricExpr": "(1e9 * (UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS) / imc_0@event\\=0x0@ if #has_pmem > 0 else 0)", "MetricGroup": "Mem;MemoryLat;Server;SoC", "MetricName": "tma_info_mem_pmm_read_latency", "PublicDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches" @@ -998,13 +998,13 @@ }, { "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]", - "MetricExpr": "64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time", + "MetricExpr": "(64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time if #has_pmem > 0 else 0)", "MetricGroup": "Mem;MemoryBW;Server;SoC", "MetricName": "tma_info_pmm_read_bw" }, { "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]", - "MetricExpr": "64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time", + "MetricExpr": "(64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time if #has_pmem > 0 else 0)", "MetricGroup": "Mem;MemoryBW;Server;SoC", "MetricName": "tma_info_pmm_write_bw" }, @@ -1310,7 +1310,7 @@ { "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0)", + "MetricExpr": "(((1 - ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) if #has_pmem > 0 else 0) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) if #has_pmem > 0 else 0))) if #has_pmem > 0 else 0)) * (CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0) if #has_pmem > 0 else 0)", "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_pmm_bound", "MetricThreshold": "tma_pmm_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", diff --git a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json index 8109088a4df7..0f9b174dfc22 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json @@ -186,7 +186,7 @@ { "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks - tma_l2_bound - tma_pmm_bound", + "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks - tma_l2_bound - tma_pmm_bound if #has_pmem > 0 else CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks - tma_l2_bound)", "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_dram_bound", "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", @@ -918,7 +918,7 @@ }, { "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]", - "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / cha_0@event\\=0x0@", + "MetricExpr": "(1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / cha_0@event\\=0x0@ if #has_pmem > 0 else 0)", "MetricGroup": "Mem;MemoryLat;Server;SoC", "MetricName": "tma_info_mem_pmm_read_latency", "PublicDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches" @@ -984,13 +984,13 @@ }, { "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]", - "MetricExpr": "64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time", + "MetricExpr": "(64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time if #has_pmem > 0 else 0)", "MetricGroup": "Mem;MemoryBW;Server;SoC", "MetricName": "tma_info_pmm_read_bw" }, { "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]", - "MetricExpr": "64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time", + "MetricExpr": "(64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time if #has_pmem > 0 else 0)", "MetricGroup": "Mem;MemoryBW;Server;SoC", "MetricName": "tma_info_pmm_write_bw" }, @@ -1298,7 +1298,7 @@ }, { "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a", - "MetricExpr": "((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0)", + "MetricExpr": "(((1 - ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) if #has_pmem > 0 else 0) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) if #has_pmem > 0 else 0))) if #has_pmem > 0 else 0)) * (CYCLE_ACTIVITY.STALLS_L3_MISS / tma_info_clks + (CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_info_clks - tma_l2_bound) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0) if #has_pmem > 0 else 0)", "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_pmm_bound", "MetricThreshold": "tma_pmm_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json index 149cc4c07fb5..126300b7ae77 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json @@ -185,7 +185,7 @@ { "BriefDescription": "This metric estimates how often the CPU was stalled on accesses to external memory (DRAM) by loads", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_clks - tma_pmm_bound", + "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_clks - tma_pmm_bound if #has_pmem > 0 else MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_clks)", "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_dram_bound", "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", @@ -968,7 +968,7 @@ }, { "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]", - "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / uncore_cha_0@event\\=0x1@", + "MetricExpr": "(1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / uncore_cha_0@event\\=0x1@ if #has_pmem > 0 else 0)", "MetricGroup": "Mem;MemoryLat;Server;SoC", "MetricName": "tma_info_mem_pmm_read_latency", "PublicDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches" @@ -1034,13 +1034,13 @@ }, { "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]", - "MetricExpr": "64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time", + "MetricExpr": "(64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time if #has_pmem > 0 else 0)", "MetricGroup": "Mem;MemoryBW;Server;SoC", "MetricName": "tma_info_pmm_read_bw" }, { "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]", - "MetricExpr": "64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time", + "MetricExpr": "(64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time if #has_pmem > 0 else 0)", "MetricGroup": "Mem;MemoryBW;Server;SoC", "MetricName": "tma_info_pmm_write_bw" }, @@ -1406,7 +1406,7 @@ }, { "BriefDescription": "This metric roughly estimates (based on idle latencies) how often the CPU was stalled on accesses to external 3D-Xpoint (Crystal Ridge, a.k.a", - "MetricExpr": "((1 - (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))))) * (MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_clks) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0)", + "MetricExpr": "(((1 - ((19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS))) / (19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + 10 * (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS)) + (25 * (MEM_LOAD_RETIRED.LOCAL_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) if #has_pmem > 0 else 0) + 33 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) if #has_pmem > 0 else 0))) if #has_pmem > 0 else 0)) * (MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_clks) if 1e6 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM) > MEM_LOAD_RETIRED.L1_MISS else 0) if #has_pmem > 0 else 0)", "MetricGroup": "MemoryBound;Server;TmaL3mem;TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_pmm_bound", "MetricThreshold": "tma_pmm_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)", -- cgit v1.2.3-58-ga151 From 9835b742ac3ee16dee361e7ccda8022f99d1cd94 Mon Sep 17 00:00:00 2001 From: Patrice Duroux Date: Fri, 3 Mar 2023 20:30:58 +0100 Subject: perf tests record_offcpu.sh: Fix redirection of stderr to stdin It's not 2&>1, the correct is 2>&1 Fixes: ade1d0307b2fb3d9 ("perf offcpu: Update offcpu test for child process") Signed-off-by: Patrice Duroux Acked-by: Ian Rogers Cc: Namhyung Kim Link: https://lore.kernel.org/r/20230303193058.21274-1-patrice.duroux@gmail.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/shell/record_offcpu.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/tests/shell/record_offcpu.sh b/tools/perf/tests/shell/record_offcpu.sh index 24f81ff85793..155d4856551a 100755 --- a/tools/perf/tests/shell/record_offcpu.sh +++ b/tools/perf/tests/shell/record_offcpu.sh @@ -65,7 +65,7 @@ test_offcpu_child() { # perf bench sched messaging creates 400 processes if ! perf record --off-cpu -e dummy -o ${perfdata} -- \ - perf bench sched messaging -g 10 > /dev/null 2&>1 + perf bench sched messaging -g 10 > /dev/null 2>&1 then echo "Child task off-cpu test [Failed record]" err=1 -- cgit v1.2.3-58-ga151 From 7f8d3fbe094be59a286f3b43431668221123ff30 Mon Sep 17 00:00:00 2001 From: Patrice Duroux Date: Fri, 3 Mar 2023 20:20:56 +0100 Subject: perf tests test_bridge_fdb_stress.sh: Fix redirection of stderr to stdin It's not 2&>1, the correct is 2>&1. Signed-off-by: Patrice Duroux Cc: linux-kselftest@vger.kernel.org Link: https://lore.kernel.org/r/20230303193058.21274-1-patrice.duroux@gmail.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/testing/selftests/drivers/net/dsa/test_bridge_fdb_stress.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/testing/selftests/drivers/net/dsa/test_bridge_fdb_stress.sh b/tools/testing/selftests/drivers/net/dsa/test_bridge_fdb_stress.sh index a1f269ee84da..92acab83fbe2 100755 --- a/tools/testing/selftests/drivers/net/dsa/test_bridge_fdb_stress.sh +++ b/tools/testing/selftests/drivers/net/dsa/test_bridge_fdb_stress.sh @@ -31,7 +31,7 @@ trap 'cleanup' EXIT eth=${NETIFS[p1]} -ip link del br0 2&>1 >/dev/null || : +ip link del br0 2>&1 >/dev/null || : ip link add br0 type bridge && ip link set $eth master br0 (while :; do -- cgit v1.2.3-58-ga151 From 51ea4cb96f35ae2f31d45d9a0dbf30da13bbe441 Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Thu, 16 Mar 2023 08:49:46 +0100 Subject: perf stat: Suppress warning when using cpum_cf events on s390 Running command perf stat -vv -e cpu_cycles -C0 -- true displays this warning: Attempting to add event pmu 'cpum_cf' with 'cpu_cycles,' that may result in non-fatal errors Make the PMU cpum_cf selectable and avoid this warning. While at it also fix this warning for PMUs pai_crypto and pai_ext. Output before: # ./perf stat -vv -e cpu_cycles -C0 -- true Using CPUID IBM,3931,704,A01,3.7,002f Attempting to add event pmu 'cpum_cf' with 'cpu_cycles,' that may result in non-fatal errors After aliases, add event pmu 'cpum_cf' with 'event,' that may result in non-fatal errors cpu_cycles -> cpum_cf/event=0/ Control descriptor is not initialized ------------------------------------------------------------ perf_event_attr: type 10 size 128 config 0x1001 sample_type IDENTIFIER read_format TOTAL_TIME_ENABLED|TOTAL_TIME_RUNNING disabled 1 inherit 1 exclude_guest 1 ------------------------------------------------------------ sys_perf_event_open: pid -1 cpu 0 group_fd -1 flags 0x8 = 3 cpu_cycles: 0: 290434 2479172 2479172: cpu_cycles: 290434 2479172 2479172 Performance counter stats for 'CPU(s) 0': 290,434 cpu_cycles 0.002465617 seconds time elapsed # Now the warning "Attempting to add event pmu 'cpum_cf' ..." does not show up anymore. Output after: # ./perf stat -vv -e cpu_cycles -C0 -- true Using CPUID IBM,3931,704,A01,3.7,002f After aliases, add event pmu 'cpum_cf' with 'event,' that may result in non-fatal errors cpu_cycles -> cpum_cf/event=0/ Control descriptor is not initialized .... Performance counter stats for 'CPU(s) 0': 357,023 cpu_cycles 0.002454995 seconds time elapsed # Signed-off-by: Thomas Richter Cc: Heiko Carstens Cc: Sumanth Korikkar Cc: Sven Schnelle Cc: Vasily Gorbik Link: https://lore.kernel.org/r/20230316074946.41110-1-tmricht@linux.ibm.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/s390/util/Build | 1 + tools/perf/arch/s390/util/pmu.c | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 tools/perf/arch/s390/util/pmu.c (limited to 'tools') diff --git a/tools/perf/arch/s390/util/Build b/tools/perf/arch/s390/util/Build index db6884086997..fa66f15a14ec 100644 --- a/tools/perf/arch/s390/util/Build +++ b/tools/perf/arch/s390/util/Build @@ -6,5 +6,6 @@ perf-$(CONFIG_DWARF) += dwarf-regs.o perf-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o perf-y += machine.o +perf-y += pmu.o perf-$(CONFIG_AUXTRACE) += auxtrace.o diff --git a/tools/perf/arch/s390/util/pmu.c b/tools/perf/arch/s390/util/pmu.c new file mode 100644 index 000000000000..11f03f32e3fd --- /dev/null +++ b/tools/perf/arch/s390/util/pmu.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * Copyright IBM Corp. 2023 + * Author(s): Thomas Richter + */ + +#include + +#include "../../../util/pmu.h" + +#define S390_PMUPAI_CRYPTO "pai_crypto" +#define S390_PMUPAI_EXT "pai_ext" +#define S390_PMUCPUM_CF "cpum_cf" + +struct perf_event_attr *perf_pmu__get_default_config(struct perf_pmu *pmu) +{ + if (!strcmp(pmu->name, S390_PMUPAI_CRYPTO) || + !strcmp(pmu->name, S390_PMUPAI_EXT) || + !strcmp(pmu->name, S390_PMUCPUM_CF)) + pmu->selectable = true; + return NULL; +} -- cgit v1.2.3-58-ga151 From ece7f7c0507cc147f72e117e22732091db758885 Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Tue, 21 Mar 2023 14:57:01 +0800 Subject: perf bench syscall: Add fork syscall benchmark This is a follow up patch for the execve bench which is actually fork + execve, it makes sense to add the fork syscall benchmark to compare the execve part precisely. Some archs have no __NR_fork definition which is used only as a check condition to call test_fork(), let us just define it as -1 to avoid build error. Suggested-by: Namhyung Kim Signed-off-by: Tiezhu Yang Acked-by: Namhyung Kim Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Peter Zijlstra Cc: loongson-kernel@lists.loongnix.cn Link: https://lore.kernel.org/r/1679381821-22736-1-git-send-email-yangtiezhu@loongson.cn Signed-off-by: Arnaldo Carvalho de Melo --- tools/arch/x86/include/uapi/asm/unistd_32.h | 4 ++-- tools/arch/x86/include/uapi/asm/unistd_64.h | 3 +++ tools/perf/bench/bench.h | 1 + tools/perf/bench/syscall.c | 35 +++++++++++++++++++++++++++++ tools/perf/builtin-bench.c | 1 + 5 files changed, 42 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/arch/x86/include/uapi/asm/unistd_32.h b/tools/arch/x86/include/uapi/asm/unistd_32.h index 2712d5e03e2e..b8ddfc4c4ab0 100644 --- a/tools/arch/x86/include/uapi/asm/unistd_32.h +++ b/tools/arch/x86/include/uapi/asm/unistd_32.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __NR_execve -#define __NR_execve 11 +#ifndef __NR_fork +#define __NR_fork 2 #endif #ifndef __NR_getppid #define __NR_getppid 64 diff --git a/tools/arch/x86/include/uapi/asm/unistd_64.h b/tools/arch/x86/include/uapi/asm/unistd_64.h index a6f7fe84d4df..f70d2cada256 100644 --- a/tools/arch/x86/include/uapi/asm/unistd_64.h +++ b/tools/arch/x86/include/uapi/asm/unistd_64.h @@ -1,4 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __NR_fork +#define __NR_fork 57 +#endif #ifndef __NR_execve #define __NR_execve 59 #endif diff --git a/tools/perf/bench/bench.h b/tools/perf/bench/bench.h index e43893151a3e..edfc25793cca 100644 --- a/tools/perf/bench/bench.h +++ b/tools/perf/bench/bench.h @@ -23,6 +23,7 @@ int bench_sched_messaging(int argc, const char **argv); int bench_sched_pipe(int argc, const char **argv); int bench_syscall_basic(int argc, const char **argv); int bench_syscall_getpgid(int argc, const char **argv); +int bench_syscall_fork(int argc, const char **argv); int bench_syscall_execve(int argc, const char **argv); int bench_mem_memcpy(int argc, const char **argv); int bench_mem_memset(int argc, const char **argv); diff --git a/tools/perf/bench/syscall.c b/tools/perf/bench/syscall.c index fe79f7f3091e..ea4dfc07cbd6 100644 --- a/tools/perf/bench/syscall.c +++ b/tools/perf/bench/syscall.c @@ -18,6 +18,10 @@ #include #include +#ifndef __NR_fork +#define __NR_fork -1 +#endif + #define LOOPS_DEFAULT 10000000 static int loops = LOOPS_DEFAULT; @@ -31,6 +35,23 @@ static const char * const bench_syscall_usage[] = { NULL }; +static void test_fork(void) +{ + pid_t pid = fork(); + + if (pid < 0) { + fprintf(stderr, "fork failed\n"); + exit(1); + } else if (pid == 0) { + exit(0); + } else { + if (waitpid(pid, NULL, 0) < 0) { + fprintf(stderr, "waitpid failed\n"); + exit(1); + } + } +} + static void test_execve(void) { const char *pathname = "/bin/true"; @@ -71,6 +92,12 @@ static int bench_syscall_common(int argc, const char **argv, int syscall) case __NR_getpgid: getpgid(0); break; + case __NR_fork: + test_fork(); + /* Only loop 10000 times to save time */ + if (i == 10000) + loops = 10000; + break; case __NR_execve: test_execve(); /* Only loop 10000 times to save time */ @@ -92,6 +119,9 @@ static int bench_syscall_common(int argc, const char **argv, int syscall) case __NR_getpgid: name = "getpgid()"; break; + case __NR_fork: + name = "fork()"; + break; case __NR_execve: name = "execve()"; break; @@ -143,6 +173,11 @@ int bench_syscall_getpgid(int argc, const char **argv) return bench_syscall_common(argc, argv, __NR_getpgid); } +int bench_syscall_fork(int argc, const char **argv) +{ + return bench_syscall_common(argc, argv, __NR_fork); +} + int bench_syscall_execve(int argc, const char **argv) { return bench_syscall_common(argc, argv, __NR_execve); diff --git a/tools/perf/builtin-bench.c b/tools/perf/builtin-bench.c index 814e9afc86f6..d0fcc3cdc185 100644 --- a/tools/perf/builtin-bench.c +++ b/tools/perf/builtin-bench.c @@ -53,6 +53,7 @@ static struct bench sched_benchmarks[] = { static struct bench syscall_benchmarks[] = { { "basic", "Benchmark for basic getppid(2) calls", bench_syscall_basic }, { "getpgid", "Benchmark for getpgid(2) calls", bench_syscall_getpgid }, + { "fork", "Benchmark for fork(2) calls", bench_syscall_fork }, { "execve", "Benchmark for execve(2) calls", bench_syscall_execve }, { "all", "Run all syscall benchmarks", NULL }, { NULL, NULL, NULL }, -- cgit v1.2.3-58-ga151 From ecd4960d908e27e40b63a7046df2f942c148c6f6 Mon Sep 17 00:00:00 2001 From: Yang Jihong Date: Fri, 24 Mar 2023 03:27:02 +0000 Subject: perf ftrace: Make system wide the default target for latency subcommand If no target is specified for 'latency' subcommand, the execution fails because - 1 (invalid value) is written to set_ftrace_pid tracefs file. Make system wide the default target, which is the same as the default behavior of 'trace' subcommand. Before the fix: # perf ftrace latency -T schedule failed to set ftrace pid After the fix: # perf ftrace latency -T schedule ^C# DURATION | COUNT | GRAPH | 0 - 1 us | 0 | | 1 - 2 us | 0 | | 2 - 4 us | 0 | | 4 - 8 us | 2828 | #### | 8 - 16 us | 23953 | ######################################## | 16 - 32 us | 408 | | 32 - 64 us | 318 | | 64 - 128 us | 4 | | 128 - 256 us | 3 | | 256 - 512 us | 0 | | 512 - 1024 us | 1 | | 1 - 2 ms | 4 | | 2 - 4 ms | 0 | | 4 - 8 ms | 0 | | 8 - 16 ms | 0 | | 16 - 32 ms | 0 | | 32 - 64 ms | 0 | | 64 - 128 ms | 0 | | 128 - 256 ms | 4 | | 256 - 512 ms | 2 | | 512 - 1024 ms | 0 | | 1 - ... s | 0 | | Fixes: 53be50282269b46c ("perf ftrace: Add 'latency' subcommand") Signed-off-by: Yang Jihong Acked-by: Namhyung Kim Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230324032702.109964-1-yangjihong1@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-ftrace.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-ftrace.c b/tools/perf/builtin-ftrace.c index 73d51ce84c3a..810e3376c7d6 100644 --- a/tools/perf/builtin-ftrace.c +++ b/tools/perf/builtin-ftrace.c @@ -1228,10 +1228,12 @@ int cmd_ftrace(int argc, const char **argv) goto out_delete_filters; } + /* Make system wide (-a) the default target. */ + if (!argc && target__none(&ftrace.target)) + ftrace.target.system_wide = true; + switch (subcmd) { case PERF_FTRACE_TRACE: - if (!argc && target__none(&ftrace.target)) - ftrace.target.system_wide = true; cmd_func = __cmd_ftrace; break; case PERF_FTRACE_LATENCY: -- cgit v1.2.3-58-ga151 From 5d9df8731c0941f3add30f96745a62586a0c9d52 Mon Sep 17 00:00:00 2001 From: Kajol Jain Date: Tue, 28 Mar 2023 16:59:08 +0530 Subject: perf vendor events power9: Remove UTF-8 characters from JSON files Commit 3c22ba5243040c13 ("perf vendor events powerpc: Update POWER9 events") added and updated power9 PMU JSON events. However some of the JSON events which are part of other.json and pipeline.json files, contains UTF-8 characters in their brief description. Having UTF-8 character could breaks the perf build on some distros. Fix this issue by removing the UTF-8 characters from other.json and pipeline.json files. Result without the fix: [command]# file -i pmu-events/arch/powerpc/power9/* pmu-events/arch/powerpc/power9/cache.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/floating-point.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/frontend.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/marked.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/memory.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/metrics.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/nest_metrics.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/other.json: application/json; charset=utf-8 pmu-events/arch/powerpc/power9/pipeline.json: application/json; charset=utf-8 pmu-events/arch/powerpc/power9/pmc.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/translation.json: application/json; charset=us-ascii [command]# Result with the fix: [command]# file -i pmu-events/arch/powerpc/power9/* pmu-events/arch/powerpc/power9/cache.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/floating-point.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/frontend.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/marked.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/memory.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/metrics.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/nest_metrics.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/other.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/pipeline.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/pmc.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/translation.json: application/json; charset=us-ascii [command]# Fixes: 3c22ba5243040c13 ("perf vendor events powerpc: Update POWER9 events") Reported-by: Arnaldo Carvalho de Melo Signed-off-by: Kajol Jain Acked-by: Ian Rogers Tested-by: Arnaldo Carvalho de Melo Cc: Athira Rajeev Cc: Disha Goel Cc: Jiri Olsa Cc: Madhavan Srinivasan Cc: Sukadev Bhattiprolu Cc: linuxppc-dev@lists.ozlabs.org Link: https://lore.kernel.org/lkml/ZBxP77deq7ikTxwG@kernel.org/ Link: https://lore.kernel.org/r/20230328112908.113158-1-kjain@linux.ibm.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/powerpc/power9/other.json | 4 ++-- tools/perf/pmu-events/arch/powerpc/power9/pipeline.json | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/powerpc/power9/other.json b/tools/perf/pmu-events/arch/powerpc/power9/other.json index 3f69422c21f9..f10bd554521a 100644 --- a/tools/perf/pmu-events/arch/powerpc/power9/other.json +++ b/tools/perf/pmu-events/arch/powerpc/power9/other.json @@ -1417,7 +1417,7 @@ { "EventCode": "0x45054", "EventName": "PM_FMA_CMPL", - "BriefDescription": "two flops operation completed (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only. " + "BriefDescription": "two flops operation completed (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only." }, { "EventCode": "0x201E8", @@ -2017,7 +2017,7 @@ { "EventCode": "0xC0BC", "EventName": "PM_LSU_FLUSH_OTHER", - "BriefDescription": "Other LSU flushes including: Sync (sync ack from L2 caused search of LRQ for oldest snooped load, This will either signal a Precise Flush of the oldest snooped loa or a Flush Next PPC); Data Valid Flush Next (several cases of this, one example is store and reload are lined up such that a store-hit-reload scenario exists and the CDF has already launched and has gotten bad/stale data); Bad Data Valid Flush Next (might be a few cases of this, one example is a larxa (D$ hit) return data and dval but can't allocate to LMQ (LMQ full or other reason). Already gave dval but can't watch it for snoop_hit_larx. Need to take the “bad dval” back and flush all younger ops)" + "BriefDescription": "Other LSU flushes including: Sync (sync ack from L2 caused search of LRQ for oldest snooped load, This will either signal a Precise Flush of the oldest snooped loa or a Flush Next PPC); Data Valid Flush Next (several cases of this, one example is store and reload are lined up such that a store-hit-reload scenario exists and the CDF has already launched and has gotten bad/stale data); Bad Data Valid Flush Next (might be a few cases of this, one example is a larxa (D$ hit) return data and dval but can't allocate to LMQ (LMQ full or other reason). Already gave dval but can't watch it for snoop_hit_larx. Need to take the 'bad dval' back and flush all younger ops)" }, { "EventCode": "0x5094", diff --git a/tools/perf/pmu-events/arch/powerpc/power9/pipeline.json b/tools/perf/pmu-events/arch/powerpc/power9/pipeline.json index d0265f255de2..723bffa41c44 100644 --- a/tools/perf/pmu-events/arch/powerpc/power9/pipeline.json +++ b/tools/perf/pmu-events/arch/powerpc/power9/pipeline.json @@ -442,7 +442,7 @@ { "EventCode": "0x4D052", "EventName": "PM_2FLOP_CMPL", - "BriefDescription": "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg " + "BriefDescription": "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg" }, { "EventCode": "0x1F142", -- cgit v1.2.3-58-ga151 From c8bb2d76a40ac0ccf6303d369e536fddcde847fb Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Thu, 16 Mar 2023 21:41:54 +0200 Subject: perf symbols: Fix use-after-free in get_plt_got_name() Fix use-after-free in get_plt_got_name(). Discovered using EXTRA_CFLAGS="-fsanitize=undefined -fsanitize=address". Fixes: ce4c8e7966f317ef ("perf symbols: Get symbols for .plt.got for x86-64") Reported-by: kernel test robot Signed-off-by: Adrian Hunter Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Jiri Olsa Cc: Namhyung Kim Link: https://lore.kernel.org/oe-lkp/202303061424.6ad43294-yujie.liu@intel.com Link: https://lore.kernel.org/r/20230316194156.8320-2-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/symbol-elf.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/symbol-elf.c b/tools/perf/util/symbol-elf.c index c0a2de42c51b..7ef5f6d7d415 100644 --- a/tools/perf/util/symbol-elf.c +++ b/tools/perf/util/symbol-elf.c @@ -557,6 +557,7 @@ static bool get_plt_got_name(GElf_Shdr *shdr, size_t i, const char *sym_name; char *demangled; GElf_Sym sym; + bool result; u32 disp; if (!di->sorted) @@ -583,9 +584,11 @@ static bool get_plt_got_name(GElf_Shdr *shdr, size_t i, snprintf(buf, buf_sz, "%s@plt", sym_name); + result = *sym_name; + free(demangled); - return *sym_name; + return result; } static int dso__synthesize_plt_got_symbols(struct dso *dso, Elf *elf, -- cgit v1.2.3-58-ga151 From a2410b579c72242ac0f77b3768093d8c1b48012e Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Thu, 16 Mar 2023 21:41:55 +0200 Subject: perf symbols: Fix unaligned access in get_x86_64_plt_disp() Use memcpy() to avoid unaligned access. Discovered using EXTRA_CFLAGS="-fsanitize=undefined -fsanitize=address". Fixes: ce4c8e7966f317ef ("perf symbols: Get symbols for .plt.got for x86-64") Reported-by: kernel test robot Signed-off-by: Adrian Hunter Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Jiri Olsa Cc: Namhyung Kim Link: https://lore.kernel.org/oe-lkp/202303061424.6ad43294-yujie.liu@intel.com Link: https://lore.kernel.org/r/20230316194156.8320-2-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/symbol-elf.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/symbol-elf.c b/tools/perf/util/symbol-elf.c index 7ef5f6d7d415..ae810d4cf3cd 100644 --- a/tools/perf/util/symbol-elf.c +++ b/tools/perf/util/symbol-elf.c @@ -542,9 +542,12 @@ static u32 get_x86_64_plt_disp(const u8 *p) n += 1; /* jmp with 4-byte displacement */ if (p[n] == 0xff && p[n + 1] == 0x25) { + u32 disp; + n += 2; /* Also add offset from start of entry to end of instruction */ - return n + 4 + le32toh(*(const u32 *)(p + n)); + memcpy(&disp, p + n, sizeof(disp)); + return n + 4 + le32toh(disp); } return 0; } -- cgit v1.2.3-58-ga151 From f5ceb159d30b87975a49b8a230ffa76bae6684b2 Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Thu, 16 Mar 2023 21:41:56 +0200 Subject: perf tools: Avoid warning in do_realloc_array_as_needed() do_realloc_array_as_needed() used memcpy() of zero size with a NULL pointer. Check the size first to avoid sanitize warning. Discovered using EXTRA_CFLAGS="-fsanitize=undefined -fsanitize=address". Reported-by: kernel test robot Signed-off-by: Adrian Hunter Acked-by: Ian Rogers Cc: Jiri Olsa Cc: Namhyung Kim Link: https://lore.kernel.org/oe-lkp/202303061424.6ad43294-yujie.liu@intel.com Link: https://lore.kernel.org/r/20230316194156.8320-2-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/util.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/util.c b/tools/perf/util/util.c index b356c9f7f0c3..089208b51e68 100644 --- a/tools/perf/util/util.c +++ b/tools/perf/util/util.c @@ -524,7 +524,8 @@ int do_realloc_array_as_needed(void **arr, size_t *arr_sz, size_t x, size_t msz, new_arr = calloc(new_sz, msz); if (!new_arr) return -ENOMEM; - memcpy(new_arr, *arr, *arr_sz * msz); + if (*arr_sz) + memcpy(new_arr, *arr, *arr_sz * msz); if (init_val) { for (i = *arr_sz; i < new_sz; i++) memcpy(new_arr + (i * msz), init_val, msz); -- cgit v1.2.3-58-ga151 From 333b1b11179b7908e3f3a06a2208dcecb0c971ef Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Tue, 28 Mar 2023 16:55:38 -0700 Subject: perf annotate: Delete session for debug builds Use the debug build indicator as the guide to free the session. This implements a behavior described in a comment, which is consequentially removed. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Andres Freund Cc: German Gomez Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Peter Zijlstra Cc: Sandipan Das Cc: Tom Rix Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20230328235543.1082207-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-annotate.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-annotate.c b/tools/perf/builtin-annotate.c index 4750fac7bf93..98d1b6379230 100644 --- a/tools/perf/builtin-annotate.c +++ b/tools/perf/builtin-annotate.c @@ -692,16 +692,12 @@ int cmd_annotate(int argc, const char **argv) out_delete: /* - * Speed up the exit process, for large files this can - * take quite a while. - * - * XXX Enable this when using valgrind or if we ever - * librarize this command. - * - * Also experiment with obstacks to see how much speed - * up we'll get here. - * - * perf_session__delete(session); + * Speed up the exit process by only deleting for debug builds. For + * large files this can save time. */ +#ifndef NDEBUG + perf_session__delete(annotate.session); +#endif + return ret; } -- cgit v1.2.3-58-ga151 From 8f08c363fd6c682d10f2b055d4287ad1e54e76ea Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Tue, 28 Mar 2023 16:55:39 -0700 Subject: perf report: Additional config warnings If the default_sort_order isn't correctly strdup-ed warn and return an error. Debug warn if no option is matched. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Andres Freund Cc: German Gomez Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Peter Zijlstra Cc: Sandipan Das Cc: Tom Rix Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20230328235543.1082207-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-report.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'tools') diff --git a/tools/perf/builtin-report.c b/tools/perf/builtin-report.c index 6400615b5e98..500f9d8902e7 100644 --- a/tools/perf/builtin-report.c +++ b/tools/perf/builtin-report.c @@ -143,6 +143,10 @@ static int report__config(const char *var, const char *value, void *cb) if (!strcmp(var, "report.sort_order")) { default_sort_order = strdup(value); + if (!default_sort_order) { + pr_err("Not enough memory for report.sort_order\n"); + return -1; + } return 0; } @@ -151,6 +155,7 @@ static int report__config(const char *var, const char *value, void *cb) return 0; } + pr_debug("%s variable unknown, ignoring...", var); return 0; } -- cgit v1.2.3-58-ga151 From 217b7d41ea2038e52991b7a600a0b958330d8ae6 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Tue, 28 Mar 2023 16:55:40 -0700 Subject: perf annotate: Add init/exit to annotation_options remove default The annotation__default_options global variable was used to initialize annotation_options. Switch to the init/exit pattern as later changes will give ownership over strings and this will be necessary to avoid memory leaks. Committer note: Fix the GTK2=1 build, hist_entry__gtk_annotate() needs to receive a 'struct annotation_options' pointer. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Andres Freund Cc: German Gomez Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Peter Zijlstra Cc: Sandipan Das Cc: Tom Rix Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20230328235543.1082207-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-annotate.c | 6 ++++-- tools/perf/builtin-report.c | 7 ++++--- tools/perf/builtin-top.c | 4 +++- tools/perf/ui/gtk/annotate.c | 6 ++++-- tools/perf/ui/gtk/gtk.h | 2 ++ tools/perf/util/annotate.c | 25 +++++++++++++++++-------- tools/perf/util/annotate.h | 5 +++-- 7 files changed, 37 insertions(+), 18 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-annotate.c b/tools/perf/builtin-annotate.c index 98d1b6379230..997a1e65d090 100644 --- a/tools/perf/builtin-annotate.c +++ b/tools/perf/builtin-annotate.c @@ -352,6 +352,7 @@ find_next: int ret; int (*annotate)(struct hist_entry *he, struct evsel *evsel, + struct annotation_options *options, struct hist_browser_timer *hbt); annotate = dlsym(perf_gtk_handle, @@ -361,7 +362,7 @@ find_next: return; } - ret = annotate(he, evsel, NULL); + ret = annotate(he, evsel, &ann->opts, NULL); if (!ret || !ann->skip_missing) return; @@ -509,7 +510,6 @@ int cmd_annotate(int argc, const char **argv) .ordered_events = true, .ordering_requires_timestamps = true, }, - .opts = annotation__default_options, }; struct perf_data data = { .mode = PERF_DATA_MODE_READ, @@ -598,6 +598,7 @@ int cmd_annotate(int argc, const char **argv) set_option_flag(options, 0, "show-total-period", PARSE_OPT_EXCLUSIVE); set_option_flag(options, 0, "show-nr-samples", PARSE_OPT_EXCLUSIVE); + annotation_options__init(&annotate.opts); ret = hists__init(); if (ret < 0) @@ -698,6 +699,7 @@ out_delete: #ifndef NDEBUG perf_session__delete(annotate.session); #endif + annotation_options__exit(&annotate.opts); return ret; } diff --git a/tools/perf/builtin-report.c b/tools/perf/builtin-report.c index 500f9d8902e7..b41e1219d153 100644 --- a/tools/perf/builtin-report.c +++ b/tools/perf/builtin-report.c @@ -728,8 +728,7 @@ static int hists__resort_cb(struct hist_entry *he, void *arg) if (rep->symbol_ipc && sym && !sym->annotate2) { struct evsel *evsel = hists_to_evsel(he->hists); - symbol__annotate2(&he->ms, evsel, - &annotation__default_options, NULL); + symbol__annotate2(&he->ms, evsel, &rep->annotation_opts, NULL); } return 0; @@ -1223,7 +1222,6 @@ int cmd_report(int argc, const char **argv) .max_stack = PERF_MAX_STACK_DEPTH, .pretty_printing_style = "normal", .socket_filter = -1, - .annotation_opts = annotation__default_options, .skip_empty = true, }; char *sort_order_help = sort_help("sort by key(s):"); @@ -1403,6 +1401,8 @@ int cmd_report(int argc, const char **argv) if (ret < 0) goto exit; + annotation_options__init(&report.annotation_opts); + ret = perf_config(report__config, &report); if (ret) goto exit; @@ -1706,6 +1706,7 @@ error: zstd_fini(&(session->zstd_data)); perf_session__delete(session); exit: + annotation_options__exit(&report.annotation_opts); free(sort_order_help); free(field_order_help); return ret; diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c index d4b5b02bab73..592eb827fba9 100644 --- a/tools/perf/builtin-top.c +++ b/tools/perf/builtin-top.c @@ -1435,7 +1435,6 @@ int cmd_top(int argc, const char **argv) .sample_time_set = true, }, .max_stack = sysctl__max_stack(), - .annotation_opts = annotation__default_options, .nr_threads_synthesize = UINT_MAX, }; struct record_opts *opts = &top.record_opts; @@ -1587,6 +1586,8 @@ int cmd_top(int argc, const char **argv) if (status < 0) return status; + annotation_options__init(&top.annotation_opts); + top.annotation_opts.min_pcnt = 5; top.annotation_opts.context = 4; @@ -1783,6 +1784,7 @@ int cmd_top(int argc, const char **argv) out_delete_evlist: evlist__delete(top.evlist); perf_session__delete(top.session); + annotation_options__exit(&top.annotation_opts); return status; } diff --git a/tools/perf/ui/gtk/annotate.c b/tools/perf/ui/gtk/annotate.c index 0a50e962f9a3..a1c021a6d3c1 100644 --- a/tools/perf/ui/gtk/annotate.c +++ b/tools/perf/ui/gtk/annotate.c @@ -162,6 +162,7 @@ static int perf_gtk__annotate_symbol(GtkWidget *window, struct map_symbol *ms, } static int symbol__gtk_annotate(struct map_symbol *ms, struct evsel *evsel, + struct annotation_options *options, struct hist_browser_timer *hbt) { struct symbol *sym = ms->sym; @@ -174,7 +175,7 @@ static int symbol__gtk_annotate(struct map_symbol *ms, struct evsel *evsel, if (ms->map->dso->annotate_warned) return -1; - err = symbol__annotate(ms, evsel, &annotation__default_options, NULL); + err = symbol__annotate(ms, evsel, options, NULL); if (err) { char msg[BUFSIZ]; ms->map->dso->annotate_warned = true; @@ -242,9 +243,10 @@ static int symbol__gtk_annotate(struct map_symbol *ms, struct evsel *evsel, int hist_entry__gtk_annotate(struct hist_entry *he, struct evsel *evsel, + struct annotation_options *options, struct hist_browser_timer *hbt) { - return symbol__gtk_annotate(&he->ms, evsel, hbt); + return symbol__gtk_annotate(&he->ms, evsel, options, hbt); } void perf_gtk__show_annotations(void) diff --git a/tools/perf/ui/gtk/gtk.h b/tools/perf/ui/gtk/gtk.h index a2b497f03fd6..1e84dceb5267 100644 --- a/tools/perf/ui/gtk/gtk.h +++ b/tools/perf/ui/gtk/gtk.h @@ -56,11 +56,13 @@ struct evsel; struct evlist; struct hist_entry; struct hist_browser_timer; +struct annotation_options; int evlist__gtk_browse_hists(struct evlist *evlist, const char *help, struct hist_browser_timer *hbt, float min_pcnt); int hist_entry__gtk_annotate(struct hist_entry *he, struct evsel *evsel, + struct annotation_options *options, struct hist_browser_timer *hbt); void perf_gtk__show_annotations(void); diff --git a/tools/perf/util/annotate.c b/tools/perf/util/annotate.c index db475e44f42f..a984bdae7811 100644 --- a/tools/perf/util/annotate.c +++ b/tools/perf/util/annotate.c @@ -55,14 +55,6 @@ #include -struct annotation_options annotation__default_options = { - .use_offset = true, - .jump_arrows = true, - .annotate_src = true, - .offset_level = ANNOTATION__OFFSET_JUMP_TARGETS, - .percent_type = PERCENT_PERIOD_LOCAL, -}; - static regex_t file_lineno; static struct ins_ops *ins__find(struct arch *arch, const char *name); @@ -3226,6 +3218,23 @@ static int annotation__config(const char *var, const char *value, void *data) return 0; } +void annotation_options__init(struct annotation_options *opt) +{ + memset(opt, 0, sizeof(*opt)); + + /* Default values. */ + opt->use_offset = true; + opt->jump_arrows = true; + opt->annotate_src = true; + opt->offset_level = ANNOTATION__OFFSET_JUMP_TARGETS; + opt->percent_type = PERCENT_PERIOD_LOCAL; +} + + +void annotation_options__exit(struct annotation_options *opt __maybe_unused) +{ +} + void annotation_config__init(struct annotation_options *opt) { perf_config(annotation__config, opt); diff --git a/tools/perf/util/annotate.h b/tools/perf/util/annotate.h index 8934072c39e6..e7238c694465 100644 --- a/tools/perf/util/annotate.h +++ b/tools/perf/util/annotate.h @@ -109,8 +109,6 @@ enum { #define ANNOTATION__MIN_OFFSET_LEVEL ANNOTATION__OFFSET_JUMP_TARGETS -extern struct annotation_options annotation__default_options; - struct annotation; struct sym_hist_entry { @@ -418,6 +416,9 @@ static inline int symbol__tui_annotate(struct map_symbol *ms __maybe_unused, } #endif +void annotation_options__init(struct annotation_options *opt); +void annotation_options__exit(struct annotation_options *opt); + void annotation_config__init(struct annotation_options *opt); int annotate_parse_percent_type(const struct option *opt, const char *_str, -- cgit v1.2.3-58-ga151 From 56d9117c5004e7192d8062da67fef220e4fdcd19 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Tue, 28 Mar 2023 16:55:41 -0700 Subject: perf annotate: Own objdump_path and disassembler_style strings Make struct annotation_options own the strings objdump_path and disassembler_style, freeing them on exit. Add missing strdup for disassembler_style when read from a config file. Committer notes: Converted free(obj->member) to zfree(&obj->member) in annotation_options__exit() Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Andres Freund Cc: German Gomez Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Peter Zijlstra Cc: Sandipan Das Cc: Tom Rix Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20230328235543.1082207-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/common.c | 4 ++-- tools/perf/arch/common.h | 2 +- tools/perf/builtin-annotate.c | 16 ++++++++++++++-- tools/perf/builtin-report.c | 16 ++++++++++++++-- tools/perf/builtin-top.c | 17 +++++++++++++++-- tools/perf/util/annotate.c | 10 ++++++++-- tools/perf/util/annotate.h | 4 ++-- 7 files changed, 56 insertions(+), 13 deletions(-) (limited to 'tools') diff --git a/tools/perf/arch/common.c b/tools/perf/arch/common.c index 59dd875fd5e4..28ac09997928 100644 --- a/tools/perf/arch/common.c +++ b/tools/perf/arch/common.c @@ -130,7 +130,7 @@ static int lookup_triplets(const char *const *triplets, const char *name) } static int perf_env__lookup_binutils_path(struct perf_env *env, - const char *name, const char **path) + const char *name, char **path) { int idx; const char *arch = perf_env__arch(env), *cross_env; @@ -202,7 +202,7 @@ out_error: return -1; } -int perf_env__lookup_objdump(struct perf_env *env, const char **path) +int perf_env__lookup_objdump(struct perf_env *env, char **path) { /* * For live mode, env->arch will be NULL and we can use diff --git a/tools/perf/arch/common.h b/tools/perf/arch/common.h index e965ed8bb328..4224c299cc70 100644 --- a/tools/perf/arch/common.h +++ b/tools/perf/arch/common.h @@ -6,7 +6,7 @@ struct perf_env; -int perf_env__lookup_objdump(struct perf_env *env, const char **path); +int perf_env__lookup_objdump(struct perf_env *env, char **path); bool perf_env__single_address_space(struct perf_env *env); #endif /* ARCH_PERF_COMMON_H */ diff --git a/tools/perf/builtin-annotate.c b/tools/perf/builtin-annotate.c index 997a1e65d090..5b31c4ee8d06 100644 --- a/tools/perf/builtin-annotate.c +++ b/tools/perf/builtin-annotate.c @@ -517,6 +517,7 @@ int cmd_annotate(int argc, const char **argv) struct itrace_synth_opts itrace_synth_opts = { .set = 0, }; + const char *disassembler_style = NULL, *objdump_path = NULL; struct option options[] = { OPT_STRING('i', "input", &input_name, "file", "input file name"), @@ -561,13 +562,13 @@ int cmd_annotate(int argc, const char **argv) "Interleave source code with assembly code (default)"), OPT_BOOLEAN(0, "asm-raw", &annotate.opts.show_asm_raw, "Display raw encoding of assembly instructions (default)"), - OPT_STRING('M', "disassembler-style", &annotate.opts.disassembler_style, "disassembler style", + OPT_STRING('M', "disassembler-style", &disassembler_style, "disassembler style", "Specify disassembler style (e.g. -M intel for intel syntax)"), OPT_STRING(0, "prefix", &annotate.opts.prefix, "prefix", "Add prefix to source file path names in programs (with --prefix-strip)"), OPT_STRING(0, "prefix-strip", &annotate.opts.prefix_strip, "N", "Strip first N entries of source file path name in programs (with --prefix)"), - OPT_STRING(0, "objdump", &annotate.opts.objdump_path, "path", + OPT_STRING(0, "objdump", &objdump_path, "path", "objdump binary to use for disassembly and annotations"), OPT_BOOLEAN(0, "demangle", &symbol_conf.demangle, "Enable symbol demangling"), @@ -618,6 +619,17 @@ int cmd_annotate(int argc, const char **argv) annotate.sym_hist_filter = argv[0]; } + if (disassembler_style) { + annotate.opts.disassembler_style = strdup(disassembler_style); + if (!annotate.opts.disassembler_style) + return -ENOMEM; + } + if (objdump_path) { + annotate.opts.objdump_path = strdup(objdump_path); + if (!annotate.opts.objdump_path) + return -ENOMEM; + } + if (annotate_check_args(&annotate.opts) < 0) return -EINVAL; diff --git a/tools/perf/builtin-report.c b/tools/perf/builtin-report.c index b41e1219d153..15b0cf649e1a 100644 --- a/tools/perf/builtin-report.c +++ b/tools/perf/builtin-report.c @@ -1226,6 +1226,7 @@ int cmd_report(int argc, const char **argv) }; char *sort_order_help = sort_help("sort by key(s):"); char *field_order_help = sort_help("output field(s): overhead period sample "); + const char *disassembler_style = NULL, *objdump_path = NULL; const struct option options[] = { OPT_STRING('i', "input", &input_name, "file", "input file name"), @@ -1322,7 +1323,7 @@ int cmd_report(int argc, const char **argv) "Interleave source code with assembly code (default)"), OPT_BOOLEAN(0, "asm-raw", &report.annotation_opts.show_asm_raw, "Display raw encoding of assembly instructions (default)"), - OPT_STRING('M', "disassembler-style", &report.annotation_opts.disassembler_style, "disassembler style", + OPT_STRING('M', "disassembler-style", &disassembler_style, "disassembler style", "Specify disassembler style (e.g. -M intel for intel syntax)"), OPT_STRING(0, "prefix", &report.annotation_opts.prefix, "prefix", "Add prefix to source file path names in programs (with --prefix-strip)"), @@ -1341,7 +1342,7 @@ int cmd_report(int argc, const char **argv) parse_branch_mode), OPT_BOOLEAN(0, "branch-history", &branch_call_mode, "add last branch records to call history"), - OPT_STRING(0, "objdump", &report.annotation_opts.objdump_path, "path", + OPT_STRING(0, "objdump", &objdump_path, "path", "objdump binary to use for disassembly and annotations"), OPT_BOOLEAN(0, "demangle", &symbol_conf.demangle, "Disable symbol demangling"), @@ -1419,6 +1420,17 @@ int cmd_report(int argc, const char **argv) report.symbol_filter_str = argv[0]; } + if (disassembler_style) { + report.annotation_opts.disassembler_style = strdup(disassembler_style); + if (!report.annotation_opts.disassembler_style) + return -ENOMEM; + } + if (objdump_path) { + report.annotation_opts.objdump_path = strdup(objdump_path); + if (!report.annotation_opts.objdump_path) + return -ENOMEM; + } + if (annotate_check_args(&report.annotation_opts) < 0) { ret = -EINVAL; goto exit; diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c index 592eb827fba9..57a273cd03de 100644 --- a/tools/perf/builtin-top.c +++ b/tools/perf/builtin-top.c @@ -1439,6 +1439,7 @@ int cmd_top(int argc, const char **argv) }; struct record_opts *opts = &top.record_opts; struct target *target = &opts->target; + const char *disassembler_style = NULL, *objdump_path = NULL; const struct option options[] = { OPT_CALLBACK('e', "event", &top.evlist, "event", "event selector. use 'perf list' to list available events", @@ -1524,9 +1525,9 @@ int cmd_top(int argc, const char **argv) OPT_BOOLEAN(0, "demangle-kernel", &symbol_conf.demangle_kernel, "Enable kernel symbol demangling"), OPT_BOOLEAN(0, "no-bpf-event", &top.record_opts.no_bpf_event, "do not record bpf events"), - OPT_STRING(0, "objdump", &top.annotation_opts.objdump_path, "path", + OPT_STRING(0, "objdump", &objdump_path, "path", "objdump binary to use for disassembly and annotations"), - OPT_STRING('M', "disassembler-style", &top.annotation_opts.disassembler_style, "disassembler style", + OPT_STRING('M', "disassembler-style", &disassembler_style, "disassembler style", "Specify disassembler style (e.g. -M intel for intel syntax)"), OPT_STRING(0, "prefix", &top.annotation_opts.prefix, "prefix", "Add prefix to source file path names in programs (with --prefix-strip)"), @@ -1618,6 +1619,18 @@ int cmd_top(int argc, const char **argv) if (argc) usage_with_options(top_usage, options); + if (disassembler_style) { + top.annotation_opts.disassembler_style = strdup(disassembler_style); + if (!top.annotation_opts.disassembler_style) + return -ENOMEM; + } + if (objdump_path) { + top.annotation_opts.objdump_path = strdup(objdump_path); + if (!top.annotation_opts.objdump_path) + return -ENOMEM; + } + + status = symbol__validate_sym_arguments(); if (status) goto out_delete_evlist; diff --git a/tools/perf/util/annotate.c b/tools/perf/util/annotate.c index a984bdae7811..08e041a9b9cc 100644 --- a/tools/perf/util/annotate.c +++ b/tools/perf/util/annotate.c @@ -3206,7 +3206,11 @@ static int annotation__config(const char *var, const char *value, void *data) } else if (!strcmp(var, "annotate.use_offset")) { opt->use_offset = perf_config_bool("use_offset", value); } else if (!strcmp(var, "annotate.disassembler_style")) { - opt->disassembler_style = value; + opt->disassembler_style = strdup(value); + if (!opt->disassembler_style) { + pr_err("Not enough memory for annotate.disassembler_style\n"); + return -1; + } } else if (!strcmp(var, "annotate.demangle")) { symbol_conf.demangle = perf_config_bool("demangle", value); } else if (!strcmp(var, "annotate.demangle_kernel")) { @@ -3231,8 +3235,10 @@ void annotation_options__init(struct annotation_options *opt) } -void annotation_options__exit(struct annotation_options *opt __maybe_unused) +void annotation_options__exit(struct annotation_options *opt) { + zfree(&opt->disassembler_style); + zfree(&opt->objdump_path); } void annotation_config__init(struct annotation_options *opt) diff --git a/tools/perf/util/annotate.h b/tools/perf/util/annotate.h index e7238c694465..1c6335b8333a 100644 --- a/tools/perf/util/annotate.h +++ b/tools/perf/util/annotate.h @@ -94,8 +94,8 @@ struct annotation_options { int min_pcnt; int max_lines; int context; - const char *objdump_path; - const char *disassembler_style; + char *objdump_path; + char *disassembler_style; const char *prefix; const char *prefix_strip; unsigned int percent_type; -- cgit v1.2.3-58-ga151 From 0b02b47e71fa0e006407efd4f647b0e1336a2e8c Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Tue, 28 Mar 2023 16:55:42 -0700 Subject: perf annotate: Allow objdump to be set in perfconfig Allow the setting of the objdump command in the perfconfig. Update man page for this new option. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Andres Freund Cc: German Gomez Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Peter Zijlstra Cc: Sandipan Das Cc: Tom Rix Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20230328235543.1082207-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Documentation/perf-config.txt | 5 ++++- tools/perf/util/annotate.c | 6 ++++++ 2 files changed, 10 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/Documentation/perf-config.txt b/tools/perf/Documentation/perf-config.txt index 39c890ead2dc..697f7f924545 100644 --- a/tools/perf/Documentation/perf-config.txt +++ b/tools/perf/Documentation/perf-config.txt @@ -250,7 +250,10 @@ annotate.*:: These are in control of addresses, jump function, source code in lines of assembly code from a specific program. - annotate.disassembler_style: + annotate.objdump:: + objdump binary to use for disassembly and annotations. + + annotate.disassembler_style:: Use this to change the default disassembler style to some other value supported by binutils, such as "intel", see the '-M' option help in the 'objdump' man page. diff --git a/tools/perf/util/annotate.c b/tools/perf/util/annotate.c index 08e041a9b9cc..317c987d3001 100644 --- a/tools/perf/util/annotate.c +++ b/tools/perf/util/annotate.c @@ -3211,6 +3211,12 @@ static int annotation__config(const char *var, const char *value, void *data) pr_err("Not enough memory for annotate.disassembler_style\n"); return -1; } + } else if (!strcmp(var, "annotate.objdump")) { + opt->objdump_path = strdup(value); + if (!opt->objdump_path) { + pr_err("Not enough memory for annotate.objdump\n"); + return -1; + } } else if (!strcmp(var, "annotate.demangle")) { symbol_conf.demangle = perf_config_bool("demangle", value); } else if (!strcmp(var, "annotate.demangle_kernel")) { -- cgit v1.2.3-58-ga151 From 57594454ceb92defaa0707cf29289f0c3c266ede Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Tue, 28 Mar 2023 16:55:43 -0700 Subject: perf symbol: Add command line support for addr2line path Allow addr2line to be set either on the command line or via the perfconfig file. This doesn't currently work with llvm-addr2line as the addr2line code emits two things: 1) the address to decode, 2) a bogus ',' value. The expectation is the bogus value will generate: ?? ??:0 that terminates the addr2line reading. However, the output from llvm-addr2line is a single line with just the input ',' locking up the addr2line reading that is expecting a second line. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: Andres Freund Cc: German Gomez Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Peter Zijlstra Cc: Sandipan Das Cc: Tom Rix Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20230328235543.1082207-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Documentation/perf-annotate.txt | 3 +++ tools/perf/Documentation/perf-config.txt | 3 +++ tools/perf/Documentation/perf-report.txt | 3 +++ tools/perf/Documentation/perf-top.txt | 6 ++++++ tools/perf/builtin-annotate.c | 9 ++++++++- tools/perf/builtin-report.c | 9 ++++++++- tools/perf/builtin-top.c | 10 ++++++++-- tools/perf/util/annotate.c | 6 ++++++ tools/perf/util/srcline.c | 26 ++++++++++++++++---------- tools/perf/util/symbol_conf.h | 1 + 10 files changed, 62 insertions(+), 14 deletions(-) (limited to 'tools') diff --git a/tools/perf/Documentation/perf-annotate.txt b/tools/perf/Documentation/perf-annotate.txt index 980fe2c29275..fe168e8165c8 100644 --- a/tools/perf/Documentation/perf-annotate.txt +++ b/tools/perf/Documentation/perf-annotate.txt @@ -116,6 +116,9 @@ include::itrace.txt[] -M:: --disassembler-style=:: Set disassembler style for objdump. +--addr2line=:: + Path to addr2line binary. + --objdump=:: Path to objdump binary. diff --git a/tools/perf/Documentation/perf-config.txt b/tools/perf/Documentation/perf-config.txt index 697f7f924545..e56ae54805a8 100644 --- a/tools/perf/Documentation/perf-config.txt +++ b/tools/perf/Documentation/perf-config.txt @@ -250,6 +250,9 @@ annotate.*:: These are in control of addresses, jump function, source code in lines of assembly code from a specific program. + annotate.addr2line:: + addr2line binary to use for file names and line numbers. + annotate.objdump:: objdump binary to use for disassembly and annotations. diff --git a/tools/perf/Documentation/perf-report.txt b/tools/perf/Documentation/perf-report.txt index cfd502f7e6da..af068b4f1e5a 100644 --- a/tools/perf/Documentation/perf-report.txt +++ b/tools/perf/Documentation/perf-report.txt @@ -381,6 +381,9 @@ OPTIONS This allows to examine the path the program took to each sample. The data collection must have used -b (or -j) and -g. +--addr2line=:: + Path to addr2line binary. + --objdump=:: Path to objdump binary. diff --git a/tools/perf/Documentation/perf-top.txt b/tools/perf/Documentation/perf-top.txt index c60e615b7183..619cc8143ad5 100644 --- a/tools/perf/Documentation/perf-top.txt +++ b/tools/perf/Documentation/perf-top.txt @@ -161,6 +161,12 @@ Default is to monitor all CPUS. -M:: --disassembler-style=:: Set disassembler style for objdump. +--addr2line=:: + Path to addr2line binary. + +--objdump=:: + Path to objdump binary. + --prefix=PREFIX:: --prefix-strip=N:: Remove first N entries from source file path names in executables diff --git a/tools/perf/builtin-annotate.c b/tools/perf/builtin-annotate.c index 5b31c4ee8d06..655987afef58 100644 --- a/tools/perf/builtin-annotate.c +++ b/tools/perf/builtin-annotate.c @@ -517,7 +517,7 @@ int cmd_annotate(int argc, const char **argv) struct itrace_synth_opts itrace_synth_opts = { .set = 0, }; - const char *disassembler_style = NULL, *objdump_path = NULL; + const char *disassembler_style = NULL, *objdump_path = NULL, *addr2line_path = NULL; struct option options[] = { OPT_STRING('i', "input", &input_name, "file", "input file name"), @@ -570,6 +570,8 @@ int cmd_annotate(int argc, const char **argv) "Strip first N entries of source file path name in programs (with --prefix)"), OPT_STRING(0, "objdump", &objdump_path, "path", "objdump binary to use for disassembly and annotations"), + OPT_STRING(0, "addr2line", &addr2line_path, "path", + "addr2line binary to use for line numbers"), OPT_BOOLEAN(0, "demangle", &symbol_conf.demangle, "Enable symbol demangling"), OPT_BOOLEAN(0, "demangle-kernel", &symbol_conf.demangle_kernel, @@ -629,6 +631,11 @@ int cmd_annotate(int argc, const char **argv) if (!annotate.opts.objdump_path) return -ENOMEM; } + if (addr2line_path) { + symbol_conf.addr2line_path = strdup(addr2line_path); + if (!symbol_conf.addr2line_path) + return -ENOMEM; + } if (annotate_check_args(&annotate.opts) < 0) return -EINVAL; diff --git a/tools/perf/builtin-report.c b/tools/perf/builtin-report.c index 15b0cf649e1a..4011abc03d0d 100644 --- a/tools/perf/builtin-report.c +++ b/tools/perf/builtin-report.c @@ -1226,7 +1226,7 @@ int cmd_report(int argc, const char **argv) }; char *sort_order_help = sort_help("sort by key(s):"); char *field_order_help = sort_help("output field(s): overhead period sample "); - const char *disassembler_style = NULL, *objdump_path = NULL; + const char *disassembler_style = NULL, *objdump_path = NULL, *addr2line_path = NULL; const struct option options[] = { OPT_STRING('i', "input", &input_name, "file", "input file name"), @@ -1344,6 +1344,8 @@ int cmd_report(int argc, const char **argv) "add last branch records to call history"), OPT_STRING(0, "objdump", &objdump_path, "path", "objdump binary to use for disassembly and annotations"), + OPT_STRING(0, "addr2line", &addr2line_path, "path", + "addr2line binary to use for line numbers"), OPT_BOOLEAN(0, "demangle", &symbol_conf.demangle, "Disable symbol demangling"), OPT_BOOLEAN(0, "demangle-kernel", &symbol_conf.demangle_kernel, @@ -1430,6 +1432,11 @@ int cmd_report(int argc, const char **argv) if (!report.annotation_opts.objdump_path) return -ENOMEM; } + if (addr2line_path) { + symbol_conf.addr2line_path = strdup(addr2line_path); + if (!symbol_conf.addr2line_path) + return -ENOMEM; + } if (annotate_check_args(&report.annotation_opts) < 0) { ret = -EINVAL; diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c index 57a273cd03de..82c6c065830d 100644 --- a/tools/perf/builtin-top.c +++ b/tools/perf/builtin-top.c @@ -1439,7 +1439,7 @@ int cmd_top(int argc, const char **argv) }; struct record_opts *opts = &top.record_opts; struct target *target = &opts->target; - const char *disassembler_style = NULL, *objdump_path = NULL; + const char *disassembler_style = NULL, *objdump_path = NULL, *addr2line_path = NULL; const struct option options[] = { OPT_CALLBACK('e', "event", &top.evlist, "event", "event selector. use 'perf list' to list available events", @@ -1527,6 +1527,8 @@ int cmd_top(int argc, const char **argv) OPT_BOOLEAN(0, "no-bpf-event", &top.record_opts.no_bpf_event, "do not record bpf events"), OPT_STRING(0, "objdump", &objdump_path, "path", "objdump binary to use for disassembly and annotations"), + OPT_STRING(0, "addr2line", &addr2line_path, "path", + "addr2line binary to use for line numbers"), OPT_STRING('M', "disassembler-style", &disassembler_style, "disassembler style", "Specify disassembler style (e.g. -M intel for intel syntax)"), OPT_STRING(0, "prefix", &top.annotation_opts.prefix, "prefix", @@ -1629,7 +1631,11 @@ int cmd_top(int argc, const char **argv) if (!top.annotation_opts.objdump_path) return -ENOMEM; } - + if (addr2line_path) { + symbol_conf.addr2line_path = strdup(addr2line_path); + if (!symbol_conf.addr2line_path) + return -ENOMEM; + } status = symbol__validate_sym_arguments(); if (status) diff --git a/tools/perf/util/annotate.c b/tools/perf/util/annotate.c index 317c987d3001..f47b5dde66bc 100644 --- a/tools/perf/util/annotate.c +++ b/tools/perf/util/annotate.c @@ -3217,6 +3217,12 @@ static int annotation__config(const char *var, const char *value, void *data) pr_err("Not enough memory for annotate.objdump\n"); return -1; } + } else if (!strcmp(var, "annotate.addr2line")) { + symbol_conf.addr2line_path = strdup(value); + if (!symbol_conf.addr2line_path) { + pr_err("Not enough memory for annotate.addr2line\n"); + return -1; + } } else if (!strcmp(var, "annotate.demangle")) { symbol_conf.demangle = perf_config_bool("demangle", value); } else if (!strcmp(var, "annotate.demangle_kernel")) { diff --git a/tools/perf/util/srcline.c b/tools/perf/util/srcline.c index 33321867416b..f0a96a834e4b 100644 --- a/tools/perf/util/srcline.c +++ b/tools/perf/util/srcline.c @@ -414,9 +414,14 @@ static void addr2line_subprocess_cleanup(struct a2l_subprocess *a2l) free(a2l); } -static struct a2l_subprocess *addr2line_subprocess_init(const char *path) -{ - const char *argv[] = { "addr2line", "-e", path, "-i", "-f", NULL }; +static struct a2l_subprocess *addr2line_subprocess_init(const char *addr2line_path, + const char *binary_path) +{ + const char *argv[] = { + addr2line_path ?: "addr2line", + "-e", binary_path, + "-i", "-f", NULL + }; struct a2l_subprocess *a2l = zalloc(sizeof(*a2l)); int start_command_status = 0; @@ -436,21 +441,22 @@ static struct a2l_subprocess *addr2line_subprocess_init(const char *path) a2l->addr2line.argv = NULL; /* it's not used after start_command; avoid dangling pointers */ if (start_command_status != 0) { - pr_warning("could not start addr2line for %s: start_command return code %d\n", - path, - start_command_status); + pr_warning("could not start addr2line (%s) for %s: start_command return code %d\n", + addr2line_path, binary_path, start_command_status); goto out; } a2l->to_child = fdopen(a2l->addr2line.in, "w"); if (a2l->to_child == NULL) { - pr_warning("could not open write-stream to addr2line of %s\n", path); + pr_warning("could not open write-stream to addr2line (%s) of %s\n", + addr2line_path, binary_path); goto out; } a2l->from_child = fdopen(a2l->addr2line.out, "r"); if (a2l->from_child == NULL) { - pr_warning("could not open read-stream from addr2line of %s\n", path); + pr_warning("could not open read-stream from addr2line (%s) of %s\n", + addr2line_path, binary_path); goto out; } @@ -490,7 +496,6 @@ static int read_addr2line_record(struct a2l_subprocess *a2l, if (getline(&line, &line_len, a2l->from_child) < 0 || !line_len) goto error; - if (function != NULL) *function = strdup(strim(line)); @@ -553,7 +558,8 @@ static int addr2line(const char *dso_name, u64 addr, if (!filename__has_section(dso_name, ".debug_line")) goto out; - dso->a2l = addr2line_subprocess_init(dso_name); + dso->a2l = addr2line_subprocess_init(symbol_conf.addr2line_path, + dso_name); a2l = dso->a2l; } diff --git a/tools/perf/util/symbol_conf.h b/tools/perf/util/symbol_conf.h index bc3d046fbb63..5accd8e69ad2 100644 --- a/tools/perf/util/symbol_conf.h +++ b/tools/perf/util/symbol_conf.h @@ -61,6 +61,7 @@ struct symbol_conf { *sym_list_str, *col_width_list_str, *bt_stop_list_str; + char *addr2line_path; unsigned long time_quantum; struct strlist *dso_list, *comm_list, -- cgit v1.2.3-58-ga151 From 0372358a094011663e86f695e81be3b96a93b468 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Wed, 29 Mar 2023 09:23:18 -0700 Subject: perf vendor events: Update Alderlake for E-Core TMA v2.3 https://github.com/intel/perfmon/pull/65 Generated by: https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py The PR notes state: - E-Core TMA version 2.3. - FP_UOPS changed to FPDIV_Uops - Added BR_MISP breakdown stats - Frontend_Bandwidth/Latency changed to Fetch_Bandwidth/Latency - Load_Store_Bound changed to Memory_Bound - Icache changed to ICache_Misses - ITLB changed to ITLB_Misses - Store_Fwd changed to Store_Fwd_Blk Reviewed-by: Kan Liang Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230329162318.1227114-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/alderlake/adl-metrics.json | 132 ++++++++++++--------- .../arch/x86/alderlaken/adln-metrics.json | 120 +++++++++++-------- 2 files changed, 148 insertions(+), 104 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json b/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json index 7bb8410a2bf9..75d80e70e5cd 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json @@ -169,7 +169,7 @@ { "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend", "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_DETECT / tma_info_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_latency_group", + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", "MetricName": "tma_branch_detect", "MetricThreshold": "tma_branch_detect > 0.05", "PublicDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", @@ -188,7 +188,7 @@ { "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_RESTEER / tma_info_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_latency_group", + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", "MetricName": "tma_branch_resteer", "MetricThreshold": "tma_branch_resteer > 0.05", "ScaleUnit": "100%", @@ -197,7 +197,7 @@ { "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS).", "MetricExpr": "TOPDOWN_FE_BOUND.CISC / tma_info_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_bandwidth_group", + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", "MetricName": "tma_cisc", "MetricThreshold": "tma_cisc > 0.05", "ScaleUnit": "100%", @@ -205,7 +205,7 @@ }, { "BriefDescription": "Counts the number of cycles due to backend bound stalls that are core execution bound and not attributed to outstanding demand load or store stalls.", - "MetricExpr": "max(0, tma_backend_bound - tma_load_store_bound)", + "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)", "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1", @@ -215,7 +215,7 @@ { "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to decode stalls.", "MetricExpr": "TOPDOWN_FE_BOUND.DECODE / tma_info_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_bandwidth_group", + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", "MetricName": "tma_decode", "MetricThreshold": "tma_decode > 0.05", "ScaleUnit": "100%", @@ -234,7 +234,7 @@ "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / tma_info_clks - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD", - "MetricGroup": "TopdownL3;tma_L3_group;tma_load_store_bound_group", + "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_dram_bound", "MetricThreshold": "tma_dram_bound > 0.1", "ScaleUnit": "100%", @@ -249,6 +249,24 @@ "ScaleUnit": "100%", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", + "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / tma_info_slots", + "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_bandwidth", + "MetricThreshold": "tma_fetch_bandwidth > 0.1", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", + "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY / tma_info_slots", + "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_latency", + "MetricThreshold": "tma_fetch_latency > 0.15", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, { "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to FP assists.", "MetricExpr": "tma_nuke * (MACHINE_CLEARS.FP_ASSIST / MACHINE_CLEARS.SLOW)", @@ -259,20 +277,11 @@ "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of floating point operations per uop with all default weighting.", + "BriefDescription": "Counts the number of floating point divide operations per uop.", "MetricExpr": "UOPS_RETIRED.FPDIV / tma_info_slots", "MetricGroup": "TopdownL3;tma_L3_group;tma_base_group", - "MetricName": "tma_fp_uops", - "MetricThreshold": "tma_fp_uops > 0.2", - "ScaleUnit": "100%", - "Unit": "cpu_atom" - }, - { - "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", - "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / tma_info_slots", - "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_frontend_bandwidth", - "MetricThreshold": "tma_frontend_bandwidth > 0.1", + "MetricName": "tma_fpdiv_uops", + "MetricThreshold": "tma_fpdiv_uops > 0.2", "ScaleUnit": "100%", "Unit": "cpu_atom" }, @@ -285,21 +294,12 @@ "ScaleUnit": "100%", "Unit": "cpu_atom" }, - { - "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", - "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY / tma_info_slots", - "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_frontend_latency", - "MetricThreshold": "tma_frontend_latency > 0.15", - "ScaleUnit": "100%", - "Unit": "cpu_atom" - }, { "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses.", "MetricExpr": "TOPDOWN_FE_BOUND.ICACHE / tma_info_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_latency_group", - "MetricName": "tma_icache", - "MetricThreshold": "tma_icache > 0.05", + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_icache_misses", + "MetricThreshold": "tma_icache_misses > 0.05", "ScaleUnit": "100%", "Unit": "cpu_atom" }, @@ -443,7 +443,31 @@ "Unit": "cpu_atom" }, { - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction", + "BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was not taken", + "MetricExpr": "INST_RETIRED.ANY / (BR_MISP_RETIRED.COND - BR_MISP_RETIRED.COND_TAKEN)", + "MetricName": "tma_info_ipmisp_cond_ntaken", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was taken", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN", + "MetricName": "tma_info_ipmisp_cond_taken", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Instructions per retired indirect call or jump Branch Misprediction", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT", + "MetricName": "tma_info_ipmisp_indirect", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Instructions per retired return Branch Misprediction", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RETURN", + "MetricName": "tma_info_ipmisp_ret", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Instructions per retired Branch Misprediction", "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", "MetricGroup": " ", "MetricName": "tma_info_ipmispredict", @@ -520,16 +544,16 @@ { "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", "MetricExpr": "TOPDOWN_FE_BOUND.ITLB / tma_info_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_latency_group", - "MetricName": "tma_itlb", - "MetricThreshold": "tma_itlb > 0.05", + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a load block.", "MetricExpr": "LD_HEAD.L1_BOUND_AT_RET / tma_info_clks", - "MetricGroup": "TopdownL3;tma_L3_group;tma_load_store_bound_group", + "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l1_bound", "MetricThreshold": "tma_l1_bound > 0.1", "ScaleUnit": "100%", @@ -539,7 +563,7 @@ "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 Cache.", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / tma_info_clks - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD", - "MetricGroup": "TopdownL3;tma_L3_group;tma_load_store_bound_group", + "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "MetricThreshold": "tma_l2_bound > 0.1", "ScaleUnit": "100%", @@ -548,7 +572,7 @@ { "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / tma_info_clks - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD", - "MetricGroup": "TopdownL3;tma_L3_group;tma_load_store_bound_group", + "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l3_bound", "MetricThreshold": "tma_l3_bound > 0.1", "ScaleUnit": "100%", @@ -563,15 +587,6 @@ "ScaleUnit": "100%", "Unit": "cpu_atom" }, - { - "BriefDescription": "Counts the number of cycles the core is stalled due to stores or loads.", - "MetricExpr": "min(tma_backend_bound, LD_HEAD.ANY_AT_RET / tma_info_clks + tma_store_bound)", - "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_load_store_bound", - "MetricThreshold": "tma_load_store_bound > 0.2", - "ScaleUnit": "100%", - "Unit": "cpu_atom" - }, { "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", "MetricExpr": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS / tma_info_slots", @@ -590,6 +605,15 @@ "ScaleUnit": "100%", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to stores or loads.", + "MetricExpr": "min(tma_backend_bound, LD_HEAD.ANY_AT_RET / tma_info_clks + tma_store_bound)", + "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_memory_bound", + "MetricThreshold": "tma_memory_bound > 0.2", + "ScaleUnit": "100%", + "Unit": "cpu_atom" + }, { "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to memory ordering.", "MetricExpr": "tma_nuke * (MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.SLOW)", @@ -630,7 +654,7 @@ { "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized.", "MetricExpr": "TOPDOWN_FE_BOUND.OTHER / tma_info_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_bandwidth_group", + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", "MetricName": "tma_other_fb", "MetricThreshold": "tma_other_fb > 0.05", "ScaleUnit": "100%", @@ -647,8 +671,8 @@ }, { "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hits in the L2, LLC, DRAM or MMIO (Non-DRAM) but could not be correctly attributed or cycles in which the load miss is waiting on a request buffer.", - "MetricExpr": "max(0, tma_load_store_bound - (tma_store_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound))", - "MetricGroup": "TopdownL3;tma_L3_group;tma_load_store_bound_group", + "MetricExpr": "max(0, tma_memory_bound - (tma_store_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound))", + "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_other_load_store", "MetricThreshold": "tma_other_load_store > 0.1", "ScaleUnit": "100%", @@ -675,7 +699,7 @@ { "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes.", "MetricExpr": "TOPDOWN_FE_BOUND.PREDECODE / tma_info_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_bandwidth_group", + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", "MetricName": "tma_predecode", "MetricThreshold": "tma_predecode > 0.05", "ScaleUnit": "100%", @@ -775,7 +799,7 @@ { "BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full.", "MetricExpr": "tma_mem_scheduler * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_BLOCK.ALL)", - "MetricGroup": "TopdownL3;tma_L3_group;tma_load_store_bound_group", + "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_store_bound", "MetricThreshold": "tma_store_bound > 0.1", "ScaleUnit": "100%", @@ -785,8 +809,8 @@ "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a store forward block.", "MetricExpr": "LD_HEAD.ST_ADDR_AT_RET / tma_info_clks", "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_store_fwd", - "MetricThreshold": "tma_store_fwd > 0.05", + "MetricName": "tma_store_fwd_blk", + "MetricThreshold": "tma_store_fwd_blk > 0.05", "ScaleUnit": "100%", "Unit": "cpu_atom" }, @@ -2084,7 +2108,7 @@ }, { "BriefDescription": "This metric represents fraction of slots the Memory subsystem within the Backend was a bottleneck", - "MetricExpr": "topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_slots", + "MetricExpr": "min(tma_backend_bound, LD_HEAD.ANY_AT_RET / tma_info_clks + tma_store_bound)", "MetricGroup": "Backend;TmaL2;TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_memory_bound", "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0.2", diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json b/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json index 5078c468480f..1a85d935c733 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json @@ -130,7 +130,7 @@ { "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend", "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_DETECT / tma_info_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_latency_group", + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", "MetricName": "tma_branch_detect", "MetricThreshold": "tma_branch_detect > 0.05", "PublicDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", @@ -147,7 +147,7 @@ { "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_RESTEER / tma_info_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_latency_group", + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", "MetricName": "tma_branch_resteer", "MetricThreshold": "tma_branch_resteer > 0.05", "ScaleUnit": "100%" @@ -155,14 +155,14 @@ { "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS).", "MetricExpr": "TOPDOWN_FE_BOUND.CISC / tma_info_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_bandwidth_group", + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", "MetricName": "tma_cisc", "MetricThreshold": "tma_cisc > 0.05", "ScaleUnit": "100%" }, { "BriefDescription": "Counts the number of cycles due to backend bound stalls that are core execution bound and not attributed to outstanding demand load or store stalls.", - "MetricExpr": "max(0, tma_backend_bound - tma_load_store_bound)", + "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)", "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_core_bound", "MetricThreshold": "tma_core_bound > 0.1", @@ -171,7 +171,7 @@ { "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to decode stalls.", "MetricExpr": "TOPDOWN_FE_BOUND.DECODE / tma_info_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_bandwidth_group", + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", "MetricName": "tma_decode", "MetricThreshold": "tma_decode > 0.05", "ScaleUnit": "100%" @@ -188,7 +188,7 @@ "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / tma_info_clks - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD", - "MetricGroup": "TopdownL3;tma_L3_group;tma_load_store_bound_group", + "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_dram_bound", "MetricThreshold": "tma_dram_bound > 0.1", "ScaleUnit": "100%" @@ -201,6 +201,22 @@ "MetricThreshold": "tma_fast_nuke > 0.05", "ScaleUnit": "100%" }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", + "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / tma_info_slots", + "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_bandwidth", + "MetricThreshold": "tma_fetch_bandwidth > 0.1", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", + "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY / tma_info_slots", + "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_fetch_latency", + "MetricThreshold": "tma_fetch_latency > 0.15", + "ScaleUnit": "100%" + }, { "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to FP assists.", "MetricExpr": "tma_nuke * (MACHINE_CLEARS.FP_ASSIST / MACHINE_CLEARS.SLOW)", @@ -210,19 +226,11 @@ "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of floating point operations per uop with all default weighting.", + "BriefDescription": "Counts the number of floating point divide operations per uop.", "MetricExpr": "UOPS_RETIRED.FPDIV / tma_info_slots", "MetricGroup": "TopdownL3;tma_L3_group;tma_base_group", - "MetricName": "tma_fp_uops", - "MetricThreshold": "tma_fp_uops > 0.2", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", - "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / tma_info_slots", - "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_frontend_bandwidth", - "MetricThreshold": "tma_frontend_bandwidth > 0.1", + "MetricName": "tma_fpdiv_uops", + "MetricThreshold": "tma_fpdiv_uops > 0.2", "ScaleUnit": "100%" }, { @@ -233,20 +241,12 @@ "MetricThreshold": "tma_frontend_bound > 0.2", "ScaleUnit": "100%" }, - { - "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", - "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY / tma_info_slots", - "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_frontend_latency", - "MetricThreshold": "tma_frontend_latency > 0.15", - "ScaleUnit": "100%" - }, { "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses.", "MetricExpr": "TOPDOWN_FE_BOUND.ICACHE / tma_info_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_latency_group", - "MetricName": "tma_icache", - "MetricThreshold": "tma_icache > 0.05", + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_icache_misses", + "MetricThreshold": "tma_icache_misses > 0.05", "ScaleUnit": "100%" }, { @@ -369,7 +369,27 @@ "MetricName": "tma_info_ipload" }, { - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction", + "BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was not taken", + "MetricExpr": "INST_RETIRED.ANY / (BR_MISP_RETIRED.COND - BR_MISP_RETIRED.COND_TAKEN)", + "MetricName": "tma_info_ipmisp_cond_ntaken" + }, + { + "BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was taken", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN", + "MetricName": "tma_info_ipmisp_cond_taken" + }, + { + "BriefDescription": "Instructions per retired indirect call or jump Branch Misprediction", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT", + "MetricName": "tma_info_ipmisp_indirect" + }, + { + "BriefDescription": "Instructions per retired return Branch Misprediction", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RETURN", + "MetricName": "tma_info_ipmisp_ret" + }, + { + "BriefDescription": "Instructions per retired Branch Misprediction", "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", "MetricGroup": " ", "MetricName": "tma_info_ipmispredict" @@ -435,15 +455,15 @@ { "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", "MetricExpr": "TOPDOWN_FE_BOUND.ITLB / tma_info_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_latency_group", - "MetricName": "tma_itlb", - "MetricThreshold": "tma_itlb > 0.05", + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05", "ScaleUnit": "100%" }, { "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a load block.", "MetricExpr": "LD_HEAD.L1_BOUND_AT_RET / tma_info_clks", - "MetricGroup": "TopdownL3;tma_L3_group;tma_load_store_bound_group", + "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l1_bound", "MetricThreshold": "tma_l1_bound > 0.1", "ScaleUnit": "100%" @@ -452,7 +472,7 @@ "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 Cache.", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / tma_info_clks - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD", - "MetricGroup": "TopdownL3;tma_L3_group;tma_load_store_bound_group", + "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "MetricThreshold": "tma_l2_bound > 0.1", "ScaleUnit": "100%" @@ -460,7 +480,7 @@ { "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / tma_info_clks - MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD", - "MetricGroup": "TopdownL3;tma_L3_group;tma_load_store_bound_group", + "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_l3_bound", "MetricThreshold": "tma_l3_bound > 0.1", "ScaleUnit": "100%" @@ -473,14 +493,6 @@ "MetricThreshold": "tma_ld_buffer > 0.05", "ScaleUnit": "100%" }, - { - "BriefDescription": "Counts the number of cycles the core is stalled due to stores or loads.", - "MetricExpr": "min(tma_backend_bound, LD_HEAD.ANY_AT_RET / tma_info_clks + tma_store_bound)", - "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_load_store_bound", - "MetricThreshold": "tma_load_store_bound > 0.2", - "ScaleUnit": "100%" - }, { "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", "MetricExpr": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS / tma_info_slots", @@ -497,6 +509,14 @@ "MetricThreshold": "tma_mem_scheduler > 0.1", "ScaleUnit": "100%" }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to stores or loads.", + "MetricExpr": "min(tma_backend_bound, LD_HEAD.ANY_AT_RET / tma_info_clks + tma_store_bound)", + "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_memory_bound", + "MetricThreshold": "tma_memory_bound > 0.2", + "ScaleUnit": "100%" + }, { "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to memory ordering.", "MetricExpr": "tma_nuke * (MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.SLOW)", @@ -533,7 +553,7 @@ { "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized.", "MetricExpr": "TOPDOWN_FE_BOUND.OTHER / tma_info_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_bandwidth_group", + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", "MetricName": "tma_other_fb", "MetricThreshold": "tma_other_fb > 0.05", "ScaleUnit": "100%" @@ -548,8 +568,8 @@ }, { "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hits in the L2, LLC, DRAM or MMIO (Non-DRAM) but could not be correctly attributed or cycles in which the load miss is waiting on a request buffer.", - "MetricExpr": "max(0, tma_load_store_bound - (tma_store_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound))", - "MetricGroup": "TopdownL3;tma_L3_group;tma_load_store_bound_group", + "MetricExpr": "max(0, tma_memory_bound - (tma_store_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound))", + "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_other_load_store", "MetricThreshold": "tma_other_load_store > 0.1", "ScaleUnit": "100%" @@ -573,7 +593,7 @@ { "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes.", "MetricExpr": "TOPDOWN_FE_BOUND.PREDECODE / tma_info_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_frontend_bandwidth_group", + "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", "MetricName": "tma_predecode", "MetricThreshold": "tma_predecode > 0.05", "ScaleUnit": "100%" @@ -662,7 +682,7 @@ { "BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full.", "MetricExpr": "tma_mem_scheduler * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_BLOCK.ALL)", - "MetricGroup": "TopdownL3;tma_L3_group;tma_load_store_bound_group", + "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", "MetricName": "tma_store_bound", "MetricThreshold": "tma_store_bound > 0.1", "ScaleUnit": "100%" @@ -671,8 +691,8 @@ "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a store forward block.", "MetricExpr": "LD_HEAD.ST_ADDR_AT_RET / tma_info_clks", "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_store_fwd", - "MetricThreshold": "tma_store_fwd > 0.05", + "MetricName": "tma_store_fwd_blk", + "MetricThreshold": "tma_store_fwd_blk > 0.05", "ScaleUnit": "100%" } ] -- cgit v1.2.3-58-ga151 From d1babea9c38282b58a6f822ab95027cba3165a42 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 30 Mar 2023 11:38:25 -0700 Subject: perf bench: Avoid NDEBUG warning With NDEBUG set the asserts are compiled out. This yields "unused-but-set-variable" variables. Move these variables behind NDEBUG to avoid the warning. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Paolo Bonzini Cc: Peter Zijlstra Cc: Sean Christopherson Link: https://lore.kernel.org/r/20230330183827.1412303-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/bench/find-bit-bench.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/bench/find-bit-bench.c b/tools/perf/bench/find-bit-bench.c index d103c3136983..7e25b0e413f6 100644 --- a/tools/perf/bench/find-bit-bench.c +++ b/tools/perf/bench/find-bit-bench.c @@ -61,7 +61,6 @@ static int do_for_each_set_bit(unsigned int num_bits) double time_average, time_stddev; unsigned int bit, i, j; unsigned int set_bits, skip; - unsigned int old; init_stats(&fb_time_stats); init_stats(&tb_time_stats); @@ -73,7 +72,10 @@ static int do_for_each_set_bit(unsigned int num_bits) __set_bit(i, to_test); for (i = 0; i < outer_iterations; i++) { - old = accumulator; +#ifndef NDEBUG + unsigned int old = accumulator; +#endif + gettimeofday(&start, NULL); for (j = 0; j < inner_iterations; j++) { for_each_set_bit(bit, to_test, num_bits) @@ -85,7 +87,9 @@ static int do_for_each_set_bit(unsigned int num_bits) runtime_us = diff.tv_sec * USEC_PER_SEC + diff.tv_usec; update_stats(&fb_time_stats, runtime_us); +#ifndef NDEBUG old = accumulator; +#endif gettimeofday(&start, NULL); for (j = 0; j < inner_iterations; j++) { for (bit = 0; bit < num_bits; bit++) { -- cgit v1.2.3-58-ga151 From 984a785f25e5b5db5fa673130b60dca6ca794406 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 30 Mar 2023 11:38:26 -0700 Subject: perf block-range: Move debug code behind ifndef NDEBUG Make good on a comment and avoid a unused-but-set-variable warning. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Paolo Bonzini Cc: Peter Zijlstra Cc: Sean Christopherson Link: https://lore.kernel.org/r/20230330183827.1412303-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/block-range.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/block-range.c b/tools/perf/util/block-range.c index 1be432657501..680e92774d0c 100644 --- a/tools/perf/util/block-range.c +++ b/tools/perf/util/block-range.c @@ -11,11 +11,7 @@ struct { static void block_range__debug(void) { - /* - * XXX still paranoid for now; see if we can make this depend on - * DEBUG=1 builds. - */ -#if 1 +#ifndef NDEBUG struct rb_node *rb; u64 old = 0; /* NULL isn't executable */ -- cgit v1.2.3-58-ga151 From 616b14b47a86d880ba21a363440f20f82152d8f2 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 30 Mar 2023 11:38:27 -0700 Subject: perf build: Conditionally define NDEBUG When a build is done without DEBUG=1 then define NDEBUG. This will compile out asserts and other debug code. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Paolo Bonzini Cc: Peter Zijlstra Cc: Sean Christopherson Link: https://lore.kernel.org/r/20230330183827.1412303-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Makefile.config | 1 + 1 file changed, 1 insertion(+) (limited to 'tools') diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index 3066d0c318c3..236d763181c5 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -228,6 +228,7 @@ ifndef DEBUG endif ifeq ($(DEBUG),0) +CORE_CFLAGS += -DNDEBUG=1 ifeq ($(CC_NO_CLANG), 0) CORE_CFLAGS += -O3 else -- cgit v1.2.3-58-ga151 From 5ef506130c739a0601d234b36f5dfd2129f966c0 Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Thu, 30 Mar 2023 16:18:32 +0300 Subject: perf top: Add --branch-history option Add --branch-history option, to act the same as that option does for perf report. Example: $ cat tcallf.c volatile a = 10000, b = 100000, c; __attribute__((noinline)) f2() { c = a / b; } __attribute__((noinline)) f1() { f2(); f2(); } main() { while (1) f1(); } $ gcc -w -g -o tcallf tcallf.c $ ./tcallf & [1] 29409 $ perf top -e cycles:u -t $(pidof tcallf) --stdio --no-children --branch-history PerfTop: 3819 irqs/sec kernel: 0.0% exact: 0.0% lost: 0/0 drop: 0/0 [4000Hz cycles:u], (target_tid: 29409) -------------------------------------------------------------------------------------------------------------------- 49.01% tcallf.c:5 [.] f2 tcallf | |--24.91%--f2 tcallf.c:4 | | | |--17.14%--f1 tcallf.c:11 (cycles:1) | | f1 tcallf.c:11 | | f2 tcallf.c:6 (cycles:3) | | f2 tcallf.c:4 | | f1 tcallf.c:10 (cycles:2) | | f1 tcallf.c:9 | | main tcallf.c:16 (cycles:1) | | main tcallf.c:16 | | main tcallf.c:16 (cycles:1) | | main tcallf.c:16 | | f1 tcallf.c:12 (cycles:1) | | f1 tcallf.c:12 | | f2 tcallf.c:6 (cycles:3) | | f2 tcallf.c:4 | | f1 tcallf.c:11 (cycles:1 iter:1 avg_cycles:12) | | f1 tcallf.c:11 | | f2 tcallf.c:6 (cycles:3 iter:1 avg_cycles:12) | | f2 tcallf.c:4 | | f1 tcallf.c:10 (cycles:2 iter:1 avg_cycles:12) | | | --7.78%--f1 tcallf.c:10 (cycles:2) | f1 tcallf.c:9 | main tcallf.c:16 (cycles:1) | main tcallf.c:16 | main tcallf.c:16 (cycles:1) | main tcallf.c:16 | f1 tcallf.c:12 (cycles:1) | f1 tcallf.c:12 | f2 tcallf.c:6 (cycles:3) | f2 tcallf.c:4 | f1 tcallf.c:11 (cycles:1) | f1 tcallf.c:11 | f2 tcallf.c:6 (cycles:3) | f2 tcallf.c:4 | f1 tcallf.c:10 (cycles:2 iter:1 avg_cycles:12) | f1 tcallf.c:9 | main tcallf.c:16 (cycles:1 iter:1 avg_cycles:12) | main tcallf.c:16 | main tcallf.c:16 (cycles:1 iter:1 avg_cycles:12) ... $ pkill tcallf [1]+ Terminated ./tcallf Signed-off-by: Adrian Hunter Cc: Andi Kleen Cc: Ian Rogers Cc: Jiri Olsa Cc: Namhyung Kim Link: https://lore.kernel.org/r/20230330131833.12864-2-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Documentation/perf-top.txt | 4 ++++ tools/perf/builtin-top.c | 17 +++++++++++++++++ 2 files changed, 21 insertions(+) (limited to 'tools') diff --git a/tools/perf/Documentation/perf-top.txt b/tools/perf/Documentation/perf-top.txt index 619cc8143ad5..3c202ec080ba 100644 --- a/tools/perf/Documentation/perf-top.txt +++ b/tools/perf/Documentation/perf-top.txt @@ -254,6 +254,10 @@ Default is to monitor all CPUS. The various filters must be specified as a comma separated list: --branch-filter any_ret,u,k Note that this feature may not be available on all processors. +--branch-history:: + Add the addresses of sampled taken branches to the callstack. + This allows to examine the path the program took to each sample. + --raw-trace:: When displaying traceevent output, do not use print fmt or plugins. diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c index 82c6c065830d..2c985cfea517 100644 --- a/tools/perf/builtin-top.c +++ b/tools/perf/builtin-top.c @@ -1437,6 +1437,7 @@ int cmd_top(int argc, const char **argv) .max_stack = sysctl__max_stack(), .nr_threads_synthesize = UINT_MAX, }; + bool branch_call_mode = false; struct record_opts *opts = &top.record_opts; struct target *target = &opts->target; const char *disassembler_style = NULL, *objdump_path = NULL, *addr2line_path = NULL; @@ -1551,6 +1552,8 @@ int cmd_top(int argc, const char **argv) OPT_CALLBACK('j', "branch-filter", &opts->branch_stack, "branch filter mask", "branch stack filter modes", parse_branch_stack), + OPT_BOOLEAN(0, "branch-history", &branch_call_mode, + "add last branch records to call history"), OPT_BOOLEAN(0, "raw-trace", &symbol_conf.raw_trace, "Show raw trace event output (do not use print fmt or plugins)"), OPT_BOOLEAN(0, "hierarchy", &symbol_conf.report_hierarchy, @@ -1677,6 +1680,20 @@ int cmd_top(int argc, const char **argv) goto out_delete_evlist; } + if (branch_call_mode) { + if (!opts->branch_stack) + opts->branch_stack = PERF_SAMPLE_BRANCH_ANY; + symbol_conf.use_callchain = true; + callchain_param.key = CCKEY_ADDRESS; + callchain_param.branch_callstack = true; + callchain_param.enabled = true; + if (callchain_param.record_mode == CALLCHAIN_NONE) + callchain_param.record_mode = CALLCHAIN_FP; + callchain_register_param(&callchain_param); + if (!sort_order) + sort_order = "srcline,symbol,dso"; + } + if (opts->branch_stack && callchain_param.enabled) symbol_conf.show_branchflag_count = true; -- cgit v1.2.3-58-ga151 From 5a892c3da39fae73d008cc43706ff29456fa8cf1 Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Thu, 30 Mar 2023 16:18:33 +0300 Subject: perf symbol: Remove unused branch_callstack branch_callstack was added by commit 8b7bad58efb7 ("perf callchain: Support handling complete branch stacks as histograms") but never used. Signed-off-by: Adrian Hunter Cc: Andi Kleen Cc: Ian Rogers Cc: Jiri Olsa Cc: Namhyung Kim Link: https://lore.kernel.org/r/20230330131833.12864-2-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/symbol_conf.h | 1 - 1 file changed, 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/symbol_conf.h b/tools/perf/util/symbol_conf.h index 5accd8e69ad2..f26f81eb8252 100644 --- a/tools/perf/util/symbol_conf.h +++ b/tools/perf/util/symbol_conf.h @@ -33,7 +33,6 @@ struct symbol_conf { demangle_kernel, filter_relative, show_hist_headers, - branch_callstack, has_filter, show_ref_callgraph, hide_unresolved, -- cgit v1.2.3-58-ga151 From 337fa2db04785c60fc3aa736af98ce8358f87d34 Mon Sep 17 00:00:00 2001 From: Andreas Herrmann Date: Thu, 30 Mar 2023 09:42:02 +0200 Subject: perf bench numa: Fix type of loop iterator in do_work, it should be 'long' 'j' is of type int and start/end are of type 'long'. Thus 'j' might become negative and cause segfault in access_data(). Fix it by using 'long' for 'j' as well. Reviewed-by: James Clark Signed-off-by: Andreas Herrmann Link: https://lore.kernel.org/r/20230330074202.14052-1-aherrmann@suse.de Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/bench/numa.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/bench/numa.c b/tools/perf/bench/numa.c index 9717c6c17433..1fbd7c947abc 100644 --- a/tools/perf/bench/numa.c +++ b/tools/perf/bench/numa.c @@ -847,7 +847,7 @@ static u64 do_work(u8 *__data, long bytes, int nr, int nr_max, int loop, u64 val if (g->p.data_rand_walk) { u32 lfsr = nr + loop + val; - int j; + long j; for (i = 0; i < words/1024; i++) { long start, end; -- cgit v1.2.3-58-ga151 From 319593215260da74a78c7de1dccd877ea13916fb Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Tue, 28 Mar 2023 16:41:42 -0700 Subject: perf vendor events intel: Update ivybridge and ivytown Update to versions 24 and 23 respectively. Adds the event BR_MISP_EXEC.INDIRECT. Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230328234142.1080045-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json | 8 ++++++++ tools/perf/pmu-events/arch/x86/ivytown/pipeline.json | 8 ++++++++ tools/perf/pmu-events/arch/x86/mapfile.csv | 4 ++-- 3 files changed, 18 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json b/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json index d1e64e0d683e..30a3da9cd22b 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json @@ -215,6 +215,14 @@ "SampleAfterValue": "200003", "UMask": "0xc4" }, + { + "BriefDescription": "Speculative mispredicted indirect branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.INDIRECT", + "PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, { "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", "EventCode": "0x89", diff --git a/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json b/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json index d1e64e0d683e..30a3da9cd22b 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json @@ -215,6 +215,14 @@ "SampleAfterValue": "200003", "UMask": "0xc4" }, + { + "BriefDescription": "Speculative mispredicted indirect branches", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.INDIRECT", + "PublicDescription": "Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, { "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", "EventCode": "0x89", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 41d755d570e6..97b3ffc284a6 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -14,8 +14,8 @@ GenuineIntel-6-(3C|45|46),v33,haswell,core GenuineIntel-6-3F,v27,haswellx,core GenuineIntel-6-(7D|7E|A7),v1.17,icelake,core GenuineIntel-6-6[AC],v1.19,icelakex,core -GenuineIntel-6-3A,v23,ivybridge,core -GenuineIntel-6-3E,v22,ivytown,core +GenuineIntel-6-3A,v24,ivybridge,core +GenuineIntel-6-3E,v23,ivytown,core GenuineIntel-6-2D,v23,jaketown,core GenuineIntel-6-(57|85),v10,knightslanding,core GenuineIntel-6-A[AC],v1.01,meteorlake,core -- cgit v1.2.3-58-ga151 From 35bf007e2ee0447166081646c0797bfa831b062f Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Mon, 27 Mar 2023 15:57:10 -0700 Subject: perf lock contention: Fix debug stat if no contention It should not divide if the total number is 0. Otherwise it'd show NaN in the bad rate output. Also add a whitespace in the "output for debug" message. $ sudo perf lock contention -abv true Looking at the vmlinux_path (8 entries long) symsrc__init: cannot get elf header. Using /proc/kcore for kernel data Using /proc/kallsyms for symbols contended total wait max wait avg wait type caller === output for debug=== bad: 0, total: 0 bad rate: -nan % <------------------------- (here) histogram of events caused bad sequence acquire: 0 acquired: 0 contended: 0 release: 0 Signed-off-by: Namhyung Kim Cc: Adrian Hunter Cc: Hao Luo Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Peter Zijlstra Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230327225711.245738-1-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-lock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-lock.c b/tools/perf/builtin-lock.c index 3c8a19ebc496..82dd2dfe5692 100644 --- a/tools/perf/builtin-lock.c +++ b/tools/perf/builtin-lock.c @@ -1323,10 +1323,10 @@ static void print_bad_events(int bad, int total) for (i = 0; i < BROKEN_MAX; i++) broken += bad_hist[i]; - if (quiet || (broken == 0 && verbose <= 0)) + if (quiet || total == 0 || (broken == 0 && verbose <= 0)) return; - pr_info("\n=== output for debug===\n\n"); + pr_info("\n=== output for debug ===\n\n"); pr_info("bad: %d, total: %d\n", bad, total); pr_info("bad rate: %.2f %%\n", (double)bad / (double)total * 100); pr_info("histogram of events caused bad sequence\n"); -- cgit v1.2.3-58-ga151 From 84c3a2bb4c513ca9fd1326cf24d3729b769d9cf1 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Mon, 27 Mar 2023 15:57:11 -0700 Subject: perf lock contention: Show detail failure reason for BPF It can fail to collect lock stat from BPF for various reasons. For example, I've got a report that sometimes time calculation seems wrong in case of contended spinlocks. I suspect the time delta went negative for some reason. Count them separately and show in the output like below: $ sudo perf lock contention -abE5 sleep 10 contended total wait max wait avg wait type caller 13 785.61 us 79.36 us 60.43 us spinlock remove_wait_queue+0x14 10 469.02 us 87.51 us 46.90 us spinlock prepare_to_wait+0x27 9 289.09 us 69.08 us 32.12 us spinlock finish_wait+0x36 114 251.05 us 8.56 us 2.20 us spinlock try_to_wake_up+0x1f5 132 188.63 us 5.01 us 1.43 us spinlock __wake_up_common_lock+0x62 === output for debug === bad: 1, total: 279 bad rate: 0.36 % histogram of failure reasons task: 1 stack: 0 time: 0 Signed-off-by: Namhyung Kim Cc: Adrian Hunter Cc: Hao Luo Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Peter Zijlstra Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230327225711.245738-1-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-lock.c | 28 ++++++++++++++++++++------ tools/perf/util/bpf_lock_contention.c | 4 +++- tools/perf/util/bpf_skel/lock_contention.bpf.c | 13 +++++++++--- tools/perf/util/lock-contention.h | 8 +++++++- 4 files changed, 42 insertions(+), 11 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-lock.c b/tools/perf/builtin-lock.c index 82dd2dfe5692..32ec58fb80e4 100644 --- a/tools/perf/builtin-lock.c +++ b/tools/perf/builtin-lock.c @@ -1619,6 +1619,24 @@ static void sort_contention_result(void) sort_result(); } +static void print_bpf_events(int total, struct lock_contention_fails *fails) +{ + /* Output for debug, this have to be removed */ + int broken = fails->task + fails->stack + fails->time; + + if (quiet || total == 0 || (broken == 0 && verbose <= 0)) + return; + + total += broken; + pr_info("\n=== output for debug ===\n\n"); + pr_info("bad: %d, total: %d\n", broken, total); + pr_info("bad rate: %.2f %%\n", (double)broken / (double)total * 100); + + pr_info("histogram of failure reasons\n"); + pr_info(" %10s: %d\n", "task", fails->task); + pr_info(" %10s: %d\n", "stack", fails->stack); + pr_info(" %10s: %d\n", "time", fails->time); +} static void print_contention_result(struct lock_contention *con) { struct lock_stat *st; @@ -1646,8 +1664,6 @@ static void print_contention_result(struct lock_contention *con) } bad = total = printed = 0; - if (use_bpf) - bad = bad_hist[BROKEN_CONTENDED]; while ((st = pop_from_result())) { struct thread *t; @@ -1704,7 +1720,10 @@ static void print_contention_result(struct lock_contention *con) break; } - print_bad_events(bad, total); + if (use_bpf) + print_bpf_events(total, &con->fails); + else + print_bad_events(bad, total); } static bool force; @@ -1931,9 +1950,6 @@ static int __cmd_contention(int argc, const char **argv) lock_contention_stop(); lock_contention_read(&con); - - /* abuse bad hist stats for lost entries */ - bad_hist[BROKEN_CONTENDED] = con.lost; } else { err = perf_session__process_events(session); if (err) diff --git a/tools/perf/util/bpf_lock_contention.c b/tools/perf/util/bpf_lock_contention.c index 5927bf0bd92b..b3e8aa9cd011 100644 --- a/tools/perf/util/bpf_lock_contention.c +++ b/tools/perf/util/bpf_lock_contention.c @@ -259,7 +259,9 @@ int lock_contention_read(struct lock_contention *con) fd = bpf_map__fd(skel->maps.lock_stat); stack = bpf_map__fd(skel->maps.stacks); - con->lost = skel->bss->lost; + con->fails.task = skel->bss->task_fail; + con->fails.stack = skel->bss->stack_fail; + con->fails.time = skel->bss->time_fail; stack_trace = zalloc(stack_size); if (stack_trace == NULL) diff --git a/tools/perf/util/bpf_skel/lock_contention.bpf.c b/tools/perf/util/bpf_skel/lock_contention.bpf.c index ed9160999c32..3f4ee3992e81 100644 --- a/tools/perf/util/bpf_skel/lock_contention.bpf.c +++ b/tools/perf/util/bpf_skel/lock_contention.bpf.c @@ -124,7 +124,9 @@ int lock_owner; int aggr_mode; /* error stat */ -int lost; +int task_fail; +int stack_fail; +int time_fail; static inline int can_record(u64 *ctx) { @@ -283,7 +285,7 @@ int contention_begin(u64 *ctx) bpf_map_update_elem(&tstamp, &pid, &zero, BPF_ANY); pelem = bpf_map_lookup_elem(&tstamp, &pid); if (pelem == NULL) { - lost++; + __sync_fetch_and_add(&task_fail, 1); return 0; } } @@ -296,7 +298,7 @@ int contention_begin(u64 *ctx) pelem->stack_id = bpf_get_stackid(ctx, &stacks, BPF_F_FAST_STACK_CMP | stack_skip); if (pelem->stack_id < 0) - lost++; + __sync_fetch_and_add(&stack_fail, 1); } else if (aggr_mode == LOCK_AGGR_TASK) { struct task_struct *task; @@ -340,6 +342,11 @@ int contention_end(u64 *ctx) return 0; duration = bpf_ktime_get_ns() - pelem->timestamp; + if ((__s64)duration < 0) { + bpf_map_delete_elem(&tstamp, &pid); + __sync_fetch_and_add(&time_fail, 1); + return 0; + } switch (aggr_mode) { case LOCK_AGGR_CALLER: diff --git a/tools/perf/util/lock-contention.h b/tools/perf/util/lock-contention.h index 040b618b2215..10c28302420c 100644 --- a/tools/perf/util/lock-contention.h +++ b/tools/perf/util/lock-contention.h @@ -122,14 +122,20 @@ struct evlist; struct machine; struct target; +struct lock_contention_fails { + int task; + int stack; + int time; +}; + struct lock_contention { struct evlist *evlist; struct target *target; struct machine *machine; struct hlist_head *result; struct lock_filter *filters; + struct lock_contention_fails fails; unsigned long map_nr_entries; - int lost; int max_stack; int stack_skip; int aggr_mode; -- cgit v1.2.3-58-ga151 From 092772955568fa848b1e782e6cb3fa395eccea81 Mon Sep 17 00:00:00 2001 From: Mike Leach Date: Fri, 31 Mar 2023 06:56:43 +0100 Subject: perf cs-etm: Move mapping of Trace ID and cpu into helper function The information to associate Trace ID and CPU will be changing. Drivers will start outputting this as a hardware ID packet in the data file which if present will be used in preference to the AUXINFO values. To prepare for this we provide a helper functions to do the individual ID mapping, and one to extract the IDs from the completed metadata blocks. Reviewed-by: James Clark Signed-off-by: Mike Leach Acked-by: Suzuki Poulouse Cc: Alexander Shishkin Cc: Darren Hart Cc: Ganapatrao Kulkarni Cc: Ingo Molnar Cc: Jiri Olsa Cc: Leo Yan Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Will Deacon Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230331055645.26918-2-mike.leach@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/include/linux/coresight-pmu.h | 5 ++ tools/perf/util/cs-etm-base.c | 3 +- tools/perf/util/cs-etm.c | 92 ++++++++++++++++++++++++------------- tools/perf/util/cs-etm.h | 14 +++++- 4 files changed, 79 insertions(+), 35 deletions(-) (limited to 'tools') diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/coresight-pmu.h index 6c2fd6cc5a98..db9c7c0abb6a 100644 --- a/tools/include/linux/coresight-pmu.h +++ b/tools/include/linux/coresight-pmu.h @@ -7,9 +7,14 @@ #ifndef _LINUX_CORESIGHT_PMU_H #define _LINUX_CORESIGHT_PMU_H +#include + #define CORESIGHT_ETM_PMU_NAME "cs_etm" #define CORESIGHT_ETM_PMU_SEED 0x10 +/* CoreSight trace ID is currently the bottom 7 bits of the value */ +#define CORESIGHT_TRACE_ID_VAL_MASK GENMASK(6, 0) + /* * Below are the definition of bit offsets for perf option, and works as * arbitrary values for all ETM versions. diff --git a/tools/perf/util/cs-etm-base.c b/tools/perf/util/cs-etm-base.c index 5f48b756c4cf..4abe416e3feb 100644 --- a/tools/perf/util/cs-etm-base.c +++ b/tools/perf/util/cs-etm-base.c @@ -148,7 +148,8 @@ static void cs_etm__print_auxtrace_info(u64 *val, int num) for (i = CS_HEADER_VERSION_MAX; cpu < num; cpu++) { if (version == 0) err = cs_etm__print_cpu_metadata_v0(val, &i); - else if (version == 1) + /* printing same for both, but value bit flags added on v2 */ + else if ((version == 1) || (version == 2)) err = cs_etm__print_cpu_metadata_v1(val, &i); if (err) return; diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index f65bac5ddbdb..5fc9c288080b 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -196,6 +196,30 @@ int cs_etm__get_pid_fmt(u8 trace_chan_id, u64 *pid_fmt) return 0; } +static int cs_etm__map_trace_id(u8 trace_chan_id, u64 *cpu_metadata) +{ + struct int_node *inode; + + /* Get an RB node for this CPU */ + inode = intlist__findnew(traceid_list, trace_chan_id); + + /* Something went wrong, no need to continue */ + if (!inode) + return -ENOMEM; + + /* + * The node for that CPU should not be taken. + * Back out if that's the case. + */ + if (inode->priv) + return -EINVAL; + + /* All good, associate the traceID with the metadata pointer */ + inode->priv = cpu_metadata; + + return 0; +} + void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq, u8 trace_chan_id) { @@ -2804,17 +2828,46 @@ static bool cs_etm__has_virtual_ts(u64 **metadata, int num_cpu) return true; } +/* map trace ids to correct metadata block, from information in metadata */ +static int cs_etm__map_trace_ids_metadata(int num_cpu, u64 **metadata) +{ + u64 cs_etm_magic; + u8 trace_chan_id; + int i, err; + + for (i = 0; i < num_cpu; i++) { + cs_etm_magic = metadata[i][CS_ETM_MAGIC]; + switch (cs_etm_magic) { + case __perf_cs_etmv3_magic: + trace_chan_id = (u8)((metadata[i][CS_ETM_ETMTRACEIDR]) & + CORESIGHT_TRACE_ID_VAL_MASK); + break; + case __perf_cs_etmv4_magic: + case __perf_cs_ete_magic: + trace_chan_id = (u8)((metadata[i][CS_ETMV4_TRCTRACEIDR]) & + CORESIGHT_TRACE_ID_VAL_MASK); + break; + default: + /* unknown magic number */ + return -EINVAL; + } + err = cs_etm__map_trace_id(trace_chan_id, metadata[i]); + if (err) + return err; + } + return 0; +} + int cs_etm__process_auxtrace_info_full(union perf_event *event, struct perf_session *session) { struct perf_record_auxtrace_info *auxtrace_info = &event->auxtrace_info; struct cs_etm_auxtrace *etm = NULL; - struct int_node *inode; struct perf_record_time_conv *tc = &session->time_conv; int event_header_size = sizeof(struct perf_event_header); int total_size = auxtrace_info->header.size; int priv_size = 0; - int num_cpu, trcidr_idx; + int num_cpu; int err = 0; int i, j; u64 *ptr = NULL; @@ -2853,23 +2906,13 @@ int cs_etm__process_auxtrace_info_full(union perf_event *event, cs_etm__create_meta_blk(ptr, &i, CS_ETM_PRIV_MAX, CS_ETM_NR_TRC_PARAMS_V0); - - /* The traceID is our handle */ - trcidr_idx = CS_ETM_ETMTRACEIDR; - } else if (ptr[i] == __perf_cs_etmv4_magic) { metadata[j] = cs_etm__create_meta_blk(ptr, &i, CS_ETMV4_PRIV_MAX, CS_ETMV4_NR_TRC_PARAMS_V0); - - /* The traceID is our handle */ - trcidr_idx = CS_ETMV4_TRCTRACEIDR; } else if (ptr[i] == __perf_cs_ete_magic) { metadata[j] = cs_etm__create_meta_blk(ptr, &i, CS_ETE_PRIV_MAX, -1); - - /* ETE shares first part of metadata with ETMv4 */ - trcidr_idx = CS_ETMV4_TRCTRACEIDR; } else { ui__error("CS ETM Trace: Unrecognised magic number %#"PRIx64". File could be from a newer version of perf.\n", ptr[i]); @@ -2881,26 +2924,6 @@ int cs_etm__process_auxtrace_info_full(union perf_event *event, err = -ENOMEM; goto err_free_metadata; } - - /* Get an RB node for this CPU */ - inode = intlist__findnew(traceid_list, metadata[j][trcidr_idx]); - - /* Something went wrong, no need to continue */ - if (!inode) { - err = -ENOMEM; - goto err_free_metadata; - } - - /* - * The node for that CPU should not be taken. - * Back out if that's the case. - */ - if (inode->priv) { - err = -EINVAL; - goto err_free_metadata; - } - /* All good, associate the traceID with the metadata pointer */ - inode->priv = metadata[j]; } /* @@ -2994,6 +3017,11 @@ int cs_etm__process_auxtrace_info_full(union perf_event *event, if (err) goto err_delete_thread; + /* before aux records are queued, need to map metadata to trace IDs */ + err = cs_etm__map_trace_ids_metadata(num_cpu, metadata); + if (err) + goto err_delete_thread; + err = cs_etm__queue_aux_records(session); if (err) goto err_delete_thread; diff --git a/tools/perf/util/cs-etm.h b/tools/perf/util/cs-etm.h index 98a4f7113d2f..661f029322e4 100644 --- a/tools/perf/util/cs-etm.h +++ b/tools/perf/util/cs-etm.h @@ -29,13 +29,17 @@ enum { /* * Update the version for new format. * - * New version 1 format adds a param count to the per cpu metadata. + * Version 1: format adds a param count to the per cpu metadata. * This allows easy adding of new metadata parameters. * Requires that new params always added after current ones. * Also allows client reader to handle file versions that are different by * checking the number of params in the file vs the number expected. + * + * Version 2: Drivers will use PERF_RECORD_AUX_OUTPUT_HW_ID to output + * CoreSight Trace ID. ...TRACEIDR metadata will be set to legacy values + * but with addition flags. */ -#define CS_HEADER_CURRENT_VERSION 1 +#define CS_HEADER_CURRENT_VERSION 2 /* Beginning of header common to both ETMv3 and V4 */ enum { @@ -97,6 +101,12 @@ enum { CS_ETE_PRIV_MAX }; +/* + * Check for valid CoreSight trace ID. If an invalid value is present in the metadata, + * then IDs are present in the hardware ID packet in the data file. + */ +#define CS_IS_VALID_TRACE_ID(id) ((id > 0) && (id < 0x70)) + /* * ETMv3 exception encoding number: * See Embedded Trace Macrocell specification (ARM IHI 0014Q) -- cgit v1.2.3-58-ga151 From e5fa5b4110fe7d0ab08252943fc47072a7ff6c9d Mon Sep 17 00:00:00 2001 From: Mike Leach Date: Fri, 31 Mar 2023 06:56:44 +0100 Subject: perf cs-etm: Update record event to use new Trace ID protocol Trace IDs are now dynamically allocated. Previously used the static association algorithm that is no longer used. The 'cpu * 2 + seed' was outdated and broken for systems with high core counts (>46). as it did not scale and was broken for larger core counts. Trace ID will now be sent in PERF_RECORD_AUX_OUTPUT_HW_ID record. Legacy ID algorithm renamed and retained for limited backward compatibility use. Reviewed-by: James Clark Signed-off-by: Mike Leach Acked-by: Suzuki Poulouse Cc: Alexander Shishkin Cc: Darren Hart Cc: Ganapatrao Kulkarni Cc: Ingo Molnar Cc: Jiri Olsa Cc: Leo Yan Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Will Deacon Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230331055645.26918-2-mike.leach@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/include/linux/coresight-pmu.h | 29 +++++++++++++++++------------ tools/perf/arch/arm/util/cs-etm.c | 27 +++++++++++++++++---------- 2 files changed, 34 insertions(+), 22 deletions(-) (limited to 'tools') diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/coresight-pmu.h index db9c7c0abb6a..1760f9a574b0 100644 --- a/tools/include/linux/coresight-pmu.h +++ b/tools/include/linux/coresight-pmu.h @@ -10,11 +10,27 @@ #include #define CORESIGHT_ETM_PMU_NAME "cs_etm" -#define CORESIGHT_ETM_PMU_SEED 0x10 + +/* + * The legacy Trace ID system based on fixed calculation from the cpu + * number. This has been replaced by drivers using a dynamic allocation + * system - but need to retain the legacy algorithm for backward comparibility + * in certain situations:- + * a) new perf running on older systems that generate the legacy mapping + * b) older tools that may not update at the same time as the kernel. + */ +#define CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) (0x10 + (cpu * 2)) /* CoreSight trace ID is currently the bottom 7 bits of the value */ #define CORESIGHT_TRACE_ID_VAL_MASK GENMASK(6, 0) +/* + * perf record will set the legacy meta data values as unused initially. + * This allows perf report to manage the decoders created when dynamic + * allocation in operation. + */ +#define CORESIGHT_TRACE_ID_UNUSED_FLAG BIT(31) + /* * Below are the definition of bit offsets for perf option, and works as * arbitrary values for all ETM versions. @@ -39,15 +55,4 @@ #define ETM4_CFG_BIT_RETSTK 12 #define ETM4_CFG_BIT_VMID_OPT 15 -static inline int coresight_get_trace_id(int cpu) -{ - /* - * A trace ID of value 0 is invalid, so let's start at some - * random value that fits in 7 bits and go from there. Since - * the common convention is to have data trace IDs be I(N) + 1, - * set instruction trace IDs as a function of the CPU number. - */ - return (CORESIGHT_ETM_PMU_SEED + (cpu * 2)); -} - #endif diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c index 86b61ad74f90..e02a9bfc3d42 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -437,13 +437,16 @@ static int cs_etm_recording_options(struct auxtrace_record *itr, evlist__to_front(evlist, cs_etm_evsel); /* - * In the case of per-cpu mmaps, we need the CPU on the - * AUX event. We also need the contextID in order to be notified + * get the CPU on the sample - need it to associate trace ID in the + * AUX_OUTPUT_HW_ID event, and the AUX event for per-cpu mmaps. + */ + evsel__set_sample_bit(cs_etm_evsel, CPU); + + /* + * Also the case of per-cpu mmaps, need the contextID in order to be notified * when a context switch happened. */ if (!perf_cpu_map__empty(cpus)) { - evsel__set_sample_bit(cs_etm_evsel, CPU); - err = cs_etm_set_option(itr, cs_etm_evsel, BIT(ETM_OPT_CTXTID) | BIT(ETM_OPT_TS)); if (err) @@ -679,8 +682,10 @@ static void cs_etm_save_etmv4_header(__u64 data[], struct auxtrace_record *itr, /* Get trace configuration register */ data[CS_ETMV4_TRCCONFIGR] = cs_etmv4_get_config(itr); - /* Get traceID from the framework */ - data[CS_ETMV4_TRCTRACEIDR] = coresight_get_trace_id(cpu); + /* traceID set to legacy version, in case new perf running on older system */ + data[CS_ETMV4_TRCTRACEIDR] = + CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) | CORESIGHT_TRACE_ID_UNUSED_FLAG; + /* Get read-only information from sysFS */ data[CS_ETMV4_TRCIDR0] = cs_etm_get_ro(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TRCIDR0]); @@ -711,8 +716,10 @@ static void cs_etm_save_ete_header(__u64 data[], struct auxtrace_record *itr, in /* Get trace configuration register */ data[CS_ETE_TRCCONFIGR] = cs_etmv4_get_config(itr); - /* Get traceID from the framework */ - data[CS_ETE_TRCTRACEIDR] = coresight_get_trace_id(cpu); + /* traceID set to legacy version, in case new perf running on older system */ + data[CS_ETE_TRCTRACEIDR] = + CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) | CORESIGHT_TRACE_ID_UNUSED_FLAG; + /* Get read-only information from sysFS */ data[CS_ETE_TRCIDR0] = cs_etm_get_ro(cs_etm_pmu, cpu, metadata_ete_ro[CS_ETE_TRCIDR0]); @@ -768,9 +775,9 @@ static void cs_etm_get_metadata(int cpu, u32 *offset, magic = __perf_cs_etmv3_magic; /* Get configuration register */ info->priv[*offset + CS_ETM_ETMCR] = cs_etm_get_config(itr); - /* Get traceID from the framework */ + /* traceID set to legacy value in case new perf running on old system */ info->priv[*offset + CS_ETM_ETMTRACEIDR] = - coresight_get_trace_id(cpu); + CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) | CORESIGHT_TRACE_ID_UNUSED_FLAG; /* Get read-only information from sysFS */ info->priv[*offset + CS_ETM_ETMCCER] = cs_etm_get_ro(cs_etm_pmu, cpu, -- cgit v1.2.3-58-ga151 From b6521ea2a033b0c49669bd60d69ca16d0746dcea Mon Sep 17 00:00:00 2001 From: Mike Leach Date: Fri, 31 Mar 2023 06:56:45 +0100 Subject: perf cs-etm: Handle PERF_RECORD_AUX_OUTPUT_HW_ID packet When using dynamically assigned CoreSight trace IDs the drivers can output the ID / CPU association as a PERF_RECORD_AUX_OUTPUT_HW_ID packet. Update cs-etm decoder to handle this packet by setting the CPU/Trace ID mapping. Reviewed-by: James Clark Signed-off-by: Mike Leach Acked-by: Suzuki Poulouse Cc: Alexander Shishkin Cc: Darren Hart Cc: Ganapatrao Kulkarni Cc: Ingo Molnar Cc: Jiri Olsa Cc: Leo Yan Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Will Deacon Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230331055645.26918-2-mike.leach@linaro.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/include/linux/coresight-pmu.h | 15 ++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 7 + tools/perf/util/cs-etm.c | 246 ++++++++++++++++++++++-- 3 files changed, 250 insertions(+), 18 deletions(-) (limited to 'tools') diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/coresight-pmu.h index 1760f9a574b0..cef3b1c25335 100644 --- a/tools/include/linux/coresight-pmu.h +++ b/tools/include/linux/coresight-pmu.h @@ -31,6 +31,9 @@ */ #define CORESIGHT_TRACE_ID_UNUSED_FLAG BIT(31) +/* Value to set for unused trace ID values */ +#define CORESIGHT_TRACE_ID_UNUSED_VAL 0x7F + /* * Below are the definition of bit offsets for perf option, and works as * arbitrary values for all ETM versions. @@ -55,4 +58,16 @@ #define ETM4_CFG_BIT_RETSTK 12 #define ETM4_CFG_BIT_VMID_OPT 15 +/* + * Interpretation of the PERF_RECORD_AUX_OUTPUT_HW_ID payload. + * Used to associate a CPU with the CoreSight Trace ID. + * [07:00] - Trace ID - uses 8 bits to make value easy to read in file. + * [59:08] - Unused (SBZ) + * [63:60] - Version + */ +#define CS_AUX_HW_ID_TRACE_ID_MASK GENMASK_ULL(7, 0) +#define CS_AUX_HW_ID_VERSION_MASK GENMASK_ULL(63, 60) + +#define CS_AUX_HW_ID_CURR_VERSION 0 + #endif diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c index d0e521dfcf35..82a27ab90c8b 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c @@ -668,6 +668,7 @@ cs_etm_decoder__create_etm_decoder(struct cs_etm_decoder_params *d_params, switch (t_params->protocol) { case CS_ETM_PROTO_ETMV3: case CS_ETM_PROTO_PTM: + csid = (t_params->etmv3.reg_idr & CORESIGHT_TRACE_ID_VAL_MASK); cs_etm_decoder__gen_etmv3_config(t_params, &config_etmv3); decoder->decoder_name = (t_params->protocol == CS_ETM_PROTO_ETMV3) ? OCSD_BUILTIN_DCD_ETMV3 : @@ -675,11 +676,13 @@ cs_etm_decoder__create_etm_decoder(struct cs_etm_decoder_params *d_params, trace_config = &config_etmv3; break; case CS_ETM_PROTO_ETMV4i: + csid = (t_params->etmv4.reg_traceidr & CORESIGHT_TRACE_ID_VAL_MASK); cs_etm_decoder__gen_etmv4_config(t_params, &trace_config_etmv4); decoder->decoder_name = OCSD_BUILTIN_DCD_ETMV4I; trace_config = &trace_config_etmv4; break; case CS_ETM_PROTO_ETE: + csid = (t_params->ete.reg_traceidr & CORESIGHT_TRACE_ID_VAL_MASK); cs_etm_decoder__gen_ete_config(t_params, &trace_config_ete); decoder->decoder_name = OCSD_BUILTIN_DCD_ETE; trace_config = &trace_config_ete; @@ -688,6 +691,10 @@ cs_etm_decoder__create_etm_decoder(struct cs_etm_decoder_params *d_params, return -1; } + /* if the CPU has no trace ID associated, no decoder needed */ + if (csid == CORESIGHT_TRACE_ID_UNUSED_VAL) + return 0; + if (d_params->operation == CS_ETM_OPERATION_DECODE) { if (ocsd_dt_create_decoder(decoder->dcd_tree, decoder->decoder_name, diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 5fc9c288080b..94e2d02009eb 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -220,6 +220,143 @@ static int cs_etm__map_trace_id(u8 trace_chan_id, u64 *cpu_metadata) return 0; } +static int cs_etm__metadata_get_trace_id(u8 *trace_chan_id, u64 *cpu_metadata) +{ + u64 cs_etm_magic = cpu_metadata[CS_ETM_MAGIC]; + + switch (cs_etm_magic) { + case __perf_cs_etmv3_magic: + *trace_chan_id = (u8)(cpu_metadata[CS_ETM_ETMTRACEIDR] & + CORESIGHT_TRACE_ID_VAL_MASK); + break; + case __perf_cs_etmv4_magic: + case __perf_cs_ete_magic: + *trace_chan_id = (u8)(cpu_metadata[CS_ETMV4_TRCTRACEIDR] & + CORESIGHT_TRACE_ID_VAL_MASK); + break; + default: + return -EINVAL; + } + return 0; +} + +/* + * update metadata trace ID from the value found in the AUX_HW_INFO packet. + * This will also clear the CORESIGHT_TRACE_ID_UNUSED_FLAG flag if present. + */ +static int cs_etm__metadata_set_trace_id(u8 trace_chan_id, u64 *cpu_metadata) +{ + u64 cs_etm_magic = cpu_metadata[CS_ETM_MAGIC]; + + switch (cs_etm_magic) { + case __perf_cs_etmv3_magic: + cpu_metadata[CS_ETM_ETMTRACEIDR] = trace_chan_id; + break; + case __perf_cs_etmv4_magic: + case __perf_cs_ete_magic: + cpu_metadata[CS_ETMV4_TRCTRACEIDR] = trace_chan_id; + break; + + default: + return -EINVAL; + } + return 0; +} + +/* + * FIELD_GET (linux/bitfield.h) not available outside kernel code, + * and the header contains too many dependencies to just copy over, + * so roll our own based on the original + */ +#define __bf_shf(x) (__builtin_ffsll(x) - 1) +#define FIELD_GET(_mask, _reg) \ + ({ \ + (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ + }) + +/* + * Handle the PERF_RECORD_AUX_OUTPUT_HW_ID event. + * + * The payload associates the Trace ID and the CPU. + * The routine is tolerant of seeing multiple packets with the same association, + * but a CPU / Trace ID association changing during a session is an error. + */ +static int cs_etm__process_aux_output_hw_id(struct perf_session *session, + union perf_event *event) +{ + struct cs_etm_auxtrace *etm; + struct perf_sample sample; + struct int_node *inode; + struct evsel *evsel; + u64 *cpu_data; + u64 hw_id; + int cpu, version, err; + u8 trace_chan_id, curr_chan_id; + + /* extract and parse the HW ID */ + hw_id = event->aux_output_hw_id.hw_id; + version = FIELD_GET(CS_AUX_HW_ID_VERSION_MASK, hw_id); + trace_chan_id = FIELD_GET(CS_AUX_HW_ID_TRACE_ID_MASK, hw_id); + + /* check that we can handle this version */ + if (version > CS_AUX_HW_ID_CURR_VERSION) + return -EINVAL; + + /* get access to the etm metadata */ + etm = container_of(session->auxtrace, struct cs_etm_auxtrace, auxtrace); + if (!etm || !etm->metadata) + return -EINVAL; + + /* parse the sample to get the CPU */ + evsel = evlist__event2evsel(session->evlist, event); + if (!evsel) + return -EINVAL; + err = evsel__parse_sample(evsel, event, &sample); + if (err) + return err; + cpu = sample.cpu; + if (cpu == -1) { + /* no CPU in the sample - possibly recorded with an old version of perf */ + pr_err("CS_ETM: no CPU AUX_OUTPUT_HW_ID sample. Use compatible perf to record."); + return -EINVAL; + } + + /* See if the ID is mapped to a CPU, and it matches the current CPU */ + inode = intlist__find(traceid_list, trace_chan_id); + if (inode) { + cpu_data = inode->priv; + if ((int)cpu_data[CS_ETM_CPU] != cpu) { + pr_err("CS_ETM: map mismatch between HW_ID packet CPU and Trace ID\n"); + return -EINVAL; + } + + /* check that the mapped ID matches */ + err = cs_etm__metadata_get_trace_id(&curr_chan_id, cpu_data); + if (err) + return err; + if (curr_chan_id != trace_chan_id) { + pr_err("CS_ETM: mismatch between CPU trace ID and HW_ID packet ID\n"); + return -EINVAL; + } + + /* mapped and matched - return OK */ + return 0; + } + + /* not one we've seen before - lets map it */ + cpu_data = etm->metadata[cpu]; + err = cs_etm__map_trace_id(trace_chan_id, cpu_data); + if (err) + return err; + + /* + * if we are picking up the association from the packet, need to plug + * the correct trace ID into the metadata for setting up decoders later. + */ + err = cs_etm__metadata_set_trace_id(trace_chan_id, cpu_data); + return err; +} + void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq, u8 trace_chan_id) { @@ -2668,11 +2805,16 @@ static int cs_etm__queue_aux_fragment(struct perf_session *session, off_t file_o } /* - * In per-thread mode, CPU is set to -1, but TID will be set instead. See - * auxtrace_mmap_params__set_idx(). Return 'not found' if neither CPU nor TID match. + * In per-thread mode, auxtrace CPU is set to -1, but TID will be set instead. See + * auxtrace_mmap_params__set_idx(). However, the sample AUX event will contain a + * CPU as we set this always for the AUX_OUTPUT_HW_ID event. + * So now compare only TIDs if auxtrace CPU is -1, and CPUs if auxtrace CPU is not -1. + * Return 'not found' if mismatch. */ - if ((auxtrace_event->cpu == (__u32) -1 && auxtrace_event->tid != sample->tid) || - auxtrace_event->cpu != sample->cpu) + if (auxtrace_event->cpu == (__u32) -1) { + if (auxtrace_event->tid != sample->tid) + return 1; + } else if (auxtrace_event->cpu != sample->cpu) return 1; if (aux_event->flags & PERF_AUX_FLAG_OVERWRITE) { @@ -2721,6 +2863,17 @@ static int cs_etm__queue_aux_fragment(struct perf_session *session, off_t file_o return 1; } +static int cs_etm__process_aux_hw_id_cb(struct perf_session *session, union perf_event *event, + u64 offset __maybe_unused, void *data __maybe_unused) +{ + /* look to handle PERF_RECORD_AUX_OUTPUT_HW_ID early to ensure decoders can be set up */ + if (event->header.type == PERF_RECORD_AUX_OUTPUT_HW_ID) { + (*(int *)data)++; /* increment found count */ + return cs_etm__process_aux_output_hw_id(session, event); + } + return 0; +} + static int cs_etm__queue_aux_records_cb(struct perf_session *session, union perf_event *event, u64 offset __maybe_unused, void *data __maybe_unused) { @@ -2839,13 +2992,13 @@ static int cs_etm__map_trace_ids_metadata(int num_cpu, u64 **metadata) cs_etm_magic = metadata[i][CS_ETM_MAGIC]; switch (cs_etm_magic) { case __perf_cs_etmv3_magic: - trace_chan_id = (u8)((metadata[i][CS_ETM_ETMTRACEIDR]) & - CORESIGHT_TRACE_ID_VAL_MASK); + metadata[i][CS_ETM_ETMTRACEIDR] &= CORESIGHT_TRACE_ID_VAL_MASK; + trace_chan_id = (u8)(metadata[i][CS_ETM_ETMTRACEIDR]); break; case __perf_cs_etmv4_magic: case __perf_cs_ete_magic: - trace_chan_id = (u8)((metadata[i][CS_ETMV4_TRCTRACEIDR]) & - CORESIGHT_TRACE_ID_VAL_MASK); + metadata[i][CS_ETMV4_TRCTRACEIDR] &= CORESIGHT_TRACE_ID_VAL_MASK; + trace_chan_id = (u8)(metadata[i][CS_ETMV4_TRCTRACEIDR]); break; default: /* unknown magic number */ @@ -2858,6 +3011,35 @@ static int cs_etm__map_trace_ids_metadata(int num_cpu, u64 **metadata) return 0; } +/* + * If we found AUX_HW_ID packets, then set any metadata marked as unused to the + * unused value to reduce the number of unneeded decoders created. + */ +static int cs_etm__clear_unused_trace_ids_metadata(int num_cpu, u64 **metadata) +{ + u64 cs_etm_magic; + int i; + + for (i = 0; i < num_cpu; i++) { + cs_etm_magic = metadata[i][CS_ETM_MAGIC]; + switch (cs_etm_magic) { + case __perf_cs_etmv3_magic: + if (metadata[i][CS_ETM_ETMTRACEIDR] & CORESIGHT_TRACE_ID_UNUSED_FLAG) + metadata[i][CS_ETM_ETMTRACEIDR] = CORESIGHT_TRACE_ID_UNUSED_VAL; + break; + case __perf_cs_etmv4_magic: + case __perf_cs_ete_magic: + if (metadata[i][CS_ETMV4_TRCTRACEIDR] & CORESIGHT_TRACE_ID_UNUSED_FLAG) + metadata[i][CS_ETMV4_TRCTRACEIDR] = CORESIGHT_TRACE_ID_UNUSED_VAL; + break; + default: + /* unknown magic number */ + return -EINVAL; + } + } + return 0; +} + int cs_etm__process_auxtrace_info_full(union perf_event *event, struct perf_session *session) { @@ -2869,6 +3051,7 @@ int cs_etm__process_auxtrace_info_full(union perf_event *event, int priv_size = 0; int num_cpu; int err = 0; + int aux_hw_id_found; int i, j; u64 *ptr = NULL; u64 **metadata = NULL; @@ -3017,8 +3200,43 @@ int cs_etm__process_auxtrace_info_full(union perf_event *event, if (err) goto err_delete_thread; - /* before aux records are queued, need to map metadata to trace IDs */ - err = cs_etm__map_trace_ids_metadata(num_cpu, metadata); + /* + * Map Trace ID values to CPU metadata. + * + * Trace metadata will always contain Trace ID values from the legacy algorithm. If the + * files has been recorded by a "new" perf updated to handle AUX_HW_ID then the metadata + * ID value will also have the CORESIGHT_TRACE_ID_UNUSED_FLAG set. + * + * The updated kernel drivers that use AUX_HW_ID to sent Trace IDs will attempt to use + * the same IDs as the old algorithm as far as is possible, unless there are clashes + * in which case a different value will be used. This means an older perf may still + * be able to record and read files generate on a newer system. + * + * For a perf able to interpret AUX_HW_ID packets we first check for the presence of + * those packets. If they are there then the values will be mapped and plugged into + * the metadata. We then set any remaining metadata values with the used flag to a + * value CORESIGHT_TRACE_ID_UNUSED_VAL - which indicates no decoder is required. + * + * If no AUX_HW_ID packets are present - which means a file recorded on an old kernel + * then we map Trace ID values to CPU directly from the metadata - clearing any unused + * flags if present. + */ + + /* first scan for AUX_OUTPUT_HW_ID records to map trace ID values to CPU metadata */ + aux_hw_id_found = 0; + err = perf_session__peek_events(session, session->header.data_offset, + session->header.data_size, + cs_etm__process_aux_hw_id_cb, &aux_hw_id_found); + if (err) + goto err_delete_thread; + + /* if HW ID found then clear any unused metadata ID values */ + if (aux_hw_id_found) + err = cs_etm__clear_unused_trace_ids_metadata(num_cpu, metadata); + /* otherwise, this is a file with metadata values only, map from metadata */ + else + err = cs_etm__map_trace_ids_metadata(num_cpu, metadata); + if (err) goto err_delete_thread; @@ -3027,14 +3245,6 @@ int cs_etm__process_auxtrace_info_full(union perf_event *event, goto err_delete_thread; etm->data_queued = etm->queues.populated; - /* - * Print warning in pipe mode, see cs_etm__process_auxtrace_event() and - * cs_etm__queue_aux_fragment() for details relating to limitations. - */ - if (!etm->data_queued) - pr_warning("CS ETM warning: Coresight decode and TRBE support requires random file access.\n" - "Continuing with best effort decoding in piped mode.\n\n"); - return 0; err_delete_thread: -- cgit v1.2.3-58-ga151 From 34fb60400e3257f3a046ee8e6b49242cf65cc1a3 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 27 Mar 2023 11:20:57 -0500 Subject: perf arm-spe: Add raw decoding for SPEv1.3 MTE and MOPS load/store Arm SPEv1.3 adds new load/store operation subclasses for Memory Tagging Extension (MTE) and memory operations (MOPS). The memory operations are memcpy and memset. Add support for decoding these new subclasses in the raw decoding. Reviewed-by: Leo Yan Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Leo Yan Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230327162057.4057188-1-robh@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c | 9 +++++++++ tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h | 3 +++ 2 files changed, 12 insertions(+) (limited to 'tools') diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c index fed4741f372e..a454c6737563 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c +++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c @@ -381,6 +381,15 @@ static int arm_spe_pkt_desc_op_type(const struct arm_spe_pkt *packet, case SPE_OP_PKT_LDST_SUBCLASS_NV_SYSREG: arm_spe_pkt_out_string(&err, &buf, &buf_len, " NV-SYSREG"); break; + case SPE_OP_PKT_LDST_SUBCLASS_MTE_TAG: + arm_spe_pkt_out_string(&err, &buf, &buf_len, " MTE-TAG"); + break; + case SPE_OP_PKT_LDST_SUBCLASS_MEMCPY: + arm_spe_pkt_out_string(&err, &buf, &buf_len, " MEMCPY"); + break; + case SPE_OP_PKT_LDST_SUBCLASS_MEMSET: + arm_spe_pkt_out_string(&err, &buf, &buf_len, " MEMSET"); + break; default: break; } diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h index f75ed3a8a050..464a912b221c 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h +++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.h @@ -123,6 +123,9 @@ enum arm_spe_events { #define SPE_OP_PKT_LDST_SUBCLASS_SIMD_FP 0x4 #define SPE_OP_PKT_LDST_SUBCLASS_UNSPEC_REG 0x10 #define SPE_OP_PKT_LDST_SUBCLASS_NV_SYSREG 0x30 +#define SPE_OP_PKT_LDST_SUBCLASS_MTE_TAG 0x14 +#define SPE_OP_PKT_LDST_SUBCLASS_MEMCPY 0x20 +#define SPE_OP_PKT_LDST_SUBCLASS_MEMSET 0x25 #define SPE_OP_PKT_IS_LDST_ATOMIC(v) (((v) & (GENMASK_ULL(7, 5) | BIT(1))) == 0x2) -- cgit v1.2.3-58-ga151 From 1f9f33ccf0320be21703d9195dd2b36a1c9a07cb Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Mon, 3 Apr 2023 18:48:30 +0300 Subject: perf auxtrace: Fix address filter entire kernel size kallsyms is not completely in address order. In find_entire_kern_cb(), calculate the kernel end from the maximum address not the last symbol. Example: Before: $ sudo cat /proc/kallsyms | grep ' [twTw] ' | tail -1 ffffffffc00b8bd0 t bpf_prog_6deef7357e7b4530 [bpf] $ sudo cat /proc/kallsyms | grep ' [twTw] ' | sort | tail -1 ffffffffc15e0cc0 t iwl_mvm_exit [iwlmvm] $ perf.d093603a05aa record -v --kcore -e intel_pt// --filter 'filter *' -- uname |& grep filter Address filter: filter 0xffffffff93200000/0x2ceba000 After: $ perf.8fb0f7a01f8e record -v --kcore -e intel_pt// --filter 'filter *' -- uname |& grep filter Address filter: filter 0xffffffff93200000/0x2e3e2000 Fixes: 1b36c03e356936d6 ("perf record: Add support for using symbols in address filters") Signed-off-by: Adrian Hunter Cc: Adrian Hunter Cc: Ian Rogers Cc: Jiri Olsa Cc: Namhyung Kim Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230403154831.8651-2-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/auxtrace.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/auxtrace.c b/tools/perf/util/auxtrace.c index 498ff7f24463..b2a5e5397bad 100644 --- a/tools/perf/util/auxtrace.c +++ b/tools/perf/util/auxtrace.c @@ -2449,6 +2449,7 @@ static int find_entire_kern_cb(void *arg, const char *name __maybe_unused, char type, u64 start) { struct sym_args *args = arg; + u64 size; if (!kallsyms__is_function(type)) return 0; @@ -2458,7 +2459,9 @@ static int find_entire_kern_cb(void *arg, const char *name __maybe_unused, args->start = start; } /* Don't know exactly where the kernel ends, so we add a page */ - args->size = round_up(start, page_size) + page_size - args->start; + size = round_up(start, page_size) + page_size - args->start; + if (size > args->size) + args->size = size; return 0; } -- cgit v1.2.3-58-ga151 From 430635a0ef1ce958b7b4311f172694ece2c692b8 Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Mon, 3 Apr 2023 18:48:31 +0300 Subject: perf intel-pt: Fix CYC timestamps after standalone CBR After a standalone CBR (not associated with TSC), update the cycles reference timestamp and reset the cycle count, so that CYC timestamps are calculated relative to that point with the new frequency. Fixes: cc33618619cefc6d ("perf tools: Add Intel PT support for decoding CYC packets") Signed-off-by: Adrian Hunter Cc: Adrian Hunter Cc: Ian Rogers Cc: Jiri Olsa Cc: Namhyung Kim Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230403154831.8651-2-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/intel-pt-decoder/intel-pt-decoder.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'tools') diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c b/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c index 0ac860c8dd2b..7145c5890de0 100644 --- a/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c +++ b/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c @@ -1998,6 +1998,8 @@ static void intel_pt_calc_cbr(struct intel_pt_decoder *decoder) decoder->cbr = cbr; decoder->cbr_cyc_to_tsc = decoder->max_non_turbo_ratio_fp / cbr; + decoder->cyc_ref_timestamp = decoder->timestamp; + decoder->cycle_cnt = 0; intel_pt_mtc_cyc_cnt_cbr(decoder); } -- cgit v1.2.3-58-ga151 From 9e03608e93858620317d54bc88a9a0069bce003d Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Tue, 4 Apr 2023 11:05:57 -0300 Subject: tools build: Add a feature test for scandirat(), that is not implemented so far in musl and uclibc We use it just when listing tracepoint events, and for root, so just emit a warning about it to get users to ask the library maintainers to implement it, as suggested in this systemd ticket: https://github.com/systemd/casync/issues/129 Cc: Adrian Hunter Cc: Ian Rogers Cc: Jiri Olsa Cc: Namhyung Kim Link: https://lore.kernel.org/lkml/ZCwv4z5Dh%2FdHUMG6@kernel.org/ Signed-off-by: Arnaldo Carvalho de Melo --- tools/build/Makefile.feature | 1 + tools/build/feature/Makefile | 4 ++++ tools/build/feature/test-all.c | 5 +++++ tools/build/feature/test-scandirat.c | 13 +++++++++++++ tools/perf/Makefile.config | 4 ++++ 5 files changed, 27 insertions(+) create mode 100644 tools/build/feature/test-scandirat.c (limited to 'tools') diff --git a/tools/build/Makefile.feature b/tools/build/Makefile.feature index 214622d7537c..934e2777a2db 100644 --- a/tools/build/Makefile.feature +++ b/tools/build/Makefile.feature @@ -64,6 +64,7 @@ FEATURE_TESTS_BASIC := \ lzma \ get_cpuid \ bpf \ + scandirat \ sched_getcpu \ sdt \ setns \ diff --git a/tools/build/feature/Makefile b/tools/build/feature/Makefile index 0a3b9281f8b0..0f0aa9b7d7b5 100644 --- a/tools/build/feature/Makefile +++ b/tools/build/feature/Makefile @@ -65,6 +65,7 @@ FILES= \ test-gettid.bin \ test-jvmti.bin \ test-jvmti-cmlr.bin \ + test-scandirat.bin \ test-sched_getcpu.bin \ test-setns.bin \ test-libopencsd.bin \ @@ -129,6 +130,9 @@ $(OUTPUT)test-get_current_dir_name.bin: $(OUTPUT)test-glibc.bin: $(BUILD) +$(OUTPUT)test-scandirat.bin: + $(BUILD) + $(OUTPUT)test-sched_getcpu.bin: $(BUILD) diff --git a/tools/build/feature/test-all.c b/tools/build/feature/test-all.c index 957c02c7b163..6f4bf386a3b5 100644 --- a/tools/build/feature/test-all.c +++ b/tools/build/feature/test-all.c @@ -114,6 +114,10 @@ # include "test-pthread-barrier.c" #undef main +#define main main_test_scandirat +# include "test-scandirat.c" +#undef main + #define main main_test_sched_getcpu # include "test-sched_getcpu.c" #undef main @@ -206,6 +210,7 @@ int main(int argc, char *argv[]) main_test_get_cpuid(); main_test_bpf(); main_test_libcrypto(); + main_test_scandirat(); main_test_sched_getcpu(); main_test_sdt(); main_test_setns(); diff --git a/tools/build/feature/test-scandirat.c b/tools/build/feature/test-scandirat.c new file mode 100644 index 000000000000..d7e19e1858a5 --- /dev/null +++ b/tools/build/feature/test-scandirat.c @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +#ifndef _GNU_SOURCE +#define _GNU_SOURCE +#endif +#include + +int main(void) +{ + // expects non-NULL, arg3 is 'restrict' so "pointers" have to be different + return scandirat(/*dirfd=*/ 0, /*dirp=*/ (void *)1, /*namelist=*/ (void *)2, /*filter=*/ (void *)3, /*compar=*/ (void *)4); +} + +#undef _GNU_SOURCE diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index 236d763181c5..fd1be9596d12 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -479,6 +479,10 @@ ifdef NO_DWARF NO_LIBDW_DWARF_UNWIND := 1 endif +ifeq ($(feature-scandirat), 1) + CFLAGS += -DHAVE_SCANDIRAT_SUPPORT +endif + ifeq ($(feature-sched_getcpu), 1) CFLAGS += -DHAVE_SCHED_GETCPU_SUPPORT endif -- cgit v1.2.3-58-ga151 From 00462d8eaca4eb48e4c07a9a9b49cea2a871fd35 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Fri, 31 Mar 2023 13:29:41 -0700 Subject: perf list: Use relative path for tracepoint scan Committer notes: Added missing #include for the close() prototype to fix this on Alma Linux 8: 1 21.54 almalinux:8 : FAIL gcc version 8.5.0 20210514 (Red Hat 8.5.0-16) (GCC) util/print-events.c: In function 'print_tracepoint_events': util/print-events.c:103:4: error: implicit declaration of function 'close'; did you mean 'clone'? [-Werror=implicit-function-declaration] close(evt_fd); ^~~~~ clone Also use the newly added scandirat feature test to check if that function is available, providing a HAVE_SCANDIRAT_SUPPORT conditional warning to the user if it isn't available. Signed-off-by: Namhyung Kim Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Leo Yan Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230331202949.810326-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/print-events.c | 38 +++++++++++++++++++++++++++++++------- 1 file changed, 31 insertions(+), 7 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/print-events.c b/tools/perf/util/print-events.c index 62e9ea7dcf40..386b1ab0b60e 100644 --- a/tools/perf/util/print-events.c +++ b/tools/perf/util/print-events.c @@ -4,7 +4,9 @@ #include #include #include +#include #include +#include #include #include @@ -56,7 +58,18 @@ static const struct event_symbol event_symbols_tool[PERF_TOOL_MAX] = { /* * Print the events from /tracing/events */ -void print_tracepoint_events(const struct print_callbacks *print_cb, void *print_state) +void print_tracepoint_events(const struct print_callbacks *print_cb __maybe_unused, void *print_state __maybe_unused) +{ + char *events_path = get_tracing_file("events"); + int events_fd = open(events_path, O_PATH); + + put_tracing_file(events_path); + if (events_fd < 0) { + printf("Error: failed to open tracing events directory\n"); + return; + } + +#ifdef HAVE_SCANDIRAT_SUPPORT { struct dirent **sys_namelist = NULL; int sys_items = tracing_events__scandir_alphasort(&sys_namelist); @@ -64,7 +77,7 @@ void print_tracepoint_events(const struct print_callbacks *print_cb, void *print for (int i = 0; i < sys_items; i++) { struct dirent *sys_dirent = sys_namelist[i]; struct dirent **evt_namelist = NULL; - char *dir_path; + int dir_fd; int evt_items; if (sys_dirent->d_type != DT_DIR || @@ -72,22 +85,26 @@ void print_tracepoint_events(const struct print_callbacks *print_cb, void *print !strcmp(sys_dirent->d_name, "..")) continue; - dir_path = get_events_file(sys_dirent->d_name); - if (!dir_path) + dir_fd = openat(events_fd, sys_dirent->d_name, O_PATH); + if (dir_fd < 0) continue; - evt_items = scandir(dir_path, &evt_namelist, NULL, alphasort); + evt_items = scandirat(events_fd, sys_dirent->d_name, &evt_namelist, NULL, alphasort); for (int j = 0; j < evt_items; j++) { struct dirent *evt_dirent = evt_namelist[j]; char evt_path[MAXPATHLEN]; + int evt_fd; if (evt_dirent->d_type != DT_DIR || !strcmp(evt_dirent->d_name, ".") || !strcmp(evt_dirent->d_name, "..")) continue; - if (tp_event_has_id(dir_path, evt_dirent) != 0) + snprintf(evt_path, sizeof(evt_path), "%s/id", evt_dirent->d_name); + evt_fd = openat(dir_fd, evt_path, O_RDONLY); + if (evt_fd < 0) continue; + close(evt_fd); snprintf(evt_path, MAXPATHLEN, "%s:%s", sys_dirent->d_name, evt_dirent->d_name); @@ -103,11 +120,18 @@ void print_tracepoint_events(const struct print_callbacks *print_cb, void *print /*long_desc=*/NULL, /*encoding_desc=*/NULL); } - free(dir_path); + close(dir_fd); free(evt_namelist); } + free(sys_namelist); } +#else + printf("\nWARNING: Your libc doesn't have the scandir function, please ask its maintainers to implement it.\n" + " As a rough fallback, please do 'ls %s' to see the available tracepoint events.\n", events_path); +#endif + close(events_fd); +} void print_sdt_events(const struct print_callbacks *print_cb, void *print_state) { -- cgit v1.2.3-58-ga151 From 66c9598bd8916c6c1319d0100ac916cac89d4b0e Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Fri, 31 Mar 2023 13:29:42 -0700 Subject: perf tools: Fix a asan issue in parse_events_multi_pmu_add() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In the parse_events_multi_pmu_add() it passes the 'config' variable twice to parse_events_term__num() - one for config and another for loc_term. I'm not sure about the second one as it's converted to YYLTYPE variable. Asan reports it like below: In function ‘parse_events_term__num’, inlined from ‘parse_events_multi_pmu_add’ at util/parse-events.c:1602:6: util/parse-events.c:2653:64: error: array subscript ‘YYLTYPE[0]’ is partly outside array bounds of ‘char[8]’ [-Werror=array-bounds] 2653 | .err_term = loc_term ? loc_term->first_column : 0, | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~ util/parse-events.c: In function ‘parse_events_multi_pmu_add’: util/parse-events.c:1587:15: note: object ‘config’ of size 8 1587 | char *config; | ^~~~~~ cc1: all warnings being treated as errors Signed-off-by: Namhyung Kim Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Leo Yan Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230331202949.810326-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/parse-events.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index cc8e8766ca30..0010e5e0ee68 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -1601,7 +1601,7 @@ int parse_events_multi_pmu_add(struct parse_events_state *parse_state, if (parse_events_term__num(&term, PARSE_EVENTS__TERM_TYPE_USER, - config, 1, false, &config, + config, 1, false, NULL, NULL) < 0) { free(config); goto out_err; -- cgit v1.2.3-58-ga151 From eec1131091c88e5e72cb012a2e3b3789fbb53c15 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Fri, 31 Mar 2023 13:29:43 -0700 Subject: perf pmu: Add perf_pmu__destroy() function It seems there's no function to delete the perf pmu struct. Add the perf_pmu__destroy() to do the job. While at it, add some more helper functions to delete pmu aliases and caps. Signed-off-by: Namhyung Kim Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Leo Yan Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230331202949.810326-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/pmu.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ tools/perf/util/pmu.h | 2 ++ 2 files changed, 52 insertions(+) (limited to 'tools') diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index e3aae731bd6f..b112606f36ec 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -300,6 +300,16 @@ void perf_pmu_free_alias(struct perf_pmu_alias *newalias) free(newalias); } +static void perf_pmu__del_aliases(struct perf_pmu *pmu) +{ + struct perf_pmu_alias *alias, *tmp; + + list_for_each_entry_safe(alias, tmp, &pmu->aliases, list) { + list_del(&alias->list); + perf_pmu_free_alias(alias); + } +} + /* Merge an alias, search in alias list. If this name is already * present merge both of them to combine all information. */ @@ -921,6 +931,8 @@ static struct perf_pmu *pmu_lookup(const char *lookup_name) if (is_hybrid) list_add_tail(&pmu->hybrid_list, &perf_pmu__hybrid_pmus); + else + INIT_LIST_HEAD(&pmu->hybrid_list); pmu->default_config = perf_pmu__get_default_config(pmu); @@ -1750,6 +1762,18 @@ free_caps: return -ENOMEM; } +static void perf_pmu__del_caps(struct perf_pmu *pmu) +{ + struct perf_pmu_caps *caps, *tmp; + + list_for_each_entry_safe(caps, tmp, &pmu->caps, list) { + list_del(&caps->list); + free(caps->name); + free(caps->value); + free(caps); + } +} + /* * Reading/parsing the given pmu capabilities, which should be located at: * /sys/bus/event_source/devices//caps as sysfs group attributes. @@ -1932,3 +1956,29 @@ int perf_pmu__pathname_scnprintf(char *buf, size_t size, return 0; return scnprintf(buf, size, "%s%s/%s", base_path, pmu_name, filename); } + +static void perf_pmu__delete(struct perf_pmu *pmu) +{ + perf_pmu__del_formats(&pmu->format); + perf_pmu__del_aliases(pmu); + perf_pmu__del_caps(pmu); + + perf_cpu_map__put(pmu->cpus); + + free(pmu->default_config); + free(pmu->name); + free(pmu->alias_name); + free(pmu); +} + +void perf_pmu__destroy(void) +{ + struct perf_pmu *pmu, *tmp; + + list_for_each_entry_safe(pmu, tmp, &pmus, list) { + list_del(&pmu->list); + list_del(&pmu->hybrid_list); + + perf_pmu__delete(pmu); + } +} diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h index 24cf69ab32cd..72fd5de334c0 100644 --- a/tools/perf/util/pmu.h +++ b/tools/perf/util/pmu.h @@ -259,4 +259,6 @@ int perf_pmu__pathname_scnprintf(char *buf, size_t size, const char *pmu_name, const char *filename); FILE *perf_pmu__open_file(struct perf_pmu *pmu, const char *name); +void perf_pmu__destroy(void); + #endif /* __PMU_H */ -- cgit v1.2.3-58-ga151 From f6a7bbbfe61cc34c4e443141d3eb110a80473d8c Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Fri, 31 Mar 2023 13:29:44 -0700 Subject: perf bench: Add pmu-scan benchmark The pmu-scan benchmark will repeatedly scan the sysfs to get the available PMU information. $ ./perf bench internals pmu-scan # Running 'internals/pmu-scan' benchmark: Computing performance of sysfs PMU event scan for 100 times Average PMU scanning took: 6850.990 usec (+- 48.445 usec) Signed-off-by: Namhyung Kim Acked-by: Ian Rogers Tested-by: Arnaldo Carvalho de Melo Cc: Adrian Hunter Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Leo Yan Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230331202949.810326-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/bench/Build | 1 + tools/perf/bench/bench.h | 1 + tools/perf/bench/pmu-scan.c | 184 ++++++++++++++++++++++++++++++++++++++++++++ tools/perf/builtin-bench.c | 1 + 4 files changed, 187 insertions(+) create mode 100644 tools/perf/bench/pmu-scan.c (limited to 'tools') diff --git a/tools/perf/bench/Build b/tools/perf/bench/Build index 6b6155a8ad09..0f158dc8139b 100644 --- a/tools/perf/bench/Build +++ b/tools/perf/bench/Build @@ -15,6 +15,7 @@ perf-y += find-bit-bench.o perf-y += inject-buildid.o perf-y += evlist-open-close.o perf-y += breakpoint.o +perf-y += pmu-scan.o perf-$(CONFIG_X86_64) += mem-memcpy-x86-64-asm.o perf-$(CONFIG_X86_64) += mem-memset-x86-64-asm.o diff --git a/tools/perf/bench/bench.h b/tools/perf/bench/bench.h index edfc25793cca..0d2b65976212 100644 --- a/tools/perf/bench/bench.h +++ b/tools/perf/bench/bench.h @@ -42,6 +42,7 @@ int bench_inject_build_id(int argc, const char **argv); int bench_evlist_open_close(int argc, const char **argv); int bench_breakpoint_thread(int argc, const char **argv); int bench_breakpoint_enable(int argc, const char **argv); +int bench_pmu_scan(int argc, const char **argv); #define BENCH_FORMAT_DEFAULT_STR "default" #define BENCH_FORMAT_DEFAULT 0 diff --git a/tools/perf/bench/pmu-scan.c b/tools/perf/bench/pmu-scan.c new file mode 100644 index 000000000000..f0f007843bb8 --- /dev/null +++ b/tools/perf/bench/pmu-scan.c @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Benchmark scanning sysfs files for PMU information. + * + * Copyright 2023 Google LLC. + */ +#include +#include "bench.h" +#include "util/debug.h" +#include "util/pmu.h" +#include "util/pmus.h" +#include "util/stat.h" +#include +#include +#include +#include + +static unsigned int iterations = 100; + +struct pmu_scan_result { + char *name; + int nr_aliases; + int nr_formats; + int nr_caps; +}; + +static const struct option options[] = { + OPT_UINTEGER('i', "iterations", &iterations, + "Number of iterations used to compute average"), + OPT_END() +}; + +static const char *const bench_usage[] = { + "perf bench internals pmu-scan ", + NULL +}; + +static int nr_pmus; +static struct pmu_scan_result *results; + +static int save_result(void) +{ + struct perf_pmu *pmu; + struct list_head *list; + struct pmu_scan_result *r; + + perf_pmu__scan(NULL); + + perf_pmus__for_each_pmu(pmu) { + r = realloc(results, (nr_pmus + 1) * sizeof(*r)); + if (r == NULL) + return -ENOMEM; + + results = r; + r = results + nr_pmus; + + r->name = strdup(pmu->name); + r->nr_caps = pmu->nr_caps; + + r->nr_aliases = 0; + list_for_each(list, &pmu->aliases) + r->nr_aliases++; + + r->nr_formats = 0; + list_for_each(list, &pmu->format) + r->nr_formats++; + + pr_debug("pmu[%d] name=%s, nr_caps=%d, nr_aliases=%d, nr_formats=%d\n", + nr_pmus, r->name, r->nr_caps, r->nr_aliases, r->nr_formats); + nr_pmus++; + } + + perf_pmu__destroy(); + return 0; +} + +static int check_result(void) +{ + struct pmu_scan_result *r; + struct perf_pmu *pmu; + struct list_head *list; + int nr; + + for (int i = 0; i < nr_pmus; i++) { + r = &results[i]; + pmu = perf_pmu__find(r->name); + if (pmu == NULL) { + pr_err("Cannot find PMU %s\n", r->name); + return -1; + } + + if (pmu->nr_caps != (u32)r->nr_caps) { + pr_err("Unmatched number of event caps in %s: expect %d vs got %d\n", + pmu->name, r->nr_caps, pmu->nr_caps); + return -1; + } + + nr = 0; + list_for_each(list, &pmu->aliases) + nr++; + if (nr != r->nr_aliases) { + pr_err("Unmatched number of event aliases in %s: expect %d vs got %d\n", + pmu->name, r->nr_aliases, nr); + return -1; + } + + nr = 0; + list_for_each(list, &pmu->format) + nr++; + if (nr != r->nr_formats) { + pr_err("Unmatched number of event formats in %s: expect %d vs got %d\n", + pmu->name, r->nr_formats, nr); + return -1; + } + } + return 0; +} + +static void delete_result(void) +{ + for (int i = 0; i < nr_pmus; i++) + free(results[i].name); + free(results); + + results = NULL; + nr_pmus = 0; +} + +static int run_pmu_scan(void) +{ + struct stats stats; + struct timeval start, end, diff; + double time_average, time_stddev; + u64 runtime_us; + unsigned int i; + int ret; + + init_stats(&stats); + pr_info("Computing performance of sysfs PMU event scan for %u times\n", + iterations); + + if (save_result() < 0) { + pr_err("Failed to initialize PMU scan result\n"); + return -1; + } + + for (i = 0; i < iterations; i++) { + gettimeofday(&start, NULL); + perf_pmu__scan(NULL); + gettimeofday(&end, NULL); + + timersub(&end, &start, &diff); + runtime_us = diff.tv_sec * USEC_PER_SEC + diff.tv_usec; + update_stats(&stats, runtime_us); + + ret = check_result(); + perf_pmu__destroy(); + if (ret < 0) + break; + } + + time_average = avg_stats(&stats); + time_stddev = stddev_stats(&stats); + pr_info(" Average PMU scanning took: %.3f usec (+- %.3f usec)\n", + time_average, time_stddev); + + delete_result(); + return 0; +} + +int bench_pmu_scan(int argc, const char **argv) +{ + int err = 0; + + argc = parse_options(argc, argv, options, bench_usage, 0); + if (argc) { + usage_with_options(bench_usage, options); + exit(EXIT_FAILURE); + } + + err = run_pmu_scan(); + + return err; +} diff --git a/tools/perf/builtin-bench.c b/tools/perf/builtin-bench.c index d0fcc3cdc185..58f1cfe1eb34 100644 --- a/tools/perf/builtin-bench.c +++ b/tools/perf/builtin-bench.c @@ -92,6 +92,7 @@ static struct bench internals_benchmarks[] = { { "kallsyms-parse", "Benchmark kallsyms parsing", bench_kallsyms_parse }, { "inject-build-id", "Benchmark build-id injection", bench_inject_build_id }, { "evlist-open-close", "Benchmark evlist open and close", bench_evlist_open_close }, + { "pmu-scan", "Benchmark sysfs PMU info scanning", bench_pmu_scan }, { NULL, NULL, NULL } }; -- cgit v1.2.3-58-ga151 From e293a5e816c03b57f07078db60497933f3400b2a Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Fri, 31 Mar 2023 13:29:45 -0700 Subject: perf pmu: Use relative path for sysfs scan The PMU information is in the kernel sysfs so it needs to scan the directory to get the whole information like event aliases, formats and so on. During the traversal, it opens a lot of files and directories like below: dir = opendir("/sys/bus/event_source/devices"); while (dentry = readdir(dir)) { char buf[PATH_MAX]; snprintf(buf, sizeof(buf), "%s/%s", "/sys/bus/event_source/devices", dentry->d_name); fd = open(buf, O_RDONLY); ... } But this is not good since it needs to copy the string to build the absolute pathname, and it makes redundant pathname walk (from the /sys) unnecessarily. We can use openat(2) to open the file in the given directory. While it's not a problem ususally, it can be a problem when the kernel has contentions on the sysfs. Add a couple of new helper to return the file descriptor of PMU directory so that it can use it with relative paths. * perf_pmu__event_source_devices_fd() - returns a fd for the PMU root ("/sys/bus/event_source/devices") * perf_pmu__pathname_fd() - returns a fd for "/" under the PMU root Now the above code can be converted something like below: dirfd = perf_pmu__event_source_devices_fd(); dir = fdopendir(dirfd); while (dentry = readdir(dir)) { fd = openat(dirfd, dentry->d_name, O_RDONLY); ... } Signed-off-by: Namhyung Kim Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Leo Yan Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230331202949.810326-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/pmu.c | 9 ++- tools/perf/util/pmu.c | 161 ++++++++++++++++++++++++++++++------------------- tools/perf/util/pmu.h | 4 +- 3 files changed, 111 insertions(+), 63 deletions(-) (limited to 'tools') diff --git a/tools/perf/tests/pmu.c b/tools/perf/tests/pmu.c index 8507bd615e97..3cf25f883df7 100644 --- a/tools/perf/tests/pmu.c +++ b/tools/perf/tests/pmu.c @@ -3,6 +3,7 @@ #include "pmu.h" #include "tests.h" #include +#include #include #include #include @@ -149,10 +150,16 @@ static int test__pmu(struct test_suite *test __maybe_unused, int subtest __maybe do { struct perf_event_attr attr; + int fd; memset(&attr, 0, sizeof(attr)); - ret = perf_pmu__format_parse(format, &formats); + fd = open(format, O_DIRECTORY); + if (fd < 0) { + ret = fd; + break; + } + ret = perf_pmu__format_parse(fd, &formats); if (ret) break; diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index b112606f36ec..9fc6b8b5732b 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -62,38 +62,38 @@ extern FILE *perf_pmu_in; static bool hybrid_scanned; +static struct perf_pmu *perf_pmu__find2(int dirfd, const char *name); + /* * Parse & process all the sysfs attributes located under * the directory specified in 'dir' parameter. */ -int perf_pmu__format_parse(char *dir, struct list_head *head) +int perf_pmu__format_parse(int dirfd, struct list_head *head) { struct dirent *evt_ent; DIR *format_dir; int ret = 0; - format_dir = opendir(dir); + format_dir = fdopendir(dirfd); if (!format_dir) return -EINVAL; while (!ret && (evt_ent = readdir(format_dir))) { - char path[PATH_MAX]; char *name = evt_ent->d_name; - FILE *file; + int fd; if (!strcmp(name, ".") || !strcmp(name, "..")) continue; - snprintf(path, PATH_MAX, "%s/%s", dir, name); ret = -EINVAL; - file = fopen(path, "r"); - if (!file) + fd = openat(dirfd, name, O_RDONLY); + if (fd < 0) break; - perf_pmu_in = file; + perf_pmu_in = fdopen(fd, "r"); ret = perf_pmu_parse(head, name); - fclose(file); + fclose(perf_pmu_in); } closedir(format_dir); @@ -105,17 +105,16 @@ int perf_pmu__format_parse(char *dir, struct list_head *head) * located at: * /sys/bus/event_source/devices//format as sysfs group attributes. */ -static int pmu_format(const char *name, struct list_head *format) +static int pmu_format(int dirfd, const char *name, struct list_head *format) { - char path[PATH_MAX]; - - if (!perf_pmu__pathname_scnprintf(path, sizeof(path), name, "format")) - return -1; + int fd; - if (!file_available(path)) + fd = perf_pmu__pathname_fd(dirfd, name, "format", O_DIRECTORY); + if (fd < 0) return 0; - if (perf_pmu__format_parse(path, format)) + /* it'll close the fd */ + if (perf_pmu__format_parse(fd, format)) return -1; return 0; @@ -158,7 +157,7 @@ out: return ret; } -static int perf_pmu__parse_scale(struct perf_pmu_alias *alias, char *dir, char *name) +static int perf_pmu__parse_scale(struct perf_pmu_alias *alias, int dirfd, char *name) { struct stat st; ssize_t sret; @@ -166,9 +165,9 @@ static int perf_pmu__parse_scale(struct perf_pmu_alias *alias, char *dir, char * int fd, ret = -1; char path[PATH_MAX]; - scnprintf(path, PATH_MAX, "%s/%s.scale", dir, name); + scnprintf(path, PATH_MAX, "%s.scale", name); - fd = open(path, O_RDONLY); + fd = openat(dirfd, path, O_RDONLY); if (fd == -1) return -1; @@ -190,15 +189,15 @@ error: return ret; } -static int perf_pmu__parse_unit(struct perf_pmu_alias *alias, char *dir, char *name) +static int perf_pmu__parse_unit(struct perf_pmu_alias *alias, int dirfd, char *name) { char path[PATH_MAX]; ssize_t sret; int fd; - scnprintf(path, PATH_MAX, "%s/%s.unit", dir, name); + scnprintf(path, PATH_MAX, "%s.unit", name); - fd = open(path, O_RDONLY); + fd = openat(dirfd, path, O_RDONLY); if (fd == -1) return -1; @@ -221,14 +220,14 @@ error: } static int -perf_pmu__parse_per_pkg(struct perf_pmu_alias *alias, char *dir, char *name) +perf_pmu__parse_per_pkg(struct perf_pmu_alias *alias, int dirfd, char *name) { char path[PATH_MAX]; int fd; - scnprintf(path, PATH_MAX, "%s/%s.per-pkg", dir, name); + scnprintf(path, PATH_MAX, "%s.per-pkg", name); - fd = open(path, O_RDONLY); + fd = openat(dirfd, path, O_RDONLY); if (fd == -1) return -1; @@ -239,14 +238,14 @@ perf_pmu__parse_per_pkg(struct perf_pmu_alias *alias, char *dir, char *name) } static int perf_pmu__parse_snapshot(struct perf_pmu_alias *alias, - char *dir, char *name) + int dirfd, char *name) { char path[PATH_MAX]; int fd; - scnprintf(path, PATH_MAX, "%s/%s.snapshot", dir, name); + scnprintf(path, PATH_MAX, "%s.snapshot", name); - fd = open(path, O_RDONLY); + fd = openat(dirfd, path, O_RDONLY); if (fd == -1) return -1; @@ -332,7 +331,7 @@ static bool perf_pmu_merge_alias(struct perf_pmu_alias *newalias, return false; } -static int __perf_pmu__new_alias(struct list_head *list, char *dir, char *name, +static int __perf_pmu__new_alias(struct list_head *list, int dirfd, char *name, char *desc, char *val, const struct pmu_event *pe) { struct parse_events_term *term; @@ -391,14 +390,14 @@ static int __perf_pmu__new_alias(struct list_head *list, char *dir, char *name, } alias->name = strdup(name); - if (dir) { + if (dirfd >= 0) { /* * load unit name and scale if available */ - perf_pmu__parse_unit(alias, dir, name); - perf_pmu__parse_scale(alias, dir, name); - perf_pmu__parse_per_pkg(alias, dir, name); - perf_pmu__parse_snapshot(alias, dir, name); + perf_pmu__parse_unit(alias, dirfd, name); + perf_pmu__parse_scale(alias, dirfd, name); + perf_pmu__parse_per_pkg(alias, dirfd, name); + perf_pmu__parse_snapshot(alias, dirfd, name); } alias->desc = desc ? strdup(desc) : NULL; @@ -419,7 +418,7 @@ static int __perf_pmu__new_alias(struct list_head *list, char *dir, char *name, return 0; } -static int perf_pmu__new_alias(struct list_head *list, char *dir, char *name, FILE *file) +static int perf_pmu__new_alias(struct list_head *list, int dirfd, char *name, FILE *file) { char buf[256]; int ret; @@ -433,7 +432,7 @@ static int perf_pmu__new_alias(struct list_head *list, char *dir, char *name, FI /* Remove trailing newline from sysfs file */ strim(buf); - return __perf_pmu__new_alias(list, dir, name, NULL, buf, NULL); + return __perf_pmu__new_alias(list, dirfd, name, NULL, buf, NULL); } static inline bool pmu_alias_info_file(char *name) @@ -457,17 +456,17 @@ static inline bool pmu_alias_info_file(char *name) * Process all the sysfs attributes located under the directory * specified in 'dir' parameter. */ -static int pmu_aliases_parse(char *dir, struct list_head *head) +static int pmu_aliases_parse(int dirfd, struct list_head *head) { struct dirent *evt_ent; DIR *event_dir; + int fd; - event_dir = opendir(dir); + event_dir = fdopendir(dirfd); if (!event_dir) return -EINVAL; while ((evt_ent = readdir(event_dir))) { - char path[PATH_MAX]; char *name = evt_ent->d_name; FILE *file; @@ -480,15 +479,14 @@ static int pmu_aliases_parse(char *dir, struct list_head *head) if (pmu_alias_info_file(name)) continue; - scnprintf(path, PATH_MAX, "%s/%s", dir, name); - - file = fopen(path, "r"); + fd = openat(dirfd, name, O_RDONLY); + file = fdopen(fd, "r"); if (!file) { - pr_debug("Cannot open %s\n", path); + pr_debug("Cannot open %s\n", name); continue; } - if (perf_pmu__new_alias(head, dir, name, file) < 0) + if (perf_pmu__new_alias(head, dirfd, name, file) < 0) pr_debug("Cannot set up %s\n", name); fclose(file); } @@ -501,17 +499,16 @@ static int pmu_aliases_parse(char *dir, struct list_head *head) * Reading the pmu event aliases definition, which should be located at: * /sys/bus/event_source/devices//events as sysfs group attributes. */ -static int pmu_aliases(const char *name, struct list_head *head) +static int pmu_aliases(int dirfd, const char *name, struct list_head *head) { - char path[PATH_MAX]; - - if (!perf_pmu__pathname_scnprintf(path, sizeof(path), name, "events")) - return -1; + int fd; - if (!file_available(path)) + fd = perf_pmu__pathname_fd(dirfd, name, "events", O_DIRECTORY); + if (fd < 0) return 0; - if (pmu_aliases_parse(path, head)) + /* it'll close the fd */ + if (pmu_aliases_parse(fd, head)) return -1; return 0; @@ -544,14 +541,15 @@ static int pmu_alias_terms(struct perf_pmu_alias *alias, /* Add all pmus in sysfs to pmu list: */ static void pmu_read_sysfs(void) { - char path[PATH_MAX]; + int fd; DIR *dir; struct dirent *dent; - if (!perf_pmu__event_source_devices_scnprintf(path, sizeof(path))) + fd = perf_pmu__event_source_devices_fd(); + if (fd < 0) return; - dir = opendir(path); + dir = fdopendir(fd); if (!dir) return; @@ -559,7 +557,7 @@ static void pmu_read_sysfs(void) if (!strcmp(dent->d_name, ".") || !strcmp(dent->d_name, "..")) continue; /* add to static LIST_HEAD(pmus): */ - perf_pmu__find(dent->d_name); + perf_pmu__find2(fd, dent->d_name); } closedir(dir); @@ -763,7 +761,7 @@ static int pmu_add_cpu_aliases_map_callback(const struct pmu_event *pe, new_alias: /* need type casts to override 'const' */ - __perf_pmu__new_alias(data->head, NULL, (char *)pe->name, (char *)pe->desc, + __perf_pmu__new_alias(data->head, -1, (char *)pe->name, (char *)pe->desc, (char *)pe->event, pe); return 0; } @@ -814,7 +812,7 @@ static int pmu_add_sys_aliases_iter_fn(const struct pmu_event *pe, if (!strcmp(pmu->id, pe->compat) && pmu_uncore_alias_match(pe->pmu, pmu->name)) { - __perf_pmu__new_alias(idata->head, NULL, + __perf_pmu__new_alias(idata->head, -1, (char *)pe->name, (char *)pe->desc, (char *)pe->event, @@ -863,7 +861,7 @@ static int pmu_max_precise(struct perf_pmu *pmu) return max_precise; } -static struct perf_pmu *pmu_lookup(const char *lookup_name) +static struct perf_pmu *pmu_lookup(int dirfd, const char *lookup_name) { struct perf_pmu *pmu; LIST_HEAD(format); @@ -884,13 +882,13 @@ static struct perf_pmu *pmu_lookup(const char *lookup_name) * type value and format definitions. Load both right * now. */ - if (pmu_format(name, &format)) + if (pmu_format(dirfd, name, &format)) return NULL; /* * Check the aliases first to avoid unnecessary work. */ - if (pmu_aliases(name, &aliases)) + if (pmu_aliases(dirfd, name, &aliases)) return NULL; pmu = zalloc(sizeof(*pmu)); @@ -1024,6 +1022,27 @@ bool evsel__is_aux_event(const struct evsel *evsel) } struct perf_pmu *perf_pmu__find(const char *name) +{ + struct perf_pmu *pmu; + int dirfd; + + /* + * Once PMU is loaded it stays in the list, + * so we keep us from multiple reading/parsing + * the pmu format definitions. + */ + pmu = pmu_find(name); + if (pmu) + return pmu; + + dirfd = perf_pmu__event_source_devices_fd(); + pmu = pmu_lookup(dirfd, name); + close(dirfd); + + return pmu; +} + +static struct perf_pmu *perf_pmu__find2(int dirfd, const char *name) { struct perf_pmu *pmu; @@ -1036,7 +1055,7 @@ struct perf_pmu *perf_pmu__find(const char *name) if (pmu) return pmu; - return pmu_lookup(name); + return pmu_lookup(dirfd, name); } static struct perf_pmu_format * @@ -1938,6 +1957,18 @@ int perf_pmu__event_source_devices_scnprintf(char *pathname, size_t size) return scnprintf(pathname, size, "%s/bus/event_source/devices/", sysfs); } +int perf_pmu__event_source_devices_fd(void) +{ + char path[PATH_MAX]; + const char *sysfs = sysfs__mountpoint(); + + if (!sysfs) + return -1; + + scnprintf(path, sizeof(path), "%s/bus/event_source/devices/", sysfs); + return open(path, O_DIRECTORY); +} + /* * Fill 'buf' with the path to a file or folder in 'pmu_name' in * sysfs. For example if pmu_name = "cs_etm" and 'filename' = "format" @@ -1957,6 +1988,14 @@ int perf_pmu__pathname_scnprintf(char *buf, size_t size, return scnprintf(buf, size, "%s%s/%s", base_path, pmu_name, filename); } +int perf_pmu__pathname_fd(int dirfd, const char *pmu_name, const char *filename, int flags) +{ + char path[PATH_MAX]; + + scnprintf(path, sizeof(path), "%s/%s", pmu_name, filename); + return openat(dirfd, path, flags); +} + static void perf_pmu__delete(struct perf_pmu *pmu) { perf_pmu__del_formats(&pmu->format); diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h index 72fd5de334c0..751c7016e7b6 100644 --- a/tools/perf/util/pmu.h +++ b/tools/perf/util/pmu.h @@ -211,7 +211,7 @@ void perf_pmu_error(struct list_head *list, char *name, char const *msg); int perf_pmu__new_format(struct list_head *list, char *name, int config, unsigned long *bits); void perf_pmu__set_format(unsigned long *bits, long from, long to); -int perf_pmu__format_parse(char *dir, struct list_head *head); +int perf_pmu__format_parse(int dirfd, struct list_head *head); void perf_pmu__del_formats(struct list_head *formats); struct perf_pmu *perf_pmu__scan(struct perf_pmu *pmu); @@ -257,6 +257,8 @@ double perf_pmu__cpu_slots_per_cycle(void); int perf_pmu__event_source_devices_scnprintf(char *pathname, size_t size); int perf_pmu__pathname_scnprintf(char *buf, size_t size, const char *pmu_name, const char *filename); +int perf_pmu__event_source_devices_fd(void); +int perf_pmu__pathname_fd(int dirfd, const char *pmu_name, const char *filename, int flags); FILE *perf_pmu__open_file(struct perf_pmu *pmu, const char *name); void perf_pmu__destroy(void); -- cgit v1.2.3-58-ga151 From b39094d37d0c1f6399a1a1a24453ff48b4a0c7a6 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Fri, 31 Mar 2023 13:29:46 -0700 Subject: perf pmu: Use relative path in perf_pmu__caps_parse() Likewise, it needs to traverse the pmu/caps directory, let's use openat() with the dirfd instead of open() using the absolute path. Signed-off-by: Namhyung Kim Acked-by: Ian Rogers Link: https://lore.kernel.org/r/20230331202949.810326-2-namhyung@kernel.org Cc: Peter Zijlstra Cc: Adrian Hunter Cc: Arnaldo Carvalho de Melo Cc: Jiri Olsa Cc: Ingo Molnar Cc: Leo Yan Cc: Kan Liang Cc: LKML Cc: linux-perf-users@vger.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/pmu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 9fc6b8b5732b..0c1d87f10b23 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -1804,6 +1804,7 @@ int perf_pmu__caps_parse(struct perf_pmu *pmu) char caps_path[PATH_MAX]; DIR *caps_dir; struct dirent *evt_ent; + int caps_fd; if (pmu->caps_initialized) return pmu->nr_caps; @@ -1822,18 +1823,19 @@ int perf_pmu__caps_parse(struct perf_pmu *pmu) if (!caps_dir) return -EINVAL; + caps_fd = dirfd(caps_dir); + while ((evt_ent = readdir(caps_dir)) != NULL) { - char path[PATH_MAX + NAME_MAX + 1]; char *name = evt_ent->d_name; char value[128]; FILE *file; + int fd; if (!strcmp(name, ".") || !strcmp(name, "..")) continue; - snprintf(path, sizeof(path), "%s/%s", caps_path, name); - - file = fopen(path, "r"); + fd = openat(caps_fd, name, O_RDONLY); + file = fdopen(fd, "r"); if (!file) continue; -- cgit v1.2.3-58-ga151 From 463786658d234df43ad1d9dfcf8aba25176d071c Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Fri, 31 Mar 2023 13:29:47 -0700 Subject: perf pmu: Use relative path in setup_pmu_alias_list() Likewise, x86 needs to traverse the PMU list to build alias. Let's use the new helpers to use relative paths. Signed-off-by: Namhyung Kim Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Leo Yan Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230331202949.810326-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/x86/util/pmu.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) (limited to 'tools') diff --git a/tools/perf/arch/x86/util/pmu.c b/tools/perf/arch/x86/util/pmu.c index f73b80dcd8bd..3c0de3370d7e 100644 --- a/tools/perf/arch/x86/util/pmu.c +++ b/tools/perf/arch/x86/util/pmu.c @@ -71,7 +71,7 @@ out_delete: static int setup_pmu_alias_list(void) { - char path[PATH_MAX]; + int fd, dirfd; DIR *dir; struct dirent *dent; struct pmu_alias *pmu_alias; @@ -79,10 +79,11 @@ static int setup_pmu_alias_list(void) FILE *file; int ret = -ENOMEM; - if (!perf_pmu__event_source_devices_scnprintf(path, sizeof(path))) + dirfd = perf_pmu__event_source_devices_fd(); + if (dirfd < 0) return -1; - dir = opendir(path); + dir = fdopendir(dirfd); if (!dir) return -errno; @@ -91,11 +92,11 @@ static int setup_pmu_alias_list(void) !strcmp(dent->d_name, "..")) continue; - perf_pmu__pathname_scnprintf(path, sizeof(path), dent->d_name, "alias"); - if (!file_available(path)) + fd = perf_pmu__pathname_fd(dirfd, dent->d_name, "alias", O_RDONLY); + if (fd < 0) continue; - file = fopen(path, "r"); + file = fdopen(fd, "r"); if (!file) continue; -- cgit v1.2.3-58-ga151 From 3a69672e881afc1dcc8ed60272197af8958b5404 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Fri, 31 Mar 2023 13:29:48 -0700 Subject: perf pmu: Add perf_pmu__{open,scan}_file_at() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These two helpers will also use openat() to reduce the overhead with relative pathnames. Convert other functions in pmu_lookup() to use the new helpers. Committer testing: Before: ⬢[acme@toolbox perf-tools-next]$ perf bench internals pmu-scan # Running 'internals/pmu-scan' benchmark: Computing performance of sysfs PMU event scan for 100 times Average PMU scanning took: 2729.040 usec (+- 7.117 usec) ⬢[acme@toolbox perf-tools-next]$ After: ⬢[acme@toolbox perf-tools-next]$ perf bench internals pmu-scan # Running 'internals/pmu-scan' benchmark: Computing performance of sysfs PMU event scan for 100 times Average PMU scanning took: 2419.870 usec (+- 9.057 usec) ⬢[acme@toolbox perf-tools-next]$ Signed-off-by: Namhyung Kim Acked-by: Ian Rogers Tested-by: Arnaldo Carvalho de Melo Cc: Adrian Hunter Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Leo Yan Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230331202949.810326-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/pmu.c | 57 ++++++++++++++++++++++++++++++++++++++++----------- tools/perf/util/pmu.h | 6 +++++- 2 files changed, 50 insertions(+), 13 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 0c1d87f10b23..78a407b42ad1 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -567,7 +567,7 @@ static void pmu_read_sysfs(void) * Uncore PMUs have a "cpumask" file under sysfs. CPU PMUs (e.g. on arm/arm64) * may have a "cpus" file. */ -static struct perf_cpu_map *pmu_cpumask(const char *name) +static struct perf_cpu_map *pmu_cpumask(int dirfd, const char *name) { struct perf_cpu_map *cpus; const char *templates[] = { @@ -582,10 +582,11 @@ static struct perf_cpu_map *pmu_cpumask(const char *name) strlcpy(pmu_name, name, sizeof(pmu_name)); for (template = templates; *template; template++) { - file = perf_pmu__open_file(&pmu, *template); + file = perf_pmu__open_file_at(&pmu, dirfd, *template); if (!file) continue; cpus = perf_cpu_map__read(file); + fclose(file); if (cpus) return cpus; } @@ -593,15 +594,19 @@ static struct perf_cpu_map *pmu_cpumask(const char *name) return NULL; } -static bool pmu_is_uncore(const char *name) +static bool pmu_is_uncore(int dirfd, const char *name) { - char path[PATH_MAX]; + int fd; if (perf_pmu__hybrid_mounted(name)) return false; - perf_pmu__pathname_scnprintf(path, sizeof(path), name, "cpumask"); - return file_available(path); + fd = perf_pmu__pathname_fd(dirfd, name, "cpumask", O_PATH); + if (fd < 0) + return false; + + close(fd); + return true; } static char *pmu_id(const char *name) @@ -853,11 +858,11 @@ pmu_find_alias_name(const char *name __maybe_unused) return NULL; } -static int pmu_max_precise(struct perf_pmu *pmu) +static int pmu_max_precise(int dirfd, struct perf_pmu *pmu) { int max_precise = -1; - perf_pmu__scan_file(pmu, "caps/max_precise", "%d", &max_precise); + perf_pmu__scan_file_at(pmu, dirfd, "caps/max_precise", "%d", &max_precise); return max_precise; } @@ -895,14 +900,14 @@ static struct perf_pmu *pmu_lookup(int dirfd, const char *lookup_name) if (!pmu) return NULL; - pmu->cpus = pmu_cpumask(name); + pmu->cpus = pmu_cpumask(dirfd, name); pmu->name = strdup(name); if (!pmu->name) goto err; /* Read type, and ensure that type value is successfully assigned (return 1) */ - if (perf_pmu__scan_file(pmu, "type", "%u", &type) != 1) + if (perf_pmu__scan_file_at(pmu, dirfd, "type", "%u", &type) != 1) goto err; alias_name = pmu_find_alias_name(name); @@ -913,10 +918,10 @@ static struct perf_pmu *pmu_lookup(int dirfd, const char *lookup_name) } pmu->type = type; - pmu->is_uncore = pmu_is_uncore(name); + pmu->is_uncore = pmu_is_uncore(dirfd, name); if (pmu->is_uncore) pmu->id = pmu_id(name); - pmu->max_precise = pmu_max_precise(pmu); + pmu->max_precise = pmu_max_precise(dirfd, pmu); pmu_add_cpu_aliases(&aliases, pmu); pmu_add_sys_aliases(&aliases, pmu); @@ -1730,6 +1735,17 @@ FILE *perf_pmu__open_file(struct perf_pmu *pmu, const char *name) return fopen(path, "r"); } +FILE *perf_pmu__open_file_at(struct perf_pmu *pmu, int dirfd, const char *name) +{ + int fd; + + fd = perf_pmu__pathname_fd(dirfd, pmu->name, name, O_RDONLY); + if (fd < 0) + return NULL; + + return fdopen(fd, "r"); +} + int perf_pmu__scan_file(struct perf_pmu *pmu, const char *name, const char *fmt, ...) { @@ -1747,6 +1763,23 @@ int perf_pmu__scan_file(struct perf_pmu *pmu, const char *name, const char *fmt, return ret; } +int perf_pmu__scan_file_at(struct perf_pmu *pmu, int dirfd, const char *name, + const char *fmt, ...) +{ + va_list args; + FILE *file; + int ret = EOF; + + va_start(args, fmt); + file = perf_pmu__open_file_at(pmu, dirfd, name); + if (file) { + ret = vfscanf(file, fmt, args); + fclose(file); + } + va_end(args); + return ret; +} + bool perf_pmu__file_exists(struct perf_pmu *pmu, const char *name) { char path[PATH_MAX]; diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h index 751c7016e7b6..32c3a75bca0e 100644 --- a/tools/perf/util/pmu.h +++ b/tools/perf/util/pmu.h @@ -220,7 +220,12 @@ bool is_pmu_core(const char *name); void print_pmu_events(const struct print_callbacks *print_cb, void *print_state); bool pmu_have_event(const char *pname, const char *name); +FILE *perf_pmu__open_file(struct perf_pmu *pmu, const char *name); +FILE *perf_pmu__open_file_at(struct perf_pmu *pmu, int dirfd, const char *name); + int perf_pmu__scan_file(struct perf_pmu *pmu, const char *name, const char *fmt, ...) __scanf(3, 4); +int perf_pmu__scan_file_at(struct perf_pmu *pmu, int dirfd, const char *name, + const char *fmt, ...) __scanf(4, 5); bool perf_pmu__file_exists(struct perf_pmu *pmu, const char *name); @@ -259,7 +264,6 @@ int perf_pmu__pathname_scnprintf(char *buf, size_t size, const char *pmu_name, const char *filename); int perf_pmu__event_source_devices_fd(void); int perf_pmu__pathname_fd(int dirfd, const char *pmu_name, const char *filename, int flags); -FILE *perf_pmu__open_file(struct perf_pmu *pmu, const char *name); void perf_pmu__destroy(void); -- cgit v1.2.3-58-ga151 From 98b7ce0ed8f7a93ac0f6e0a0576c70093b669a71 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Fri, 31 Mar 2023 13:29:49 -0700 Subject: perf intel-pt: Use perf_pmu__scan_file_at() if possible Intel-PT calls perf_pmu__scan_file() a lot, let's use relative address when it accesses multiple files at one place. Signed-off-by: Namhyung Kim Acked-by: Adrian Hunter Acked-by: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Leo Yan Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230331202949.810326-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/x86/util/intel-pt.c | 52 +++++++++++++++++++++++-------------- 1 file changed, 32 insertions(+), 20 deletions(-) (limited to 'tools') diff --git a/tools/perf/arch/x86/util/intel-pt.c b/tools/perf/arch/x86/util/intel-pt.c index 1e39a034cee9..2cff11de9d8a 100644 --- a/tools/perf/arch/x86/util/intel-pt.c +++ b/tools/perf/arch/x86/util/intel-pt.c @@ -194,16 +194,19 @@ static u64 intel_pt_default_config(struct perf_pmu *intel_pt_pmu) int pos = 0; u64 config; char c; + int dirfd; + + dirfd = perf_pmu__event_source_devices_fd(); pos += scnprintf(buf + pos, sizeof(buf) - pos, "tsc"); - if (perf_pmu__scan_file(intel_pt_pmu, "caps/mtc", "%d", - &mtc) != 1) + if (perf_pmu__scan_file_at(intel_pt_pmu, dirfd, "caps/mtc", "%d", + &mtc) != 1) mtc = 1; if (mtc) { - if (perf_pmu__scan_file(intel_pt_pmu, "caps/mtc_periods", "%x", - &mtc_periods) != 1) + if (perf_pmu__scan_file_at(intel_pt_pmu, dirfd, "caps/mtc_periods", "%x", + &mtc_periods) != 1) mtc_periods = 0; if (mtc_periods) { mtc_period = intel_pt_pick_bit(mtc_periods, 3); @@ -212,13 +215,13 @@ static u64 intel_pt_default_config(struct perf_pmu *intel_pt_pmu) } } - if (perf_pmu__scan_file(intel_pt_pmu, "caps/psb_cyc", "%d", - &psb_cyc) != 1) + if (perf_pmu__scan_file_at(intel_pt_pmu, dirfd, "caps/psb_cyc", "%d", + &psb_cyc) != 1) psb_cyc = 1; if (psb_cyc && mtc_periods) { - if (perf_pmu__scan_file(intel_pt_pmu, "caps/psb_periods", "%x", - &psb_periods) != 1) + if (perf_pmu__scan_file_at(intel_pt_pmu, dirfd, "caps/psb_periods", "%x", + &psb_periods) != 1) psb_periods = 0; if (psb_periods) { psb_period = intel_pt_pick_bit(psb_periods, 3); @@ -227,8 +230,8 @@ static u64 intel_pt_default_config(struct perf_pmu *intel_pt_pmu) } } - if (perf_pmu__scan_file(intel_pt_pmu, "format/pt", "%c", &c) == 1 && - perf_pmu__scan_file(intel_pt_pmu, "format/branch", "%c", &c) == 1) + if (perf_pmu__scan_file_at(intel_pt_pmu, dirfd, "format/pt", "%c", &c) == 1 && + perf_pmu__scan_file_at(intel_pt_pmu, dirfd, "format/branch", "%c", &c) == 1) pos += scnprintf(buf + pos, sizeof(buf) - pos, ",pt,branch"); pr_debug2("%s default config: %s\n", intel_pt_pmu->name, buf); @@ -236,6 +239,7 @@ static u64 intel_pt_default_config(struct perf_pmu *intel_pt_pmu) intel_pt_parse_terms(intel_pt_pmu->name, &intel_pt_pmu->format, buf, &config); + close(dirfd); return config; } @@ -488,7 +492,7 @@ static void intel_pt_valid_str(char *str, size_t len, u64 valid) } } -static int intel_pt_val_config_term(struct perf_pmu *intel_pt_pmu, +static int intel_pt_val_config_term(struct perf_pmu *intel_pt_pmu, int dirfd, const char *caps, const char *name, const char *supported, u64 config) { @@ -498,11 +502,11 @@ static int intel_pt_val_config_term(struct perf_pmu *intel_pt_pmu, u64 bits; int ok; - if (perf_pmu__scan_file(intel_pt_pmu, caps, "%llx", &valid) != 1) + if (perf_pmu__scan_file_at(intel_pt_pmu, dirfd, caps, "%llx", &valid) != 1) valid = 0; if (supported && - perf_pmu__scan_file(intel_pt_pmu, supported, "%d", &ok) == 1 && !ok) + perf_pmu__scan_file_at(intel_pt_pmu, dirfd, supported, "%d", &ok) == 1 && !ok) valid = 0; valid |= 1; @@ -531,37 +535,45 @@ out_err: static int intel_pt_validate_config(struct perf_pmu *intel_pt_pmu, struct evsel *evsel) { - int err; + int err, dirfd; char c; if (!evsel) return 0; + dirfd = perf_pmu__event_source_devices_fd(); + if (dirfd < 0) + return dirfd; + /* * If supported, force pass-through config term (pt=1) even if user * sets pt=0, which avoids senseless kernel errors. */ - if (perf_pmu__scan_file(intel_pt_pmu, "format/pt", "%c", &c) == 1 && + if (perf_pmu__scan_file_at(intel_pt_pmu, dirfd, "format/pt", "%c", &c) == 1 && !(evsel->core.attr.config & 1)) { pr_warning("pt=0 doesn't make sense, forcing pt=1\n"); evsel->core.attr.config |= 1; } - err = intel_pt_val_config_term(intel_pt_pmu, "caps/cycle_thresholds", + err = intel_pt_val_config_term(intel_pt_pmu, dirfd, "caps/cycle_thresholds", "cyc_thresh", "caps/psb_cyc", evsel->core.attr.config); if (err) - return err; + goto out; - err = intel_pt_val_config_term(intel_pt_pmu, "caps/mtc_periods", + err = intel_pt_val_config_term(intel_pt_pmu, dirfd, "caps/mtc_periods", "mtc_period", "caps/mtc", evsel->core.attr.config); if (err) - return err; + goto out; - return intel_pt_val_config_term(intel_pt_pmu, "caps/psb_periods", + err = intel_pt_val_config_term(intel_pt_pmu, dirfd, "caps/psb_periods", "psb_period", "caps/psb_cyc", evsel->core.attr.config); + +out: + close(dirfd); + return err; } static void intel_pt_config_sample_mode(struct perf_pmu *intel_pt_pmu, -- cgit v1.2.3-58-ga151 From c9dc580c43b8d83de0c14158e826f79e41098822 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 3 Apr 2023 11:40:30 -0700 Subject: tools api: Add io__getline Reads a line to allocated memory up to a newline following the getline API. Committer notes: It also adds this new function to the 'api io' 'perf test' entry: $ perf test "api io" 64: Test api io : Ok $ Signed-off-by: Ian Rogers Tested-by: Arnaldo Carvalho de Melo Acked-by: Namhyung Kim Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Peter Zijlstra Cc: Tom Rix Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20230403184033.1836023-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/lib/api/io.h | 45 +++++++++++++++++++++++++++++++++++++++++++++ tools/perf/tests/api-io.c | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 81 insertions(+) (limited to 'tools') diff --git a/tools/lib/api/io.h b/tools/lib/api/io.h index 777c20f6b604..d5e8cf0dada0 100644 --- a/tools/lib/api/io.h +++ b/tools/lib/api/io.h @@ -7,7 +7,9 @@ #ifndef __API_IO__ #define __API_IO__ +#include #include +#include #include struct io { @@ -112,4 +114,47 @@ static inline int io__get_dec(struct io *io, __u64 *dec) } } +/* Read up to and including the first newline following the pattern of getline. */ +static inline ssize_t io__getline(struct io *io, char **line_out, size_t *line_len_out) +{ + char buf[128]; + int buf_pos = 0; + char *line = NULL, *temp; + size_t line_len = 0; + int ch = 0; + + /* TODO: reuse previously allocated memory. */ + free(*line_out); + while (ch != '\n') { + ch = io__get_char(io); + + if (ch < 0) + break; + + if (buf_pos == sizeof(buf)) { + temp = realloc(line, line_len + sizeof(buf)); + if (!temp) + goto err_out; + line = temp; + memcpy(&line[line_len], buf, sizeof(buf)); + line_len += sizeof(buf); + buf_pos = 0; + } + buf[buf_pos++] = (char)ch; + } + temp = realloc(line, line_len + buf_pos + 1); + if (!temp) + goto err_out; + line = temp; + memcpy(&line[line_len], buf, buf_pos); + line[line_len + buf_pos] = '\0'; + line_len += buf_pos; + *line_out = line; + *line_len_out = line_len; + return line_len; +err_out: + free(line); + return -ENOMEM; +} + #endif /* __API_IO__ */ diff --git a/tools/perf/tests/api-io.c b/tools/perf/tests/api-io.c index e91cf2c127f1..6aea84ca6673 100644 --- a/tools/perf/tests/api-io.c +++ b/tools/perf/tests/api-io.c @@ -289,6 +289,40 @@ static int test_get_dec(void) return ret; } +static int test_get_line(void) +{ + char path[PATH_MAX]; + struct io io; + char test_string[1024]; + char *line = NULL; + size_t i, line_len = 0; + size_t buf_size = 128; + int ret = 0; + + for (i = 0; i < 512; i++) + test_string[i] = 'a'; + test_string[512] = '\n'; + for (i = 513; i < 1023; i++) + test_string[i] = 'b'; + test_string[1023] = '\0'; + + if (setup_test(path, test_string, buf_size, &io)) + return -1; + + EXPECT_EQUAL((int)io__getline(&io, &line, &line_len), 513); + EXPECT_EQUAL((int)strlen(line), 513); + for (i = 0; i < 512; i++) + EXPECT_EQUAL(line[i], 'a'); + EXPECT_EQUAL(line[512], '\n'); + EXPECT_EQUAL((int)io__getline(&io, &line, &line_len), 510); + for (i = 0; i < 510; i++) + EXPECT_EQUAL(line[i], 'b'); + + free(line); + cleanup_test(path, &io); + return ret; +} + static int test__api_io(struct test_suite *test __maybe_unused, int subtest __maybe_unused) { @@ -300,6 +334,8 @@ static int test__api_io(struct test_suite *test __maybe_unused, ret = TEST_FAIL; if (test_get_dec()) ret = TEST_FAIL; + if (test_get_line()) + ret = TEST_FAIL; return ret; } -- cgit v1.2.3-58-ga151 From b3801e7912316c7a100a05de152a80df4121871e Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 3 Apr 2023 11:40:31 -0700 Subject: perf srcline: Simplify addr2line subprocess Don't wrap stdin and stdout of subprocess with streams, use the api/io library for buffering. Signed-off-by: Ian Rogers Acked-by: Namhyung Kim Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Peter Zijlstra Cc: Tom Rix Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20230403184033.1836023-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/srcline.c | 103 +++++++++++++++++----------------------------- 1 file changed, 38 insertions(+), 65 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/srcline.c b/tools/perf/util/srcline.c index f0a96a834e4b..5339ab4c5e12 100644 --- a/tools/perf/util/srcline.c +++ b/tools/perf/util/srcline.c @@ -10,6 +10,8 @@ #include #include +#include + #include "util/dso.h" #include "util/debug.h" #include "util/callchain.h" @@ -366,12 +368,6 @@ void dso__free_a2l(struct dso *dso) #else /* HAVE_LIBBFD_SUPPORT */ -struct a2l_subprocess { - struct child_process addr2line; - FILE *to_child; - FILE *from_child; -}; - static int filename_split(char *filename, unsigned int *line_nr) { char *sep; @@ -393,28 +389,18 @@ static int filename_split(char *filename, unsigned int *line_nr) return 0; } -static void addr2line_subprocess_cleanup(struct a2l_subprocess *a2l) +static void addr2line_subprocess_cleanup(struct child_process *a2l) { - if (a2l->addr2line.pid != -1) { - kill(a2l->addr2line.pid, SIGKILL); - finish_command(&a2l->addr2line); /* ignore result, we don't care */ - a2l->addr2line.pid = -1; - } - - if (a2l->to_child != NULL) { - fclose(a2l->to_child); - a2l->to_child = NULL; - } - - if (a2l->from_child != NULL) { - fclose(a2l->from_child); - a2l->from_child = NULL; + if (a2l->pid != -1) { + kill(a2l->pid, SIGKILL); + finish_command(a2l); /* ignore result, we don't care */ + a2l->pid = -1; } free(a2l); } -static struct a2l_subprocess *addr2line_subprocess_init(const char *addr2line_path, +static struct child_process *addr2line_subprocess_init(const char *addr2line_path, const char *binary_path) { const char *argv[] = { @@ -422,54 +408,34 @@ static struct a2l_subprocess *addr2line_subprocess_init(const char *addr2line_pa "-e", binary_path, "-i", "-f", NULL }; - struct a2l_subprocess *a2l = zalloc(sizeof(*a2l)); + struct child_process *a2l = zalloc(sizeof(*a2l)); int start_command_status = 0; - if (a2l == NULL) - goto out; - - a2l->to_child = NULL; - a2l->from_child = NULL; + if (a2l == NULL) { + pr_err("Failed to allocate memory for addr2line"); + return NULL; + } - a2l->addr2line.pid = -1; - a2l->addr2line.in = -1; - a2l->addr2line.out = -1; - a2l->addr2line.no_stderr = 1; + a2l->pid = -1; + a2l->in = -1; + a2l->out = -1; + a2l->no_stderr = 1; - a2l->addr2line.argv = argv; - start_command_status = start_command(&a2l->addr2line); - a2l->addr2line.argv = NULL; /* it's not used after start_command; avoid dangling pointers */ + a2l->argv = argv; + start_command_status = start_command(a2l); + a2l->argv = NULL; /* it's not used after start_command; avoid dangling pointers */ if (start_command_status != 0) { pr_warning("could not start addr2line (%s) for %s: start_command return code %d\n", addr2line_path, binary_path, start_command_status); - goto out; - } - - a2l->to_child = fdopen(a2l->addr2line.in, "w"); - if (a2l->to_child == NULL) { - pr_warning("could not open write-stream to addr2line (%s) of %s\n", - addr2line_path, binary_path); - goto out; - } - - a2l->from_child = fdopen(a2l->addr2line.out, "r"); - if (a2l->from_child == NULL) { - pr_warning("could not open read-stream from addr2line (%s) of %s\n", - addr2line_path, binary_path); - goto out; + addr2line_subprocess_cleanup(a2l); + return NULL; } return a2l; - -out: - if (a2l) - addr2line_subprocess_cleanup(a2l); - - return NULL; } -static int read_addr2line_record(struct a2l_subprocess *a2l, +static int read_addr2line_record(struct io *io, char **function, char **filename, unsigned int *line_nr) @@ -494,7 +460,7 @@ static int read_addr2line_record(struct a2l_subprocess *a2l, if (line_nr != NULL) *line_nr = 0; - if (getline(&line, &line_len, a2l->from_child) < 0 || !line_len) + if (io__getline(io, &line, &line_len) < 0 || !line_len) goto error; if (function != NULL) *function = strdup(strim(line)); @@ -502,7 +468,7 @@ static int read_addr2line_record(struct a2l_subprocess *a2l, zfree(&line); line_len = 0; - if (getline(&line, &line_len, a2l->from_child) < 0 || !line_len) + if (io__getline(io, &line, &line_len) < 0 || !line_len) goto error; if (filename_split(line, line_nr == NULL ? &dummy_line_nr : line_nr) == 0) { @@ -546,13 +512,17 @@ static int addr2line(const char *dso_name, u64 addr, struct inline_node *node, struct symbol *sym __maybe_unused) { - struct a2l_subprocess *a2l = dso->a2l; + struct child_process *a2l = dso->a2l; char *record_function = NULL; char *record_filename = NULL; unsigned int record_line_nr = 0; int record_status = -1; int ret = 0; size_t inline_count = 0; + int len; + char buf[128]; + ssize_t written; + struct io io; if (!a2l) { if (!filename__has_section(dso_name, ".debug_line")) @@ -578,13 +548,16 @@ static int addr2line(const char *dso_name, u64 addr, * though, because it may be genuinely unknown, in which case we'll get two sets of * "??"/"??:0" lines. */ - if (fprintf(a2l->to_child, "%016"PRIx64"\n,\n", addr) < 0 || fflush(a2l->to_child) != 0) { + len = snprintf(buf, sizeof(buf), "%016"PRIx64"\n,\n", addr); + written = len > 0 ? write(a2l->in, buf, len) : -1; + if (written != len) { if (!symbol_conf.disable_add2line_warn) pr_warning("%s %s: could not send request\n", __func__, dso_name); goto out; } + io__init(&io, a2l->out, buf, sizeof(buf)); - switch (read_addr2line_record(a2l, &record_function, &record_filename, &record_line_nr)) { + switch (read_addr2line_record(&io, &record_function, &record_filename, &record_line_nr)) { case -1: if (!symbol_conf.disable_add2line_warn) pr_warning("%s %s: could not read first record\n", __func__, dso_name); @@ -594,7 +567,7 @@ static int addr2line(const char *dso_name, u64 addr, * The first record was invalid, so return failure, but first read another * record, since we asked a junk question and have to clear the answer out. */ - switch (read_addr2line_record(a2l, NULL, NULL, NULL)) { + switch (read_addr2line_record(&io, NULL, NULL, NULL)) { case -1: if (!symbol_conf.disable_add2line_warn) pr_warning("%s %s: could not read delimiter record\n", @@ -632,7 +605,7 @@ static int addr2line(const char *dso_name, u64 addr, } /* We have to read the records even if we don't care about the inline info. */ - while ((record_status = read_addr2line_record(a2l, + while ((record_status = read_addr2line_record(&io, &record_function, &record_filename, &record_line_nr)) == 1) { @@ -656,7 +629,7 @@ out: void dso__free_a2l(struct dso *dso) { - struct a2l_subprocess *a2l = dso->a2l; + struct child_process *a2l = dso->a2l; if (!a2l) return; -- cgit v1.2.3-58-ga151 From 2c4b928074839425b64155cb3f6d4e0e5e67e835 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 3 Apr 2023 11:40:32 -0700 Subject: perf srcline: Support for llvm-addr2line The sentinel value differs for llvm-addr2line. Configure this once and then detect when reading records. Signed-off-by: Ian Rogers Acked-by: Namhyung Kim Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Peter Zijlstra Cc: Tom Rix Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20230403184033.1836023-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/srcline.c | 74 ++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 67 insertions(+), 7 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/srcline.c b/tools/perf/util/srcline.c index 5339ab4c5e12..f4fcdada821b 100644 --- a/tools/perf/util/srcline.c +++ b/tools/perf/util/srcline.c @@ -435,7 +435,50 @@ static struct child_process *addr2line_subprocess_init(const char *addr2line_pat return a2l; } +enum a2l_style { + BROKEN, + GNU_BINUTILS, + LLVM, +}; + +static enum a2l_style addr2line_configure(struct child_process *a2l) +{ + static bool cached; + static enum a2l_style style; + + if (!cached) { + char buf[128]; + struct io io; + int ch; + + if (write(a2l->in, ",\n", 2) != 2) + return BROKEN; + + io__init(&io, a2l->out, buf, sizeof(buf)); + ch = io__get_char(&io); + if (ch == ',') { + style = LLVM; + cached = true; + } else if (ch == '?') { + style = GNU_BINUTILS; + cached = true; + } else { + style = BROKEN; + } + do { + ch = io__get_char(&io); + } while (ch > 0 && ch != '\n'); + if (style == GNU_BINUTILS) { + do { + ch = io__get_char(&io); + } while (ch > 0 && ch != '\n'); + } + } + return style; +} + static int read_addr2line_record(struct io *io, + enum a2l_style style, char **function, char **filename, unsigned int *line_nr) @@ -462,6 +505,12 @@ static int read_addr2line_record(struct io *io, if (io__getline(io, &line, &line_len) < 0 || !line_len) goto error; + + if (style == LLVM && line_len == 2 && line[0] == ',') { + zfree(&line); + return 0; + } + if (function != NULL) *function = strdup(strim(line)); @@ -471,7 +520,8 @@ static int read_addr2line_record(struct io *io, if (io__getline(io, &line, &line_len) < 0 || !line_len) goto error; - if (filename_split(line, line_nr == NULL ? &dummy_line_nr : line_nr) == 0) { + if (filename_split(line, line_nr == NULL ? &dummy_line_nr : line_nr) == 0 && + style == GNU_BINUTILS) { ret = 0; goto error; } @@ -523,6 +573,7 @@ static int addr2line(const char *dso_name, u64 addr, char buf[128]; ssize_t written; struct io io; + enum a2l_style a2l_style; if (!a2l) { if (!filename__has_section(dso_name, ".debug_line")) @@ -538,15 +589,22 @@ static int addr2line(const char *dso_name, u64 addr, pr_warning("%s %s: addr2line_subprocess_init failed\n", __func__, dso_name); goto out; } + a2l_style = addr2line_configure(a2l); + if (a2l_style == BROKEN) { + if (!symbol_conf.disable_add2line_warn) + pr_warning("%s: addr2line configuration failed\n", __func__); + goto out; + } /* * Send our request and then *deliberately* send something that can't be interpreted as * a valid address to ask addr2line about (namely, ","). This causes addr2line to first * write out the answer to our request, in an unbounded/unknown number of records, and - * then to write out the lines "??" and "??:0", so that we can detect when it has - * finished giving us anything useful. We have to be careful about the first record, - * though, because it may be genuinely unknown, in which case we'll get two sets of - * "??"/"??:0" lines. + * then to write out the lines "??" and "??:0", for GNU binutils, or "," for + * llvm-addr2line, so that we can detect when it has finished giving us anything + * useful. With GNU binutils, we have to be careful about the first record, though, + * because it may be genuinely unknown, in which case we'll get two sets of "??"/"??:0" + * lines. */ len = snprintf(buf, sizeof(buf), "%016"PRIx64"\n,\n", addr); written = len > 0 ? write(a2l->in, buf, len) : -1; @@ -557,7 +615,8 @@ static int addr2line(const char *dso_name, u64 addr, } io__init(&io, a2l->out, buf, sizeof(buf)); - switch (read_addr2line_record(&io, &record_function, &record_filename, &record_line_nr)) { + switch (read_addr2line_record(&io, a2l_style, + &record_function, &record_filename, &record_line_nr)) { case -1: if (!symbol_conf.disable_add2line_warn) pr_warning("%s %s: could not read first record\n", __func__, dso_name); @@ -567,7 +626,7 @@ static int addr2line(const char *dso_name, u64 addr, * The first record was invalid, so return failure, but first read another * record, since we asked a junk question and have to clear the answer out. */ - switch (read_addr2line_record(&io, NULL, NULL, NULL)) { + switch (read_addr2line_record(&io, a2l_style, NULL, NULL, NULL)) { case -1: if (!symbol_conf.disable_add2line_warn) pr_warning("%s %s: could not read delimiter record\n", @@ -606,6 +665,7 @@ static int addr2line(const char *dso_name, u64 addr, /* We have to read the records even if we don't care about the inline info. */ while ((record_status = read_addr2line_record(&io, + a2l_style, &record_function, &record_filename, &record_line_nr)) == 1) { -- cgit v1.2.3-58-ga151 From 75a616c6d332342291c45b0381abe00bd597036c Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 3 Apr 2023 11:40:33 -0700 Subject: perf srcline: Avoid addr2line SIGPIPEs Ignore SIGPIPEs when addr2line is configured. Signed-off-by: Ian Rogers Acked-by: Namhyung Kim Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Peter Zijlstra Cc: Tom Rix Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20230403184033.1836023-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/srcline.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'tools') diff --git a/tools/perf/util/srcline.c b/tools/perf/util/srcline.c index f4fcdada821b..cfca03abd6f8 100644 --- a/tools/perf/util/srcline.c +++ b/tools/perf/util/srcline.c @@ -473,6 +473,8 @@ static enum a2l_style addr2line_configure(struct child_process *a2l) ch = io__get_char(&io); } while (ch > 0 && ch != '\n'); } + /* Ignore SIGPIPE in the event addr2line exits. */ + signal(SIGPIPE, SIG_IGN); } return style; } -- cgit v1.2.3-58-ga151 From 3ad45105dc44ca8419441032760c04d81504c0e6 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 3 Apr 2023 14:10:20 -0700 Subject: perf build: Allow C++ demangle without libelf The cxa demangle support isn't dependent on libelf and so we no longer need to disable demangling if libelf isn't present. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andrii Nakryiko Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230403211021.1892231-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Makefile.config | 1 - 1 file changed, 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index fd1be9596d12..16bea51f0bcd 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -412,7 +412,6 @@ endif ifdef NO_LIBELF NO_DWARF := 1 - NO_DEMANGLE := 1 NO_LIBUNWIND := 1 NO_LIBDW_DWARF_UNWIND := 1 NO_LIBBPF := 1 -- cgit v1.2.3-58-ga151 From dc67c7837a832952459c4f7829e89b9d8d15f420 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 3 Apr 2023 13:35:45 -0700 Subject: perf jit: Fix a few memory leaks As reported by leak sanitizer. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Brian Robbins Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Yuan Can Link: https://lore.kernel.org/r/20230403203545.1872196-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/genelf_debug.c | 45 ++++++++++++++++++++++++++---------------- tools/perf/util/jitdump.c | 7 ++++++- 2 files changed, 34 insertions(+), 18 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/genelf_debug.c b/tools/perf/util/genelf_debug.c index dd40683bd4c0..8786c366566e 100644 --- a/tools/perf/util/genelf_debug.c +++ b/tools/perf/util/genelf_debug.c @@ -87,6 +87,12 @@ buffer_ext_init(struct buffer_ext *be) be->max_sz = 0; } +static void +buffer_ext_exit(struct buffer_ext *be) +{ + free(be->data); +} + static inline size_t buffer_ext_size(struct buffer_ext *be) { @@ -487,28 +493,28 @@ jit_add_debug_info(Elf *e, uint64_t code_addr, void *debug, int nr_debug_entries Elf_Scn *scn; Elf_Shdr *shdr; struct buffer_ext dl, di, da; - int ret; + int ret = -1; buffer_ext_init(&dl); buffer_ext_init(&di); buffer_ext_init(&da); - ret = jit_process_debug_info(code_addr, debug, nr_debug_entries, &dl, &da, &di); - if (ret) - return -1; + if (jit_process_debug_info(code_addr, debug, nr_debug_entries, &dl, &da, &di)) + goto out; + /* * setup .debug_line section */ scn = elf_newscn(e); if (!scn) { warnx("cannot create section"); - return -1; + goto out; } d = elf_newdata(scn); if (!d) { warnx("cannot get new data"); - return -1; + goto out; } d->d_align = 1; @@ -521,7 +527,7 @@ jit_add_debug_info(Elf *e, uint64_t code_addr, void *debug, int nr_debug_entries shdr = elf_getshdr(scn); if (!shdr) { warnx("cannot get section header"); - return -1; + goto out; } shdr->sh_name = 52; /* .debug_line */ @@ -536,13 +542,13 @@ jit_add_debug_info(Elf *e, uint64_t code_addr, void *debug, int nr_debug_entries scn = elf_newscn(e); if (!scn) { warnx("cannot create section"); - return -1; + goto out; } d = elf_newdata(scn); if (!d) { warnx("cannot get new data"); - return -1; + goto out; } d->d_align = 1; @@ -555,7 +561,7 @@ jit_add_debug_info(Elf *e, uint64_t code_addr, void *debug, int nr_debug_entries shdr = elf_getshdr(scn); if (!shdr) { warnx("cannot get section header"); - return -1; + goto out; } shdr->sh_name = 64; /* .debug_info */ @@ -570,13 +576,13 @@ jit_add_debug_info(Elf *e, uint64_t code_addr, void *debug, int nr_debug_entries scn = elf_newscn(e); if (!scn) { warnx("cannot create section"); - return -1; + goto out; } d = elf_newdata(scn); if (!d) { warnx("cannot get new data"); - return -1; + goto out; } d->d_align = 1; @@ -589,7 +595,7 @@ jit_add_debug_info(Elf *e, uint64_t code_addr, void *debug, int nr_debug_entries shdr = elf_getshdr(scn); if (!shdr) { warnx("cannot get section header"); - return -1; + goto out; } shdr->sh_name = 76; /* .debug_info */ @@ -601,9 +607,14 @@ jit_add_debug_info(Elf *e, uint64_t code_addr, void *debug, int nr_debug_entries /* * now we update the ELF image with all the sections */ - if (elf_update(e, ELF_C_WRITE) < 0) { + if (elf_update(e, ELF_C_WRITE) < 0) warnx("elf_update debug failed"); - return -1; - } - return 0; + else + ret = 0; + +out: + buffer_ext_exit(&dl); + buffer_ext_exit(&di); + buffer_ext_exit(&da); + return ret; } diff --git a/tools/perf/util/jitdump.c b/tools/perf/util/jitdump.c index 0e033278fa12..28e49502db5e 100644 --- a/tools/perf/util/jitdump.c +++ b/tools/perf/util/jitdump.c @@ -235,9 +235,11 @@ jit_open(struct jit_buf_desc *jd, const char *name) */ strcpy(jd->dir, name); dirname(jd->dir); + free(buf); return 0; error: + free(buf); funlockfile(jd->in); fclose(jd->in); return retval; @@ -523,7 +525,7 @@ static int jit_repipe_code_load(struct jit_buf_desc *jd, union jr_entry *jr) ret = perf_event__process_mmap2(tool, event, &sample, jd->machine); if (ret) - return ret; + goto out; ret = jit_inject_event(jd, event); /* @@ -532,6 +534,8 @@ static int jit_repipe_code_load(struct jit_buf_desc *jd, union jr_entry *jr) if (!ret) build_id__mark_dso_hit(tool, event, &sample, NULL, jd->machine); +out: + free(event); return ret; } @@ -874,6 +878,7 @@ jit_process(struct perf_session *session, } nsinfo__put(jd.nsi); + free(jd.buf); return ret; } -- cgit v1.2.3-58-ga151 From 83720209961f5cfed17214bc78978a02e3414a41 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 20 Mar 2023 14:22:32 -0700 Subject: perf map: Move map list node into symbol Using a perf map as a list node is only done in symbol. Move the list_node struct into symbol as a single pointer to the map. This makes reference count behavior more obvious and easy to check. Committer notes: Some changes to reduce the number of lines touched by keeping, for instance, the 'new_map' variable and setting it to new_node->map, so that we keep more of the project history in place and keep as much as possible the value of the 'git blame' tool. Also use map__zput() when putting a struct members, so that when we free the container struct we can get use-after-free errors as NULL pointer derefs sometimes. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexey Bayduraev Cc: Andi Kleen Cc: Andrew Morton Cc: Andy Shevchenko Cc: Darren Hart Cc: Davidlohr Bueso Cc: Dmitriy Vyukov Cc: Eric Dumazet Cc: German Gomez Cc: Hao Luo Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Madhavan Srinivasan Cc: Mark Rutland Cc: Masami Hiramatsu Cc: Miaoqian Lin Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Riccardo Mancini Cc: Shunsuke Nakamura Cc: Song Liu Cc: Stephane Eranian Cc: Stephen Brennan Cc: Steven Rostedt (VMware) Cc: Thomas Gleixner Cc: Thomas Richter Cc: Yury Norov Link: https://lore.kernel.org/r/20230320212248.1175731-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/map.h | 5 +--- tools/perf/util/symbol.c | 73 +++++++++++++++++++++++++++++++++++------------- 2 files changed, 54 insertions(+), 24 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/map.h b/tools/perf/util/map.h index 3dcfe06db6b3..2879cae05ee0 100644 --- a/tools/perf/util/map.h +++ b/tools/perf/util/map.h @@ -16,10 +16,7 @@ struct maps; struct machine; struct map { - union { - struct rb_node rb_node; - struct list_head node; - }; + struct rb_node rb_node; u64 start; u64 end; bool erange_warned:1; diff --git a/tools/perf/util/symbol.c b/tools/perf/util/symbol.c index a458aa8b87bb..8719074b7f21 100644 --- a/tools/perf/util/symbol.c +++ b/tools/perf/util/symbol.c @@ -48,6 +48,11 @@ static bool symbol__is_idle(const char *name); int vmlinux_path__nr_entries; char **vmlinux_path; +struct map_list_node { + struct list_head node; + struct map *map; +}; + struct symbol_conf symbol_conf = { .nanosecs = false, .use_modules = true, @@ -85,6 +90,11 @@ static enum dso_binary_type binary_type_symtab[] = { #define DSO_BINARY_TYPE__SYMTAB_CNT ARRAY_SIZE(binary_type_symtab) +static struct map_list_node *map_list_node__new(void) +{ + return malloc(sizeof(struct map_list_node)); +} + static bool symbol_type__filter(char symbol_type) { symbol_type = toupper(symbol_type); @@ -1219,16 +1229,21 @@ struct kcore_mapfn_data { static int kcore_mapfn(u64 start, u64 len, u64 pgoff, void *data) { struct kcore_mapfn_data *md = data; - struct map *map; + struct map_list_node *list_node = map_list_node__new(); - map = map__new2(start, md->dso); - if (map == NULL) + if (!list_node) return -ENOMEM; - map->end = map->start + len; - map->pgoff = pgoff; + list_node->map = map__new2(start, md->dso); + if (!list_node->map) { + free(list_node); + return -ENOMEM; + } - list_add(&map->node, &md->maps); + list_node->map->end = list_node->map->start + len; + list_node->map->pgoff = pgoff; + + list_add(&list_node->node, &md->maps); return 0; } @@ -1264,12 +1279,18 @@ int maps__merge_in(struct maps *kmaps, struct map *new_map) * |new.............| -> |new..| |new..| * |old....| -> |old....| */ - struct map *m = map__clone(new_map); + struct map_list_node *m = map_list_node__new(); if (!m) return -ENOMEM; - m->end = old_map->start; + m->map = map__clone(new_map); + if (!m->map) { + free(m); + return -ENOMEM; + } + + m->map->end = old_map->start; list_add_tail(&m->node, &merged); new_map->pgoff += old_map->end - new_map->start; new_map->start = old_map->end; @@ -1299,10 +1320,13 @@ int maps__merge_in(struct maps *kmaps, struct map *new_map) } while (!list_empty(&merged)) { - old_map = list_entry(merged.next, struct map, node); - list_del_init(&old_map->node); - maps__insert(kmaps, old_map); - map__put(old_map); + struct map_list_node *old_node; + + old_node = list_entry(merged.next, struct map_list_node, node); + list_del_init(&old_node->node); + maps__insert(kmaps, old_node->map); + map__put(old_node->map); + free(old_node); } if (new_map) { @@ -1317,7 +1341,7 @@ static int dso__load_kcore(struct dso *dso, struct map *map, { struct maps *kmaps = map__kmaps(map); struct kcore_mapfn_data md; - struct map *old_map, *new_map, *replacement_map = NULL, *next; + struct map *old_map, *replacement_map = NULL, *next; struct machine *machine; bool is_64_bit; int err, fd; @@ -1378,8 +1402,10 @@ static int dso__load_kcore(struct dso *dso, struct map *map, /* Find the kernel map using the '_stext' symbol */ if (!kallsyms__get_function_start(kallsyms_filename, "_stext", &stext)) { u64 replacement_size = 0; + struct map_list_node *new_node; - list_for_each_entry(new_map, &md.maps, node) { + list_for_each_entry(new_node, &md.maps, node) { + struct map *new_map = new_node->map; u64 new_size = new_map->end - new_map->start; if (!(stext >= new_map->start && stext < new_map->end)) @@ -1399,12 +1425,15 @@ static int dso__load_kcore(struct dso *dso, struct map *map, } if (!replacement_map) - replacement_map = list_entry(md.maps.next, struct map, node); + replacement_map = list_entry(md.maps.next, struct map_list_node, node)->map; /* Add new maps */ while (!list_empty(&md.maps)) { - new_map = list_entry(md.maps.next, struct map, node); - list_del_init(&new_map->node); + struct map_list_node *new_node = list_entry(md.maps.next, struct map_list_node, node); + struct map *new_map = new_node->map; + + list_del_init(&new_node->node); + if (new_map == replacement_map) { map->start = new_map->start; map->end = new_map->end; @@ -1426,6 +1455,7 @@ static int dso__load_kcore(struct dso *dso, struct map *map, if (maps__merge_in(kmaps, new_map)) goto out_err; } + free(new_node); } if (machine__is(machine, "x86_64")) { @@ -1462,9 +1492,12 @@ static int dso__load_kcore(struct dso *dso, struct map *map, out_err: while (!list_empty(&md.maps)) { - map = list_entry(md.maps.next, struct map, node); - list_del_init(&map->node); - map__put(map); + struct map_list_node *list_node; + + list_node = list_entry(md.maps.next, struct map_list_node, node); + list_del_init(&list_node->node); + map__zput(list_node->map); + free(list_node); } close(fd); return -EINVAL; -- cgit v1.2.3-58-ga151 From ff583dc43dc8b62c9ec639604adae641ba38a91d Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 20 Mar 2023 14:22:33 -0700 Subject: perf maps: Remove rb_node from struct map struct map is reference counted, having it also be a node in an red-black tree complicates the reference counting. Switch to having a map_rb_node which is a red-block tree node but points at the reference counted struct map. This reference is responsible for a single reference count. Committer notes: Fixed up tools/perf/util/unwind-libunwind-local.c to use map_rb_node as well. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexey Bayduraev Cc: Andi Kleen Cc: Andrew Morton Cc: Andy Shevchenko Cc: Darren Hart Cc: Davidlohr Bueso Cc: Dmitriy Vyukov Cc: Eric Dumazet Cc: German Gomez Cc: Hao Luo Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Madhavan Srinivasan Cc: Mark Rutland Cc: Masami Hiramatsu Cc: Miaoqian Lin Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Riccardo Mancini Cc: Shunsuke Nakamura Cc: Song Liu Cc: Stephane Eranian Cc: Stephen Brennan Cc: Steven Rostedt (VMware) Cc: Thomas Gleixner Cc: Thomas Richter Cc: Yury Norov Link: https://lore.kernel.org/r/20230320212248.1175731-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/x86/util/event.c | 13 +-- tools/perf/builtin-report.c | 6 +- tools/perf/tests/maps.c | 8 +- tools/perf/tests/vmlinux-kallsyms.c | 17 +-- tools/perf/util/bpf_lock_contention.c | 2 +- tools/perf/util/machine.c | 68 +++++++----- tools/perf/util/map.c | 16 --- tools/perf/util/map.h | 1 - tools/perf/util/maps.c | 180 ++++++++++++++++++++----------- tools/perf/util/maps.h | 17 ++- tools/perf/util/probe-event.c | 18 ++-- tools/perf/util/symbol-elf.c | 9 +- tools/perf/util/symbol.c | 77 ++++++++----- tools/perf/util/synthetic-events.c | 26 ++--- tools/perf/util/thread.c | 10 +- tools/perf/util/unwind-libunwind-local.c | 6 +- tools/perf/util/vdso.c | 7 +- 17 files changed, 295 insertions(+), 186 deletions(-) (limited to 'tools') diff --git a/tools/perf/arch/x86/util/event.c b/tools/perf/arch/x86/util/event.c index e4288d09f3a0..17bf60babfbd 100644 --- a/tools/perf/arch/x86/util/event.c +++ b/tools/perf/arch/x86/util/event.c @@ -19,7 +19,7 @@ int perf_event__synthesize_extra_kmaps(struct perf_tool *tool, struct machine *machine) { int rc = 0; - struct map *pos; + struct map_rb_node *pos; struct maps *kmaps = machine__kernel_maps(machine); union perf_event *event = zalloc(sizeof(event->mmap) + machine->id_hdr_size); @@ -33,11 +33,12 @@ int perf_event__synthesize_extra_kmaps(struct perf_tool *tool, maps__for_each_entry(kmaps, pos) { struct kmap *kmap; size_t size; + struct map *map = pos->map; - if (!__map__is_extra_kernel_map(pos)) + if (!__map__is_extra_kernel_map(map)) continue; - kmap = map__kmap(pos); + kmap = map__kmap(map); size = sizeof(event->mmap) - sizeof(event->mmap.filename) + PERF_ALIGN(strlen(kmap->name) + 1, sizeof(u64)) + @@ -58,9 +59,9 @@ int perf_event__synthesize_extra_kmaps(struct perf_tool *tool, event->mmap.header.size = size; - event->mmap.start = pos->start; - event->mmap.len = pos->end - pos->start; - event->mmap.pgoff = pos->pgoff; + event->mmap.start = map->start; + event->mmap.len = map->end - map->start; + event->mmap.pgoff = map->pgoff; event->mmap.pid = machine->pid; strlcpy(event->mmap.filename, kmap->name, PATH_MAX); diff --git a/tools/perf/builtin-report.c b/tools/perf/builtin-report.c index 4011abc03d0d..c7e3863e8f44 100644 --- a/tools/perf/builtin-report.c +++ b/tools/perf/builtin-report.c @@ -844,9 +844,11 @@ static struct task *tasks_list(struct task *task, struct machine *machine) static size_t maps__fprintf_task(struct maps *maps, int indent, FILE *fp) { size_t printed = 0; - struct map *map; + struct map_rb_node *rb_node; + + maps__for_each_entry(maps, rb_node) { + struct map *map = rb_node->map; - maps__for_each_entry(maps, map) { printed += fprintf(fp, "%*s %" PRIx64 "-%" PRIx64 " %c%c%c%c %08" PRIx64 " %" PRIu64 " %s\n", indent, "", map->start, map->end, map->prot & PROT_READ ? 'r' : '-', diff --git a/tools/perf/tests/maps.c b/tools/perf/tests/maps.c index a69988a89d26..8246d37e4b7a 100644 --- a/tools/perf/tests/maps.c +++ b/tools/perf/tests/maps.c @@ -15,10 +15,12 @@ struct map_def { static int check_maps(struct map_def *merged, unsigned int size, struct maps *maps) { - struct map *map; + struct map_rb_node *rb_node; unsigned int i = 0; - maps__for_each_entry(maps, map) { + maps__for_each_entry(maps, rb_node) { + struct map *map = rb_node->map; + if (i > 0) TEST_ASSERT_VAL("less maps expected", (map && i < size) || (!map && i == size)); @@ -74,7 +76,7 @@ static int test__maps__merge_in(struct test_suite *t __maybe_unused, int subtest map->start = bpf_progs[i].start; map->end = bpf_progs[i].end; - maps__insert(maps, map); + TEST_ASSERT_VAL("failed to insert map", maps__insert(maps, map) == 0); map__put(map); } diff --git a/tools/perf/tests/vmlinux-kallsyms.c b/tools/perf/tests/vmlinux-kallsyms.c index 8ab035b55875..c8abb3ca8347 100644 --- a/tools/perf/tests/vmlinux-kallsyms.c +++ b/tools/perf/tests/vmlinux-kallsyms.c @@ -118,7 +118,8 @@ static int test__vmlinux_matches_kallsyms(struct test_suite *test __maybe_unused int err = TEST_FAIL; struct rb_node *nd; struct symbol *sym; - struct map *kallsyms_map, *vmlinux_map, *map; + struct map *kallsyms_map, *vmlinux_map; + struct map_rb_node *rb_node; struct machine kallsyms, vmlinux; struct maps *maps; u64 mem_start, mem_end; @@ -290,15 +291,15 @@ next_pair: header_printed = false; - maps__for_each_entry(maps, map) { - struct map * + maps__for_each_entry(maps, rb_node) { + struct map *map = rb_node->map; /* * If it is the kernel, kallsyms is always "[kernel.kallsyms]", while * the kernel will have the path for the vmlinux file being used, * so use the short name, less descriptive but the same ("[kernel]" in * both cases. */ - pair = maps__find_by_name(kallsyms.kmaps, (map->dso->kernel ? + struct map *pair = maps__find_by_name(kallsyms.kmaps, (map->dso->kernel ? map->dso->short_name : map->dso->name)); if (pair) { @@ -314,8 +315,8 @@ next_pair: header_printed = false; - maps__for_each_entry(maps, map) { - struct map *pair; + maps__for_each_entry(maps, rb_node) { + struct map *pair, *map = rb_node->map; mem_start = vmlinux_map->unmap_ip(vmlinux_map, map->start); mem_end = vmlinux_map->unmap_ip(vmlinux_map, map->end); @@ -344,7 +345,9 @@ next_pair: maps = machine__kernel_maps(&kallsyms); - maps__for_each_entry(maps, map) { + maps__for_each_entry(maps, rb_node) { + struct map *map = rb_node->map; + if (!map->priv) { if (!header_printed) { pr_info("WARN: Maps only in kallsyms:\n"); diff --git a/tools/perf/util/bpf_lock_contention.c b/tools/perf/util/bpf_lock_contention.c index b3e8aa9cd011..8a5d0eb44189 100644 --- a/tools/perf/util/bpf_lock_contention.c +++ b/tools/perf/util/bpf_lock_contention.c @@ -284,7 +284,7 @@ int lock_contention_read(struct lock_contention *con) } /* make sure it loads the kernel map */ - map__load(maps__first(machine->kmaps)); + map__load(maps__first(machine->kmaps)->map); prev_key = NULL; while (!bpf_map_get_next_key(fd, prev_key, &key)) { diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c index 3182815c73c6..2058623726d2 100644 --- a/tools/perf/util/machine.c +++ b/tools/perf/util/machine.c @@ -883,6 +883,7 @@ static int machine__process_ksymbol_register(struct machine *machine, if (!map) { struct dso *dso = dso__new(event->ksymbol.name); + int err; if (dso) { dso->kernel = DSO_SPACE__KERNEL; @@ -902,8 +903,11 @@ static int machine__process_ksymbol_register(struct machine *machine, map->start = event->ksymbol.addr; map->end = map->start + event->ksymbol.len; - maps__insert(machine__kernel_maps(machine), map); + err = maps__insert(machine__kernel_maps(machine), map); map__put(map); + if (err) + return err; + dso__set_loaded(dso); if (is_bpf_image(event->ksymbol.name)) { @@ -1003,6 +1007,7 @@ static struct map *machine__addnew_module_map(struct machine *machine, u64 start struct map *map = NULL; struct kmod_path m; struct dso *dso; + int err; if (kmod_path__parse_name(&m, filename)) return NULL; @@ -1015,10 +1020,14 @@ static struct map *machine__addnew_module_map(struct machine *machine, u64 start if (map == NULL) goto out; - maps__insert(machine__kernel_maps(machine), map); + err = maps__insert(machine__kernel_maps(machine), map); /* Put the map here because maps__insert already got it */ map__put(map); + + /* If maps__insert failed, return NULL. */ + if (err) + map = NULL; out: /* put the dso here, corresponding to machine__findnew_module_dso */ dso__put(dso); @@ -1185,10 +1194,11 @@ int machine__create_extra_kernel_map(struct machine *machine, { struct kmap *kmap; struct map *map; + int err; map = map__new2(xm->start, kernel); if (!map) - return -1; + return -ENOMEM; map->end = xm->end; map->pgoff = xm->pgoff; @@ -1197,14 +1207,16 @@ int machine__create_extra_kernel_map(struct machine *machine, strlcpy(kmap->name, xm->name, KMAP_NAME_LEN); - maps__insert(machine__kernel_maps(machine), map); + err = maps__insert(machine__kernel_maps(machine), map); - pr_debug2("Added extra kernel map %s %" PRIx64 "-%" PRIx64 "\n", - kmap->name, map->start, map->end); + if (!err) { + pr_debug2("Added extra kernel map %s %" PRIx64 "-%" PRIx64 "\n", + kmap->name, map->start, map->end); + } map__put(map); - return 0; + return err; } static u64 find_entry_trampoline(struct dso *dso) @@ -1245,16 +1257,16 @@ int machine__map_x86_64_entry_trampolines(struct machine *machine, struct maps *kmaps = machine__kernel_maps(machine); int nr_cpus_avail, cpu; bool found = false; - struct map *map; + struct map_rb_node *rb_node; u64 pgoff; /* * In the vmlinux case, pgoff is a virtual address which must now be * mapped to a vmlinux offset. */ - maps__for_each_entry(kmaps, map) { + maps__for_each_entry(kmaps, rb_node) { + struct map *dest_map, *map = rb_node->map; struct kmap *kmap = __map__kmap(map); - struct map *dest_map; if (!kmap || !is_entry_trampoline(kmap->name)) continue; @@ -1309,11 +1321,10 @@ __machine__create_kernel_maps(struct machine *machine, struct dso *kernel) machine->vmlinux_map = map__new2(0, kernel); if (machine->vmlinux_map == NULL) - return -1; + return -ENOMEM; machine->vmlinux_map->map_ip = machine->vmlinux_map->unmap_ip = identity__map_ip; - maps__insert(machine__kernel_maps(machine), machine->vmlinux_map); - return 0; + return maps__insert(machine__kernel_maps(machine), machine->vmlinux_map); } void machine__destroy_kernel_maps(struct machine *machine) @@ -1635,25 +1646,26 @@ static void machine__set_kernel_mmap(struct machine *machine, machine->vmlinux_map->end = ~0ULL; } -static void machine__update_kernel_mmap(struct machine *machine, +static int machine__update_kernel_mmap(struct machine *machine, u64 start, u64 end) { struct map *map = machine__kernel_map(machine); + int err; map__get(map); maps__remove(machine__kernel_maps(machine), map); machine__set_kernel_mmap(machine, start, end); - maps__insert(machine__kernel_maps(machine), map); + err = maps__insert(machine__kernel_maps(machine), map); map__put(map); + return err; } int machine__create_kernel_maps(struct machine *machine) { struct dso *kernel = machine__get_kernel(machine); const char *name = NULL; - struct map *map; u64 start = 0, end = ~0ULL; int ret; @@ -1685,7 +1697,9 @@ int machine__create_kernel_maps(struct machine *machine) * we have a real start address now, so re-order the kmaps * assume it's the last in the kmaps */ - machine__update_kernel_mmap(machine, start, end); + ret = machine__update_kernel_mmap(machine, start, end); + if (ret < 0) + goto out_put; } if (machine__create_extra_kernel_maps(machine, kernel)) @@ -1693,9 +1707,12 @@ int machine__create_kernel_maps(struct machine *machine) if (end == ~0ULL) { /* update end address of the kernel map using adjacent module address */ - map = map__next(machine__kernel_map(machine)); - if (map) - machine__set_kernel_mmap(machine, start, map->start); + struct map_rb_node *rb_node = maps__find_node(machine__kernel_maps(machine), + machine__kernel_map(machine)); + struct map_rb_node *next = map_rb_node__next(rb_node); + + if (next) + machine__set_kernel_mmap(machine, start, next->map->start); } out_put: @@ -1828,7 +1845,10 @@ static int machine__process_kernel_mmap_event(struct machine *machine, if (strstr(kernel->long_name, "vmlinux")) dso__set_short_name(kernel, "[kernel.vmlinux]", false); - machine__update_kernel_mmap(machine, xm->start, xm->end); + if (machine__update_kernel_mmap(machine, xm->start, xm->end) < 0) { + dso__put(kernel); + goto out_problem; + } if (build_id__is_defined(bid)) dso__set_build_id(kernel, bid); @@ -3330,11 +3350,11 @@ int machine__for_each_dso(struct machine *machine, machine__dso_t fn, void *priv int machine__for_each_kernel_map(struct machine *machine, machine__map_t fn, void *priv) { struct maps *maps = machine__kernel_maps(machine); - struct map *map; + struct map_rb_node *pos; int err = 0; - for (map = maps__first(maps); map != NULL; map = map__next(map)) { - err = fn(map, priv); + maps__for_each_entry(maps, pos) { + err = fn(pos->map, priv); if (err != 0) { break; } diff --git a/tools/perf/util/map.c b/tools/perf/util/map.c index f3a3d9b3a40d..7620cfa114d4 100644 --- a/tools/perf/util/map.c +++ b/tools/perf/util/map.c @@ -111,7 +111,6 @@ void map__init(struct map *map, u64 start, u64 end, u64 pgoff, struct dso *dso) map->dso = dso__get(dso); map->map_ip = map__map_ip; map->unmap_ip = map__unmap_ip; - RB_CLEAR_NODE(&map->rb_node); map->erange_warned = false; refcount_set(&map->refcnt, 1); } @@ -397,7 +396,6 @@ struct map *map__clone(struct map *from) map = memdup(from, size); if (map != NULL) { refcount_set(&map->refcnt, 1); - RB_CLEAR_NODE(&map->rb_node); dso__get(map->dso); } @@ -537,20 +535,6 @@ bool map__contains_symbol(const struct map *map, const struct symbol *sym) return ip >= map->start && ip < map->end; } -static struct map *__map__next(struct map *map) -{ - struct rb_node *next = rb_next(&map->rb_node); - - if (next) - return rb_entry(next, struct map, rb_node); - return NULL; -} - -struct map *map__next(struct map *map) -{ - return map ? __map__next(map) : NULL; -} - struct kmap *__map__kmap(struct map *map) { if (!map->dso || !map->dso->kernel) diff --git a/tools/perf/util/map.h b/tools/perf/util/map.h index 2879cae05ee0..d1a6f85fd31d 100644 --- a/tools/perf/util/map.h +++ b/tools/perf/util/map.h @@ -16,7 +16,6 @@ struct maps; struct machine; struct map { - struct rb_node rb_node; u64 start; u64 end; bool erange_warned:1; diff --git a/tools/perf/util/maps.c b/tools/perf/util/maps.c index 37bd5b40000d..83ec126bcbe5 100644 --- a/tools/perf/util/maps.c +++ b/tools/perf/util/maps.c @@ -10,8 +10,6 @@ #include "ui/ui.h" #include "unwind.h" -static void __maps__insert(struct maps *maps, struct map *map); - static void maps__init(struct maps *maps, struct machine *machine) { maps->entries = RB_ROOT; @@ -32,10 +30,44 @@ static void __maps__free_maps_by_name(struct maps *maps) maps->nr_maps_allocated = 0; } -void maps__insert(struct maps *maps, struct map *map) +static int __maps__insert(struct maps *maps, struct map *map) { + struct rb_node **p = &maps->entries.rb_node; + struct rb_node *parent = NULL; + const u64 ip = map->start; + struct map_rb_node *m, *new_rb_node; + + new_rb_node = malloc(sizeof(*new_rb_node)); + if (!new_rb_node) + return -ENOMEM; + + RB_CLEAR_NODE(&new_rb_node->rb_node); + new_rb_node->map = map; + + while (*p != NULL) { + parent = *p; + m = rb_entry(parent, struct map_rb_node, rb_node); + if (ip < m->map->start) + p = &(*p)->rb_left; + else + p = &(*p)->rb_right; + } + + rb_link_node(&new_rb_node->rb_node, parent, p); + rb_insert_color(&new_rb_node->rb_node, &maps->entries); + map__get(map); + return 0; +} + +int maps__insert(struct maps *maps, struct map *map) +{ + int err; + down_write(&maps->lock); - __maps__insert(maps, map); + err = __maps__insert(maps, map); + if (err) + goto out; + ++maps->nr_maps; if (map->dso && map->dso->kernel) { @@ -59,32 +91,39 @@ void maps__insert(struct maps *maps, struct map *map) if (maps_by_name == NULL) { __maps__free_maps_by_name(maps); - up_write(&maps->lock); - return; + err = -ENOMEM; + goto out; } maps->maps_by_name = maps_by_name; maps->nr_maps_allocated = nr_allocate; - } +} maps->maps_by_name[maps->nr_maps - 1] = map; __maps__sort_by_name(maps); } + out: up_write(&maps->lock); + return err; } -static void __maps__remove(struct maps *maps, struct map *map) +static void __maps__remove(struct maps *maps, struct map_rb_node *rb_node) { - rb_erase_init(&map->rb_node, &maps->entries); - map__put(map); + rb_erase_init(&rb_node->rb_node, &maps->entries); + map__put(rb_node->map); + free(rb_node); } void maps__remove(struct maps *maps, struct map *map) { + struct map_rb_node *rb_node; + down_write(&maps->lock); if (maps->last_search_by_name == map) maps->last_search_by_name = NULL; - __maps__remove(maps, map); + rb_node = maps__find_node(maps, map); + assert(rb_node->map == map); + __maps__remove(maps, rb_node); --maps->nr_maps; if (maps->maps_by_name) __maps__free_maps_by_name(maps); @@ -93,11 +132,12 @@ void maps__remove(struct maps *maps, struct map *map) static void __maps__purge(struct maps *maps) { - struct map *pos, *next; + struct map_rb_node *pos, *next; maps__for_each_entry_safe(maps, pos, next) { rb_erase_init(&pos->rb_node, &maps->entries); - map__put(pos); + map__put(pos->map); + free(pos); } } @@ -153,21 +193,21 @@ struct symbol *maps__find_symbol(struct maps *maps, u64 addr, struct map **mapp) struct symbol *maps__find_symbol_by_name(struct maps *maps, const char *name, struct map **mapp) { struct symbol *sym; - struct map *pos; + struct map_rb_node *pos; down_read(&maps->lock); maps__for_each_entry(maps, pos) { - sym = map__find_symbol_by_name(pos, name); + sym = map__find_symbol_by_name(pos->map, name); if (sym == NULL) continue; - if (!map__contains_symbol(pos, sym)) { + if (!map__contains_symbol(pos->map, sym)) { sym = NULL; continue; } if (mapp != NULL) - *mapp = pos; + *mapp = pos->map; goto out; } @@ -196,15 +236,15 @@ int maps__find_ams(struct maps *maps, struct addr_map_symbol *ams) size_t maps__fprintf(struct maps *maps, FILE *fp) { size_t printed = 0; - struct map *pos; + struct map_rb_node *pos; down_read(&maps->lock); maps__for_each_entry(maps, pos) { printed += fprintf(fp, "Map:"); - printed += map__fprintf(pos, fp); + printed += map__fprintf(pos->map, fp); if (verbose > 2) { - printed += dso__fprintf(pos->dso, fp); + printed += dso__fprintf(pos->map->dso, fp); printed += fprintf(fp, "--\n"); } } @@ -231,11 +271,11 @@ int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp) next = root->rb_node; first = NULL; while (next) { - struct map *pos = rb_entry(next, struct map, rb_node); + struct map_rb_node *pos = rb_entry(next, struct map_rb_node, rb_node); - if (pos->end > map->start) { + if (pos->map->end > map->start) { first = next; - if (pos->start <= map->start) + if (pos->map->start <= map->start) break; next = next->rb_left; } else @@ -244,14 +284,14 @@ int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp) next = first; while (next) { - struct map *pos = rb_entry(next, struct map, rb_node); + struct map_rb_node *pos = rb_entry(next, struct map_rb_node, rb_node); next = rb_next(&pos->rb_node); /* * Stop if current map starts after map->end. * Maps are ordered by start: next will not overlap for sure. */ - if (pos->start >= map->end) + if (pos->map->start >= map->end) break; if (verbose >= 2) { @@ -262,7 +302,7 @@ int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp) } else { fputs("overlapping maps:\n", fp); map__fprintf(map, fp); - map__fprintf(pos, fp); + map__fprintf(pos->map, fp); } } @@ -271,8 +311,8 @@ int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp) * Now check if we need to create new maps for areas not * overlapped by the new map: */ - if (map->start > pos->start) { - struct map *before = map__clone(pos); + if (map->start > pos->map->start) { + struct map *before = map__clone(pos->map); if (before == NULL) { err = -ENOMEM; @@ -280,14 +320,17 @@ int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp) } before->end = map->start; - __maps__insert(maps, before); + err = __maps__insert(maps, before); + if (err) + goto put_map; + if (verbose >= 2 && !use_browser) map__fprintf(before, fp); map__put(before); } - if (map->end < pos->end) { - struct map *after = map__clone(pos); + if (map->end < pos->map->end) { + struct map *after = map__clone(pos->map); if (after == NULL) { err = -ENOMEM; @@ -295,15 +338,19 @@ int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp) } after->start = map->end; - after->pgoff += map->end - pos->start; - assert(pos->map_ip(pos, map->end) == after->map_ip(after, map->end)); - __maps__insert(maps, after); + after->pgoff += map->end - pos->map->start; + assert(pos->map->map_ip(pos->map, map->end) == + after->map_ip(after, map->end)); + err = __maps__insert(maps, after); + if (err) + goto put_map; + if (verbose >= 2 && !use_browser) map__fprintf(after, fp); map__put(after); } put_map: - map__put(pos); + map__put(pos->map); if (err) goto out; @@ -322,12 +369,12 @@ int maps__clone(struct thread *thread, struct maps *parent) { struct maps *maps = thread->maps; int err; - struct map *map; + struct map_rb_node *rb_node; down_read(&parent->lock); - maps__for_each_entry(parent, map) { - struct map *new = map__clone(map); + maps__for_each_entry(parent, rb_node) { + struct map *new = map__clone(rb_node->map); if (new == NULL) { err = -ENOMEM; @@ -338,7 +385,10 @@ int maps__clone(struct thread *thread, struct maps *parent) if (err) goto out_unlock; - maps__insert(maps, new); + err = maps__insert(maps, new); + if (err) + goto out_unlock; + map__put(new); } @@ -348,40 +398,31 @@ out_unlock: return err; } -static void __maps__insert(struct maps *maps, struct map *map) +struct map_rb_node *maps__find_node(struct maps *maps, struct map *map) { - struct rb_node **p = &maps->entries.rb_node; - struct rb_node *parent = NULL; - const u64 ip = map->start; - struct map *m; + struct map_rb_node *rb_node; - while (*p != NULL) { - parent = *p; - m = rb_entry(parent, struct map, rb_node); - if (ip < m->start) - p = &(*p)->rb_left; - else - p = &(*p)->rb_right; + maps__for_each_entry(maps, rb_node) { + if (rb_node->map == map) + return rb_node; } - - rb_link_node(&map->rb_node, parent, p); - rb_insert_color(&map->rb_node, &maps->entries); - map__get(map); + return NULL; } struct map *maps__find(struct maps *maps, u64 ip) { struct rb_node *p; - struct map *m; + struct map_rb_node *m; + down_read(&maps->lock); p = maps->entries.rb_node; while (p != NULL) { - m = rb_entry(p, struct map, rb_node); - if (ip < m->start) + m = rb_entry(p, struct map_rb_node, rb_node); + if (ip < m->map->start) p = p->rb_left; - else if (ip >= m->end) + else if (ip >= m->map->end) p = p->rb_right; else goto out; @@ -390,14 +431,29 @@ struct map *maps__find(struct maps *maps, u64 ip) m = NULL; out: up_read(&maps->lock); - return m; + return m ? m->map : NULL; } -struct map *maps__first(struct maps *maps) +struct map_rb_node *maps__first(struct maps *maps) { struct rb_node *first = rb_first(&maps->entries); if (first) - return rb_entry(first, struct map, rb_node); + return rb_entry(first, struct map_rb_node, rb_node); return NULL; } + +struct map_rb_node *map_rb_node__next(struct map_rb_node *node) +{ + struct rb_node *next; + + if (!node) + return NULL; + + next = rb_next(&node->rb_node); + + if (!next) + return NULL; + + return rb_entry(next, struct map_rb_node, rb_node); +} diff --git a/tools/perf/util/maps.h b/tools/perf/util/maps.h index 7e729ff42749..512746ec0f9a 100644 --- a/tools/perf/util/maps.h +++ b/tools/perf/util/maps.h @@ -15,15 +15,22 @@ struct map; struct maps; struct thread; +struct map_rb_node { + struct rb_node rb_node; + struct map *map; +}; + +struct map_rb_node *maps__first(struct maps *maps); +struct map_rb_node *map_rb_node__next(struct map_rb_node *node); +struct map_rb_node *maps__find_node(struct maps *maps, struct map *map); struct map *maps__find(struct maps *maps, u64 addr); -struct map *maps__first(struct maps *maps); -struct map *map__next(struct map *map); #define maps__for_each_entry(maps, map) \ - for (map = maps__first(maps); map; map = map__next(map)) + for (map = maps__first(maps); map; map = map_rb_node__next(map)) #define maps__for_each_entry_safe(maps, map, next) \ - for (map = maps__first(maps), next = map__next(map); map; map = next, next = map__next(map)) + for (map = maps__first(maps), next = map_rb_node__next(map); map; \ + map = next, next = map_rb_node__next(map)) struct maps { struct rb_root entries; @@ -63,7 +70,7 @@ void maps__put(struct maps *maps); int maps__clone(struct thread *thread, struct maps *parent); size_t maps__fprintf(struct maps *maps, FILE *fp); -void maps__insert(struct maps *maps, struct map *map); +int maps__insert(struct maps *maps, struct map *map); void maps__remove(struct maps *maps, struct map *map); diff --git a/tools/perf/util/probe-event.c b/tools/perf/util/probe-event.c index 881d94f65a6b..cdf5d655d84c 100644 --- a/tools/perf/util/probe-event.c +++ b/tools/perf/util/probe-event.c @@ -151,23 +151,27 @@ static int kernel_get_symbol_address_by_name(const char *name, u64 *addr, static struct map *kernel_get_module_map(const char *module) { struct maps *maps = machine__kernel_maps(host_machine); - struct map *pos; + struct map_rb_node *pos; /* A file path -- this is an offline module */ if (module && strchr(module, '/')) return dso__new_map(module); if (!module) { - pos = machine__kernel_map(host_machine); - return map__get(pos); + struct map *map = machine__kernel_map(host_machine); + + return map__get(map); } maps__for_each_entry(maps, pos) { /* short_name is "[module]" */ - if (strncmp(pos->dso->short_name + 1, module, - pos->dso->short_name_len - 2) == 0 && - module[pos->dso->short_name_len - 2] == '\0') { - return map__get(pos); + const char *short_name = pos->map->dso->short_name; + u16 short_name_len = pos->map->dso->short_name_len; + + if (strncmp(short_name + 1, module, + short_name_len - 2) == 0 && + module[short_name_len - 2] == '\0') { + return map__get(pos->map); } } return NULL; diff --git a/tools/perf/util/symbol-elf.c b/tools/perf/util/symbol-elf.c index ae810d4cf3cd..33e1f587baa9 100644 --- a/tools/perf/util/symbol-elf.c +++ b/tools/perf/util/symbol-elf.c @@ -1361,10 +1361,14 @@ static int dso__process_kernel_symbol(struct dso *dso, struct map *map, map->unmap_ip = map__unmap_ip; /* Ensure maps are correctly ordered */ if (kmaps) { + int err; + map__get(map); maps__remove(kmaps, map); - maps__insert(kmaps, map); + err = maps__insert(kmaps, map); map__put(map); + if (err) + return err; } } @@ -1417,7 +1421,8 @@ static int dso__process_kernel_symbol(struct dso *dso, struct map *map, curr_map->map_ip = curr_map->unmap_ip = identity__map_ip; } curr_dso->symtab_type = dso->symtab_type; - maps__insert(kmaps, curr_map); + if (maps__insert(kmaps, curr_map)) + return -1; /* * Add it before we drop the reference to curr_map, i.e. while * we still are sure to have a reference to this DSO via diff --git a/tools/perf/util/symbol.c b/tools/perf/util/symbol.c index 8719074b7f21..e7a8ae290c57 100644 --- a/tools/perf/util/symbol.c +++ b/tools/perf/util/symbol.c @@ -273,13 +273,13 @@ void symbols__fixup_end(struct rb_root_cached *symbols, bool is_kallsyms) void maps__fixup_end(struct maps *maps) { - struct map *prev = NULL, *curr; + struct map_rb_node *prev = NULL, *curr; down_write(&maps->lock); maps__for_each_entry(maps, curr) { - if (prev != NULL && !prev->end) - prev->end = curr->start; + if (prev != NULL && !prev->map->end) + prev->map->end = curr->map->start; prev = curr; } @@ -288,8 +288,8 @@ void maps__fixup_end(struct maps *maps) * We still haven't the actual symbols, so guess the * last map final address. */ - if (curr && !curr->end) - curr->end = ~0ULL; + if (curr && !curr->map->end) + curr->map->end = ~0ULL; up_write(&maps->lock); } @@ -942,7 +942,10 @@ static int maps__split_kallsyms(struct maps *kmaps, struct dso *dso, u64 delta, } curr_map->map_ip = curr_map->unmap_ip = identity__map_ip; - maps__insert(kmaps, curr_map); + if (maps__insert(kmaps, curr_map)) { + dso__put(ndso); + return -1; + } ++kernel_range; } else if (delta) { /* Kernel was relocated at boot time */ @@ -1130,14 +1133,15 @@ out_delete_from: static int do_validate_kcore_modules(const char *filename, struct maps *kmaps) { struct rb_root modules = RB_ROOT; - struct map *old_map; + struct map_rb_node *old_node; int err; err = read_proc_modules(filename, &modules); if (err) return err; - maps__for_each_entry(kmaps, old_map) { + maps__for_each_entry(kmaps, old_node) { + struct map *old_map = old_node->map; struct module_info *mi; if (!__map__is_kmodule(old_map)) { @@ -1254,10 +1258,13 @@ static int kcore_mapfn(u64 start, u64 len, u64 pgoff, void *data) */ int maps__merge_in(struct maps *kmaps, struct map *new_map) { - struct map *old_map; + struct map_rb_node *rb_node; LIST_HEAD(merged); + int err = 0; + + maps__for_each_entry(kmaps, rb_node) { + struct map *old_map = rb_node->map; - maps__for_each_entry(kmaps, old_map) { /* no overload with this one */ if (new_map->end < old_map->start || new_map->start >= old_map->end) @@ -1281,13 +1288,16 @@ int maps__merge_in(struct maps *kmaps, struct map *new_map) */ struct map_list_node *m = map_list_node__new(); - if (!m) - return -ENOMEM; + if (!m) { + err = -ENOMEM; + goto out; + } m->map = map__clone(new_map); if (!m->map) { free(m); - return -ENOMEM; + err = -ENOMEM; + goto out; } m->map->end = old_map->start; @@ -1319,21 +1329,24 @@ int maps__merge_in(struct maps *kmaps, struct map *new_map) } } +out: while (!list_empty(&merged)) { struct map_list_node *old_node; old_node = list_entry(merged.next, struct map_list_node, node); list_del_init(&old_node->node); - maps__insert(kmaps, old_node->map); + if (!err) + err = maps__insert(kmaps, old_node->map); map__put(old_node->map); free(old_node); } if (new_map) { - maps__insert(kmaps, new_map); + if (!err) + err = maps__insert(kmaps, new_map); map__put(new_map); } - return 0; + return err; } static int dso__load_kcore(struct dso *dso, struct map *map, @@ -1341,7 +1354,8 @@ static int dso__load_kcore(struct dso *dso, struct map *map, { struct maps *kmaps = map__kmaps(map); struct kcore_mapfn_data md; - struct map *old_map, *replacement_map = NULL, *next; + struct map *replacement_map = NULL; + struct map_rb_node *old_node, *next; struct machine *machine; bool is_64_bit; int err, fd; @@ -1388,7 +1402,9 @@ static int dso__load_kcore(struct dso *dso, struct map *map, } /* Remove old maps */ - maps__for_each_entry_safe(kmaps, old_map, next) { + maps__for_each_entry_safe(kmaps, old_node, next) { + struct map *old_map = old_node->map; + /* * We need to preserve eBPF maps even if they are * covered by kcore, because we need to access @@ -1443,17 +1459,21 @@ static int dso__load_kcore(struct dso *dso, struct map *map, /* Ensure maps are correctly ordered */ map__get(map); maps__remove(kmaps, map); - maps__insert(kmaps, map); + err = maps__insert(kmaps, map); map__put(map); map__put(new_map); + if (err) + goto out_err; } else { /* * Merge kcore map into existing maps, * and ensure that current maps (eBPF) * stay intact. */ - if (maps__merge_in(kmaps, new_map)) + if (maps__merge_in(kmaps, new_map)) { + err = -EINVAL; goto out_err; + } } free(new_node); } @@ -1500,7 +1520,7 @@ out_err: free(list_node); } close(fd); - return -EINVAL; + return err; } /* @@ -2044,8 +2064,9 @@ void __maps__sort_by_name(struct maps *maps) static int map__groups__sort_by_name_from_rbtree(struct maps *maps) { - struct map *map; - struct map **maps_by_name = realloc(maps->maps_by_name, maps->nr_maps * sizeof(map)); + struct map_rb_node *rb_node; + struct map **maps_by_name = realloc(maps->maps_by_name, + maps->nr_maps * sizeof(struct map *)); int i = 0; if (maps_by_name == NULL) @@ -2057,8 +2078,8 @@ static int map__groups__sort_by_name_from_rbtree(struct maps *maps) maps->maps_by_name = maps_by_name; maps->nr_maps_allocated = maps->nr_maps; - maps__for_each_entry(maps, map) - maps_by_name[i++] = map; + maps__for_each_entry(maps, rb_node) + maps_by_name[i++] = rb_node->map; __maps__sort_by_name(maps); @@ -2084,6 +2105,7 @@ static struct map *__maps__find_by_name(struct maps *maps, const char *name) struct map *maps__find_by_name(struct maps *maps, const char *name) { + struct map_rb_node *rb_node; struct map *map; down_read(&maps->lock); @@ -2102,12 +2124,13 @@ struct map *maps__find_by_name(struct maps *maps, const char *name) goto out_unlock; /* Fallback to traversing the rbtree... */ - maps__for_each_entry(maps, map) + maps__for_each_entry(maps, rb_node) { + map = rb_node->map; if (strcmp(map->dso->short_name, name) == 0) { maps->last_search_by_name = map; goto out_unlock; } - + } map = NULL; out_unlock: diff --git a/tools/perf/util/synthetic-events.c b/tools/perf/util/synthetic-events.c index 6def01036eb5..57b95c1d7e39 100644 --- a/tools/perf/util/synthetic-events.c +++ b/tools/perf/util/synthetic-events.c @@ -669,7 +669,7 @@ int perf_event__synthesize_modules(struct perf_tool *tool, perf_event__handler_t struct machine *machine) { int rc = 0; - struct map *pos; + struct map_rb_node *pos; struct maps *maps = machine__kernel_maps(machine); union perf_event *event; size_t size = symbol_conf.buildid_mmap2 ? @@ -692,37 +692,39 @@ int perf_event__synthesize_modules(struct perf_tool *tool, perf_event__handler_t event->header.misc = PERF_RECORD_MISC_GUEST_KERNEL; maps__for_each_entry(maps, pos) { - if (!__map__is_kmodule(pos)) + struct map *map = pos->map; + + if (!__map__is_kmodule(map)) continue; if (symbol_conf.buildid_mmap2) { - size = PERF_ALIGN(pos->dso->long_name_len + 1, sizeof(u64)); + size = PERF_ALIGN(map->dso->long_name_len + 1, sizeof(u64)); event->mmap2.header.type = PERF_RECORD_MMAP2; event->mmap2.header.size = (sizeof(event->mmap2) - (sizeof(event->mmap2.filename) - size)); memset(event->mmap2.filename + size, 0, machine->id_hdr_size); event->mmap2.header.size += machine->id_hdr_size; - event->mmap2.start = pos->start; - event->mmap2.len = pos->end - pos->start; + event->mmap2.start = map->start; + event->mmap2.len = map->end - map->start; event->mmap2.pid = machine->pid; - memcpy(event->mmap2.filename, pos->dso->long_name, - pos->dso->long_name_len + 1); + memcpy(event->mmap2.filename, map->dso->long_name, + map->dso->long_name_len + 1); perf_record_mmap2__read_build_id(&event->mmap2, machine, false); } else { - size = PERF_ALIGN(pos->dso->long_name_len + 1, sizeof(u64)); + size = PERF_ALIGN(map->dso->long_name_len + 1, sizeof(u64)); event->mmap.header.type = PERF_RECORD_MMAP; event->mmap.header.size = (sizeof(event->mmap) - (sizeof(event->mmap.filename) - size)); memset(event->mmap.filename + size, 0, machine->id_hdr_size); event->mmap.header.size += machine->id_hdr_size; - event->mmap.start = pos->start; - event->mmap.len = pos->end - pos->start; + event->mmap.start = map->start; + event->mmap.len = map->end - map->start; event->mmap.pid = machine->pid; - memcpy(event->mmap.filename, pos->dso->long_name, - pos->dso->long_name_len + 1); + memcpy(event->mmap.filename, map->dso->long_name, + map->dso->long_name_len + 1); } if (perf_tool__process_synth_event(tool, event, machine, process) != 0) { diff --git a/tools/perf/util/thread.c b/tools/perf/util/thread.c index a2490a20eb56..24e53bd55f7d 100644 --- a/tools/perf/util/thread.c +++ b/tools/perf/util/thread.c @@ -352,9 +352,7 @@ int thread__insert_map(struct thread *thread, struct map *map) return ret; maps__fixup_overlappings(thread->maps, map, stderr); - maps__insert(thread->maps, map); - - return 0; + return maps__insert(thread->maps, map); } static int __thread__prepare_access(struct thread *thread) @@ -362,12 +360,12 @@ static int __thread__prepare_access(struct thread *thread) bool initialized = false; int err = 0; struct maps *maps = thread->maps; - struct map *map; + struct map_rb_node *rb_node; down_read(&maps->lock); - maps__for_each_entry(maps, map) { - err = unwind__prepare_access(thread->maps, map, &initialized); + maps__for_each_entry(maps, rb_node) { + err = unwind__prepare_access(thread->maps, rb_node->map, &initialized); if (err || initialized) break; } diff --git a/tools/perf/util/unwind-libunwind-local.c b/tools/perf/util/unwind-libunwind-local.c index 81b6bd6e1536..dea70a477b91 100644 --- a/tools/perf/util/unwind-libunwind-local.c +++ b/tools/perf/util/unwind-libunwind-local.c @@ -306,7 +306,7 @@ static int read_unwind_spec_eh_frame(struct dso *dso, struct unwind_info *ui, u64 *table_data, u64 *segbase, u64 *fde_count) { - struct map *map; + struct map_rb_node *map_node; u64 base_addr = UINT64_MAX; int ret, fd; @@ -325,7 +325,9 @@ static int read_unwind_spec_eh_frame(struct dso *dso, struct unwind_info *ui, return -EINVAL; } - maps__for_each_entry(ui->thread->maps, map) { + maps__for_each_entry(ui->thread->maps, map_node) { + struct map *map = map_node->map; + if (map->dso == dso && map->start < base_addr) base_addr = map->start; } diff --git a/tools/perf/util/vdso.c b/tools/perf/util/vdso.c index 43beb169631d..835c39efb80d 100644 --- a/tools/perf/util/vdso.c +++ b/tools/perf/util/vdso.c @@ -144,10 +144,11 @@ static enum dso_type machine__thread_dso_type(struct machine *machine, struct thread *thread) { enum dso_type dso_type = DSO__TYPE_UNKNOWN; - struct map *map; + struct map_rb_node *rb_node; + + maps__for_each_entry(thread->maps, rb_node) { + struct dso *dso = rb_node->map->dso; - maps__for_each_entry(thread->maps, map) { - struct dso *dso = map->dso; if (!dso || dso->long_name[0] != '/') continue; dso_type = dso__type(dso, machine); -- cgit v1.2.3-58-ga151 From 5ab6d715c32f6249415bcd1972bae7e6c03636f0 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 20 Mar 2023 14:22:34 -0700 Subject: perf maps: Add functions to access maps Introduce functions to access struct maps. These functions reduce the number of places reference counting is necessary. While tidying APIs do some small const-ification, in particlar to unwind_libunwind_ops. Committer notes: Fixed up tools/perf/util/unwind-libunwind.c: - return ops->get_entries(cb, arg, thread, data, max_stack); + return ops->get_entries(cb, arg, thread, data, max_stack, best_effort); Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexey Bayduraev Cc: Andi Kleen Cc: Andrew Morton Cc: Andy Shevchenko Cc: Darren Hart Cc: Davidlohr Bueso Cc: Dmitriy Vyukov Cc: Eric Dumazet Cc: German Gomez Cc: Hao Luo Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Madhavan Srinivasan Cc: Mark Rutland Cc: Masami Hiramatsu Cc: Miaoqian Lin Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Riccardo Mancini Cc: Shunsuke Nakamura Cc: Song Liu Cc: Stephane Eranian Cc: Stephen Brennan Cc: Steven Rostedt (VMware) Cc: Thomas Gleixner Cc: Thomas Richter Cc: Yury Norov Link: https://lore.kernel.org/r/20230320212248.1175731-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../perf/scripts/python/Perf-Trace-Util/Context.c | 7 ++- tools/perf/tests/code-reading.c | 2 +- tools/perf/ui/browsers/hists.c | 3 +- tools/perf/util/callchain.c | 9 +-- tools/perf/util/db-export.c | 12 ++-- tools/perf/util/dlfilter.c | 8 ++- tools/perf/util/event.c | 4 +- tools/perf/util/hist.c | 2 +- tools/perf/util/machine.c | 2 +- tools/perf/util/map.c | 14 +++-- tools/perf/util/maps.c | 71 ++++++++++++---------- tools/perf/util/maps.h | 47 +++++++++++--- .../util/scripting-engines/trace-event-python.c | 2 +- tools/perf/util/sort.c | 2 +- tools/perf/util/symbol-elf.c | 2 +- tools/perf/util/symbol.c | 44 +++++++------- tools/perf/util/thread-stack.c | 4 +- tools/perf/util/thread.c | 4 +- tools/perf/util/unwind-libunwind-local.c | 16 ++--- tools/perf/util/unwind-libunwind.c | 31 ++++++---- 20 files changed, 175 insertions(+), 111 deletions(-) (limited to 'tools') diff --git a/tools/perf/scripts/python/Perf-Trace-Util/Context.c b/tools/perf/scripts/python/Perf-Trace-Util/Context.c index b0d449f41650..feedd02b3b3d 100644 --- a/tools/perf/scripts/python/Perf-Trace-Util/Context.c +++ b/tools/perf/scripts/python/Perf-Trace-Util/Context.c @@ -100,10 +100,11 @@ static PyObject *perf_sample_insn(PyObject *obj, PyObject *args) if (!c) return NULL; - if (c->sample->ip && !c->sample->insn_len && - c->al->thread->maps && c->al->thread->maps->machine) - script_fetch_insn(c->sample, c->al->thread, c->al->thread->maps->machine); + if (c->sample->ip && !c->sample->insn_len && c->al->thread->maps) { + struct machine *machine = maps__machine(c->al->thread->maps); + script_fetch_insn(c->sample, c->al->thread, machine); + } if (!c->sample->insn_len) Py_RETURN_NONE; /* N.B. This is a return statement */ diff --git a/tools/perf/tests/code-reading.c b/tools/perf/tests/code-reading.c index fb67fd5ebd9f..8d2036f2f944 100644 --- a/tools/perf/tests/code-reading.c +++ b/tools/perf/tests/code-reading.c @@ -269,7 +269,7 @@ static int read_object_code(u64 addr, size_t len, u8 cpumode, len = al.map->end - addr; /* Read the object code using perf */ - ret_len = dso__data_read_offset(al.map->dso, thread->maps->machine, + ret_len = dso__data_read_offset(al.map->dso, maps__machine(thread->maps), al.addr, buf1, len); if (ret_len != len) { pr_debug("dso__data_read_offset failed\n"); diff --git a/tools/perf/ui/browsers/hists.c b/tools/perf/ui/browsers/hists.c index b72ee6822222..572ff38ceb0f 100644 --- a/tools/perf/ui/browsers/hists.c +++ b/tools/perf/ui/browsers/hists.c @@ -3139,7 +3139,8 @@ do_hotkey: // key came straight from options ui__popup_menu() continue; case 'k': if (browser->selection != NULL) - hists_browser__zoom_map(browser, browser->selection->maps->machine->vmlinux_map); + hists_browser__zoom_map(browser, + maps__machine(browser->selection->maps)->vmlinux_map); continue; case 'V': verbose = (verbose + 1) % 4; diff --git a/tools/perf/util/callchain.c b/tools/perf/util/callchain.c index a093a15f048f..0aa979f64565 100644 --- a/tools/perf/util/callchain.c +++ b/tools/perf/util/callchain.c @@ -1112,6 +1112,8 @@ int hist_entry__append_callchain(struct hist_entry *he, struct perf_sample *samp int fill_callchain_info(struct addr_location *al, struct callchain_cursor_node *node, bool hide_unresolved) { + struct machine *machine = maps__machine(node->ms.maps); + al->maps = node->ms.maps; al->map = node->ms.map; al->sym = node->ms.sym; @@ -1124,9 +1126,8 @@ int fill_callchain_info(struct addr_location *al, struct callchain_cursor_node * if (al->map == NULL) goto out; } - - if (al->maps == machine__kernel_maps(al->maps->machine)) { - if (machine__is_host(al->maps->machine)) { + if (al->maps == machine__kernel_maps(machine)) { + if (machine__is_host(machine)) { al->cpumode = PERF_RECORD_MISC_KERNEL; al->level = 'k'; } else { @@ -1134,7 +1135,7 @@ int fill_callchain_info(struct addr_location *al, struct callchain_cursor_node * al->level = 'g'; } } else { - if (machine__is_host(al->maps->machine)) { + if (machine__is_host(machine)) { al->cpumode = PERF_RECORD_MISC_USER; al->level = '.'; } else if (perf_guest) { diff --git a/tools/perf/util/db-export.c b/tools/perf/util/db-export.c index e0d4f08839fb..1cfcfdd3cf52 100644 --- a/tools/perf/util/db-export.c +++ b/tools/perf/util/db-export.c @@ -181,7 +181,7 @@ static int db_ids_from_al(struct db_export *dbe, struct addr_location *al, if (al->map) { struct dso *dso = al->map->dso; - err = db_export__dso(dbe, dso, al->maps->machine); + err = db_export__dso(dbe, dso, maps__machine(al->maps)); if (err) return err; *dso_db_id = dso->db_id; @@ -354,19 +354,21 @@ int db_export__sample(struct db_export *dbe, union perf_event *event, }; struct thread *main_thread; struct comm *comm = NULL; + struct machine *machine; int err; err = db_export__evsel(dbe, evsel); if (err) return err; - err = db_export__machine(dbe, al->maps->machine); + machine = maps__machine(al->maps); + err = db_export__machine(dbe, machine); if (err) return err; - main_thread = thread__main_thread(al->maps->machine, thread); + main_thread = thread__main_thread(machine, thread); - err = db_export__threads(dbe, thread, main_thread, al->maps->machine, &comm); + err = db_export__threads(dbe, thread, main_thread, machine, &comm); if (err) goto out_put; @@ -380,7 +382,7 @@ int db_export__sample(struct db_export *dbe, union perf_event *event, goto out_put; if (dbe->cpr) { - struct call_path *cp = call_path_from_sample(dbe, al->maps->machine, + struct call_path *cp = call_path_from_sample(dbe, machine, thread, sample, evsel); if (cp) { diff --git a/tools/perf/util/dlfilter.c b/tools/perf/util/dlfilter.c index 37beb7530288..fe2a0752a0f6 100644 --- a/tools/perf/util/dlfilter.c +++ b/tools/perf/util/dlfilter.c @@ -197,8 +197,12 @@ static const __u8 *dlfilter__insn(void *ctx, __u32 *len) if (!al->thread && machine__resolve(d->machine, al, d->sample) < 0) return NULL; - if (al->thread->maps && al->thread->maps->machine) - script_fetch_insn(d->sample, al->thread, al->thread->maps->machine); + if (al->thread->maps) { + struct machine *machine = maps__machine(al->thread->maps); + + if (machine) + script_fetch_insn(d->sample, al->thread, machine); + } } if (!d->sample->insn_len) diff --git a/tools/perf/util/event.c b/tools/perf/util/event.c index 1fa14598b916..f40cdd6ac126 100644 --- a/tools/perf/util/event.c +++ b/tools/perf/util/event.c @@ -572,7 +572,7 @@ struct map *thread__find_map(struct thread *thread, u8 cpumode, u64 addr, struct addr_location *al) { struct maps *maps = thread->maps; - struct machine *machine = maps->machine; + struct machine *machine = maps__machine(maps); bool load_map = false; al->maps = maps; @@ -637,7 +637,7 @@ struct map *thread__find_map_fb(struct thread *thread, u8 cpumode, u64 addr, struct addr_location *al) { struct map *map = thread__find_map(thread, cpumode, addr, al); - struct machine *machine = thread->maps->machine; + struct machine *machine = maps__machine(thread->maps); u8 addr_cpumode = machine__addr_cpumode(machine, cpumode, addr); if (map || addr_cpumode == cpumode) diff --git a/tools/perf/util/hist.c b/tools/perf/util/hist.c index b339ff863fe2..5f9f38ed5da1 100644 --- a/tools/perf/util/hist.c +++ b/tools/perf/util/hist.c @@ -241,7 +241,7 @@ void hists__calc_col_len(struct hists *hists, struct hist_entry *h) if (h->cgroup) { const char *cgrp_name = "unknown"; - struct cgroup *cgrp = cgroup__find(h->ms.maps->machine->env, + struct cgroup *cgrp = cgroup__find(maps__machine(h->ms.maps)->env, h->cgroup); if (cgrp != NULL) cgrp_name = cgrp->name; diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c index 2058623726d2..d6da4b5e1333 100644 --- a/tools/perf/util/machine.c +++ b/tools/perf/util/machine.c @@ -2847,7 +2847,7 @@ static int find_prev_cpumode(struct ip_callchain *chain, struct thread *thread, static u64 get_leaf_frame_caller(struct perf_sample *sample, struct thread *thread, int usr_idx) { - if (machine__normalized_is(thread->maps->machine, "arm64")) + if (machine__normalized_is(maps__machine(thread->maps), "arm64")) return get_leaf_frame_caller_aarch64(sample, thread, usr_idx); else return 0; diff --git a/tools/perf/util/map.c b/tools/perf/util/map.c index 7620cfa114d4..a99dbde656a2 100644 --- a/tools/perf/util/map.c +++ b/tools/perf/util/map.c @@ -234,7 +234,7 @@ bool __map__is_kernel(const struct map *map) { if (!map->dso->kernel) return false; - return machine__kernel_map(map__kmaps((struct map *)map)->machine) == map; + return machine__kernel_map(maps__machine(map__kmaps((struct map *)map))) == map; } bool __map__is_extra_kernel_map(const struct map *map) @@ -475,11 +475,15 @@ u64 map__rip_2objdump(struct map *map, u64 rip) * kcore may not either. However the trampoline object code is on the * main kernel map, so just use that instead. */ - if (kmap && is_entry_trampoline(kmap->name) && kmap->kmaps && kmap->kmaps->machine) { - struct map *kernel_map = machine__kernel_map(kmap->kmaps->machine); + if (kmap && is_entry_trampoline(kmap->name) && kmap->kmaps) { + struct machine *machine = maps__machine(kmap->kmaps); - if (kernel_map) - map = kernel_map; + if (machine) { + struct map *kernel_map = machine__kernel_map(machine); + + if (kernel_map) + map = kernel_map; + } } if (!map->dso->adjust_symbols) diff --git a/tools/perf/util/maps.c b/tools/perf/util/maps.c index 83ec126bcbe5..91bb015caede 100644 --- a/tools/perf/util/maps.c +++ b/tools/perf/util/maps.c @@ -13,7 +13,7 @@ static void maps__init(struct maps *maps, struct machine *machine) { maps->entries = RB_ROOT; - init_rwsem(&maps->lock); + init_rwsem(maps__lock(maps)); maps->machine = machine; maps->last_search_by_name = NULL; maps->nr_maps = 0; @@ -32,7 +32,7 @@ static void __maps__free_maps_by_name(struct maps *maps) static int __maps__insert(struct maps *maps, struct map *map) { - struct rb_node **p = &maps->entries.rb_node; + struct rb_node **p = &maps__entries(maps)->rb_node; struct rb_node *parent = NULL; const u64 ip = map->start; struct map_rb_node *m, *new_rb_node; @@ -54,7 +54,7 @@ static int __maps__insert(struct maps *maps, struct map *map) } rb_link_node(&new_rb_node->rb_node, parent, p); - rb_insert_color(&new_rb_node->rb_node, &maps->entries); + rb_insert_color(&new_rb_node->rb_node, maps__entries(maps)); map__get(map); return 0; } @@ -63,7 +63,7 @@ int maps__insert(struct maps *maps, struct map *map) { int err; - down_write(&maps->lock); + down_write(maps__lock(maps)); err = __maps__insert(maps, map); if (err) goto out; @@ -84,10 +84,11 @@ int maps__insert(struct maps *maps, struct map *map) * If we already performed some search by name, then we need to add the just * inserted map and resort. */ - if (maps->maps_by_name) { - if (maps->nr_maps > maps->nr_maps_allocated) { - int nr_allocate = maps->nr_maps * 2; - struct map **maps_by_name = realloc(maps->maps_by_name, nr_allocate * sizeof(map)); + if (maps__maps_by_name(maps)) { + if (maps__nr_maps(maps) > maps->nr_maps_allocated) { + int nr_allocate = maps__nr_maps(maps) * 2; + struct map **maps_by_name = realloc(maps__maps_by_name(maps), + nr_allocate * sizeof(map)); if (maps_by_name == NULL) { __maps__free_maps_by_name(maps); @@ -97,18 +98,18 @@ int maps__insert(struct maps *maps, struct map *map) maps->maps_by_name = maps_by_name; maps->nr_maps_allocated = nr_allocate; -} - maps->maps_by_name[maps->nr_maps - 1] = map; + } + maps__maps_by_name(maps)[maps__nr_maps(maps) - 1] = map; __maps__sort_by_name(maps); } out: - up_write(&maps->lock); + up_write(maps__lock(maps)); return err; } static void __maps__remove(struct maps *maps, struct map_rb_node *rb_node) { - rb_erase_init(&rb_node->rb_node, &maps->entries); + rb_erase_init(&rb_node->rb_node, maps__entries(maps)); map__put(rb_node->map); free(rb_node); } @@ -117,7 +118,7 @@ void maps__remove(struct maps *maps, struct map *map) { struct map_rb_node *rb_node; - down_write(&maps->lock); + down_write(maps__lock(maps)); if (maps->last_search_by_name == map) maps->last_search_by_name = NULL; @@ -125,9 +126,9 @@ void maps__remove(struct maps *maps, struct map *map) assert(rb_node->map == map); __maps__remove(maps, rb_node); --maps->nr_maps; - if (maps->maps_by_name) + if (maps__maps_by_name(maps)) __maps__free_maps_by_name(maps); - up_write(&maps->lock); + up_write(maps__lock(maps)); } static void __maps__purge(struct maps *maps) @@ -135,7 +136,7 @@ static void __maps__purge(struct maps *maps) struct map_rb_node *pos, *next; maps__for_each_entry_safe(maps, pos, next) { - rb_erase_init(&pos->rb_node, &maps->entries); + rb_erase_init(&pos->rb_node, maps__entries(maps)); map__put(pos->map); free(pos); } @@ -143,9 +144,9 @@ static void __maps__purge(struct maps *maps) static void maps__exit(struct maps *maps) { - down_write(&maps->lock); + down_write(maps__lock(maps)); __maps__purge(maps); - up_write(&maps->lock); + up_write(maps__lock(maps)); } bool maps__empty(struct maps *maps) @@ -170,6 +171,14 @@ void maps__delete(struct maps *maps) free(maps); } +struct maps *maps__get(struct maps *maps) +{ + if (maps) + refcount_inc(&maps->refcnt); + + return maps; +} + void maps__put(struct maps *maps) { if (maps && refcount_dec_and_test(&maps->refcnt)) @@ -195,7 +204,7 @@ struct symbol *maps__find_symbol_by_name(struct maps *maps, const char *name, st struct symbol *sym; struct map_rb_node *pos; - down_read(&maps->lock); + down_read(maps__lock(maps)); maps__for_each_entry(maps, pos) { sym = map__find_symbol_by_name(pos->map, name); @@ -213,7 +222,7 @@ struct symbol *maps__find_symbol_by_name(struct maps *maps, const char *name, st sym = NULL; out: - up_read(&maps->lock); + up_read(maps__lock(maps)); return sym; } @@ -238,7 +247,7 @@ size_t maps__fprintf(struct maps *maps, FILE *fp) size_t printed = 0; struct map_rb_node *pos; - down_read(&maps->lock); + down_read(maps__lock(maps)); maps__for_each_entry(maps, pos) { printed += fprintf(fp, "Map:"); @@ -249,7 +258,7 @@ size_t maps__fprintf(struct maps *maps, FILE *fp) } } - up_read(&maps->lock); + up_read(maps__lock(maps)); return printed; } @@ -260,9 +269,9 @@ int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp) struct rb_node *next, *first; int err = 0; - down_write(&maps->lock); + down_write(maps__lock(maps)); - root = &maps->entries; + root = maps__entries(maps); /* * Find first map where end > map->start. @@ -358,7 +367,7 @@ put_map: err = 0; out: - up_write(&maps->lock); + up_write(maps__lock(maps)); return err; } @@ -371,7 +380,7 @@ int maps__clone(struct thread *thread, struct maps *parent) int err; struct map_rb_node *rb_node; - down_read(&parent->lock); + down_read(maps__lock(parent)); maps__for_each_entry(parent, rb_node) { struct map *new = map__clone(rb_node->map); @@ -394,7 +403,7 @@ int maps__clone(struct thread *thread, struct maps *parent) err = 0; out_unlock: - up_read(&parent->lock); + up_read(maps__lock(parent)); return err; } @@ -415,9 +424,9 @@ struct map *maps__find(struct maps *maps, u64 ip) struct map_rb_node *m; - down_read(&maps->lock); + down_read(maps__lock(maps)); - p = maps->entries.rb_node; + p = maps__entries(maps)->rb_node; while (p != NULL) { m = rb_entry(p, struct map_rb_node, rb_node); if (ip < m->map->start) @@ -430,13 +439,13 @@ struct map *maps__find(struct maps *maps, u64 ip) m = NULL; out: - up_read(&maps->lock); + up_read(maps__lock(maps)); return m ? m->map : NULL; } struct map_rb_node *maps__first(struct maps *maps) { - struct rb_node *first = rb_first(&maps->entries); + struct rb_node *first = rb_first(maps__entries(maps)); if (first) return rb_entry(first, struct map_rb_node, rb_node); diff --git a/tools/perf/util/maps.h b/tools/perf/util/maps.h index 512746ec0f9a..bde3390c7096 100644 --- a/tools/perf/util/maps.h +++ b/tools/perf/util/maps.h @@ -43,7 +43,7 @@ struct maps { unsigned int nr_maps_allocated; #ifdef HAVE_LIBUNWIND_SUPPORT void *addr_space; - struct unwind_libunwind_ops *unwind_libunwind_ops; + const struct unwind_libunwind_ops *unwind_libunwind_ops; #endif }; @@ -58,20 +58,51 @@ struct kmap { struct maps *maps__new(struct machine *machine); void maps__delete(struct maps *maps); bool maps__empty(struct maps *maps); +int maps__clone(struct thread *thread, struct maps *parent); + +struct maps *maps__get(struct maps *maps); +void maps__put(struct maps *maps); -static inline struct maps *maps__get(struct maps *maps) +static inline struct rb_root *maps__entries(struct maps *maps) { - if (maps) - refcount_inc(&maps->refcnt); - return maps; + return &maps->entries; } -void maps__put(struct maps *maps); -int maps__clone(struct thread *thread, struct maps *parent); +static inline struct machine *maps__machine(struct maps *maps) +{ + return maps->machine; +} + +static inline struct rw_semaphore *maps__lock(struct maps *maps) +{ + return &maps->lock; +} + +static inline struct map **maps__maps_by_name(struct maps *maps) +{ + return maps->maps_by_name; +} + +static inline unsigned int maps__nr_maps(const struct maps *maps) +{ + return maps->nr_maps; +} + +#ifdef HAVE_LIBUNWIND_SUPPORT +static inline void *maps__addr_space(struct maps *maps) +{ + return maps->addr_space; +} + +static inline const struct unwind_libunwind_ops *maps__unwind_libunwind_ops(const struct maps *maps) +{ + return maps->unwind_libunwind_ops; +} +#endif + size_t maps__fprintf(struct maps *maps, FILE *fp); int maps__insert(struct maps *maps, struct map *map); - void maps__remove(struct maps *maps, struct map *map); struct symbol *maps__find_symbol(struct maps *maps, u64 addr, struct map **mapp); diff --git a/tools/perf/util/scripting-engines/trace-event-python.c b/tools/perf/util/scripting-engines/trace-event-python.c index 0f4ef61f2ffa..e5cc18f6fcda 100644 --- a/tools/perf/util/scripting-engines/trace-event-python.c +++ b/tools/perf/util/scripting-engines/trace-event-python.c @@ -1288,7 +1288,7 @@ static void python_export_sample_table(struct db_export *dbe, tuple_set_d64(t, 0, es->db_id); tuple_set_d64(t, 1, es->evsel->db_id); - tuple_set_d64(t, 2, es->al->maps->machine->db_id); + tuple_set_d64(t, 2, maps__machine(es->al->maps)->db_id); tuple_set_d64(t, 3, es->al->thread->db_id); tuple_set_d64(t, 4, es->comm_db_id); tuple_set_d64(t, 5, es->dso_db_id); diff --git a/tools/perf/util/sort.c b/tools/perf/util/sort.c index 2b5cc8e4aa6e..430f67e7cc82 100644 --- a/tools/perf/util/sort.c +++ b/tools/perf/util/sort.c @@ -803,7 +803,7 @@ static int hist_entry__cgroup_snprintf(struct hist_entry *he, const char *cgrp_name = "N/A"; if (he->cgroup) { - struct cgroup *cgrp = cgroup__find(he->ms.maps->machine->env, + struct cgroup *cgrp = cgroup__find(maps__machine(he->ms.maps)->env, he->cgroup); if (cgrp != NULL) cgrp_name = cgrp->name; diff --git a/tools/perf/util/symbol-elf.c b/tools/perf/util/symbol-elf.c index 33e1f587baa9..3084e556d3eb 100644 --- a/tools/perf/util/symbol-elf.c +++ b/tools/perf/util/symbol-elf.c @@ -1428,7 +1428,7 @@ static int dso__process_kernel_symbol(struct dso *dso, struct map *map, * we still are sure to have a reference to this DSO via * *curr_map->dso. */ - dsos__add(&kmaps->machine->dsos, curr_dso); + dsos__add(&maps__machine(kmaps)->dsos, curr_dso); /* kmaps already got it */ map__put(curr_map); dso__set_loaded(curr_dso); diff --git a/tools/perf/util/symbol.c b/tools/perf/util/symbol.c index e7a8ae290c57..316b63fb5691 100644 --- a/tools/perf/util/symbol.c +++ b/tools/perf/util/symbol.c @@ -275,7 +275,7 @@ void maps__fixup_end(struct maps *maps) { struct map_rb_node *prev = NULL, *curr; - down_write(&maps->lock); + down_write(maps__lock(maps)); maps__for_each_entry(maps, curr) { if (prev != NULL && !prev->map->end) @@ -291,7 +291,7 @@ void maps__fixup_end(struct maps *maps) if (curr && !curr->map->end) curr->map->end = ~0ULL; - up_write(&maps->lock); + up_write(maps__lock(maps)); } struct symbol *symbol__new(u64 start, u64 len, u8 binding, u8 type, const char *name) @@ -844,7 +844,7 @@ static int maps__split_kallsyms(struct maps *kmaps, struct dso *dso, u64 delta, if (!kmaps) return -1; - machine = kmaps->machine; + machine = maps__machine(kmaps); x86_64 = machine__is(machine, "x86_64"); @@ -968,7 +968,7 @@ discard_symbol: if (curr_map != initial_map && dso->kernel == DSO_SPACE__KERNEL_GUEST && - machine__is_default_guest(kmaps->machine)) { + machine__is_default_guest(maps__machine(kmaps))) { dso__set_loaded(curr_map->dso); } @@ -1365,7 +1365,7 @@ static int dso__load_kcore(struct dso *dso, struct map *map, if (!kmaps) return -EINVAL; - machine = kmaps->machine; + machine = maps__machine(kmaps); /* This function requires that the map is the kernel map */ if (!__map__is_kernel(map)) @@ -1894,7 +1894,7 @@ int dso__load(struct dso *dso, struct map *map) else if (dso->kernel == DSO_SPACE__KERNEL_GUEST) ret = dso__load_guest_kernel_sym(dso, map); - machine = map__kmaps(map)->machine; + machine = maps__machine(map__kmaps(map)); if (machine__is(machine, "x86_64")) machine__map_x86_64_entry_trampolines(machine, dso); goto out; @@ -2059,32 +2059,32 @@ static int map__strcmp_name(const void *name, const void *b) void __maps__sort_by_name(struct maps *maps) { - qsort(maps->maps_by_name, maps->nr_maps, sizeof(struct map *), map__strcmp); + qsort(maps__maps_by_name(maps), maps__nr_maps(maps), sizeof(struct map *), map__strcmp); } static int map__groups__sort_by_name_from_rbtree(struct maps *maps) { struct map_rb_node *rb_node; - struct map **maps_by_name = realloc(maps->maps_by_name, - maps->nr_maps * sizeof(struct map *)); + struct map **maps_by_name = realloc(maps__maps_by_name(maps), + maps__nr_maps(maps) * sizeof(struct map *)); int i = 0; if (maps_by_name == NULL) return -1; - up_read(&maps->lock); - down_write(&maps->lock); + up_read(maps__lock(maps)); + down_write(maps__lock(maps)); maps->maps_by_name = maps_by_name; - maps->nr_maps_allocated = maps->nr_maps; + maps->nr_maps_allocated = maps__nr_maps(maps); maps__for_each_entry(maps, rb_node) maps_by_name[i++] = rb_node->map; __maps__sort_by_name(maps); - up_write(&maps->lock); - down_read(&maps->lock); + up_write(maps__lock(maps)); + down_read(maps__lock(maps)); return 0; } @@ -2093,11 +2093,12 @@ static struct map *__maps__find_by_name(struct maps *maps, const char *name) { struct map **mapp; - if (maps->maps_by_name == NULL && + if (maps__maps_by_name(maps) == NULL && map__groups__sort_by_name_from_rbtree(maps)) return NULL; - mapp = bsearch(name, maps->maps_by_name, maps->nr_maps, sizeof(*mapp), map__strcmp_name); + mapp = bsearch(name, maps__maps_by_name(maps), maps__nr_maps(maps), + sizeof(*mapp), map__strcmp_name); if (mapp) return *mapp; return NULL; @@ -2108,9 +2109,10 @@ struct map *maps__find_by_name(struct maps *maps, const char *name) struct map_rb_node *rb_node; struct map *map; - down_read(&maps->lock); + down_read(maps__lock(maps)); - if (maps->last_search_by_name && strcmp(maps->last_search_by_name->dso->short_name, name) == 0) { + if (maps->last_search_by_name && + strcmp(maps->last_search_by_name->dso->short_name, name) == 0) { map = maps->last_search_by_name; goto out_unlock; } @@ -2120,7 +2122,7 @@ struct map *maps__find_by_name(struct maps *maps, const char *name) * made. */ map = __maps__find_by_name(maps, name); - if (map || maps->maps_by_name != NULL) + if (map || maps__maps_by_name(maps) != NULL) goto out_unlock; /* Fallback to traversing the rbtree... */ @@ -2134,7 +2136,7 @@ struct map *maps__find_by_name(struct maps *maps, const char *name) map = NULL; out_unlock: - up_read(&maps->lock); + up_read(maps__lock(maps)); return map; } @@ -2386,7 +2388,7 @@ static int dso__load_guest_kernel_sym(struct dso *dso, struct map *map) { int err; const char *kallsyms_filename; - struct machine *machine = map__kmaps(map)->machine; + struct machine *machine = maps__machine(map__kmaps(map)); char path[PATH_MAX]; if (machine->kallsyms_filename) { diff --git a/tools/perf/util/thread-stack.c b/tools/perf/util/thread-stack.c index 1b992bbba4e8..4b85c1728012 100644 --- a/tools/perf/util/thread-stack.c +++ b/tools/perf/util/thread-stack.c @@ -155,8 +155,8 @@ static int thread_stack__init(struct thread_stack *ts, struct thread *thread, ts->br_stack_sz = br_stack_sz; } - if (thread->maps && thread->maps->machine) { - struct machine *machine = thread->maps->machine; + if (thread->maps && maps__machine(thread->maps)) { + struct machine *machine = maps__machine(thread->maps); const char *arch = perf_env__arch(machine->env); ts->kernel_start = machine__kernel_start(machine); diff --git a/tools/perf/util/thread.c b/tools/perf/util/thread.c index 24e53bd55f7d..292585a52281 100644 --- a/tools/perf/util/thread.c +++ b/tools/perf/util/thread.c @@ -362,7 +362,7 @@ static int __thread__prepare_access(struct thread *thread) struct maps *maps = thread->maps; struct map_rb_node *rb_node; - down_read(&maps->lock); + down_read(maps__lock(maps)); maps__for_each_entry(maps, rb_node) { err = unwind__prepare_access(thread->maps, rb_node->map, &initialized); @@ -370,7 +370,7 @@ static int __thread__prepare_access(struct thread *thread) break; } - up_read(&maps->lock); + up_read(maps__lock(maps)); return err; } diff --git a/tools/perf/util/unwind-libunwind-local.c b/tools/perf/util/unwind-libunwind-local.c index dea70a477b91..c487a249b33c 100644 --- a/tools/perf/util/unwind-libunwind-local.c +++ b/tools/perf/util/unwind-libunwind-local.c @@ -667,24 +667,26 @@ static unw_accessors_t accessors = { static int _unwind__prepare_access(struct maps *maps) { - maps->addr_space = unw_create_addr_space(&accessors, 0); - if (!maps->addr_space) { + void *addr_space = unw_create_addr_space(&accessors, 0); + + maps->addr_space = addr_space; + if (!addr_space) { pr_err("unwind: Can't create unwind address space.\n"); return -ENOMEM; } - unw_set_caching_policy(maps->addr_space, UNW_CACHE_GLOBAL); + unw_set_caching_policy(addr_space, UNW_CACHE_GLOBAL); return 0; } static void _unwind__flush_access(struct maps *maps) { - unw_flush_cache(maps->addr_space, 0, 0); + unw_flush_cache(maps__addr_space(maps), 0, 0); } static void _unwind__finish_access(struct maps *maps) { - unw_destroy_addr_space(maps->addr_space); + unw_destroy_addr_space(maps__addr_space(maps)); } static int get_entries(struct unwind_info *ui, unwind_entry_cb_t cb, @@ -709,7 +711,7 @@ static int get_entries(struct unwind_info *ui, unwind_entry_cb_t cb, */ if (max_stack - 1 > 0) { WARN_ONCE(!ui->thread, "WARNING: ui->thread is NULL"); - addr_space = ui->thread->maps->addr_space; + addr_space = maps__addr_space(ui->thread->maps); if (addr_space == NULL) return -1; @@ -759,7 +761,7 @@ static int _unwind__get_entries(unwind_entry_cb_t cb, void *arg, struct unwind_info ui = { .sample = data, .thread = thread, - .machine = thread->maps->machine, + .machine = maps__machine(thread->maps), .best_effort = best_effort }; diff --git a/tools/perf/util/unwind-libunwind.c b/tools/perf/util/unwind-libunwind.c index 509c287ee762..42528ade513e 100644 --- a/tools/perf/util/unwind-libunwind.c +++ b/tools/perf/util/unwind-libunwind.c @@ -22,12 +22,13 @@ int unwind__prepare_access(struct maps *maps, struct map *map, bool *initialized const char *arch; enum dso_type dso_type; struct unwind_libunwind_ops *ops = local_unwind_libunwind_ops; + struct machine *machine; int err; if (!dwarf_callchain_users) return 0; - if (maps->addr_space) { + if (maps__addr_space(maps)) { pr_debug("unwind: thread map already set, dso=%s\n", map->dso->name); if (initialized) @@ -35,15 +36,16 @@ int unwind__prepare_access(struct maps *maps, struct map *map, bool *initialized return 0; } + machine = maps__machine(maps); /* env->arch is NULL for live-mode (i.e. perf top) */ - if (!maps->machine->env || !maps->machine->env->arch) + if (!machine->env || !machine->env->arch) goto out_register; - dso_type = dso__type(map->dso, maps->machine); + dso_type = dso__type(map->dso, machine); if (dso_type == DSO__TYPE_UNKNOWN) return 0; - arch = perf_env__arch(maps->machine->env); + arch = perf_env__arch(machine->env); if (!strcmp(arch, "x86")) { if (dso_type != DSO__TYPE_64BIT) @@ -60,7 +62,7 @@ int unwind__prepare_access(struct maps *maps, struct map *map, bool *initialized out_register: unwind__register_ops(maps, ops); - err = maps->unwind_libunwind_ops->prepare_access(maps); + err = maps__unwind_libunwind_ops(maps)->prepare_access(maps); if (initialized) *initialized = err ? false : true; return err; @@ -68,14 +70,18 @@ out_register: void unwind__flush_access(struct maps *maps) { - if (maps->unwind_libunwind_ops) - maps->unwind_libunwind_ops->flush_access(maps); + const struct unwind_libunwind_ops *ops = maps__unwind_libunwind_ops(maps); + + if (ops) + ops->flush_access(maps); } void unwind__finish_access(struct maps *maps) { - if (maps->unwind_libunwind_ops) - maps->unwind_libunwind_ops->finish_access(maps); + const struct unwind_libunwind_ops *ops = maps__unwind_libunwind_ops(maps); + + if (ops) + ops->finish_access(maps); } int unwind__get_entries(unwind_entry_cb_t cb, void *arg, @@ -83,8 +89,9 @@ int unwind__get_entries(unwind_entry_cb_t cb, void *arg, struct perf_sample *data, int max_stack, bool best_effort) { - if (thread->maps->unwind_libunwind_ops) - return thread->maps->unwind_libunwind_ops->get_entries(cb, arg, thread, data, - max_stack, best_effort); + const struct unwind_libunwind_ops *ops = maps__unwind_libunwind_ops(thread->maps); + + if (ops) + return ops->get_entries(cb, arg, thread, data, max_stack, best_effort); return 0; } -- cgit v1.2.3-58-ga151 From 63df0e4bc368adbd12ed70ed4789d8d52d65661d Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 20 Mar 2023 14:22:35 -0700 Subject: perf map: Add accessor for dso Later changes will add reference count checking for struct map, with dso being the most frequently accessed variable. Add an accessor so that the reference count check is only necessary in one place. Additional changes: - add a dso variable to avoid repeated map__dso calls. - in builtin-mem.c dump_raw_samples, code only partially tested for dso == NULL. Make the possibility of NULL consistent. - in thread.c thread__memcpy fix use of spaces and use tabs. Committer notes: Did missing conversions on these files: tools/perf/arch/powerpc/util/skip-callchain-idx.c tools/perf/arch/powerpc/util/sym-handling.c tools/perf/ui/browsers/hists.c tools/perf/ui/gtk/annotate.c tools/perf/util/cs-etm.c tools/perf/util/thread.c tools/perf/util/unwind-libunwind-local.c tools/perf/util/unwind-libunwind.c Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexey Bayduraev Cc: Andi Kleen Cc: Andrew Morton Cc: Andy Shevchenko Cc: Darren Hart Cc: Davidlohr Bueso Cc: Dmitriy Vyukov Cc: Eric Dumazet Cc: German Gomez Cc: Hao Luo Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Madhavan Srinivasan Cc: Mark Rutland Cc: Masami Hiramatsu Cc: Miaoqian Lin Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Riccardo Mancini Cc: Shunsuke Nakamura Cc: Song Liu Cc: Stephane Eranian Cc: Stephen Brennan Cc: Steven Rostedt (VMware) Cc: Thomas Gleixner Cc: Thomas Richter Cc: Yury Norov Link: https://lore.kernel.org/r/20230320212248.1175731-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/powerpc/util/skip-callchain-idx.c | 2 +- tools/perf/arch/powerpc/util/sym-handling.c | 2 +- tools/perf/builtin-annotate.c | 11 +-- tools/perf/builtin-buildid-list.c | 2 +- tools/perf/builtin-inject.c | 8 +- tools/perf/builtin-kallsyms.c | 4 +- tools/perf/builtin-mem.c | 10 ++- tools/perf/builtin-report.c | 7 +- tools/perf/builtin-script.c | 19 +++-- tools/perf/builtin-top.c | 11 ++- tools/perf/builtin-trace.c | 2 +- .../perf/scripts/python/Perf-Trace-Util/Context.c | 6 +- tools/perf/tests/code-reading.c | 28 ++++--- tools/perf/tests/hists_common.c | 8 +- tools/perf/tests/hists_cumulate.c | 4 +- tools/perf/tests/hists_filter.c | 4 +- tools/perf/tests/hists_output.c | 2 +- tools/perf/tests/maps.c | 2 +- tools/perf/tests/symbols.c | 6 +- tools/perf/tests/vmlinux-kallsyms.c | 13 +-- tools/perf/ui/browsers/annotate.c | 9 +- tools/perf/ui/browsers/hists.c | 17 ++-- tools/perf/ui/browsers/map.c | 4 +- tools/perf/ui/gtk/annotate.c | 5 +- tools/perf/util/annotate.c | 16 ++-- tools/perf/util/auxtrace.c | 2 +- tools/perf/util/block-info.c | 4 +- tools/perf/util/bpf-event.c | 10 ++- tools/perf/util/build-id.c | 2 +- tools/perf/util/callchain.c | 6 +- tools/perf/util/cs-etm.c | 17 ++-- tools/perf/util/data-convert-json.c | 10 ++- tools/perf/util/db-export.c | 4 +- tools/perf/util/dlfilter.c | 10 ++- tools/perf/util/event.c | 9 +- tools/perf/util/evsel_fprintf.c | 2 +- tools/perf/util/hist.c | 10 +-- tools/perf/util/intel-pt.c | 45 +++++----- tools/perf/util/machine.c | 70 +++++++++------- tools/perf/util/map.c | 96 ++++++++++++++-------- tools/perf/util/map.h | 7 +- tools/perf/util/maps.c | 7 +- tools/perf/util/probe-event.c | 30 ++++--- .../perf/util/scripting-engines/trace-event-perl.c | 10 ++- .../util/scripting-engines/trace-event-python.c | 16 ++-- tools/perf/util/sort.c | 49 +++++------ tools/perf/util/symbol-elf.c | 2 +- tools/perf/util/symbol.c | 55 ++++++++----- tools/perf/util/synthetic-events.c | 12 +-- tools/perf/util/thread.c | 30 ++++--- tools/perf/util/unwind-libdw.c | 10 +-- tools/perf/util/unwind-libunwind-local.c | 31 ++++--- tools/perf/util/unwind-libunwind.c | 6 +- tools/perf/util/vdso.c | 2 +- 54 files changed, 447 insertions(+), 319 deletions(-) (limited to 'tools') diff --git a/tools/perf/arch/powerpc/util/skip-callchain-idx.c b/tools/perf/arch/powerpc/util/skip-callchain-idx.c index 20cd6244863b..fe0e4530673c 100644 --- a/tools/perf/arch/powerpc/util/skip-callchain-idx.c +++ b/tools/perf/arch/powerpc/util/skip-callchain-idx.c @@ -255,7 +255,7 @@ int arch_skip_callchain_idx(struct thread *thread, struct ip_callchain *chain) thread__find_symbol(thread, PERF_RECORD_MISC_USER, ip, &al); if (al.map) - dso = al.map->dso; + dso = map__dso(al.map); if (!dso) { pr_debug("%" PRIx64 " dso is NULL\n", ip); diff --git a/tools/perf/arch/powerpc/util/sym-handling.c b/tools/perf/arch/powerpc/util/sym-handling.c index 0856b32f9e08..9f99fc88dbff 100644 --- a/tools/perf/arch/powerpc/util/sym-handling.c +++ b/tools/perf/arch/powerpc/util/sym-handling.c @@ -104,7 +104,7 @@ void arch__fix_tev_from_maps(struct perf_probe_event *pev, lep_offset = PPC64_LOCAL_ENTRY_OFFSET(sym->arch_sym); - if (map->dso->symtab_type == DSO_BINARY_TYPE__KALLSYMS) + if (map__dso(map)->symtab_type == DSO_BINARY_TYPE__KALLSYMS) tev->point.offset += PPC64LE_LEP_OFFSET; else if (lep_offset) { if (pev->uprobes) diff --git a/tools/perf/builtin-annotate.c b/tools/perf/builtin-annotate.c index 655987afef58..63fd2080b803 100644 --- a/tools/perf/builtin-annotate.c +++ b/tools/perf/builtin-annotate.c @@ -205,7 +205,7 @@ static int process_branch_callback(struct evsel *evsel, return 0; if (a.map != NULL) - a.map->dso->hit = 1; + map__dso(a.map)->hit = 1; hist__account_cycles(sample->branch_stack, al, sample, false, NULL); @@ -235,10 +235,11 @@ static int evsel__add_sample(struct evsel *evsel, struct perf_sample *sample, * the DSO? */ if (al->sym != NULL) { - rb_erase_cached(&al->sym->rb_node, - &al->map->dso->symbols); + struct dso *dso = map__dso(al->map); + + rb_erase_cached(&al->sym->rb_node, &dso->symbols); symbol__delete(al->sym); - dso__reset_find_symbol_cache(al->map->dso); + dso__reset_find_symbol_cache(dso); } return 0; } @@ -320,7 +321,7 @@ static void hists__find_annotations(struct hists *hists, struct hist_entry *he = rb_entry(nd, struct hist_entry, rb_node); struct annotation *notes; - if (he->ms.sym == NULL || he->ms.map->dso->annotate_warned) + if (he->ms.sym == NULL || map__dso(he->ms.map)->annotate_warned) goto find_next; if (ann->sym_hist_filter && diff --git a/tools/perf/builtin-buildid-list.c b/tools/perf/builtin-buildid-list.c index 00bfe89f0b5d..cad9ed44ce7c 100644 --- a/tools/perf/builtin-buildid-list.c +++ b/tools/perf/builtin-buildid-list.c @@ -24,7 +24,7 @@ static int buildid__map_cb(struct map *map, void *arg __maybe_unused) { - const struct dso *dso = map->dso; + const struct dso *dso = map__dso(map); char bid_buf[SBUILD_ID_SIZE]; memset(bid_buf, 0, sizeof(bid_buf)); diff --git a/tools/perf/builtin-inject.c b/tools/perf/builtin-inject.c index 10bb1d494258..8f6909dd8a54 100644 --- a/tools/perf/builtin-inject.c +++ b/tools/perf/builtin-inject.c @@ -753,9 +753,11 @@ int perf_event__inject_buildid(struct perf_tool *tool, union perf_event *event, } if (thread__find_map(thread, sample->cpumode, sample->ip, &al)) { - if (!al.map->dso->hit) { - al.map->dso->hit = 1; - dso__inject_build_id(al.map->dso, tool, machine, + struct dso *dso = map__dso(al.map); + + if (!dso->hit) { + dso->hit = 1; + dso__inject_build_id(dso, tool, machine, sample->cpumode, al.map->flags); } } diff --git a/tools/perf/builtin-kallsyms.c b/tools/perf/builtin-kallsyms.c index c08ee81529e8..5638ca4dbd8e 100644 --- a/tools/perf/builtin-kallsyms.c +++ b/tools/perf/builtin-kallsyms.c @@ -28,6 +28,7 @@ static int __cmd_kallsyms(int argc, const char **argv) for (i = 0; i < argc; ++i) { struct map *map; + const struct dso *dso; struct symbol *symbol = machine__find_kernel_symbol_by_name(machine, argv[i], &map); if (symbol == NULL) { @@ -35,8 +36,9 @@ static int __cmd_kallsyms(int argc, const char **argv) continue; } + dso = map__dso(map); printf("%s: %s %s %#" PRIx64 "-%#" PRIx64 " (%#" PRIx64 "-%#" PRIx64")\n", - symbol->name, map->dso->short_name, map->dso->long_name, + symbol->name, dso->short_name, dso->long_name, map->unmap_ip(map, symbol->start), map->unmap_ip(map, symbol->end), symbol->start, symbol->end); } diff --git a/tools/perf/builtin-mem.c b/tools/perf/builtin-mem.c index dedd612eae5e..1e27188b0de1 100644 --- a/tools/perf/builtin-mem.c +++ b/tools/perf/builtin-mem.c @@ -200,6 +200,7 @@ dump_raw_samples(struct perf_tool *tool, struct addr_location al; const char *fmt, *field_sep; char str[PAGE_SIZE_NAME_LEN]; + struct dso *dso = NULL; if (machine__resolve(machine, &al, sample) < 0) { fprintf(stderr, "problem processing %d event, skipping it.\n", @@ -210,8 +211,11 @@ dump_raw_samples(struct perf_tool *tool, if (al.filtered || (mem->hide_unresolved && al.sym == NULL)) goto out_put; - if (al.map != NULL) - al.map->dso->hit = 1; + if (al.map != NULL) { + dso = map__dso(al.map); + if (dso) + dso->hit = 1; + } field_sep = symbol_conf.field_sep; if (field_sep) { @@ -252,7 +256,7 @@ dump_raw_samples(struct perf_tool *tool, symbol_conf.field_sep, sample->data_src, symbol_conf.field_sep, - al.map ? (al.map->dso ? al.map->dso->long_name : "???") : "???", + dso ? dso->long_name : "???", al.sym ? al.sym->name : "???"); out_put: addr_location__put(&al); diff --git a/tools/perf/builtin-report.c b/tools/perf/builtin-report.c index c7e3863e8f44..ff239b89e4d0 100644 --- a/tools/perf/builtin-report.c +++ b/tools/perf/builtin-report.c @@ -319,7 +319,7 @@ static int process_sample_event(struct perf_tool *tool, } if (al.map != NULL) - al.map->dso->hit = 1; + map__dso(al.map)->hit = 1; if (ui__has_annotation() || rep->symbol_ipc || rep->total_cycles_mode) { hist__account_cycles(sample->branch_stack, &al, sample, @@ -608,7 +608,7 @@ static void report__warn_kptr_restrict(const struct report *rep) return; if (kernel_map == NULL || - (kernel_map->dso->hit && + (map__dso(kernel_map)->hit && (kernel_kmap->ref_reloc_sym == NULL || kernel_kmap->ref_reloc_sym->addr == 0))) { const char *desc = @@ -848,6 +848,7 @@ static size_t maps__fprintf_task(struct maps *maps, int indent, FILE *fp) maps__for_each_entry(maps, rb_node) { struct map *map = rb_node->map; + const struct dso *dso = map__dso(map); printed += fprintf(fp, "%*s %" PRIx64 "-%" PRIx64 " %c%c%c%c %08" PRIx64 " %" PRIu64 " %s\n", indent, "", map->start, map->end, @@ -856,7 +857,7 @@ static size_t maps__fprintf_task(struct maps *maps, int indent, FILE *fp) map->prot & PROT_EXEC ? 'x' : '-', map->flags & MAP_SHARED ? 's' : 'p', map->pgoff, - map->dso->id.ino, map->dso->name); + dso->id.ino, dso->name); } return printed; diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index c9296d8b33c0..27fd9c203600 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -1011,11 +1011,11 @@ static int perf_sample__fprintf_brstackoff(struct perf_sample *sample, to = entries[i].to; if (thread__find_map_fb(thread, sample->cpumode, from, &alf) && - !alf.map->dso->adjust_symbols) + !map__dso(alf.map)->adjust_symbols) from = map__map_ip(alf.map, from); if (thread__find_map_fb(thread, sample->cpumode, to, &alt) && - !alt.map->dso->adjust_symbols) + !map__dso(alt.map)->adjust_symbols) to = map__map_ip(alt.map, to); printed += fprintf(fp, " 0x%"PRIx64, from); @@ -1044,6 +1044,7 @@ static int grab_bb(u8 *buffer, u64 start, u64 end, long offset, len; struct addr_location al; bool kernel; + struct dso *dso; if (!start || !end) return 0; @@ -1074,11 +1075,12 @@ static int grab_bb(u8 *buffer, u64 start, u64 end, return 0; } - if (!thread__find_map(thread, *cpumode, start, &al) || !al.map->dso) { + dso = map__dso(al.map); + if (!thread__find_map(thread, *cpumode, start, &al) || !dso) { pr_debug("\tcannot resolve %" PRIx64 "-%" PRIx64 "\n", start, end); return 0; } - if (al.map->dso->data.status == DSO_DATA_STATUS_ERROR) { + if (dso->data.status == DSO_DATA_STATUS_ERROR) { pr_debug("\tcannot resolve %" PRIx64 "-%" PRIx64 "\n", start, end); return 0; } @@ -1087,10 +1089,10 @@ static int grab_bb(u8 *buffer, u64 start, u64 end, map__load(al.map); offset = al.map->map_ip(al.map, start); - len = dso__data_read_offset(al.map->dso, machine, offset, (u8 *)buffer, + len = dso__data_read_offset(dso, machine, offset, (u8 *)buffer, end - start + MAXINSN); - *is64bit = al.map->dso->is_64_bit; + *is64bit = dso->is_64_bit; if (len <= 0) pr_debug("\tcannot fetch code for block at %" PRIx64 "-%" PRIx64 "\n", start, end); @@ -1104,10 +1106,11 @@ static int map__fprintf_srccode(struct map *map, u64 addr, FILE *fp, struct srcc unsigned line; int len; char *srccode; + struct dso *dso = map__dso(map); - if (!map || !map->dso) + if (!map || !dso) return 0; - srcfile = get_srcline_split(map->dso, + srcfile = get_srcline_split(dso, map__rip_2objdump(map, addr), &line); if (!srcfile) diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c index 2c985cfea517..babfc163efe2 100644 --- a/tools/perf/builtin-top.c +++ b/tools/perf/builtin-top.c @@ -114,6 +114,7 @@ static int perf_top__parse_source(struct perf_top *top, struct hist_entry *he) struct symbol *sym; struct annotation *notes; struct map *map; + struct dso *dso; int err = -1; if (!he || !he->ms.sym) @@ -123,12 +124,12 @@ static int perf_top__parse_source(struct perf_top *top, struct hist_entry *he) sym = he->ms.sym; map = he->ms.map; + dso = map__dso(map); /* * We can't annotate with just /proc/kallsyms */ - if (map->dso->symtab_type == DSO_BINARY_TYPE__KALLSYMS && - !dso__is_kcore(map->dso)) { + if (dso->symtab_type == DSO_BINARY_TYPE__KALLSYMS && !dso__is_kcore(dso)) { pr_err("Can't annotate %s: No vmlinux file was found in the " "path\n", sym->name); sleep(1); @@ -169,6 +170,7 @@ static void ui__warn_map_erange(struct map *map, struct symbol *sym, u64 ip) { struct utsname uts; int err = uname(&uts); + struct dso *dso = map__dso(map); ui__warning("Out of bounds address found:\n\n" "Addr: %" PRIx64 "\n" @@ -180,7 +182,7 @@ static void ui__warn_map_erange(struct map *map, struct symbol *sym, u64 ip) "Tools: %s\n\n" "Not all samples will be on the annotation output.\n\n" "Please report to linux-kernel@vger.kernel.org\n", - ip, map->dso->long_name, dso__symtab_origin(map->dso), + ip, dso->long_name, dso__symtab_origin(dso), map->start, map->end, sym->start, sym->end, sym->binding == STB_GLOBAL ? 'g' : sym->binding == STB_LOCAL ? 'l' : 'w', sym->name, @@ -810,7 +812,8 @@ static void perf_event__process_sample(struct perf_tool *tool, __map__is_kernel(al.map) && map__has_symbols(al.map)) { if (symbol_conf.vmlinux_name) { char serr[256]; - dso__strerror_load(al.map->dso, serr, sizeof(serr)); + + dso__strerror_load(map__dso(al.map), serr, sizeof(serr)); ui__warning("The %s file can't be used: %s\n%s", symbol_conf.vmlinux_name, serr, msg); } else { diff --git a/tools/perf/builtin-trace.c b/tools/perf/builtin-trace.c index b363c609818b..72ef0bebb06b 100644 --- a/tools/perf/builtin-trace.c +++ b/tools/perf/builtin-trace.c @@ -2863,7 +2863,7 @@ static void print_location(FILE *f, struct perf_sample *sample, { if ((verbose > 0 || print_dso) && al->map) - fprintf(f, "%s@", al->map->dso->long_name); + fprintf(f, "%s@", map__dso(al->map)->long_name); if ((verbose > 0 || print_sym) && al->sym) fprintf(f, "%s+0x%" PRIx64, al->sym->name, diff --git a/tools/perf/scripts/python/Perf-Trace-Util/Context.c b/tools/perf/scripts/python/Perf-Trace-Util/Context.c index feedd02b3b3d..53b1587db403 100644 --- a/tools/perf/scripts/python/Perf-Trace-Util/Context.c +++ b/tools/perf/scripts/python/Perf-Trace-Util/Context.c @@ -145,6 +145,7 @@ static PyObject *perf_sample_src(PyObject *obj, PyObject *args, bool get_srccode char *srccode = NULL; PyObject *result; struct map *map; + struct dso *dso; int len = 0; u64 addr; @@ -153,9 +154,10 @@ static PyObject *perf_sample_src(PyObject *obj, PyObject *args, bool get_srccode map = c->al->map; addr = c->al->addr; + dso = map ? map__dso(map) : NULL; - if (map && map->dso) - srcfile = get_srcline_split(map->dso, map__rip_2objdump(map, addr), &line); + if (dso) + srcfile = get_srcline_split(dso, map__rip_2objdump(map, addr), &line); if (get_srccode) { if (srcfile) diff --git a/tools/perf/tests/code-reading.c b/tools/perf/tests/code-reading.c index 8d2036f2f944..936c61546e64 100644 --- a/tools/perf/tests/code-reading.c +++ b/tools/perf/tests/code-reading.c @@ -237,10 +237,11 @@ static int read_object_code(u64 addr, size_t len, u8 cpumode, char decomp_name[KMOD_DECOMP_LEN]; bool decomp = false; int ret, err = 0; + struct dso *dso; pr_debug("Reading object code for memory address: %#"PRIx64"\n", addr); - if (!thread__find_map(thread, cpumode, addr, &al) || !al.map->dso) { + if (!thread__find_map(thread, cpumode, addr, &al) || !map__dso(al.map)) { if (cpumode == PERF_RECORD_MISC_HYPERVISOR) { pr_debug("Hypervisor address can not be resolved - skipping\n"); goto out; @@ -250,11 +251,10 @@ static int read_object_code(u64 addr, size_t len, u8 cpumode, err = -1; goto out; } + dso = map__dso(al.map); + pr_debug("File is: %s\n", dso->long_name); - pr_debug("File is: %s\n", al.map->dso->long_name); - - if (al.map->dso->symtab_type == DSO_BINARY_TYPE__KALLSYMS && - !dso__is_kcore(al.map->dso)) { + if (dso->symtab_type == DSO_BINARY_TYPE__KALLSYMS && !dso__is_kcore(dso)) { pr_debug("Unexpected kernel address - skipping\n"); goto out; } @@ -269,7 +269,7 @@ static int read_object_code(u64 addr, size_t len, u8 cpumode, len = al.map->end - addr; /* Read the object code using perf */ - ret_len = dso__data_read_offset(al.map->dso, maps__machine(thread->maps), + ret_len = dso__data_read_offset(dso, maps__machine(thread->maps), al.addr, buf1, len); if (ret_len != len) { pr_debug("dso__data_read_offset failed\n"); @@ -287,7 +287,7 @@ static int read_object_code(u64 addr, size_t len, u8 cpumode, } /* objdump struggles with kcore - try each map only once */ - if (dso__is_kcore(al.map->dso)) { + if (dso__is_kcore(dso)) { size_t d; for (d = 0; d < state->done_cnt; d++) { @@ -304,9 +304,9 @@ static int read_object_code(u64 addr, size_t len, u8 cpumode, state->done[state->done_cnt++] = al.map->start; } - objdump_name = al.map->dso->long_name; - if (dso__needs_decompress(al.map->dso)) { - if (dso__decompress_kmodule_path(al.map->dso, objdump_name, + objdump_name = dso->long_name; + if (dso__needs_decompress(dso)) { + if (dso__decompress_kmodule_path(dso, objdump_name, decomp_name, sizeof(decomp_name)) < 0) { pr_debug("decompression failed\n"); @@ -335,7 +335,7 @@ static int read_object_code(u64 addr, size_t len, u8 cpumode, len -= ret; if (len) { pr_debug("Reducing len to %zu\n", len); - } else if (dso__is_kcore(al.map->dso)) { + } else if (dso__is_kcore(dso)) { /* * objdump cannot handle very large segments * that may be found in kcore. @@ -572,6 +572,7 @@ static int do_test_code_reading(bool try_kcore) pid_t pid; struct map *map; bool have_vmlinux, have_kcore, excl_kernel = false; + struct dso *dso; pid = getpid(); @@ -595,8 +596,9 @@ static int do_test_code_reading(bool try_kcore) pr_debug("map__load failed\n"); goto out_err; } - have_vmlinux = dso__is_vmlinux(map->dso); - have_kcore = dso__is_kcore(map->dso); + dso = map__dso(map); + have_vmlinux = dso__is_vmlinux(dso); + have_kcore = dso__is_kcore(dso); /* 2nd time through we just try kcore */ if (try_kcore && !have_kcore) diff --git a/tools/perf/tests/hists_common.c b/tools/perf/tests/hists_common.c index 6f34d08b84e5..745ab18d17db 100644 --- a/tools/perf/tests/hists_common.c +++ b/tools/perf/tests/hists_common.c @@ -179,9 +179,11 @@ void print_hists_in(struct hists *hists) he = rb_entry(node, struct hist_entry, rb_node_in); if (!he->filtered) { + struct dso *dso = map__dso(he->ms.map); + pr_info("%2d: entry: %-8s [%-8s] %20s: period = %"PRIu64"\n", i, thread__comm_str(he->thread), - he->ms.map->dso->short_name, + dso->short_name, he->ms.sym->name, he->stat.period); } @@ -206,9 +208,11 @@ void print_hists_out(struct hists *hists) he = rb_entry(node, struct hist_entry, rb_node); if (!he->filtered) { + struct dso *dso = map__dso(he->ms.map); + pr_info("%2d: entry: %8s:%5d [%-8s] %20s: period = %"PRIu64"/%"PRIu64"\n", i, thread__comm_str(he->thread), he->thread->tid, - he->ms.map->dso->short_name, + dso->short_name, he->ms.sym->name, he->stat.period, he->stat_acc ? he->stat_acc->period : 0); } diff --git a/tools/perf/tests/hists_cumulate.c b/tools/perf/tests/hists_cumulate.c index b42d37ff2399..f00ec9abdbcd 100644 --- a/tools/perf/tests/hists_cumulate.c +++ b/tools/perf/tests/hists_cumulate.c @@ -150,12 +150,12 @@ static void del_hist_entries(struct hists *hists) typedef int (*test_fn_t)(struct evsel *, struct machine *); #define COMM(he) (thread__comm_str(he->thread)) -#define DSO(he) (he->ms.map->dso->short_name) +#define DSO(he) (map__dso(he->ms.map)->short_name) #define SYM(he) (he->ms.sym->name) #define CPU(he) (he->cpu) #define PID(he) (he->thread->tid) #define DEPTH(he) (he->callchain->max_depth) -#define CDSO(cl) (cl->ms.map->dso->short_name) +#define CDSO(cl) (map__dso(cl->ms.map)->short_name) #define CSYM(cl) (cl->ms.sym->name) struct result { diff --git a/tools/perf/tests/hists_filter.c b/tools/perf/tests/hists_filter.c index 8e1ceeb9b7b6..7c552549f4a4 100644 --- a/tools/perf/tests/hists_filter.c +++ b/tools/perf/tests/hists_filter.c @@ -194,7 +194,7 @@ static int test__hists_filter(struct test_suite *test __maybe_unused, int subtes hists__filter_by_thread(hists); /* now applying dso filter for 'kernel' */ - hists->dso_filter = fake_samples[0].map->dso; + hists->dso_filter = map__dso(fake_samples[0].map); hists__filter_by_dso(hists); if (verbose > 2) { @@ -288,7 +288,7 @@ static int test__hists_filter(struct test_suite *test __maybe_unused, int subtes /* now applying all filters at once. */ hists->thread_filter = fake_samples[1].thread; - hists->dso_filter = fake_samples[1].map->dso; + hists->dso_filter = map__dso(fake_samples[1].map); hists__filter_by_thread(hists); hists__filter_by_dso(hists); diff --git a/tools/perf/tests/hists_output.c b/tools/perf/tests/hists_output.c index 62b0093253e3..428d11a938f2 100644 --- a/tools/perf/tests/hists_output.c +++ b/tools/perf/tests/hists_output.c @@ -116,7 +116,7 @@ static void del_hist_entries(struct hists *hists) typedef int (*test_fn_t)(struct evsel *, struct machine *); #define COMM(he) (thread__comm_str(he->thread)) -#define DSO(he) (he->ms.map->dso->short_name) +#define DSO(he) (map__dso(he->ms.map)->short_name) #define SYM(he) (he->ms.sym->name) #define CPU(he) (he->cpu) #define PID(he) (he->thread->tid) diff --git a/tools/perf/tests/maps.c b/tools/perf/tests/maps.c index 8246d37e4b7a..ae7028fbf79e 100644 --- a/tools/perf/tests/maps.c +++ b/tools/perf/tests/maps.c @@ -26,7 +26,7 @@ static int check_maps(struct map_def *merged, unsigned int size, struct maps *ma TEST_ASSERT_VAL("wrong map start", map->start == merged[i].start); TEST_ASSERT_VAL("wrong map end", map->end == merged[i].end); - TEST_ASSERT_VAL("wrong map name", !strcmp(map->dso->name, merged[i].name)); + TEST_ASSERT_VAL("wrong map name", !strcmp(map__dso(map)->name, merged[i].name)); TEST_ASSERT_VAL("wrong map refcnt", refcount_read(&map->refcnt) == 1); i++; diff --git a/tools/perf/tests/symbols.c b/tools/perf/tests/symbols.c index 0793f8f419e2..2d1aa42d36a9 100644 --- a/tools/perf/tests/symbols.c +++ b/tools/perf/tests/symbols.c @@ -102,6 +102,7 @@ static int test_file(struct test_info *ti, char *filename) { struct map *map = NULL; int ret, nr; + struct dso *dso; pr_debug("Testing %s\n", filename); @@ -109,7 +110,8 @@ static int test_file(struct test_info *ti, char *filename) if (ret != TEST_OK) return ret; - nr = dso__load(map->dso, map); + dso = map__dso(map); + nr = dso__load(dso, map); if (nr < 0) { pr_debug("dso__load() failed!\n"); ret = TEST_FAIL; @@ -122,7 +124,7 @@ static int test_file(struct test_info *ti, char *filename) goto out_put; } - ret = test_dso(map->dso); + ret = test_dso(dso); out_put: map__put(map); diff --git a/tools/perf/tests/vmlinux-kallsyms.c b/tools/perf/tests/vmlinux-kallsyms.c index c8abb3ca8347..c614c2db7e89 100644 --- a/tools/perf/tests/vmlinux-kallsyms.c +++ b/tools/perf/tests/vmlinux-kallsyms.c @@ -293,15 +293,16 @@ next_pair: maps__for_each_entry(maps, rb_node) { struct map *map = rb_node->map; + struct dso *dso = map__dso(map); /* * If it is the kernel, kallsyms is always "[kernel.kallsyms]", while * the kernel will have the path for the vmlinux file being used, * so use the short name, less descriptive but the same ("[kernel]" in * both cases. */ - struct map *pair = maps__find_by_name(kallsyms.kmaps, (map->dso->kernel ? - map->dso->short_name : - map->dso->name)); + struct map *pair = maps__find_by_name(kallsyms.kmaps, (dso->kernel ? + dso->short_name : + dso->name)); if (pair) { pair->priv = 1; } else { @@ -326,17 +327,19 @@ next_pair: continue; if (pair->start == mem_start) { + struct dso *dso = map__dso(map); + if (!header_printed) { pr_info("WARN: Maps in vmlinux with a different name in kallsyms:\n"); header_printed = true; } pr_info("WARN: %" PRIx64 "-%" PRIx64 " %" PRIx64 " %s in kallsyms as", - map->start, map->end, map->pgoff, map->dso->name); + map->start, map->end, map->pgoff, dso->name); if (mem_end != pair->end) pr_info(":\nWARN: *%" PRIx64 "-%" PRIx64 " %" PRIx64, pair->start, pair->end, pair->pgoff); - pr_info(" %s\n", pair->dso->name); + pr_info(" %s\n", dso->name); pair->priv = 1; } } diff --git a/tools/perf/ui/browsers/annotate.c b/tools/perf/ui/browsers/annotate.c index c03fa76c02ff..12c3ce530e42 100644 --- a/tools/perf/ui/browsers/annotate.c +++ b/tools/perf/ui/browsers/annotate.c @@ -441,7 +441,8 @@ static void ui_browser__init_asm_mode(struct ui_browser *browser) static int sym_title(struct symbol *sym, struct map *map, char *title, size_t sz, int percent_type) { - return snprintf(title, sz, "%s %s [Percent: %s]", sym->name, map->dso->long_name, + return snprintf(title, sz, "%s %s [Percent: %s]", sym->name, + map__dso(map)->long_name, percent_type_str(percent_type)); } @@ -964,20 +965,22 @@ int symbol__tui_annotate(struct map_symbol *ms, struct evsel *evsel, }, .opts = opts, }; + struct dso *dso; int ret = -1, err; int not_annotated = list_empty(¬es->src->source); if (sym == NULL) return -1; - if (ms->map->dso->annotate_warned) + dso = map__dso(ms->map); + if (dso->annotate_warned) return -1; if (not_annotated) { err = symbol__annotate2(ms, evsel, opts, &browser.arch); if (err) { char msg[BUFSIZ]; - ms->map->dso->annotate_warned = true; + dso->annotate_warned = true; symbol__strerror_disassemble(ms, err, msg, sizeof(msg)); ui__error("Couldn't annotate %s:\n%s", sym->name, msg); goto out_free_offsets; diff --git a/tools/perf/ui/browsers/hists.c b/tools/perf/ui/browsers/hists.c index 572ff38ceb0f..9f9f622325ae 100644 --- a/tools/perf/ui/browsers/hists.c +++ b/tools/perf/ui/browsers/hists.c @@ -2487,7 +2487,7 @@ static struct symbol *symbol__new_unresolved(u64 addr, struct map *map) return NULL; } - dso__insert_symbol(map->dso, sym); + dso__insert_symbol(map__dso(map), sym); } return sym; @@ -2499,7 +2499,9 @@ add_annotate_opt(struct hist_browser *browser __maybe_unused, struct map_symbol *ms, u64 addr) { - if (!ms->map || !ms->map->dso || ms->map->dso->annotate_warned) + struct dso *dso = map__dso(ms->map); + + if (!ms->map || !dso || dso->annotate_warned) return 0; if (!ms->sym) @@ -2589,9 +2591,10 @@ static int hists_browser__zoom_map(struct hist_browser *browser, struct map *map browser->hists->dso_filter = NULL; ui_helpline__pop(); } else { + struct dso *dso = map__dso(map); ui_helpline__fpush("To zoom out press ESC or ENTER + \"Zoom out of %s DSO\"", - __map__is_kernel(map) ? "the Kernel" : map->dso->short_name); - browser->hists->dso_filter = map->dso; + __map__is_kernel(map) ? "the Kernel" : dso->short_name); + browser->hists->dso_filter = dso; perf_hpp__set_elide(HISTC_DSO, true); pstack__push(browser->pstack, &browser->hists->dso_filter); } @@ -2616,7 +2619,7 @@ add_dso_opt(struct hist_browser *browser, struct popup_action *act, if (asprintf(optstr, "Zoom %s %s DSO (use the 'k' hotkey to zoom directly into the kernel)", browser->hists->dso_filter ? "out of" : "into", - __map__is_kernel(map) ? "the Kernel" : map->dso->short_name) < 0) + __map__is_kernel(map) ? "the Kernel" : map__dso(map)->short_name) < 0) return 0; act->ms.map = map; @@ -3091,8 +3094,8 @@ do_hotkey: // key came straight from options ui__popup_menu() if (!browser->selection || !browser->selection->map || - !browser->selection->map->dso || - browser->selection->map->dso->annotate_warned) { + !map__dso(browser->selection->map) || + map__dso(browser->selection->map)->annotate_warned) { continue; } diff --git a/tools/perf/ui/browsers/map.c b/tools/perf/ui/browsers/map.c index 3d49b916c9e4..3d1b958d8832 100644 --- a/tools/perf/ui/browsers/map.c +++ b/tools/perf/ui/browsers/map.c @@ -76,7 +76,7 @@ static int map_browser__run(struct map_browser *browser) { int key; - if (ui_browser__show(&browser->b, browser->map->dso->long_name, + if (ui_browser__show(&browser->b, map__dso(browser->map)->long_name, "Press ESC to exit, %s / to search", verbose > 0 ? "" : "restart with -v to use") < 0) return -1; @@ -106,7 +106,7 @@ int map__browse(struct map *map) { struct map_browser mb = { .b = { - .entries = &map->dso->symbols, + .entries = &map__dso(map)->symbols, .refresh = ui_browser__rb_tree_refresh, .seek = ui_browser__rb_tree_seek, .write = map_browser__write, diff --git a/tools/perf/ui/gtk/annotate.c b/tools/perf/ui/gtk/annotate.c index a1c021a6d3c1..2effac77ca8c 100644 --- a/tools/perf/ui/gtk/annotate.c +++ b/tools/perf/ui/gtk/annotate.c @@ -165,6 +165,7 @@ static int symbol__gtk_annotate(struct map_symbol *ms, struct evsel *evsel, struct annotation_options *options, struct hist_browser_timer *hbt) { + struct dso *dso = map__dso(ms->map); struct symbol *sym = ms->sym; GtkWidget *window; GtkWidget *notebook; @@ -172,13 +173,13 @@ static int symbol__gtk_annotate(struct map_symbol *ms, struct evsel *evsel, GtkWidget *tab_label; int err; - if (ms->map->dso->annotate_warned) + if (dso->annotate_warned) return -1; err = symbol__annotate(ms, evsel, options, NULL); if (err) { char msg[BUFSIZ]; - ms->map->dso->annotate_warned = true; + dso->annotate_warned = true; symbol__strerror_disassemble(ms, err, msg, sizeof(msg)); ui__error("Couldn't annotate %s: %s\n", sym->name, msg); return -1; diff --git a/tools/perf/util/annotate.c b/tools/perf/util/annotate.c index f47b5dde66bc..84100ca5f306 100644 --- a/tools/perf/util/annotate.c +++ b/tools/perf/util/annotate.c @@ -1585,7 +1585,7 @@ static void delete_last_nop(struct symbol *sym) int symbol__strerror_disassemble(struct map_symbol *ms, int errnum, char *buf, size_t buflen) { - struct dso *dso = ms->map->dso; + struct dso *dso = map__dso(ms->map); BUG_ON(buflen == 0); @@ -1727,7 +1727,7 @@ static int symbol__disassemble_bpf(struct symbol *sym, struct map *map = args->ms.map; struct perf_bpil *info_linear; struct disassemble_info info; - struct dso *dso = map->dso; + struct dso *dso = map__dso(map); int pc = 0, count, sub_id; struct btf *btf = NULL; char tpath[PATH_MAX]; @@ -1950,7 +1950,7 @@ static int symbol__disassemble(struct symbol *sym, struct annotate_args *args) { struct annotation_options *opts = args->options; struct map *map = args->ms.map; - struct dso *dso = map->dso; + struct dso *dso = map__dso(map); char *command; FILE *file; char symfs_filename[PATH_MAX]; @@ -2395,7 +2395,7 @@ int symbol__annotate_printf(struct map_symbol *ms, struct evsel *evsel, { struct map *map = ms->map; struct symbol *sym = ms->sym; - struct dso *dso = map->dso; + struct dso *dso = map__dso(map); char *filename; const char *d_filename; const char *evsel_name = evsel__name(evsel); @@ -2578,7 +2578,7 @@ int map_symbol__annotation_dump(struct map_symbol *ms, struct evsel *evsel, } fprintf(fp, "%s() %s\nEvent: %s\n\n", - ms->sym->name, ms->map->dso->long_name, ev_name); + ms->sym->name, map__dso(ms->map)->long_name, ev_name); symbol__annotate_fprintf2(ms->sym, fp, opts); fclose(fp); @@ -2804,7 +2804,7 @@ static void annotation__calc_lines(struct annotation *notes, struct map *map, if (percent_max <= 0.5) continue; - al->path = get_srcline(map->dso, notes->start + al->offset, NULL, + al->path = get_srcline(map__dso(map), notes->start + al->offset, NULL, false, true, notes->start + al->offset); insert_source_line(&tmp_root, al, opts); } @@ -2823,7 +2823,7 @@ static void symbol__calc_lines(struct map_symbol *ms, struct rb_root *root, int symbol__tty_annotate2(struct map_symbol *ms, struct evsel *evsel, struct annotation_options *opts) { - struct dso *dso = ms->map->dso; + struct dso *dso = map__dso(ms->map); struct symbol *sym = ms->sym; struct rb_root source_line = RB_ROOT; struct hists *hists = evsel__hists(evsel); @@ -2859,7 +2859,7 @@ int symbol__tty_annotate2(struct map_symbol *ms, struct evsel *evsel, int symbol__tty_annotate(struct map_symbol *ms, struct evsel *evsel, struct annotation_options *opts) { - struct dso *dso = ms->map->dso; + struct dso *dso = map__dso(ms->map); struct symbol *sym = ms->sym; struct rb_root source_line = RB_ROOT; int err; diff --git a/tools/perf/util/auxtrace.c b/tools/perf/util/auxtrace.c index b2a5e5397bad..a0368202a746 100644 --- a/tools/perf/util/auxtrace.c +++ b/tools/perf/util/auxtrace.c @@ -2560,7 +2560,7 @@ static struct dso *load_dso(const char *name) if (map__load(map) < 0) pr_err("File '%s' not found or has no symbols.\n", name); - dso = dso__get(map->dso); + dso = dso__get(map__dso(map)); map__put(map); diff --git a/tools/perf/util/block-info.c b/tools/perf/util/block-info.c index 5ecd4f401f32..16a7b4adcf18 100644 --- a/tools/perf/util/block-info.c +++ b/tools/perf/util/block-info.c @@ -317,9 +317,9 @@ static int block_dso_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, struct block_fmt *block_fmt = container_of(fmt, struct block_fmt, fmt); struct map *map = he->ms.map; - if (map && map->dso) { + if (map && map__dso(map)) { return scnprintf(hpp->buf, hpp->size, "%*s", block_fmt->width, - map->dso->short_name); + map__dso(map)->short_name); } return scnprintf(hpp->buf, hpp->size, "%*s", block_fmt->width, diff --git a/tools/perf/util/bpf-event.c b/tools/perf/util/bpf-event.c index 025f331b3867..38fcf3ba5749 100644 --- a/tools/perf/util/bpf-event.c +++ b/tools/perf/util/bpf-event.c @@ -57,10 +57,12 @@ static int machine__process_bpf_event_load(struct machine *machine, struct map *map = maps__find(machine__kernel_maps(machine), addr); if (map) { - map->dso->binary_type = DSO_BINARY_TYPE__BPF_PROG_INFO; - map->dso->bpf_prog.id = id; - map->dso->bpf_prog.sub_id = i; - map->dso->bpf_prog.env = env; + struct dso *dso = map__dso(map); + + dso->binary_type = DSO_BINARY_TYPE__BPF_PROG_INFO; + dso->bpf_prog.id = id; + dso->bpf_prog.sub_id = i; + dso->bpf_prog.env = env; } } return 0; diff --git a/tools/perf/util/build-id.c b/tools/perf/util/build-id.c index ea9c083ab1e3..06a8cd88cbef 100644 --- a/tools/perf/util/build-id.c +++ b/tools/perf/util/build-id.c @@ -59,7 +59,7 @@ int build_id__mark_dso_hit(struct perf_tool *tool __maybe_unused, } if (thread__find_map(thread, sample->cpumode, sample->ip, &al)) - al.map->dso->hit = 1; + map__dso(al.map)->hit = 1; thread__put(thread); return 0; diff --git a/tools/perf/util/callchain.c b/tools/perf/util/callchain.c index 0aa979f64565..9e9c39dd9d2b 100644 --- a/tools/perf/util/callchain.c +++ b/tools/perf/util/callchain.c @@ -701,8 +701,8 @@ static enum match_result match_chain_strings(const char *left, static enum match_result match_chain_dso_addresses(struct map *left_map, u64 left_ip, struct map *right_map, u64 right_ip) { - struct dso *left_dso = left_map ? left_map->dso : NULL; - struct dso *right_dso = right_map ? right_map->dso : NULL; + struct dso *left_dso = left_map ? map__dso(left_map) : NULL; + struct dso *right_dso = right_map ? map__dso(right_map) : NULL; if (left_dso != right_dso) return left_dso < right_dso ? MATCH_LT : MATCH_GT; @@ -1174,7 +1174,7 @@ char *callchain_list__sym_name(struct callchain_list *cl, if (show_dso) scnprintf(bf + printed, bfsize - printed, " %s", cl->ms.map ? - cl->ms.map->dso->short_name : + map__dso(cl->ms.map)->short_name : "unknown"); return bf; diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 94e2d02009eb..528a7fb066cf 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -865,6 +865,7 @@ static u32 cs_etm__mem_access(struct cs_etm_queue *etmq, u8 trace_chan_id, struct thread *thread; struct machine *machine; struct addr_location al; + struct dso *dso; struct cs_etm_traceid_queue *tidq; if (!etmq) @@ -883,27 +884,29 @@ static u32 cs_etm__mem_access(struct cs_etm_queue *etmq, u8 trace_chan_id, thread = etmq->etm->unknown_thread; } - if (!thread__find_map(thread, cpumode, address, &al) || !al.map->dso) + dso = map__dso(al.map); + + if (!thread__find_map(thread, cpumode, address, &al) || !dso) return 0; - if (al.map->dso->data.status == DSO_DATA_STATUS_ERROR && - dso__data_status_seen(al.map->dso, DSO_DATA_STATUS_SEEN_ITRACE)) + if (dso->data.status == DSO_DATA_STATUS_ERROR && + dso__data_status_seen(dso, DSO_DATA_STATUS_SEEN_ITRACE)) return 0; offset = al.map->map_ip(al.map, address); map__load(al.map); - len = dso__data_read_offset(al.map->dso, machine, offset, buffer, size); + len = dso__data_read_offset(dso, machine, offset, buffer, size); if (len <= 0) { ui__warning_once("CS ETM Trace: Missing DSO. Use 'perf archive' or debuginfod to export data from the traced system.\n" " Enable CONFIG_PROC_KCORE or use option '-k /path/to/vmlinux' for kernel symbols.\n"); - if (!al.map->dso->auxtrace_warned) { + if (!dso->auxtrace_warned) { pr_err("CS ETM Trace: Debug data not found for address %#"PRIx64" in %s\n", address, - al.map->dso->long_name ? al.map->dso->long_name : "Unknown"); - al.map->dso->auxtrace_warned = true; + dso->long_name ? dso->long_name : "Unknown"); + dso->auxtrace_warned = true; } return 0; } diff --git a/tools/perf/util/data-convert-json.c b/tools/perf/util/data-convert-json.c index ba9d93ce9463..653709ab867a 100644 --- a/tools/perf/util/data-convert-json.c +++ b/tools/perf/util/data-convert-json.c @@ -128,15 +128,17 @@ static void output_sample_callchain_entry(struct perf_tool *tool, output_json_key_format(out, false, 5, "ip", "\"0x%" PRIx64 "\"", ip); if (al && al->sym && al->sym->namelen) { + struct dso *dso = al->map ? map__dso(al->map) : NULL; + fputc(',', out); output_json_key_string(out, false, 5, "symbol", al->sym->name); - if (al->map && al->map->dso) { - const char *dso = al->map->dso->short_name; + if (dso) { + const char *dso_name = dso->short_name; - if (dso && strlen(dso) > 0) { + if (dso_name && strlen(dso_name) > 0) { fputc(',', out); - output_json_key_string(out, false, 5, "dso", dso); + output_json_key_string(out, false, 5, "dso", dso_name); } } } diff --git a/tools/perf/util/db-export.c b/tools/perf/util/db-export.c index 1cfcfdd3cf52..84c970c11794 100644 --- a/tools/perf/util/db-export.c +++ b/tools/perf/util/db-export.c @@ -179,7 +179,7 @@ static int db_ids_from_al(struct db_export *dbe, struct addr_location *al, int err; if (al->map) { - struct dso *dso = al->map->dso; + struct dso *dso = map__dso(al->map); err = db_export__dso(dbe, dso, maps__machine(al->maps)); if (err) @@ -255,7 +255,7 @@ static struct call_path *call_path_from_sample(struct db_export *dbe, al.addr = node->ip; if (al.map && !al.sym) - al.sym = dso__find_symbol(al.map->dso, al.addr); + al.sym = dso__find_symbol(map__dso(al.map), al.addr); db_ids_from_al(dbe, &al, &dso_db_id, &sym_db_id, &offset); diff --git a/tools/perf/util/dlfilter.c b/tools/perf/util/dlfilter.c index fe2a0752a0f6..8a7ffe0d805a 100644 --- a/tools/perf/util/dlfilter.c +++ b/tools/perf/util/dlfilter.c @@ -29,7 +29,7 @@ static void al_to_d_al(struct addr_location *al, struct perf_dlfilter_al *d_al) d_al->size = sizeof(*d_al); if (al->map) { - struct dso *dso = al->map->dso; + struct dso *dso = map__dso(al->map); if (symbol_conf.show_kernel_path && dso->long_name) d_al->dso = dso->long_name; @@ -220,6 +220,7 @@ static const char *dlfilter__srcline(void *ctx, __u32 *line_no) unsigned int line = 0; char *srcfile = NULL; struct map *map; + struct dso *dso; u64 addr; if (!d->ctx_valid || !line_no) @@ -231,9 +232,10 @@ static const char *dlfilter__srcline(void *ctx, __u32 *line_no) map = al->map; addr = al->addr; + dso = map ? map__dso(map) : NULL; - if (map && map->dso) - srcfile = get_srcline_split(map->dso, map__rip_2objdump(map, addr), &line); + if (dso) + srcfile = get_srcline_split(dso, map__rip_2objdump(map, addr), &line); *line_no = line; return srcfile; @@ -279,7 +281,7 @@ have_map: offset = map->map_ip(map, ip); if (ip + len >= map->end) len = map->end - ip; - return dso__data_read_offset(map->dso, d->machine, offset, buf, len); + return dso__data_read_offset(map__dso(map), d->machine, offset, buf, len); } static const struct perf_dlfilter_fns perf_dlfilter_fns = { diff --git a/tools/perf/util/event.c b/tools/perf/util/event.c index f40cdd6ac126..2ddc75dee019 100644 --- a/tools/perf/util/event.c +++ b/tools/perf/util/event.c @@ -685,6 +685,7 @@ int machine__resolve(struct machine *machine, struct addr_location *al, struct perf_sample *sample) { struct thread *thread; + struct dso *dso; if (symbol_conf.guest_code && !machine__is_host(machine)) thread = machine__findnew_guest_code(machine, sample->pid); @@ -695,9 +696,11 @@ int machine__resolve(struct machine *machine, struct addr_location *al, dump_printf(" ... thread: %s:%d\n", thread__comm_str(thread), thread->tid); thread__find_map(thread, sample->cpumode, sample->ip, al); + dso = al->map ? map__dso(al->map) : NULL; dump_printf(" ...... dso: %s\n", - al->map ? al->map->dso->long_name : - al->level == 'H' ? "[hypervisor]" : ""); + dso + ? dso->long_name + : (al->level == 'H' ? "[hypervisor]" : "")); if (thread__is_filtered(thread)) al->filtered |= (1 << HIST_FILTER__THREAD); @@ -715,8 +718,6 @@ int machine__resolve(struct machine *machine, struct addr_location *al, } if (al->map) { - struct dso *dso = al->map->dso; - if (symbol_conf.dso_list && (!dso || !(strlist__has_entry(symbol_conf.dso_list, dso->short_name) || diff --git a/tools/perf/util/evsel_fprintf.c b/tools/perf/util/evsel_fprintf.c index bd22c4932d10..dff5d8c4b06d 100644 --- a/tools/perf/util/evsel_fprintf.c +++ b/tools/perf/util/evsel_fprintf.c @@ -155,7 +155,7 @@ int sample__fprintf_callchain(struct perf_sample *sample, int left_alignment, if (print_ip) { /* Show binary offset for userspace addr */ - if (map && !map->dso->kernel) + if (map && !map__dso(map)->kernel) printed += fprintf(fp, "%c%16" PRIx64, s, addr); else printed += fprintf(fp, "%c%16" PRIx64, s, node->ip); diff --git a/tools/perf/util/hist.c b/tools/perf/util/hist.c index 5f9f38ed5da1..e494425cad06 100644 --- a/tools/perf/util/hist.c +++ b/tools/perf/util/hist.c @@ -106,7 +106,7 @@ void hists__calc_col_len(struct hists *hists, struct hist_entry *h) hists__set_col_len(hists, HISTC_THREAD, len + 8); if (h->ms.map) { - len = dso__name_len(h->ms.map->dso); + len = dso__name_len(map__dso(h->ms.map)); hists__new_col_len(hists, HISTC_DSO, len); } @@ -120,7 +120,7 @@ void hists__calc_col_len(struct hists *hists, struct hist_entry *h) symlen += BITS_PER_LONG / 4 + 2 + 3; hists__new_col_len(hists, HISTC_SYMBOL_FROM, symlen); - symlen = dso__name_len(h->branch_info->from.ms.map->dso); + symlen = dso__name_len(map__dso(h->branch_info->from.ms.map)); hists__new_col_len(hists, HISTC_DSO_FROM, symlen); } else { symlen = unresolved_col_width + 4 + 2; @@ -135,7 +135,7 @@ void hists__calc_col_len(struct hists *hists, struct hist_entry *h) symlen += BITS_PER_LONG / 4 + 2 + 3; hists__new_col_len(hists, HISTC_SYMBOL_TO, symlen); - symlen = dso__name_len(h->branch_info->to.ms.map->dso); + symlen = dso__name_len(map__dso(h->branch_info->to.ms.map)); hists__new_col_len(hists, HISTC_DSO_TO, symlen); } else { symlen = unresolved_col_width + 4 + 2; @@ -180,7 +180,7 @@ void hists__calc_col_len(struct hists *hists, struct hist_entry *h) } if (h->mem_info->daddr.ms.map) { - symlen = dso__name_len(h->mem_info->daddr.ms.map->dso); + symlen = dso__name_len(map__dso(h->mem_info->daddr.ms.map)); hists__new_col_len(hists, HISTC_MEM_DADDR_DSO, symlen); } else { @@ -2110,7 +2110,7 @@ static bool hists__filter_entry_by_dso(struct hists *hists, struct hist_entry *he) { if (hists->dso_filter != NULL && - (he->ms.map == NULL || he->ms.map->dso != hists->dso_filter)) { + (he->ms.map == NULL || map__dso(he->ms.map) != hists->dso_filter)) { he->filtered |= (1 << HIST_FILTER__DSO); return true; } diff --git a/tools/perf/util/intel-pt.c b/tools/perf/util/intel-pt.c index 955c1b9dc6a4..8cec88e09792 100644 --- a/tools/perf/util/intel-pt.c +++ b/tools/perf/util/intel-pt.c @@ -801,17 +801,19 @@ static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn, } while (1) { - if (!thread__find_map(thread, cpumode, *ip, &al) || !al.map->dso) { + struct dso *dso; + + if (!thread__find_map(thread, cpumode, *ip, &al) || !map__dso(al.map)) { if (al.map) intel_pt_log("ERROR: thread has no dso for %#" PRIx64 "\n", *ip); else intel_pt_log("ERROR: thread has no map for %#" PRIx64 "\n", *ip); return -EINVAL; } + dso = map__dso(al.map); - if (al.map->dso->data.status == DSO_DATA_STATUS_ERROR && - dso__data_status_seen(al.map->dso, - DSO_DATA_STATUS_SEEN_ITRACE)) + if (dso->data.status == DSO_DATA_STATUS_ERROR && + dso__data_status_seen(dso, DSO_DATA_STATUS_SEEN_ITRACE)) return -ENOENT; offset = al.map->map_ip(al.map, *ip); @@ -819,7 +821,7 @@ static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn, if (!to_ip && one_map) { struct intel_pt_cache_entry *e; - e = intel_pt_cache_lookup(al.map->dso, machine, offset); + e = intel_pt_cache_lookup(dso, machine, offset); if (e && (!max_insn_cnt || e->insn_cnt <= max_insn_cnt)) { *insn_cnt_ptr = e->insn_cnt; @@ -829,8 +831,7 @@ static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn, intel_pt_insn->emulated_ptwrite = e->emulated_ptwrite; intel_pt_insn->length = e->length; intel_pt_insn->rel = e->rel; - memcpy(intel_pt_insn->buf, e->insn, - INTEL_PT_INSN_BUF_SZ); + memcpy(intel_pt_insn->buf, e->insn, INTEL_PT_INSN_BUF_SZ); intel_pt_log_insn_no_data(intel_pt_insn, *ip); return 0; } @@ -842,17 +843,17 @@ static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn, /* Load maps to ensure dso->is_64_bit has been updated */ map__load(al.map); - x86_64 = al.map->dso->is_64_bit; + x86_64 = dso->is_64_bit; while (1) { - len = dso__data_read_offset(al.map->dso, machine, + len = dso__data_read_offset(dso, machine, offset, buf, INTEL_PT_INSN_BUF_SZ); if (len <= 0) { intel_pt_log("ERROR: failed to read at offset %#" PRIx64 " ", offset); if (intel_pt_enable_logging) - dso__fprintf(al.map->dso, intel_pt_log_fp()); + dso__fprintf(dso, intel_pt_log_fp()); return -EINVAL; } @@ -871,7 +872,7 @@ static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn, goto out; /* Check for emulated ptwrite */ offs = offset + intel_pt_insn->length; - eptw = intel_pt_emulated_ptwrite(al.map->dso, machine, offs); + eptw = intel_pt_emulated_ptwrite(dso, machine, offs); intel_pt_insn->emulated_ptwrite = eptw; goto out; } @@ -906,13 +907,13 @@ out: if (to_ip) { struct intel_pt_cache_entry *e; - e = intel_pt_cache_lookup(al.map->dso, machine, start_offset); + e = intel_pt_cache_lookup(map__dso(al.map), machine, start_offset); if (e) return 0; } /* Ignore cache errors */ - intel_pt_cache_add(al.map->dso, machine, start_offset, insn_cnt, + intel_pt_cache_add(map__dso(al.map), machine, start_offset, insn_cnt, *ip - start_ip, intel_pt_insn); return 0; @@ -983,13 +984,12 @@ static int __intel_pt_pgd_ip(uint64_t ip, void *data) if (!thread) return -EINVAL; - if (!thread__find_map(thread, cpumode, ip, &al) || !al.map->dso) + if (!thread__find_map(thread, cpumode, ip, &al) || !map__dso(al.map)) return -EINVAL; offset = al.map->map_ip(al.map, ip); - return intel_pt_match_pgd_ip(ptq->pt, ip, offset, - al.map->dso->long_name); + return intel_pt_match_pgd_ip(ptq->pt, ip, offset, map__dso(al.map)->long_name); } static bool intel_pt_pgd_ip(uint64_t ip, void *data) @@ -2744,7 +2744,7 @@ static u64 intel_pt_switch_ip(struct intel_pt *pt, u64 *ptss_ip) if (map__load(map)) return 0; - start = dso__first_symbol(map->dso); + start = dso__first_symbol(map__dso(map)); for (sym = start; sym; sym = dso__next_symbol(sym)) { if (sym->binding == STB_GLOBAL && @@ -3381,18 +3381,21 @@ static int intel_pt_text_poke(struct intel_pt *pt, union perf_event *event) return 0; for (; cnt; cnt--, addr--) { + struct dso *dso; + if (intel_pt_find_map(thread, cpumode, addr, &al)) { if (addr < event->text_poke.addr) return 0; continue; } - if (!al.map->dso || !al.map->dso->auxtrace_cache) + dso = map__dso(al.map); + if (!dso || !dso->auxtrace_cache) continue; offset = al.map->map_ip(al.map, addr); - e = intel_pt_cache_lookup(al.map->dso, machine, offset); + e = intel_pt_cache_lookup(dso, machine, offset); if (!e) continue; @@ -3405,9 +3408,9 @@ static int intel_pt_text_poke(struct intel_pt *pt, union perf_event *event) if (e->branch != INTEL_PT_BR_NO_BRANCH) return 0; } else { - intel_pt_cache_invalidate(al.map->dso, machine, offset); + intel_pt_cache_invalidate(dso, machine, offset); intel_pt_log("Invalidated instruction cache for %s at %#"PRIx64"\n", - al.map->dso->long_name, addr); + dso->long_name, addr); } } diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c index d6da4b5e1333..8bae38c96788 100644 --- a/tools/perf/util/machine.c +++ b/tools/perf/util/machine.c @@ -48,7 +48,7 @@ static int append_inlines(struct callchain_cursor *cursor, struct map_symbol *ms static struct dso *machine__kernel_dso(struct machine *machine) { - return machine->vmlinux_map->dso; + return map__dso(machine->vmlinux_map); } static void dsos__init(struct dsos *dsos) @@ -879,12 +879,13 @@ static int machine__process_ksymbol_register(struct machine *machine, struct perf_sample *sample __maybe_unused) { struct symbol *sym; + struct dso *dso; struct map *map = maps__find(machine__kernel_maps(machine), event->ksymbol.addr); if (!map) { - struct dso *dso = dso__new(event->ksymbol.name); int err; + dso = dso__new(event->ksymbol.name); if (dso) { dso->kernel = DSO_SPACE__KERNEL; map = map__new2(0, dso); @@ -896,9 +897,9 @@ static int machine__process_ksymbol_register(struct machine *machine, } if (event->ksymbol.ksym_type == PERF_RECORD_KSYMBOL_TYPE_OOL) { - map->dso->binary_type = DSO_BINARY_TYPE__OOL; - map->dso->data.file_size = event->ksymbol.len; - dso__set_loaded(map->dso); + dso->binary_type = DSO_BINARY_TYPE__OOL; + dso->data.file_size = event->ksymbol.len; + dso__set_loaded(dso); } map->start = event->ksymbol.addr; @@ -914,6 +915,8 @@ static int machine__process_ksymbol_register(struct machine *machine, dso->binary_type = DSO_BINARY_TYPE__BPF_IMAGE; dso__set_long_name(dso, "", false); } + } else { + dso = map__dso(map); } sym = symbol__new(map->map_ip(map, map->start), @@ -921,7 +924,7 @@ static int machine__process_ksymbol_register(struct machine *machine, 0, 0, event->ksymbol.name); if (!sym) return -ENOMEM; - dso__insert_symbol(map->dso, sym); + dso__insert_symbol(dso, sym); return 0; } @@ -939,9 +942,11 @@ static int machine__process_ksymbol_unregister(struct machine *machine, if (map != machine->vmlinux_map) maps__remove(machine__kernel_maps(machine), map); else { - sym = dso__find_symbol(map->dso, map->map_ip(map, map->start)); + struct dso *dso = map__dso(map); + + sym = dso__find_symbol(dso, map->map_ip(map, map->start)); if (sym) - dso__delete_symbol(map->dso, sym); + dso__delete_symbol(dso, sym); } return 0; @@ -965,6 +970,7 @@ int machine__process_text_poke(struct machine *machine, union perf_event *event, { struct map *map = maps__find(machine__kernel_maps(machine), event->text_poke.addr); u8 cpumode = event->header.misc & PERF_RECORD_MISC_CPUMODE_MASK; + struct dso *dso = map ? map__dso(map) : NULL; if (dump_trace) perf_event__fprintf_text_poke(event, machine, stdout); @@ -977,7 +983,7 @@ int machine__process_text_poke(struct machine *machine, union perf_event *event, return 0; } - if (map && map->dso) { + if (dso) { u8 *new_bytes = event->text_poke.bytes + event->text_poke.old_len; int ret; @@ -986,7 +992,7 @@ int machine__process_text_poke(struct machine *machine, union perf_event *event, * must be done prior to using kernel maps. */ map__load(map); - ret = dso__data_write_cache_addr(map->dso, map, machine, + ret = dso__data_write_cache_addr(dso, map, machine, event->text_poke.addr, new_bytes, event->text_poke.new_len); @@ -1422,10 +1428,11 @@ int machines__create_kernel_maps(struct machines *machines, pid_t pid) int machine__load_kallsyms(struct machine *machine, const char *filename) { struct map *map = machine__kernel_map(machine); - int ret = __dso__load_kallsyms(map->dso, filename, map, true); + struct dso *dso = map__dso(map); + int ret = __dso__load_kallsyms(dso, filename, map, true); if (ret > 0) { - dso__set_loaded(map->dso); + dso__set_loaded(dso); /* * Since /proc/kallsyms will have multiple sessions for the * kernel, with modules between them, fixup the end of all @@ -1440,10 +1447,11 @@ int machine__load_kallsyms(struct machine *machine, const char *filename) int machine__load_vmlinux_path(struct machine *machine) { struct map *map = machine__kernel_map(machine); - int ret = dso__load_vmlinux_path(map->dso, map); + struct dso *dso = map__dso(map); + int ret = dso__load_vmlinux_path(dso, map); if (ret > 0) - dso__set_loaded(map->dso); + dso__set_loaded(dso); return ret; } @@ -1485,6 +1493,7 @@ static bool is_kmod_dso(struct dso *dso) static int maps__set_module_path(struct maps *maps, const char *path, struct kmod_path *m) { char *long_name; + struct dso *dso; struct map *map = maps__find_by_name(maps, m->name); if (map == NULL) @@ -1494,16 +1503,17 @@ static int maps__set_module_path(struct maps *maps, const char *path, struct kmo if (long_name == NULL) return -ENOMEM; - dso__set_long_name(map->dso, long_name, true); - dso__kernel_module_get_build_id(map->dso, ""); + dso = map__dso(map); + dso__set_long_name(dso, long_name, true); + dso__kernel_module_get_build_id(dso, ""); /* * Full name could reveal us kmod compression, so * we need to update the symtab_type if needed. */ - if (m->comp && is_kmod_dso(map->dso)) { - map->dso->symtab_type++; - map->dso->comp = m->comp; + if (m->comp && is_kmod_dso(dso)) { + dso->symtab_type++; + dso->comp = m->comp; } return 0; @@ -1602,7 +1612,7 @@ static int machine__create_module(void *arg, const char *name, u64 start, return -1; map->end = start + size; - dso__kernel_module_get_build_id(map->dso, machine->root_dir); + dso__kernel_module_get_build_id(map__dso(map), machine->root_dir); return 0; } @@ -1788,7 +1798,7 @@ static int machine__process_kernel_mmap_event(struct machine *machine, map->end = map->start + xm->end - xm->start; if (build_id__is_defined(bid)) - dso__set_build_id(map->dso, bid); + dso__set_build_id(map__dso(map), bid); } else if (is_kernel_mmap) { const char *symbol_name = xm->name + strlen(mmap_name); @@ -2248,18 +2258,20 @@ static char *callchain_srcline(struct map_symbol *ms, u64 ip) { struct map *map = ms->map; char *srcline = NULL; + struct dso *dso; if (!map || callchain_param.key == CCKEY_FUNCTION) return srcline; - srcline = srcline__tree_find(&map->dso->srclines, ip); + dso = map__dso(map); + srcline = srcline__tree_find(&dso->srclines, ip); if (!srcline) { bool show_sym = false; bool show_addr = callchain_param.key == CCKEY_ADDRESS; - srcline = get_srcline(map->dso, map__rip_2objdump(map, ip), + srcline = get_srcline(dso, map__rip_2objdump(map, ip), ms->sym, show_sym, show_addr, ip); - srcline__tree_insert(&map->dso->srclines, ip, srcline); + srcline__tree_insert(&dso->srclines, ip, srcline); } return srcline; @@ -3039,6 +3051,7 @@ static int append_inlines(struct callchain_cursor *cursor, struct map_symbol *ms struct map *map = ms->map; struct inline_node *inline_node; struct inline_list *ilist; + struct dso *dso; u64 addr; int ret = 1; @@ -3047,13 +3060,14 @@ static int append_inlines(struct callchain_cursor *cursor, struct map_symbol *ms addr = map__map_ip(map, ip); addr = map__rip_2objdump(map, addr); + dso = map__dso(map); - inline_node = inlines__tree_find(&map->dso->inlined_nodes, addr); + inline_node = inlines__tree_find(&dso->inlined_nodes, addr); if (!inline_node) { - inline_node = dso__parse_addr_inlines(map->dso, addr, sym); + inline_node = dso__parse_addr_inlines(dso, addr, sym); if (!inline_node) return ret; - inlines__tree_insert(&map->dso->inlined_nodes, inline_node); + inlines__tree_insert(&dso->inlined_nodes, inline_node); } list_for_each_entry(ilist, &inline_node->val, list) { @@ -3330,7 +3344,7 @@ char *machine__resolve_kernel_addr(void *vmachine, unsigned long long *addrp, ch if (sym == NULL) return NULL; - *modp = __map__is_kmodule(map) ? (char *)map->dso->short_name : NULL; + *modp = __map__is_kmodule(map) ? (char *)map__dso(map)->short_name : NULL; *addrp = map->unmap_ip(map, sym->start); return sym->name; } diff --git a/tools/perf/util/map.c b/tools/perf/util/map.c index a99dbde656a2..90062af6675a 100644 --- a/tools/perf/util/map.c +++ b/tools/perf/util/map.c @@ -232,7 +232,7 @@ struct map *map__new2(u64 start, struct dso *dso) bool __map__is_kernel(const struct map *map) { - if (!map->dso->kernel) + if (!map__dso(map)->kernel) return false; return machine__kernel_map(maps__machine(map__kmaps((struct map *)map))) == map; } @@ -247,8 +247,9 @@ bool __map__is_extra_kernel_map(const struct map *map) bool __map__is_bpf_prog(const struct map *map) { const char *name; + struct dso *dso = map__dso(map); - if (map->dso->binary_type == DSO_BINARY_TYPE__BPF_PROG_INFO) + if (dso->binary_type == DSO_BINARY_TYPE__BPF_PROG_INFO) return true; /* @@ -256,15 +257,16 @@ bool __map__is_bpf_prog(const struct map *map) * type of DSO_BINARY_TYPE__BPF_PROG_INFO. In such cases, we can * guess the type based on name. */ - name = map->dso->short_name; + name = dso->short_name; return name && (strstr(name, "bpf_prog_") == name); } bool __map__is_bpf_image(const struct map *map) { const char *name; + struct dso *dso = map__dso(map); - if (map->dso->binary_type == DSO_BINARY_TYPE__BPF_IMAGE) + if (dso->binary_type == DSO_BINARY_TYPE__BPF_IMAGE) return true; /* @@ -272,18 +274,20 @@ bool __map__is_bpf_image(const struct map *map) * type of DSO_BINARY_TYPE__BPF_IMAGE. In such cases, we can * guess the type based on name. */ - name = map->dso->short_name; + name = dso->short_name; return name && is_bpf_image(name); } bool __map__is_ool(const struct map *map) { - return map->dso && map->dso->binary_type == DSO_BINARY_TYPE__OOL; + const struct dso *dso = map__dso(map); + + return dso && dso->binary_type == DSO_BINARY_TYPE__OOL; } bool map__has_symbols(const struct map *map) { - return dso__has_symbols(map->dso); + return dso__has_symbols(map__dso(map)); } static void map__exit(struct map *map) @@ -306,18 +310,23 @@ void map__put(struct map *map) void map__fixup_start(struct map *map) { - struct rb_root_cached *symbols = &map->dso->symbols; + struct dso *dso = map__dso(map); + struct rb_root_cached *symbols = &dso->symbols; struct rb_node *nd = rb_first_cached(symbols); + if (nd != NULL) { struct symbol *sym = rb_entry(nd, struct symbol, rb_node); + map->start = sym->start; } } void map__fixup_end(struct map *map) { - struct rb_root_cached *symbols = &map->dso->symbols; + struct dso *dso = map__dso(map); + struct rb_root_cached *symbols = &dso->symbols; struct rb_node *nd = rb_last(&symbols->rb_root); + if (nd != NULL) { struct symbol *sym = rb_entry(nd, struct symbol, rb_node); map->end = sym->end; @@ -328,18 +337,19 @@ void map__fixup_end(struct map *map) int map__load(struct map *map) { - const char *name = map->dso->long_name; + struct dso *dso = map__dso(map); + const char *name = dso->long_name; int nr; - if (dso__loaded(map->dso)) + if (dso__loaded(dso)) return 0; - nr = dso__load(map->dso, map); + nr = dso__load(dso, map); if (nr < 0) { - if (map->dso->has_build_id) { + if (dso->has_build_id) { char sbuild_id[SBUILD_ID_SIZE]; - build_id__sprintf(&map->dso->bid, sbuild_id); + build_id__sprintf(&dso->bid, sbuild_id); pr_debug("%s with build id %s not found", name, sbuild_id); } else pr_debug("Failed to open %s", name); @@ -371,32 +381,36 @@ struct symbol *map__find_symbol(struct map *map, u64 addr) if (map__load(map) < 0) return NULL; - return dso__find_symbol(map->dso, addr); + return dso__find_symbol(map__dso(map), addr); } struct symbol *map__find_symbol_by_name(struct map *map, const char *name) { + struct dso *dso; + if (map__load(map) < 0) return NULL; - if (!dso__sorted_by_name(map->dso)) - dso__sort_by_name(map->dso); + dso = map__dso(map); + if (!dso__sorted_by_name(dso)) + dso__sort_by_name(dso); - return dso__find_symbol_by_name(map->dso, name); + return dso__find_symbol_by_name(dso, name); } struct map *map__clone(struct map *from) { size_t size = sizeof(struct map); struct map *map; + struct dso *dso = map__dso(from); - if (from->dso && from->dso->kernel) + if (dso && dso->kernel) size += sizeof(struct kmap); map = memdup(from, size); if (map != NULL) { refcount_set(&map->refcnt, 1); - dso__get(map->dso); + dso__get(dso); } return map; @@ -404,20 +418,23 @@ struct map *map__clone(struct map *from) size_t map__fprintf(struct map *map, FILE *fp) { + const struct dso *dso = map__dso(map); + return fprintf(fp, " %" PRIx64 "-%" PRIx64 " %" PRIx64 " %s\n", - map->start, map->end, map->pgoff, map->dso->name); + map->start, map->end, map->pgoff, dso->name); } size_t map__fprintf_dsoname(struct map *map, FILE *fp) { char buf[symbol_conf.pad_output_len_dso + 1]; const char *dsoname = "[unknown]"; + const struct dso *dso = map ? map__dso(map) : NULL; - if (map && map->dso) { - if (symbol_conf.show_kernel_path && map->dso->long_name) - dsoname = map->dso->long_name; + if (dso) { + if (symbol_conf.show_kernel_path && dso->long_name) + dsoname = dso->long_name; else - dsoname = map->dso->name; + dsoname = dso->name; } if (symbol_conf.pad_output_len_dso) { @@ -432,15 +449,17 @@ char *map__srcline(struct map *map, u64 addr, struct symbol *sym) { if (map == NULL) return SRCLINE_UNKNOWN; - return get_srcline(map->dso, map__rip_2objdump(map, addr), sym, true, true, addr); + + return get_srcline(map__dso(map), map__rip_2objdump(map, addr), sym, true, true, addr); } int map__fprintf_srcline(struct map *map, u64 addr, const char *prefix, FILE *fp) { + const struct dso *dso = map ? map__dso(map) : NULL; int ret = 0; - if (map && map->dso) { + if (dso) { char *srcline = map__srcline(map, addr, NULL); if (strncmp(srcline, SRCLINE_UNKNOWN, strlen(SRCLINE_UNKNOWN)) != 0) ret = fprintf(fp, "%s%s", prefix, srcline); @@ -469,6 +488,7 @@ void srccode_state_free(struct srccode_state *state) u64 map__rip_2objdump(struct map *map, u64 rip) { struct kmap *kmap = __map__kmap(map); + const struct dso *dso = map__dso(map); /* * vmlinux does not have program headers for PTI entry trampolines and @@ -486,18 +506,18 @@ u64 map__rip_2objdump(struct map *map, u64 rip) } } - if (!map->dso->adjust_symbols) + if (!dso->adjust_symbols) return rip; - if (map->dso->rel) + if (dso->rel) return rip - map->pgoff; /* * kernel modules also have DSO_TYPE_USER in dso->kernel, * but all kernel modules are ET_REL, so won't get here. */ - if (map->dso->kernel == DSO_SPACE__USER) - return rip + map->dso->text_offset; + if (dso->kernel == DSO_SPACE__USER) + return rip + dso->text_offset; return map->unmap_ip(map, rip) - map->reloc; } @@ -516,18 +536,20 @@ u64 map__rip_2objdump(struct map *map, u64 rip) */ u64 map__objdump_2mem(struct map *map, u64 ip) { - if (!map->dso->adjust_symbols) + const struct dso *dso = map__dso(map); + + if (!dso->adjust_symbols) return map->unmap_ip(map, ip); - if (map->dso->rel) + if (dso->rel) return map->unmap_ip(map, ip + map->pgoff); /* * kernel modules also have DSO_TYPE_USER in dso->kernel, * but all kernel modules are ET_REL, so won't get here. */ - if (map->dso->kernel == DSO_SPACE__USER) - return map->unmap_ip(map, ip - map->dso->text_offset); + if (dso->kernel == DSO_SPACE__USER) + return map->unmap_ip(map, ip - dso->text_offset); return ip + map->reloc; } @@ -541,7 +563,9 @@ bool map__contains_symbol(const struct map *map, const struct symbol *sym) struct kmap *__map__kmap(struct map *map) { - if (!map->dso || !map->dso->kernel) + const struct dso *dso = map__dso(map); + + if (!dso || !dso->kernel) return NULL; return (struct kmap *)(map + 1); } diff --git a/tools/perf/util/map.h b/tools/perf/util/map.h index d1a6f85fd31d..36c5add0144d 100644 --- a/tools/perf/util/map.h +++ b/tools/perf/util/map.h @@ -47,6 +47,11 @@ u64 map__unmap_ip(const struct map *map, u64 ip); /* Returns ip */ u64 identity__map_ip(const struct map *map __maybe_unused, u64 ip); +static inline struct dso *map__dso(const struct map *map) +{ + return map->dso; +} + static inline size_t map__size(const struct map *map) { return map->end - map->start; @@ -69,7 +74,7 @@ struct thread; * Note: caller must ensure map->dso is not NULL (map is loaded). */ #define map__for_each_symbol(map, pos, n) \ - dso__for_each_symbol(map->dso, pos, n) + dso__for_each_symbol(map__dso(map), pos, n) /* map__for_each_symbol_with_name - iterate over the symbols in the given map * that have the given name diff --git a/tools/perf/util/maps.c b/tools/perf/util/maps.c index 91bb015caede..09ec6bbafcbc 100644 --- a/tools/perf/util/maps.c +++ b/tools/perf/util/maps.c @@ -62,6 +62,7 @@ static int __maps__insert(struct maps *maps, struct map *map) int maps__insert(struct maps *maps, struct map *map) { int err; + const struct dso *dso = map__dso(map); down_write(maps__lock(maps)); err = __maps__insert(maps, map); @@ -70,7 +71,7 @@ int maps__insert(struct maps *maps, struct map *map) ++maps->nr_maps; - if (map->dso && map->dso->kernel) { + if (dso && dso->kernel) { struct kmap *kmap = map__kmap(map); if (kmap) @@ -253,7 +254,7 @@ size_t maps__fprintf(struct maps *maps, FILE *fp) printed += fprintf(fp, "Map:"); printed += map__fprintf(pos->map, fp); if (verbose > 2) { - printed += dso__fprintf(pos->map->dso, fp); + printed += dso__fprintf(map__dso(pos->map), fp); printed += fprintf(fp, "--\n"); } } @@ -307,7 +308,7 @@ int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp) if (use_browser) { pr_debug("overlapping maps in %s (disable tui for more info)\n", - map->dso->name); + map__dso(map)->name); } else { fputs("overlapping maps:\n", fp); map__fprintf(map, fp); diff --git a/tools/perf/util/probe-event.c b/tools/perf/util/probe-event.c index cdf5d655d84c..b26670a26005 100644 --- a/tools/perf/util/probe-event.c +++ b/tools/perf/util/probe-event.c @@ -165,8 +165,9 @@ static struct map *kernel_get_module_map(const char *module) maps__for_each_entry(maps, pos) { /* short_name is "[module]" */ - const char *short_name = pos->map->dso->short_name; - u16 short_name_len = pos->map->dso->short_name_len; + struct dso *dso = map__dso(pos->map); + const char *short_name = dso->short_name; + u16 short_name_len = dso->short_name_len; if (strncmp(short_name + 1, module, short_name_len - 2) == 0 && @@ -182,13 +183,15 @@ struct map *get_target_map(const char *target, struct nsinfo *nsi, bool user) /* Init maps of given executable or kernel */ if (user) { struct map *map; + struct dso *dso; map = dso__new_map(target); - if (map && map->dso) { - mutex_lock(&map->dso->lock); - nsinfo__put(map->dso->nsinfo); - map->dso->nsinfo = nsinfo__get(nsi); - mutex_unlock(&map->dso->lock); + dso = map ? map__dso(map) : NULL; + if (dso) { + mutex_lock(&dso->lock); + nsinfo__put(dso->nsinfo); + dso->nsinfo = nsinfo__get(nsi); + mutex_unlock(&dso->lock); } return map; } else { @@ -341,7 +344,7 @@ static int kernel_get_module_dso(const char *module, struct dso **pdso) snprintf(module_name, sizeof(module_name), "[%s]", module); map = maps__find_by_name(machine__kernel_maps(host_machine), module_name); if (map) { - dso = map->dso; + dso = map__dso(map); goto found; } pr_debug("Failed to find module %s.\n", module); @@ -349,7 +352,7 @@ static int kernel_get_module_dso(const char *module, struct dso **pdso) } map = machine__kernel_map(host_machine); - dso = map->dso; + dso = map__dso(map); if (!dso->has_build_id) dso__read_running_kernel_build_id(dso, host_machine); @@ -3737,6 +3740,7 @@ int show_available_funcs(const char *target, struct nsinfo *nsi, { struct rb_node *nd; struct map *map; + struct dso *dso; int ret; ret = init_probe_symbol_maps(user); @@ -3762,14 +3766,14 @@ int show_available_funcs(const char *target, struct nsinfo *nsi, (target) ? : "kernel"); goto end; } - if (!dso__sorted_by_name(map->dso)) - dso__sort_by_name(map->dso); + dso = map__dso(map); + if (!dso__sorted_by_name(dso)) + dso__sort_by_name(dso); /* Show all (filtered) symbols */ setup_pager(); - for (nd = rb_first_cached(&map->dso->symbol_names); nd; - nd = rb_next(nd)) { + for (nd = rb_first_cached(&dso->symbol_names); nd; nd = rb_next(nd)) { struct symbol_name_rb_node *pos = rb_entry(nd, struct symbol_name_rb_node, rb_node); if (strfilter__compare(_filter, pos->sym.name)) diff --git a/tools/perf/util/scripting-engines/trace-event-perl.c b/tools/perf/util/scripting-engines/trace-event-perl.c index 83fd2fd0ba16..039d0365ad41 100644 --- a/tools/perf/util/scripting-engines/trace-event-perl.c +++ b/tools/perf/util/scripting-engines/trace-event-perl.c @@ -315,12 +315,14 @@ static SV *perl_process_callchain(struct perf_sample *sample, if (node->ms.map) { struct map *map = node->ms.map; + struct dso *dso = map ? map__dso(map) : NULL; const char *dsoname = "[unknown]"; - if (map && map->dso) { - if (symbol_conf.show_kernel_path && map->dso->long_name) - dsoname = map->dso->long_name; + + if (dso) { + if (symbol_conf.show_kernel_path && dso->long_name) + dsoname = dso->long_name; else - dsoname = map->dso->name; + dsoname = dso->name; } if (!hv_stores(elem, "dso", newSVpv(dsoname,0))) { hv_undef(elem); diff --git a/tools/perf/util/scripting-engines/trace-event-python.c b/tools/perf/util/scripting-engines/trace-event-python.c index e5cc18f6fcda..b8e5c6f61d80 100644 --- a/tools/perf/util/scripting-engines/trace-event-python.c +++ b/tools/perf/util/scripting-engines/trace-event-python.c @@ -390,12 +390,13 @@ static PyObject *get_field_numeric_entry(struct tep_event *event, static const char *get_dsoname(struct map *map) { const char *dsoname = "[unknown]"; + struct dso *dso = map ? map__dso(map) : NULL; - if (map && map->dso) { - if (symbol_conf.show_kernel_path && map->dso->long_name) - dsoname = map->dso->long_name; + if (dso) { + if (symbol_conf.show_kernel_path && dso->long_name) + dsoname = dso->long_name; else - dsoname = map->dso->name; + dsoname = dso->name; } return dsoname; @@ -780,9 +781,10 @@ static void set_sym_in_dict(PyObject *dict, struct addr_location *al, char sbuild_id[SBUILD_ID_SIZE]; if (al->map) { - pydict_set_item_string_decref(dict, dso_field, - _PyUnicode_FromString(al->map->dso->name)); - build_id__sprintf(&al->map->dso->bid, sbuild_id); + struct dso *dso = map__dso(al->map); + + pydict_set_item_string_decref(dict, dso_field, _PyUnicode_FromString(dso->name)); + build_id__sprintf(&dso->bid, sbuild_id); pydict_set_item_string_decref(dict, dso_bid_field, _PyUnicode_FromString(sbuild_id)); pydict_set_item_string_decref(dict, dso_map_start, diff --git a/tools/perf/util/sort.c b/tools/perf/util/sort.c index 430f67e7cc82..f161589aefda 100644 --- a/tools/perf/util/sort.c +++ b/tools/perf/util/sort.c @@ -230,8 +230,8 @@ struct sort_entry sort_comm = { static int64_t _sort__dso_cmp(struct map *map_l, struct map *map_r) { - struct dso *dso_l = map_l ? map_l->dso : NULL; - struct dso *dso_r = map_r ? map_r->dso : NULL; + struct dso *dso_l = map_l ? map__dso(map_l) : NULL; + struct dso *dso_r = map_r ? map__dso(map_r) : NULL; const char *dso_name_l, *dso_name_r; if (!dso_l || !dso_r) @@ -257,13 +257,13 @@ sort__dso_cmp(struct hist_entry *left, struct hist_entry *right) static int _hist_entry__dso_snprintf(struct map *map, char *bf, size_t size, unsigned int width) { - if (map && map->dso) { - const char *dso_name = verbose > 0 ? map->dso->long_name : - map->dso->short_name; - return repsep_snprintf(bf, size, "%-*.*s", width, width, dso_name); - } + const struct dso *dso = map ? map__dso(map) : NULL; + const char *dso_name = "[unknown]"; + + if (dso) + dso_name = verbose > 0 ? dso->long_name : dso->short_name; - return repsep_snprintf(bf, size, "%-*.*s", width, width, "[unknown]"); + return repsep_snprintf(bf, size, "%-*.*s", width, width, dso_name); } static int hist_entry__dso_snprintf(struct hist_entry *he, char *bf, @@ -279,7 +279,7 @@ static int hist_entry__dso_filter(struct hist_entry *he, int type, const void *a if (type != HIST_FILTER__DSO) return -1; - return dso && (!he->ms.map || he->ms.map->dso != dso); + return dso && (!he->ms.map || map__dso(he->ms.map) != dso); } struct sort_entry sort_dso = { @@ -359,11 +359,11 @@ static int _hist_entry__sym_snprintf(struct map_symbol *ms, size_t ret = 0; if (verbose > 0) { - char o = map ? dso__symtab_origin(map->dso) : '!'; + struct dso *dso = map ? map__dso(map) : NULL; + char o = dso ? dso__symtab_origin(dso) : '!'; u64 rip = ip; - if (map && map->dso && map->dso->kernel - && map->dso->adjust_symbols) + if (dso && dso->kernel && dso->adjust_symbols) rip = map->unmap_ip(map, ip); ret += repsep_snprintf(bf, size, "%-#*llx %c ", @@ -641,7 +641,7 @@ static char *hist_entry__get_srcfile(struct hist_entry *e) if (!map) return no_srcfile; - sf = __get_srcline(map->dso, map__rip_2objdump(map, e->ip), + sf = __get_srcline(map__dso(map), map__rip_2objdump(map, e->ip), e->ms.sym, false, true, true, e->ip); if (!strcmp(sf, SRCLINE_UNKNOWN)) return no_srcfile; @@ -982,7 +982,7 @@ static int hist_entry__dso_from_filter(struct hist_entry *he, int type, return -1; return dso && (!he->branch_info || !he->branch_info->from.ms.map || - he->branch_info->from.ms.map->dso != dso); + map__dso(he->branch_info->from.ms.map) != dso); } static int64_t @@ -1014,7 +1014,7 @@ static int hist_entry__dso_to_filter(struct hist_entry *he, int type, return -1; return dso && (!he->branch_info || !he->branch_info->to.ms.map || - he->branch_info->to.ms.map->dso != dso); + map__dso(he->branch_info->to.ms.map) != dso); } static int64_t @@ -1506,6 +1506,7 @@ sort__dcacheline_cmp(struct hist_entry *left, struct hist_entry *right) { u64 l, r; struct map *l_map, *r_map; + struct dso *l_dso, *r_dso; int rc; if (!left->mem_info) return -1; @@ -1525,7 +1526,9 @@ sort__dcacheline_cmp(struct hist_entry *left, struct hist_entry *right) if (!l_map) return -1; if (!r_map) return 1; - rc = dso__cmp_id(l_map->dso, r_map->dso); + l_dso = map__dso(l_map); + r_dso = map__dso(r_map); + rc = dso__cmp_id(l_dso, r_dso); if (rc) return rc; /* @@ -1537,9 +1540,8 @@ sort__dcacheline_cmp(struct hist_entry *left, struct hist_entry *right) */ if ((left->cpumode != PERF_RECORD_MISC_KERNEL) && - (!(l_map->flags & MAP_SHARED)) && - !l_map->dso->id.maj && !l_map->dso->id.min && - !l_map->dso->id.ino && !l_map->dso->id.ino_generation) { + (!(l_map->flags & MAP_SHARED)) && !l_dso->id.maj && !l_dso->id.min && + !l_dso->id.ino && !l_dso->id.ino_generation) { /* userspace anonymous */ if (left->thread->pid_ > right->thread->pid_) return -1; @@ -1567,6 +1569,7 @@ static int hist_entry__dcacheline_snprintf(struct hist_entry *he, char *bf, if (he->mem_info) { struct map *map = he->mem_info->daddr.ms.map; + struct dso *dso = map__dso(map); addr = cl_address(he->mem_info->daddr.al_addr, chk_double_cl); ms = &he->mem_info->daddr.ms; @@ -1575,8 +1578,7 @@ static int hist_entry__dcacheline_snprintf(struct hist_entry *he, char *bf, if ((he->cpumode != PERF_RECORD_MISC_KERNEL) && map && !(map->prot & PROT_EXEC) && (map->flags & MAP_SHARED) && - (map->dso->id.maj || map->dso->id.min || - map->dso->id.ino || map->dso->id.ino_generation)) + (dso->id.maj || dso->id.min || dso->id.ino || dso->id.ino_generation)) level = 's'; else if (!map) level = 'X'; @@ -2072,9 +2074,8 @@ sort__dso_size_cmp(struct hist_entry *left, struct hist_entry *right) static int _hist_entry__dso_size_snprintf(struct map *map, char *bf, size_t bf_size, unsigned int width) { - if (map && map->dso) - return repsep_snprintf(bf, bf_size, "%*d", width, - map__size(map)); + if (map && map__dso(map)) + return repsep_snprintf(bf, bf_size, "%*d", width, map__size(map)); return repsep_snprintf(bf, bf_size, "%*s", width, "unknown"); } diff --git a/tools/perf/util/symbol-elf.c b/tools/perf/util/symbol-elf.c index 3084e556d3eb..561372869792 100644 --- a/tools/perf/util/symbol-elf.c +++ b/tools/perf/util/symbol-elf.c @@ -1435,7 +1435,7 @@ static int dso__process_kernel_symbol(struct dso *dso, struct map *map, *curr_mapp = curr_map; *curr_dsop = curr_dso; } else - *curr_dsop = curr_map->dso; + *curr_dsop = map__dso(curr_map); return 0; } diff --git a/tools/perf/util/symbol.c b/tools/perf/util/symbol.c index 316b63fb5691..a1c85c22676f 100644 --- a/tools/perf/util/symbol.c +++ b/tools/perf/util/symbol.c @@ -791,6 +791,7 @@ static int maps__split_kallsyms_for_kcore(struct maps *kmaps, struct dso *dso) *root = RB_ROOT_CACHED; while (next) { + struct dso *curr_map_dso; char *module; pos = rb_entry(next, struct symbol, rb_node); @@ -808,13 +809,13 @@ static int maps__split_kallsyms_for_kcore(struct maps *kmaps, struct dso *dso) symbol__delete(pos); continue; } - + curr_map_dso = map__dso(curr_map); pos->start -= curr_map->start - curr_map->pgoff; if (pos->end > curr_map->end) pos->end = curr_map->end; if (pos->end) pos->end -= curr_map->start - curr_map->pgoff; - symbols__insert(&curr_map->dso->symbols, pos); + symbols__insert(&curr_map_dso->symbols, pos); ++count; } @@ -856,12 +857,14 @@ static int maps__split_kallsyms(struct maps *kmaps, struct dso *dso, u64 delta, module = strchr(pos->name, '\t'); if (module) { + struct dso *curr_map_dso; + if (!symbol_conf.use_modules) goto discard_symbol; *module++ = '\0'; - - if (strcmp(curr_map->dso->short_name, module)) { + curr_map_dso = map__dso(curr_map); + if (strcmp(curr_map_dso->short_name, module)) { if (curr_map != initial_map && dso->kernel == DSO_SPACE__KERNEL_GUEST && machine__is_default_guest(machine)) { @@ -872,7 +875,7 @@ static int maps__split_kallsyms(struct maps *kmaps, struct dso *dso, u64 delta, * symbols are in its kmap. Mark it as * loaded. */ - dso__set_loaded(curr_map->dso); + dso__set_loaded(curr_map_dso); } curr_map = maps__find_by_name(kmaps, module); @@ -884,8 +887,8 @@ static int maps__split_kallsyms(struct maps *kmaps, struct dso *dso, u64 delta, curr_map = initial_map; goto discard_symbol; } - - if (curr_map->dso->loaded && + curr_map_dso = map__dso(curr_map); + if (curr_map_dso->loaded && !machine__is_default_guest(machine)) goto discard_symbol; } @@ -954,8 +957,10 @@ static int maps__split_kallsyms(struct maps *kmaps, struct dso *dso, u64 delta, } add_symbol: if (curr_map != initial_map) { + struct dso *curr_map_dso = map__dso(curr_map); + rb_erase_cached(&pos->rb_node, root); - symbols__insert(&curr_map->dso->symbols, pos); + symbols__insert(&curr_map_dso->symbols, pos); ++moved; } else ++count; @@ -969,7 +974,7 @@ discard_symbol: if (curr_map != initial_map && dso->kernel == DSO_SPACE__KERNEL_GUEST && machine__is_default_guest(maps__machine(kmaps))) { - dso__set_loaded(curr_map->dso); + dso__set_loaded(map__dso(curr_map)); } return count + moved; @@ -1143,13 +1148,14 @@ static int do_validate_kcore_modules(const char *filename, struct maps *kmaps) maps__for_each_entry(kmaps, old_node) { struct map *old_map = old_node->map; struct module_info *mi; + struct dso *dso; if (!__map__is_kmodule(old_map)) { continue; } - + dso = map__dso(old_map); /* Module must be in memory at the same address */ - mi = find_module(old_map->dso->short_name, &modules); + mi = find_module(dso->short_name, &modules); if (!mi || mi->start != old_map->start) { err = -EINVAL; goto out; @@ -2047,14 +2053,17 @@ out: static int map__strcmp(const void *a, const void *b) { - const struct map *ma = *(const struct map **)a, *mb = *(const struct map **)b; - return strcmp(ma->dso->short_name, mb->dso->short_name); + const struct dso *dso_a = map__dso(*(const struct map **)a); + const struct dso *dso_b = map__dso(*(const struct map **)b); + + return strcmp(dso_a->short_name, dso_b->short_name); } static int map__strcmp_name(const void *name, const void *b) { - const struct map *map = *(const struct map **)b; - return strcmp(name, map->dso->short_name); + const struct dso *dso = map__dso(*(const struct map **)b); + + return strcmp(name, dso->short_name); } void __maps__sort_by_name(struct maps *maps) @@ -2111,10 +2120,13 @@ struct map *maps__find_by_name(struct maps *maps, const char *name) down_read(maps__lock(maps)); - if (maps->last_search_by_name && - strcmp(maps->last_search_by_name->dso->short_name, name) == 0) { - map = maps->last_search_by_name; - goto out_unlock; + if (maps->last_search_by_name) { + const struct dso *dso = map__dso(maps->last_search_by_name); + + if (strcmp(dso->short_name, name) == 0) { + map = maps->last_search_by_name; + goto out_unlock; + } } /* * If we have maps->maps_by_name, then the name isn't in the rbtree, @@ -2127,8 +2139,11 @@ struct map *maps__find_by_name(struct maps *maps, const char *name) /* Fallback to traversing the rbtree... */ maps__for_each_entry(maps, rb_node) { + struct dso *dso; + map = rb_node->map; - if (strcmp(map->dso->short_name, name) == 0) { + dso = map__dso(map); + if (strcmp(dso->short_name, name) == 0) { maps->last_search_by_name = map; goto out_unlock; } diff --git a/tools/perf/util/synthetic-events.c b/tools/perf/util/synthetic-events.c index 57b95c1d7e39..fbd1a882b013 100644 --- a/tools/perf/util/synthetic-events.c +++ b/tools/perf/util/synthetic-events.c @@ -693,12 +693,14 @@ int perf_event__synthesize_modules(struct perf_tool *tool, perf_event__handler_t maps__for_each_entry(maps, pos) { struct map *map = pos->map; + struct dso *dso; if (!__map__is_kmodule(map)) continue; + dso = map__dso(map); if (symbol_conf.buildid_mmap2) { - size = PERF_ALIGN(map->dso->long_name_len + 1, sizeof(u64)); + size = PERF_ALIGN(dso->long_name_len + 1, sizeof(u64)); event->mmap2.header.type = PERF_RECORD_MMAP2; event->mmap2.header.size = (sizeof(event->mmap2) - (sizeof(event->mmap2.filename) - size)); @@ -708,12 +710,11 @@ int perf_event__synthesize_modules(struct perf_tool *tool, perf_event__handler_t event->mmap2.len = map->end - map->start; event->mmap2.pid = machine->pid; - memcpy(event->mmap2.filename, map->dso->long_name, - map->dso->long_name_len + 1); + memcpy(event->mmap2.filename, dso->long_name, dso->long_name_len + 1); perf_record_mmap2__read_build_id(&event->mmap2, machine, false); } else { - size = PERF_ALIGN(map->dso->long_name_len + 1, sizeof(u64)); + size = PERF_ALIGN(dso->long_name_len + 1, sizeof(u64)); event->mmap.header.type = PERF_RECORD_MMAP; event->mmap.header.size = (sizeof(event->mmap) - (sizeof(event->mmap.filename) - size)); @@ -723,8 +724,7 @@ int perf_event__synthesize_modules(struct perf_tool *tool, perf_event__handler_t event->mmap.len = map->end - map->start; event->mmap.pid = machine->pid; - memcpy(event->mmap.filename, map->dso->long_name, - map->dso->long_name_len + 1); + memcpy(event->mmap.filename, dso->long_name, dso->long_name_len + 1); } if (perf_tool__process_synth_event(tool, event, machine, process) != 0) { diff --git a/tools/perf/util/thread.c b/tools/perf/util/thread.c index 292585a52281..bb7a2ce82d46 100644 --- a/tools/perf/util/thread.c +++ b/tools/perf/util/thread.c @@ -448,23 +448,27 @@ struct thread *thread__main_thread(struct machine *machine, struct thread *threa int thread__memcpy(struct thread *thread, struct machine *machine, void *buf, u64 ip, int len, bool *is64bit) { - u8 cpumode = PERF_RECORD_MISC_USER; - struct addr_location al; - long offset; + u8 cpumode = PERF_RECORD_MISC_USER; + struct addr_location al; + struct dso *dso; + long offset; - if (machine__kernel_ip(machine, ip)) - cpumode = PERF_RECORD_MISC_KERNEL; + if (machine__kernel_ip(machine, ip)) + cpumode = PERF_RECORD_MISC_KERNEL; - if (!thread__find_map(thread, cpumode, ip, &al) || !al.map->dso || - al.map->dso->data.status == DSO_DATA_STATUS_ERROR || - map__load(al.map) < 0) - return -1; + if (!thread__find_map(thread, cpumode, ip, &al)) + return -1; - offset = al.map->map_ip(al.map, ip); - if (is64bit) - *is64bit = al.map->dso->is_64_bit; + dso = map__dso(al.map); - return dso__data_read_offset(al.map->dso, machine, offset, buf, len); + if( !dso || dso->data.status == DSO_DATA_STATUS_ERROR || map__load(al.map) < 0) + return -1; + + offset = al.map->map_ip(al.map, ip); + if (is64bit) + *is64bit = dso->is_64_bit; + + return dso__data_read_offset(dso, machine, offset, buf, len); } void thread__free_stitch_list(struct thread *thread) diff --git a/tools/perf/util/unwind-libdw.c b/tools/perf/util/unwind-libdw.c index 94aa40f6e348..c8cba9d4bfd9 100644 --- a/tools/perf/util/unwind-libdw.c +++ b/tools/perf/util/unwind-libdw.c @@ -52,7 +52,7 @@ static int __report_module(struct addr_location *al, u64 ip, thread__find_symbol(ui->thread, PERF_RECORD_MISC_USER, ip, al); if (al->map) - dso = al->map->dso; + dso = map__dso(al->map); if (!dso) return 0; @@ -134,17 +134,17 @@ static int access_dso_mem(struct unwind_info *ui, Dwarf_Addr addr, { struct addr_location al; ssize_t size; + struct dso *dso; if (!thread__find_map(ui->thread, PERF_RECORD_MISC_USER, addr, &al)) { pr_debug("unwind: no map for %lx\n", (unsigned long)addr); return -1; } - - if (!al.map->dso) + dso = map__dso(al.map); + if (!dso) return -1; - size = dso__data_read_addr(al.map->dso, al.map, ui->machine, - addr, (u8 *) data, sizeof(*data)); + size = dso__data_read_addr(dso, al.map, ui->machine, addr, (u8 *) data, sizeof(*data)); return !(size == sizeof(*data)); } diff --git a/tools/perf/util/unwind-libunwind-local.c b/tools/perf/util/unwind-libunwind-local.c index c487a249b33c..108f7b1697a7 100644 --- a/tools/perf/util/unwind-libunwind-local.c +++ b/tools/perf/util/unwind-libunwind-local.c @@ -328,7 +328,7 @@ static int read_unwind_spec_eh_frame(struct dso *dso, struct unwind_info *ui, maps__for_each_entry(ui->thread->maps, map_node) { struct map *map = map_node->map; - if (map->dso == dso && map->start < base_addr) + if (map__dso(map) == dso && map->start < base_addr) base_addr = map->start; } base_addr -= dso->data.elf_base_addr; @@ -424,19 +424,23 @@ find_proc_info(unw_addr_space_t as, unw_word_t ip, unw_proc_info_t *pi, { struct unwind_info *ui = arg; struct map *map; + struct dso *dso; unw_dyn_info_t di; u64 table_data, segbase, fde_count; int ret = -EINVAL; map = find_map(ip, ui); - if (!map || !map->dso) + if (!map) return -EINVAL; - pr_debug("unwind: find_proc_info dso %s\n", map->dso->name); + dso = map__dso(map); + if (!dso) + return -EINVAL; + + pr_debug("unwind: find_proc_info dso %s\n", dso->name); /* Check the .eh_frame section for unwinding info */ - if (!read_unwind_spec_eh_frame(map->dso, ui, - &table_data, &segbase, &fde_count)) { + if (!read_unwind_spec_eh_frame(dso, ui, &table_data, &segbase, &fde_count)) { memset(&di, 0, sizeof(di)); di.format = UNW_INFO_FORMAT_REMOTE_TABLE; di.start_ip = map->start; @@ -452,16 +456,16 @@ find_proc_info(unw_addr_space_t as, unw_word_t ip, unw_proc_info_t *pi, #ifndef NO_LIBUNWIND_DEBUG_FRAME /* Check the .debug_frame section for unwinding info */ if (ret < 0 && - !read_unwind_spec_debug_frame(map->dso, ui->machine, &segbase)) { - int fd = dso__data_get_fd(map->dso, ui->machine); - int is_exec = elf_is_exec(fd, map->dso->name); + !read_unwind_spec_debug_frame(dso, ui->machine, &segbase)) { + int fd = dso__data_get_fd(dso, ui->machine); + int is_exec = elf_is_exec(fd, dso->name); unw_word_t base = is_exec ? 0 : map->start; const char *symfile; if (fd >= 0) - dso__data_put_fd(map->dso); + dso__data_put_fd(dso); - symfile = map->dso->symsrc_filename ?: map->dso->name; + symfile = dso->symsrc_filename ?: dso->name; memset(&di, 0, sizeof(di)); if (dwarf_find_debug_frame(0, &di, ip, base, symfile, @@ -513,6 +517,7 @@ static int access_dso_mem(struct unwind_info *ui, unw_word_t addr, unw_word_t *data) { struct map *map; + struct dso *dso; ssize_t size; map = find_map(addr, ui); @@ -521,10 +526,12 @@ static int access_dso_mem(struct unwind_info *ui, unw_word_t addr, return -1; } - if (!map->dso) + dso = map__dso(map); + + if (!dso) return -1; - size = dso__data_read_addr(map->dso, map, ui->machine, + size = dso__data_read_addr(dso, map, ui->machine, addr, (u8 *) data, sizeof(*data)); return !(size == sizeof(*data)); diff --git a/tools/perf/util/unwind-libunwind.c b/tools/perf/util/unwind-libunwind.c index 42528ade513e..4378daaafcd3 100644 --- a/tools/perf/util/unwind-libunwind.c +++ b/tools/perf/util/unwind-libunwind.c @@ -22,6 +22,7 @@ int unwind__prepare_access(struct maps *maps, struct map *map, bool *initialized const char *arch; enum dso_type dso_type; struct unwind_libunwind_ops *ops = local_unwind_libunwind_ops; + struct dso *dso = map__dso(map); struct machine *machine; int err; @@ -29,8 +30,7 @@ int unwind__prepare_access(struct maps *maps, struct map *map, bool *initialized return 0; if (maps__addr_space(maps)) { - pr_debug("unwind: thread map already set, dso=%s\n", - map->dso->name); + pr_debug("unwind: thread map already set, dso=%s\n", dso->name); if (initialized) *initialized = true; return 0; @@ -41,7 +41,7 @@ int unwind__prepare_access(struct maps *maps, struct map *map, bool *initialized if (!machine->env || !machine->env->arch) goto out_register; - dso_type = dso__type(map->dso, machine); + dso_type = dso__type(dso, machine); if (dso_type == DSO__TYPE_UNKNOWN) return 0; diff --git a/tools/perf/util/vdso.c b/tools/perf/util/vdso.c index 835c39efb80d..ec777ee11493 100644 --- a/tools/perf/util/vdso.c +++ b/tools/perf/util/vdso.c @@ -147,7 +147,7 @@ static enum dso_type machine__thread_dso_type(struct machine *machine, struct map_rb_node *rb_node; maps__for_each_entry(thread->maps, rb_node) { - struct dso *dso = rb_node->map->dso; + struct dso *dso = map__dso(rb_node->map); if (!dso || dso->long_name[0] != '/') continue; -- cgit v1.2.3-58-ga151 From e5116f46d44b72ede59a6923829f68a8b8f84e76 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 20 Mar 2023 14:22:36 -0700 Subject: perf map: Add accessor for start and end Later changes will add reference count checking for struct map, start and end are frequently accessed variables. Add an accessor so that the reference count check is only necessary in one place. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexey Bayduraev Cc: Andi Kleen Cc: Andrew Morton Cc: Andy Shevchenko Cc: Darren Hart Cc: Davidlohr Bueso Cc: Dmitriy Vyukov Cc: Eric Dumazet Cc: German Gomez Cc: Hao Luo Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Madhavan Srinivasan Cc: Mark Rutland Cc: Masami Hiramatsu Cc: Miaoqian Lin Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Riccardo Mancini Cc: Shunsuke Nakamura Cc: Song Liu Cc: Stephane Eranian Cc: Stephen Brennan Cc: Steven Rostedt (VMware) Cc: Thomas Gleixner Cc: Thomas Richter Cc: Yury Norov Link: https://lore.kernel.org/r/20230320212248.1175731-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/arm/tests/dwarf-unwind.c | 2 +- tools/perf/arch/arm64/tests/dwarf-unwind.c | 2 +- tools/perf/arch/powerpc/tests/dwarf-unwind.c | 2 +- tools/perf/arch/powerpc/util/skip-callchain-idx.c | 2 +- tools/perf/arch/x86/tests/dwarf-unwind.c | 2 +- tools/perf/arch/x86/util/event.c | 4 +- tools/perf/builtin-buildid-list.c | 2 +- tools/perf/builtin-report.c | 2 +- tools/perf/builtin-script.c | 2 +- tools/perf/builtin-top.c | 2 +- tools/perf/tests/code-reading.c | 8 ++-- tools/perf/tests/maps.c | 4 +- tools/perf/tests/mmap-thread-lookup.c | 2 +- tools/perf/tests/vmlinux-kallsyms.c | 14 +++---- tools/perf/util/annotate.c | 4 +- tools/perf/util/dlfilter.c | 8 ++-- tools/perf/util/intel-pt.c | 8 ++-- tools/perf/util/machine.c | 14 +++---- tools/perf/util/map.c | 8 ++-- tools/perf/util/map.h | 12 +++++- tools/perf/util/maps.c | 30 +++++++------- tools/perf/util/probe-event.c | 4 +- .../util/scripting-engines/trace-event-python.c | 6 +-- tools/perf/util/symbol-elf.c | 8 ++-- tools/perf/util/symbol.c | 48 +++++++++++----------- tools/perf/util/symbol_fprintf.c | 2 +- tools/perf/util/synthetic-events.c | 16 ++++---- tools/perf/util/unwind-libdw.c | 6 +-- tools/perf/util/unwind-libunwind-local.c | 15 +++---- 29 files changed, 125 insertions(+), 114 deletions(-) (limited to 'tools') diff --git a/tools/perf/arch/arm/tests/dwarf-unwind.c b/tools/perf/arch/arm/tests/dwarf-unwind.c index ccfa87055c4a..566fb6c0eae7 100644 --- a/tools/perf/arch/arm/tests/dwarf-unwind.c +++ b/tools/perf/arch/arm/tests/dwarf-unwind.c @@ -33,7 +33,7 @@ static int sample_ustack(struct perf_sample *sample, return -1; } - stack_size = map->end - sp; + stack_size = map__end(map) - sp; stack_size = stack_size > STACK_SIZE ? STACK_SIZE : stack_size; memcpy(buf, (void *) sp, stack_size); diff --git a/tools/perf/arch/arm64/tests/dwarf-unwind.c b/tools/perf/arch/arm64/tests/dwarf-unwind.c index 46147a483049..90a7ef293ce7 100644 --- a/tools/perf/arch/arm64/tests/dwarf-unwind.c +++ b/tools/perf/arch/arm64/tests/dwarf-unwind.c @@ -33,7 +33,7 @@ static int sample_ustack(struct perf_sample *sample, return -1; } - stack_size = map->end - sp; + stack_size = map__end(map) - sp; stack_size = stack_size > STACK_SIZE ? STACK_SIZE : stack_size; memcpy(buf, (void *) sp, stack_size); diff --git a/tools/perf/arch/powerpc/tests/dwarf-unwind.c b/tools/perf/arch/powerpc/tests/dwarf-unwind.c index c9cb4b059392..32fffb593fbf 100644 --- a/tools/perf/arch/powerpc/tests/dwarf-unwind.c +++ b/tools/perf/arch/powerpc/tests/dwarf-unwind.c @@ -33,7 +33,7 @@ static int sample_ustack(struct perf_sample *sample, return -1; } - stack_size = map->end - sp; + stack_size = map__end(map) - sp; stack_size = stack_size > STACK_SIZE ? STACK_SIZE : stack_size; memcpy(buf, (void *) sp, stack_size); diff --git a/tools/perf/arch/powerpc/util/skip-callchain-idx.c b/tools/perf/arch/powerpc/util/skip-callchain-idx.c index fe0e4530673c..b7223feec770 100644 --- a/tools/perf/arch/powerpc/util/skip-callchain-idx.c +++ b/tools/perf/arch/powerpc/util/skip-callchain-idx.c @@ -262,7 +262,7 @@ int arch_skip_callchain_idx(struct thread *thread, struct ip_callchain *chain) return skip_slot; } - rc = check_return_addr(dso, al.map->start, ip); + rc = check_return_addr(dso, map__start(al.map), ip); pr_debug("[DSO %s, sym %s, ip 0x%" PRIx64 "] rc %d\n", dso->long_name, al.sym->name, ip, rc); diff --git a/tools/perf/arch/x86/tests/dwarf-unwind.c b/tools/perf/arch/x86/tests/dwarf-unwind.c index a54dea7c112f..497593be80f2 100644 --- a/tools/perf/arch/x86/tests/dwarf-unwind.c +++ b/tools/perf/arch/x86/tests/dwarf-unwind.c @@ -33,7 +33,7 @@ static int sample_ustack(struct perf_sample *sample, return -1; } - stack_size = map->end - sp; + stack_size = map__end(map) - sp; stack_size = stack_size > STACK_SIZE ? STACK_SIZE : stack_size; memcpy(buf, (void *) sp, stack_size); diff --git a/tools/perf/arch/x86/util/event.c b/tools/perf/arch/x86/util/event.c index 17bf60babfbd..3b2475707756 100644 --- a/tools/perf/arch/x86/util/event.c +++ b/tools/perf/arch/x86/util/event.c @@ -59,8 +59,8 @@ int perf_event__synthesize_extra_kmaps(struct perf_tool *tool, event->mmap.header.size = size; - event->mmap.start = map->start; - event->mmap.len = map->end - map->start; + event->mmap.start = map__start(map); + event->mmap.len = map__size(map); event->mmap.pgoff = map->pgoff; event->mmap.pid = machine->pid; diff --git a/tools/perf/builtin-buildid-list.c b/tools/perf/builtin-buildid-list.c index cad9ed44ce7c..eea28cbcc0b7 100644 --- a/tools/perf/builtin-buildid-list.c +++ b/tools/perf/builtin-buildid-list.c @@ -30,7 +30,7 @@ static int buildid__map_cb(struct map *map, void *arg __maybe_unused) memset(bid_buf, 0, sizeof(bid_buf)); if (dso->has_build_id) build_id__sprintf(&dso->bid, bid_buf); - printf("%s %16" PRIx64 " %16" PRIx64, bid_buf, map->start, map->end); + printf("%s %16" PRIx64 " %16" PRIx64, bid_buf, map__start(map), map__end(map)); if (dso->long_name != NULL) { printf(" %s", dso->long_name); } else if (dso->short_name != NULL) { diff --git a/tools/perf/builtin-report.c b/tools/perf/builtin-report.c index ff239b89e4d0..2a6e2cee5e0d 100644 --- a/tools/perf/builtin-report.c +++ b/tools/perf/builtin-report.c @@ -851,7 +851,7 @@ static size_t maps__fprintf_task(struct maps *maps, int indent, FILE *fp) const struct dso *dso = map__dso(map); printed += fprintf(fp, "%*s %" PRIx64 "-%" PRIx64 " %c%c%c%c %08" PRIx64 " %" PRIu64 " %s\n", - indent, "", map->start, map->end, + indent, "", map__start(map), map__end(map), map->prot & PROT_READ ? 'r' : '-', map->prot & PROT_WRITE ? 'w' : '-', map->prot & PROT_EXEC ? 'x' : '-', diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index 27fd9c203600..1d078106abc4 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -1209,7 +1209,7 @@ static int ip__fprintf_sym(uint64_t addr, struct thread *thread, if (al.addr < al.sym->end) off = al.addr - al.sym->start; else - off = al.addr - al.map->start - al.sym->start; + off = al.addr - map__start(al.map) - al.sym->start; printed += fprintf(fp, "\t%s", al.sym->name); if (off) printed += fprintf(fp, "%+d", off); diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c index babfc163efe2..b803af4329d1 100644 --- a/tools/perf/builtin-top.c +++ b/tools/perf/builtin-top.c @@ -183,7 +183,7 @@ static void ui__warn_map_erange(struct map *map, struct symbol *sym, u64 ip) "Not all samples will be on the annotation output.\n\n" "Please report to linux-kernel@vger.kernel.org\n", ip, dso->long_name, dso__symtab_origin(dso), - map->start, map->end, sym->start, sym->end, + map__start(map), map__end(map), sym->start, sym->end, sym->binding == STB_GLOBAL ? 'g' : sym->binding == STB_LOCAL ? 'l' : 'w', sym->name, err ? "[unknown]" : uts.machine, diff --git a/tools/perf/tests/code-reading.c b/tools/perf/tests/code-reading.c index 936c61546e64..1545fcaa95c6 100644 --- a/tools/perf/tests/code-reading.c +++ b/tools/perf/tests/code-reading.c @@ -265,8 +265,8 @@ static int read_object_code(u64 addr, size_t len, u8 cpumode, len = BUFSZ; /* Do not go off the map */ - if (addr + len > al.map->end) - len = al.map->end - addr; + if (addr + len > map__end(al.map)) + len = map__end(al.map) - addr; /* Read the object code using perf */ ret_len = dso__data_read_offset(dso, maps__machine(thread->maps), @@ -291,7 +291,7 @@ static int read_object_code(u64 addr, size_t len, u8 cpumode, size_t d; for (d = 0; d < state->done_cnt; d++) { - if (state->done[d] == al.map->start) { + if (state->done[d] == map__start(al.map)) { pr_debug("kcore map tested already"); pr_debug(" - skipping\n"); goto out; @@ -301,7 +301,7 @@ static int read_object_code(u64 addr, size_t len, u8 cpumode, pr_debug("Too many kcore maps - skipping\n"); goto out; } - state->done[state->done_cnt++] = al.map->start; + state->done[state->done_cnt++] = map__start(al.map); } objdump_name = dso->long_name; diff --git a/tools/perf/tests/maps.c b/tools/perf/tests/maps.c index ae7028fbf79e..fd0c464fcf95 100644 --- a/tools/perf/tests/maps.c +++ b/tools/perf/tests/maps.c @@ -24,8 +24,8 @@ static int check_maps(struct map_def *merged, unsigned int size, struct maps *ma if (i > 0) TEST_ASSERT_VAL("less maps expected", (map && i < size) || (!map && i == size)); - TEST_ASSERT_VAL("wrong map start", map->start == merged[i].start); - TEST_ASSERT_VAL("wrong map end", map->end == merged[i].end); + TEST_ASSERT_VAL("wrong map start", map__start(map) == merged[i].start); + TEST_ASSERT_VAL("wrong map end", map__end(map) == merged[i].end); TEST_ASSERT_VAL("wrong map name", !strcmp(map__dso(map)->name, merged[i].name)); TEST_ASSERT_VAL("wrong map refcnt", refcount_read(&map->refcnt) == 1); diff --git a/tools/perf/tests/mmap-thread-lookup.c b/tools/perf/tests/mmap-thread-lookup.c index a4301fc7b770..5cc4644e353d 100644 --- a/tools/perf/tests/mmap-thread-lookup.c +++ b/tools/perf/tests/mmap-thread-lookup.c @@ -202,7 +202,7 @@ static int mmap_events(synth_cb synth) break; } - pr_debug("map %p, addr %" PRIx64 "\n", al.map, al.map->start); + pr_debug("map %p, addr %" PRIx64 "\n", al.map, map__start(al.map)); } machine__delete_threads(machine); diff --git a/tools/perf/tests/vmlinux-kallsyms.c b/tools/perf/tests/vmlinux-kallsyms.c index c614c2db7e89..0a75623172c2 100644 --- a/tools/perf/tests/vmlinux-kallsyms.c +++ b/tools/perf/tests/vmlinux-kallsyms.c @@ -267,7 +267,7 @@ next_pair: continue; } - } else if (mem_start == kallsyms.vmlinux_map->end) { + } else if (mem_start == map__end(kallsyms.vmlinux_map)) { /* * Ignore aliases to _etext, i.e. to the end of the kernel text area, * such as __indirect_thunk_end. @@ -319,14 +319,14 @@ next_pair: maps__for_each_entry(maps, rb_node) { struct map *pair, *map = rb_node->map; - mem_start = vmlinux_map->unmap_ip(vmlinux_map, map->start); - mem_end = vmlinux_map->unmap_ip(vmlinux_map, map->end); + mem_start = vmlinux_map->unmap_ip(vmlinux_map, map__start(map)); + mem_end = vmlinux_map->unmap_ip(vmlinux_map, map__end(map)); pair = maps__find(kallsyms.kmaps, mem_start); if (pair == NULL || pair->priv) continue; - if (pair->start == mem_start) { + if (map__start(pair) == mem_start) { struct dso *dso = map__dso(map); if (!header_printed) { @@ -335,10 +335,10 @@ next_pair: } pr_info("WARN: %" PRIx64 "-%" PRIx64 " %" PRIx64 " %s in kallsyms as", - map->start, map->end, map->pgoff, dso->name); - if (mem_end != pair->end) + map__start(map), map__end(map), map->pgoff, dso->name); + if (mem_end != map__end(pair)) pr_info(":\nWARN: *%" PRIx64 "-%" PRIx64 " %" PRIx64, - pair->start, pair->end, pair->pgoff); + map__start(pair), map__end(pair), pair->pgoff); pr_info(" %s\n", dso->name); pair->priv = 1; } diff --git a/tools/perf/util/annotate.c b/tools/perf/util/annotate.c index 84100ca5f306..b9cff782d7df 100644 --- a/tools/perf/util/annotate.c +++ b/tools/perf/util/annotate.c @@ -1008,13 +1008,13 @@ int addr_map_symbol__account_cycles(struct addr_map_symbol *ams, if (start && (start->ms.sym == ams->ms.sym || (ams->ms.sym && - start->addr == ams->ms.sym->start + ams->ms.map->start))) + start->addr == ams->ms.sym->start + map__start(ams->ms.map)))) saddr = start->al_addr; if (saddr == 0) pr_debug2("BB with bad start: addr %"PRIx64" start %"PRIx64" sym %"PRIx64" saddr %"PRIx64"\n", ams->addr, start ? start->addr : 0, - ams->ms.sym ? ams->ms.sym->start + ams->ms.map->start : 0, + ams->ms.sym ? ams->ms.sym->start + map__start(ams->ms.map) : 0, saddr); err = symbol__account_cycles(ams->al_addr, saddr, ams->ms.sym, cycles); if (err) diff --git a/tools/perf/util/dlfilter.c b/tools/perf/util/dlfilter.c index 8a7ffe0d805a..fe401fa4be02 100644 --- a/tools/perf/util/dlfilter.c +++ b/tools/perf/util/dlfilter.c @@ -51,7 +51,7 @@ static void al_to_d_al(struct addr_location *al, struct perf_dlfilter_al *d_al) if (al->addr < sym->end) d_al->symoff = al->addr - sym->start; else - d_al->symoff = al->addr - al->map->start - sym->start; + d_al->symoff = al->addr - map__start(al->map) - sym->start; d_al->sym_binding = sym->binding; } else { d_al->sym = NULL; @@ -268,7 +268,7 @@ static __s32 dlfilter__object_code(void *ctx, __u64 ip, void *buf, __u32 len) map = al->map; - if (map && ip >= map->start && ip < map->end && + if (map && ip >= map__start(map) && ip < map__end(map) && machine__kernel_ip(d->machine, ip) == machine__kernel_ip(d->machine, d->sample->ip)) goto have_map; @@ -279,8 +279,8 @@ static __s32 dlfilter__object_code(void *ctx, __u64 ip, void *buf, __u32 len) map = a.map; have_map: offset = map->map_ip(map, ip); - if (ip + len >= map->end) - len = map->end - ip; + if (ip + len >= map__end(map)) + len = map__end(map) - ip; return dso__data_read_offset(map__dso(map), d->machine, offset, buf, len); } diff --git a/tools/perf/util/intel-pt.c b/tools/perf/util/intel-pt.c index 8cec88e09792..a2e62daa708e 100644 --- a/tools/perf/util/intel-pt.c +++ b/tools/perf/util/intel-pt.c @@ -887,7 +887,7 @@ static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn, goto out_no_cache; } - if (*ip >= al.map->end) + if (*ip >= map__end(al.map)) break; offset += intel_pt_insn->length; @@ -2750,7 +2750,7 @@ static u64 intel_pt_switch_ip(struct intel_pt *pt, u64 *ptss_ip) if (sym->binding == STB_GLOBAL && !strcmp(sym->name, "__switch_to")) { ip = map->unmap_ip(map, sym->start); - if (ip >= map->start && ip < map->end) { + if (ip >= map__start(map) && ip < map__end(map)) { switch_ip = ip; break; } @@ -2768,7 +2768,7 @@ static u64 intel_pt_switch_ip(struct intel_pt *pt, u64 *ptss_ip) for (sym = start; sym; sym = dso__next_symbol(sym)) { if (!strcmp(sym->name, ptss)) { ip = map->unmap_ip(map, sym->start); - if (ip >= map->start && ip < map->end) { + if (ip >= map__start(map) && ip < map__end(map)) { *ptss_ip = ip; break; } @@ -3356,7 +3356,7 @@ static int intel_pt_process_aux_output_hw_id(struct intel_pt *pt, static int intel_pt_find_map(struct thread *thread, u8 cpumode, u64 addr, struct addr_location *al) { - if (!al->map || addr < al->map->start || addr >= al->map->end) { + if (!al->map || addr < map__start(al->map) || addr >= map__end(al->map)) { if (!thread__find_map(thread, cpumode, addr, al)) return -1; } diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c index 8bae38c96788..7852b97da10a 100644 --- a/tools/perf/util/machine.c +++ b/tools/perf/util/machine.c @@ -903,7 +903,7 @@ static int machine__process_ksymbol_register(struct machine *machine, } map->start = event->ksymbol.addr; - map->end = map->start + event->ksymbol.len; + map->end = map__start(map) + event->ksymbol.len; err = maps__insert(machine__kernel_maps(machine), map); map__put(map); if (err) @@ -919,7 +919,7 @@ static int machine__process_ksymbol_register(struct machine *machine, dso = map__dso(map); } - sym = symbol__new(map->map_ip(map, map->start), + sym = symbol__new(map->map_ip(map, map__start(map)), event->ksymbol.len, 0, 0, event->ksymbol.name); if (!sym) @@ -944,7 +944,7 @@ static int machine__process_ksymbol_unregister(struct machine *machine, else { struct dso *dso = map__dso(map); - sym = dso__find_symbol(dso, map->map_ip(map, map->start)); + sym = dso__find_symbol(dso, map->map_ip(map, map__start(map))); if (sym) dso__delete_symbol(dso, sym); } @@ -1217,7 +1217,7 @@ int machine__create_extra_kernel_map(struct machine *machine, if (!err) { pr_debug2("Added extra kernel map %s %" PRIx64 "-%" PRIx64 "\n", - kmap->name, map->start, map->end); + kmap->name, map__start(map), map__end(map)); } map__put(map); @@ -1722,7 +1722,7 @@ int machine__create_kernel_maps(struct machine *machine) struct map_rb_node *next = map_rb_node__next(rb_node); if (next) - machine__set_kernel_mmap(machine, start, next->map->start); + machine__set_kernel_mmap(machine, start, map__start(next->map)); } out_put: @@ -1795,7 +1795,7 @@ static int machine__process_kernel_mmap_event(struct machine *machine, if (map == NULL) goto out_problem; - map->end = map->start + xm->end - xm->start; + map->end = map__start(map) + xm->end - xm->start; if (build_id__is_defined(bid)) dso__set_build_id(map__dso(map), bid); @@ -3293,7 +3293,7 @@ int machine__get_kernel_start(struct machine *machine) * kernel_start = 1ULL << 63 for x86_64. */ if (!err && !machine__is(machine, "x86_64")) - machine->kernel_start = map->start; + machine->kernel_start = map__start(map); } return err; } diff --git a/tools/perf/util/map.c b/tools/perf/util/map.c index 90062af6675a..416fc449bde8 100644 --- a/tools/perf/util/map.c +++ b/tools/perf/util/map.c @@ -421,7 +421,7 @@ size_t map__fprintf(struct map *map, FILE *fp) const struct dso *dso = map__dso(map); return fprintf(fp, " %" PRIx64 "-%" PRIx64 " %" PRIx64 " %s\n", - map->start, map->end, map->pgoff, dso->name); + map__start(map), map__end(map), map->pgoff, dso->name); } size_t map__fprintf_dsoname(struct map *map, FILE *fp) @@ -558,7 +558,7 @@ bool map__contains_symbol(const struct map *map, const struct symbol *sym) { u64 ip = map->unmap_ip(map, sym->start); - return ip >= map->start && ip < map->end; + return ip >= map__start(map) && ip < map__end(map); } struct kmap *__map__kmap(struct map *map) @@ -592,12 +592,12 @@ struct maps *map__kmaps(struct map *map) u64 map__map_ip(const struct map *map, u64 ip) { - return ip - map->start + map->pgoff; + return ip - map__start(map) + map->pgoff; } u64 map__unmap_ip(const struct map *map, u64 ip) { - return ip + map->start - map->pgoff; + return ip + map__start(map) - map->pgoff; } u64 identity__map_ip(const struct map *map __maybe_unused, u64 ip) diff --git a/tools/perf/util/map.h b/tools/perf/util/map.h index 36c5add0144d..16646b94fa3a 100644 --- a/tools/perf/util/map.h +++ b/tools/perf/util/map.h @@ -52,9 +52,19 @@ static inline struct dso *map__dso(const struct map *map) return map->dso; } +static inline u64 map__start(const struct map *map) +{ + return map->start; +} + +static inline u64 map__end(const struct map *map) +{ + return map->end; +} + static inline size_t map__size(const struct map *map) { - return map->end - map->start; + return map__end(map) - map__start(map); } /* rip/ip <-> addr suitable for passing to `objdump --start-address=` */ diff --git a/tools/perf/util/maps.c b/tools/perf/util/maps.c index 09ec6bbafcbc..21010a2b8e16 100644 --- a/tools/perf/util/maps.c +++ b/tools/perf/util/maps.c @@ -34,7 +34,7 @@ static int __maps__insert(struct maps *maps, struct map *map) { struct rb_node **p = &maps__entries(maps)->rb_node; struct rb_node *parent = NULL; - const u64 ip = map->start; + const u64 ip = map__start(map); struct map_rb_node *m, *new_rb_node; new_rb_node = malloc(sizeof(*new_rb_node)); @@ -47,7 +47,7 @@ static int __maps__insert(struct maps *maps, struct map *map) while (*p != NULL) { parent = *p; m = rb_entry(parent, struct map_rb_node, rb_node); - if (ip < m->map->start) + if (ip < map__start(m->map)) p = &(*p)->rb_left; else p = &(*p)->rb_right; @@ -229,7 +229,7 @@ out: int maps__find_ams(struct maps *maps, struct addr_map_symbol *ams) { - if (ams->addr < ams->ms.map->start || ams->addr >= ams->ms.map->end) { + if (ams->addr < map__start(ams->ms.map) || ams->addr >= map__end(ams->ms.map)) { if (maps == NULL) return -1; ams->ms.map = maps__find(maps, ams->addr); @@ -283,9 +283,9 @@ int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp) while (next) { struct map_rb_node *pos = rb_entry(next, struct map_rb_node, rb_node); - if (pos->map->end > map->start) { + if (map__end(pos->map) > map__start(map)) { first = next; - if (pos->map->start <= map->start) + if (map__start(pos->map) <= map__start(map)) break; next = next->rb_left; } else @@ -301,7 +301,7 @@ int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp) * Stop if current map starts after map->end. * Maps are ordered by start: next will not overlap for sure. */ - if (pos->map->start >= map->end) + if (map__start(pos->map) >= map__end(map)) break; if (verbose >= 2) { @@ -321,7 +321,7 @@ int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp) * Now check if we need to create new maps for areas not * overlapped by the new map: */ - if (map->start > pos->map->start) { + if (map__start(map) > map__start(pos->map)) { struct map *before = map__clone(pos->map); if (before == NULL) { @@ -329,7 +329,7 @@ int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp) goto put_map; } - before->end = map->start; + before->end = map__start(map); err = __maps__insert(maps, before); if (err) goto put_map; @@ -339,7 +339,7 @@ int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp) map__put(before); } - if (map->end < pos->map->end) { + if (map__end(map) < map__end(pos->map)) { struct map *after = map__clone(pos->map); if (after == NULL) { @@ -347,10 +347,10 @@ int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp) goto put_map; } - after->start = map->end; - after->pgoff += map->end - pos->map->start; - assert(pos->map->map_ip(pos->map, map->end) == - after->map_ip(after, map->end)); + after->start = map__end(map); + after->pgoff += map__end(map) - map__start(pos->map); + assert(pos->map->map_ip(pos->map, map__end(map)) == + after->map_ip(after, map__end(map))); err = __maps__insert(maps, after); if (err) goto put_map; @@ -430,9 +430,9 @@ struct map *maps__find(struct maps *maps, u64 ip) p = maps__entries(maps)->rb_node; while (p != NULL) { m = rb_entry(p, struct map_rb_node, rb_node); - if (ip < m->map->start) + if (ip < map__start(m->map)) p = p->rb_left; - else if (ip >= m->map->end) + else if (ip >= map__end(m->map)) p = p->rb_right; else goto out; diff --git a/tools/perf/util/probe-event.c b/tools/perf/util/probe-event.c index b26670a26005..4d9dbeeb6014 100644 --- a/tools/perf/util/probe-event.c +++ b/tools/perf/util/probe-event.c @@ -143,7 +143,7 @@ static int kernel_get_symbol_address_by_name(const char *name, u64 *addr, return -ENOENT; *addr = map->unmap_ip(map, sym->start) - ((reloc) ? 0 : map->reloc) - - ((reladdr) ? map->start : 0); + ((reladdr) ? map__start(map) : 0); } return 0; } @@ -257,7 +257,7 @@ static bool kprobe_warn_out_range(const char *symbol, u64 address) map = kernel_get_module_map(NULL); if (map) { - ret = address <= map->start || map->end < address; + ret = address <= map__start(map) || map__end(map) < address; if (ret) pr_warning("%s is out of .text, skip it.\n", symbol); map__put(map); diff --git a/tools/perf/util/scripting-engines/trace-event-python.c b/tools/perf/util/scripting-engines/trace-event-python.c index b8e5c6f61d80..cbf09eaf3734 100644 --- a/tools/perf/util/scripting-engines/trace-event-python.c +++ b/tools/perf/util/scripting-engines/trace-event-python.c @@ -409,7 +409,7 @@ static unsigned long get_offset(struct symbol *sym, struct addr_location *al) if (al->addr < sym->end) offset = al->addr - sym->start; else - offset = al->addr - al->map->start - sym->start; + offset = al->addr - map__start(al->map) - sym->start; return offset; } @@ -788,9 +788,9 @@ static void set_sym_in_dict(PyObject *dict, struct addr_location *al, pydict_set_item_string_decref(dict, dso_bid_field, _PyUnicode_FromString(sbuild_id)); pydict_set_item_string_decref(dict, dso_map_start, - PyLong_FromUnsignedLong(al->map->start)); + PyLong_FromUnsignedLong(map__start(al->map))); pydict_set_item_string_decref(dict, dso_map_end, - PyLong_FromUnsignedLong(al->map->end)); + PyLong_FromUnsignedLong(map__end(al->map))); } if (al->sym) { pydict_set_item_string_decref(dict, sym_field, diff --git a/tools/perf/util/symbol-elf.c b/tools/perf/util/symbol-elf.c index 561372869792..e715869eab8a 100644 --- a/tools/perf/util/symbol-elf.c +++ b/tools/perf/util/symbol-elf.c @@ -1355,7 +1355,7 @@ static int dso__process_kernel_symbol(struct dso *dso, struct map *map, if (*remap_kernel && dso->kernel && !kmodule) { *remap_kernel = false; map->start = shdr->sh_addr + ref_reloc(kmap); - map->end = map->start + shdr->sh_size; + map->end = map__start(map) + shdr->sh_size; map->pgoff = shdr->sh_offset; map->map_ip = map__map_ip; map->unmap_ip = map__unmap_ip; @@ -1397,7 +1397,7 @@ static int dso__process_kernel_symbol(struct dso *dso, struct map *map, u64 start = sym->st_value; if (kmodule) - start += map->start + shdr->sh_offset; + start += map__start(map) + shdr->sh_offset; curr_dso = dso__new(dso_name); if (curr_dso == NULL) @@ -1415,7 +1415,7 @@ static int dso__process_kernel_symbol(struct dso *dso, struct map *map, if (adjust_kernel_syms) { curr_map->start = shdr->sh_addr + ref_reloc(kmap); - curr_map->end = curr_map->start + shdr->sh_size; + curr_map->end = map__start(curr_map) + shdr->sh_size; curr_map->pgoff = shdr->sh_offset; } else { curr_map->map_ip = curr_map->unmap_ip = identity__map_ip; @@ -1536,7 +1536,7 @@ dso__load_sym_internal(struct dso *dso, struct map *map, struct symsrc *syms_ss, * attempted to prelink vdso to its virtual address. */ if (dso__is_vdso(dso)) - map->reloc = map->start - dso->text_offset; + map->reloc = map__start(map) - dso->text_offset; dso->adjust_symbols = runtime_ss->adjust_symbols || ref_reloc(kmap); /* diff --git a/tools/perf/util/symbol.c b/tools/perf/util/symbol.c index a1c85c22676f..b91deb177091 100644 --- a/tools/perf/util/symbol.c +++ b/tools/perf/util/symbol.c @@ -278,8 +278,8 @@ void maps__fixup_end(struct maps *maps) down_write(maps__lock(maps)); maps__for_each_entry(maps, curr) { - if (prev != NULL && !prev->map->end) - prev->map->end = curr->map->start; + if (prev != NULL && !map__end(prev->map)) + prev->map->end = map__start(curr->map); prev = curr; } @@ -288,7 +288,7 @@ void maps__fixup_end(struct maps *maps) * We still haven't the actual symbols, so guess the * last map final address. */ - if (curr && !curr->map->end) + if (curr && !map__end(curr->map)) curr->map->end = ~0ULL; up_write(maps__lock(maps)); @@ -810,11 +810,11 @@ static int maps__split_kallsyms_for_kcore(struct maps *kmaps, struct dso *dso) continue; } curr_map_dso = map__dso(curr_map); - pos->start -= curr_map->start - curr_map->pgoff; - if (pos->end > curr_map->end) - pos->end = curr_map->end; + pos->start -= map__start(curr_map) - curr_map->pgoff; + if (pos->end > map__end(curr_map)) + pos->end = map__end(curr_map); if (pos->end) - pos->end -= curr_map->start - curr_map->pgoff; + pos->end -= map__start(curr_map) - curr_map->pgoff; symbols__insert(&curr_map_dso->symbols, pos); ++count; } @@ -1156,7 +1156,7 @@ static int do_validate_kcore_modules(const char *filename, struct maps *kmaps) dso = map__dso(old_map); /* Module must be in memory at the same address */ mi = find_module(dso->short_name, &modules); - if (!mi || mi->start != old_map->start) { + if (!mi || mi->start != map__start(old_map)) { err = -EINVAL; goto out; } @@ -1250,7 +1250,7 @@ static int kcore_mapfn(u64 start, u64 len, u64 pgoff, void *data) return -ENOMEM; } - list_node->map->end = list_node->map->start + len; + list_node->map->end = map__start(list_node->map) + len; list_node->map->pgoff = pgoff; list_add(&list_node->node, &md->maps); @@ -1272,21 +1272,21 @@ int maps__merge_in(struct maps *kmaps, struct map *new_map) struct map *old_map = rb_node->map; /* no overload with this one */ - if (new_map->end < old_map->start || - new_map->start >= old_map->end) + if (map__end(new_map) < map__start(old_map) || + map__start(new_map) >= map__end(old_map)) continue; - if (new_map->start < old_map->start) { + if (map__start(new_map) < map__start(old_map)) { /* * |new...... * |old.... */ - if (new_map->end < old_map->end) { + if (map__end(new_map) < map__end(old_map)) { /* * |new......| -> |new..| * |old....| -> |old....| */ - new_map->end = old_map->start; + new_map->end = map__start(old_map); } else { /* * |new.............| -> |new..| |new..| @@ -1306,17 +1306,17 @@ int maps__merge_in(struct maps *kmaps, struct map *new_map) goto out; } - m->map->end = old_map->start; + m->map->end = map__start(old_map); list_add_tail(&m->node, &merged); - new_map->pgoff += old_map->end - new_map->start; - new_map->start = old_map->end; + new_map->pgoff += map__end(old_map) - map__start(new_map); + new_map->start = map__end(old_map); } } else { /* * |new...... * |old.... */ - if (new_map->end < old_map->end) { + if (map__end(new_map) < map__end(old_map)) { /* * |new..| -> x * |old.........| -> |old.........| @@ -1329,8 +1329,8 @@ int maps__merge_in(struct maps *kmaps, struct map *new_map) * |new......| -> |new...| * |old....| -> |old....| */ - new_map->pgoff += old_map->end - new_map->start; - new_map->start = old_map->end; + new_map->pgoff += map__end(old_map) - map__start(new_map); + new_map->start = map__end(old_map); } } } @@ -1428,9 +1428,9 @@ static int dso__load_kcore(struct dso *dso, struct map *map, list_for_each_entry(new_node, &md.maps, node) { struct map *new_map = new_node->map; - u64 new_size = new_map->end - new_map->start; + u64 new_size = map__size(new_map); - if (!(stext >= new_map->start && stext < new_map->end)) + if (!(stext >= map__start(new_map) && stext < map__end(new_map))) continue; /* @@ -1457,8 +1457,8 @@ static int dso__load_kcore(struct dso *dso, struct map *map, list_del_init(&new_node->node); if (new_map == replacement_map) { - map->start = new_map->start; - map->end = new_map->end; + map->start = map__start(new_map); + map->end = map__end(new_map); map->pgoff = new_map->pgoff; map->map_ip = new_map->map_ip; map->unmap_ip = new_map->unmap_ip; diff --git a/tools/perf/util/symbol_fprintf.c b/tools/perf/util/symbol_fprintf.c index 2664fb65e47a..d9e5ad040b6a 100644 --- a/tools/perf/util/symbol_fprintf.c +++ b/tools/perf/util/symbol_fprintf.c @@ -30,7 +30,7 @@ size_t __symbol__fprintf_symname_offs(const struct symbol *sym, if (al->addr < sym->end) offset = al->addr - sym->start; else - offset = al->addr - al->map->start - sym->start; + offset = al->addr - map__start(al->map) - sym->start; length += fprintf(fp, "+0x%lx", offset); } return length; diff --git a/tools/perf/util/synthetic-events.c b/tools/perf/util/synthetic-events.c index fbd1a882b013..b2e4afa5efa1 100644 --- a/tools/perf/util/synthetic-events.c +++ b/tools/perf/util/synthetic-events.c @@ -706,8 +706,8 @@ int perf_event__synthesize_modules(struct perf_tool *tool, perf_event__handler_t (sizeof(event->mmap2.filename) - size)); memset(event->mmap2.filename + size, 0, machine->id_hdr_size); event->mmap2.header.size += machine->id_hdr_size; - event->mmap2.start = map->start; - event->mmap2.len = map->end - map->start; + event->mmap2.start = map__start(map); + event->mmap2.len = map__size(map); event->mmap2.pid = machine->pid; memcpy(event->mmap2.filename, dso->long_name, dso->long_name_len + 1); @@ -720,8 +720,8 @@ int perf_event__synthesize_modules(struct perf_tool *tool, perf_event__handler_t (sizeof(event->mmap.filename) - size)); memset(event->mmap.filename + size, 0, machine->id_hdr_size); event->mmap.header.size += machine->id_hdr_size; - event->mmap.start = map->start; - event->mmap.len = map->end - map->start; + event->mmap.start = map__start(map); + event->mmap.len = map__size(map); event->mmap.pid = machine->pid; memcpy(event->mmap.filename, dso->long_name, dso->long_name_len + 1); @@ -1143,8 +1143,8 @@ static int __perf_event__synthesize_kernel_mmap(struct perf_tool *tool, event->mmap2.header.size = (sizeof(event->mmap2) - (sizeof(event->mmap2.filename) - size) + machine->id_hdr_size); event->mmap2.pgoff = kmap->ref_reloc_sym->addr; - event->mmap2.start = map->start; - event->mmap2.len = map->end - event->mmap.start; + event->mmap2.start = map__start(map); + event->mmap2.len = map__end(map) - event->mmap.start; event->mmap2.pid = machine->pid; perf_record_mmap2__read_build_id(&event->mmap2, machine, true); @@ -1156,8 +1156,8 @@ static int __perf_event__synthesize_kernel_mmap(struct perf_tool *tool, event->mmap.header.size = (sizeof(event->mmap) - (sizeof(event->mmap.filename) - size) + machine->id_hdr_size); event->mmap.pgoff = kmap->ref_reloc_sym->addr; - event->mmap.start = map->start; - event->mmap.len = map->end - event->mmap.start; + event->mmap.start = map__start(map); + event->mmap.len = map__end(map) - event->mmap.start; event->mmap.pid = machine->pid; } diff --git a/tools/perf/util/unwind-libdw.c b/tools/perf/util/unwind-libdw.c index c8cba9d4bfd9..b79f57e5648f 100644 --- a/tools/perf/util/unwind-libdw.c +++ b/tools/perf/util/unwind-libdw.c @@ -62,19 +62,19 @@ static int __report_module(struct addr_location *al, u64 ip, Dwarf_Addr s; dwfl_module_info(mod, NULL, &s, NULL, NULL, NULL, NULL, NULL); - if (s != al->map->start - al->map->pgoff) + if (s != map__start(al->map) - al->map->pgoff) mod = 0; } if (!mod) mod = dwfl_report_elf(ui->dwfl, dso->short_name, dso->long_name, -1, - al->map->start - al->map->pgoff, false); + map__start(al->map) - al->map->pgoff, false); if (!mod) { char filename[PATH_MAX]; if (dso__build_id_filename(dso, filename, sizeof(filename), false)) mod = dwfl_report_elf(ui->dwfl, dso->short_name, filename, -1, - al->map->start - al->map->pgoff, false); + map__start(al->map) - al->map->pgoff, false); } if (mod) { diff --git a/tools/perf/util/unwind-libunwind-local.c b/tools/perf/util/unwind-libunwind-local.c index 108f7b1697a7..1c13f43e7d22 100644 --- a/tools/perf/util/unwind-libunwind-local.c +++ b/tools/perf/util/unwind-libunwind-local.c @@ -327,9 +327,10 @@ static int read_unwind_spec_eh_frame(struct dso *dso, struct unwind_info *ui, maps__for_each_entry(ui->thread->maps, map_node) { struct map *map = map_node->map; + u64 start = map__start(map); - if (map__dso(map) == dso && map->start < base_addr) - base_addr = map->start; + if (map__dso(map) == dso && start < base_addr) + base_addr = start; } base_addr -= dso->data.elf_base_addr; /* Address of .eh_frame_hdr */ @@ -443,8 +444,8 @@ find_proc_info(unw_addr_space_t as, unw_word_t ip, unw_proc_info_t *pi, if (!read_unwind_spec_eh_frame(dso, ui, &table_data, &segbase, &fde_count)) { memset(&di, 0, sizeof(di)); di.format = UNW_INFO_FORMAT_REMOTE_TABLE; - di.start_ip = map->start; - di.end_ip = map->end; + di.start_ip = map__start(map); + di.end_ip = map__end(map); di.u.rti.segbase = segbase; di.u.rti.table_data = table_data; di.u.rti.table_len = fde_count * sizeof(struct table_entry) @@ -459,7 +460,8 @@ find_proc_info(unw_addr_space_t as, unw_word_t ip, unw_proc_info_t *pi, !read_unwind_spec_debug_frame(dso, ui->machine, &segbase)) { int fd = dso__data_get_fd(dso, ui->machine); int is_exec = elf_is_exec(fd, dso->name); - unw_word_t base = is_exec ? 0 : map->start; + u64 start = map__start(map); + unw_word_t base = is_exec ? 0 : start; const char *symfile; if (fd >= 0) @@ -468,8 +470,7 @@ find_proc_info(unw_addr_space_t as, unw_word_t ip, unw_proc_info_t *pi, symfile = dso->symsrc_filename ?: dso->name; memset(&di, 0, sizeof(di)); - if (dwarf_find_debug_frame(0, &di, ip, base, symfile, - map->start, map->end)) + if (dwarf_find_debug_frame(0, &di, ip, base, symfile, start, map__end(map))) return dwarf_search_unwind_table(as, ip, &di, pi, need_unwind_info, arg); } -- cgit v1.2.3-58-ga151 From 3d88aec0d42eec26b633fb2a473e294a1125bbd7 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Wed, 5 Apr 2023 23:52:23 -0700 Subject: perf pmu: Make parser reentrant By default bison uses global state for compatibility with yacc. Make the parser reentrant so that it may be used in asynchronous and multithreaded situations. Signed-off-by: Ian Rogers Acked-by: Jiri Olsa Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Gaosheng Cui Cc: German Gomez Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Leo Yan Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Rob Herring Cc: Sean Christopherson Cc: Suzuki Poulouse Link: https://lore.kernel.org/r/20230406065224.2553640-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/pmu.c | 26 ++++++++++++++++++++------ tools/perf/util/pmu.h | 2 +- tools/perf/util/pmu.l | 17 ++++++++++++----- tools/perf/util/pmu.y | 5 ++++- 4 files changed, 37 insertions(+), 13 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 78a407b42ad1..96ef317bac41 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -24,6 +24,8 @@ #include "evsel.h" #include "pmu.h" #include "pmus.h" +#include "pmu-bison.h" +#include "pmu-flex.h" #include "parse-events.h" #include "print-events.h" #include "header.h" @@ -57,9 +59,6 @@ struct perf_pmu_format { struct list_head list; }; -int perf_pmu_parse(struct list_head *list, char *name); -extern FILE *perf_pmu_in; - static bool hybrid_scanned; static struct perf_pmu *perf_pmu__find2(int dirfd, const char *name); @@ -81,6 +80,8 @@ int perf_pmu__format_parse(int dirfd, struct list_head *head) while (!ret && (evt_ent = readdir(format_dir))) { char *name = evt_ent->d_name; int fd; + void *scanner; + FILE *file; if (!strcmp(name, ".") || !strcmp(name, "..")) continue; @@ -91,9 +92,22 @@ int perf_pmu__format_parse(int dirfd, struct list_head *head) if (fd < 0) break; - perf_pmu_in = fdopen(fd, "r"); - ret = perf_pmu_parse(head, name); - fclose(perf_pmu_in); + file = fdopen(fd, "r"); + if (!file) { + close(fd); + break; + } + + ret = perf_pmu_lex_init(&scanner); + if (ret) { + fclose(file); + break; + } + + perf_pmu_set_in(file, scanner); + ret = perf_pmu_parse(head, name, scanner); + perf_pmu_lex_destroy(scanner); + fclose(file); } closedir(format_dir); diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h index 32c3a75bca0e..d53618c65c92 100644 --- a/tools/perf/util/pmu.h +++ b/tools/perf/util/pmu.h @@ -206,7 +206,7 @@ int perf_pmu__check_alias(struct perf_pmu *pmu, struct list_head *head_terms, struct perf_pmu_info *info); struct list_head *perf_pmu__alias(struct perf_pmu *pmu, struct list_head *head_terms); -void perf_pmu_error(struct list_head *list, char *name, char const *msg); +void perf_pmu_error(struct list_head *list, char *name, void *scanner, char const *msg); int perf_pmu__new_format(struct list_head *list, char *name, int config, unsigned long *bits); diff --git a/tools/perf/util/pmu.l b/tools/perf/util/pmu.l index 58b4926cfaca..67b247be693b 100644 --- a/tools/perf/util/pmu.l +++ b/tools/perf/util/pmu.l @@ -1,4 +1,6 @@ %option prefix="perf_pmu_" +%option reentrant +%option bison-bridge %{ #include @@ -6,16 +8,21 @@ #include "pmu.h" #include "pmu-bison.h" -static int value(int base) +char *perf_pmu_get_text(yyscan_t yyscanner); +YYSTYPE *perf_pmu_get_lval(yyscan_t yyscanner); + +static int value(yyscan_t scanner, int base) { + YYSTYPE *yylval = perf_pmu_get_lval(scanner); + char *text = perf_pmu_get_text(scanner); long num; errno = 0; - num = strtoul(perf_pmu_text, NULL, base); + num = strtoul(text, NULL, base); if (errno) return PP_ERROR; - perf_pmu_lval.num = num; + yylval->num = num; return PP_VALUE; } @@ -25,7 +32,7 @@ num_dec [0-9]+ %% -{num_dec} { return value(10); } +{num_dec} { return value(yyscanner, 10); } config { return PP_CONFIG; } - { return '-'; } : { return ':'; } @@ -35,7 +42,7 @@ config { return PP_CONFIG; } %% -int perf_pmu_wrap(void) +int perf_pmu_wrap(void *scanner __maybe_unused) { return 1; } diff --git a/tools/perf/util/pmu.y b/tools/perf/util/pmu.y index e675d79a0274..dff4e892ac4d 100644 --- a/tools/perf/util/pmu.y +++ b/tools/perf/util/pmu.y @@ -1,6 +1,8 @@ - +%define api.pure full %parse-param {struct list_head *format} %parse-param {char *name} +%parse-param {void *scanner} +%lex-param {void* scanner} %{ @@ -78,6 +80,7 @@ PP_VALUE void perf_pmu_error(struct list_head *list __maybe_unused, char *name __maybe_unused, + void *scanner __maybe_unused, char const *msg __maybe_unused) { } -- cgit v1.2.3-58-ga151 From 0ea8920e86e3232c56dc812c1f363fd20fce46c6 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Wed, 5 Apr 2023 23:52:24 -0700 Subject: perf pmu: Fix a few potential fd leaks Ensure fd is closed on error paths. Signed-off-by: Ian Rogers Acked-by: Jiri Olsa Acked-by: Namhyung Kim Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Gaosheng Cui Cc: German Gomez Cc: Ingo Molnar Cc: James Clark Cc: Jing Zhang Cc: Leo Yan Cc: Mark Rutland Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Rob Herring Cc: Sean Christopherson Cc: Suzuki Poulouse Link: https://lore.kernel.org/r/20230406065224.2553640-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/pmu.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 96ef317bac41..9eedbfc9e863 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -494,9 +494,13 @@ static int pmu_aliases_parse(int dirfd, struct list_head *head) continue; fd = openat(dirfd, name, O_RDONLY); + if (fd == -1) { + pr_debug("Cannot open %s\n", name); + continue; + } file = fdopen(fd, "r"); if (!file) { - pr_debug("Cannot open %s\n", name); + close(fd); continue; } @@ -1882,9 +1886,13 @@ int perf_pmu__caps_parse(struct perf_pmu *pmu) continue; fd = openat(caps_fd, name, O_RDONLY); + if (fd == -1) + continue; file = fdopen(fd, "r"); - if (!file) + if (!file) { + close(fd); continue; + } if (!fgets(value, sizeof(value), file) || (perf_pmu__new_caps(&pmu->caps, name, value) < 0)) { -- cgit v1.2.3-58-ga151 From f7a858bffcddaaf70c71b6b656e7cc21b6107cec Mon Sep 17 00:00:00 2001 From: Liam Howlett Date: Fri, 25 Nov 2022 15:50:16 +0000 Subject: tools: Rename __fallthrough to fallthrough MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename the fallthrough attribute to better align with the kernel version. Copy the definition from include/linux/compiler_attributes.h including the #else clause. Adding the #else clause allows the tools compiler.h header to drop the check for a definition entirely and keeps both definitions together. Change any __fallthrough statements to fallthrough anywhere it was used within perf. This allows other tools to use the same key word as the kernel. Committer notes: Did some missing conversions to: builtin-list.c Also included gtk.h before the 'fallthrough' definition in: tools/perf/ui/gtk/hists.c tools/perf/ui/gtk/helpline.c tools/perf/ui/gtk/browser.c As it is the arg name for a macro in glib.h: /var/home/acme/git/perf-tools-next/tools/include/linux/compiler-gcc.h:16:55: error: missing binary operator before token "(" 16 | # define fallthrough __attribute__((__fallthrough__)) | ^ /usr/include/glib-2.0/glib/gmacros.h:637:28: note: in expansion of macro ‘fallthrough’ 637 | #if g_macro__has_attribute(fallthrough) Reviewed-by: Miguel Ojeda Signed-off-by: Liam Howlett Cc: Ingo Molnar Cc: Mark Rutland Cc: Miguel Ojeda Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Peter Zijlstra Cc: Rasmus Villemoes Cc: Tom Rix Cc: linux-sparse@vger.kernel.org Cc: llvm@lists.linux.dev Link: https://lore.kernel.org/r/20221125154947.2163498-1-Liam.Howlett@oracle.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/include/linux/compiler-gcc.h | 6 ++++-- tools/include/linux/compiler.h | 4 ---- tools/perf/builtin-list.c | 4 ++-- tools/perf/builtin-probe.c | 2 +- tools/perf/builtin-stat.c | 2 +- tools/perf/builtin-top.c | 2 +- tools/perf/ui/gtk/browser.c | 2 +- tools/perf/ui/gtk/helpline.c | 2 +- tools/perf/ui/gtk/hists.c | 2 +- tools/perf/util/callchain.c | 4 ++-- tools/perf/util/intel-pt-decoder/intel-pt-decoder.c | 6 +++--- tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c | 2 +- tools/perf/util/ordered-events.c | 2 +- tools/perf/util/strfilter.c | 2 +- tools/perf/util/string.c | 2 +- 15 files changed, 21 insertions(+), 23 deletions(-) (limited to 'tools') diff --git a/tools/include/linux/compiler-gcc.h b/tools/include/linux/compiler-gcc.h index 8816f06fc6c7..62e7c901ac28 100644 --- a/tools/include/linux/compiler-gcc.h +++ b/tools/include/linux/compiler-gcc.h @@ -12,8 +12,10 @@ + __GNUC_PATCHLEVEL__) #endif -#if GCC_VERSION >= 70000 && !defined(__CHECKER__) -# define __fallthrough __attribute__ ((fallthrough)) +#if __has_attribute(__fallthrough__) +# define fallthrough __attribute__((__fallthrough__)) +#else +# define fallthrough do {} while (0) /* fallthrough */ #endif #if __has_attribute(__error__) diff --git a/tools/include/linux/compiler.h b/tools/include/linux/compiler.h index 90ba44a99199..9d36c8ce1fe7 100644 --- a/tools/include/linux/compiler.h +++ b/tools/include/linux/compiler.h @@ -186,10 +186,6 @@ static __always_inline void __write_once_size(volatile void *p, void *res, int s }) -#ifndef __fallthrough -# define __fallthrough -#endif - /* Indirect macros required for expanded argument pasting, eg. __LINE__. */ #define ___PASTE(a, b) a##b #define __PASTE(a, b) ___PASTE(a, b) diff --git a/tools/perf/builtin-list.c b/tools/perf/builtin-list.c index 76e1d31a68ee..29f09cefed88 100644 --- a/tools/perf/builtin-list.c +++ b/tools/perf/builtin-list.c @@ -278,10 +278,10 @@ static void fix_escape_printf(struct strbuf *buf, const char *fmt, ...) strbuf_addstr(buf, "\\n"); break; case '\\': - __fallthrough; + fallthrough; case '\"': strbuf_addch(buf, '\\'); - __fallthrough; + fallthrough; default: strbuf_addch(buf, s[s_pos]); break; diff --git a/tools/perf/builtin-probe.c b/tools/perf/builtin-probe.c index e72f6cea76f7..4df05b992093 100644 --- a/tools/perf/builtin-probe.c +++ b/tools/perf/builtin-probe.c @@ -715,7 +715,7 @@ __cmd_probe(int argc, const char **argv) pr_err(" Error: --bootconfig doesn't support uprobes.\n"); return -EINVAL; } - __fallthrough; + fallthrough; case 'a': /* Ensure the last given target is used */ diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index 7ef565ae7265..38133afda7fc 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -549,7 +549,7 @@ static void process_evlist(struct evlist *evlist, unsigned int interval) if (evlist__ctlfd_process(evlist, &cmd) > 0) { switch (cmd) { case EVLIST_CTL_CMD_ENABLE: - __fallthrough; + fallthrough; case EVLIST_CTL_CMD_DISABLE: if (interval) process_interval(); diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c index b803af4329d1..3162bad0d17d 100644 --- a/tools/perf/builtin-top.c +++ b/tools/perf/builtin-top.c @@ -709,7 +709,7 @@ repeat: case -1: if (errno == EINTR) continue; - __fallthrough; + fallthrough; default: c = getc(stdin); tcsetattr(0, TCSAFLUSH, &save); diff --git a/tools/perf/ui/gtk/browser.c b/tools/perf/ui/gtk/browser.c index 8f3e43d148a8..d2dadf3873fb 100644 --- a/tools/perf/ui/gtk/browser.c +++ b/tools/perf/ui/gtk/browser.c @@ -1,9 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 +#include "gtk.h" #include "../evsel.h" #include "../sort.h" #include "../hist.h" #include "../helpline.h" -#include "gtk.h" #include diff --git a/tools/perf/ui/gtk/helpline.c b/tools/perf/ui/gtk/helpline.c index e40a006aead8..8ea95898a5bd 100644 --- a/tools/perf/ui/gtk/helpline.c +++ b/tools/perf/ui/gtk/helpline.c @@ -1,9 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 +#include "gtk.h" #include #include #include -#include "gtk.h" #include "../ui.h" #include "../helpline.h" diff --git a/tools/perf/ui/gtk/hists.c b/tools/perf/ui/gtk/hists.c index c83be2d57f7e..bae21f336ae6 100644 --- a/tools/perf/ui/gtk/hists.c +++ b/tools/perf/ui/gtk/hists.c @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +#include "gtk.h" #include "../evlist.h" #include "../callchain.h" #include "../evsel.h" @@ -6,7 +7,6 @@ #include "../hist.h" #include "../helpline.h" #include "../string2.h" -#include "gtk.h" #include #include #include diff --git a/tools/perf/util/callchain.c b/tools/perf/util/callchain.c index 9e9c39dd9d2b..8e7c29836765 100644 --- a/tools/perf/util/callchain.c +++ b/tools/perf/util/callchain.c @@ -724,7 +724,7 @@ static enum match_result match_chain(struct callchain_cursor_node *node, if (match != MATCH_ERROR) break; /* otherwise fall-back to symbol-based comparison below */ - __fallthrough; + fallthrough; case CCKEY_FUNCTION: if (node->ms.sym && cnode->ms.sym) { /* @@ -745,7 +745,7 @@ static enum match_result match_chain(struct callchain_cursor_node *node, } } /* otherwise fall-back to IP-based comparison below */ - __fallthrough; + fallthrough; case CCKEY_ADDRESS: default: match = match_chain_dso_addresses(cnode->ms.map, cnode->ip, node->ms.map, node->ip); diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c b/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c index 7145c5890de0..b450178e3420 100644 --- a/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c +++ b/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c @@ -3546,7 +3546,7 @@ static int intel_pt_walk_psb(struct intel_pt_decoder *decoder) switch (decoder->packet.type) { case INTEL_PT_TIP_PGD: decoder->continuous_period = false; - __fallthrough; + fallthrough; case INTEL_PT_TIP_PGE: case INTEL_PT_TIP: case INTEL_PT_PTWRITE: @@ -3616,7 +3616,7 @@ static int intel_pt_walk_psb(struct intel_pt_decoder *decoder) decoder->pge = false; decoder->continuous_period = false; intel_pt_clear_tx_flags(decoder); - __fallthrough; + fallthrough; case INTEL_PT_TNT: decoder->have_tma = false; @@ -3980,7 +3980,7 @@ const struct intel_pt_state *intel_pt_decode(struct intel_pt_decoder *decoder) decoder->have_last_ip = false; decoder->last_ip = 0; decoder->ip = 0; - __fallthrough; + fallthrough; case INTEL_PT_STATE_ERR_RESYNC: err = intel_pt_sync_ip(decoder); break; diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c b/tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c index 18f97f43e01a..af9710622a1f 100644 --- a/tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c +++ b/tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c @@ -730,7 +730,7 @@ int intel_pt_pkt_desc(const struct intel_pt_pkt *packet, char *buf, case INTEL_PT_FUP: if (!(packet->count)) return snprintf(buf, buf_len, "%s no ip", name); - __fallthrough; + fallthrough; case INTEL_PT_CYC: case INTEL_PT_VMCS: case INTEL_PT_MTC: diff --git a/tools/perf/util/ordered-events.c b/tools/perf/util/ordered-events.c index b887dfeea673..8c62611f10aa 100644 --- a/tools/perf/util/ordered-events.c +++ b/tools/perf/util/ordered-events.c @@ -284,7 +284,7 @@ static int __ordered_events__flush(struct ordered_events *oe, enum oe_flush how, switch (how) { case OE_FLUSH__FINAL: show_progress = true; - __fallthrough; + fallthrough; case OE_FLUSH__TOP: oe->next_flush = ULLONG_MAX; break; diff --git a/tools/perf/util/strfilter.c b/tools/perf/util/strfilter.c index 78aa4c3b990d..02807b9d4122 100644 --- a/tools/perf/util/strfilter.c +++ b/tools/perf/util/strfilter.c @@ -274,7 +274,7 @@ static int strfilter_node__sprint(struct strfilter_node *node, char *buf) len = strfilter_node__sprint_pt(node->l, buf); if (len < 0) return len; - __fallthrough; + fallthrough; case '!': if (buf) { *(buf + len++) = *node->p; diff --git a/tools/perf/util/string.c b/tools/perf/util/string.c index 4f12a96f33cc..cf05b0b56c57 100644 --- a/tools/perf/util/string.c +++ b/tools/perf/util/string.c @@ -35,7 +35,7 @@ s64 perf_atoll(const char *str) if (*p) goto out_err; - __fallthrough; + fallthrough; case '\0': return length; default: -- cgit v1.2.3-58-ga151 From d783ea8f62c4e58cea1d04567048368691128d5e Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Thu, 6 Apr 2023 14:06:05 -0700 Subject: perf lock contention: Simplify parse_lock_type() The get_type_flag() should check both str and name fields in the lock_type_table so that it can find the appropriate flag without retrying with ':R' or ':W' suffix from the caller. Also fix a typo in the rt-mutex. Signed-off-by: Namhyung Kim Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Hao Luo Cc: Ingo Molnar Cc: Jiri Olsa Cc: Juri Lelli Cc: Peter Zijlstra Cc: Song Liu Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230406210611.1622492-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-lock.c | 43 ++++++++----------------------------------- 1 file changed, 8 insertions(+), 35 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-lock.c b/tools/perf/builtin-lock.c index 32ec58fb80e4..695ce6bd64f7 100644 --- a/tools/perf/builtin-lock.c +++ b/tools/perf/builtin-lock.c @@ -1557,7 +1557,7 @@ static const struct { { LCB_F_SPIN | LCB_F_WRITE, "rwlock:W", "rwlock" }, { LCB_F_READ, "rwsem:R", "rwsem" }, { LCB_F_WRITE, "rwsem:W", "rwsem" }, - { LCB_F_RT, "rt=mutex", "rt-mutex" }, + { LCB_F_RT, "rt-mutex", "rt-mutex" }, { LCB_F_RT | LCB_F_READ, "rwlock-rt:R", "rwlock-rt" }, { LCB_F_RT | LCB_F_WRITE, "rwlock-rt:W", "rwlock-rt" }, { LCB_F_PERCPU | LCB_F_READ, "pcpu-sem:R", "percpu-rwsem" }, @@ -1596,6 +1596,10 @@ static unsigned int get_type_flag(const char *str) if (!strcmp(lock_type_table[i].name, str)) return lock_type_table[i].flags; } + for (unsigned int i = 0; i < ARRAY_SIZE(lock_type_table); i++) { + if (!strcmp(lock_type_table[i].str, str)) + return lock_type_table[i].flags; + } return UINT_MAX; } @@ -2121,46 +2125,15 @@ static int parse_lock_type(const struct option *opt __maybe_unused, const char * unsigned int flags = get_type_flag(tok); if (flags == -1U) { - char buf[32]; - - if (strchr(tok, ':')) - continue; - - /* try :R and :W suffixes for rwlock, rwsem, ... */ - scnprintf(buf, sizeof(buf), "%s:R", tok); - flags = get_type_flag(buf); - if (flags != UINT_MAX) { - if (!add_lock_type(flags)) { - ret = -1; - break; - } - } - - scnprintf(buf, sizeof(buf), "%s:W", tok); - flags = get_type_flag(buf); - if (flags != UINT_MAX) { - if (!add_lock_type(flags)) { - ret = -1; - break; - } - } - continue; + pr_err("Unknown lock flags: %s\n", tok); + ret = -1; + break; } if (!add_lock_type(flags)) { ret = -1; break; } - - if (!strcmp(tok, "mutex")) { - flags = get_type_flag("mutex-spin"); - if (flags != UINT_MAX) { - if (!add_lock_type(flags)) { - ret = -1; - break; - } - } - } } free(s); -- cgit v1.2.3-58-ga151 From 84b91920304f5e640ac922cb721f5c70617a83e8 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Thu, 6 Apr 2023 14:06:06 -0700 Subject: perf lock contention: Use -M for --map-nr-entries Users often want to change the map size, let's add a short option (-M) for that. Signed-off-by: Namhyung Kim Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Hao Luo Cc: Ingo Molnar Cc: Jiri Olsa Cc: Juri Lelli Cc: Peter Zijlstra Cc: Song Liu Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230406210611.1622492-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Documentation/perf-lock.txt | 1 + tools/perf/builtin-lock.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/Documentation/perf-lock.txt b/tools/perf/Documentation/perf-lock.txt index 37aae194a2a1..b5e5d088d51c 100644 --- a/tools/perf/Documentation/perf-lock.txt +++ b/tools/perf/Documentation/perf-lock.txt @@ -155,6 +155,7 @@ CONTENTION OPTIONS --tid=:: Record events on existing thread ID (comma separated list). +-M:: --map-nr-entries=:: Maximum number of BPF map entries (default: 10240). diff --git a/tools/perf/builtin-lock.c b/tools/perf/builtin-lock.c index 695ce6bd64f7..ef56bf90058d 100644 --- a/tools/perf/builtin-lock.c +++ b/tools/perf/builtin-lock.c @@ -2294,7 +2294,7 @@ int cmd_lock(int argc, const char **argv) "Trace on existing process id"), OPT_STRING(0, "tid", &target.tid, "tid", "Trace on existing thread id (exclusive to --pid)"), - OPT_CALLBACK(0, "map-nr-entries", &bpf_map_entries, "num", + OPT_CALLBACK('M', "map-nr-entries", &bpf_map_entries, "num", "Max number of BPF map entries", parse_map_entry), OPT_CALLBACK(0, "max-stack", &max_stack_depth, "num", "Set the maximum stack depth when collecting lopck contention, " -- cgit v1.2.3-58-ga151 From 2d8d016527928ad65ad1fe11c9943d8b81f05d18 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Thu, 6 Apr 2023 14:06:07 -0700 Subject: perf lock contention: Update default map size to 16384 The BPF hash map will align the map size to a power of 2. So 10k would be 16k anyway. Let's have the actual size to avoid confusions. Signed-off-by: Namhyung Kim Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Hao Luo Cc: Ingo Molnar Cc: Jiri Olsa Cc: Juri Lelli Cc: Peter Zijlstra Cc: Song Liu Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230406210611.1622492-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Documentation/perf-lock.txt | 3 ++- tools/perf/builtin-lock.c | 2 +- tools/perf/util/bpf_skel/lock_contention.bpf.c | 5 +---- tools/perf/util/bpf_skel/lock_data.h | 3 +++ 4 files changed, 7 insertions(+), 6 deletions(-) (limited to 'tools') diff --git a/tools/perf/Documentation/perf-lock.txt b/tools/perf/Documentation/perf-lock.txt index b5e5d088d51c..6e5ba3cd2b72 100644 --- a/tools/perf/Documentation/perf-lock.txt +++ b/tools/perf/Documentation/perf-lock.txt @@ -157,7 +157,8 @@ CONTENTION OPTIONS -M:: --map-nr-entries=:: - Maximum number of BPF map entries (default: 10240). + Maximum number of BPF map entries (default: 16384). + This will be aligned to a power of 2. --max-stack=:: Maximum stack depth when collecting lock contention (default: 8). diff --git a/tools/perf/builtin-lock.c b/tools/perf/builtin-lock.c index ef56bf90058d..9b92c7a5aefb 100644 --- a/tools/perf/builtin-lock.c +++ b/tools/perf/builtin-lock.c @@ -60,7 +60,7 @@ static bool show_thread_stats; static bool show_lock_addrs; static bool show_lock_owner; static bool use_bpf; -static unsigned long bpf_map_entries = 10240; +static unsigned long bpf_map_entries = MAX_ENTRIES; static int max_stack_depth = CONTENTION_STACK_DEPTH; static int stack_skip = CONTENTION_STACK_SKIP; static int print_nr_entries = INT_MAX / 2; diff --git a/tools/perf/util/bpf_skel/lock_contention.bpf.c b/tools/perf/util/bpf_skel/lock_contention.bpf.c index 3f4ee3992e81..f9d2d792ccc8 100644 --- a/tools/perf/util/bpf_skel/lock_contention.bpf.c +++ b/tools/perf/util/bpf_skel/lock_contention.bpf.c @@ -7,9 +7,6 @@ #include "lock_data.h" -/* default buffer size */ -#define MAX_ENTRIES 10240 - /* for collect_lock_syms(). 4096 was rejected by the verifier */ #define MAX_CPUS 1024 @@ -63,7 +60,7 @@ struct { __uint(type, BPF_MAP_TYPE_HASH); __uint(key_size, sizeof(__u64)); __uint(value_size, sizeof(__u32)); - __uint(max_entries, 16384); + __uint(max_entries, MAX_ENTRIES); } lock_syms SEC(".maps"); struct { diff --git a/tools/perf/util/bpf_skel/lock_data.h b/tools/perf/util/bpf_skel/lock_data.h index 1ba61cb4d480..260062a9f2ab 100644 --- a/tools/perf/util/bpf_skel/lock_data.h +++ b/tools/perf/util/bpf_skel/lock_data.h @@ -15,6 +15,9 @@ struct contention_task_data { char comm[TASK_COMM_LEN]; }; +/* default buffer size */ +#define MAX_ENTRIES 16384 + /* * Upper bits of the flags in the contention_data are used to identify * some well-known locks which do not have symbols (non-global locks). -- cgit v1.2.3-58-ga151 From 954cdac74e1e7aca518c8ef49d4fa70c8ae72d7b Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Thu, 6 Apr 2023 14:06:08 -0700 Subject: perf lock contention: Add data failure stat It's possible to fail to update the data when the lock_stat map is full. We should check that case and show the number at the end. $ sudo ./perf lock con -ablv -E3 -- ./perf bench sched messaging ... contended total wait max wait avg wait address symbol 6157 208.48 ms 69.29 us 33.86 us ffff934c001c1f00 (spinlock) 4030 72.04 ms 61.84 us 17.88 us ffff934c000415c0 (spinlock) 3201 50.30 ms 47.73 us 15.71 us ffff934c2eead850 (spinlock) === output for debug === bad: 0, total: 13388 bad rate: 0.00 % histogram of failure reasons task: 0 stack: 0 time: 0 data: 0 <----- added Signed-off-by: Namhyung Kim Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Hao Luo Cc: Ingo Molnar Cc: Jiri Olsa Cc: Juri Lelli Cc: Peter Zijlstra Cc: Song Liu Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230406210611.1622492-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-lock.c | 4 +++- tools/perf/util/bpf_lock_contention.c | 1 + tools/perf/util/bpf_skel/lock_contention.bpf.c | 4 +++- tools/perf/util/lock-contention.h | 1 + 4 files changed, 8 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-lock.c b/tools/perf/builtin-lock.c index 9b92c7a5aefb..01b318d6c80a 100644 --- a/tools/perf/builtin-lock.c +++ b/tools/perf/builtin-lock.c @@ -1626,7 +1626,7 @@ static void sort_contention_result(void) static void print_bpf_events(int total, struct lock_contention_fails *fails) { /* Output for debug, this have to be removed */ - int broken = fails->task + fails->stack + fails->time; + int broken = fails->task + fails->stack + fails->time + fails->data; if (quiet || total == 0 || (broken == 0 && verbose <= 0)) return; @@ -1640,7 +1640,9 @@ static void print_bpf_events(int total, struct lock_contention_fails *fails) pr_info(" %10s: %d\n", "task", fails->task); pr_info(" %10s: %d\n", "stack", fails->stack); pr_info(" %10s: %d\n", "time", fails->time); + pr_info(" %10s: %d\n", "data", fails->data); } + static void print_contention_result(struct lock_contention *con) { struct lock_stat *st; diff --git a/tools/perf/util/bpf_lock_contention.c b/tools/perf/util/bpf_lock_contention.c index 8a5d0eb44189..0071058ac3d2 100644 --- a/tools/perf/util/bpf_lock_contention.c +++ b/tools/perf/util/bpf_lock_contention.c @@ -262,6 +262,7 @@ int lock_contention_read(struct lock_contention *con) con->fails.task = skel->bss->task_fail; con->fails.stack = skel->bss->stack_fail; con->fails.time = skel->bss->time_fail; + con->fails.data = skel->bss->data_fail; stack_trace = zalloc(stack_size); if (stack_trace == NULL) diff --git a/tools/perf/util/bpf_skel/lock_contention.bpf.c b/tools/perf/util/bpf_skel/lock_contention.bpf.c index f9d2d792ccc8..cb87c98e5340 100644 --- a/tools/perf/util/bpf_skel/lock_contention.bpf.c +++ b/tools/perf/util/bpf_skel/lock_contention.bpf.c @@ -124,6 +124,7 @@ int aggr_mode; int task_fail; int stack_fail; int time_fail; +int data_fail; static inline int can_record(u64 *ctx) { @@ -380,7 +381,8 @@ int contention_end(u64 *ctx) if (aggr_mode == LOCK_AGGR_ADDR) first.flags |= check_lock_type(pelem->lock, pelem->flags); - bpf_map_update_elem(&lock_stat, &key, &first, BPF_NOEXIST); + if (bpf_map_update_elem(&lock_stat, &key, &first, BPF_NOEXIST) < 0) + __sync_fetch_and_add(&data_fail, 1); bpf_map_delete_elem(&tstamp, &pid); return 0; } diff --git a/tools/perf/util/lock-contention.h b/tools/perf/util/lock-contention.h index 10c28302420c..3ed1cad370fc 100644 --- a/tools/perf/util/lock-contention.h +++ b/tools/perf/util/lock-contention.h @@ -126,6 +126,7 @@ struct lock_contention_fails { int task; int stack; int time; + int data; }; struct lock_contention { -- cgit v1.2.3-58-ga151 From aae7e4534adbd96598d06e449d4f05867b0ed23f Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Thu, 6 Apr 2023 14:06:09 -0700 Subject: perf lock contention: Update total/bad stats for hidden entries When -E option is used, it only prints the given number of entries but the event stat at the end should have the numbers for entire entries. Likewise, -S option will hide entries that don't have the named function in the callstack. Also update event stat for them. Signed-off-by: Namhyung Kim Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Hao Luo Cc: Ingo Molnar Cc: Jiri Olsa Cc: Juri Lelli Cc: Peter Zijlstra Cc: Song Liu Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230406210611.1622492-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-lock.c | 11 +++++++++++ tools/perf/util/bpf_lock_contention.c | 4 +++- tools/perf/util/lock-contention.h | 1 + 3 files changed, 15 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/builtin-lock.c b/tools/perf/builtin-lock.c index 01b318d6c80a..7742fa255c44 100644 --- a/tools/perf/builtin-lock.c +++ b/tools/perf/builtin-lock.c @@ -1726,6 +1726,17 @@ static void print_contention_result(struct lock_contention *con) break; } + if (print_nr_entries) { + /* update the total/bad stats */ + while ((st = pop_from_result())) { + total += use_bpf ? st->nr_contended : 1; + if (st->broken) + bad++; + } + } + /* some entries are collected but hidden by the callstack filter */ + total += con->nr_filtered; + if (use_bpf) print_bpf_events(total, &con->fails); else diff --git a/tools/perf/util/bpf_lock_contention.c b/tools/perf/util/bpf_lock_contention.c index 0071058ac3d2..ea4f697d2a9f 100644 --- a/tools/perf/util/bpf_lock_contention.c +++ b/tools/perf/util/bpf_lock_contention.c @@ -299,8 +299,10 @@ int lock_contention_read(struct lock_contention *con) if (con->save_callstack) { bpf_map_lookup_elem(stack, &key.stack_id, stack_trace); - if (!match_callstack_filter(machine, stack_trace)) + if (!match_callstack_filter(machine, stack_trace)) { + con->nr_filtered += data.count; goto next; + } } switch (con->aggr_mode) { diff --git a/tools/perf/util/lock-contention.h b/tools/perf/util/lock-contention.h index 3ed1cad370fc..fa16532c971c 100644 --- a/tools/perf/util/lock-contention.h +++ b/tools/perf/util/lock-contention.h @@ -141,6 +141,7 @@ struct lock_contention { int stack_skip; int aggr_mode; int owner; + int nr_filtered; bool save_callstack; }; -- cgit v1.2.3-58-ga151 From 0fba226548501099616b7f1cc73c853ffd560511 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Thu, 6 Apr 2023 14:06:10 -0700 Subject: perf lock contention: Revise needs_callstack() condition It needs callstacks for two reasons: * for stack aggregation mode, the map key is the stack id and it can also show the full stack traces when -v is used * for other aggregation modes, the stack filter can be used to limit lock contentions from known call paths The -v option is meaningful (in terms of stack trace) only for stack aggregation mode, so it should not set the save_callstack for other mode like with -t or -l options. I've noticed this with the following command line: $ sudo ./perf lock con -ablv -E 3 -M 16 -- ./perf bench sched messaging ... contended total wait max wait avg wait address symbol 88 4.59 ms 108.07 us 52.13 us ffff935757f46ec0 (spinlock) 33 905.22 us 73.67 us 27.43 us ffff935757f41700 (spinlock) 28 703.69 us 79.28 us 25.13 us ffff938a3d9b0c80 rq_lock (spinlock) === output for debug === bad: 12272, total: 12421 bad rate: 98.80 % histogram of failure reasons task: 8285 stack: 3987 <---------- here time: 0 data: 0 It should not have any failure on stacks since it doesn't use it. No functional change intended. Signed-off-by: Namhyung Kim Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Hao Luo Cc: Ingo Molnar Cc: Jiri Olsa Cc: Juri Lelli Cc: Peter Zijlstra Cc: Song Liu Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230406210611.1622492-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-lock.c | 2 +- tools/perf/util/bpf_lock_contention.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-lock.c b/tools/perf/builtin-lock.c index 7742fa255c44..4e24351b18bd 100644 --- a/tools/perf/builtin-lock.c +++ b/tools/perf/builtin-lock.c @@ -77,7 +77,7 @@ static enum lock_aggr_mode aggr_mode = LOCK_AGGR_ADDR; static bool needs_callstack(void) { - return verbose > 0 || !list_empty(&callstack_filters); + return !list_empty(&callstack_filters); } static struct thread_stat *thread_stat_find(u32 tid) diff --git a/tools/perf/util/bpf_lock_contention.c b/tools/perf/util/bpf_lock_contention.c index ea4f697d2a9f..9e20fa8ade09 100644 --- a/tools/perf/util/bpf_lock_contention.c +++ b/tools/perf/util/bpf_lock_contention.c @@ -346,7 +346,7 @@ int lock_contention_read(struct lock_contention *con) if (data.count) st->avg_wait_time = data.total_time / data.count; - if (con->save_callstack) { + if (con->aggr_mode == LOCK_AGGR_CALLER && verbose > 0) { st->callstack = memdup(stack_trace, stack_size); if (st->callstack == NULL) break; -- cgit v1.2.3-58-ga151 From 222de5e53926252bf8815751ba555778cf8ff6ca Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Thu, 6 Apr 2023 14:06:11 -0700 Subject: perf lock contention: Do not try to update if hash map is full It doesn't delete data in the task_data and lock_stat maps. The data is kept there until it's consumed by userspace at the end. But it calls bpf_map_update_elem() again and again, and the data will be discarded if the map is full. This is not good. Worse, in the bpf_map_update_elem(), it keeps trying to get a new node even if the map was full. I guess it makes sense if it deletes some node like in the tstamp map (that's why I didn't make the change there). In a pre-allocated hash map, that means it'd iterate all CPU to check the freelist. And it has a bad performance impact on large machines. I've checked it on my 64 CPU machine with this. $ perf bench sched messaging -g 1000 # Running 'sched/messaging' benchmark: # 20 sender and receiver processes per group # 1000 groups == 40000 processes run Total time: 2.825 [sec] And I used the task mode, so that it can guarantee the map is full. The default map entry size is 16K and this workload has 40K tasks. Before: $ sudo ./perf lock con -abt -E3 -- perf bench sched messaging -g 1000 # Running 'sched/messaging' benchmark: # 20 sender and receiver processes per group # 1000 groups == 40000 processes run Total time: 11.299 [sec] contended total wait max wait avg wait pid comm 19284 3.51 s 3.70 ms 181.91 us 1305863 sched-messaging 243 84.09 ms 466.67 us 346.04 us 1336608 sched-messaging 177 66.35 ms 12.08 ms 374.88 us 1220416 node For some reason, it didn't report the data failures. But you can see the total time in the workload is increased a lot (2.8 -> 11.3). If it fails early when the map is full, it goes back to normal. After: $ sudo ./perf lock con -abt -E3 -- perf bench sched messaging -g 1000 # Running 'sched/messaging' benchmark: # 20 sender and receiver processes per group # 1000 groups == 40000 processes run Total time: 3.044 [sec] contended total wait max wait avg wait pid comm 18743 591.92 ms 442.96 us 31.58 us 1431454 sched-messaging 51 210.64 ms 207.45 ms 4.13 ms 1468724 sched-messaging 81 68.61 ms 65.79 ms 847.07 us 1463183 sched-messaging === output for debug === bad: 1164137, total: 2253341 bad rate: 51.66 % histogram of failure reasons task: 0 stack: 0 time: 0 data: 1164137 Signed-off-by: Namhyung Kim Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Hao Luo Cc: Ingo Molnar Cc: Jiri Olsa Cc: Juri Lelli Cc: Peter Zijlstra Cc: Song Liu Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230406210611.1622492-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/bpf_skel/lock_contention.bpf.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/bpf_skel/lock_contention.bpf.c b/tools/perf/util/bpf_skel/lock_contention.bpf.c index cb87c98e5340..23f6e63544ed 100644 --- a/tools/perf/util/bpf_skel/lock_contention.bpf.c +++ b/tools/perf/util/bpf_skel/lock_contention.bpf.c @@ -4,6 +4,7 @@ #include #include #include +#include #include "lock_data.h" @@ -126,6 +127,9 @@ int stack_fail; int time_fail; int data_fail; +int task_map_full; +int data_map_full; + static inline int can_record(u64 *ctx) { if (has_cpu) { @@ -177,11 +181,12 @@ static inline int update_task_data(struct task_struct *task) return -1; p = bpf_map_lookup_elem(&task_data, &pid); - if (p == NULL) { + if (p == NULL && !task_map_full) { struct contention_task_data data = {}; BPF_CORE_READ_STR_INTO(&data.comm, task, comm); - bpf_map_update_elem(&task_data, &pid, &data, BPF_NOEXIST); + if (bpf_map_update_elem(&task_data, &pid, &data, BPF_NOEXIST) == -E2BIG) + task_map_full = 1; } return 0; @@ -370,6 +375,12 @@ int contention_end(u64 *ctx) data = bpf_map_lookup_elem(&lock_stat, &key); if (!data) { + if (data_map_full) { + bpf_map_delete_elem(&tstamp, &pid); + __sync_fetch_and_add(&data_fail, 1); + return 0; + } + struct contention_data first = { .total_time = duration, .max_time = duration, @@ -377,12 +388,17 @@ int contention_end(u64 *ctx) .count = 1, .flags = pelem->flags, }; + int err; if (aggr_mode == LOCK_AGGR_ADDR) first.flags |= check_lock_type(pelem->lock, pelem->flags); - if (bpf_map_update_elem(&lock_stat, &key, &first, BPF_NOEXIST) < 0) + err = bpf_map_update_elem(&lock_stat, &key, &first, BPF_NOEXIST); + if (err < 0) { + if (err == -E2BIG) + data_map_full = 1; __sync_fetch_and_add(&data_fail, 1); + } bpf_map_delete_elem(&tstamp, &pid); return 0; } -- cgit v1.2.3-58-ga151 From 330f40a0d951d7f23995ccbfeea9be7282942e93 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 6 Apr 2023 16:52:54 -0700 Subject: perf pmu: Fewer const casts struct pmu_event has const char*s, only unit needs to be non-const for the sake of passing as an out argument to strtod(). Reduce the const casts from 4 down to 1. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Rob Herring Cc: Sean Christopherson Cc: Suzuki Poulouse Link: https://lore.kernel.org/r/20230406235256.2768773-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/pmu.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 9eedbfc9e863..d033343f75f9 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -352,16 +352,16 @@ static int __perf_pmu__new_alias(struct list_head *list, int dirfd, char *name, struct perf_pmu_alias *alias; int ret; char newval[256]; - char *long_desc = NULL, *topic = NULL, *unit = NULL, *pmu_name = NULL; + const char *long_desc = NULL, *topic = NULL, *unit = NULL, *pmu_name = NULL; bool deprecated = false, perpkg = false; if (pe) { - long_desc = (char *)pe->long_desc; - topic = (char *)pe->topic; - unit = (char *)pe->unit; + long_desc = pe->long_desc; + topic = pe->topic; + unit = pe->unit; perpkg = pe->perpkg; deprecated = pe->deprecated; - pmu_name = (char *)pe->pmu; + pmu_name = pe->pmu; } alias = malloc(sizeof(*alias)); @@ -419,7 +419,7 @@ static int __perf_pmu__new_alias(struct list_head *list, int dirfd, char *name, desc ? strdup(desc) : NULL; alias->topic = topic ? strdup(topic) : NULL; if (unit) { - if (perf_pmu__convert_scale(unit, &unit, &alias->scale) < 0) + if (perf_pmu__convert_scale(unit, (char **)&unit, &alias->scale) < 0) return -1; snprintf(alias->unit, sizeof(alias->unit), "%s", unit); } -- cgit v1.2.3-58-ga151 From 240e6fd0a923933493192e71f191d9326ba53f0b Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 6 Apr 2023 16:52:55 -0700 Subject: perf pmu: Improve name/comments, avoid a memory allocation Improve documentation around perf_pmu_alias pmu_name and on functions. Reduce the scope of pmu_uncore_alias_match to just file. Rename perf_pmu__valid_suffix to the more revealing perf_pmu__match_ignoring_suffix. Add a short-cut to perf_pmu__match_ignoring_suffix for PMU names that don't also have a socket value, and can therefore avoid a memory allocation. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Rob Herring Cc: Sean Christopherson Cc: Suzuki Poulouse Link: https://lore.kernel.org/r/20230406235256.2768773-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/pmu.c | 27 ++++++++++++++++++++------- tools/perf/util/pmu.h | 8 +++++--- 2 files changed, 25 insertions(+), 10 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index d033343f75f9..2e4f60b49959 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -686,11 +686,14 @@ __weak const struct pmu_metrics_table *pmu_metrics_table__find(void) return perf_pmu__find_metrics_table(NULL); } -/* - * Suffix must be in form tok_{digits}, or tok{digits}, or same as pmu_name - * to be valid. +/** + * perf_pmu__match_ignoring_suffix - Does the pmu_name match tok ignoring any + * trailing suffix? The Suffix must be in form + * tok_{digits}, or tok{digits}. + * @pmu_name: The pmu_name with possible suffix. + * @tok: The possible match to pmu_name without suffix. */ -static bool perf_pmu__valid_suffix(const char *pmu_name, char *tok) +static bool perf_pmu__match_ignoring_suffix(const char *pmu_name, const char *tok) { const char *p; @@ -715,11 +718,21 @@ static bool perf_pmu__valid_suffix(const char *pmu_name, char *tok) return true; } -bool pmu_uncore_alias_match(const char *pmu_name, const char *name) +/** + * pmu_uncore_alias_match - does name match the PMU name? + * @pmu_name: the json struct pmu_event name. This may lack a suffix (which + * matches) or be of the form "socket,pmuname" which will match + * "socketX_pmunameY". + * @name: a real full PMU name as from sysfs. + */ +static bool pmu_uncore_alias_match(const char *pmu_name, const char *name) { char *tmp = NULL, *tok, *str; bool res; + if (strchr(pmu_name, ',') == NULL) + return perf_pmu__match_ignoring_suffix(name, pmu_name); + str = strdup(pmu_name); if (!str) return false; @@ -746,7 +759,7 @@ bool pmu_uncore_alias_match(const char *pmu_name, const char *name) name = strstr(name, tok); if (!name || - (!next_tok && !perf_pmu__valid_suffix(name, tok))) { + (!next_tok && !perf_pmu__match_ignoring_suffix(name, tok))) { res = false; goto out; } @@ -1961,7 +1974,7 @@ int perf_pmu__match(char *pattern, char *name, char *tok) if (fnmatch(pattern, name, 0)) return -1; - if (tok && !perf_pmu__valid_suffix(name, tok)) + if (tok && !perf_pmu__match_ignoring_suffix(name, tok)) return -1; return 0; diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h index d53618c65c92..b9a02dedd473 100644 --- a/tools/perf/util/pmu.h +++ b/tools/perf/util/pmu.h @@ -35,7 +35,7 @@ struct perf_pmu_caps { }; /** - * struct perf_pmu - hi + * struct perf_pmu */ struct perf_pmu { /** @name: The name of the PMU such as "cpu". */ @@ -186,7 +186,10 @@ struct perf_pmu_alias { * default. */ bool deprecated; - /** @pmu_name: The name copied from struct perf_pmu. */ + /** + * @pmu_name: The name copied from the json struct pmu_event. This can + * differ from the PMU name as it won't have suffixes. + */ char *pmu_name; }; @@ -238,7 +241,6 @@ void pmu_add_cpu_aliases_table(struct list_head *head, struct perf_pmu *pmu, char *perf_pmu__getcpuid(struct perf_pmu *pmu); const struct pmu_events_table *pmu_events_table__find(void); const struct pmu_metrics_table *pmu_metrics_table__find(void); -bool pmu_uncore_alias_match(const char *pmu_name, const char *name); void perf_pmu_free_alias(struct perf_pmu_alias *alias); int perf_pmu__convert_scale(const char *scale, char **end, double *sval); -- cgit v1.2.3-58-ga151 From 3f980eab56d1c4226bcb91a5f21c9c32a56edb5a Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 6 Apr 2023 16:52:56 -0700 Subject: perf pmu: Sort and remove duplicates using JSON PMU name We may have a lot of copies of a particular uncore PMU, such as uncore_cha_0 to uncore_cha_59 on Intel sapphirerapids. The JSON events may match each of PMUs and so the events are copied to it. In 'perf list' this means we see the same JSON event 60 times as events on different PMUs don't have duplicates removed. There are 284 uncore_cha events on sapphirerapids. Rather than use the PMU's name to sort and remove duplicates, use the JSON PMU name. This reduces the 60 copies back down to 1 and has the side effect of speeding things like the "perf all PMU test" shell test. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Rob Herring Cc: Sean Christopherson Cc: Suzuki Poulouse Link: https://lore.kernel.org/r/20230406235256.2768773-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/pmu.c | 47 +++++++++++++++++++++++++++++++---------------- 1 file changed, 31 insertions(+), 16 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 2e4f60b49959..91cccfb3c515 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -1574,7 +1574,7 @@ static int cmp_sevent(const void *a, const void *b) { const struct sevent *as = a; const struct sevent *bs = b; - const char *a_pmu_name, *b_pmu_name; + const char *a_pmu_name = NULL, *b_pmu_name = NULL; const char *a_name = "//", *a_desc = NULL, *a_topic = ""; const char *b_name = "//", *b_desc = NULL, *b_topic = ""; int ret; @@ -1583,11 +1583,13 @@ static int cmp_sevent(const void *a, const void *b) a_name = as->event->name; a_desc = as->event->desc; a_topic = as->event->topic ?: ""; + a_pmu_name = as->event->pmu_name; } if (bs->event) { b_name = bs->event->name; b_desc = bs->event->desc; b_topic = bs->event->topic ?: ""; + b_pmu_name = bs->event->pmu_name; } /* Put extra events last. */ if (!!a_desc != !!b_desc) @@ -1603,11 +1605,13 @@ static int cmp_sevent(const void *a, const void *b) return as->is_cpu ? -1 : 1; /* Order by PMU name. */ - a_pmu_name = as->pmu->name ?: ""; - b_pmu_name = bs->pmu->name ?: ""; - ret = strcmp(a_pmu_name, b_pmu_name); - if (ret) - return ret; + if (as->pmu != bs->pmu) { + a_pmu_name = a_pmu_name ?: (as->pmu->name ?: ""); + b_pmu_name = b_pmu_name ?: (bs->pmu->name ?: ""); + ret = strcmp(a_pmu_name, b_pmu_name); + if (ret) + return ret; + } /* Order by event name. */ return strcmp(a_name, b_name); @@ -1621,17 +1625,26 @@ bool is_pmu_core(const char *name) static bool pmu_alias_is_duplicate(struct sevent *alias_a, struct sevent *alias_b) { - const char *a_pmu_name, *b_pmu_name; - const char *a_name = alias_a->event ? alias_a->event->name : "//"; - const char *b_name = alias_b->event ? alias_b->event->name : "//"; + const char *a_pmu_name = NULL, *b_pmu_name = NULL; + const char *a_name = "//", *b_name = "//"; + + + if (alias_a->event) { + a_name = alias_a->event->name; + a_pmu_name = alias_a->event->pmu_name; + } + if (alias_b->event) { + b_name = alias_b->event->name; + b_pmu_name = alias_b->event->pmu_name; + } /* Different names -> never duplicates */ if (strcmp(a_name, b_name)) return false; /* Don't remove duplicates for different PMUs */ - a_pmu_name = alias_a->pmu->name ?: ""; - b_pmu_name = alias_b->pmu->name ?: ""; + a_pmu_name = a_pmu_name ?: (alias_a->pmu->name ?: ""); + b_pmu_name = b_pmu_name ?: (alias_b->pmu->name ?: ""); return strcmp(a_pmu_name, b_pmu_name) == 0; } @@ -1680,7 +1693,8 @@ void print_pmu_events(const struct print_callbacks *print_cb, void *print_state) for (j = 0; j < len; j++) { const char *name, *alias = NULL, *scale_unit = NULL, *desc = NULL, *long_desc = NULL, - *encoding_desc = NULL, *topic = NULL; + *encoding_desc = NULL, *topic = NULL, + *pmu_name = NULL; bool deprecated = false; size_t buf_used; @@ -1690,7 +1704,8 @@ void print_pmu_events(const struct print_callbacks *print_cb, void *print_state) if (!aliases[j].event) { /* A selectable event. */ - buf_used = snprintf(buf, sizeof(buf), "%s//", aliases[j].pmu->name) + 1; + pmu_name = aliases[j].pmu->name; + buf_used = snprintf(buf, sizeof(buf), "%s//", pmu_name) + 1; name = buf; } else { if (aliases[j].event->desc) { @@ -1705,6 +1720,7 @@ void print_pmu_events(const struct print_callbacks *print_cb, void *print_state) } buf_used = strlen(buf) + 1; } + pmu_name = aliases[j].event->pmu_name ?: (aliases[j].pmu->name ?: ""); if (strlen(aliases[j].event->unit) || aliases[j].event->scale != 1.0) { scale_unit = buf + buf_used; buf_used += snprintf(buf + buf_used, sizeof(buf) - buf_used, @@ -1716,12 +1732,11 @@ void print_pmu_events(const struct print_callbacks *print_cb, void *print_state) topic = aliases[j].event->topic; encoding_desc = buf + buf_used; buf_used += snprintf(buf + buf_used, sizeof(buf) - buf_used, - "%s/%s/", aliases[j].pmu->name, - aliases[j].event->str) + 1; + "%s/%s/", pmu_name, aliases[j].event->str) + 1; deprecated = aliases[j].event->deprecated; } print_cb->print_event(print_state, - aliases[j].pmu->name, + pmu_name, topic, name, alias, -- cgit v1.2.3-58-ga151 From 2e4555b015de6b1429f70263633c622c06c5c6eb Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 6 Apr 2023 17:13:18 -0700 Subject: perf vendor events intel: Update free running alderlake events Fix the PMU name, event code and umask. These updates were generated by: https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py with this PR: https://github.com/intel/perfmon/pull/66 Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230407001322.2776268-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/alderlake/uncore-memory.json | 16 ++++++++++++---- .../pmu-events/arch/x86/alderlaken/uncore-memory.json | 16 ++++++++++++---- 2 files changed, 24 insertions(+), 8 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json b/tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json index 2ccd9cf96957..163d7e7755c4 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json @@ -1,29 +1,37 @@ [ { "BriefDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).", + "EventCode": "0xff", "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", "PerPkg": "1", "PublicDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).", - "Unit": "iMC" + "UMask": "0x20", + "Unit": "imc_free_running_0" }, { "BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", + "EventCode": "0xff", "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", "PerPkg": "1", - "Unit": "iMC" + "UMask": "0x30", + "Unit": "imc_free_running_0" }, { "BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels).", + "EventCode": "0xff", "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", "PerPkg": "1", "PublicDescription": "Counts every 64B read entering the Memory Controller 1 to DRAM (sum of all channels).", - "Unit": "iMC" + "UMask": "0x20", + "Unit": "imc_free_running_1" }, { "BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", + "EventCode": "0xff", "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", "PerPkg": "1", - "Unit": "iMC" + "UMask": "0x30", + "Unit": "imc_free_running_1" }, { "BriefDescription": "ACT command for a read request sent to DRAM", diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json index 2ccd9cf96957..163d7e7755c4 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json @@ -1,29 +1,37 @@ [ { "BriefDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).", + "EventCode": "0xff", "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", "PerPkg": "1", "PublicDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels).", - "Unit": "iMC" + "UMask": "0x20", + "Unit": "imc_free_running_0" }, { "BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", + "EventCode": "0xff", "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", "PerPkg": "1", - "Unit": "iMC" + "UMask": "0x30", + "Unit": "imc_free_running_0" }, { "BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels).", + "EventCode": "0xff", "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", "PerPkg": "1", "PublicDescription": "Counts every 64B read entering the Memory Controller 1 to DRAM (sum of all channels).", - "Unit": "iMC" + "UMask": "0x20", + "Unit": "imc_free_running_1" }, { "BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", + "EventCode": "0xff", "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", "PerPkg": "1", - "Unit": "iMC" + "UMask": "0x30", + "Unit": "imc_free_running_1" }, { "BriefDescription": "ACT command for a read request sent to DRAM", -- cgit v1.2.3-58-ga151 From 5a45940b56fe0c67674ffa964b85f44b4fbb4e38 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 6 Apr 2023 17:13:19 -0700 Subject: perf vendor events intel: Update free running icelakex events Fix the PMU names, event code and umask. Remove UNC_IIO_BANDWIDTH_OUT events that aren't supported. These updates were generated by: https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py with this PR: https://github.com/intel/perfmon/pull/66 Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230407001322.2776268-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/x86/icelakex/uncore-memory.json | 4 +- .../pmu-events/arch/x86/icelakex/uncore-other.json | 84 +++++++--------------- 2 files changed, 30 insertions(+), 58 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json index 66bb4538c6f2..814d9599474d 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json @@ -106,9 +106,11 @@ }, { "BriefDescription": "Free running counter that increments for the Memory Controller", + "EventCode": "0xff", "EventName": "UNC_M_CLOCKTICKS_FREERUN", "PerPkg": "1", - "Unit": "iMC" + "UMask": "0x10", + "Unit": "imc_free_running" }, { "BriefDescription": "DRAM Precharge All Commands", diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json index b1d29877c141..8210e286eec1 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json @@ -9859,99 +9859,67 @@ }, { "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN", "PerPkg": "1", - "Unit": "IIO" + "UMask": "0x20", + "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN", "PerPkg": "1", - "Unit": "IIO" + "UMask": "0x21", + "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN", "PerPkg": "1", - "Unit": "IIO" + "UMask": "0x22", + "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN", "PerPkg": "1", - "Unit": "IIO" + "UMask": "0x23", + "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN", "PerPkg": "1", - "Unit": "IIO" + "UMask": "0x24", + "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN", "PerPkg": "1", - "Unit": "IIO" + "UMask": "0x25", + "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN", "PerPkg": "1", - "Unit": "IIO" + "UMask": "0x26", + "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN", "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventName": "UNC_IIO_BANDWIDTH_OUT.PART0_FREERUN", - "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventName": "UNC_IIO_BANDWIDTH_OUT.PART1_FREERUN", - "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventName": "UNC_IIO_BANDWIDTH_OUT.PART2_FREERUN", - "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventName": "UNC_IIO_BANDWIDTH_OUT.PART3_FREERUN", - "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventName": "UNC_IIO_BANDWIDTH_OUT.PART4_FREERUN", - "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventName": "UNC_IIO_BANDWIDTH_OUT.PART5_FREERUN", - "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventName": "UNC_IIO_BANDWIDTH_OUT.PART6_FREERUN", - "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventName": "UNC_IIO_BANDWIDTH_OUT.PART7_FREERUN", - "PerPkg": "1", - "Unit": "IIO" + "UMask": "0x27", + "Unit": "iio_free_running" }, { "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller", @@ -9963,10 +9931,12 @@ }, { "BriefDescription": "Free running counter that increments for IIO clocktick", + "EventCode": "0xff", "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", "PerPkg": "1", "PublicDescription": "Free running counter that increments for integrated IO (IIO) traffic controller clockticks", - "Unit": "IIO" + "UMask": "0x10", + "Unit": "iio_free_running" }, { "BriefDescription": "PCIe Completion Buffer Inserts : All Ports", -- cgit v1.2.3-58-ga151 From 54bc363afa5bbc97d9ce3423ec54ac907a95c669 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 6 Apr 2023 17:13:20 -0700 Subject: perf vendor events intel: Correct knightslanding memory topic Correct the memory topic of events for the imc related PMUs. These updates were generated by: https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py with this PR: https://github.com/intel/perfmon/pull/66 Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230407001322.2776268-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/x86/knightslanding/uncore-memory.json | 38 ++++++++++++++++++++++ .../arch/x86/knightslanding/uncore-other.json | 36 -------------------- 2 files changed, 38 insertions(+), 36 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/knightslanding/uncore-memory.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-memory.json b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-memory.json new file mode 100644 index 000000000000..47da947b1a6e --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-memory.json @@ -0,0 +1,38 @@ +[ + { + "BriefDescription": "CAS All", + "EventCode": "0x03", + "EventName": "UNC_M_CAS_COUNT.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC_DCLK" + }, + { + "BriefDescription": "CAS Reads", + "EventCode": "0x03", + "EventName": "UNC_M_CAS_COUNT.RD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC_DCLK" + }, + { + "BriefDescription": "CAS Writes", + "EventCode": "0x03", + "EventName": "UNC_M_CAS_COUNT.WR", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC_DCLK" + }, + { + "BriefDescription": "DCLK count", + "EventName": "UNC_M_D_CLOCKTICKS", + "PerPkg": "1", + "Unit": "iMC_DCLK" + }, + { + "BriefDescription": "UCLK count", + "EventName": "UNC_M_U_CLOCKTICKS", + "PerPkg": "1", + "Unit": "iMC_UCLK" + } +] diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json index 491cb37ddab0..fc85e0c95318 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json @@ -3621,41 +3621,5 @@ "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" - }, - { - "BriefDescription": "CAS All", - "EventCode": "0x03", - "EventName": "UNC_M_CAS_COUNT.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "iMC_DCLK" - }, - { - "BriefDescription": "CAS Reads", - "EventCode": "0x03", - "EventName": "UNC_M_CAS_COUNT.RD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "iMC_DCLK" - }, - { - "BriefDescription": "CAS Writes", - "EventCode": "0x03", - "EventName": "UNC_M_CAS_COUNT.WR", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "iMC_DCLK" - }, - { - "BriefDescription": "DCLK count", - "EventName": "UNC_M_D_CLOCKTICKS", - "PerPkg": "1", - "Unit": "iMC_DCLK" - }, - { - "BriefDescription": "UCLK count", - "EventName": "UNC_M_U_CLOCKTICKS", - "PerPkg": "1", - "Unit": "iMC_UCLK" } ] -- cgit v1.2.3-58-ga151 From 4781f1f270fea983a6579ddad5e8dc8ad33f1fed Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 6 Apr 2023 17:13:21 -0700 Subject: perf vendor events intel: Update free running snowridgex events Fix the PMU names, event code and umask. Remove UNC_IIO_BANDWIDTH_OUT events that aren't supported. These updates were generated by: https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py with this PR: https://github.com/intel/perfmon/pull/66 Signed-off-by: Ian Rogers : Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230407001322.2776268-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/x86/snowridgex/uncore-memory.json | 4 +- .../arch/x86/snowridgex/uncore-other.json | 92 +++++++--------------- 2 files changed, 30 insertions(+), 66 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json index 7dc0910694ed..530e9b71b92a 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json @@ -127,10 +127,12 @@ }, { "BriefDescription": "Free running counter that increments for the Memory Controller", + "EventCode": "0xff", "EventName": "UNC_M_CLOCKTICKS_FREERUN", "PerPkg": "1", "PublicDescription": "UNC_M_CLOCKTICKS_FREERUN", - "Unit": "iMC" + "UMask": "0x10", + "Unit": "imc_free_running" }, { "BriefDescription": "DRAM Precharge All Commands", diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json index 3b35e08e24d6..8bd041bc0c57 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json @@ -7129,115 +7129,75 @@ }, { "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN", "PerPkg": "1", "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN", - "Unit": "IIO" + "UMask": "0x20", + "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN", "PerPkg": "1", "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN", - "Unit": "IIO" + "UMask": "0x21", + "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN", "PerPkg": "1", "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN", - "Unit": "IIO" + "UMask": "0x22", + "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN", "PerPkg": "1", "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN", - "Unit": "IIO" + "UMask": "0x23", + "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN", "PerPkg": "1", "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN", - "Unit": "IIO" + "UMask": "0x24", + "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN", "PerPkg": "1", "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN", - "Unit": "IIO" + "UMask": "0x25", + "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN", "PerPkg": "1", "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN", - "Unit": "IIO" + "UMask": "0x26", + "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN", "PerPkg": "1", "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN", - "Unit": "IIO" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventName": "UNC_IIO_BANDWIDTH_OUT.PART0_FREERUN", - "PerPkg": "1", - "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART0_FREERUN", - "Unit": "IIO" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventName": "UNC_IIO_BANDWIDTH_OUT.PART1_FREERUN", - "PerPkg": "1", - "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART1_FREERUN", - "Unit": "IIO" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventName": "UNC_IIO_BANDWIDTH_OUT.PART2_FREERUN", - "PerPkg": "1", - "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART2_FREERUN", - "Unit": "IIO" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventName": "UNC_IIO_BANDWIDTH_OUT.PART3_FREERUN", - "PerPkg": "1", - "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART3_FREERUN", - "Unit": "IIO" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventName": "UNC_IIO_BANDWIDTH_OUT.PART4_FREERUN", - "PerPkg": "1", - "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART4_FREERUN", - "Unit": "IIO" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventName": "UNC_IIO_BANDWIDTH_OUT.PART5_FREERUN", - "PerPkg": "1", - "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART5_FREERUN", - "Unit": "IIO" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventName": "UNC_IIO_BANDWIDTH_OUT.PART6_FREERUN", - "PerPkg": "1", - "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART6_FREERUN", - "Unit": "IIO" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventName": "UNC_IIO_BANDWIDTH_OUT.PART7_FREERUN", - "PerPkg": "1", - "PublicDescription": "UNC_IIO_BANDWIDTH_OUT.PART7_FREERUN", - "Unit": "IIO" + "UMask": "0x27", + "Unit": "iio_free_running" }, { "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller", @@ -7248,10 +7208,12 @@ }, { "BriefDescription": "Free running counter that increments for IIO clocktick", + "EventCode": "0xff", "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", "PerPkg": "1", "PublicDescription": "Free running counter that increments for integrated IO (IIO) traffic controller clockticks", - "Unit": "IIO" + "UMask": "0x10", + "Unit": "iio_free_running" }, { "BriefDescription": "PCIe Completion Buffer Inserts : All Ports", -- cgit v1.2.3-58-ga151 From 5a4f5be9c91ab79762747f39c14ad43d27a389dc Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 6 Apr 2023 17:13:22 -0700 Subject: perf vendor events intel: Update free running tigerlake events Fix the topic, PMU name, event code and umask. These updates were generated by: https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py with this PR: https://github.com/intel/perfmon/pull/66 Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230407001322.2776268-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/x86/tigerlake/uncore-memory.json | 50 ++++++++++++++++++++++ .../arch/x86/tigerlake/uncore-other.json | 36 ---------------- 2 files changed, 50 insertions(+), 36 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/tigerlake/uncore-memory.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-memory.json b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-memory.json new file mode 100644 index 000000000000..99fb5259fd25 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-memory.json @@ -0,0 +1,50 @@ +[ + { + "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.", + "EventCode": "0xff", + "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "imc_free_running_0" + }, + { + "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", + "EventCode": "0xff", + "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "imc_free_running_0" + }, + { + "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.", + "EventCode": "0xff", + "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", + "PerPkg": "1", + "UMask": "0x30", + "Unit": "imc_free_running_0" + }, + { + "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.", + "EventCode": "0xff", + "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "imc_free_running_1" + }, + { + "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", + "EventCode": "0xff", + "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "imc_free_running_1" + }, + { + "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.", + "EventCode": "0xff", + "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", + "PerPkg": "1", + "UMask": "0x30", + "Unit": "imc_free_running_1" + } +] diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json index a5a254327ae9..6e43aaf64e28 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json @@ -93,41 +93,5 @@ "EventName": "UNC_CLOCK.SOCKET", "PerPkg": "1", "Unit": "CLOCK" - }, - { - "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.", - "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", - "PerPkg": "1", - "Unit": "imc" - }, - { - "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", - "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN", - "PerPkg": "1", - "Unit": "imc" - }, - { - "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.", - "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", - "PerPkg": "1", - "Unit": "imc" - }, - { - "BriefDescription": "Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.", - "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", - "PerPkg": "1", - "Unit": "imc" - }, - { - "BriefDescription": "Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.", - "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN", - "PerPkg": "1", - "Unit": "imc" - }, - { - "BriefDescription": "Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.", - "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", - "PerPkg": "1", - "Unit": "imc" } ] -- cgit v1.2.3-58-ga151 From 0e6aa013bbc545f3ac04ba79c884466e47136d5d Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Tue, 4 Apr 2023 13:59:43 -0700 Subject: perf map: Rename map_ip() and unmap_ip() Add dso to match comment. This avoids a naming conflict with later added accessor functions for variables in struct map. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexey Bayduraev Cc: Andi Kleen Cc: Andrew Morton Cc: Andy Shevchenko Cc: Darren Hart Cc: Davidlohr Bueso Cc: Dmitriy Vyukov Cc: Eric Dumazet Cc: German Gomez Cc: Hao Luo Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Madhavan Srinivasan Cc: Mark Rutland Cc: Masami Hiramatsu Cc: Miaoqian Lin Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Riccardo Mancini Cc: Shunsuke Nakamura Cc: Song Liu Cc: Stephane Eranian Cc: Stephen Brennan Cc: Steven Rostedt (VMware) Cc: Thomas Gleixner Cc: Thomas Richter Cc: Yury Norov Link: https://lore.kernel.org/r/20230404205954.2245628-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-kmem.c | 2 +- tools/perf/builtin-script.c | 4 ++-- tools/perf/util/machine.c | 4 ++-- tools/perf/util/map.c | 8 ++++---- tools/perf/util/map.h | 4 ++-- tools/perf/util/symbol-elf.c | 4 ++-- 6 files changed, 13 insertions(+), 13 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-kmem.c b/tools/perf/builtin-kmem.c index f3029742b800..4d4b770a401c 100644 --- a/tools/perf/builtin-kmem.c +++ b/tools/perf/builtin-kmem.c @@ -423,7 +423,7 @@ static u64 find_callsite(struct evsel *evsel, struct perf_sample *sample) if (!caller) { /* found */ if (node->ms.map) - addr = map__unmap_ip(node->ms.map, node->ip); + addr = map__dso_unmap_ip(node->ms.map, node->ip); else addr = node->ip; diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index 1d078106abc4..af0a69c7f41f 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -1012,11 +1012,11 @@ static int perf_sample__fprintf_brstackoff(struct perf_sample *sample, if (thread__find_map_fb(thread, sample->cpumode, from, &alf) && !map__dso(alf.map)->adjust_symbols) - from = map__map_ip(alf.map, from); + from = map__dso_map_ip(alf.map, from); if (thread__find_map_fb(thread, sample->cpumode, to, &alt) && !map__dso(alt.map)->adjust_symbols) - to = map__map_ip(alt.map, to); + to = map__dso_map_ip(alt.map, to); printed += fprintf(fp, " 0x%"PRIx64, from); if (PRINT_FIELD(DSO)) { diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c index 7852b97da10a..9d24980a0a93 100644 --- a/tools/perf/util/machine.c +++ b/tools/perf/util/machine.c @@ -3058,7 +3058,7 @@ static int append_inlines(struct callchain_cursor *cursor, struct map_symbol *ms if (!symbol_conf.inline_name || !map || !sym) return ret; - addr = map__map_ip(map, ip); + addr = map__dso_map_ip(map, ip); addr = map__rip_2objdump(map, addr); dso = map__dso(map); @@ -3103,7 +3103,7 @@ static int unwind_entry(struct unwind_entry *entry, void *arg) * its corresponding binary. */ if (entry->ms.map) - addr = map__map_ip(entry->ms.map, entry->ip); + addr = map__dso_map_ip(entry->ms.map, entry->ip); srcline = callchain_srcline(&entry->ms, addr); return callchain_cursor_append(cursor, entry->ip, &entry->ms, diff --git a/tools/perf/util/map.c b/tools/perf/util/map.c index 416fc449bde8..d97a6d20626f 100644 --- a/tools/perf/util/map.c +++ b/tools/perf/util/map.c @@ -109,8 +109,8 @@ void map__init(struct map *map, u64 start, u64 end, u64 pgoff, struct dso *dso) map->pgoff = pgoff; map->reloc = 0; map->dso = dso__get(dso); - map->map_ip = map__map_ip; - map->unmap_ip = map__unmap_ip; + map->map_ip = map__dso_map_ip; + map->unmap_ip = map__dso_unmap_ip; map->erange_warned = false; refcount_set(&map->refcnt, 1); } @@ -590,12 +590,12 @@ struct maps *map__kmaps(struct map *map) return kmap->kmaps; } -u64 map__map_ip(const struct map *map, u64 ip) +u64 map__dso_map_ip(const struct map *map, u64 ip) { return ip - map__start(map) + map->pgoff; } -u64 map__unmap_ip(const struct map *map, u64 ip) +u64 map__dso_unmap_ip(const struct map *map, u64 ip) { return ip + map__start(map) - map->pgoff; } diff --git a/tools/perf/util/map.h b/tools/perf/util/map.h index 16646b94fa3a..9b0a84e46e48 100644 --- a/tools/perf/util/map.h +++ b/tools/perf/util/map.h @@ -41,9 +41,9 @@ struct kmap *map__kmap(struct map *map); struct maps *map__kmaps(struct map *map); /* ip -> dso rip */ -u64 map__map_ip(const struct map *map, u64 ip); +u64 map__dso_map_ip(const struct map *map, u64 ip); /* dso rip -> ip */ -u64 map__unmap_ip(const struct map *map, u64 ip); +u64 map__dso_unmap_ip(const struct map *map, u64 ip); /* Returns ip */ u64 identity__map_ip(const struct map *map __maybe_unused, u64 ip); diff --git a/tools/perf/util/symbol-elf.c b/tools/perf/util/symbol-elf.c index e715869eab8a..c55981116f68 100644 --- a/tools/perf/util/symbol-elf.c +++ b/tools/perf/util/symbol-elf.c @@ -1357,8 +1357,8 @@ static int dso__process_kernel_symbol(struct dso *dso, struct map *map, map->start = shdr->sh_addr + ref_reloc(kmap); map->end = map__start(map) + shdr->sh_size; map->pgoff = shdr->sh_offset; - map->map_ip = map__map_ip; - map->unmap_ip = map__unmap_ip; + map->map_ip = map__dso_map_ip; + map->unmap_ip = map__dso_unmap_ip; /* Ensure maps are correctly ordered */ if (kmaps) { int err; -- cgit v1.2.3-58-ga151 From 78a1f7cd9000d5d633268a2acb2d9b62d41a2f2c Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Tue, 4 Apr 2023 13:59:44 -0700 Subject: perf map: Add helper for ->map_ip() and ->unmap_ip() Later changes will add reference count checking for struct map, add a helper function to invoke the map_ip and unmap_ip function pointers. The helper allows the reference count check to be in fewer places. Committer notes: Add missing conversions to: tools/perf/util/map.c tools/perf/util/cs-etm.c tools/perf/util/annotate.c tools/perf/arch/powerpc/util/sym-handling.c tools/perf/arch/s390/annotate/instructions.c Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexey Bayduraev Cc: Andi Kleen Cc: Andrew Morton Cc: Andy Shevchenko Cc: Darren Hart Cc: Davidlohr Bueso Cc: Dmitriy Vyukov Cc: Eric Dumazet Cc: German Gomez Cc: Hao Luo Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Madhavan Srinivasan Cc: Mark Rutland Cc: Masami Hiramatsu Cc: Miaoqian Lin Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Riccardo Mancini Cc: Shunsuke Nakamura Cc: Song Liu Cc: Stephane Eranian Cc: Stephen Brennan Cc: Steven Rostedt (VMware) Cc: Thomas Gleixner Cc: Thomas Richter Cc: Yury Norov Link: https://lore.kernel.org/r/20230404205954.2245628-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/powerpc/util/sym-handling.c | 2 +- tools/perf/arch/s390/annotate/instructions.c | 2 +- tools/perf/builtin-kallsyms.c | 2 +- tools/perf/builtin-kmem.c | 2 +- tools/perf/builtin-lock.c | 4 ++-- tools/perf/builtin-script.c | 2 +- tools/perf/tests/vmlinux-kallsyms.c | 10 +++++----- tools/perf/util/annotate.c | 14 +++++++------- tools/perf/util/bpf_lock_contention.c | 4 ++-- tools/perf/util/cs-etm.c | 2 +- tools/perf/util/dlfilter.c | 2 +- tools/perf/util/dso.c | 6 ++++-- tools/perf/util/event.c | 8 ++++---- tools/perf/util/evsel_fprintf.c | 2 +- tools/perf/util/intel-pt.c | 10 +++++----- tools/perf/util/machine.c | 16 ++++++++-------- tools/perf/util/map.c | 12 ++++++------ tools/perf/util/map.h | 10 ++++++++++ tools/perf/util/maps.c | 8 ++++---- tools/perf/util/probe-event.c | 8 ++++---- tools/perf/util/scripting-engines/trace-event-python.c | 2 +- tools/perf/util/sort.c | 12 ++++++------ tools/perf/util/symbol.c | 4 ++-- tools/perf/util/thread.c | 2 +- tools/perf/util/unwind-libdw.c | 2 +- tools/perf/util/unwind-libunwind-local.c | 2 +- 26 files changed, 81 insertions(+), 69 deletions(-) (limited to 'tools') diff --git a/tools/perf/arch/powerpc/util/sym-handling.c b/tools/perf/arch/powerpc/util/sym-handling.c index 9f99fc88dbff..947bfad7aa59 100644 --- a/tools/perf/arch/powerpc/util/sym-handling.c +++ b/tools/perf/arch/powerpc/util/sym-handling.c @@ -131,7 +131,7 @@ void arch__post_process_probe_trace_events(struct perf_probe_event *pev, for (i = 0; i < ntevs; i++) { tev = &pev->tevs[i]; map__for_each_symbol(map, sym, tmp) { - if (map->unmap_ip(map, sym->start) == tev->point.address) { + if (map__unmap_ip(map, sym->start) == tev->point.address) { arch__fix_tev_from_maps(pev, tev, map, sym); break; } diff --git a/tools/perf/arch/s390/annotate/instructions.c b/tools/perf/arch/s390/annotate/instructions.c index 0e136630659e..de925b0e35ce 100644 --- a/tools/perf/arch/s390/annotate/instructions.c +++ b/tools/perf/arch/s390/annotate/instructions.c @@ -39,7 +39,7 @@ static int s390_call__parse(struct arch *arch, struct ins_operands *ops, target.addr = map__objdump_2mem(map, ops->target.addr); if (maps__find_ams(ms->maps, &target) == 0 && - map__rip_2objdump(target.ms.map, map->map_ip(target.ms.map, target.addr)) == ops->target.addr) + map__rip_2objdump(target.ms.map, map__map_ip(target.ms.map, target.addr)) == ops->target.addr) ops->target.sym = target.ms.sym; return 0; diff --git a/tools/perf/builtin-kallsyms.c b/tools/perf/builtin-kallsyms.c index 5638ca4dbd8e..3751df744577 100644 --- a/tools/perf/builtin-kallsyms.c +++ b/tools/perf/builtin-kallsyms.c @@ -39,7 +39,7 @@ static int __cmd_kallsyms(int argc, const char **argv) dso = map__dso(map); printf("%s: %s %s %#" PRIx64 "-%#" PRIx64 " (%#" PRIx64 "-%#" PRIx64")\n", symbol->name, dso->short_name, dso->long_name, - map->unmap_ip(map, symbol->start), map->unmap_ip(map, symbol->end), + map__unmap_ip(map, symbol->start), map__unmap_ip(map, symbol->end), symbol->start, symbol->end); } diff --git a/tools/perf/builtin-kmem.c b/tools/perf/builtin-kmem.c index 4d4b770a401c..fcd2ef3bd3f5 100644 --- a/tools/perf/builtin-kmem.c +++ b/tools/perf/builtin-kmem.c @@ -1024,7 +1024,7 @@ static void __print_slab_result(struct rb_root *root, if (sym != NULL) snprintf(buf, sizeof(buf), "%s+%" PRIx64 "", sym->name, - addr - map->unmap_ip(map, sym->start)); + addr - map__unmap_ip(map, sym->start)); else snprintf(buf, sizeof(buf), "%#" PRIx64 "", addr); printf(" %-34s |", buf); diff --git a/tools/perf/builtin-lock.c b/tools/perf/builtin-lock.c index 4e24351b18bd..ecb1fac8ba3c 100644 --- a/tools/perf/builtin-lock.c +++ b/tools/perf/builtin-lock.c @@ -900,7 +900,7 @@ static int get_symbol_name_offset(struct map *map, struct symbol *sym, u64 ip, return 0; } - offset = map->map_ip(map, ip) - sym->start; + offset = map__map_ip(map, ip) - sym->start; if (offset) return scnprintf(buf, size, "%s+%#lx", sym->name, offset); @@ -1070,7 +1070,7 @@ static int report_lock_contention_begin_event(struct evsel *evsel, return -ENOMEM; } - addrs[filters.nr_addrs++] = kmap->unmap_ip(kmap, sym->start); + addrs[filters.nr_addrs++] = map__unmap_ip(kmap, sym->start); filters.addrs = addrs; } } diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index af0a69c7f41f..8fba247b798c 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -1088,7 +1088,7 @@ static int grab_bb(u8 *buffer, u64 start, u64 end, /* Load maps to ensure dso->is_64_bit has been updated */ map__load(al.map); - offset = al.map->map_ip(al.map, start); + offset = map__map_ip(al.map, start); len = dso__data_read_offset(dso, machine, offset, (u8 *)buffer, end - start + MAXINSN); diff --git a/tools/perf/tests/vmlinux-kallsyms.c b/tools/perf/tests/vmlinux-kallsyms.c index 0a75623172c2..05a322ea3f9f 100644 --- a/tools/perf/tests/vmlinux-kallsyms.c +++ b/tools/perf/tests/vmlinux-kallsyms.c @@ -13,7 +13,7 @@ #include "debug.h" #include "machine.h" -#define UM(x) kallsyms_map->unmap_ip(kallsyms_map, (x)) +#define UM(x) map__unmap_ip(kallsyms_map, (x)) static bool is_ignored_symbol(const char *name, char type) { @@ -221,8 +221,8 @@ static int test__vmlinux_matches_kallsyms(struct test_suite *test __maybe_unused if (sym->start == sym->end) continue; - mem_start = vmlinux_map->unmap_ip(vmlinux_map, sym->start); - mem_end = vmlinux_map->unmap_ip(vmlinux_map, sym->end); + mem_start = map__unmap_ip(vmlinux_map, sym->start); + mem_end = map__unmap_ip(vmlinux_map, sym->end); first_pair = machine__find_kernel_symbol(&kallsyms, mem_start, NULL); pair = first_pair; @@ -319,8 +319,8 @@ next_pair: maps__for_each_entry(maps, rb_node) { struct map *pair, *map = rb_node->map; - mem_start = vmlinux_map->unmap_ip(vmlinux_map, map__start(map)); - mem_end = vmlinux_map->unmap_ip(vmlinux_map, map__end(map)); + mem_start = map__unmap_ip(vmlinux_map, map__start(map)); + mem_end = map__unmap_ip(vmlinux_map, map__end(map)); pair = maps__find(kallsyms.kmaps, mem_start); if (pair == NULL || pair->priv) diff --git a/tools/perf/util/annotate.c b/tools/perf/util/annotate.c index b9cff782d7df..55f2e3a7577e 100644 --- a/tools/perf/util/annotate.c +++ b/tools/perf/util/annotate.c @@ -272,7 +272,7 @@ find_target: target.addr = map__objdump_2mem(map, ops->target.addr); if (maps__find_ams(ms->maps, &target) == 0 && - map__rip_2objdump(target.ms.map, map->map_ip(target.ms.map, target.addr)) == ops->target.addr) + map__rip_2objdump(target.ms.map, map__map_ip(target.ms.map, target.addr)) == ops->target.addr) ops->target.sym = target.ms.sym; return 0; @@ -376,8 +376,8 @@ static int jump__parse(struct arch *arch, struct ins_operands *ops, struct map_s } target.addr = map__objdump_2mem(map, ops->target.addr); - start = map->unmap_ip(map, sym->start), - end = map->unmap_ip(map, sym->end); + start = map__unmap_ip(map, sym->start); + end = map__unmap_ip(map, sym->end); ops->target.outside = target.addr < start || target.addr > end; @@ -400,7 +400,7 @@ static int jump__parse(struct arch *arch, struct ins_operands *ops, struct map_s * the symbol searching and disassembly should be done. */ if (maps__find_ams(ms->maps, &target) == 0 && - map__rip_2objdump(target.ms.map, map->map_ip(target.ms.map, target.addr)) == ops->target.addr) + map__rip_2objdump(target.ms.map, map__map_ip(target.ms.map, target.addr)) == ops->target.addr) ops->target.sym = target.ms.sym; if (!ops->target.outside) { @@ -881,7 +881,7 @@ static int __symbol__inc_addr_samples(struct map_symbol *ms, unsigned offset; struct sym_hist *h; - pr_debug3("%s: addr=%#" PRIx64 "\n", __func__, ms->map->unmap_ip(ms->map, addr)); + pr_debug3("%s: addr=%#" PRIx64 "\n", __func__, map__unmap_ip(ms->map, addr)); if ((addr < sym->start || addr >= sym->end) && (addr != sym->end || sym->start != sym->end)) { @@ -1977,8 +1977,8 @@ static int symbol__disassemble(struct symbol *sym, struct annotate_args *args) return err; pr_debug("%s: filename=%s, sym=%s, start=%#" PRIx64 ", end=%#" PRIx64 "\n", __func__, - symfs_filename, sym->name, map->unmap_ip(map, sym->start), - map->unmap_ip(map, sym->end)); + symfs_filename, sym->name, map__unmap_ip(map, sym->start), + map__unmap_ip(map, sym->end)); pr_debug("annotating [%p] %30s : [%p] %30s\n", dso, dso->long_name, sym, sym->name); diff --git a/tools/perf/util/bpf_lock_contention.c b/tools/perf/util/bpf_lock_contention.c index 9e20fa8ade09..e7dddf0127bc 100644 --- a/tools/perf/util/bpf_lock_contention.c +++ b/tools/perf/util/bpf_lock_contention.c @@ -74,7 +74,7 @@ int lock_contention_prepare(struct lock_contention *con) continue; } - addrs[con->filters->nr_addrs++] = kmap->unmap_ip(kmap, sym->start); + addrs[con->filters->nr_addrs++] = map__unmap_ip(kmap, sym->start); con->filters->addrs = addrs; } naddrs = con->filters->nr_addrs; @@ -233,7 +233,7 @@ static const char *lock_contention_get_name(struct lock_contention *con, if (sym) { unsigned long offset; - offset = kmap->map_ip(kmap, addr) - sym->start; + offset = map__map_ip(kmap, addr) - sym->start; if (offset == 0) return sym->name; diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 528a7fb066cf..944835e16430 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -893,7 +893,7 @@ static u32 cs_etm__mem_access(struct cs_etm_queue *etmq, u8 trace_chan_id, dso__data_status_seen(dso, DSO_DATA_STATUS_SEEN_ITRACE)) return 0; - offset = al.map->map_ip(al.map, address); + offset = map__map_ip(al.map, address); map__load(al.map); diff --git a/tools/perf/util/dlfilter.c b/tools/perf/util/dlfilter.c index fe401fa4be02..16238f823a5e 100644 --- a/tools/perf/util/dlfilter.c +++ b/tools/perf/util/dlfilter.c @@ -278,7 +278,7 @@ static __s32 dlfilter__object_code(void *ctx, __u64 ip, void *buf, __u32 len) map = a.map; have_map: - offset = map->map_ip(map, ip); + offset = map__map_ip(map, ip); if (ip + len >= map__end(map)) len = map__end(map) - ip; return dso__data_read_offset(map__dso(map), d->machine, offset, buf, len); diff --git a/tools/perf/util/dso.c b/tools/perf/util/dso.c index f1a14c0ad26d..e36b418df2c6 100644 --- a/tools/perf/util/dso.c +++ b/tools/perf/util/dso.c @@ -1122,7 +1122,8 @@ ssize_t dso__data_read_addr(struct dso *dso, struct map *map, struct machine *machine, u64 addr, u8 *data, ssize_t size) { - u64 offset = map->map_ip(map, addr); + u64 offset = map__map_ip(map, addr); + return dso__data_read_offset(dso, machine, offset, data, size); } @@ -1162,7 +1163,8 @@ ssize_t dso__data_write_cache_addr(struct dso *dso, struct map *map, struct machine *machine, u64 addr, const u8 *data, ssize_t size) { - u64 offset = map->map_ip(map, addr); + u64 offset = map__map_ip(map, addr); + return dso__data_write_cache_offs(dso, machine, offset, data, size); } diff --git a/tools/perf/util/event.c b/tools/perf/util/event.c index 2ddc75dee019..2712d1a8264e 100644 --- a/tools/perf/util/event.c +++ b/tools/perf/util/event.c @@ -487,7 +487,7 @@ size_t perf_event__fprintf_text_poke(union perf_event *event, struct machine *ma al.map = maps__find(machine__kernel_maps(machine), tp->addr); if (al.map && map__load(al.map) >= 0) { - al.addr = al.map->map_ip(al.map, tp->addr); + al.addr = map__map_ip(al.map, tp->addr); al.sym = map__find_symbol(al.map, al.addr); if (al.sym) ret += symbol__fprintf_symname_offs(al.sym, &al, fp); @@ -622,7 +622,7 @@ struct map *thread__find_map(struct thread *thread, u8 cpumode, u64 addr, */ if (load_map) map__load(al->map); - al->addr = al->map->map_ip(al->map, al->addr); + al->addr = map__map_ip(al->map, al->addr); } return al->map; @@ -743,12 +743,12 @@ int machine__resolve(struct machine *machine, struct addr_location *al, } if (!ret && al->sym) { snprintf(al_addr_str, sz, "0x%"PRIx64, - al->map->unmap_ip(al->map, al->sym->start)); + map__unmap_ip(al->map, al->sym->start)); ret = strlist__has_entry(symbol_conf.sym_list, al_addr_str); } if (!ret && symbol_conf.addr_list && al->map) { - unsigned long addr = al->map->unmap_ip(al->map, al->addr); + unsigned long addr = map__unmap_ip(al->map, al->addr); ret = intlist__has_entry(symbol_conf.addr_list, addr); if (!ret && symbol_conf.addr_range) { diff --git a/tools/perf/util/evsel_fprintf.c b/tools/perf/util/evsel_fprintf.c index dff5d8c4b06d..a09ac00810b7 100644 --- a/tools/perf/util/evsel_fprintf.c +++ b/tools/perf/util/evsel_fprintf.c @@ -151,7 +151,7 @@ int sample__fprintf_callchain(struct perf_sample *sample, int left_alignment, printed += fprintf(fp, " <-"); if (map) - addr = map->map_ip(map, node->ip); + addr = map__map_ip(map, node->ip); if (print_ip) { /* Show binary offset for userspace addr */ diff --git a/tools/perf/util/intel-pt.c b/tools/perf/util/intel-pt.c index a2e62daa708e..fe893c9bab3f 100644 --- a/tools/perf/util/intel-pt.c +++ b/tools/perf/util/intel-pt.c @@ -816,7 +816,7 @@ static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn, dso__data_status_seen(dso, DSO_DATA_STATUS_SEEN_ITRACE)) return -ENOENT; - offset = al.map->map_ip(al.map, *ip); + offset = map__map_ip(al.map, *ip); if (!to_ip && one_map) { struct intel_pt_cache_entry *e; @@ -987,7 +987,7 @@ static int __intel_pt_pgd_ip(uint64_t ip, void *data) if (!thread__find_map(thread, cpumode, ip, &al) || !map__dso(al.map)) return -EINVAL; - offset = al.map->map_ip(al.map, ip); + offset = map__map_ip(al.map, ip); return intel_pt_match_pgd_ip(ptq->pt, ip, offset, map__dso(al.map)->long_name); } @@ -2749,7 +2749,7 @@ static u64 intel_pt_switch_ip(struct intel_pt *pt, u64 *ptss_ip) for (sym = start; sym; sym = dso__next_symbol(sym)) { if (sym->binding == STB_GLOBAL && !strcmp(sym->name, "__switch_to")) { - ip = map->unmap_ip(map, sym->start); + ip = map__unmap_ip(map, sym->start); if (ip >= map__start(map) && ip < map__end(map)) { switch_ip = ip; break; @@ -2767,7 +2767,7 @@ static u64 intel_pt_switch_ip(struct intel_pt *pt, u64 *ptss_ip) for (sym = start; sym; sym = dso__next_symbol(sym)) { if (!strcmp(sym->name, ptss)) { - ip = map->unmap_ip(map, sym->start); + ip = map__unmap_ip(map, sym->start); if (ip >= map__start(map) && ip < map__end(map)) { *ptss_ip = ip; break; @@ -3393,7 +3393,7 @@ static int intel_pt_text_poke(struct intel_pt *pt, union perf_event *event) if (!dso || !dso->auxtrace_cache) continue; - offset = al.map->map_ip(al.map, addr); + offset = map__map_ip(al.map, addr); e = intel_pt_cache_lookup(dso, machine, offset); if (!e) diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c index 9d24980a0a93..d29ec4a04488 100644 --- a/tools/perf/util/machine.c +++ b/tools/perf/util/machine.c @@ -919,7 +919,7 @@ static int machine__process_ksymbol_register(struct machine *machine, dso = map__dso(map); } - sym = symbol__new(map->map_ip(map, map__start(map)), + sym = symbol__new(map__map_ip(map, map__start(map)), event->ksymbol.len, 0, 0, event->ksymbol.name); if (!sym) @@ -944,7 +944,7 @@ static int machine__process_ksymbol_unregister(struct machine *machine, else { struct dso *dso = map__dso(map); - sym = dso__find_symbol(dso, map->map_ip(map, map__start(map))); + sym = dso__find_symbol(dso, map__map_ip(map, map__start(map))); if (sym) dso__delete_symbol(dso, sym); } @@ -1279,7 +1279,7 @@ int machine__map_x86_64_entry_trampolines(struct machine *machine, dest_map = maps__find(kmaps, map->pgoff); if (dest_map != map) - map->pgoff = dest_map->map_ip(dest_map, map->pgoff); + map->pgoff = map__map_ip(dest_map, map->pgoff); found = true; } if (found || machine->trampolines_mapped) @@ -3345,7 +3345,7 @@ char *machine__resolve_kernel_addr(void *vmachine, unsigned long long *addrp, ch return NULL; *modp = __map__is_kmodule(map) ? (char *)map__dso(map)->short_name : NULL; - *addrp = map->unmap_ip(map, sym->start); + *addrp = map__unmap_ip(map, sym->start); return sym->name; } @@ -3388,17 +3388,17 @@ bool machine__is_lock_function(struct machine *machine, u64 addr) return false; } - machine->sched.text_start = kmap->unmap_ip(kmap, sym->start); + machine->sched.text_start = map__unmap_ip(kmap, sym->start); /* should not fail from here */ sym = machine__find_kernel_symbol_by_name(machine, "__sched_text_end", &kmap); - machine->sched.text_end = kmap->unmap_ip(kmap, sym->start); + machine->sched.text_end = map__unmap_ip(kmap, sym->start); sym = machine__find_kernel_symbol_by_name(machine, "__lock_text_start", &kmap); - machine->lock.text_start = kmap->unmap_ip(kmap, sym->start); + machine->lock.text_start = map__unmap_ip(kmap, sym->start); sym = machine__find_kernel_symbol_by_name(machine, "__lock_text_end", &kmap); - machine->lock.text_end = kmap->unmap_ip(kmap, sym->start); + machine->lock.text_end = map__unmap_ip(kmap, sym->start); } /* failed to get kernel symbols */ diff --git a/tools/perf/util/map.c b/tools/perf/util/map.c index d97a6d20626f..a55aef4b1310 100644 --- a/tools/perf/util/map.c +++ b/tools/perf/util/map.c @@ -519,7 +519,7 @@ u64 map__rip_2objdump(struct map *map, u64 rip) if (dso->kernel == DSO_SPACE__USER) return rip + dso->text_offset; - return map->unmap_ip(map, rip) - map->reloc; + return map__unmap_ip(map, rip) - map->reloc; } /** @@ -530,7 +530,7 @@ u64 map__rip_2objdump(struct map *map, u64 rip) * Closely related to map__rip_2objdump(), this function takes an address from * objdump and converts it to a memory address. Note this assumes that @map * contains the address. To be sure the result is valid, check it forwards - * e.g. map__rip_2objdump(map->map_ip(map, map__objdump_2mem(map, ip))) == ip + * e.g. map__rip_2objdump(map__map_ip(map, map__objdump_2mem(map, ip))) == ip * * Return: Memory address. */ @@ -539,24 +539,24 @@ u64 map__objdump_2mem(struct map *map, u64 ip) const struct dso *dso = map__dso(map); if (!dso->adjust_symbols) - return map->unmap_ip(map, ip); + return map__unmap_ip(map, ip); if (dso->rel) - return map->unmap_ip(map, ip + map->pgoff); + return map__unmap_ip(map, ip + map->pgoff); /* * kernel modules also have DSO_TYPE_USER in dso->kernel, * but all kernel modules are ET_REL, so won't get here. */ if (dso->kernel == DSO_SPACE__USER) - return map->unmap_ip(map, ip - dso->text_offset); + return map__unmap_ip(map, ip - dso->text_offset); return ip + map->reloc; } bool map__contains_symbol(const struct map *map, const struct symbol *sym) { - u64 ip = map->unmap_ip(map, sym->start); + u64 ip = map__unmap_ip(map, sym->start); return ip >= map__start(map) && ip < map__end(map); } diff --git a/tools/perf/util/map.h b/tools/perf/util/map.h index 9b0a84e46e48..9118eba71032 100644 --- a/tools/perf/util/map.h +++ b/tools/perf/util/map.h @@ -52,6 +52,16 @@ static inline struct dso *map__dso(const struct map *map) return map->dso; } +static inline u64 map__map_ip(const struct map *map, u64 ip) +{ + return map->map_ip(map, ip); +} + +static inline u64 map__unmap_ip(const struct map *map, u64 ip) +{ + return map->unmap_ip(map, ip); +} + static inline u64 map__start(const struct map *map) { return map->start; diff --git a/tools/perf/util/maps.c b/tools/perf/util/maps.c index 21010a2b8e16..0eee27e24c33 100644 --- a/tools/perf/util/maps.c +++ b/tools/perf/util/maps.c @@ -194,7 +194,7 @@ struct symbol *maps__find_symbol(struct maps *maps, u64 addr, struct map **mapp) if (map != NULL && map__load(map) >= 0) { if (mapp != NULL) *mapp = map; - return map__find_symbol(map, map->map_ip(map, addr)); + return map__find_symbol(map, map__map_ip(map, addr)); } return NULL; @@ -237,7 +237,7 @@ int maps__find_ams(struct maps *maps, struct addr_map_symbol *ams) return -1; } - ams->al_addr = ams->ms.map->map_ip(ams->ms.map, ams->addr); + ams->al_addr = map__map_ip(ams->ms.map, ams->addr); ams->ms.sym = map__find_symbol(ams->ms.map, ams->al_addr); return ams->ms.sym ? 0 : -1; @@ -349,8 +349,8 @@ int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp) after->start = map__end(map); after->pgoff += map__end(map) - map__start(pos->map); - assert(pos->map->map_ip(pos->map, map__end(map)) == - after->map_ip(after, map__end(map))); + assert(map__map_ip(pos->map, map__end(map)) == + map__map_ip(after, map__end(map))); err = __maps__insert(maps, after); if (err) goto put_map; diff --git a/tools/perf/util/probe-event.c b/tools/perf/util/probe-event.c index 4d9dbeeb6014..bb44a3798df8 100644 --- a/tools/perf/util/probe-event.c +++ b/tools/perf/util/probe-event.c @@ -141,7 +141,7 @@ static int kernel_get_symbol_address_by_name(const char *name, u64 *addr, sym = machine__find_kernel_symbol_by_name(host_machine, name, &map); if (!sym) return -ENOENT; - *addr = map->unmap_ip(map, sym->start) - + *addr = map__unmap_ip(map, sym->start) - ((reloc) ? 0 : map->reloc) - ((reladdr) ? map__start(map) : 0); } @@ -400,7 +400,7 @@ static int find_alternative_probe_point(struct debuginfo *dinfo, "Consider identifying the final function used at run time and set the probe directly on that.\n", pp->function); } else - address = map->unmap_ip(map, sym->start) - map->reloc; + address = map__unmap_ip(map, sym->start) - map->reloc; break; } if (!address) { @@ -2249,7 +2249,7 @@ static int find_perf_probe_point_from_map(struct probe_trace_point *tp, goto out; pp->retprobe = tp->retprobe; - pp->offset = addr - map->unmap_ip(map, sym->start); + pp->offset = addr - map__unmap_ip(map, sym->start); pp->function = strdup(sym->name); ret = pp->function ? 0 : -ENOMEM; @@ -3123,7 +3123,7 @@ static int find_probe_trace_events_from_map(struct perf_probe_event *pev, goto err_out; } /* Add one probe point */ - tp->address = map->unmap_ip(map, sym->start) + pp->offset; + tp->address = map__unmap_ip(map, sym->start) + pp->offset; /* Check the kprobe (not in module) is within .text */ if (!pev->uprobes && !pev->target && diff --git a/tools/perf/util/scripting-engines/trace-event-python.c b/tools/perf/util/scripting-engines/trace-event-python.c index cbf09eaf3734..41d4f9e6a8b7 100644 --- a/tools/perf/util/scripting-engines/trace-event-python.c +++ b/tools/perf/util/scripting-engines/trace-event-python.c @@ -471,7 +471,7 @@ static PyObject *python_process_callchain(struct perf_sample *sample, struct addr_location node_al; unsigned long offset; - node_al.addr = map->map_ip(map, node->ip); + node_al.addr = map__map_ip(map, node->ip); node_al.map = map; offset = get_offset(node->ms.sym, &node_al); diff --git a/tools/perf/util/sort.c b/tools/perf/util/sort.c index f161589aefda..87a3ba584af5 100644 --- a/tools/perf/util/sort.c +++ b/tools/perf/util/sort.c @@ -364,7 +364,7 @@ static int _hist_entry__sym_snprintf(struct map_symbol *ms, u64 rip = ip; if (dso && dso->kernel && dso->adjust_symbols) - rip = map->unmap_ip(map, ip); + rip = map__unmap_ip(map, ip); ret += repsep_snprintf(bf, size, "%-#*llx %c ", BITS_PER_LONG / 4 + 2, rip, o); @@ -375,7 +375,7 @@ static int _hist_entry__sym_snprintf(struct map_symbol *ms, if (sym->type == STT_OBJECT) { ret += repsep_snprintf(bf + ret, size - ret, "%s", sym->name); ret += repsep_snprintf(bf + ret, size - ret, "+0x%llx", - ip - map->unmap_ip(map, sym->start)); + ip - map__unmap_ip(map, sym->start)); } else { ret += repsep_snprintf(bf + ret, size - ret, "%.*s", width - ret, @@ -1147,7 +1147,7 @@ static int _hist_entry__addr_snprintf(struct map_symbol *ms, if (sym->type == STT_OBJECT) { ret += repsep_snprintf(bf + ret, size - ret, "%s", sym->name); ret += repsep_snprintf(bf + ret, size - ret, "+0x%llx", - ip - map->unmap_ip(map, sym->start)); + ip - map__unmap_ip(map, sym->start)); } else { ret += repsep_snprintf(bf + ret, size - ret, "%.*s", width - ret, @@ -2104,9 +2104,9 @@ sort__addr_cmp(struct hist_entry *left, struct hist_entry *right) struct map *right_map = right->ms.map; if (left_map) - left_ip = left_map->unmap_ip(left_map, left_ip); + left_ip = map__unmap_ip(left_map, left_ip); if (right_map) - right_ip = right_map->unmap_ip(right_map, right_ip); + right_ip = map__unmap_ip(right_map, right_ip); return _sort__addr_cmp(left_ip, right_ip); } @@ -2118,7 +2118,7 @@ static int hist_entry__addr_snprintf(struct hist_entry *he, char *bf, struct map *map = he->ms.map; if (map) - ip = map->unmap_ip(map, ip); + ip = map__unmap_ip(map, ip); return repsep_snprintf(bf, size, "%-#*llx", width, ip); } diff --git a/tools/perf/util/symbol.c b/tools/perf/util/symbol.c index b91deb177091..9ba49c1ef6ef 100644 --- a/tools/perf/util/symbol.c +++ b/tools/perf/util/symbol.c @@ -896,8 +896,8 @@ static int maps__split_kallsyms(struct maps *kmaps, struct dso *dso, u64 delta, * So that we look just like we get from .ko files, * i.e. not prelinked, relative to initial_map->start. */ - pos->start = curr_map->map_ip(curr_map, pos->start); - pos->end = curr_map->map_ip(curr_map, pos->end); + pos->start = map__map_ip(curr_map, pos->start); + pos->end = map__map_ip(curr_map, pos->end); } else if (x86_64 && is_entry_trampoline(pos->name)) { /* * These symbols are not needed anymore since the diff --git a/tools/perf/util/thread.c b/tools/perf/util/thread.c index bb7a2ce82d46..4b5bdc277baa 100644 --- a/tools/perf/util/thread.c +++ b/tools/perf/util/thread.c @@ -464,7 +464,7 @@ int thread__memcpy(struct thread *thread, struct machine *machine, if( !dso || dso->data.status == DSO_DATA_STATUS_ERROR || map__load(al.map) < 0) return -1; - offset = al.map->map_ip(al.map, ip); + offset = map__map_ip(al.map, ip); if (is64bit) *is64bit = dso->is_64_bit; diff --git a/tools/perf/util/unwind-libdw.c b/tools/perf/util/unwind-libdw.c index b79f57e5648f..538320e4260c 100644 --- a/tools/perf/util/unwind-libdw.c +++ b/tools/perf/util/unwind-libdw.c @@ -115,7 +115,7 @@ static int entry(u64 ip, struct unwind_info *ui) pr_debug("unwind: %s:ip = 0x%" PRIx64 " (0x%" PRIx64 ")\n", al.sym ? al.sym->name : "''", ip, - al.map ? al.map->map_ip(al.map, ip) : (u64) 0); + al.map ? map__map_ip(al.map, ip) : (u64) 0); return 0; } diff --git a/tools/perf/util/unwind-libunwind-local.c b/tools/perf/util/unwind-libunwind-local.c index 1c13f43e7d22..f9a52af48de4 100644 --- a/tools/perf/util/unwind-libunwind-local.c +++ b/tools/perf/util/unwind-libunwind-local.c @@ -640,7 +640,7 @@ static int entry(u64 ip, struct thread *thread, pr_debug("unwind: %s:ip = 0x%" PRIx64 " (0x%" PRIx64 ")\n", al.sym ? al.sym->name : "''", ip, - al.map ? al.map->map_ip(al.map, ip) : (u64) 0); + al.map ? map__map_ip(al.map, ip) : (u64) 0); return cb(&e, arg); } -- cgit v1.2.3-58-ga151 From ddee3f2bddc11f850f7f6fcfc04bc26ceeab23ce Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Tue, 4 Apr 2023 13:59:45 -0700 Subject: perf map: Add accessors for ->prot, ->priv and ->flags Later changes will add reference count checking for 'struct map'. Add an accessor so that the reference count check is only necessary in one place. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexey Bayduraev Cc: Andi Kleen Cc: Andrew Morton Cc: Andy Shevchenko Cc: Darren Hart Cc: Davidlohr Bueso Cc: Dmitriy Vyukov Cc: Eric Dumazet Cc: German Gomez Cc: Hao Luo Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Madhavan Srinivasan Cc: Mark Rutland Cc: Masami Hiramatsu Cc: Miaoqian Lin Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Riccardo Mancini Cc: Shunsuke Nakamura Cc: Song Liu Cc: Stephane Eranian Cc: Stephen Brennan Cc: Steven Rostedt (VMware) Cc: Thomas Gleixner Cc: Thomas Richter Cc: Yury Norov Link: https://lore.kernel.org/r/20230404205954.2245628-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-inject.c | 2 +- tools/perf/builtin-report.c | 9 +++++---- tools/perf/tests/vmlinux-kallsyms.c | 4 ++-- tools/perf/util/map.h | 15 +++++++++++++++ tools/perf/util/sort.c | 6 +++--- tools/perf/util/symbol.c | 4 ++-- 6 files changed, 28 insertions(+), 12 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-inject.c b/tools/perf/builtin-inject.c index 8f6909dd8a54..fd2b38458a5d 100644 --- a/tools/perf/builtin-inject.c +++ b/tools/perf/builtin-inject.c @@ -758,7 +758,7 @@ int perf_event__inject_buildid(struct perf_tool *tool, union perf_event *event, if (!dso->hit) { dso->hit = 1; dso__inject_build_id(dso, tool, machine, - sample->cpumode, al.map->flags); + sample->cpumode, map__flags(al.map)); } } diff --git a/tools/perf/builtin-report.c b/tools/perf/builtin-report.c index 2a6e2cee5e0d..c066452219c8 100644 --- a/tools/perf/builtin-report.c +++ b/tools/perf/builtin-report.c @@ -849,13 +849,14 @@ static size_t maps__fprintf_task(struct maps *maps, int indent, FILE *fp) maps__for_each_entry(maps, rb_node) { struct map *map = rb_node->map; const struct dso *dso = map__dso(map); + u32 prot = map__prot(map); printed += fprintf(fp, "%*s %" PRIx64 "-%" PRIx64 " %c%c%c%c %08" PRIx64 " %" PRIu64 " %s\n", indent, "", map__start(map), map__end(map), - map->prot & PROT_READ ? 'r' : '-', - map->prot & PROT_WRITE ? 'w' : '-', - map->prot & PROT_EXEC ? 'x' : '-', - map->flags & MAP_SHARED ? 's' : 'p', + prot & PROT_READ ? 'r' : '-', + prot & PROT_WRITE ? 'w' : '-', + prot & PROT_EXEC ? 'x' : '-', + map__flags(map) ? 's' : 'p', map->pgoff, dso->id.ino, dso->name); } diff --git a/tools/perf/tests/vmlinux-kallsyms.c b/tools/perf/tests/vmlinux-kallsyms.c index 05a322ea3f9f..7db102868bc2 100644 --- a/tools/perf/tests/vmlinux-kallsyms.c +++ b/tools/perf/tests/vmlinux-kallsyms.c @@ -323,7 +323,7 @@ next_pair: mem_end = map__unmap_ip(vmlinux_map, map__end(map)); pair = maps__find(kallsyms.kmaps, mem_start); - if (pair == NULL || pair->priv) + if (pair == NULL || map__priv(pair)) continue; if (map__start(pair) == mem_start) { @@ -351,7 +351,7 @@ next_pair: maps__for_each_entry(maps, rb_node) { struct map *map = rb_node->map; - if (!map->priv) { + if (!map__priv(map)) { if (!header_printed) { pr_info("WARN: Maps only in kallsyms:\n"); header_printed = true; diff --git a/tools/perf/util/map.h b/tools/perf/util/map.h index 9118eba71032..fd440c9c279e 100644 --- a/tools/perf/util/map.h +++ b/tools/perf/util/map.h @@ -72,6 +72,21 @@ static inline u64 map__end(const struct map *map) return map->end; } +static inline u32 map__flags(const struct map *map) +{ + return map->flags; +} + +static inline u32 map__prot(const struct map *map) +{ + return map->prot; +} + +static inline bool map__priv(const struct map *map) +{ + return map->priv; +} + static inline size_t map__size(const struct map *map) { return map__end(map) - map__start(map); diff --git a/tools/perf/util/sort.c b/tools/perf/util/sort.c index 87a3ba584af5..80c9960c37e5 100644 --- a/tools/perf/util/sort.c +++ b/tools/perf/util/sort.c @@ -1540,7 +1540,7 @@ sort__dcacheline_cmp(struct hist_entry *left, struct hist_entry *right) */ if ((left->cpumode != PERF_RECORD_MISC_KERNEL) && - (!(l_map->flags & MAP_SHARED)) && !l_dso->id.maj && !l_dso->id.min && + (!(map__flags(l_map) & MAP_SHARED)) && !l_dso->id.maj && !l_dso->id.min && !l_dso->id.ino && !l_dso->id.ino_generation) { /* userspace anonymous */ @@ -1576,8 +1576,8 @@ static int hist_entry__dcacheline_snprintf(struct hist_entry *he, char *bf, /* print [s] for shared data mmaps */ if ((he->cpumode != PERF_RECORD_MISC_KERNEL) && - map && !(map->prot & PROT_EXEC) && - (map->flags & MAP_SHARED) && + map && !(map__prot(map) & PROT_EXEC) && + (map__flags(map) & MAP_SHARED) && (dso->id.maj || dso->id.min || dso->id.ino || dso->id.ino_generation)) level = 's'; else if (!map) diff --git a/tools/perf/util/symbol.c b/tools/perf/util/symbol.c index 9ba49c1ef6ef..5c075d77a792 100644 --- a/tools/perf/util/symbol.c +++ b/tools/perf/util/symbol.c @@ -1396,7 +1396,7 @@ static int dso__load_kcore(struct dso *dso, struct map *map, } /* Read new maps into temporary lists */ - err = file__read_maps(fd, map->prot & PROT_EXEC, kcore_mapfn, &md, + err = file__read_maps(fd, map__prot(map) & PROT_EXEC, kcore_mapfn, &md, &is_64_bit); if (err) goto out_err; @@ -1509,7 +1509,7 @@ static int dso__load_kcore(struct dso *dso, struct map *map, close(fd); - if (map->prot & PROT_EXEC) + if (map__prot(map) & PROT_EXEC) pr_debug("Using %s for kernel object code\n", kcore_filename); else pr_debug("Using %s for kernel data\n", kcore_filename); -- cgit v1.2.3-58-ga151 From 2a6e5e8a2ab68c9048f80d174d1698427fbd9c8c Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Tue, 4 Apr 2023 13:59:46 -0700 Subject: perf map: Add accessors for ->pgoff and ->reloc Later changes will add reference count checking for 'struct map'. Add accessors so that the reference count check is only necessary in one place. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexey Bayduraev Cc: Andi Kleen Cc: Andrew Morton Cc: Andy Shevchenko Cc: Darren Hart Cc: Davidlohr Bueso Cc: Dmitriy Vyukov Cc: Eric Dumazet Cc: German Gomez Cc: Hao Luo Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Madhavan Srinivasan Cc: Mark Rutland Cc: Masami Hiramatsu Cc: Miaoqian Lin Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Riccardo Mancini Cc: Shunsuke Nakamura Cc: Song Liu Cc: Stephane Eranian Cc: Stephen Brennan Cc: Steven Rostedt (VMware) Cc: Thomas Gleixner Cc: Thomas Richter Cc: Yury Norov Link: https://lore.kernel.org/r/20230404205954.2245628-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/x86/util/event.c | 2 +- tools/perf/builtin-report.c | 2 +- tools/perf/tests/vmlinux-kallsyms.c | 4 ++-- tools/perf/util/machine.c | 4 ++-- tools/perf/util/map.c | 14 +++++++------- tools/perf/util/map.h | 10 ++++++++++ tools/perf/util/probe-event.c | 8 ++++---- tools/perf/util/symbol.c | 6 +++--- tools/perf/util/unwind-libdw.c | 6 +++--- 9 files changed, 33 insertions(+), 23 deletions(-) (limited to 'tools') diff --git a/tools/perf/arch/x86/util/event.c b/tools/perf/arch/x86/util/event.c index 3b2475707756..5741ffe47312 100644 --- a/tools/perf/arch/x86/util/event.c +++ b/tools/perf/arch/x86/util/event.c @@ -61,7 +61,7 @@ int perf_event__synthesize_extra_kmaps(struct perf_tool *tool, event->mmap.start = map__start(map); event->mmap.len = map__size(map); - event->mmap.pgoff = map->pgoff; + event->mmap.pgoff = map__pgoff(map); event->mmap.pid = machine->pid; strlcpy(event->mmap.filename, kmap->name, PATH_MAX); diff --git a/tools/perf/builtin-report.c b/tools/perf/builtin-report.c index c066452219c8..92c6797e7cba 100644 --- a/tools/perf/builtin-report.c +++ b/tools/perf/builtin-report.c @@ -857,7 +857,7 @@ static size_t maps__fprintf_task(struct maps *maps, int indent, FILE *fp) prot & PROT_WRITE ? 'w' : '-', prot & PROT_EXEC ? 'x' : '-', map__flags(map) ? 's' : 'p', - map->pgoff, + map__pgoff(map), dso->id.ino, dso->name); } diff --git a/tools/perf/tests/vmlinux-kallsyms.c b/tools/perf/tests/vmlinux-kallsyms.c index 7db102868bc2..af511233c764 100644 --- a/tools/perf/tests/vmlinux-kallsyms.c +++ b/tools/perf/tests/vmlinux-kallsyms.c @@ -335,10 +335,10 @@ next_pair: } pr_info("WARN: %" PRIx64 "-%" PRIx64 " %" PRIx64 " %s in kallsyms as", - map__start(map), map__end(map), map->pgoff, dso->name); + map__start(map), map__end(map), map__pgoff(map), dso->name); if (mem_end != map__end(pair)) pr_info(":\nWARN: *%" PRIx64 "-%" PRIx64 " %" PRIx64, - map__start(pair), map__end(pair), pair->pgoff); + map__start(pair), map__end(pair), map__pgoff(pair)); pr_info(" %s\n", dso->name); pair->priv = 1; } diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c index d29ec4a04488..1ea6f6c06bbb 100644 --- a/tools/perf/util/machine.c +++ b/tools/perf/util/machine.c @@ -1277,9 +1277,9 @@ int machine__map_x86_64_entry_trampolines(struct machine *machine, if (!kmap || !is_entry_trampoline(kmap->name)) continue; - dest_map = maps__find(kmaps, map->pgoff); + dest_map = maps__find(kmaps, map__pgoff(map)); if (dest_map != map) - map->pgoff = map__map_ip(dest_map, map->pgoff); + map->pgoff = map__map_ip(dest_map, map__pgoff(map)); found = true; } if (found || machine->trampolines_mapped) diff --git a/tools/perf/util/map.c b/tools/perf/util/map.c index a55aef4b1310..6426af6882c2 100644 --- a/tools/perf/util/map.c +++ b/tools/perf/util/map.c @@ -421,7 +421,7 @@ size_t map__fprintf(struct map *map, FILE *fp) const struct dso *dso = map__dso(map); return fprintf(fp, " %" PRIx64 "-%" PRIx64 " %" PRIx64 " %s\n", - map__start(map), map__end(map), map->pgoff, dso->name); + map__start(map), map__end(map), map__pgoff(map), dso->name); } size_t map__fprintf_dsoname(struct map *map, FILE *fp) @@ -510,7 +510,7 @@ u64 map__rip_2objdump(struct map *map, u64 rip) return rip; if (dso->rel) - return rip - map->pgoff; + return rip - map__pgoff(map); /* * kernel modules also have DSO_TYPE_USER in dso->kernel, @@ -519,7 +519,7 @@ u64 map__rip_2objdump(struct map *map, u64 rip) if (dso->kernel == DSO_SPACE__USER) return rip + dso->text_offset; - return map__unmap_ip(map, rip) - map->reloc; + return map__unmap_ip(map, rip) - map__reloc(map); } /** @@ -542,7 +542,7 @@ u64 map__objdump_2mem(struct map *map, u64 ip) return map__unmap_ip(map, ip); if (dso->rel) - return map__unmap_ip(map, ip + map->pgoff); + return map__unmap_ip(map, ip + map__pgoff(map)); /* * kernel modules also have DSO_TYPE_USER in dso->kernel, @@ -551,7 +551,7 @@ u64 map__objdump_2mem(struct map *map, u64 ip) if (dso->kernel == DSO_SPACE__USER) return map__unmap_ip(map, ip - dso->text_offset); - return ip + map->reloc; + return ip + map__reloc(map); } bool map__contains_symbol(const struct map *map, const struct symbol *sym) @@ -592,12 +592,12 @@ struct maps *map__kmaps(struct map *map) u64 map__dso_map_ip(const struct map *map, u64 ip) { - return ip - map__start(map) + map->pgoff; + return ip - map__start(map) + map__pgoff(map); } u64 map__dso_unmap_ip(const struct map *map, u64 ip) { - return ip + map__start(map) - map->pgoff; + return ip + map__start(map) - map__pgoff(map); } u64 identity__map_ip(const struct map *map __maybe_unused, u64 ip) diff --git a/tools/perf/util/map.h b/tools/perf/util/map.h index fd440c9c279e..102485699aa8 100644 --- a/tools/perf/util/map.h +++ b/tools/perf/util/map.h @@ -72,6 +72,16 @@ static inline u64 map__end(const struct map *map) return map->end; } +static inline u64 map__pgoff(const struct map *map) +{ + return map->pgoff; +} + +static inline u64 map__reloc(const struct map *map) +{ + return map->reloc; +} + static inline u32 map__flags(const struct map *map) { return map->flags; diff --git a/tools/perf/util/probe-event.c b/tools/perf/util/probe-event.c index bb44a3798df8..6e2110d605fb 100644 --- a/tools/perf/util/probe-event.c +++ b/tools/perf/util/probe-event.c @@ -135,14 +135,14 @@ static int kernel_get_symbol_address_by_name(const char *name, u64 *addr, /* ref_reloc_sym is just a label. Need a special fix*/ reloc_sym = kernel_get_ref_reloc_sym(&map); if (reloc_sym && strcmp(name, reloc_sym->name) == 0) - *addr = (!map->reloc || reloc) ? reloc_sym->addr : + *addr = (!map__reloc(map) || reloc) ? reloc_sym->addr : reloc_sym->unrelocated_addr; else { sym = machine__find_kernel_symbol_by_name(host_machine, name, &map); if (!sym) return -ENOENT; *addr = map__unmap_ip(map, sym->start) - - ((reloc) ? 0 : map->reloc) - + ((reloc) ? 0 : map__reloc(map)) - ((reladdr) ? map__start(map) : 0); } return 0; @@ -400,7 +400,7 @@ static int find_alternative_probe_point(struct debuginfo *dinfo, "Consider identifying the final function used at run time and set the probe directly on that.\n", pp->function); } else - address = map__unmap_ip(map, sym->start) - map->reloc; + address = map__unmap_ip(map, sym->start) - map__reloc(map); break; } if (!address) { @@ -866,7 +866,7 @@ post_process_kernel_probe_trace_events(struct probe_trace_event *tevs, free(tevs[i].point.symbol); tevs[i].point.symbol = tmp; tevs[i].point.offset = tevs[i].point.address - - (map->reloc ? reloc_sym->unrelocated_addr : + (map__reloc(map) ? reloc_sym->unrelocated_addr : reloc_sym->addr); } return skipped; diff --git a/tools/perf/util/symbol.c b/tools/perf/util/symbol.c index 5c075d77a792..7282119c2990 100644 --- a/tools/perf/util/symbol.c +++ b/tools/perf/util/symbol.c @@ -810,11 +810,11 @@ static int maps__split_kallsyms_for_kcore(struct maps *kmaps, struct dso *dso) continue; } curr_map_dso = map__dso(curr_map); - pos->start -= map__start(curr_map) - curr_map->pgoff; + pos->start -= map__start(curr_map) - map__pgoff(curr_map); if (pos->end > map__end(curr_map)) pos->end = map__end(curr_map); if (pos->end) - pos->end -= map__start(curr_map) - curr_map->pgoff; + pos->end -= map__start(curr_map) - map__pgoff(curr_map); symbols__insert(&curr_map_dso->symbols, pos); ++count; } @@ -1459,7 +1459,7 @@ static int dso__load_kcore(struct dso *dso, struct map *map, if (new_map == replacement_map) { map->start = map__start(new_map); map->end = map__end(new_map); - map->pgoff = new_map->pgoff; + map->pgoff = map__pgoff(new_map); map->map_ip = new_map->map_ip; map->unmap_ip = new_map->unmap_ip; /* Ensure maps are correctly ordered */ diff --git a/tools/perf/util/unwind-libdw.c b/tools/perf/util/unwind-libdw.c index 538320e4260c..9565f9906e5d 100644 --- a/tools/perf/util/unwind-libdw.c +++ b/tools/perf/util/unwind-libdw.c @@ -62,19 +62,19 @@ static int __report_module(struct addr_location *al, u64 ip, Dwarf_Addr s; dwfl_module_info(mod, NULL, &s, NULL, NULL, NULL, NULL, NULL); - if (s != map__start(al->map) - al->map->pgoff) + if (s != map__start(al->map) - map__pgoff(al->map)) mod = 0; } if (!mod) mod = dwfl_report_elf(ui->dwfl, dso->short_name, dso->long_name, -1, - map__start(al->map) - al->map->pgoff, false); + map__start(al->map) - map__pgoff(al->map), false); if (!mod) { char filename[PATH_MAX]; if (dso__build_id_filename(dso, filename, sizeof(filename), false)) mod = dwfl_report_elf(ui->dwfl, dso->short_name, filename, -1, - map__start(al->map) - al->map->pgoff, false); + map__start(al->map) - map__pgoff(al->map), false); } if (mod) { -- cgit v1.2.3-58-ga151 From 93c9f1c287d00ab396f76955a79beac46efca2d5 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Tue, 4 Apr 2023 13:59:47 -0700 Subject: perf test: Add extra diagnostics to maps test Dump the resultant and comparison maps on failure. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexey Bayduraev Cc: Andi Kleen Cc: Andrew Morton Cc: Andy Shevchenko Cc: Darren Hart Cc: Davidlohr Bueso Cc: Dmitriy Vyukov Cc: Eric Dumazet Cc: German Gomez Cc: Hao Luo Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Madhavan Srinivasan Cc: Mark Rutland Cc: Masami Hiramatsu Cc: Miaoqian Lin Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Riccardo Mancini Cc: Shunsuke Nakamura Cc: Song Liu Cc: Stephane Eranian Cc: Stephen Brennan Cc: Steven Rostedt (VMware) Cc: Thomas Gleixner Cc: Thomas Richter Cc: Yury Norov Link: https://lore.kernel.org/r/20230404205954.2245628-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/maps.c | 51 ++++++++++++++++++++++++++++++++++--------------- 1 file changed, 36 insertions(+), 15 deletions(-) (limited to 'tools') diff --git a/tools/perf/tests/maps.c b/tools/perf/tests/maps.c index fd0c464fcf95..1c7293476aca 100644 --- a/tools/perf/tests/maps.c +++ b/tools/perf/tests/maps.c @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +#include #include #include #include "tests.h" @@ -17,22 +18,42 @@ static int check_maps(struct map_def *merged, unsigned int size, struct maps *ma { struct map_rb_node *rb_node; unsigned int i = 0; - - maps__for_each_entry(maps, rb_node) { - struct map *map = rb_node->map; - - if (i > 0) - TEST_ASSERT_VAL("less maps expected", (map && i < size) || (!map && i == size)); - - TEST_ASSERT_VAL("wrong map start", map__start(map) == merged[i].start); - TEST_ASSERT_VAL("wrong map end", map__end(map) == merged[i].end); - TEST_ASSERT_VAL("wrong map name", !strcmp(map__dso(map)->name, merged[i].name)); - TEST_ASSERT_VAL("wrong map refcnt", refcount_read(&map->refcnt) == 1); - - i++; + bool failed = false; + + if (maps__nr_maps(maps) != size) { + pr_debug("Expected %d maps, got %d", size, maps__nr_maps(maps)); + failed = true; + } else { + maps__for_each_entry(maps, rb_node) { + struct map *map = rb_node->map; + + if (map__start(map) != merged[i].start || + map__end(map) != merged[i].end || + strcmp(map__dso(map)->name, merged[i].name) || + refcount_read(&map->refcnt) != 1) { + failed = true; + } + i++; + } } - - return TEST_OK; + if (failed) { + pr_debug("Expected:\n"); + for (i = 0; i < size; i++) { + pr_debug("\tstart: %" PRIu64 " end: %" PRIu64 " name: '%s' refcnt: 1\n", + merged[i].start, merged[i].end, merged[i].name); + } + pr_debug("Got:\n"); + maps__for_each_entry(maps, rb_node) { + struct map *map = rb_node->map; + + pr_debug("\tstart: %" PRIu64 " end: %" PRIu64 " name: '%s' refcnt: %d\n", + map__start(map), + map__end(map), + map__dso(map)->name, + refcount_read(&map->refcnt)); + } + } + return failed ? TEST_FAIL : TEST_OK; } static int test__maps__merge_in(struct test_suite *t __maybe_unused, int subtest __maybe_unused) -- cgit v1.2.3-58-ga151 From 392cf49ec54f0c7ba825ce9b04bf32bb85998135 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Tue, 4 Apr 2023 13:59:48 -0700 Subject: perf maps: Modify maps_by_name to hold a reference to a map To make it clearer about the ownership of a reference count split the by-name case from the regular start-address sorted tree. Put the reference count when maps_by_name is freed, which requires moving a decrement to nr_maps in maps__remove. Add two missing map puts in maps__fixup_overlappings in the event maps__insert fails. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexey Bayduraev Cc: Andi Kleen Cc: Andrew Morton Cc: Andy Shevchenko Cc: Darren Hart Cc: Davidlohr Bueso Cc: Dmitriy Vyukov Cc: Eric Dumazet Cc: German Gomez Cc: Hao Luo Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Madhavan Srinivasan Cc: Mark Rutland Cc: Masami Hiramatsu Cc: Miaoqian Lin Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Riccardo Mancini Cc: Shunsuke Nakamura Cc: Song Liu Cc: Stephane Eranian Cc: Stephen Brennan Cc: Steven Rostedt (VMware) Cc: Thomas Gleixner Cc: Thomas Richter Cc: Yury Norov Link: https://lore.kernel.org/r/20230404205954.2245628-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/maps.c | 30 ++++++++++++++++-------------- tools/perf/util/symbol.c | 21 +++++++++++++++++---- 2 files changed, 33 insertions(+), 18 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/maps.c b/tools/perf/util/maps.c index 0eee27e24c33..5afed53ea0b4 100644 --- a/tools/perf/util/maps.c +++ b/tools/perf/util/maps.c @@ -26,6 +26,9 @@ static void __maps__free_maps_by_name(struct maps *maps) /* * Free everything to try to do it from the rbtree in the next search */ + for (unsigned int i = 0; i < maps__nr_maps(maps); i++) + map__put(maps__maps_by_name(maps)[i]); + zfree(&maps->maps_by_name); maps->nr_maps_allocated = 0; } @@ -42,7 +45,7 @@ static int __maps__insert(struct maps *maps, struct map *map) return -ENOMEM; RB_CLEAR_NODE(&new_rb_node->rb_node); - new_rb_node->map = map; + new_rb_node->map = map__get(map); while (*p != NULL) { parent = *p; @@ -55,7 +58,6 @@ static int __maps__insert(struct maps *maps, struct map *map) rb_link_node(&new_rb_node->rb_node, parent, p); rb_insert_color(&new_rb_node->rb_node, maps__entries(maps)); - map__get(map); return 0; } @@ -100,7 +102,7 @@ int maps__insert(struct maps *maps, struct map *map) maps->maps_by_name = maps_by_name; maps->nr_maps_allocated = nr_allocate; } - maps__maps_by_name(maps)[maps__nr_maps(maps) - 1] = map; + maps__maps_by_name(maps)[maps__nr_maps(maps) - 1] = map__get(map); __maps__sort_by_name(maps); } out: @@ -126,9 +128,9 @@ void maps__remove(struct maps *maps, struct map *map) rb_node = maps__find_node(maps, map); assert(rb_node->map == map); __maps__remove(maps, rb_node); - --maps->nr_maps; if (maps__maps_by_name(maps)) __maps__free_maps_by_name(maps); + --maps->nr_maps; up_write(maps__lock(maps)); } @@ -136,6 +138,9 @@ static void __maps__purge(struct maps *maps) { struct map_rb_node *pos, *next; + if (maps__maps_by_name(maps)) + __maps__free_maps_by_name(maps); + maps__for_each_entry_safe(maps, pos, next) { rb_erase_init(&pos->rb_node, maps__entries(maps)); map__put(pos->map); @@ -293,7 +298,7 @@ int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp) } next = first; - while (next) { + while (next && !err) { struct map_rb_node *pos = rb_entry(next, struct map_rb_node, rb_node); next = rb_next(&pos->rb_node); @@ -331,8 +336,10 @@ int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp) before->end = map__start(map); err = __maps__insert(maps, before); - if (err) + if (err) { + map__put(before); goto put_map; + } if (verbose >= 2 && !use_browser) map__fprintf(before, fp); @@ -352,22 +359,17 @@ int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp) assert(map__map_ip(pos->map, map__end(map)) == map__map_ip(after, map__end(map))); err = __maps__insert(maps, after); - if (err) + if (err) { + map__put(after); goto put_map; - + } if (verbose >= 2 && !use_browser) map__fprintf(after, fp); map__put(after); } put_map: map__put(pos->map); - - if (err) - goto out; } - - err = 0; -out: up_write(maps__lock(maps)); return err; } diff --git a/tools/perf/util/symbol.c b/tools/perf/util/symbol.c index 7282119c2990..91ebf93e0c20 100644 --- a/tools/perf/util/symbol.c +++ b/tools/perf/util/symbol.c @@ -2053,10 +2053,23 @@ out: static int map__strcmp(const void *a, const void *b) { - const struct dso *dso_a = map__dso(*(const struct map **)a); - const struct dso *dso_b = map__dso(*(const struct map **)b); + const struct map *map_a = *(const struct map **)a; + const struct map *map_b = *(const struct map **)b; + const struct dso *dso_a = map__dso(map_a); + const struct dso *dso_b = map__dso(map_b); + int ret = strcmp(dso_a->short_name, dso_b->short_name); - return strcmp(dso_a->short_name, dso_b->short_name); + if (ret == 0 && map_a != map_b) { + /* + * Ensure distinct but name equal maps have an order in part to + * aid reference counting. + */ + ret = (int)map__start(map_a) - (int)map__start(map_b); + if (ret == 0) + ret = (int)((intptr_t)map_a - (intptr_t)map_b); + } + + return ret; } static int map__strcmp_name(const void *name, const void *b) @@ -2088,7 +2101,7 @@ static int map__groups__sort_by_name_from_rbtree(struct maps *maps) maps->nr_maps_allocated = maps__nr_maps(maps); maps__for_each_entry(maps, rb_node) - maps_by_name[i++] = rb_node->map; + maps_by_name[i++] = map__get(rb_node->map); __maps__sort_by_name(maps); -- cgit v1.2.3-58-ga151 From ec417ad4c691b5d90ab13cf26789e8719468ae39 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Tue, 4 Apr 2023 13:59:49 -0700 Subject: perf map: Changes to reference counting When a pointer to a map exists do a get, when that pointer is overwritten or freed, put the map. This avoids issues with gets and puts being inconsistently used causing, use after puts, etc. For example, the map in struct addr_location is changed to hold a reference count. Reference count checking and address sanitizer were used to identify issues. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexey Bayduraev Cc: Andi Kleen Cc: Andrew Morton Cc: Andy Shevchenko Cc: Darren Hart Cc: Davidlohr Bueso Cc: Dmitriy Vyukov Cc: Eric Dumazet Cc: German Gomez Cc: Hao Luo Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Madhavan Srinivasan Cc: Mark Rutland Cc: Masami Hiramatsu Cc: Miaoqian Lin Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Riccardo Mancini Cc: Shunsuke Nakamura Cc: Song Liu Cc: Stephane Eranian Cc: Stephen Brennan Cc: Steven Rostedt (VMware) Cc: Thomas Gleixner Cc: Thomas Richter Cc: Yury Norov Link: https://lore.kernel.org/r/20230404205954.2245628-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/code-reading.c | 1 + tools/perf/tests/hists_cumulate.c | 10 +++++ tools/perf/tests/hists_filter.c | 10 +++++ tools/perf/tests/hists_link.c | 18 +++++++- tools/perf/tests/hists_output.c | 10 +++++ tools/perf/tests/mmap-thread-lookup.c | 1 + tools/perf/util/callchain.c | 9 ++-- tools/perf/util/event.c | 6 ++- tools/perf/util/hist.c | 10 ++--- tools/perf/util/machine.c | 79 +++++++++++++++++++++-------------- tools/perf/util/map.c | 2 +- 11 files changed, 112 insertions(+), 44 deletions(-) (limited to 'tools') diff --git a/tools/perf/tests/code-reading.c b/tools/perf/tests/code-reading.c index 1545fcaa95c6..efe026a35010 100644 --- a/tools/perf/tests/code-reading.c +++ b/tools/perf/tests/code-reading.c @@ -366,6 +366,7 @@ static int read_object_code(u64 addr, size_t len, u8 cpumode, } pr_debug("Bytes read match those read by objdump\n"); out: + map__put(al.map); return err; } diff --git a/tools/perf/tests/hists_cumulate.c b/tools/perf/tests/hists_cumulate.c index f00ec9abdbcd..8c0e3f334747 100644 --- a/tools/perf/tests/hists_cumulate.c +++ b/tools/perf/tests/hists_cumulate.c @@ -112,6 +112,7 @@ static int add_hist_entries(struct hists *hists, struct machine *machine) } fake_samples[i].thread = al.thread; + map__put(fake_samples[i].map); fake_samples[i].map = al.map; fake_samples[i].sym = al.sym; } @@ -147,6 +148,14 @@ static void del_hist_entries(struct hists *hists) } } +static void put_fake_samples(void) +{ + size_t i; + + for (i = 0; i < ARRAY_SIZE(fake_samples); i++) + map__put(fake_samples[i].map); +} + typedef int (*test_fn_t)(struct evsel *, struct machine *); #define COMM(he) (thread__comm_str(he->thread)) @@ -733,6 +742,7 @@ out: /* tear down everything */ evlist__delete(evlist); machines__exit(&machines); + put_fake_samples(); return err; } diff --git a/tools/perf/tests/hists_filter.c b/tools/perf/tests/hists_filter.c index 7c552549f4a4..98eff5935a1c 100644 --- a/tools/perf/tests/hists_filter.c +++ b/tools/perf/tests/hists_filter.c @@ -89,6 +89,7 @@ static int add_hist_entries(struct evlist *evlist, } fake_samples[i].thread = al.thread; + map__put(fake_samples[i].map); fake_samples[i].map = al.map; fake_samples[i].sym = al.sym; } @@ -101,6 +102,14 @@ out: return TEST_FAIL; } +static void put_fake_samples(void) +{ + size_t i; + + for (i = 0; i < ARRAY_SIZE(fake_samples); i++) + map__put(fake_samples[i].map); +} + static int test__hists_filter(struct test_suite *test __maybe_unused, int subtest __maybe_unused) { int err = TEST_FAIL; @@ -322,6 +331,7 @@ out: evlist__delete(evlist); reset_output_field(); machines__exit(&machines); + put_fake_samples(); return err; } diff --git a/tools/perf/tests/hists_link.c b/tools/perf/tests/hists_link.c index e7e4ee57ce04..64ce8097889c 100644 --- a/tools/perf/tests/hists_link.c +++ b/tools/perf/tests/hists_link.c @@ -6,6 +6,7 @@ #include "evsel.h" #include "evlist.h" #include "machine.h" +#include "map.h" #include "parse-events.h" #include "hists_common.h" #include "util/mmap.h" @@ -94,6 +95,7 @@ static int add_hist_entries(struct evlist *evlist, struct machine *machine) } fake_common_samples[k].thread = al.thread; + map__put(fake_common_samples[k].map); fake_common_samples[k].map = al.map; fake_common_samples[k].sym = al.sym; } @@ -126,11 +128,24 @@ out: return -1; } +static void put_fake_samples(void) +{ + size_t i, j; + + for (i = 0; i < ARRAY_SIZE(fake_common_samples); i++) + map__put(fake_common_samples[i].map); + for (i = 0; i < ARRAY_SIZE(fake_samples); i++) { + for (j = 0; j < ARRAY_SIZE(fake_samples[0]); j++) + map__put(fake_samples[i][j].map); + } +} + static int find_sample(struct sample *samples, size_t nr_samples, struct thread *t, struct map *m, struct symbol *s) { while (nr_samples--) { - if (samples->thread == t && samples->map == m && + if (samples->thread == t && + samples->map == m && samples->sym == s) return 1; samples++; @@ -336,6 +351,7 @@ out: evlist__delete(evlist); reset_output_field(); machines__exit(&machines); + put_fake_samples(); return err; } diff --git a/tools/perf/tests/hists_output.c b/tools/perf/tests/hists_output.c index 428d11a938f2..cebd5226bb12 100644 --- a/tools/perf/tests/hists_output.c +++ b/tools/perf/tests/hists_output.c @@ -78,6 +78,7 @@ static int add_hist_entries(struct hists *hists, struct machine *machine) } fake_samples[i].thread = al.thread; + map__put(fake_samples[i].map); fake_samples[i].map = al.map; fake_samples[i].sym = al.sym; } @@ -113,6 +114,14 @@ static void del_hist_entries(struct hists *hists) } } +static void put_fake_samples(void) +{ + size_t i; + + for (i = 0; i < ARRAY_SIZE(fake_samples); i++) + map__put(fake_samples[i].map); +} + typedef int (*test_fn_t)(struct evsel *, struct machine *); #define COMM(he) (thread__comm_str(he->thread)) @@ -620,6 +629,7 @@ out: /* tear down everything */ evlist__delete(evlist); machines__exit(&machines); + put_fake_samples(); return err; } diff --git a/tools/perf/tests/mmap-thread-lookup.c b/tools/perf/tests/mmap-thread-lookup.c index 5cc4644e353d..898eda55b7a8 100644 --- a/tools/perf/tests/mmap-thread-lookup.c +++ b/tools/perf/tests/mmap-thread-lookup.c @@ -203,6 +203,7 @@ static int mmap_events(synth_cb synth) } pr_debug("map %p, addr %" PRIx64 "\n", al.map, map__start(al.map)); + map__put(al.map); } machine__delete_threads(machine); diff --git a/tools/perf/util/callchain.c b/tools/perf/util/callchain.c index 8e7c29836765..b0dafc758173 100644 --- a/tools/perf/util/callchain.c +++ b/tools/perf/util/callchain.c @@ -589,7 +589,7 @@ fill_node(struct callchain_node *node, struct callchain_cursor *cursor) } call->ip = cursor_node->ip; call->ms = cursor_node->ms; - map__get(call->ms.map); + call->ms.map = map__get(call->ms.map); call->srcline = cursor_node->srcline; if (cursor_node->branch) { @@ -1067,7 +1067,7 @@ int callchain_cursor_append(struct callchain_cursor *cursor, node->ip = ip; map__zput(node->ms.map); node->ms = *ms; - map__get(node->ms.map); + node->ms.map = map__get(node->ms.map); node->branch = branch; node->nr_loop_iter = nr_loop_iter; node->iter_cycles = iter_cycles; @@ -1115,7 +1115,8 @@ int fill_callchain_info(struct addr_location *al, struct callchain_cursor_node * struct machine *machine = maps__machine(node->ms.maps); al->maps = node->ms.maps; - al->map = node->ms.map; + map__put(al->map); + al->map = map__get(node->ms.map); al->sym = node->ms.sym; al->srcline = node->srcline; al->addr = node->ip; @@ -1528,7 +1529,7 @@ int callchain_node__make_parent_list(struct callchain_node *node) goto out; *new = *chain; new->has_children = false; - map__get(new->ms.map); + new->ms.map = map__get(new->ms.map); list_add_tail(&new->list, &head); } parent = parent->parent; diff --git a/tools/perf/util/event.c b/tools/perf/util/event.c index 2712d1a8264e..13f7f85e92e1 100644 --- a/tools/perf/util/event.c +++ b/tools/perf/util/event.c @@ -485,13 +485,14 @@ size_t perf_event__fprintf_text_poke(union perf_event *event, struct machine *ma if (machine) { struct addr_location al; - al.map = maps__find(machine__kernel_maps(machine), tp->addr); + al.map = map__get(maps__find(machine__kernel_maps(machine), tp->addr)); if (al.map && map__load(al.map) >= 0) { al.addr = map__map_ip(al.map, tp->addr); al.sym = map__find_symbol(al.map, al.addr); if (al.sym) ret += symbol__fprintf_symname_offs(al.sym, &al, fp); } + map__put(al.map); } ret += fprintf(fp, " old len %u new len %u\n", tp->old_len, tp->new_len); old = true; @@ -614,7 +615,7 @@ struct map *thread__find_map(struct thread *thread, u8 cpumode, u64 addr, return NULL; } - al->map = maps__find(maps, al->addr); + al->map = map__get(maps__find(maps, al->addr)); if (al->map != NULL) { /* * Kernel maps might be changed when loading symbols so loading @@ -773,6 +774,7 @@ int machine__resolve(struct machine *machine, struct addr_location *al, */ void addr_location__put(struct addr_location *al) { + map__zput(al->map); thread__zput(al->thread); } diff --git a/tools/perf/util/hist.c b/tools/perf/util/hist.c index e494425cad06..51020da15ffc 100644 --- a/tools/perf/util/hist.c +++ b/tools/perf/util/hist.c @@ -450,7 +450,7 @@ static int hist_entry__init(struct hist_entry *he, memset(&he->stat, 0, sizeof(he->stat)); } - map__get(he->ms.map); + he->ms.map = map__get(he->ms.map); if (he->branch_info) { /* @@ -465,13 +465,13 @@ static int hist_entry__init(struct hist_entry *he, memcpy(he->branch_info, template->branch_info, sizeof(*he->branch_info)); - map__get(he->branch_info->from.ms.map); - map__get(he->branch_info->to.ms.map); + he->branch_info->from.ms.map = map__get(he->branch_info->from.ms.map); + he->branch_info->to.ms.map = map__get(he->branch_info->to.ms.map); } if (he->mem_info) { - map__get(he->mem_info->iaddr.ms.map); - map__get(he->mem_info->daddr.ms.map); + he->mem_info->iaddr.ms.map = map__get(he->mem_info->iaddr.ms.map); + he->mem_info->daddr.ms.map = map__get(he->mem_info->daddr.ms.map); } if (hist_entry__has_callchains(he) && symbol_conf.use_callchain) diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c index 1ea6f6c06bbb..25738775834e 100644 --- a/tools/perf/util/machine.c +++ b/tools/perf/util/machine.c @@ -881,21 +881,29 @@ static int machine__process_ksymbol_register(struct machine *machine, struct symbol *sym; struct dso *dso; struct map *map = maps__find(machine__kernel_maps(machine), event->ksymbol.addr); + bool put_map = false; + int err = 0; if (!map) { - int err; - dso = dso__new(event->ksymbol.name); - if (dso) { - dso->kernel = DSO_SPACE__KERNEL; - map = map__new2(0, dso); - dso__put(dso); - } - if (!dso || !map) { - return -ENOMEM; + if (!dso) { + err = -ENOMEM; + goto out; } - + dso->kernel = DSO_SPACE__KERNEL; + map = map__new2(0, dso); + dso__put(dso); + if (!map) { + err = -ENOMEM; + goto out; + } + /* + * The inserted map has a get on it, we need to put to release + * the reference count here, but do it after all accesses are + * done. + */ + put_map = true; if (event->ksymbol.ksym_type == PERF_RECORD_KSYMBOL_TYPE_OOL) { dso->binary_type = DSO_BINARY_TYPE__OOL; dso->data.file_size = event->ksymbol.len; @@ -905,9 +913,10 @@ static int machine__process_ksymbol_register(struct machine *machine, map->start = event->ksymbol.addr; map->end = map__start(map) + event->ksymbol.len; err = maps__insert(machine__kernel_maps(machine), map); - map__put(map); - if (err) - return err; + if (err) { + err = -ENOMEM; + goto out; + } dso__set_loaded(dso); @@ -922,10 +931,15 @@ static int machine__process_ksymbol_register(struct machine *machine, sym = symbol__new(map__map_ip(map, map__start(map)), event->ksymbol.len, 0, 0, event->ksymbol.name); - if (!sym) - return -ENOMEM; + if (!sym) { + err = -ENOMEM; + goto out; + } dso__insert_symbol(dso, sym); - return 0; +out: + if (put_map) + map__put(map); + return err; } static int machine__process_ksymbol_unregister(struct machine *machine, @@ -1027,13 +1041,11 @@ static struct map *machine__addnew_module_map(struct machine *machine, u64 start goto out; err = maps__insert(machine__kernel_maps(machine), map); - - /* Put the map here because maps__insert already got it */ - map__put(map); - /* If maps__insert failed, return NULL. */ - if (err) + if (err) { + map__put(map); map = NULL; + } out: /* put the dso here, corresponding to machine__findnew_module_dso */ dso__put(dso); @@ -1325,6 +1337,7 @@ __machine__create_kernel_maps(struct machine *machine, struct dso *kernel) /* In case of renewal the kernel map, destroy previous one */ machine__destroy_kernel_maps(machine); + map__put(machine->vmlinux_map); machine->vmlinux_map = map__new2(0, kernel); if (machine->vmlinux_map == NULL) return -ENOMEM; @@ -1613,7 +1626,7 @@ static int machine__create_module(void *arg, const char *name, u64 start, map->end = start + size; dso__kernel_module_get_build_id(map__dso(map), machine->root_dir); - + map__put(map); return 0; } @@ -1659,16 +1672,18 @@ static void machine__set_kernel_mmap(struct machine *machine, static int machine__update_kernel_mmap(struct machine *machine, u64 start, u64 end) { - struct map *map = machine__kernel_map(machine); + struct map *orig, *updated; int err; - map__get(map); - maps__remove(machine__kernel_maps(machine), map); + orig = machine->vmlinux_map; + updated = map__get(orig); + machine->vmlinux_map = updated; machine__set_kernel_mmap(machine, start, end); + maps__remove(machine__kernel_maps(machine), orig); + err = maps__insert(machine__kernel_maps(machine), updated); + map__put(orig); - err = maps__insert(machine__kernel_maps(machine), map); - map__put(map); return err; } @@ -2295,7 +2310,7 @@ static int add_callchain_ip(struct thread *thread, { struct map_symbol ms; struct addr_location al; - int nr_loop_iter = 0; + int nr_loop_iter = 0, err; u64 iter_cycles = 0; const char *srcline = NULL; @@ -2360,9 +2375,11 @@ static int add_callchain_ip(struct thread *thread, return 0; srcline = callchain_srcline(&ms, al.addr); - return callchain_cursor_append(cursor, ip, &ms, - branch, flags, nr_loop_iter, - iter_cycles, branch_from, srcline); + err = callchain_cursor_append(cursor, ip, &ms, + branch, flags, nr_loop_iter, + iter_cycles, branch_from, srcline); + map__put(al.map); + return err; } struct branch_info *sample__resolve_bstack(struct perf_sample *sample, diff --git a/tools/perf/util/map.c b/tools/perf/util/map.c index 6426af6882c2..d81b6ca18ee9 100644 --- a/tools/perf/util/map.c +++ b/tools/perf/util/map.c @@ -410,7 +410,7 @@ struct map *map__clone(struct map *from) map = memdup(from, size); if (map != NULL) { refcount_set(&map->refcnt, 1); - dso__get(dso); + map->dso = dso__get(dso); } return map; -- cgit v1.2.3-58-ga151 From 0c1228486befa3d6e943488406f1e3c05679721b Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 7 Apr 2023 22:52:07 -0700 Subject: perf lock contention: Support pre-5.14 kernels 'struct rq's member '__lock' was renamed from 'lock' in 5.14. Signed-off-by: Ian Rogers Acked-by: Namhyung Kim Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Peter Zijlstra Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230408055208.1283832-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/bpf_skel/lock_contention.bpf.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/bpf_skel/lock_contention.bpf.c b/tools/perf/util/bpf_skel/lock_contention.bpf.c index 23f6e63544ed..8911e2a077d8 100644 --- a/tools/perf/util/bpf_skel/lock_contention.bpf.c +++ b/tools/perf/util/bpf_skel/lock_contention.bpf.c @@ -418,6 +418,14 @@ int contention_end(u64 *ctx) extern struct rq runqueues __ksym; +struct rq__old { + raw_spinlock_t lock; +} __attribute__((preserve_access_index)); + +struct rq__new { + raw_spinlock_t __lock; +} __attribute__((preserve_access_index)); + SEC("raw_tp/bpf_test_finish") int BPF_PROG(collect_lock_syms) { @@ -426,11 +434,16 @@ int BPF_PROG(collect_lock_syms) for (int i = 0; i < MAX_CPUS; i++) { struct rq *rq = bpf_per_cpu_ptr(&runqueues, i); + struct rq__new *rq_new = (void *)rq; + struct rq__old *rq_old = (void *)rq; if (rq == NULL) break; - lock_addr = (__u64)&rq->__lock; + if (bpf_core_field_exists(rq_new->__lock)) + lock_addr = (__u64)&rq_new->__lock; + else + lock_addr = (__u64)&rq_old->lock; lock_flag = LOCK_CLASS_RQLOCK; bpf_map_update_elem(&lock_syms, &lock_addr, &lock_flag, BPF_ANY); } -- cgit v1.2.3-58-ga151 From 3a8b8fc3174891c4c12f5766d82184a82d4b2e3e Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 7 Apr 2023 22:52:08 -0700 Subject: perf bpf filter: Support pre-5.16 kernels where 'mem_hops' isn't in 'union perf_mem_data_src' The 'mem_hops' bits were added in 5.16 with no prior equivalent. Signed-off-by: Ian Rogers Acked-by: Namhyung Kim Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Peter Zijlstra Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230408055208.1283832-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/bpf_skel/sample_filter.bpf.c | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/bpf_skel/sample_filter.bpf.c b/tools/perf/util/bpf_skel/sample_filter.bpf.c index 57e3c67d6d37..cffe493af1ed 100644 --- a/tools/perf/util/bpf_skel/sample_filter.bpf.c +++ b/tools/perf/util/bpf_skel/sample_filter.bpf.c @@ -24,6 +24,24 @@ struct perf_sample_data___new { __u64 sample_flags; } __attribute__((preserve_access_index)); +/* new kernel perf_mem_data_src definition */ +union perf_mem_data_src__new { + __u64 val; + struct { + __u64 mem_op:5, /* type of opcode */ + mem_lvl:14, /* memory hierarchy level */ + mem_snoop:5, /* snoop mode */ + mem_lock:2, /* lock instr */ + mem_dtlb:7, /* tlb access */ + mem_lvl_num:4, /* memory hierarchy level number */ + mem_remote:1, /* remote */ + mem_snoopx:2, /* snoop mode, ext */ + mem_blk:3, /* access blocked */ + mem_hops:3, /* hop level */ + mem_rsvd:18; + }; +}; + /* helper function to return the given perf sample data */ static inline __u64 perf_get_sample(struct bpf_perf_event_data_kern *kctx, struct perf_bpf_filter_entry *entry) @@ -89,8 +107,14 @@ static inline __u64 perf_get_sample(struct bpf_perf_event_data_kern *kctx, return kctx->data->data_src.mem_dtlb; if (entry->part == 7) return kctx->data->data_src.mem_blk; - if (entry->part == 8) - return kctx->data->data_src.mem_hops; + if (entry->part == 8) { + union perf_mem_data_src__new *data = (void *)&kctx->data->data_src; + + if (bpf_core_field_exists(data->mem_hops)) + return data->mem_hops; + + return 0; + } /* return the whole word */ return kctx->data->data_src.val; default: -- cgit v1.2.3-58-ga151 From 220368293a010d39fe41f130b99b666394034b08 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 7 Apr 2023 22:44:54 -0700 Subject: perf test stat+csv_output: Write CSV output to a file Write the CSV output to a file, then sanity check this output. This avoids problems with debug/warning/error output corrupting the file format. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Athira Rajeev Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Sumanth Korikkar Cc: Thomas Richter Link: https://lore.kernel.org/r/20230408054456.3001367-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/shell/stat+csv_output.sh | 58 ++++++++++++++++++++++--------- 1 file changed, 42 insertions(+), 16 deletions(-) (limited to 'tools') diff --git a/tools/perf/tests/shell/stat+csv_output.sh b/tools/perf/tests/shell/stat+csv_output.sh index 324fc9e6edd7..fb78b6251a4e 100755 --- a/tools/perf/tests/shell/stat+csv_output.sh +++ b/tools/perf/tests/shell/stat+csv_output.sh @@ -9,6 +9,20 @@ set -e skip_test=0 csv_sep=@ +stat_output=$(mktemp /tmp/__perf_test.stat_output.csv.XXXXX) + +cleanup() { + rm -f "${stat_output}" + + trap - EXIT TERM INT +} + +trap_cleanup() { + cleanup + exit 1 +} +trap trap_cleanup EXIT TERM INT + function commachecker() { local -i cnt=0 @@ -30,9 +44,11 @@ function commachecker() while read line do - # Check for lines beginning with Failed - x=${line:0:6} - [ "$x" = "Failed" ] && continue + # Ignore initial "started on" comment. + x=${line:0:1} + [ "$x" = "#" ] && continue + # Ignore initial blank line. + [ "$line" = "" ] && continue # Count the number of commas x=$(echo $line | tr -d -c $csv_sep) @@ -42,7 +58,7 @@ function commachecker() echo "wrong number of fields. expected $exp in $line" 1>&2 exit 1; } - done + done < "${stat_output}" return 0 } @@ -55,7 +71,8 @@ function ParanoidAndNotRoot() check_no_args() { echo -n "Checking CSV output: no args " - perf stat -x$csv_sep true 2>&1 | commachecker --no-args + perf stat -x$csv_sep -o "${stat_output}" true + commachecker --no-args echo "[Success]" } @@ -67,27 +84,29 @@ check_system_wide() echo "[Skip] paranoid and not root" return fi - perf stat -x$csv_sep -a true 2>&1 | commachecker --system-wide + perf stat -x$csv_sep -a -o "${stat_output}" true + commachecker --system-wide echo "[Success]" } check_system_wide_no_aggr() { - echo -n "Checking CSV output: system wide " + echo -n "Checking CSV output: system wide no aggregation " if ParanoidAndNotRoot 0 then echo "[Skip] paranoid and not root" return fi - echo -n "Checking CSV output: system wide no aggregation " - perf stat -x$csv_sep -A -a --no-merge true 2>&1 | commachecker --system-wide-no-aggr + perf stat -x$csv_sep -A -a --no-merge -o "${stat_output}" true + commachecker --system-wide-no-aggr echo "[Success]" } check_interval() { echo -n "Checking CSV output: interval " - perf stat -x$csv_sep -I 1000 true 2>&1 | commachecker --interval + perf stat -x$csv_sep -I 1000 -o "${stat_output}" true + commachecker --interval echo "[Success]" } @@ -95,7 +114,8 @@ check_interval() check_event() { echo -n "Checking CSV output: event " - perf stat -x$csv_sep -e cpu-clock true 2>&1 | commachecker --event + perf stat -x$csv_sep -e cpu-clock -o "${stat_output}" true + commachecker --event echo "[Success]" } @@ -107,7 +127,8 @@ check_per_core() echo "[Skip] paranoid and not root" return fi - perf stat -x$csv_sep --per-core -a true 2>&1 | commachecker --per-core + perf stat -x$csv_sep --per-core -a -o "${stat_output}" true + commachecker --per-core echo "[Success]" } @@ -119,7 +140,8 @@ check_per_thread() echo "[Skip] paranoid and not root" return fi - perf stat -x$csv_sep --per-thread -a true 2>&1 | commachecker --per-thread + perf stat -x$csv_sep --per-thread -a -o "${stat_output}" true + commachecker --per-thread echo "[Success]" } @@ -131,7 +153,8 @@ check_per_die() echo "[Skip] paranoid and not root" return fi - perf stat -x$csv_sep --per-die -a true 2>&1 | commachecker --per-die + perf stat -x$csv_sep --per-die -a -o "${stat_output}" true + commachecker --per-die echo "[Success]" } @@ -143,7 +166,8 @@ check_per_node() echo "[Skip] paranoid and not root" return fi - perf stat -x$csv_sep --per-node -a true 2>&1 | commachecker --per-node + perf stat -x$csv_sep --per-node -a -o "${stat_output}" true + commachecker --per-node echo "[Success]" } @@ -155,7 +179,8 @@ check_per_socket() echo "[Skip] paranoid and not root" return fi - perf stat -x$csv_sep --per-socket -a true 2>&1 | commachecker --per-socket + perf stat -x$csv_sep --per-socket -a -o "${stat_output}" true + commachecker --per-socket echo "[Success]" } @@ -202,4 +227,5 @@ then else echo "[Skip] Skipping tests for system_wide_no_aggr, per_core, per_die and per_socket since socket id exposed via topology is invalid" fi +cleanup exit 0 -- cgit v1.2.3-58-ga151 From 4228df84f952ff12540510a5c6cd00e976d992ab Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 7 Apr 2023 22:44:55 -0700 Subject: perf stat: Don't write invalid "started on" comment for JSON output JSON files don't support comments. Disable the "started on" comment when writing json output to file. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Athira Rajeev Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Sumanth Korikkar Cc: Thomas Richter Link: https://lore.kernel.org/r/20230408054456.3001367-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-stat.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index 38133afda7fc..40770926a230 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -2272,8 +2272,10 @@ int cmd_stat(int argc, const char **argv) perror("failed to create output file"); return -1; } - clock_gettime(CLOCK_REALTIME, &tm); - fprintf(output, "# started on %s\n", ctime(&tm.tv_sec)); + if (!stat_config.json_output) { + clock_gettime(CLOCK_REALTIME, &tm); + fprintf(output, "# started on %s\n", ctime(&tm.tv_sec)); + } } else if (output_fd > 0) { mode = append_file ? "a" : "w"; output = fdopen(output_fd, mode); -- cgit v1.2.3-58-ga151 From 760eafb2a3dd568a8eec519bf21c9a24582930f3 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 7 Apr 2023 22:44:56 -0700 Subject: perf test stat+json_output: Write JSON output to a file Write the JSON output to a file, then sanity check this output. This avoids problems with debug/warning/error output corrupting the file format. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Athira Rajeev Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Sumanth Korikkar Cc: Thomas Richter Link: https://lore.kernel.org/r/20230408054456.3001367-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../perf/tests/shell/lib/perf_json_output_lint.py | 3 +- tools/perf/tests/shell/stat+json_output.sh | 48 ++++++++++++++++------ 2 files changed, 38 insertions(+), 13 deletions(-) (limited to 'tools') diff --git a/tools/perf/tests/shell/lib/perf_json_output_lint.py b/tools/perf/tests/shell/lib/perf_json_output_lint.py index 97598d14e532..61f3059ca54b 100644 --- a/tools/perf/tests/shell/lib/perf_json_output_lint.py +++ b/tools/perf/tests/shell/lib/perf_json_output_lint.py @@ -17,9 +17,10 @@ ap.add_argument('--per-thread', action='store_true') ap.add_argument('--per-die', action='store_true') ap.add_argument('--per-node', action='store_true') ap.add_argument('--per-socket', action='store_true') +ap.add_argument('--file', type=argparse.FileType('r'), default=sys.stdin) args = ap.parse_args() -Lines = sys.stdin.readlines() +Lines = args.file.readlines() def isfloat(num): try: diff --git a/tools/perf/tests/shell/stat+json_output.sh b/tools/perf/tests/shell/stat+json_output.sh index 2c4212c641ed..f3e4967cc72e 100755 --- a/tools/perf/tests/shell/stat+json_output.sh +++ b/tools/perf/tests/shell/stat+json_output.sh @@ -23,6 +23,20 @@ then fi fi +stat_output=$(mktemp /tmp/__perf_test.stat_output.json.XXXXX) + +cleanup() { + rm -f "${stat_output}" + + trap - EXIT TERM INT +} + +trap_cleanup() { + cleanup + exit 1 +} +trap trap_cleanup EXIT TERM INT + # Return true if perf_event_paranoid is > $1 and not running as root. function ParanoidAndNotRoot() { @@ -32,7 +46,8 @@ function ParanoidAndNotRoot() check_no_args() { echo -n "Checking json output: no args " - perf stat -j true 2>&1 | $PYTHON $pythonchecker --no-args + perf stat -j -o "${stat_output}" true + $PYTHON $pythonchecker --no-args --file "${stat_output}" echo "[Success]" } @@ -44,27 +59,29 @@ check_system_wide() echo "[Skip] paranoia and not root" return fi - perf stat -j -a true 2>&1 | $PYTHON $pythonchecker --system-wide + perf stat -j -a -o "${stat_output}" true + $PYTHON $pythonchecker --system-wide --file "${stat_output}" echo "[Success]" } check_system_wide_no_aggr() { - echo -n "Checking json output: system wide " + echo -n "Checking json output: system wide no aggregation " if ParanoidAndNotRoot 0 then echo "[Skip] paranoia and not root" return fi - echo -n "Checking json output: system wide no aggregation " - perf stat -j -A -a --no-merge true 2>&1 | $PYTHON $pythonchecker --system-wide-no-aggr + perf stat -j -A -a --no-merge -o "${stat_output}" true + $PYTHON $pythonchecker --system-wide-no-aggr --file "${stat_output}" echo "[Success]" } check_interval() { echo -n "Checking json output: interval " - perf stat -j -I 1000 true 2>&1 | $PYTHON $pythonchecker --interval + perf stat -j -I 1000 -o "${stat_output}" true + $PYTHON $pythonchecker --interval --file "${stat_output}" echo "[Success]" } @@ -72,7 +89,8 @@ check_interval() check_event() { echo -n "Checking json output: event " - perf stat -j -e cpu-clock true 2>&1 | $PYTHON $pythonchecker --event + perf stat -j -e cpu-clock -o "${stat_output}" true + $PYTHON $pythonchecker --event --file "${stat_output}" echo "[Success]" } @@ -84,7 +102,8 @@ check_per_core() echo "[Skip] paranoia and not root" return fi - perf stat -j --per-core -a true 2>&1 | $PYTHON $pythonchecker --per-core + perf stat -j --per-core -a -o "${stat_output}" true + $PYTHON $pythonchecker --per-core --file "${stat_output}" echo "[Success]" } @@ -96,7 +115,8 @@ check_per_thread() echo "[Skip] paranoia and not root" return fi - perf stat -j --per-thread -a true 2>&1 | $PYTHON $pythonchecker --per-thread + perf stat -j --per-thread -a -o "${stat_output}" true + $PYTHON $pythonchecker --per-thread --file "${stat_output}" echo "[Success]" } @@ -108,7 +128,8 @@ check_per_die() echo "[Skip] paranoia and not root" return fi - perf stat -j --per-die -a true 2>&1 | $PYTHON $pythonchecker --per-die + perf stat -j --per-die -a -o "${stat_output}" true + $PYTHON $pythonchecker --per-die --file "${stat_output}" echo "[Success]" } @@ -120,7 +141,8 @@ check_per_node() echo "[Skip] paranoia and not root" return fi - perf stat -j --per-node -a true 2>&1 | $PYTHON $pythonchecker --per-node + perf stat -j --per-node -a -o "${stat_output}" true + $PYTHON $pythonchecker --per-node --file "${stat_output}" echo "[Success]" } @@ -132,7 +154,8 @@ check_per_socket() echo "[Skip] paranoia and not root" return fi - perf stat -j --per-socket -a true 2>&1 | $PYTHON $pythonchecker --per-socket + perf stat -j --per-socket -a -o "${stat_output}" true + $PYTHON $pythonchecker --per-socket --file "${stat_output}" echo "[Success]" } @@ -179,4 +202,5 @@ then else echo "[Skip] Skipping tests for system_wide_no_aggr, per_core, per_die and per_socket since socket id exposed via topology is invalid" fi +cleanup exit 0 -- cgit v1.2.3-58-ga151 From cd8ef949203c0fe88b031530cb5b63afd582e0f7 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 10 Apr 2023 09:25:06 -0700 Subject: perf ui: Move window resize signal functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move under tools/perf/ui rather than in perf.c. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Athira Rajeev Cc: Chengdong Li Cc: Denis Nikitin Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Martin Liška Cc: Mathieu Poirier Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Raul Silvera Cc: Ravi Bangoria Cc: Rob Herring Cc: Sean Christopherson Cc: Suzuki Poulouse Cc: Will Deacon Cc: Xing Zhengjun Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230410162511.3055900-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/perf.c | 18 ------------------ tools/perf/perf.h | 2 -- tools/perf/ui/setup.c | 19 +++++++++++++++++++ tools/perf/ui/tui/setup.c | 1 - tools/perf/ui/ui.h | 3 +++ 5 files changed, 22 insertions(+), 21 deletions(-) (limited to 'tools') diff --git a/tools/perf/perf.c b/tools/perf/perf.c index 82bbe0ca858b..4b1b31e78332 100644 --- a/tools/perf/perf.c +++ b/tools/perf/perf.c @@ -432,24 +432,6 @@ static int run_argv(int *argcp, const char ***argv) return 0; } -static void pthread__block_sigwinch(void) -{ - sigset_t set; - - sigemptyset(&set); - sigaddset(&set, SIGWINCH); - pthread_sigmask(SIG_BLOCK, &set, NULL); -} - -void pthread__unblock_sigwinch(void) -{ - sigset_t set; - - sigemptyset(&set); - sigaddset(&set, SIGWINCH); - pthread_sigmask(SIG_UNBLOCK, &set, NULL); -} - static int libperf_print(enum libperf_print_level level, const char *fmt, va_list ap) { diff --git a/tools/perf/perf.h b/tools/perf/perf.h index 74014033df60..e21a7e15a34c 100644 --- a/tools/perf/perf.h +++ b/tools/perf/perf.h @@ -12,8 +12,6 @@ extern const char *input_name; extern bool perf_host, perf_guest; extern const char perf_version_string[]; -void pthread__unblock_sigwinch(void); - enum perf_affinity { PERF_AFFINITY_SYS = 0, PERF_AFFINITY_NODE, diff --git a/tools/perf/ui/setup.c b/tools/perf/ui/setup.c index 25ded88801a3..ff800047e697 100644 --- a/tools/perf/ui/setup.c +++ b/tools/perf/ui/setup.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include +#include #include #include @@ -120,3 +121,21 @@ void exit_browser(bool wait_for_ok) } mutex_destroy(&ui__lock); } + +void pthread__block_sigwinch(void) +{ + sigset_t set; + + sigemptyset(&set); + sigaddset(&set, SIGWINCH); + pthread_sigmask(SIG_BLOCK, &set, NULL); +} + +void pthread__unblock_sigwinch(void) +{ + sigset_t set; + + sigemptyset(&set); + sigaddset(&set, SIGWINCH); + pthread_sigmask(SIG_UNBLOCK, &set, NULL); +} diff --git a/tools/perf/ui/tui/setup.c b/tools/perf/ui/tui/setup.c index a3b8c397c24d..c1886aa184b3 100644 --- a/tools/perf/ui/tui/setup.c +++ b/tools/perf/ui/tui/setup.c @@ -9,7 +9,6 @@ #endif #include "../../util/debug.h" -#include "../../perf.h" #include "../browser.h" #include "../helpline.h" #include "../ui.h" diff --git a/tools/perf/ui/ui.h b/tools/perf/ui/ui.h index 99f8d2fe9bc5..d8e911205582 100644 --- a/tools/perf/ui/ui.h +++ b/tools/perf/ui/ui.h @@ -31,4 +31,7 @@ struct option; int stdio__config_color(const struct option *opt, const char *mode, int unset); +void pthread__block_sigwinch(void); +void pthread__unblock_sigwinch(void); + #endif /* _PERF_UI_H_ */ -- cgit v1.2.3-58-ga151 From 0adea51ab2e6a0d9c8336673c7c07abb7a8b858a Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 10 Apr 2023 09:25:07 -0700 Subject: perf usage: Move usage strings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The usage function is part of util.h, move the usage strings there too. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Athira Rajeev Cc: Chengdong Li Cc: Denis Nikitin Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Martin Liška Cc: Mathieu Poirier Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Raul Silvera Cc: Ravi Bangoria Cc: Rob Herring Cc: Sean Christopherson Cc: Suzuki Poulouse Cc: Will Deacon Cc: Xing Zhengjun Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230410162511.3055900-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-help.c | 1 + tools/perf/builtin.h | 3 --- tools/perf/perf.c | 6 ------ tools/perf/util/usage.c | 6 ++++++ tools/perf/util/util.h | 3 +++ 5 files changed, 10 insertions(+), 9 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-help.c b/tools/perf/builtin-help.c index 3976aebe3677..3e7f52054fac 100644 --- a/tools/perf/builtin-help.c +++ b/tools/perf/builtin-help.c @@ -14,6 +14,7 @@ #include #include #include "util/debug.h" +#include "util/util.h" #include #include #include diff --git a/tools/perf/builtin.h b/tools/perf/builtin.h index d03afea86217..f2ab5bae2150 100644 --- a/tools/perf/builtin.h +++ b/tools/perf/builtin.h @@ -2,9 +2,6 @@ #ifndef BUILTIN_H #define BUILTIN_H -extern const char perf_usage_string[]; -extern const char perf_more_info_string[]; - void list_common_cmds_help(void); const char *help_unknown_cmd(const char *cmd); diff --git a/tools/perf/perf.c b/tools/perf/perf.c index 4b1b31e78332..997bb9ea5ebc 100644 --- a/tools/perf/perf.c +++ b/tools/perf/perf.c @@ -39,12 +39,6 @@ #include #include -const char perf_usage_string[] = - "perf [--version] [--help] [OPTIONS] COMMAND [ARGS]"; - -const char perf_more_info_string[] = - "See 'perf help COMMAND' for more information on a specific command."; - static int use_pager = -1; const char *input_name; diff --git a/tools/perf/util/usage.c b/tools/perf/util/usage.c index 196438ee4c9d..4c8ffbad2323 100644 --- a/tools/perf/util/usage.c +++ b/tools/perf/util/usage.c @@ -12,6 +12,12 @@ #include #include +const char perf_usage_string[] = + "perf [--version] [--help] [OPTIONS] COMMAND [ARGS]"; + +const char perf_more_info_string[] = + "See 'perf help COMMAND' for more information on a specific command."; + static __noreturn void usage_builtin(const char *err) { fprintf(stderr, "\n Usage: %s\n", err); diff --git a/tools/perf/util/util.h b/tools/perf/util/util.h index 1d3b300af5a1..5010abf9e01e 100644 --- a/tools/perf/util/util.h +++ b/tools/perf/util/util.h @@ -15,6 +15,9 @@ #include #endif +extern const char perf_usage_string[]; +extern const char perf_more_info_string[]; + /* General helper functions */ void usage(const char *err) __noreturn; void die(const char *err, ...) __noreturn __printf(1, 2); -- cgit v1.2.3-58-ga151 From 8641661cb7ee90f623276511ddb9ba901b15f904 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 10 Apr 2023 09:25:08 -0700 Subject: perf header: Move perf_version_string declaration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move to match the definition in header.c. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Athira Rajeev Cc: Chengdong Li Cc: Denis Nikitin Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Martin Liška Cc: Mathieu Poirier Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Raul Silvera Cc: Ravi Bangoria Cc: Rob Herring Cc: Sean Christopherson Cc: Suzuki Poulouse Cc: Will Deacon Cc: Xing Zhengjun Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230410162511.3055900-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-version.c | 2 +- tools/perf/perf.h | 1 - tools/perf/util/header.h | 2 ++ 3 files changed, 3 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-version.c b/tools/perf/builtin-version.c index c5d03a11e565..4a43043ca8ef 100644 --- a/tools/perf/builtin-version.c +++ b/tools/perf/builtin-version.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "builtin.h" -#include "perf.h" #include "color.h" +#include "util/header.h" #include #include #include diff --git a/tools/perf/perf.h b/tools/perf/perf.h index e21a7e15a34c..20e9b93f8a39 100644 --- a/tools/perf/perf.h +++ b/tools/perf/perf.h @@ -10,7 +10,6 @@ extern const char *input_name; extern bool perf_host, perf_guest; -extern const char perf_version_string[]; enum perf_affinity { PERF_AFFINITY_SYS = 0, diff --git a/tools/perf/util/header.h b/tools/perf/util/header.h index e3861ae62172..59eeb4a32ac5 100644 --- a/tools/perf/util/header.h +++ b/tools/perf/util/header.h @@ -115,6 +115,8 @@ struct perf_session; struct perf_tool; union perf_event; +extern const char perf_version_string[]; + int perf_session__read_header(struct perf_session *session, int repipe_fd); int perf_session__write_header(struct perf_session *session, struct evlist *evlist, -- cgit v1.2.3-58-ga151 From 2176f9e21cc5cf4c1e7c9f5772625755dcb32d7b Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 10 Apr 2023 09:25:09 -0700 Subject: perf version: Use regular verbose flag MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove additional version_verbose flag by using the existing verbose variable. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Athira Rajeev Cc: Chengdong Li Cc: Denis Nikitin Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Martin Liška Cc: Mathieu Poirier Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Raul Silvera Cc: Ravi Bangoria Cc: Rob Herring Cc: Sean Christopherson Cc: Suzuki Poulouse Cc: Will Deacon Cc: Xing Zhengjun Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230410162511.3055900-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-version.c | 5 ++--- tools/perf/perf.c | 2 +- tools/perf/perf.h | 1 - 3 files changed, 3 insertions(+), 5 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-version.c b/tools/perf/builtin-version.c index 4a43043ca8ef..1872c90a6667 100644 --- a/tools/perf/builtin-version.c +++ b/tools/perf/builtin-version.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "builtin.h" #include "color.h" +#include "util/debug.h" #include "util/header.h" #include #include @@ -8,8 +9,6 @@ #include #include -int version_verbose; - struct version { bool build_options; }; @@ -92,7 +91,7 @@ int cmd_version(int argc, const char **argv) printf("perf version %s\n", perf_version_string); - if (version.build_options || version_verbose == 1) + if (version.build_options || verbose > 0) library_status(); return 0; diff --git a/tools/perf/perf.c b/tools/perf/perf.c index 997bb9ea5ebc..441c354b8304 100644 --- a/tools/perf/perf.c +++ b/tools/perf/perf.c @@ -212,7 +212,7 @@ static int handle_options(const char ***argv, int *argc, int *envchanged) if (!strcmp(cmd, "-vv")) { (*argv)[0] = "version"; - version_verbose = 1; + verbose = 1; break; } diff --git a/tools/perf/perf.h b/tools/perf/perf.h index 20e9b93f8a39..989eb17ec474 100644 --- a/tools/perf/perf.h +++ b/tools/perf/perf.h @@ -18,5 +18,4 @@ enum perf_affinity { PERF_AFFINITY_MAX }; -extern int version_verbose; #endif -- cgit v1.2.3-58-ga151 From f12ad2727bbed890cbc2890470fb00c95b089b28 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 10 Apr 2023 09:25:10 -0700 Subject: perf util: Move input_name to util MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 'input_name' is the name of the input perf.data file, it is used by data convert and ui code. Move it to util to make it more consistent with other global state. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Athira Rajeev Cc: Chengdong Li Cc: Denis Nikitin Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Martin Liška Cc: Mathieu Poirier Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Raul Silvera Cc: Ravi Bangoria Cc: Rob Herring Cc: Sean Christopherson Cc: Suzuki Poulouse Cc: Will Deacon Cc: Xing Zhengjun Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230410162511.3055900-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-annotate.c | 2 +- tools/perf/builtin-buildid-list.c | 2 +- tools/perf/builtin-c2c.c | 2 +- tools/perf/builtin-data.c | 2 +- tools/perf/builtin-evlist.c | 2 +- tools/perf/builtin-kmem.c | 2 +- tools/perf/builtin-kwork.c | 2 +- tools/perf/builtin-mem.c | 2 +- tools/perf/builtin-sched.c | 2 +- tools/perf/builtin-stat.c | 2 +- tools/perf/builtin-timechart.c | 2 +- tools/perf/perf.c | 1 - tools/perf/perf.h | 1 - tools/perf/ui/browsers/hists.c | 2 +- tools/perf/util/util.c | 2 ++ tools/perf/util/util.h | 2 ++ 16 files changed, 16 insertions(+), 14 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-annotate.c b/tools/perf/builtin-annotate.c index 63fd2080b803..63cdf6ea6f6d 100644 --- a/tools/perf/builtin-annotate.c +++ b/tools/perf/builtin-annotate.c @@ -15,7 +15,6 @@ #include #include "util/symbol.h" -#include "perf.h" #include "util/debug.h" #include "util/evlist.h" @@ -36,6 +35,7 @@ #include "util/block-range.h" #include "util/map_symbol.h" #include "util/branch.h" +#include "util/util.h" #include #include diff --git a/tools/perf/builtin-buildid-list.c b/tools/perf/builtin-buildid-list.c index eea28cbcc0b7..c9037477865a 100644 --- a/tools/perf/builtin-buildid-list.c +++ b/tools/perf/builtin-buildid-list.c @@ -8,7 +8,6 @@ * Copyright (C) 2009, Arnaldo Carvalho de Melo */ #include "builtin.h" -#include "perf.h" #include "util/build-id.h" #include "util/debug.h" #include "util/dso.h" @@ -18,6 +17,7 @@ #include "util/session.h" #include "util/symbol.h" #include "util/data.h" +#include "util/util.h" #include #include #include diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c index d3181fee4d3d..6c12f0865860 100644 --- a/tools/perf/builtin-c2c.c +++ b/tools/perf/builtin-c2c.c @@ -41,10 +41,10 @@ #include "symbol.h" #include "ui/ui.h" #include "ui/progress.h" -#include "../perf.h" #include "pmu.h" #include "pmu-hybrid.h" #include "string2.h" +#include "util/util.h" struct c2c_hists { struct hists hists; diff --git a/tools/perf/builtin-data.c b/tools/perf/builtin-data.c index b2a9a3b7f68d..ce51cbf6dc97 100644 --- a/tools/perf/builtin-data.c +++ b/tools/perf/builtin-data.c @@ -3,10 +3,10 @@ #include #include #include "builtin.h" -#include "perf.h" #include "debug.h" #include #include "data-convert.h" +#include "util/util.h" typedef int (*data_cmd_fn_t)(int argc, const char **argv); diff --git a/tools/perf/builtin-evlist.c b/tools/perf/builtin-evlist.c index b1076177c37f..7117656939e7 100644 --- a/tools/perf/builtin-evlist.c +++ b/tools/perf/builtin-evlist.c @@ -7,7 +7,6 @@ #include -#include "perf.h" #include "util/evlist.h" #include "util/evsel.h" #include "util/evsel_fprintf.h" @@ -18,6 +17,7 @@ #include "util/debug.h" #include #include "util/tool.h" +#include "util/util.h" static int process_header_feature(struct perf_session *session __maybe_unused, union perf_event *event __maybe_unused) diff --git a/tools/perf/builtin-kmem.c b/tools/perf/builtin-kmem.c index fcd2ef3bd3f5..2150eeced892 100644 --- a/tools/perf/builtin-kmem.c +++ b/tools/perf/builtin-kmem.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 #include "builtin.h" -#include "perf.h" #include "util/dso.h" #include "util/evlist.h" @@ -24,6 +23,7 @@ #include "util/debug.h" #include "util/string2.h" +#include "util/util.h" #include #include diff --git a/tools/perf/builtin-kwork.c b/tools/perf/builtin-kwork.c index dc59d75180d1..a9395c52b23b 100644 --- a/tools/perf/builtin-kwork.c +++ b/tools/perf/builtin-kwork.c @@ -6,7 +6,6 @@ */ #include "builtin.h" -#include "perf.h" #include "util/data.h" #include "util/evlist.h" @@ -20,6 +19,7 @@ #include "util/string2.h" #include "util/callchain.h" #include "util/evsel_fprintf.h" +#include "util/util.h" #include #include diff --git a/tools/perf/builtin-mem.c b/tools/perf/builtin-mem.c index 1e27188b0de1..65465930ef8e 100644 --- a/tools/perf/builtin-mem.c +++ b/tools/perf/builtin-mem.c @@ -4,7 +4,6 @@ #include #include #include "builtin.h" -#include "perf.h" #include #include "util/auxtrace.h" @@ -22,6 +21,7 @@ #include "util/pmu-hybrid.h" #include "util/sample.h" #include "util/string2.h" +#include "util/util.h" #include #define MEM_OPERATION_LOAD 0x1 diff --git a/tools/perf/builtin-sched.c b/tools/perf/builtin-sched.c index 86e18575c9be..96a0dceadeff 100644 --- a/tools/perf/builtin-sched.c +++ b/tools/perf/builtin-sched.c @@ -1,6 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 #include "builtin.h" -#include "perf.h" #include "perf-sys.h" #include "util/cpumap.h" @@ -27,6 +26,7 @@ #include "util/debug.h" #include "util/event.h" +#include "util/util.h" #include #include diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index 40770926a230..d3cbee7460fc 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -41,7 +41,6 @@ */ #include "builtin.h" -#include "perf.h" #include "util/cgroup.h" #include #include "util/parse-events.h" @@ -71,6 +70,7 @@ #include "util/bpf_counter.h" #include "util/iostat.h" #include "util/pmu-hybrid.h" +#include "util/util.h" #include "asm/bug.h" #include diff --git a/tools/perf/builtin-timechart.c b/tools/perf/builtin-timechart.c index 6c629e7d370a..bce1cf896f9c 100644 --- a/tools/perf/builtin-timechart.c +++ b/tools/perf/builtin-timechart.c @@ -24,7 +24,6 @@ #include "util/thread.h" #include "util/callchain.h" -#include "perf.h" #include "util/header.h" #include #include @@ -37,6 +36,7 @@ #include "util/debug.h" #include "util/string2.h" #include "util/tracepoint.h" +#include "util/util.h" #include #include diff --git a/tools/perf/perf.c b/tools/perf/perf.c index 441c354b8304..38cae4721583 100644 --- a/tools/perf/perf.c +++ b/tools/perf/perf.c @@ -40,7 +40,6 @@ #include static int use_pager = -1; -const char *input_name; struct cmd_struct { const char *cmd; diff --git a/tools/perf/perf.h b/tools/perf/perf.h index 989eb17ec474..49e15e2be49e 100644 --- a/tools/perf/perf.h +++ b/tools/perf/perf.h @@ -8,7 +8,6 @@ #define MAX_NR_CPUS 2048 #endif -extern const char *input_name; extern bool perf_host, perf_guest; enum perf_affinity { diff --git a/tools/perf/ui/browsers/hists.c b/tools/perf/ui/browsers/hists.c index 9f9f622325ae..ab70e5f5fad2 100644 --- a/tools/perf/ui/browsers/hists.c +++ b/tools/perf/ui/browsers/hists.c @@ -29,8 +29,8 @@ #include "../../util/top.h" #include "../../util/thread.h" #include "../../util/block-info.h" +#include "../../util/util.h" #include "../../arch/common.h" -#include "../../perf.h" #include "../browsers/hists.h" #include "../helpline.h" diff --git a/tools/perf/util/util.c b/tools/perf/util/util.c index 089208b51e68..c1fd9ba6d697 100644 --- a/tools/perf/util/util.c +++ b/tools/perf/util/util.c @@ -28,6 +28,8 @@ * XXX We need to find a better place for these things... */ +const char *input_name; + bool perf_singlethreaded = true; void perf_set_singlethreaded(void) diff --git a/tools/perf/util/util.h b/tools/perf/util/util.h index 5010abf9e01e..8bd515b67739 100644 --- a/tools/perf/util/util.h +++ b/tools/perf/util/util.h @@ -18,6 +18,8 @@ extern const char perf_usage_string[]; extern const char perf_more_info_string[]; +extern const char *input_name; + /* General helper functions */ void usage(const char *err) __noreturn; void die(const char *err, ...) __noreturn __printf(1, 2); -- cgit v1.2.3-58-ga151 From ea0c52399d99d2e48cafdf97e2d8589bf8beb7c2 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 10 Apr 2023 09:25:11 -0700 Subject: perf util: Move perf_guest/host declarations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The definitions are in util.c so move the declarations to match. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Athira Rajeev Cc: Chengdong Li Cc: Denis Nikitin Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kan Liang Cc: Leo Yan Cc: Mark Rutland Cc: Martin Liška Cc: Mathieu Poirier Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Raul Silvera Cc: Ravi Bangoria Cc: Rob Herring Cc: Sean Christopherson Cc: Suzuki Poulouse Cc: Will Deacon Cc: Xing Zhengjun Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230410162511.3055900-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-diff.c | 2 +- tools/perf/builtin-kvm.c | 1 + tools/perf/perf.h | 4 ---- tools/perf/ui/hist.c | 2 +- tools/perf/util/cs-etm.c | 1 + tools/perf/util/event.c | 2 +- tools/perf/util/evlist.c | 1 + tools/perf/util/parse-events.c | 2 +- tools/perf/util/session.c | 2 +- tools/perf/util/top.c | 2 +- tools/perf/util/util.h | 3 +++ 11 files changed, 12 insertions(+), 10 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-diff.c b/tools/perf/builtin-diff.c index 22b526766e14..dbb0562d6a4f 100644 --- a/tools/perf/builtin-diff.c +++ b/tools/perf/builtin-diff.c @@ -6,7 +6,6 @@ * DSOs and symbol information, sort them and produce a diff. */ #include "builtin.h" -#include "perf.h" #include "util/debug.h" #include "util/event.h" @@ -26,6 +25,7 @@ #include "util/spark.h" #include "util/block-info.h" #include "util/stream.h" +#include "util/util.h" #include #include #include diff --git a/tools/perf/builtin-kvm.c b/tools/perf/builtin-kvm.c index fb9dc0dc46f9..747d19336340 100644 --- a/tools/perf/builtin-kvm.c +++ b/tools/perf/builtin-kvm.c @@ -23,6 +23,7 @@ #include "util/data.h" #include "util/ordered-events.h" #include "util/kvm-stat.h" +#include "util/util.h" #include "ui/browsers/hists.h" #include "ui/progress.h" #include "ui/ui.h" diff --git a/tools/perf/perf.h b/tools/perf/perf.h index 49e15e2be49e..c004dd4e65a3 100644 --- a/tools/perf/perf.h +++ b/tools/perf/perf.h @@ -2,14 +2,10 @@ #ifndef _PERF_PERF_H #define _PERF_PERF_H -#include - #ifndef MAX_NR_CPUS #define MAX_NR_CPUS 2048 #endif -extern bool perf_host, perf_guest; - enum perf_affinity { PERF_AFFINITY_SYS = 0, PERF_AFFINITY_NODE, diff --git a/tools/perf/ui/hist.c b/tools/perf/ui/hist.c index 5075ecead5f3..f164bd26fc41 100644 --- a/tools/perf/ui/hist.c +++ b/tools/perf/ui/hist.c @@ -11,7 +11,7 @@ #include "../util/sort.h" #include "../util/evsel.h" #include "../util/evlist.h" -#include "../perf.h" +#include "../util/util.h" /* hist period print (hpp) functions */ diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 944835e16430..103865968700 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -38,6 +38,7 @@ #include "tsc.h" #include #include "util/synthetic-events.h" +#include "util/util.h" struct cs_etm_auxtrace { struct auxtrace auxtrace; diff --git a/tools/perf/util/event.c b/tools/perf/util/event.c index 13f7f85e92e1..8ae742e32e3c 100644 --- a/tools/perf/util/event.c +++ b/tools/perf/util/event.c @@ -33,7 +33,7 @@ #include "bpf-event.h" #include "print_binary.h" #include "tool.h" -#include "../perf.h" +#include "util.h" static const char *perf_event__names[] = { [0] = "TOTAL", diff --git a/tools/perf/util/evlist.c b/tools/perf/util/evlist.c index cc491a037836..df6af38ca22e 100644 --- a/tools/perf/util/evlist.c +++ b/tools/perf/util/evlist.c @@ -32,6 +32,7 @@ #include "util/pmu.h" #include "util/sample.h" #include "util/bpf-filter.h" +#include "util/util.h" #include #include #include diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 0010e5e0ee68..f341995cb04e 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -25,10 +25,10 @@ #include "util/parse-branch-options.h" #include "util/evsel_config.h" #include "util/event.h" -#include "perf.h" #include "util/parse-events-hybrid.h" #include "util/pmu-hybrid.h" #include "util/bpf-filter.h" +#include "util/util.h" #include "tracepoint.h" #include "thread_map.h" diff --git a/tools/perf/util/session.c b/tools/perf/util/session.c index 7d8d057d1772..e2806791c76a 100644 --- a/tools/perf/util/session.c +++ b/tools/perf/util/session.c @@ -33,7 +33,7 @@ #include "stat.h" #include "tsc.h" #include "ui/progress.h" -#include "../perf.h" +#include "util.h" #include "arch/common.h" #include "units.h" #include diff --git a/tools/perf/util/top.c b/tools/perf/util/top.c index b8b32431d2f7..be7157de0451 100644 --- a/tools/perf/util/top.c +++ b/tools/perf/util/top.c @@ -11,7 +11,7 @@ #include "parse-events.h" #include "symbol.h" #include "top.h" -#include "../perf.h" +#include "util.h" #include #define SNPRINTF(buf, size, fmt, args...) \ diff --git a/tools/perf/util/util.h b/tools/perf/util/util.h index 8bd515b67739..7c8915d92dca 100644 --- a/tools/perf/util/util.h +++ b/tools/perf/util/util.h @@ -20,6 +20,9 @@ extern const char perf_more_info_string[]; extern const char *input_name; +extern bool perf_host; +extern bool perf_guest; + /* General helper functions */ void usage(const char *err) __noreturn; void die(const char *err, ...) __noreturn __printf(1, 2); -- cgit v1.2.3-58-ga151 From 51924ae69eea5bc90b5da525fbcf4bbd5f8551b3 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 10 Apr 2023 09:09:05 -0700 Subject: perf build: Warn for BPF skeletons if endian mismatches Done as a warning as I'm not fully confident of the test's robustness of comparing the macro definition of __BYTE_ORDER__. v2. Is a rebase following patch 1 being merged. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andrii Nakryiko Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230410160905.3052640-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Makefile.config | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) (limited to 'tools') diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index 16bea51f0bcd..71442c54c25f 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -663,14 +663,17 @@ ifndef NO_BPF_SKEL $(call feature_check,clang-bpf-co-re) ifeq ($(feature-clang-bpf-co-re), 0) dummy := $(error: ERROR: BPF skeletons unsupported. clang too old/not installed or build with NO_BPF_SKEL=1.) - else - ifeq ($(filter -DHAVE_LIBBPF_SUPPORT, $(CFLAGS)),) - dummy := $(error: ERROR: BPF skeletons unsupported. BPF skeleton support requires libbpf or build with NO_BPF_SKEL=1.) - else - $(call detected,CONFIG_PERF_BPF_SKEL) - CFLAGS += -DHAVE_BPF_SKEL - endif endif + ifeq ($(filter -DHAVE_LIBBPF_SUPPORT, $(CFLAGS)),) + dummy := $(error: ERROR: BPF skeletons unsupported. BPF skeleton support requires libbpf or build with NO_BPF_SKEL=1.) + endif + host_byte_order=$(echo ""|$(HOSTCC) -dM -E -|grep __BYTE_ORDER__) + target_byte_order=$(echo ""|$(CC) -dM -E -|grep __BYTE_ORDER__) + ifneq ($(host_byte_order), $(target_byte_order)) + $(warning Possibly mismatched host and target endianness may break BPF skeletons) + endif + $(call detected,CONFIG_PERF_BPF_SKEL) + CFLAGS += -DHAVE_BPF_SKEL endif dwarf-post-unwind := 1 -- cgit v1.2.3-58-ga151 From e0999b0e2149a0ec97f88547ab3658032d8ed70d Mon Sep 17 00:00:00 2001 From: Ravi Bangoria Date: Fri, 7 Apr 2023 16:54:54 +0530 Subject: tools include UAPI: Sync uapi/linux/perf_event.h with the kernel sources ... to bring PERF_MEM_LVLNUM_UNC definition to userspace Signed-off-by: Ravi Bangoria Acked-by: Namhyung Kim Cc: Adrian Hunter Cc: Ananth Narayan Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Peter Zijlstra Cc: Sandipan Das Cc: Santosh Shukla Cc: Stephane Eranian Link: https://lore.kernel.org/r/20230407112459.548-5-ravi.bangoria@amd.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/include/uapi/linux/perf_event.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/include/uapi/linux/perf_event.h b/tools/include/uapi/linux/perf_event.h index 37675437b768..39c6a250dd1b 100644 --- a/tools/include/uapi/linux/perf_event.h +++ b/tools/include/uapi/linux/perf_event.h @@ -1339,7 +1339,8 @@ union perf_mem_data_src { #define PERF_MEM_LVLNUM_L2 0x02 /* L2 */ #define PERF_MEM_LVLNUM_L3 0x03 /* L3 */ #define PERF_MEM_LVLNUM_L4 0x04 /* L4 */ -/* 5-0x8 available */ +/* 5-0x7 available */ +#define PERF_MEM_LVLNUM_UNC 0x08 /* Uncached */ #define PERF_MEM_LVLNUM_CXL 0x09 /* CXL */ #define PERF_MEM_LVLNUM_IO 0x0a /* I/O */ #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */ -- cgit v1.2.3-58-ga151 From fd359ec81399f5cec92ac774df1c3b95f4d699a6 Mon Sep 17 00:00:00 2001 From: Ravi Bangoria Date: Fri, 7 Apr 2023 16:54:55 +0530 Subject: perf mem: Add PERF_MEM_LVLNUM_NA to PERF_MEM_DATA_SRC_NONE Add PERF_MEM_LVLNUM_NA wherever PERF_MEM_DATA_SRC_NONE is used to set default values. Signed-off-by: Ravi Bangoria Acked-by: Namhyung Kim Cc: Adrian Hunter Cc: Ananth Narayan Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Peter Zijlstra Cc: Sandipan Das Cc: Santosh Shukla Cc: Stephane Eranian Link: https://lore.kernel.org/r/20230407112459.548-5-ravi.bangoria@amd.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/event.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/event.h b/tools/perf/util/event.h index 6663a676eadc..de20e01c9d72 100644 --- a/tools/perf/util/event.h +++ b/tools/perf/util/event.h @@ -89,7 +89,8 @@ enum { PERF_MEM_S(LVL, NA) |\ PERF_MEM_S(SNOOP, NA) |\ PERF_MEM_S(LOCK, NA) |\ - PERF_MEM_S(TLB, NA)) + PERF_MEM_S(TLB, NA) |\ + PERF_MEM_S(LVLNUM, NA)) /* Attribute type for custom synthesized events */ #define PERF_TYPE_SYNTH (INT_MAX + 1U) -- cgit v1.2.3-58-ga151 From d5fa7e9d0c13d67be30305dff689811478ae53cb Mon Sep 17 00:00:00 2001 From: Ravi Bangoria Date: Fri, 7 Apr 2023 16:54:56 +0530 Subject: perf mem: Add support for printing PERF_MEM_LVLNUM_UNC Add support for printing PERF_MEM_LVLNUM_UNC in perf mem report. Signed-off-by: Ravi Bangoria Acked-by: Namhyung Kim Cc: Adrian Hunter Cc: Ananth Narayan Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Peter Zijlstra Cc: Sandipan Das Cc: Santosh Shukla Cc: Stephane Eranian Link: https://lore.kernel.org/r/20230407112459.548-5-ravi.bangoria@amd.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/mem-events.c | 1 + 1 file changed, 1 insertion(+) (limited to 'tools') diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c index b3a91093069a..3a7c72be8326 100644 --- a/tools/perf/util/mem-events.c +++ b/tools/perf/util/mem-events.c @@ -295,6 +295,7 @@ static const char * const mem_lvl[] = { }; static const char * const mem_lvlnum[] = { + [PERF_MEM_LVLNUM_UNC] = "Uncached", [PERF_MEM_LVLNUM_CXL] = "CXL", [PERF_MEM_LVLNUM_IO] = "I/O", [PERF_MEM_LVLNUM_ANY_CACHE] = "Any cache", -- cgit v1.2.3-58-ga151 From ddeac198e1990715a162bf14faeab6000376ed1e Mon Sep 17 00:00:00 2001 From: Ravi Bangoria Date: Fri, 7 Apr 2023 16:54:57 +0530 Subject: perf mem: Refactor perf_mem__lvl_scnprintf() to process 'union perf_mem_data_src' more intuitively Interpretation of 'union perf_mem_data_src' by perf_mem__lvl_scnprintf() is non-intuitive. For ex, it ignores 'mem_lvl' when 'mem_hops' is set but considers it otherwise. It prints both 'mem_lvl_num' and 'mem_lvl' when 'mem_hops' is not set. Refactor this function such that it behaves more intuitively: Use new API 'mem_lvl_num'|'mem_remote'|'mem_hops' if 'mem_lvl_num' contains value other than PERF_MEM_LVLNUM_NA. Otherwise, fallback to old API 'mem_lvl'. Since new API has no way to indicate MISS, use it from old api, otherwise don't club old and new APIs while parsing as well as printing. Before: $ sudo ./perf mem report -F sample,mem --stdio # Samples Memory access # ............ ........................ # 250097 N/A 188907 L1 hit 4116 L2 hit 3496 Remote Cache (1 hop) hit 3271 Remote Cache (2 hops) hit 873 L3 hit 598 Local RAM hit 438 Remote RAM (1 hop) hit 1 Uncached hit After: $ sudo ./perf mem report -F sample,mem --stdio # Samples Memory access # ............ ....................................... # 255517 N/A 189989 L1 hit 4541 L2 hit 3363 Remote core, same node Any cache hit 3336 Remote node, same socket Any cache hit 1275 L3 hit 743 RAM hit 545 Remote node, same socket RAM hit 4 Uncached hit Signed-off-by: Ravi Bangoria Acked-by: Namhyung Kim Cc: Adrian Hunter Cc: Ananth Narayan Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Peter Zijlstra Cc: Sandipan Das Cc: Santosh Shukla Cc: Stephane Eranian Link: https://lore.kernel.org/r/20230407112459.548-5-ravi.bangoria@amd.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/mem-events.c | 89 +++++++++++++++++++++++--------------------- 1 file changed, 47 insertions(+), 42 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c index 3a7c72be8326..ed1ee4b05356 100644 --- a/tools/perf/util/mem-events.c +++ b/tools/perf/util/mem-events.c @@ -344,66 +344,71 @@ static int perf_mem__op_scnprintf(char *out, size_t sz, struct mem_info *mem_inf int perf_mem__lvl_scnprintf(char *out, size_t sz, struct mem_info *mem_info) { - size_t i, l = 0; - u64 m = PERF_MEM_LVL_NA; - u64 hit, miss; + union perf_mem_data_src data_src; int printed = 0; - - if (mem_info) - m = mem_info->data_src.mem_lvl; + size_t l = 0; + size_t i; + int lvl; + char hit_miss[5] = {0}; sz -= 1; /* -1 for null termination */ out[0] = '\0'; - hit = m & PERF_MEM_LVL_HIT; - miss = m & PERF_MEM_LVL_MISS; + if (!mem_info) + goto na; - /* already taken care of */ - m &= ~(PERF_MEM_LVL_HIT|PERF_MEM_LVL_MISS); + data_src = mem_info->data_src; - if (mem_info && mem_info->data_src.mem_remote) { - strcat(out, "Remote "); - l += 7; - } + if (data_src.mem_lvl & PERF_MEM_LVL_HIT) + memcpy(hit_miss, "hit", 3); + else if (data_src.mem_lvl & PERF_MEM_LVL_MISS) + memcpy(hit_miss, "miss", 4); - /* - * Incase mem_hops field is set, we can skip printing data source via - * PERF_MEM_LVL namespace. - */ - if (mem_info && mem_info->data_src.mem_hops) { - l += scnprintf(out + l, sz - l, "%s ", mem_hops[mem_info->data_src.mem_hops]); - } else { - for (i = 0; m && i < ARRAY_SIZE(mem_lvl); i++, m >>= 1) { - if (!(m & 0x1)) - continue; - if (printed++) { - strcat(out, " or "); - l += 4; - } - l += scnprintf(out + l, sz - l, mem_lvl[i]); + lvl = data_src.mem_lvl_num; + if (lvl && lvl != PERF_MEM_LVLNUM_NA) { + if (data_src.mem_remote) { + strcat(out, "Remote "); + l += 7; } + + if (data_src.mem_hops) + l += scnprintf(out + l, sz - l, "%s ", mem_hops[data_src.mem_hops]); + + if (mem_lvlnum[lvl]) + l += scnprintf(out + l, sz - l, mem_lvlnum[lvl]); + else + l += scnprintf(out + l, sz - l, "L%d", lvl); + + l += scnprintf(out + l, sz - l, " %s", hit_miss); + return l; } - if (mem_info && mem_info->data_src.mem_lvl_num) { - int lvl = mem_info->data_src.mem_lvl_num; + lvl = data_src.mem_lvl; + if (!lvl) + goto na; + + lvl &= ~(PERF_MEM_LVL_NA | PERF_MEM_LVL_HIT | PERF_MEM_LVL_MISS); + if (!lvl) + goto na; + + for (i = 0; lvl && i < ARRAY_SIZE(mem_lvl); i++, lvl >>= 1) { + if (!(lvl & 0x1)) + continue; if (printed++) { strcat(out, " or "); l += 4; } - if (mem_lvlnum[lvl]) - l += scnprintf(out + l, sz - l, mem_lvlnum[lvl]); - else - l += scnprintf(out + l, sz - l, "L%d", lvl); + l += scnprintf(out + l, sz - l, mem_lvl[i]); } - if (l == 0) - l += scnprintf(out + l, sz - l, "N/A"); - if (hit) - l += scnprintf(out + l, sz - l, " hit"); - if (miss) - l += scnprintf(out + l, sz - l, " miss"); + if (printed) { + l += scnprintf(out + l, sz - l, " %s", hit_miss); + return l; + } - return l; +na: + strcat(out, "N/A"); + return 3; } static const char * const snoop_access[] = { -- cgit v1.2.3-58-ga151 From 4953c8979d19a34fa98f4e8e55eae603cffe128a Mon Sep 17 00:00:00 2001 From: Ravi Bangoria Date: Fri, 7 Apr 2023 16:54:58 +0530 Subject: perf mem: Increase HISTC_MEM_LVL column size to 39 chars 39 is taken from the length of longest printable new API string: "Remote socket, same board Any cache hit". Although, using old API can result into even longer strings, let's not overkill by making it dynamic length. Signed-off-by: Ravi Bangoria Acked-by: Namhyung Kim Cc: Adrian Hunter Cc: Ananth Narayan Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Peter Zijlstra Cc: Sandipan Das Cc: Santosh Shukla Cc: Stephane Eranian Link: https://lore.kernel.org/r/20230407112459.548-5-ravi.bangoria@amd.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/hist.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/hist.c b/tools/perf/util/hist.c index 51020da15ffc..3c9301a26dfc 100644 --- a/tools/perf/util/hist.c +++ b/tools/perf/util/hist.c @@ -208,7 +208,7 @@ void hists__calc_col_len(struct hists *hists, struct hist_entry *h) hists__new_col_len(hists, HISTC_MEM_LOCKED, 6); hists__new_col_len(hists, HISTC_MEM_TLB, 22); hists__new_col_len(hists, HISTC_MEM_SNOOP, 12); - hists__new_col_len(hists, HISTC_MEM_LVL, 21 + 3); + hists__new_col_len(hists, HISTC_MEM_LVL, 36 + 3); hists__new_col_len(hists, HISTC_LOCAL_WEIGHT, 12); hists__new_col_len(hists, HISTC_GLOBAL_WEIGHT, 12); hists__new_col_len(hists, HISTC_MEM_BLOCKED, 10); -- cgit v1.2.3-58-ga151 From 3d3a3a49e20f006fa88e4fec5ad236864faa3a35 Mon Sep 17 00:00:00 2001 From: Ravi Bangoria Date: Fri, 7 Apr 2023 16:54:59 +0530 Subject: perf script ibs: Change bit description according to latest AMD PPR ("Processor Programming Reference") Some of the IBS_OP_DATA2 bit descriptions were stale (taken from old version of PPR). Change it according to latest PPR. Signed-off-by: Ravi Bangoria Acked-by: Namhyung Kim Cc: Adrian Hunter Cc: Ananth Narayan Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Peter Zijlstra Cc: Sandipan Das Cc: Santosh Shukla Cc: Stephane Eranian Link: https://lore.kernel.org/r/20230407112459.548-5-ravi.bangoria@amd.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/amd-sample-raw.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/amd-sample-raw.c b/tools/perf/util/amd-sample-raw.c index b0e70ce9d87a..6a6ddba76c75 100644 --- a/tools/perf/util/amd-sample-raw.c +++ b/tools/perf/util/amd-sample-raw.c @@ -105,17 +105,17 @@ static void pr_ibs_op_data2_extended(union ibs_op_data2 reg) static const char * const data_src_str[] = { "", " DataSrc 1=Local L3 or other L1/L2 in CCX", - " DataSrc 2=A peer cache in a near CCX", - " DataSrc 3=Data returned from DRAM", + " DataSrc 2=Another CCX cache in the same NUMA node", + " DataSrc 3=DRAM", " DataSrc 4=(reserved)", - " DataSrc 5=A peer cache in a far CCX", - " DataSrc 6=DRAM address map with \"long latency\" bit set", - " DataSrc 7=Data returned from MMIO/Config/PCI/APIC", - " DataSrc 8=Extension Memory (S-Link, GenZ, etc)", + " DataSrc 5=Another CCX cache in a different NUMA node", + " DataSrc 6=Long-latency DIMM", + " DataSrc 7=MMIO/Config/PCI/APIC", + " DataSrc 8=Extension Memory", " DataSrc 9=(reserved)", " DataSrc 10=(reserved)", " DataSrc 11=(reserved)", - " DataSrc 12=Peer Agent Memory", + " DataSrc 12=Coherent Memory of a different processor type", /* 13 to 31 are reserved. Avoid printing them. */ }; int data_src = (reg.data_src_hi << 3) | reg.data_src_lo; -- cgit v1.2.3-58-ga151 From cf57cf51d7c63595a50359694537b41aa05dda7e Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 10 Apr 2023 13:56:59 -0700 Subject: perf evsel: Avoid SEGV if delete is called on NULL Seen in "perf stat --bpf-counters --for-each-cgroup test" running in a container: libbpf: Failed to bump RLIMIT_MEMLOCK (err = -1), you might need to do it explicitly! libbpf: Error in bpf_object__probe_loading():Operation not permitted(1). Couldn't load trivial BPF program. Make sure your kernel supports BPF (CONFIG_BPF_SYSCALL=y) and/or that RLIMIT_MEMLOCK is set to big enough value. libbpf: failed to load object 'bperf_cgroup_bpf' libbpf: failed to load BPF skeleton 'bperf_cgroup_bpf': -1 Failed to load cgroup skeleton #0 0x55f28a650981 in list_empty tools/include/linux/list.h:189 #1 0x55f28a6593b4 in evsel__exit util/evsel.c:1518 #2 0x55f28a6596af in evsel__delete util/evsel.c:1544 #3 0x55f28a89d166 in bperf_cgrp__destroy util/bpf_counter_cgroup.c:283 #4 0x55f28a899e9a in bpf_counter__destroy util/bpf_counter.c:816 #5 0x55f28a659455 in evsel__exit util/evsel.c:1520 #6 0x55f28a6596af in evsel__delete util/evsel.c:1544 #7 0x55f28a640d4d in evlist__purge util/evlist.c:148 #8 0x55f28a640ea6 in evlist__delete util/evlist.c:169 #9 0x55f28a4efbf2 in cmd_stat tools/perf/builtin-stat.c:2598 #10 0x55f28a6050c2 in run_builtin tools/perf/perf.c:330 #11 0x55f28a605633 in handle_internal_command tools/perf/perf.c:384 #12 0x55f28a6059fb in run_argv tools/perf/perf.c:428 #13 0x55f28a6061d3 in main tools/perf/perf.c:562 Signed-off-by: Ian Rogers Acked-by: Namhyung Kim Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Florian Fischer Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230410205659.3131608-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/evsel.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'tools') diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index dc3faf005c3b..fe3ce765a4f3 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -1541,6 +1541,9 @@ void evsel__exit(struct evsel *evsel) void evsel__delete(struct evsel *evsel) { + if (!evsel) + return; + evsel__exit(evsel); free(evsel); } -- cgit v1.2.3-58-ga151 From e013733612854f446fae9193a42addfe7a926b9c Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 10 Apr 2023 22:17:18 -0700 Subject: perf bperf: Avoid use after free via unrelated 'struct evsel' anonymous union field If bperf (perf tools that use BPF skels) sets evsel->leader_skel or evsel->follower_skel then it appears that evsel->bpf_skel is set and can trigger the following use-after-free: ==13575==ERROR: AddressSanitizer: heap-use-after-free on address 0x60c000014080 at pc 0x55684b939880 bp 0x7ffdfcf30d70 sp 0x7ffdfcf30d68 READ of size 8 at 0x60c000014080 thread T0 #0 0x55684b93987f in sample_filter_bpf__destroy tools/perf/bpf_skel/sample_filter.skel.h:44:11 #1 0x55684b93987f in perf_bpf_filter__destroy tools/perf/util/bpf-filter.c:155:2 #2 0x55684b98f71e in evsel__exit tools/perf/util/evsel.c:1521:2 #3 0x55684b98a352 in evsel__delete tools/perf/util/evsel.c:1547:2 #4 0x55684b981918 in evlist__purge tools/perf/util/evlist.c:148:3 #5 0x55684b981918 in evlist__delete tools/perf/util/evlist.c:169:2 #6 0x55684b887d60 in cmd_stat tools/perf/builtin-stat.c:2598:2 .. 0x60c000014080 is located 0 bytes inside of 128-byte region [0x60c000014080,0x60c000014100) freed by thread T0 here: #0 0x55684b780e86 in free compiler-rt/lib/asan/asan_malloc_linux.cpp:52:3 #1 0x55684b9462da in bperf_cgroup_bpf__destroy tools/perf/bpf_skel/bperf_cgroup.skel.h:61:2 #2 0x55684b9462da in bperf_cgrp__destroy tools/perf/util/bpf_counter_cgroup.c:282:2 #3 0x55684b944c75 in bpf_counter__destroy tools/perf/util/bpf_counter.c:819:2 #4 0x55684b98f716 in evsel__exit tools/perf/util/evsel.c:1520:2 #5 0x55684b98a352 in evsel__delete tools/perf/util/evsel.c:1547:2 #6 0x55684b981918 in evlist__purge tools/perf/util/evlist.c:148:3 #7 0x55684b981918 in evlist__delete tools/perf/util/evlist.c:169:2 #8 0x55684b887d60 in cmd_stat tools/perf/builtin-stat.c:2598:2 ... previously allocated by thread T0 here: #0 0x55684b781338 in calloc compiler-rt/lib/asan/asan_malloc_linux.cpp:77:3 #1 0x55684b944e25 in bperf_cgroup_bpf__open_opts tools/perf/bpf_skel/bperf_cgroup.skel.h:73:35 #2 0x55684b944e25 in bperf_cgroup_bpf__open tools/perf/bpf_skel/bperf_cgroup.skel.h:97:9 #3 0x55684b944e25 in bperf_load_program tools/perf/util/bpf_counter_cgroup.c:55:9 #4 0x55684b944e25 in bperf_cgrp__load tools/perf/util/bpf_counter_cgroup.c:178:23 #5 0x55684b889289 in __run_perf_stat tools/perf/builtin-stat.c:713:7 #6 0x55684b889289 in run_perf_stat tools/perf/builtin-stat.c:949:8 #7 0x55684b888029 in cmd_stat tools/perf/builtin-stat.c:2537:12 Resolve by clearing 'evsel->bpf_skel' as part of bpf_counter__destroy(). Suggested-by: Namhyung Kim Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: bpf@vger.kernel.org Link: http://lore.kernel.org/lkml/20230411051718.267228-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/bpf_counter.c | 1 + 1 file changed, 1 insertion(+) (limited to 'tools') diff --git a/tools/perf/util/bpf_counter.c b/tools/perf/util/bpf_counter.c index 76ee3e86824a..6732cbbcf9b3 100644 --- a/tools/perf/util/bpf_counter.c +++ b/tools/perf/util/bpf_counter.c @@ -815,4 +815,5 @@ void bpf_counter__destroy(struct evsel *evsel) return; evsel->bpf_counter_ops->destroy(evsel); evsel->bpf_counter_ops = NULL; + evsel->bpf_skel = NULL; } -- cgit v1.2.3-58-ga151 From 588c8a2da99eac937069a4189eba9f375e38e592 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Tue, 11 Apr 2023 16:44:38 -0700 Subject: perf vendor events: Update alderlake to v1.20 Update from v1.19 to v1.20 affecting the performance/goldencove events. Adds cmask=1 for ARITH.IDIV_ACTIVE, and updates event descriptions. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230411234440.3313680-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/alderlake/other.json | 3 ++- tools/perf/pmu-events/arch/x86/alderlake/pipeline.json | 4 +++- tools/perf/pmu-events/arch/x86/mapfile.csv | 4 ++-- 3 files changed, 7 insertions(+), 4 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/alderlake/other.json b/tools/perf/pmu-events/arch/x86/alderlake/other.json index 329c611d7cf7..1db73e020215 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/other.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/other.json @@ -162,10 +162,11 @@ "Unit": "cpu_core" }, { - "BriefDescription": "XQ.FULL_CYCLES", + "BriefDescription": "Cycles the uncore cannot take further requests", "CounterMask": "1", "EventCode": "0x2d", "EventName": "XQ.FULL_CYCLES", + "PublicDescription": "number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache).", "SampleAfterValue": "1000003", "UMask": "0x1", "Unit": "cpu_core" diff --git a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json b/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json index f848530fbf07..cb5b8611064b 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json @@ -31,6 +31,7 @@ }, { "BriefDescription": "This event counts the cycles the integer divider is busy.", + "CounterMask": "1", "EventCode": "0xb0", "EventName": "ARITH.IDIV_ACTIVE", "SampleAfterValue": "1000003", @@ -1079,9 +1080,10 @@ "Unit": "cpu_core" }, { - "BriefDescription": "MISC2_RETIRED.LFENCE", + "BriefDescription": "LFENCE instructions retired", "EventCode": "0xe0", "EventName": "MISC2_RETIRED.LFENCE", + "PublicDescription": "number of LFENCE retired instructions", "SampleAfterValue": "400009", "UMask": "0x20", "Unit": "cpu_core" diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 97b3ffc284a6..9e7545d09b23 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -1,6 +1,6 @@ Family-model,Version,Filename,EventType -GenuineIntel-6-(97|9A|B7|BA|BF),v1.19,alderlake,core -GenuineIntel-6-BE,v1.19,alderlaken,core +GenuineIntel-6-(97|9A|B7|BA|BF),v1.20,alderlake,core +GenuineIntel-6-BE,v1.20,alderlaken,core GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core GenuineIntel-6-(3D|47),v27,broadwell,core GenuineIntel-6-56,v9,broadwellde,core -- cgit v1.2.3-58-ga151 From f00e589228d1d60a664dc13fef53acbde4a1d941 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Tue, 11 Apr 2023 16:44:39 -0700 Subject: perf vendor events: Update icelakex to v1.20 Update from v1.19 to v1.20 affecting the uncore UNC_CHA_CORE_SNP.REMOTE_GTONE event's umask. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230411234440.3313680-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json | 2 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json index 8210e286eec1..134b54da0869 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json @@ -981,7 +981,7 @@ "EventName": "UNC_CHA_CORE_SNP.REMOTE_GTONE", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Multiple Snoop Targets from Remote : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x22", + "UMask": "0x12", "Unit": "CHA" }, { diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 9e7545d09b23..58faf18474b5 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -13,7 +13,7 @@ GenuineIntel-6-A[DE],v1.01,graniterapids,core GenuineIntel-6-(3C|45|46),v33,haswell,core GenuineIntel-6-3F,v27,haswellx,core GenuineIntel-6-(7D|7E|A7),v1.17,icelake,core -GenuineIntel-6-6[AC],v1.19,icelakex,core +GenuineIntel-6-6[AC],v1.20,icelakex,core GenuineIntel-6-3A,v24,ivybridge,core GenuineIntel-6-3E,v23,ivytown,core GenuineIntel-6-2D,v23,jaketown,core -- cgit v1.2.3-58-ga151 From 79b40a1b182bcca381bb59d0219e1dd681a64981 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 12 Apr 2023 09:50:08 -0300 Subject: perf inject: Use zfree() to reduce chances of use after free Do defensive programming by using zfree() to initialize freed pointers to NULL, so that eventual use after free result in a NULL pointer deref instead of more subtle behaviour. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-inject.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-inject.c b/tools/perf/builtin-inject.c index fd2b38458a5d..76723ac314b6 100644 --- a/tools/perf/builtin-inject.c +++ b/tools/perf/builtin-inject.c @@ -1311,10 +1311,10 @@ static void guest_session__exit(struct guest_session *gs) if (gs->tmp_fd >= 0) close(gs->tmp_fd); unlink(gs->tmp_file_name); - free(gs->tmp_file_name); + zfree(&gs->tmp_file_name); } - free(gs->vcpu); - free(gs->perf_data_file); + zfree(&gs->vcpu); + zfree(&gs->perf_data_file); } static void get_tsc_conv(struct perf_tsc_conversion *tc, struct perf_record_time_conv *time_conv) -- cgit v1.2.3-58-ga151 From 789eae7f203edc1301d7122ad9b3046e7c56937c Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 12 Apr 2023 09:50:08 -0300 Subject: perf daemon: Use zfree() to reduce chances of use after free Do defensive programming by using zfree() to initialize freed pointers to NULL, so that eventual use after free result in a NULL pointer deref instead of more subtle behaviour. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-daemon.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-daemon.c b/tools/perf/builtin-daemon.c index 7036ec92d47d..34cbe3e959aa 100644 --- a/tools/perf/builtin-daemon.c +++ b/tools/perf/builtin-daemon.c @@ -193,7 +193,7 @@ static int session_config(struct daemon *daemon, const char *var, const char *va if (!same) { if (session->run) { - free(session->run); + zfree(&session->run); pr_debug("reconfig: session %s is changed\n", name); } @@ -924,9 +924,9 @@ static void daemon__signal(struct daemon *daemon, int sig) static void daemon_session__delete(struct daemon_session *session) { - free(session->base); - free(session->name); - free(session->run); + zfree(&session->base); + zfree(&session->name); + zfree(&session->run); free(session); } @@ -975,9 +975,9 @@ static void daemon__exit(struct daemon *daemon) list_for_each_entry_safe(session, h, &daemon->sessions, list) daemon_session__remove(session); - free(daemon->config_real); - free(daemon->config_base); - free(daemon->base); + zfree(&daemon->config_real); + zfree(&daemon->config_base); + zfree(&daemon->base); } static int daemon__reconfig(struct daemon *daemon) -- cgit v1.2.3-58-ga151 From 9997d5dd177c52017fa0541bf236a4232c8148e6 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 12 Apr 2023 09:50:08 -0300 Subject: perf trace: Use zfree() to reduce chances of use after free Do defensive programming by using zfree() to initialize freed pointers to NULL, so that eventual use after free result in a NULL pointer deref instead of more subtle behaviour. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-trace.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-trace.c b/tools/perf/builtin-trace.c index 72ef0bebb06b..8ee3a45c3c54 100644 --- a/tools/perf/builtin-trace.c +++ b/tools/perf/builtin-trace.c @@ -2288,7 +2288,7 @@ static void syscall__exit(struct syscall *sc) if (!sc) return; - free(sc->arg_fmt); + zfree(&sc->arg_fmt); } static int trace__sys_enter(struct trace *trace, struct evsel *evsel, @@ -3124,7 +3124,7 @@ static void evlist__free_syscall_tp_fields(struct evlist *evlist) if (!et || !evsel->tp_format || strcmp(evsel->tp_format->system, "syscalls")) continue; - free(et->fmt); + zfree(&et->fmt); free(et); } } @@ -4670,11 +4670,11 @@ static void trace__exit(struct trace *trace) int i; strlist__delete(trace->ev_qualifier); - free(trace->ev_qualifier_ids.entries); + zfree(&trace->ev_qualifier_ids.entries); if (trace->syscalls.table) { for (i = 0; i <= trace->sctbl->syscalls.max_id; i++) syscall__exit(&trace->syscalls.table[i]); - free(trace->syscalls.table); + zfree(&trace->syscalls.table); } syscalltbl__delete(trace->sctbl); zfree(&trace->perfconfig_events); -- cgit v1.2.3-58-ga151 From 190de75481439205f3a9362bd0511fd48ad1a718 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 12 Apr 2023 09:50:08 -0300 Subject: perf c2c: Use zfree() to reduce chances of use after free Do defensive programming by using zfree() to initialize freed pointers to NULL, so that eventual use after free result in a NULL pointer deref instead of more subtle behaviour. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-c2c.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c index 6c12f0865860..08455e26b606 100644 --- a/tools/perf/builtin-c2c.c +++ b/tools/perf/builtin-c2c.c @@ -165,8 +165,8 @@ static void *c2c_he_zalloc(size_t size) return &c2c_he->he; out_free: - free(c2c_he->nodeset); - free(c2c_he->cpuset); + zfree(&c2c_he->nodeset); + zfree(&c2c_he->cpuset); free(c2c_he); return NULL; } @@ -178,13 +178,13 @@ static void c2c_he_free(void *he) c2c_he = container_of(he, struct c2c_hist_entry, he); if (c2c_he->hists) { hists__delete_entries(&c2c_he->hists->hists); - free(c2c_he->hists); + zfree(&c2c_he->hists); } - free(c2c_he->cpuset); - free(c2c_he->nodeset); - free(c2c_he->nodestr); - free(c2c_he->node_stats); + zfree(&c2c_he->cpuset); + zfree(&c2c_he->nodeset); + zfree(&c2c_he->nodestr); + zfree(&c2c_he->node_stats); free(c2c_he); } -- cgit v1.2.3-58-ga151 From b20c63084eb2c591006109aefbdeb3cad7a57d23 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 12 Apr 2023 09:50:08 -0300 Subject: perf list: Use zfree() to reduce chances of use after free Do defensive programming by using zfree() to initialize freed pointers to NULL, so that eventual use after free result in a NULL pointer deref instead of more subtle behaviour. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-list.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-list.c b/tools/perf/builtin-list.c index 29f09cefed88..1f5dbd5f0ba4 100644 --- a/tools/perf/builtin-list.c +++ b/tools/perf/builtin-list.c @@ -127,7 +127,7 @@ static void default_print_event(void *ps, const char *pmu_name, const char *topi if (strcmp(print_state->last_topic, topic ?: "")) { if (topic) printf("\n%s:\n", topic); - free(print_state->last_topic); + zfree(&print_state->last_topic); print_state->last_topic = strdup(topic ?: ""); } @@ -197,7 +197,7 @@ static void default_print_metric(void *ps, else printf("%s\n", group); } - free(print_state->last_metricgroups); + zfree(&print_state->last_metricgroups); print_state->last_metricgroups = strdup(group ?: ""); } if (!print_state->metrics) -- cgit v1.2.3-58-ga151 From d729163d0641d8b4c50fdca1b2b9d5d24d9d376d Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 12 Apr 2023 09:50:08 -0300 Subject: perf symbol: Use zfree() to reduce chances of use after free Do defensive programming by using zfree() to initialize freed pointers to NULL, so that eventual use after free result in a NULL pointer deref instead of more subtle behaviour. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/symbol-elf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/symbol-elf.c b/tools/perf/util/symbol-elf.c index c55981116f68..35724f6a84fa 100644 --- a/tools/perf/util/symbol-elf.c +++ b/tools/perf/util/symbol-elf.c @@ -396,7 +396,7 @@ static bool get_ifunc_name(Elf *elf, struct dso *dso, GElf_Ehdr *ehdr, static void exit_rel(struct rel_info *ri) { - free(ri->sorted); + zfree(&ri->sorted); } static bool get_plt_sizes(struct dso *dso, GElf_Ehdr *ehdr, GElf_Shdr *shdr_plt, @@ -460,7 +460,7 @@ struct rela_dyn_info { static void exit_rela_dyn(struct rela_dyn_info *di) { - free(di->sorted); + zfree(&di->sorted); } static int cmp_offset(const void *a, const void *b) -- cgit v1.2.3-58-ga151 From 313b4c1ccdb273f6733e8c44948f8c7141f592a4 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 12 Apr 2023 09:50:08 -0300 Subject: perf x86 iostat: Use zfree() to reduce chances of use after free Do defensive programming by using zfree() to initialize freed pointers to NULL, so that eventual use after free result in a NULL pointer deref instead of more subtle behaviour. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/x86/util/iostat.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'tools') diff --git a/tools/perf/arch/x86/util/iostat.c b/tools/perf/arch/x86/util/iostat.c index 7eb0a7b00b95..df7b5dfcc26a 100644 --- a/tools/perf/arch/x86/util/iostat.c +++ b/tools/perf/arch/x86/util/iostat.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -100,8 +101,8 @@ static void iio_root_ports_list_free(struct iio_root_ports_list *list) if (list) { for (idx = 0; idx < list->nr_entries; idx++) - free(list->rps[idx]); - free(list->rps); + zfree(&list->rps[idx]); + zfree(&list->rps); free(list); } } @@ -390,7 +391,7 @@ void iostat_release(struct evlist *evlist) evlist__for_each_entry(evlist, evsel) { if (rp != evsel->priv) { rp = evsel->priv; - free(evsel->priv); + zfree(&evsel->priv); } } } -- cgit v1.2.3-58-ga151 From 9fbde6c8002bce61acd0c2187cc41c43a7c99968 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 12 Apr 2023 09:50:08 -0300 Subject: perf env: Use zfree() to reduce chances of use after free Do defensive programming by using zfree() to initialize freed pointers to NULL, so that eventual use after free result in a NULL pointer deref instead of more subtle behaviour. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/env.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/env.c b/tools/perf/util/env.c index 5b8cf6a421a4..ebf2e801c275 100644 --- a/tools/perf/util/env.c +++ b/tools/perf/util/env.c @@ -149,7 +149,7 @@ static void perf_env__purge_bpf(struct perf_env *env) node = rb_entry(next, struct bpf_prog_info_node, rb_node); next = rb_next(&node->rb_node); rb_erase(&node->rb_node, root); - free(node->info_linear); + zfree(&node->info_linear); free(node); } -- cgit v1.2.3-58-ga151 From efe98a7a39777ce266142159f303fb52c3b817c0 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 12 Apr 2023 09:50:08 -0300 Subject: perf pmu: Use zfree() to reduce chances of use after free Do defensive programming by using zfree() to initialize freed pointers to NULL, so that eventual use after free result in a NULL pointer deref instead of more subtle behaviour. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/pmu.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 91cccfb3c515..01533302d5f9 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -972,8 +972,7 @@ static struct perf_pmu *pmu_lookup(int dirfd, const char *lookup_name) return pmu; err: - if (pmu->name) - free(pmu->name); + zfree(&pmu->name); free(pmu); return NULL; } @@ -1519,7 +1518,7 @@ void perf_pmu__del_formats(struct list_head *formats) list_for_each_entry_safe(fmt, tmp, formats, list) { list_del(&fmt->list); - free(fmt->name); + zfree(&fmt->name); free(fmt); } } @@ -1866,8 +1865,8 @@ static void perf_pmu__del_caps(struct perf_pmu *pmu) list_for_each_entry_safe(caps, tmp, &pmu->caps, list) { list_del(&caps->list); - free(caps->name); - free(caps->value); + zfree(&caps->name); + zfree(&caps->value); free(caps); } } @@ -2089,9 +2088,9 @@ static void perf_pmu__delete(struct perf_pmu *pmu) perf_cpu_map__put(pmu->cpus); - free(pmu->default_config); - free(pmu->name); - free(pmu->alias_name); + zfree(&pmu->default_config); + zfree(&pmu->name); + zfree(&pmu->alias_name); free(pmu); } -- cgit v1.2.3-58-ga151 From cdf13c0918c9b1b233d6db690fc4c06afbc29e57 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 12 Apr 2023 09:50:08 -0300 Subject: perf evsel: Use zfree() to reduce chances of use after free Do defensive programming by using zfree() to initialize freed pointers to NULL, so that eventual use after free result in a NULL pointer deref instead of more subtle behaviour. Also remove one NULL test before free(), as it accepts a NULL arg and we get one line shaved not doing it explicitely. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/evsel.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index fe3ce765a4f3..a85a987128aa 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -2917,8 +2917,7 @@ bool evsel__fallback(struct evsel *evsel, int err, char *msg, size_t msgsize) if (asprintf(&new_name, "%s%su", name, sep) < 0) return false; - if (evsel->name) - free(evsel->name); + free(evsel->name); evsel->name = new_name; scnprintf(msg, msgsize, "kernel.perf_event_paranoid=%d, trying " "to fall back to excluding kernel and hypervisor " @@ -3156,7 +3155,7 @@ void evsel__zero_per_pkg(struct evsel *evsel) if (evsel->per_pkg_mask) { hashmap__for_each_entry(evsel->per_pkg_mask, cur, bkt) - free((void *)cur->pkey); + zfree(&cur->pkey); hashmap__clear(evsel->per_pkg_mask); } -- cgit v1.2.3-58-ga151 From a77f8184a07cbe81cdee30582640ed1b412705fc Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 12 Apr 2023 09:50:08 -0300 Subject: perf expr: Use zfree() to reduce chances of use after free Do defensive programming by using zfree() to initialize freed pointers to NULL, so that eventual use after free result in a NULL pointer deref instead of more subtle behaviour. Also remove one NULL test before free(), as it accepts a NULL arg and we get one line shaved not doing it explicitely. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/expr.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/expr.c b/tools/perf/util/expr.c index bb6ddad7e021..f4e52919324e 100644 --- a/tools/perf/util/expr.c +++ b/tools/perf/util/expr.c @@ -86,8 +86,8 @@ void ids__free(struct hashmap *ids) return; hashmap__for_each_entry(ids, cur, bkt) { - free((void *)cur->pkey); - free((void *)cur->pvalue); + zfree(&cur->pkey); + zfree(&cur->pvalue); } hashmap__free(ids); @@ -311,8 +311,8 @@ void expr__ctx_clear(struct expr_parse_ctx *ctx) size_t bkt; hashmap__for_each_entry(ctx->ids, cur, bkt) { - free((void *)cur->pkey); - free(cur->pvalue); + zfree(&cur->pkey); + zfree(&cur->pvalue); } hashmap__clear(ctx->ids); } @@ -325,10 +325,10 @@ void expr__ctx_free(struct expr_parse_ctx *ctx) if (!ctx) return; - free(ctx->sctx.user_requested_cpu_list); + zfree(&ctx->sctx.user_requested_cpu_list); hashmap__for_each_entry(ctx->ids, cur, bkt) { - free((void *)cur->pkey); - free(cur->pvalue); + zfree(&cur->pkey); + zfree(&cur->pvalue); } hashmap__free(ctx->ids); free(ctx); -- cgit v1.2.3-58-ga151 From 25feb605fe3b2674142d084379e0737a99945aba Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 12 Apr 2023 09:50:08 -0300 Subject: perf parse-events: Use zfree() to reduce chances of use after free Do defensive programming by using zfree() to initialize freed pointers to NULL, so that eventual use after free result in a NULL pointer deref instead of more subtle behaviour. Also remove one NULL test before free(), as it accepts a NULL arg and we get one line shaved not doing it explicitely. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/parse-events.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index f341995cb04e..d71019dcd614 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -2020,7 +2020,7 @@ int perf_pmu__test_parse_init(void) err_free: for (j = 0, tmp = list; j < i; j++, tmp++) - free(tmp->symbol); + zfree(&tmp->symbol); free(list); return -ENOMEM; } -- cgit v1.2.3-58-ga151 From c77ceb2eb03eefd92e6b84a509ecec1db8d97858 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 12 Apr 2023 09:50:08 -0300 Subject: perf annotate: Use zfree() to reduce chances of use after free Do defensive programming by using zfree() to initialize freed pointers to NULL, so that eventual use after free result in a NULL pointer deref instead of more subtle behaviour. Also include the missing linux/zalloc.h header directive. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/annotate.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/annotate.c b/tools/perf/util/annotate.c index 55f2e3a7577e..e2693a1c28d5 100644 --- a/tools/perf/util/annotate.c +++ b/tools/perf/util/annotate.c @@ -38,6 +38,7 @@ #include #include #include +#include #include #include @@ -1881,7 +1882,7 @@ symbol__disassemble_bpf_image(struct symbol *sym, if (dl) annotation_line__add(&dl->al, ¬es->src->source); - free(args->line); + zfree(&args->line); return 0; } -- cgit v1.2.3-58-ga151 From 2bfc8134f95852bd8b0190641c2d2b059cb1c8cc Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 12 Apr 2023 09:50:08 -0300 Subject: perf evlist: Use zfree() to reduce chances of use after free Do defensive programming by using zfree() to initialize freed pointers to NULL, so that eventual use after free result in a NULL pointer deref instead of more subtle behaviour. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/evlist.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/evlist.c b/tools/perf/util/evlist.c index df6af38ca22e..2260e27adf44 100644 --- a/tools/perf/util/evlist.c +++ b/tools/perf/util/evlist.c @@ -2325,7 +2325,7 @@ int evlist__parse_event_enable_time(struct evlist *evlist, struct record_opts *o close_timerfd: close(eet->timerfd); free_eet_times: - free(eet->times); + zfree(&eet->times); free_eet: free(eet); return err; @@ -2407,7 +2407,7 @@ void event_enable_timer__exit(struct event_enable_timer **ep) { if (!ep || !*ep) return; - free((*ep)->times); + zfree(&(*ep)->times); zfree(ep); } -- cgit v1.2.3-58-ga151 From e413f9f13f6a8a591af0ac39ef50af02b42a0df8 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 12 Apr 2023 09:50:08 -0300 Subject: perf genelf: Use zfree() to reduce chances of use after free Do defensive programming by using zfree() to initialize freed pointers to NULL, so that eventual use after free result in a NULL pointer deref instead of more subtle behaviour. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/genelf_debug.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/genelf_debug.c b/tools/perf/util/genelf_debug.c index 8786c366566e..aa5dcc56b2ac 100644 --- a/tools/perf/util/genelf_debug.c +++ b/tools/perf/util/genelf_debug.c @@ -11,6 +11,7 @@ * @author Philippe Elie */ #include +#include #include #include #include @@ -90,7 +91,7 @@ buffer_ext_init(struct buffer_ext *be) static void buffer_ext_exit(struct buffer_ext *be) { - free(be->data); + zfree(&be->data); } static inline size_t -- cgit v1.2.3-58-ga151 From 97d0dd1e283a9a11ede495928c9c2a148b47cef4 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 12 Apr 2023 09:50:08 -0300 Subject: perf bench inject-buildid: Use zfree() to reduce chances of use after free Do defensive programming by using zfree() to initialize freed pointers to NULL, so that eventual use after free result in a NULL pointer deref instead of more subtle behaviour. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/bench/inject-buildid.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/bench/inject-buildid.c b/tools/perf/bench/inject-buildid.c index 4561bda0ce6a..49331743c743 100644 --- a/tools/perf/bench/inject-buildid.c +++ b/tools/perf/bench/inject-buildid.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -122,7 +123,7 @@ static void release_dso(void) for (i = 0; i < nr_dsos; i++) { struct bench_dso *dso = &dsos[i]; - free(dso->name); + zfree(&dso->name); } free(dsos); } -- cgit v1.2.3-58-ga151 From 9ccbc21166ce149c5f7429cad22f9073d3fab0b1 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 12 Apr 2023 09:50:08 -0300 Subject: perf tests api-io: Use zfree() to reduce chances of use after free Do defensive programming by using zfree() to initialize freed pointers to NULL, so that eventual use after free result in a NULL pointer deref instead of more subtle behaviour. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/api-io.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/tests/api-io.c b/tools/perf/tests/api-io.c index 6aea84ca6673..0ba3d5ccebcf 100644 --- a/tools/perf/tests/api-io.c +++ b/tools/perf/tests/api-io.c @@ -12,6 +12,7 @@ #include "tests.h" #include #include +#include #define TEMPL "/tmp/perf-test-XXXXXX" @@ -79,7 +80,7 @@ static int setup_test(char path[PATH_MAX], const char *contents, static void cleanup_test(char path[PATH_MAX], struct io *io) { - free(io->buf); + zfree(&io->buf); close(io->fd); unlink(path); } -- cgit v1.2.3-58-ga151 From 2e384400549be734795072b1d904880efc0db2f9 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 12 Apr 2023 09:50:08 -0300 Subject: perf arm-spe: Use zfree() to reduce chances of use after free Do defensive programming by using zfree() to initialize freed pointers to NULL, so that eventual use after free result in a NULL pointer deref instead of more subtle behaviour. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/arm64/util/arm-spe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/arch/arm64/util/arm-spe.c b/tools/perf/arch/arm64/util/arm-spe.c index d4c234076541..ef497a29e814 100644 --- a/tools/perf/arch/arm64/util/arm-spe.c +++ b/tools/perf/arch/arm64/util/arm-spe.c @@ -479,7 +479,7 @@ static void arm_spe_recording_free(struct auxtrace_record *itr) struct arm_spe_recording *sper = container_of(itr, struct arm_spe_recording, itr); - free(sper->wrapped); + zfree(&sper->wrapped); free(sper); } -- cgit v1.2.3-58-ga151 From 11ff9bcd7dfeefa6a9a9fcd4c7775b8066c46a31 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 12 Apr 2023 09:50:08 -0300 Subject: perf metricgroups: Use zfree() to reduce chances of use after free Do defensive programming by using zfree() to initialize freed pointers to NULL, so that eventual use after free result in a NULL pointer deref instead of more subtle behaviour. This file already used zfree() in other places, so this just plugs some leftovers. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/metricgroup.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index 5783f4c2d1ef..4b9a16291b96 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -90,9 +90,9 @@ static void metric_event_delete(struct rblist *rblist __maybe_unused, struct metric_expr *expr, *tmp; list_for_each_entry_safe(expr, tmp, &me->head, nd) { - free((char *)expr->metric_name); - free(expr->metric_refs); - free(expr->metric_events); + zfree(&expr->metric_name); + zfree(&expr->metric_refs); + zfree(&expr->metric_events); free(expr); } @@ -192,9 +192,9 @@ static void metric__free(struct metric *m) if (!m) return; - free(m->metric_refs); + zfree(&m->metric_refs); expr__ctx_free(m->pctx); - free((char *)m->modifier); + zfree(&m->modifier); evlist__delete(m->evlist); free(m); } @@ -617,7 +617,7 @@ static int decode_all_metric_ids(struct evlist *perf_evlist, const char *modifie if (strstr(ev->name, "metric-id=")) { bool has_slash = false; - free(ev->name); + zfree(&ev->name); for (cur = strchr(sb.buf, '@') ; cur; cur = strchr(++cur, '@')) { *cur = '/'; has_slash = true; @@ -1760,7 +1760,7 @@ int metricgroup__copy_metric_events(struct evlist *evlist, struct cgroup *cgrp, alloc_size = sizeof(*new_expr->metric_events); new_expr->metric_events = calloc(nr + 1, alloc_size); if (!new_expr->metric_events) { - free(new_expr->metric_refs); + zfree(&new_expr->metric_refs); free(new_expr); return -ENOMEM; } @@ -1770,8 +1770,8 @@ int metricgroup__copy_metric_events(struct evlist *evlist, struct cgroup *cgrp, evsel = old_expr->metric_events[idx]; evsel = evlist__find_evsel(evlist, evsel->core.idx); if (evsel == NULL) { - free(new_expr->metric_events); - free(new_expr->metric_refs); + zfree(&new_expr->metric_events); + zfree(&new_expr->metric_refs); free(new_expr); return -EINVAL; } -- cgit v1.2.3-58-ga151 From 57f14b5ae1a97537f2abd2828ee7212cada7036e Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 12 Apr 2023 10:23:35 -0300 Subject: perf pmu: zfree() expects a pointer to a pointer to zero it after freeing its contents An audit showed just this one problem with zfree(), fix it. Fixes: 9fbc61f832ebf432 ("perf pmu: Add support for PMU capabilities") Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 01533302d5f9..561e2616861f 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -1852,7 +1852,7 @@ static int perf_pmu__new_caps(struct list_head *list, char *name, char *value) return 0; free_name: - zfree(caps->name); + zfree(&caps->name); free_caps: free(caps); -- cgit v1.2.3-58-ga151 From ed4da0d3de1e1781f8fbdc9cf1028b39cc658c7f Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Fri, 7 Apr 2023 10:21:30 +0800 Subject: tools headers: Remove s390 ptrace.h in check-headers.sh After commit 1f265d2aea0dff1f ("selftests/bpf: Remove not used headers"), tools/arch/s390/include/uapi/asm/ptrace.h has been removed, so remove it in check-headers.sh too, otherwise we can see the following build warning: diff: tools/arch/s390/include/uapi/asm/ptrace.h: No such file or directory Fixes: 1f265d2aea0dff1f ("selftests/bpf: Remove not used headers") Reported-by: kernel test robot Signed-off-by: Tiezhu Yang Acked-by: Daniel Borkmann Acked-by: Jiri Olsa Cc: Alexei Starovoitov Cc: Andrii Nakryiko Cc: Tiezhu Yang Cc: bpf@vger.kernel.org Cc: loongson-kernel@lists.loongnix.cn Link: https://lore.kernel.org/oe-kbuild-all/202304050029.38NdbQPf-lkp@intel.com/ Link: https://lore.kernel.org/r/1680834090-2322-1-git-send-email-yangtiezhu@loongson.cn Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/check-headers.sh | 1 - 1 file changed, 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/check-headers.sh b/tools/perf/check-headers.sh index eacca9a874e2..e4a8b5348678 100755 --- a/tools/perf/check-headers.sh +++ b/tools/perf/check-headers.sh @@ -52,7 +52,6 @@ arch/x86/include/uapi/asm/vmx.h arch/powerpc/include/uapi/asm/kvm.h arch/s390/include/uapi/asm/kvm.h arch/s390/include/uapi/asm/kvm_perf.h -arch/s390/include/uapi/asm/ptrace.h arch/s390/include/uapi/asm/sie.h arch/arm/include/uapi/asm/kvm.h arch/arm64/include/uapi/asm/kvm.h -- cgit v1.2.3-58-ga151 From eab5051788f6111adb88268a784af0c981616579 Mon Sep 17 00:00:00 2001 From: Hangliang Lai Date: Tue, 11 Apr 2023 09:32:24 +0800 Subject: perf top: Expand the range of multithreaded phase In __cmd_top(), perf_set_multithreaded() is used to enable pthread_rwlock, thus down_read() and down_write () are not nops, handling concurrency problems Then 'perf top' uses perf_set_singlethreaded(), switching to the single threaded phase, assuming that no thread concurrency will happen later. However, a use after free problem could occur in the single threaded phase, the concurrent procedure is this: display_thread process_thread -------------- -------------- thread__comm_len -> thread__comm_str -> __thread__comm_str(thread) thread__delete -> comm__free -> comm_str__put -> zfree(&cs->str) -> thread->comm_len = strlen(comm); Since in single thread phase, perf_singlethreaded is true, down_read() and down_write() do nothing to avoid concurrency problems. This patch moves the perf_set_singlethreaded() call to the function tail to expand the multithreaded phase range, making display_thread() and process_thread() concurrency safe. Reviewed-by: Yunfeng Ye Signed-off-by: Hangliang Lai Co-developed-by: Wenyu Liu Acked-by: Namhyung Kim Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Christian Brauner Cc: Feilong Lin Cc: Hewenliang Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Link: https://lore.kernel.org/r/20230411013224.2079-1-laihangliang1@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-top.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c index 3162bad0d17d..5d448c36ed22 100644 --- a/tools/perf/builtin-top.c +++ b/tools/perf/builtin-top.c @@ -1276,8 +1276,7 @@ static int __cmd_top(struct perf_top *top) top->evlist->core.threads, true, false, top->nr_threads_synthesize); - if (top->nr_threads_synthesize > 1) - perf_set_singlethreaded(); + perf_set_multithreaded(); if (perf_hpp_list.socket) { ret = perf_env__read_cpu_topology_map(&perf_env); @@ -1355,6 +1354,7 @@ out_join: out_join_thread: cond_signal(&top->qe.cond); pthread_join(thread_process, NULL); + perf_set_singlethreaded(); return ret; } -- cgit v1.2.3-58-ga151 From 984abd349d0f76d4b267abc0d8e1a86af3ec2d84 Mon Sep 17 00:00:00 2001 From: Alexander Pantyukhin Date: Sat, 14 Jan 2023 18:05:33 +0500 Subject: perf scripts python intel-pt-events: Delete unused 'event_attr variable The 'event_attr' is never used later, the var is ok be deleted. Additional code simplification is to substitute string slice comparison with "substring" function. This case no need to know the length specific words. Signed-off-by: Alexander Pantyukhin Acked-by: Adrian Hunter Cc: Andrew Morton Cc: Ingo Molnar Cc: Jiri Olsa Cc: Namhyung Kim Link: https://lore.kernel.org/r/20230114130533.2877-1-apantykhin@gmail.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/scripts/python/intel-pt-events.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'tools') diff --git a/tools/perf/scripts/python/intel-pt-events.py b/tools/perf/scripts/python/intel-pt-events.py index 1c76368f13c1..346c89bd16d6 100644 --- a/tools/perf/scripts/python/intel-pt-events.py +++ b/tools/perf/scripts/python/intel-pt-events.py @@ -340,7 +340,6 @@ def print_srccode(comm, param_dict, sample, symbol, dso, with_insn): print(start_str, src_str) def do_process_event(param_dict): - event_attr = param_dict["attr"] sample = param_dict["sample"] raw_buf = param_dict["raw_buf"] comm = param_dict["comm"] @@ -349,6 +348,7 @@ def do_process_event(param_dict): # callchain = param_dict["callchain"] # brstack = param_dict["brstack"] # brstacksym = param_dict["brstacksym"] + # event_attr = param_dict["attr"] # Symbol and dso info are not always resolved dso = get_optional(param_dict, "dso") @@ -359,13 +359,13 @@ def do_process_event(param_dict): print(glb_switch_str[cpu]) del glb_switch_str[cpu] - if name[0:12] == "instructions": + if name.startswith("instructions"): if glb_src: print_srccode(comm, param_dict, sample, symbol, dso, True) else: print_instructions_start(comm, sample) print_common_ip(param_dict, sample, symbol, dso) - elif name[0:8] == "branches": + elif name.startswith("branches"): if glb_src: print_srccode(comm, param_dict, sample, symbol, dso, False) else: -- cgit v1.2.3-58-ga151 From 4e8db2d7520f780f86055465c680e20327008a34 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 12 Apr 2023 12:36:58 -0300 Subject: perf map: Add map__refcnt() accessor to use in the maps test To remove one more direct access to 'struct map' so that we can intecept accesses to its instantiations and refcount check it to catch use after free, etc. Cc: Adrian Hunter Cc: Alexey Bayduraev Cc: Dmitriy Vyukov Cc: Ian Rogers Cc: Jiri Olsa Cc: Namhyung Kim Cc: Riccardo Mancini Cc: Stephane Eranian Cc: Stephen Brennan Link: https://lore.kernel.org/lkml/ZDbRIJknafLnDwtO@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/maps.c | 4 ++-- tools/perf/util/map.h | 5 +++++ 2 files changed, 7 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/tests/maps.c b/tools/perf/tests/maps.c index 1c7293476aca..a6278f9c8b71 100644 --- a/tools/perf/tests/maps.c +++ b/tools/perf/tests/maps.c @@ -30,7 +30,7 @@ static int check_maps(struct map_def *merged, unsigned int size, struct maps *ma if (map__start(map) != merged[i].start || map__end(map) != merged[i].end || strcmp(map__dso(map)->name, merged[i].name) || - refcount_read(&map->refcnt) != 1) { + refcount_read(map__refcnt(map)) != 1) { failed = true; } i++; @@ -50,7 +50,7 @@ static int check_maps(struct map_def *merged, unsigned int size, struct maps *ma map__start(map), map__end(map), map__dso(map)->name, - refcount_read(&map->refcnt)); + refcount_read(map__refcnt(map))); } } return failed ? TEST_FAIL : TEST_OK; diff --git a/tools/perf/util/map.h b/tools/perf/util/map.h index 102485699aa8..f89ab7c2d327 100644 --- a/tools/perf/util/map.h +++ b/tools/perf/util/map.h @@ -97,6 +97,11 @@ static inline bool map__priv(const struct map *map) return map->priv; } +static inline refcount_t *map__refcnt(struct map *map) +{ + return &map->refcnt; +} + static inline size_t map__size(const struct map *map) { return map__end(map) - map__start(map); -- cgit v1.2.3-58-ga151 From 7bb1d048bdfe1c7d36fdd72be9abd5f552b6246a Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Wed, 12 Apr 2023 12:45:45 -0300 Subject: perf cpumap: Use perf_cpu_map__nr(cpus) to access cpus->nr So that we can have a single point where to refcount check 'struct perf_cpu_map' instances for use after free, etc. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexey Bayduraev Cc: Dmitriy Vyukov Cc: Jiri Olsa Cc: Namhyung Kim Cc: Riccardo Mancini Cc: Stephane Eranian Cc: Stephen Brennan Link: https://lore.kernel.org/lkml/20230407230405.2931830-3-irogers@google.com [ Split from a larger patch ] Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/cpumap.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/cpumap.c b/tools/perf/util/cpumap.c index 5e564974fba4..c8484b75413e 100644 --- a/tools/perf/util/cpumap.c +++ b/tools/perf/util/cpumap.c @@ -239,7 +239,7 @@ struct cpu_aggr_map *cpu_aggr_map__new(const struct perf_cpu_map *cpus, { int idx; struct perf_cpu cpu; - struct cpu_aggr_map *c = cpu_aggr_map__empty_new(cpus->nr); + struct cpu_aggr_map *c = cpu_aggr_map__empty_new(perf_cpu_map__nr(cpus)); if (!c) return NULL; @@ -263,7 +263,7 @@ struct cpu_aggr_map *cpu_aggr_map__new(const struct perf_cpu_map *cpus, } } /* Trim. */ - if (c->nr != cpus->nr) { + if (c->nr != perf_cpu_map__nr(cpus)) { struct cpu_aggr_map *trimmed_c = realloc(c, sizeof(struct cpu_aggr_map) + sizeof(struct aggr_cpu_id) * c->nr); @@ -582,9 +582,9 @@ size_t cpu_map__snprint(struct perf_cpu_map *map, char *buf, size_t size) #define COMMA first ? "" : "," - for (i = 0; i < map->nr + 1; i++) { + for (i = 0; i < perf_cpu_map__nr(map) + 1; i++) { struct perf_cpu cpu = { .cpu = INT_MAX }; - bool last = i == map->nr; + bool last = i == perf_cpu_map__nr(map); if (!last) cpu = map->map[i]; @@ -633,7 +633,7 @@ size_t cpu_map__snprint_mask(struct perf_cpu_map *map, char *buf, size_t size) int i, cpu; char *ptr = buf; unsigned char *bitmap; - struct perf_cpu last_cpu = perf_cpu_map__cpu(map, map->nr - 1); + struct perf_cpu last_cpu = perf_cpu_map__cpu(map, perf_cpu_map__nr(map) - 1); if (buf == NULL) return 0; @@ -644,7 +644,7 @@ size_t cpu_map__snprint_mask(struct perf_cpu_map *map, char *buf, size_t size) return 0; } - for (i = 0; i < map->nr; i++) { + for (i = 0; i < perf_cpu_map__nr(map); i++) { cpu = perf_cpu_map__cpu(map, i).cpu; bitmap[cpu / 8] |= 1 << (cpu % 8); } -- cgit v1.2.3-58-ga151 From 1f94479edb4decdcec3e902528abb47f0ccd5d16 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Wed, 12 Apr 2023 12:54:44 -0300 Subject: libperf: Make perf_cpu_map__alloc() available as an internal function for tools/perf to use We had the open coded equivalent in perf_cpu_map__empty_new(), so reuse what is in libperf. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexey Bayduraev Cc: Dmitriy Vyukov Cc: Jiri Olsa Cc: Namhyung Kim Cc: Riccardo Mancini Cc: Stephane Eranian Cc: Stephen Brennan Link: https://lore.kernel.org/lkml/20230407230405.2931830-3-irogers@google.com [ Split from a larger patch ] Signed-off-by: Arnaldo Carvalho de Melo --- tools/lib/perf/cpumap.c | 2 +- tools/lib/perf/include/internal/cpumap.h | 1 + tools/perf/util/cpumap.c | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/lib/perf/cpumap.c b/tools/lib/perf/cpumap.c index 6cd0be7c1bb4..0833423c243b 100644 --- a/tools/lib/perf/cpumap.c +++ b/tools/lib/perf/cpumap.c @@ -10,7 +10,7 @@ #include #include -static struct perf_cpu_map *perf_cpu_map__alloc(int nr_cpus) +struct perf_cpu_map *perf_cpu_map__alloc(int nr_cpus) { struct perf_cpu_map *cpus = malloc(sizeof(*cpus) + sizeof(struct perf_cpu) * nr_cpus); diff --git a/tools/lib/perf/include/internal/cpumap.h b/tools/lib/perf/include/internal/cpumap.h index 35dd29642296..f5bffb1f8674 100644 --- a/tools/lib/perf/include/internal/cpumap.h +++ b/tools/lib/perf/include/internal/cpumap.h @@ -24,6 +24,7 @@ struct perf_cpu_map { #define MAX_NR_CPUS 2048 #endif +struct perf_cpu_map *perf_cpu_map__alloc(int nr_cpus); int perf_cpu_map__idx(const struct perf_cpu_map *cpus, struct perf_cpu cpu); bool perf_cpu_map__is_subset(const struct perf_cpu_map *a, const struct perf_cpu_map *b); diff --git a/tools/perf/util/cpumap.c b/tools/perf/util/cpumap.c index c8484b75413e..072831f0cad4 100644 --- a/tools/perf/util/cpumap.c +++ b/tools/perf/util/cpumap.c @@ -160,7 +160,7 @@ size_t cpu_map__fprintf(struct perf_cpu_map *map, FILE *fp) struct perf_cpu_map *perf_cpu_map__empty_new(int nr) { - struct perf_cpu_map *cpus = malloc(sizeof(*cpus) + sizeof(int) * nr); + struct perf_cpu_map *cpus = perf_cpu_map__alloc(nr); if (cpus != NULL) { int i; -- cgit v1.2.3-58-ga151 From b277851417e0149aff5e6986e1ad6e2d8054e4a6 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 12 Apr 2023 14:53:35 -0300 Subject: libperf: Add a perf_cpu_map__set_nr() available as an internal function for tools/perf to use We'll need to reference count check 'struct perf_cpu_map', so wrap accesses to its internal state to allow intercepting accesses to its instances. Cc: Adrian Hunter Cc: Alexey Bayduraev Cc: Dmitriy Vyukov Cc: Ian Rogers Cc: Jiri Olsa Cc: Namhyung Kim Cc: Riccardo Mancini Cc: Stephane Eranian Cc: Stephen Brennan Link: https://lore.kernel.org/ Signed-off-by: Arnaldo Carvalho de Melo --- tools/lib/perf/cpumap.c | 5 +++++ tools/lib/perf/include/internal/cpumap.h | 2 ++ 2 files changed, 7 insertions(+) (limited to 'tools') diff --git a/tools/lib/perf/cpumap.c b/tools/lib/perf/cpumap.c index 0833423c243b..6bbcbb83eb14 100644 --- a/tools/lib/perf/cpumap.c +++ b/tools/lib/perf/cpumap.c @@ -10,6 +10,11 @@ #include #include +void perf_cpu_map__set_nr(struct perf_cpu_map *map, int nr_cpus) +{ + map->nr = nr_cpus; +} + struct perf_cpu_map *perf_cpu_map__alloc(int nr_cpus) { struct perf_cpu_map *cpus = malloc(sizeof(*cpus) + sizeof(struct perf_cpu) * nr_cpus); diff --git a/tools/lib/perf/include/internal/cpumap.h b/tools/lib/perf/include/internal/cpumap.h index f5bffb1f8674..b82fd6607a00 100644 --- a/tools/lib/perf/include/internal/cpumap.h +++ b/tools/lib/perf/include/internal/cpumap.h @@ -28,4 +28,6 @@ struct perf_cpu_map *perf_cpu_map__alloc(int nr_cpus); int perf_cpu_map__idx(const struct perf_cpu_map *cpus, struct perf_cpu cpu); bool perf_cpu_map__is_subset(const struct perf_cpu_map *a, const struct perf_cpu_map *b); +void perf_cpu_map__set_nr(struct perf_cpu_map *map, int nr_cpus); + #endif /* __LIBPERF_INTERNAL_CPUMAP_H */ -- cgit v1.2.3-58-ga151 From 9efe423e4387893498e11c75207bc9a1c9121246 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 12 Apr 2023 14:56:28 -0300 Subject: perf pmu: Use perf_cpu_map__set_nr() in perf_pmu__cpus_match() to allow for refcnt checking One more step to allow for checking reference counting, user after free, etc. Cc: Adrian Hunter Cc: Alexey Bayduraev Cc: Dmitriy Vyukov Cc: Ian Rogers Cc: Jiri Olsa Cc: Namhyung Kim Cc: Riccardo Mancini Cc: Stephane Eranian Cc: Stephen Brennan Link: https://lore.kernel.org/ZDb9dycHQ11UIXwx@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/pmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 561e2616861f..760c848c9fa2 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -2020,8 +2020,8 @@ int perf_pmu__cpus_match(struct perf_pmu *pmu, struct perf_cpu_map *cpus, matched_cpus->map[matched_nr++] = cpu; } - unmatched_cpus->nr = unmatched_nr; - matched_cpus->nr = matched_nr; + perf_cpu_map__set_nr(unmatched_cpus, unmatched_nr); + perf_cpu_map__set_nr(matched_cpus, matched_nr); *mcpus_ptr = matched_cpus; *ucpus_ptr = unmatched_cpus; return 0; -- cgit v1.2.3-58-ga151 From 4453deacf44615b2d45a0b5226ff132e830bd03d Mon Sep 17 00:00:00 2001 From: Chunxin Zang Date: Tue, 28 Mar 2023 14:00:57 +0800 Subject: perf sched: Fix sched latency analysis incorrection when using 'sched:sched_wakeup' 'perf sched latency' is incorrect to get process schedule latency when it used 'sched:sched_wakeup' to analysis perf.data. Because 'perf record' prefers to use 'sched:sched_waking' to 'sched:sched_wakeup' since commit d566a9c2d482 ("perf sched: Prefer sched_waking event when it exists"). It's very reasonable to evaluate process schedule latency. Similarly, update sched latency/map/replay to use sched_waking events. Signed-off-by: Chunxin Zang Acked-by: Namhyung Kim Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230328060038.2346935-1-zangchunxin@lixiang.com Signed-off-by: Jerry Zhou Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-sched.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/builtin-sched.c b/tools/perf/builtin-sched.c index 96a0dceadeff..cc4ba506e119 100644 --- a/tools/perf/builtin-sched.c +++ b/tools/perf/builtin-sched.c @@ -1516,6 +1516,14 @@ static int process_sched_wakeup_event(struct perf_tool *tool, return 0; } +static int process_sched_wakeup_ignore(struct perf_tool *tool __maybe_unused, + struct evsel *evsel __maybe_unused, + struct perf_sample *sample __maybe_unused, + struct machine *machine __maybe_unused) +{ + return 0; +} + union map_priv { void *ptr; bool color; @@ -1816,10 +1824,11 @@ static int perf_sched__process_comm(struct perf_tool *tool __maybe_unused, static int perf_sched__read_events(struct perf_sched *sched) { - const struct evsel_str_handler handlers[] = { + struct evsel_str_handler handlers[] = { { "sched:sched_switch", process_sched_switch_event, }, { "sched:sched_stat_runtime", process_sched_runtime_event, }, { "sched:sched_wakeup", process_sched_wakeup_event, }, + { "sched:sched_waking", process_sched_wakeup_event, }, { "sched:sched_wakeup_new", process_sched_wakeup_event, }, { "sched:sched_migrate_task", process_sched_migrate_task_event, }, }; @@ -1839,6 +1848,10 @@ static int perf_sched__read_events(struct perf_sched *sched) symbol__init(&session->header.env); + /* prefer sched_waking if it is captured */ + if (evlist__find_tracepoint_by_name(session->evlist, "sched:sched_waking")) + handlers[2].handler = process_sched_wakeup_ignore; + if (perf_session__set_tracepoints_handlers(session, handlers)) goto out_delete; -- cgit v1.2.3-58-ga151 From 54f5de6f2998cfefbb68e7f6b2672f0b0ea5ab24 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 13 Apr 2023 06:29:29 -0700 Subject: perf vendor events intel: Update sapphirerapids to v1.12 Summary from https://github.com/intel/perfmon/pull/68 - Numerous uncore event additions and changes. - Description updates for core events XQ.FULL_CYCLES and MISC2_RETIRED.LFENCE. - Update ARITH.IDIV_ACTIVE counter mask. This change also gets rid of uncore-other as a topic, derived from the file name, breaking it apart in to more specific topics. Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Edward Baker Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: http://lore.kernel.org/lkml/20230413132949.3487664-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- .../pmu-events/arch/x86/sapphirerapids/other.json | 3 +- .../arch/x86/sapphirerapids/pipeline.json | 4 +- .../arch/x86/sapphirerapids/uncore-cache.json | 5644 ++++++++++++++++++ .../arch/x86/sapphirerapids/uncore-cxl.json | 450 ++ .../x86/sapphirerapids/uncore-interconnect.json | 6199 ++++++++++++++++++++ .../arch/x86/sapphirerapids/uncore-io.json | 3651 ++++++++++++ .../arch/x86/sapphirerapids/uncore-memory.json | 3283 ++++++++++- .../arch/x86/sapphirerapids/uncore-other.json | 4525 -------------- .../arch/x86/sapphirerapids/uncore-power.json | 107 + 10 files changed, 19122 insertions(+), 4746 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cache.json create mode 100644 tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cxl.json create mode 100644 tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-interconnect.json create mode 100644 tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-io.json delete mode 100644 tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-other.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 58faf18474b5..437eeecfaf64 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -22,7 +22,7 @@ GenuineIntel-6-A[AC],v1.01,meteorlake,core GenuineIntel-6-1[AEF],v3,nehalemep,core GenuineIntel-6-2E,v3,nehalemex,core GenuineIntel-6-2A,v19,sandybridge,core -GenuineIntel-6-(8F|CF),v1.11,sapphirerapids,core +GenuineIntel-6-(8F|CF),v1.12,sapphirerapids,core GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v55,skylake,core GenuineIntel-6-55-[01234],v1.29,skylakex,core diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/other.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/other.json index 5d4c15dbf4d3..31b6be9fb8c7 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/other.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/other.json @@ -331,10 +331,11 @@ "UMask": "0x7" }, { - "BriefDescription": "XQ.FULL_CYCLES", + "BriefDescription": "Cycles the uncore cannot take further requests", "CounterMask": "1", "EventCode": "0x2d", "EventName": "XQ.FULL_CYCLES", + "PublicDescription": "number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache).", "SampleAfterValue": "1000003", "UMask": "0x1" } diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json index 40e52357ade1..72e9bdfa9f80 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json @@ -44,6 +44,7 @@ }, { "BriefDescription": "This event counts the cycles the integer divider is busy.", + "CounterMask": "1", "EventCode": "0xb0", "EventName": "ARITH.IDIV_ACTIVE", "SampleAfterValue": "1000003", @@ -655,9 +656,10 @@ "UMask": "0x4" }, { - "BriefDescription": "MISC2_RETIRED.LFENCE", + "BriefDescription": "LFENCE instructions retired", "EventCode": "0xe0", "EventName": "MISC2_RETIRED.LFENCE", + "PublicDescription": "number of LFENCE retired instructions", "SampleAfterValue": "400009", "UMask": "0x20" }, diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cache.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cache.json new file mode 100644 index 000000000000..b91cebf81f50 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cache.json @@ -0,0 +1,5644 @@ +[ + { + "BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", + "PerPkg": "1", + "PublicDescription": "CHA to iMC Bypass : Intermediate bypass Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the intermediate bypass.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Bypass : Not Taken", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", + "PerPkg": "1", + "PublicDescription": "CHA to iMC Bypass : Not Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Bypass : Taken", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN", + "PerPkg": "1", + "PublicDescription": "CHA to iMC Bypass : Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the full bypass.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA Clockticks", + "EventCode": "0x01", + "EventName": "UNC_CHA_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Number of CHA clock cycles while the event is enabled", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Clockticks", + "EventCode": "0xc0", + "EventName": "UNC_CHA_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0xf2", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Any Single Snoop", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_ONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Any Single Snoop : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0xf1", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Multiple Core Requests", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Multiple Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x42", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Single Core Requests", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.CORE_ONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Single Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x41", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Multiple Eviction", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Multiple Eviction : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x82", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Single Eviction", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Single Eviction : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x81", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Multiple External Snoops", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Multiple External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x22", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Single External Snoops", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_ONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Single External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Multiple Snoop Targets from Remote", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.REMOTE_GTONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Multiple Snoop Targets from Remote : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x12", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Single Snoop Target from Remote", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.REMOTE_ONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Single Snoop Target from Remote : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6e", + "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6e", + "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6e", + "EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6d", + "EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6d", + "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6d", + "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6d", + "EventName": "UNC_CHA_DIRECT_GO_OPC.GO", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6d", + "EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6d", + "EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6d", + "EventName": "UNC_CHA_DIRECT_GO_OPC.NOP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6d", + "EventName": "UNC_CHA_DIRECT_GO_OPC.PULL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed", + "EventCode": "0x53", + "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP", + "PerPkg": "1", + "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed", + "EventCode": "0x53", + "EventName": "UNC_CHA_DIR_LOOKUP.SNP", + "PerPkg": "1", + "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe", + "EventCode": "0x54", + "EventName": "UNC_CHA_DIR_UPDATE.HA", + "PerPkg": "1", + "PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe", + "EventCode": "0x54", + "EventName": "UNC_CHA_DIR_UPDATE.TOR", + "PerPkg": "1", + "PublicDescription": "Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Down", + "EventCode": "0xba", + "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Up", + "EventCode": "0xba", + "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state", + "EventCode": "0x5f", + "EventName": "UNC_CHA_HITME_HIT.EX_RDS", + "PerPkg": "1", + "PublicDescription": "Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state. This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*).", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache : Shared hit and op is RdInvOwn, RdInv, Inv*", + "EventCode": "0x5f", + "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache : op is WbMtoE", + "EventCode": "0x5f", + "EventName": "UNC_CHA_HITME_HIT.WBMTOE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache : op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", + "EventCode": "0x5f", + "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed : op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*", + "EventCode": "0x5e", + "EventName": "UNC_CHA_HITME_LOOKUP.READ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed : op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", + "EventCode": "0x5e", + "EventName": "UNC_CHA_HITME_LOOKUP.WRITE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Misses in HitMe Cache : No SF/LLC HitS/F and op is RdInvOwn", + "EventCode": "0x60", + "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Misses in HitMe Cache : op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*", + "EventCode": "0x60", + "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Misses in HitMe Cache : SF/LLC HitS/F and op is RdInvOwn", + "EventCode": "0x60", + "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Deallocate HitME$ on Reads without RspFwdI*", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", + "PerPkg": "1", + "PublicDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request : Received RspFwdI* for a local request, but converted HitME$ to SF entry", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache on RdInvOwn even if not RspFwdI*", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM", + "PerPkg": "1", + "PublicDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request : Updated HitME$ on RspFwdI* or local HitM/E received for a remote request", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache to SHARed", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.SHARED", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Normal priority reads issued to the memory controller from the CHA", + "EventCode": "0x59", + "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", + "PerPkg": "1", + "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "HA to iMC Reads Issued : ISOCH", + "EventCode": "0x59", + "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY", + "PerPkg": "1", + "PublicDescription": "HA to iMC Reads Issued : ISOCH : Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH", + "EventCode": "0x5b", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", + "PerPkg": "1", + "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line", + "EventCode": "0x5b", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "PerPkg": "1", + "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line : Counts the total number of full line writes issued from the HA into the memory controller.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH", + "EventCode": "0x5b", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "PerPkg": "1", + "PublicDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH : Counts the total number of full line writes issued from the HA into the memory controller.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial", + "EventCode": "0x5b", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "PerPkg": "1", + "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial : Counts the total number of full line writes issued from the HA into the memory controller.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Any Request", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.", + "UMask": "0x1fffff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : All transactions from Remote Agents", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.ALL_REMOTE", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : All transactions from Remote Agents : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x17e0ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : All Requests", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.ANY_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : All Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Any local or remote transaction to the LLC, including prefetch.", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : CRd Requests", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.", + "UMask": "0x1bd0ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : CRd Requests", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Local non-prefetch requests", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Local non-prefetch requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Any local transaction to the LLC, not including prefetch", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions", + "UMask": "0x1bc1ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Data Reads", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Data Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x1fc1ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Data Read Request", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Data Read Request : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Read transactions.", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Demand Data Reads, Core and LLC prefetches", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Demand Data Reads, Core and LLC prefetches : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x841ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Data Read Misses", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Data Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x1fc101", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : E State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.E", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Hit Exclusive State", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : F State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : F State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Hit Forward State", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Flush or Invalidate Requests", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.", + "UMask": "0x1a44ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Flush", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : I State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.I", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : I State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Miss", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Local LLC prefetch requests (from LLC)", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Local LLC prefetch requests (from LLC) : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Any local LLC prefetch to the LLC", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Transactions homed locally", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCALLY_HOMED_ADDRESS", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Transactions homed locally : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC.", + "UMask": "0xbdfff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : CRd Requests that come from the local socket (usually the core)", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_CODE", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.", + "UMask": "0x19d0ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request that come from the local socket (usually the core)", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DATA_RD", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions", + "UMask": "0x19c1ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Demand CRd Requests that come from the local socket (usually the core)", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_CODE", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.", + "UMask": "0x1850ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Demand Data Reads that come from the local socket (usually the core)", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_DATA_RD", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions", + "UMask": "0x1841ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Demand RFO Requests that come from the local socket (usually the core)", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_RFO", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.", + "UMask": "0x1848ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Transactions homed locally", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Transactions homed locally : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC.", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Flush or Invalidate Requests that come from the local socket (usually the core)", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_FLUSH_INV", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.", + "UMask": "0x1844ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Prefetch requests to the LLC that come from the local socket (usually the core)", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_LLC_PF", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions", + "UMask": "0x189dff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Prefetches that come from the local socket (usually the core)", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions", + "UMask": "0x199dff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : CRd Prefetches that come from the local socket (usually the core)", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_CODE", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.", + "UMask": "0x1910ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Prefetches that come from the local socket (usually the core)", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_DATA_RD", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions", + "UMask": "0x1981ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : RFO Prefetches that come from the local socket (usually the core)", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_RFO", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.", + "UMask": "0x1908ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : RFO Requests that come from the local socket (usually the core)", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_RFO", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.", + "UMask": "0x19c8ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : M State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.M", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : M State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Hit Modified State", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : All Misses", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x1fe001", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Write Requests", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Write Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Remote non-snoop requests", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.PREF_OR_DMND_REMOTE_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Remote non-snoop requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Remote non-snoop transactions to the LLC.", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Transactions homed remotely", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTELY_HOMED_ADDRESS", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Transactions homed remotely : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC", + "UMask": "0x15dfff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : CRd Requests that come from a Remote socket.", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_CODE", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.", + "UMask": "0x1a10ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Requests that come from a Remote socket", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_DATA_RD", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions", + "UMask": "0x1a01ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Transactions homed remotely", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Transactions homed remotely : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Flush or Invalidate requests that come from a Remote socket.", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_FLUSH_INV", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.", + "UMask": "0x1a04ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Filters Requests for those that write info into the cache that come from a remote socket", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_OTHER", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Write Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.", + "UMask": "0x1a02ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : RFO Requests that come from a Remote socket.", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_RFO", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.", + "UMask": "0x1a08ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Remote snoop requests", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Remote snoop requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Remote snoop transactions to the LLC.", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Snoop Requests from a Remote Socket", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.", + "UMask": "0x1c19ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : RFO Requests", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.", + "UMask": "0x1bc8ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : RFO Request Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO_F", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Locally HOMed RFOs - Demand and Prefetches", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x9c8ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : S State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.S", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Hit Shared State", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : SnoopFilter - E State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.SF_E", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : SnoopFilter - E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : SF Hit Exclusive State", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : SnoopFilter - H State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.SF_H", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : SnoopFilter - H State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : SF Hit HitMe State", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : SnoopFilter - S State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.SF_S", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : SnoopFilter - S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : SF Hit Shared State", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Writes", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Requests that install or change a line in the LLC. Examples: Writebacks from Core L2's and UPI. Prefetches into the LLC.", + "UMask": "0x842ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Remote Writes", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x17c2ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Lines in E state", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Lines in E state : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : IA traffic", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.IA", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : IA traffic : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : IO traffic", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.IO", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : IO traffic : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "All LLC lines in E state that are victimized on a fill from an IO device", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.IO_E", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x12", + "Unit": "CHA" + }, + { + "BriefDescription": "All LLC lines in F or S state that are victimized on a fill from an IO device", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.IO_FS", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x1c", + "Unit": "CHA" + }, + { + "BriefDescription": "All LLC lines in M state that are victimized on a fill from an IO device", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.IO_M", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "All LLC lines in any state that are victimized on a fill from an IO device", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.IO_MESF", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x1f", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Local - All Lines", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x200f", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x2002", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x2001", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Local Only", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Local Only : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x2004", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Lines in M state", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Lines in M state : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Remote - All Lines", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x800f", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x8002", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x8001", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Remote Only", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ONLY", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Remote Only : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x8004", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Lines in S State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "All LLC lines in E state that are victimized on a fill", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "All LLC lines in M state that are victimized on a fill", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "All LLC lines in S state that are victimized on a fill", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc : CV0 Prefetch Miss", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.CV0_PREF_MISS", + "PerPkg": "1", + "PublicDescription": "Cbo Misc : CV0 Prefetch Miss : Miscellaneous events in the Cbo.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc : CV0 Prefetch Victim", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.CV0_PREF_VIC", + "PerPkg": "1", + "PublicDescription": "Cbo Misc : CV0 Prefetch Victim : Miscellaneous events in the Cbo.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Number of times that an RFO hit in S state.", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.RFO_HIT_S", + "PerPkg": "1", + "PublicDescription": "Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc : Silent Snoop Eviction", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE", + "PerPkg": "1", + "PublicDescription": "Cbo Misc : Silent Snoop Eviction : Miscellaneous events in the Cbo. : Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc : Write Combining Aliasing", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.WC_ALIASING", + "PerPkg": "1", + "PublicDescription": "Cbo Misc : Write Combining Aliasing : Miscellaneous events in the Cbo. : Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast : Local InvItoE", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB.LOCAL_INVITOE", + "PerPkg": "1", + "PublicDescription": "OSB Snoop Broadcast : Local InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast : Local Rd", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB.LOCAL_READ", + "PerPkg": "1", + "PublicDescription": "OSB Snoop Broadcast : Local Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast : Off", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB.OFF_PWRHEURISTIC", + "PerPkg": "1", + "PublicDescription": "OSB Snoop Broadcast : Off : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast : Remote Rd", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB.REMOTE_READ", + "PerPkg": "1", + "PublicDescription": "OSB Snoop Broadcast : Remote Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast : Remote Rd InvItoE", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB.REMOTE_READINVITOE", + "PerPkg": "1", + "PublicDescription": "OSB Snoop Broadcast : Remote Rd InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB.RFO_HITS_SNP_BCAST", + "PerPkg": "1", + "PublicDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL", + "EventCode": "0x65", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE", + "EventCode": "0x65", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT", + "EventCode": "0x65", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw a Near Memory set conflict in SF/LLC", + "EventCode": "0x64", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC", + "PerPkg": "1", + "PublicDescription": "Near Memory evictions due to another read to the same Near Memory set in the LLC.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw a Near memory set conflict in SF/LLC", + "EventCode": "0x64", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF", + "PerPkg": "1", + "PublicDescription": "Near Memory evictions due to another read to the same Near Memory set in the SF", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw a Near Memory set conflict in TOR", + "EventCode": "0x64", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR", + "PerPkg": "1", + "PublicDescription": "No Reject in the CHA due to a pending read to the same Near Memory set in the TOR.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC", + "EventCode": "0x70", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR", + "EventCode": "0x70", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI", + "EventCode": "0x70", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT", + "EventCode": "0x66", + "EventName": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_QOS.REJ_IRQ", + "EventCode": "0x66", + "EventName": "UNC_CHA_PMM_QOS.REJ_IRQ", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP", + "EventCode": "0x66", + "EventName": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_QOS.SLOW_INSERT", + "EventCode": "0x66", + "EventName": "UNC_CHA_PMM_QOS.SLOW_INSERT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE", + "EventCode": "0x66", + "EventName": "UNC_CHA_PMM_QOS.THROTTLE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_IRQ", + "EventCode": "0x66", + "EventName": "UNC_CHA_PMM_QOS.THROTTLE_IRQ", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_PRQ", + "EventCode": "0x66", + "EventName": "UNC_CHA_PMM_QOS.THROTTLE_PRQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO", + "EventCode": "0x67", + "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO", + "PerPkg": "1", + "PublicDescription": ": count # of FAST TOR Request inserted to ha_tor_req_fifo", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Number of SLOW TOR Request inserted to ha_pmm_tor_req_fifo", + "EventCode": "0x67", + "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC0", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC0 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 0 only.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC1", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC1 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 1 only.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC2", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC2 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 2 only.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC3", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC3 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 3 only.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC4", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC4 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 4 only.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC5", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC5 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 5 only.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Requests for exclusive ownership of a cache line without receiving data", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.INVITOE", + "PerPkg": "1", + "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "UMask": "0x30", + "Unit": "CHA" + }, + { + "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Remote requests for exclusive ownership of a cache line without receiving data", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Read requests made into the CHA", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS", + "PerPkg": "1", + "PublicDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) .", + "UMask": "0x3", + "Unit": "CHA" + }, + { + "BriefDescription": "Read requests from a unit on this socket", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Read requests from a remote socket", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Write requests made into the CHA", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES", + "PerPkg": "1", + "PublicDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", + "UMask": "0xc", + "Unit": "CHA" + }, + { + "BriefDescription": "Write Requests from a unit on this socket", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Read and Write Requests; Writes Remote", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : IPQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IPQ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Allocations : IPQ : Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : IRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IRQ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Allocations : IRQ : Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Allocations : IRQ Rejected : Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : PRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.PRQ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : PRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : RRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.RRQ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Allocations : RRQ : Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : WBQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.WBQ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Allocations : WBQ : Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Allow Snoop", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : ANY0", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0", + "PerPkg": "1", + "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IPQ0 Reject counter was true", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : HA", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC Victim", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : SF Victim", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Victim", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IRQ0 Reject counter was true", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way : Way conflict with another request that caused the reject", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC Victim", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Victim", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0", + "EventCode": "0x2c", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0", + "EventCode": "0x2c", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request", + "EventCode": "0x2c", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0", + "EventCode": "0x2c", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0", + "EventCode": "0x2c", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0", + "EventCode": "0x2c", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0", + "EventCode": "0x2c", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request", + "EventCode": "0x2c", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 1 : ANY0", + "EventCode": "0x25", + "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 1 : HA", + "EventCode": "0x25", + "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 1 : ANY0", + "EventCode": "0x2d", + "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 1 : HA", + "EventCode": "0x2d", + "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy : IPQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Occupancy : IPQ : Counts number of entries in the specified Ingress queue in each cycle.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy : RRQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Occupancy : RRQ : Counts number of entries in the specified Ingress queue in each cycle.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy : WBQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Occupancy : WBQ : Counts number of entries in the specified Ingress queue in each cycle.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : AD REQ on VN0", + "EventCode": "0x2e", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : AD REQ on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a request", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : AD RSP on VN0", + "EventCode": "0x2e", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : AD RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a response", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : Non UPI AK Request", + "EventCode": "0x2e", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : Non UPI AK Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject AK ring message", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : BL NCB on VN0", + "EventCode": "0x2e", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : BL NCB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCB", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : BL NCS on VN0", + "EventCode": "0x2e", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : BL NCS on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCS", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : BL RSP on VN0", + "EventCode": "0x2e", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : BL RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a response", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : BL WB on VN0", + "EventCode": "0x2e", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : BL WB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : Non UPI IV Request", + "EventCode": "0x2e", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : Non UPI IV Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject IV ring message", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : Allow Snoop", + "EventCode": "0x2f", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 1 : Allow Snoop : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : ANY0", + "EventCode": "0x2f", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 1 : ANY0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Any condition listed in the Other0 Reject counter was true", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : HA", + "EventCode": "0x2f", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 1 : HA : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : LLC OR SF Way", + "EventCode": "0x2f", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 1 : LLC OR SF Way : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Way conflict with another request that caused the reject", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : LLC Victim", + "EventCode": "0x2f", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 1 : LLC Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : PhyAddr Match", + "EventCode": "0x2f", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 1 : PhyAddr Match : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Address match with an outstanding request that was rejected.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : SF Victim", + "EventCode": "0x2f", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 1 : SF Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Requests did not generate Snoop filter victim", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : Victim", + "EventCode": "0x2f", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 1 : Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the PRQ0 Reject counter was true", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC Victim", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Victim", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0", + "EventCode": "0x2a", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : AD REQ on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a request", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0", + "EventCode": "0x2a", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : AD RSP on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a response", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Request", + "EventCode": "0x2a", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : Non UPI AK Request : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject AK ring message", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0", + "EventCode": "0x2a", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : BL NCB on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCB", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0", + "EventCode": "0x2a", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : BL NCS on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCS", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0", + "EventCode": "0x2a", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : BL RSP on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a response", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0", + "EventCode": "0x2a", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : BL WB on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Request", + "EventCode": "0x2a", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : Non UPI IV Request : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject IV ring message", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop", + "EventCode": "0x2b", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : Allow Snoop : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : ANY0", + "EventCode": "0x2b", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : ANY0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Any condition listed in the WBQ0 Reject counter was true", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : HA", + "EventCode": "0x2b", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : HA : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way", + "EventCode": "0x2b", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : LLC OR SF Way : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Way conflict with another request that caused the reject", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : LLC Victim", + "EventCode": "0x2b", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : LLC Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match", + "EventCode": "0x2b", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : PhyAddr Match : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Address match with an outstanding request that was rejected.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : SF Victim", + "EventCode": "0x2b", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : SF Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Requests did not generate Snoop filter victim", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : Victim", + "EventCode": "0x2b", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 0 : AD REQ on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No AD VN0 credit for generating a request", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 0 : AD RSP on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No AD VN0 credit for generating a response", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 0 : Non UPI AK Request", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Can't inject AK ring message", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 0 : BL NCB on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for NCB", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 0 : BL NCS on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for NCS", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 0 : BL RSP on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for generating a response", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 0 : BL WB on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 0 : Non UPI IV Request", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Can't inject IV ring message", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 1 : Allow Snoop", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 1 : Allow Snoop : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 1 : ANY0", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Any condition listed in the RRQ0 Reject counter was true", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 1 : HA", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 1 : HA : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 1 : LLC OR SF Way", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 1 : LLC OR SF Way : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Way conflict with another request that caused the reject", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 1 : LLC Victim", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 1 : LLC Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 1 : PhyAddr Match", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 1 : PhyAddr Match : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Address match with an outstanding request that was rejected.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 1 : SF Victim", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 1 : SF Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Requests did not generate Snoop filter victim", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 1 : Victim", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 1 : Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 0 : AD REQ on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No AD VN0 credit for generating a request", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 0 : AD RSP on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No AD VN0 credit for generating a response", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 0 : Non UPI AK Request", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Can't inject AK ring message", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 0 : BL NCB on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for NCB", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 0 : BL NCS on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for NCS", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 0 : BL RSP on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for generating a response", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 0 : BL WB on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 0 : Non UPI IV Request", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Can't inject IV ring message", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 1 : Allow Snoop", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 1 : Allow Snoop : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 1 : ANY0", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Any condition listed in the WBQ0 Reject counter was true", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 1 : HA", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 1 : HA : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 1 : LLC OR SF Way", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 1 : LLC OR SF Way : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Way conflict with another request that caused the reject", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 1 : LLC Victim", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 1 : LLC Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 1 : PhyAddr Match", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 1 : PhyAddr Match : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Address match with an outstanding request that was rejected.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 1 : SF Victim", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 1 : SF Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Requests did not generate Snoop filter victim", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 1 : Victim", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 1 : Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : All", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.ALL", + "PerPkg": "1", + "PublicDescription": "Snoops Sent : All : Counts the number of snoops issued by the HA.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : Broadcast snoop for Local Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL", + "PerPkg": "1", + "PublicDescription": "Snoops Sent : Broadcast snoop for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA. This filter includes only requests coming from local sockets.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : Broadcast snoops for Remote Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE", + "PerPkg": "1", + "PublicDescription": "Snoops Sent : Broadcast snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA.This filter includes only requests coming from remote sockets.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : Directed snoops for Local Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", + "PerPkg": "1", + "PublicDescription": "Snoops Sent : Directed snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA. This filter includes only requests coming from local sockets.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : Directed snoops for Remote Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", + "PerPkg": "1", + "PublicDescription": "Snoops Sent : Directed snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA. This filter includes only requests coming from remote sockets.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : Broadcast or directed Snoops sent for Local Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL", + "PerPkg": "1", + "PublicDescription": "Snoops Sent : Broadcast or directed Snoops sent for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the local socket.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : Broadcast or directed Snoops sent for Remote Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE", + "PerPkg": "1", + "PublicDescription": "Snoops Sent : Broadcast or directed Snoops sent for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the remote socket.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received : RSPCNFLCT*", + "EventCode": "0x5c", + "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCT", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received : RSPCNFLCT* : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for snoops responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received : RspFwd", + "EventCode": "0x5c", + "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received : RspFwd : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of RspFwd to a CA request. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received : Rsp*Fwd*WB", + "EventCode": "0x5c", + "EventName": "UNC_CHA_SNOOP_RESP.RSPFWDWB", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received : Rsp*Fwd*WB : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "RspI Snoop Responses Received", + "EventCode": "0x5c", + "EventName": "UNC_CHA_SNOOP_RESP.RSPI", + "PerPkg": "1", + "PublicDescription": "Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data).", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "RspIFwd Snoop Responses Received", + "EventCode": "0x5c", + "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD", + "PerPkg": "1", + "PublicDescription": "Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "RspS Snoop Responses Received", + "EventCode": "0x5c", + "EventName": "UNC_CHA_SNOOP_RESP.RSPS", + "PerPkg": "1", + "PublicDescription": "Counts when a transaction with the opcode type RspS Snoop Response was received which indicates when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "RspSFwd Snoop Responses Received", + "EventCode": "0x5c", + "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD", + "PerPkg": "1", + "PublicDescription": "Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received : Rsp*WB", + "EventCode": "0x5c", + "EventName": "UNC_CHA_SNOOP_RESP.RSPWB", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received : Rsp*WB : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of RspIWB or RspSWB. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : RspCnflct", + "EventCode": "0x5d", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received Local : RspCnflct : Number of snoop responses received for a Local request : Filters for snoops responses of RspConflict to local CA requests. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : RspFwd", + "EventCode": "0x5d", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received Local : RspFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspFwd to local CA requests. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB", + "EventCode": "0x5d", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received Local : Rsp*FWD*WB : Number of snoop responses received for a Local request : Filters for a snoop response of Rsp*Fwd*WB to local CA requests. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : RspI", + "EventCode": "0x5d", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received Local : RspI : Number of snoop responses received for a Local request : Filters for snoops responses of RspI to local CA requests. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : RspIFwd", + "EventCode": "0x5d", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received Local : RspIFwd : Number of snoop responses received for a Local request : Filters for snoop responses of RspIFwd to local CA requests. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : RspS", + "EventCode": "0x5d", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received Local : RspS : Number of snoop responses received for a Local request : Filters for snoop responses of RspS to local CA requests. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : RspSFwd", + "EventCode": "0x5d", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received Local : RspSFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspSFwd to local CA requests. This is returned when a remote caching agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : Rsp*WB", + "EventCode": "0x5d", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received Local : Rsp*WB : Number of snoop responses received for a Local request : Filters for a snoop response of RspIWB or RspSWB to local CA requests. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Misc Snoop Responses Received : MtoI RspIDataM", + "EventCode": "0x6b", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM", + "EventCode": "0x6b", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit LLC", + "EventCode": "0x6b", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit SF", + "EventCode": "0x6b", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit LLC", + "EventCode": "0x6b", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit SF", + "EventCode": "0x6b", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ALL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "UMask": "0xc001ffff", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DDR Access", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DDR Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : SF/LLC Evictions", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.EVICT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : SF/LLC Evictions : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just Hits", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.HIT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Just Hits : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; All from Local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests from IA Cores", + "UMask": "0xc001ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts;CLFlush from Local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; CLFlush events that are initiated from the Core", + "UMask": "0xc8c7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts;CLFlushOpt from Local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; CLFlushOpt events that are initiated from the Core", + "UMask": "0xc8d7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; CRd from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Code read from local IA that misses in the snoop filter", + "UMask": "0xc80fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; CRd Pref from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter", + "UMask": "0xc88fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; DRd from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", + "UMask": "0xc817ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc837ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; DRd Opt from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read opt from local IA that misses in the snoop filter", + "UMask": "0xc827ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; DRd Opt Pref from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read opt prefetch from local IA that misses in the snoop filter", + "UMask": "0xc8a7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; DRd Pref from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read prefetch from local IA that misses in the snoop filter", + "UMask": "0xc897ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Hits from Local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "UMask": "0xc001fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; CRd hits from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Code read from local IA that hits in the snoop filter", + "UMask": "0xc80ffd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; CRd Pref hits from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Code read prefetch from local IA that hits in the snoop filter", + "UMask": "0xc88ffd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; DRd hits from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read from local IA that hits in the snoop filter", + "UMask": "0xc817fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to page walks that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc837fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; DRd Opt hits from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read opt from local IA that hits in the snoop filter", + "UMask": "0xc827fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; DRd Opt Pref hits from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read opt prefetch from local IA that hits in the snoop filter", + "UMask": "0xc8a7fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; DRd Pref hits from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read prefetch from local IA that hits in the snoop filter", + "UMask": "0xc897fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc47fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; LLCPrefCode hits from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Last level cache prefetch code read from local IA that hits in the snoop filter", + "UMask": "0xcccffd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; LLCPrefData hits from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Last level cache prefetch data read from local IA that hits in the snoop filter", + "UMask": "0xccd7fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; LLCPrefRFO hits from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Last level cache prefetch read for ownership from local IA that hits in the snoop filter", + "UMask": "0xccc7fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; RFO hits from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Read for ownership from local IA that hits in the snoop filter", + "UMask": "0xc807fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; RFO Pref hits from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that hits in the snoop filter", + "UMask": "0xc887fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts;ItoM from Local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; ItoM events that are initiated from the Core", + "UMask": "0xcc47ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcd47ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; LLCPrefCode from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Last level cache prefetch code read from local IA.", + "UMask": "0xcccfff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; LLCPrefData from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Last level cache prefetch data read from local IA.", + "UMask": "0xccd7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; LLCPrefRFO from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Last level cache prefetch read for ownership from local IA that misses in the snoop filter", + "UMask": "0xccc7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; misses from Local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts for CRd misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "PerPkg": "1", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode CRd", + "UMask": "0xc80ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "CRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRDMORPH_CXL_ACC", + "PerPkg": "1", + "UMask": "0x10c80b8201", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc80efe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; CRd Pref misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter", + "UMask": "0xc88ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc88efe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc88f7e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc80f7e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts for DRd misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "PerPkg": "1", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd", + "UMask": "0xc817fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDMORPH_CXL_ACC", + "PerPkg": "1", + "UMask": "0x10c8138201", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc837fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts for DRds issued by IA Cores targeting DDR Mem that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", + "PerPkg": "1", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target DDR memory", + "UMask": "0xc8178601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts for DRd misses from local IA targeting local memory", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "PerPkg": "1", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target local memory", + "UMask": "0xc816fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8168601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8168a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; DRd Opt misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read opt from local IA that misses in the snoop filter", + "UMask": "0xc827fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; DRd Opt Pref misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read opt prefetch from local IA that misses in the snoop filter", + "UMask": "0xc8a7fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts for DRds issued by iA Cores targeting PMM Mem that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM", + "PerPkg": "1", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target PMM memory", + "UMask": "0xc8178a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts for DRd Pref misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", + "PerPkg": "1", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF", + "UMask": "0xc897fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_DDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8978601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts for DRd Pref misses from local IA targeting local memory", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", + "PerPkg": "1", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target local memory", + "UMask": "0xc896fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_DDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8968601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_PMM", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8968a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_PMM", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8978a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts for DRd Pref misses from local IA targeting remote memory", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", + "PerPkg": "1", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target remote memory", + "UMask": "0xc8977e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_DDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8970601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_PMM", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8970a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts for DRd misses from local IA targeting remote memory", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "PerPkg": "1", + "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and target remote memory", + "UMask": "0xc8177e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8170601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8170a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc47fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; LLCPrefCode misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Last level cache prefetch code read from local IA that misses in the snoop filter", + "UMask": "0xcccffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "LLC Prefetch Code transactions issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE_CXL_ACC", + "PerPkg": "1", + "UMask": "0x10cccf8201", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; LLCPrefData misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Last level cache prefetch data read from local IA that misses in the snoop filter", + "UMask": "0xccd7fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; LLCPrefRFO misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Last level cache prefetch read for ownership from local IA that misses in the snoop filter", + "UMask": "0xccc7fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8668601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_PMM", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8668a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86e8601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_PMM", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86e8a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8670601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_PMM", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8670a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86f0601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_PMM", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86f0a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; RFO misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Read for ownership from local IA that misses in the snoop filter", + "UMask": "0xc807fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "RFO and L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFOMORPH_CXL_ACC", + "PerPkg": "1", + "UMask": "0x10c8038201", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts RFO misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Read for ownership from local IA that misses in the snoop filter", + "UMask": "0xc806fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; RFO pref misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter", + "UMask": "0xc887fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; RFO prefetch misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter", + "UMask": "0xc886fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; RFO prefetch misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter", + "UMask": "0xc8877e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; RFO misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts Read for ownership from local IA that misses in the snoop filter", + "UMask": "0xc8077e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc877de01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc867fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8678601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_PMM", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8678a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86f8601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_PMM", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86f8a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc87fde01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; RFO from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Read for ownership from local IA that misses in the snoop filter", + "UMask": "0xc807ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; RFO pref from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter", + "UMask": "0xc887ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts;SpecItoM from Local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; SpecItoM events that are initiated from the Core", + "UMask": "0xcc57ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE", + "PerPkg": "1", + "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc3fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI", + "PerPkg": "1", + "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc37ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE", + "PerPkg": "1", + "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc2fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI", + "PerPkg": "1", + "PublicDescription": "WbMtoIs issued by iA Cores . (Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc27ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI", + "PerPkg": "1", + "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc67ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc867ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; All from local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8c3ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Hits from local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; ItoM hits from local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc43fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcd43fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; RdCur and FsRdCur hits from local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8f3fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; RFO hits from local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc803fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts for ItoM from local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "PerPkg": "1", + "PublicDescription": "Inserts into the TOR from local IO with the opcode ItoM", + "UMask": "0xcc43ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts for ItoMCacheNears from IO devices.", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "Inserts into the TOR from local IO devices with the opcode ItoMCacheNears. This event indicates a partial write request.", + "UMask": "0xcd43ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Misses from local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; ItoM misses from local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc43fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcd43fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; RdCur and FsRdCur misses from local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8f3fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; RFO misses from local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc803fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts for RdCur from local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "Inserts into the TOR from local IO with the opcode RdCur", + "UMask": "0xc8f3ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; RFO from local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc803ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc23ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : IPQ", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IPQ", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : IPQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : IRQ - iA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : IRQ - iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : From an iA Core", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : IRQ - Non iA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : IRQ - Non iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just ISOC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ISOC", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Just ISOC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just Local Targets", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Just Local Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All from Local iA and IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All from Local iA and IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All locally initiated requests", + "UMask": "0xc000ff05", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All from Local iA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All from Local iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All locally initiated requests from iA Cores", + "UMask": "0xc000ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All from Local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All from Local IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All locally generated IO traffic", + "UMask": "0xc000ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just Misses", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.MISS", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Just Misses : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : MMCFG Access", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.MMCFG", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : MMCFG Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : MMIO Access", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.MMIO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : MMIO Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just NearMem", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.NEARMEM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Just NearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just NonCoherent", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.NONCOH", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Just NonCoherent : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just NotNearMem", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Just NotNearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : PMM Access", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.PMM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PM Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : PRQ - IOSF", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PRQ - IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : From a PCIe Device", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : PRQ - Non IOSF", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PRQ - Non IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just Remote Targets", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.REMOTE_TGT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Just Remote Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All from Remote", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All from Remote : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All remote requests (e.g. snoops, writebacks) that came from remote sockets", + "UMask": "0xc001ffc8", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All Snoops from Remote", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.REM_SNPS", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All Snoops from Remote : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All snoops to this LLC that came from remote sockets", + "UMask": "0xc001ff08", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RRQ", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.RRQ", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RRQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; All Snoops from Remote", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.SNPS_FROM_REM", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. All snoops to this LLC that came from remote sockets.", + "UMask": "0xc001ff08", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WBQ", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.WBQ", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WBQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "UMask": "0xc001ffff", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DDR Access", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DDR Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : SF/LLC Evictions", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : SF/LLC Evictions : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just Hits", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Just Hits : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; All from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8c7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8d7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; CRd from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Code read from local IA that misses in the snoop filter", + "UMask": "0xc80fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; CRd Pref from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter", + "UMask": "0xc88fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; DRd from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", + "UMask": "0xc817ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc837ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; DRd Opt from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read opt from local IA that misses in the snoop filter", + "UMask": "0xc827ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; DRd Opt Pref from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read opt prefetch from local IA that misses in the snoop filter", + "UMask": "0xc8a7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; DRd Pref from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter", + "UMask": "0xc897ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Hits from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; CRd hits from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Code read from local IA that hits in the snoop filter", + "UMask": "0xc80ffd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; CRd Pref hits from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that hits in the snoop filter", + "UMask": "0xc88ffd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; DRd hits from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read from local IA that hits in the snoop filter", + "UMask": "0xc817fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc837fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; DRd Opt hits from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read opt from local IA that hits in the snoop filter", + "UMask": "0xc827fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; DRd Opt Pref hits from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read opt prefetch from local IA that hits in the snoop filter", + "UMask": "0xc8a7fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; DRd Pref hits from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that hits in the snoop filter", + "UMask": "0xc897fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc47fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; LLCPrefCode hits from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Last level cache prefetch code read from local IA that hits in the snoop filter", + "UMask": "0xcccffd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; LLCPrefData hits from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Last level cache prefetch data read from local IA that hits in the snoop filter", + "UMask": "0xccd7fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; LLCPrefRFO hits from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Last level cache prefetch read for ownership from local IA that hits in the snoop filter", + "UMask": "0xccc7fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; RFO hits from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Read for ownership from local IA that hits in the snoop filter", + "UMask": "0xc807fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; RFO Pref hits from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that hits in the snoop filter", + "UMask": "0xc887fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc47ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcd47ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; LLCPrefCode from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Last level cache prefetch data read from local IA.", + "UMask": "0xcccfff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; LLCPrefData from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Last level cache prefetch data read from local IA that misses in the snoop filter", + "UMask": "0xccd7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; LLCPrefRFO from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Last level cache prefetch read for ownership from local IA that misses in the snoop filter", + "UMask": "0xccc7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Misses from Local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; CRd misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Code read from local IA that misses in the snoop filter", + "UMask": "0xc80ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for CRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRDMORPH_CXL_ACC", + "PerPkg": "1", + "UMask": "0x10c80b8201", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc80efe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; CRd Pref misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter", + "UMask": "0xc88ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc88efe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc88f7e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc80f7e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for DRd misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "PerPkg": "1", + "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd", + "UMask": "0xc817fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for DRds and equivalent opcodes issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDMORPH_CXL_ACC", + "PerPkg": "1", + "UMask": "0x10c8138201", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc837fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for DRds issued by iA Cores targeting DDR Mem that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", + "PerPkg": "1", + "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target DDR memory", + "UMask": "0xc8178601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for DRd misses from local IA targeting local memory", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL", + "PerPkg": "1", + "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target local memory", + "UMask": "0xc816fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8168601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8168a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; DRd Opt misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read opt from local IA that misses in the snoop filter", + "UMask": "0xc827fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; DRd Opt Pref misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read opt prefetch from local IA that misses in the snoop filter", + "UMask": "0xc8a7fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for DRds issued by iA Cores targeting PMM Mem that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM", + "PerPkg": "1", + "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target PMM memory", + "UMask": "0xc8178a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter", + "UMask": "0xc897fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8978601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter", + "UMask": "0xc896fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8968601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8968a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8978a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter", + "UMask": "0xc8977e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8970601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8970a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for DRd misses from local IA targeting remote memory", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE", + "PerPkg": "1", + "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target remote memory", + "UMask": "0xc8177e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8170601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8170a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc47fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; LLCPrefCode misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Last level cache prefetch code read from local IA that misses in the snoop filter", + "UMask": "0xcccffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for LLC Prefetch Code transactions issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE_CXL_ACC", + "PerPkg": "1", + "UMask": "0x10cccf8201", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; LLCPrefData misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Last level cache prefetch data read from local IA that misses in the snoop filter", + "UMask": "0xccd7fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; LLCPrefRFO misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Last level cache prefetch read for ownership from local IA that misses in the snoop filter", + "UMask": "0xccc7fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8668601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8668a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86e8601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86e8a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8670601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8670a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86f0601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86f0a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; RFO misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Read for ownership from local IA that misses in the snoop filter", + "UMask": "0xc807fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for RFO and L2 RFO prefetches issued from an IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFOMORPH_CXL_ACC", + "PerPkg": "1", + "UMask": "0x10c8038201", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; RFO misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Read for ownership from local IA that misses in the snoop filter", + "UMask": "0xc806fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter", + "UMask": "0xc887fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter", + "UMask": "0xc886fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter", + "UMask": "0xc8877e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; RFO misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Read for ownership from local IA that misses in the snoop filter", + "UMask": "0xc8077e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc877de01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc867fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8678601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8678a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86f8601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86f8a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc87fde01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; RFO from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Read for ownership from local IA that misses in the snoop filter", + "UMask": "0xc807ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; RFO prefetch from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter", + "UMask": "0xc887ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc57ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc27ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc867ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; All from local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Devices", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8c3ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Hits from local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; ITOM hits from local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc43fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcd43fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; RdCur and FsRdCur hits from local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8f3fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; RFO hits from local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc803fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; ITOM from local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc43ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcd43ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Misses from local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; ITOM misses from local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc43fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcd43fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; RdCur and FsRdCur misses from local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8f3fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; RFO misses from local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc803fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; RdCur and FsRdCur from local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8f3ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; ItoM from local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc803ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc23ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : IPQ", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : IPQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : IRQ - iA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : IRQ - iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : From an iA Core", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : IRQ - Non iA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : IRQ - Non iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just ISOC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Just ISOC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just Local Targets", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Just Local Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All from Local iA and IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All from Local iA and IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All locally initiated requests", + "UMask": "0xc000ff05", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All from Local iA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All from Local iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All locally initiated requests from iA Cores", + "UMask": "0xc000ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All from Local IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All locally generated IO traffic", + "UMask": "0xc000ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just Misses", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Just Misses : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : MMCFG Access", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : MMCFG Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : MMIO Access", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.MMIO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : MMIO Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just NearMem", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Just NearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just NonCoherent", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Just NonCoherent : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just NotNearMem", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Just NotNearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : PMM Access", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PMM Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : PRQ - IOSF", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PRQ - IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : From a PCIe Device", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : PRQ - Non IOSF", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PRQ - Non IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just Remote Targets", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.REMOTE_TGT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Just Remote Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All from Remote", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.REM_ALL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All from Remote : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All remote requests (e.g. snoops, writebacks) that came from remote sockets", + "UMask": "0xc001ffc8", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All Snoops from Remote", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.REM_SNPS", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All Snoops from Remote : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All snoops to this LLC that came from remote sockets", + "UMask": "0xc001ff08", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RRQ", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.RRQ", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RRQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; All Snoops from Remote", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.SNPS_FROM_REM", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. All snoops to this LLC that came from remote sockets.", + "UMask": "0xc001ff08", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WBQ", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.WBQ", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WBQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "WbPushMtoI : Pushed to LLC", + "EventCode": "0x56", + "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC", + "PerPkg": "1", + "PublicDescription": "WbPushMtoI : Pushed to LLC : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was able to push WbPushMToI to LLC", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "WbPushMtoI : Pushed to Memory", + "EventCode": "0x56", + "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM", + "PerPkg": "1", + "PublicDescription": "WbPushMtoI : Pushed to Memory : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0", + "EventCode": "0x5a", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC0 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 0 only.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1", + "EventCode": "0x5a", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC1 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 1 only.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2", + "EventCode": "0x5a", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC2 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 2 only.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3", + "EventCode": "0x5a", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC3 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 3 only.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4", + "EventCode": "0x5a", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC4 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 4 only.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5", + "EventCode": "0x5a", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC5 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 5 only.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT", + "PerPkg": "1", + "PublicDescription": "XPT Prefetches : Dropped (on 0?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD", + "PerPkg": "1", + "PublicDescription": "XPT Prefetches : Dropped (on 0?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT", + "PerPkg": "1", + "PublicDescription": "XPT Prefetches : Dropped (on 1?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD", + "PerPkg": "1", + "PublicDescription": "XPT Prefetches : Dropped (on 1?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "XPT Prefetches : Sent (on 0?)", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.SENT0", + "PerPkg": "1", + "PublicDescription": "XPT Prefetches : Sent (on 0?) : Number of XPT prefetches sent", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "XPT Prefetches : Sent (on 1?)", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.SENT1", + "PerPkg": "1", + "PublicDescription": "XPT Prefetches : Sent (on 1?) : Number of XPT prefetches sent", + "UMask": "0x10", + "Unit": "CHA" + } +] diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cxl.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cxl.json new file mode 100644 index 000000000000..f3e84fd88de3 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cxl.json @@ -0,0 +1,450 @@ +[ + { + "BriefDescription": "Counts the number of lfclk ticks", + "EventCode": "0x01", + "EventName": "UNC_CXLCM_CLOCKTICKS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of Allocation to Mem Rxx AGF 0", + "EventCode": "0x43", + "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_DATA", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of Allocation to Cache Req AGF0", + "EventCode": "0x43", + "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_REQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of Allocation to Cache Rsp AGF", + "EventCode": "0x43", + "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_REQ1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of Allocation to Cache Data AGF", + "EventCode": "0x43", + "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_RSP0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of Allocation to Cache Rsp AGF", + "EventCode": "0x43", + "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_RSP1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of Allocation to Cache Req AGF 1", + "EventCode": "0x43", + "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.MEM_DATA", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of Allocation to Mem Data AGF", + "EventCode": "0x43", + "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.MEM_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Count the number of Flits with AK set", + "EventCode": "0x4b", + "EventName": "UNC_CXLCM_RxC_FLITS.AK_HDR", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Count the number of Flits with BE set", + "EventCode": "0x4b", + "EventName": "UNC_CXLCM_RxC_FLITS.BE_HDR", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Count the number of control flits received", + "EventCode": "0x4b", + "EventName": "UNC_CXLCM_RxC_FLITS.CTRL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Count the number of Headerless flits received", + "EventCode": "0x4b", + "EventName": "UNC_CXLCM_RxC_FLITS.NO_HDR", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Count the number of protocol flits received", + "EventCode": "0x4b", + "EventName": "UNC_CXLCM_RxC_FLITS.PROT", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Count the number of Flits with SZ set", + "EventCode": "0x4b", + "EventName": "UNC_CXLCM_RxC_FLITS.SZ_HDR", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Count the number of flits received", + "EventCode": "0x4b", + "EventName": "UNC_CXLCM_RxC_FLITS.VALID", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Count the number of valid messages in the flit", + "EventCode": "0x4b", + "EventName": "UNC_CXLCM_RxC_FLITS.VALID_MSG", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Count the number of CRC errors detected", + "EventCode": "0x40", + "EventName": "UNC_CXLCM_RxC_MISC.CRC_ERRORS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Count the number of Init flits sent", + "EventCode": "0x40", + "EventName": "UNC_CXLCM_RxC_MISC.INIT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Count the number of LLCRD flits sent", + "EventCode": "0x40", + "EventName": "UNC_CXLCM_RxC_MISC.LLCRD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Count the number of Retry flits sent", + "EventCode": "0x40", + "EventName": "UNC_CXLCM_RxC_MISC.RETRY", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of cycles the Packing Buffer is Full", + "EventCode": "0x52", + "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.CACHE_DATA", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of cycles the Packing Buffer is Full", + "EventCode": "0x52", + "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.CACHE_REQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of cycles the Packing Buffer is Full", + "EventCode": "0x52", + "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.CACHE_RSP", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of cycles the Packing Buffer is Full", + "EventCode": "0x52", + "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.MEM_DATA", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of cycles the Packing Buffer is Full", + "EventCode": "0x52", + "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.MEM_REQ", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of Allocation to Cache Data Packing buffer", + "EventCode": "0x41", + "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.CACHE_DATA", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of Allocation to Cache Req Packing buffer", + "EventCode": "0x41", + "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.CACHE_REQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of Allocation to Cache Rsp Packing buffer", + "EventCode": "0x41", + "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.CACHE_RSP", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of Allocation to Mem Data Packing buffer", + "EventCode": "0x41", + "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of Allocation to Mem Rxx Packing buffer", + "EventCode": "0x41", + "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_REQ", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of cycles of Not Empty for Cache Data Packing buffer", + "EventCode": "0x42", + "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.CACHE_DATA", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of cycles of Not Empty for Cache Req Packing buffer", + "EventCode": "0x42", + "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.CACHE_REQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of cycles of Not Empty for Cache Rsp Packing buffer", + "EventCode": "0x42", + "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.CACHE_RSP", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of cycles of Not Empty for Mem Data Packing buffer", + "EventCode": "0x42", + "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.MEM_DATA", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of cycles of Not Empty for Mem Rxx Packing buffer", + "EventCode": "0x42", + "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.MEM_REQ", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Count the number of Flits with AK set", + "EventCode": "0x05", + "EventName": "UNC_CXLCM_TxC_FLITS.AK_HDR", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Count the number of Flits with BE set", + "EventCode": "0x05", + "EventName": "UNC_CXLCM_TxC_FLITS.BE_HDR", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Count the number of control flits packed", + "EventCode": "0x05", + "EventName": "UNC_CXLCM_TxC_FLITS.CTRL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Count the number of Headerless flits packed", + "EventCode": "0x05", + "EventName": "UNC_CXLCM_TxC_FLITS.NO_HDR", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Count the number of protocol flits packed", + "EventCode": "0x05", + "EventName": "UNC_CXLCM_TxC_FLITS.PROT", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Count the number of Flits with SZ set", + "EventCode": "0x05", + "EventName": "UNC_CXLCM_TxC_FLITS.SZ_HDR", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Count the number of flits packed", + "EventCode": "0x05", + "EventName": "UNC_CXLCM_TxC_FLITS.VALID", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of Allocation to Cache Data Packing buffer", + "EventCode": "0x02", + "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_DATA", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of Allocation to Cache Req Packing buffer", + "EventCode": "0x02", + "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_REQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of Allocation to Cache Rsp1 Packing buffer", + "EventCode": "0x02", + "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_REQ1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of Allocation to Cache Rsp0 Packing buffer", + "EventCode": "0x02", + "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_RSP0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of Allocation to Cache Req Packing buffer", + "EventCode": "0x02", + "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_RSP1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of Allocation to Mem Data Packing buffer", + "EventCode": "0x02", + "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.MEM_DATA", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of Allocation to Mem Rxx Packing buffer", + "EventCode": "0x02", + "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.MEM_REQ", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Counts the number of uclk ticks", + "EventCode": "0x01", + "EventName": "UNC_CXLDP_CLOCKTICKS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CXLDP" + }, + { + "BriefDescription": "Number of Allocation to M2S Data AGF", + "EventCode": "0x02", + "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.M2S_DATA", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CXLDP" + }, + { + "BriefDescription": "Number of Allocation to M2S Req AGF", + "EventCode": "0x02", + "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.M2S_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CXLDP" + }, + { + "BriefDescription": "Number of Allocation to U2C Data AGF", + "EventCode": "0x02", + "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_DATA", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CXLDP" + }, + { + "BriefDescription": "Number of Allocation to U2C Req AGF", + "EventCode": "0x02", + "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_REQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CXLDP" + }, + { + "BriefDescription": "Number of Allocation to U2C Rsp AGF 0", + "EventCode": "0x02", + "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_RSP0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CXLDP" + }, + { + "BriefDescription": "Number of Allocation to U2C Rsp AGF 1", + "EventCode": "0x02", + "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_RSP1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CXLDP" + } +] diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-interconnect.json new file mode 100644 index 000000000000..08faf38115d9 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-interconnect.json @@ -0,0 +1,6199 @@ +[ + { + "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory.", + "EventCode": "0x0f", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", + "PerPkg": "1", + "PublicDescription": "Total IRP occupancy of inbound read and write requests to coherent memory. This is effectively the sum of read occupancy and write occupancy.", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "IRP Clockticks", + "EventCode": "0x01", + "EventName": "UNC_I_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Number of IRP clock cycles while the event is enabled", + "Unit": "IRP" + }, + { + "BriefDescription": "FAF RF full", + "EventCode": "0x17", + "EventName": "UNC_I_FAF_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "FAF - request insert from TC.", + "EventCode": "0x18", + "EventName": "UNC_I_FAF_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "FAF occupancy", + "EventCode": "0x19", + "EventName": "UNC_I_FAF_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "FAF allocation -- sent to ADQ", + "EventCode": "0x16", + "EventName": "UNC_I_FAF_TRANSACTIONS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", + "EventCode": "0x20", + "EventName": "UNC_I_IRP_ALL.EVICTS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)", + "EventCode": "0x20", + "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", + "EventCode": "0x20", + "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary", + "EventCode": "0x1e", + "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary", + "EventCode": "0x1e", + "EventName": "UNC_I_MISC0.2ND_RD_INSERT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary", + "EventCode": "0x1e", + "EventName": "UNC_I_MISC0.2ND_WR_INSERT", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", + "EventCode": "0x1e", + "EventName": "UNC_I_MISC0.FAST_REJ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests", + "EventCode": "0x1e", + "EventName": "UNC_I_MISC0.FAST_REQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary", + "EventCode": "0x1e", + "EventName": "UNC_I_MISC0.FAST_XFER", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary", + "EventCode": "0x1e", + "EventName": "UNC_I_MISC0.PF_ACK_HINT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch", + "EventCode": "0x1e", + "EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Lost Forward", + "EventCode": "0x1f", + "EventName": "UNC_I_MISC1.LOST_FWD", + "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Received Invalid", + "EventCode": "0x1f", + "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", + "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Received Invalid : Secondary received a transfer that did not have sufficient MESI state", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Received Valid", + "EventCode": "0x1f", + "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", + "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Received Valid : Secondary received a transfer that did have sufficient MESI state", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line", + "EventCode": "0x1f", + "EventName": "UNC_I_MISC1.SLOW_E", + "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Slow Transfer of E Line : Secondary received a transfer that did have sufficient MESI state", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line", + "EventCode": "0x1f", + "EventName": "UNC_I_MISC1.SLOW_I", + "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Slow Transfer of I Line : Snoop took cacheline ownership before write from data was committed.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line", + "EventCode": "0x1f", + "EventName": "UNC_I_MISC1.SLOW_M", + "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Slow Transfer of M Line : Snoop took cacheline ownership before write from data was committed.", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line", + "EventCode": "0x1f", + "EventName": "UNC_I_MISC1.SLOW_S", + "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Slow Transfer of S Line : Secondary received a transfer that did not have sufficient MESI state", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO", + "UMask": "0x7e", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache", + "UMask": "0x74", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache", + "UMask": "0x72", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache", + "UMask": "0x78", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that miss the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_MISS", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that miss the IIO cache", + "UMask": "0x71", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : Hit E or S", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_ES", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : Hit I", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_I", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : Hit M", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_M", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : Miss", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.MISS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : SnpCode", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPCODE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : SnpData", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPDATA", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : SnpInv", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPINV", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound write (fast path) requests received by the IRP.", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "PerPkg": "1", + "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "AK Egress Allocations", + "EventCode": "0x0b", + "EventName": "UNC_I_TxC_AK_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL DRS Egress Cycles Full", + "EventCode": "0x05", + "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL DRS Egress Inserts", + "EventCode": "0x02", + "EventName": "UNC_I_TxC_BL_DRS_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL DRS Egress Occupancy", + "EventCode": "0x08", + "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCB Egress Cycles Full", + "EventCode": "0x06", + "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCB Egress Inserts", + "EventCode": "0x03", + "EventName": "UNC_I_TxC_BL_NCB_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCB Egress Occupancy", + "EventCode": "0x09", + "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCS Egress Cycles Full", + "EventCode": "0x07", + "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCS Egress Inserts", + "EventCode": "0x04", + "EventName": "UNC_I_TxC_BL_NCS_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCS Egress Occupancy", + "EventCode": "0x0a", + "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", + "EventCode": "0x1c", + "EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": ": Counts the number times when it is not possible to issue a request to the M2PCIe because there are no Egress Credits available on AD0, A1 or AD0AD1 both. Stalls on both AD0 and AD1 will count as 2", + "Unit": "IRP" + }, + { + "BriefDescription": "No AD0 Egress Credits Stalls", + "EventCode": "0x1a", + "EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "No AD0 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD0 Egress Credits available.", + "Unit": "IRP" + }, + { + "BriefDescription": "No AD1 Egress Credits Stalls", + "EventCode": "0x1b", + "EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "No AD1 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD1 Egress Credits available.", + "Unit": "IRP" + }, + { + "BriefDescription": "No BL Egress Credit Stalls", + "EventCode": "0x1d", + "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "No BL Egress Credit Stalls : Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "EventCode": "0x0d", + "EventName": "UNC_I_TxS_DATA_INSERTS_NCB", + "PerPkg": "1", + "PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "EventCode": "0x0e", + "EventName": "UNC_I_TxS_DATA_INSERTS_NCS", + "PerPkg": "1", + "PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Request Queue Occupancy", + "EventCode": "0x0c", + "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Outbound Request Queue Occupancy : Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.", + "Unit": "IRP" + }, + { + "BriefDescription": "M2M Clockticks", + "EventCode": "0x01", + "EventName": "UNC_M2M_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Clockticks of the mesh to memory (M2M)", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Clockticks", + "EventCode": "0xc0", + "EventName": "UNC_M2M_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled", + "EventCode": "0x17", + "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles when direct to core mode, which bypasses the CHA, was disabled : Non Cisgress", + "EventCode": "0x17", + "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE.NON_CISGRESS", + "PerPkg": "1", + "PublicDescription": "Cycles when direct to core mode, which bypasses the CHA, was disabled : Non Cisgress : Counts the number of time non cisgress D2C was not honoured by egress due to directory state constraints", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Counts the time when FM didn? do d2c for fill reads (cross tile case)", + "EventCode": "0x4a", + "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number of reads in which direct to core transaction were overridden", + "EventCode": "0x18", + "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "Number of reads in which direct to core transaction was overridden : Cisgress", + "EventCode": "0x18", + "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE.CISGRESS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Number of reads in which direct to core transaction was overridden : 2LM Hit?", + "EventCode": "0x18", + "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE.PMM_HIT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number of times a direct to UPI transaction was overridden.", + "EventCode": "0x1C", + "EventName": "UNC_M2M_DIRECT2UPITXN_OVERRIDE.PMM_HIT", + "PerPkg": "1", + "PublicDescription": "Number of times a direct to UPI transaction was overridden. : Counts the number of times D2K wasn't honored even though the incoming request had d2k set", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden", + "EventCode": "0x1b", + "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles when direct to Intel UPI was disabled", + "EventCode": "0x1a", + "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles when Direct2UPI was Disabled : Cisgress D2U Ignored", + "EventCode": "0x1A", + "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE.CISGRESS", + "PerPkg": "1", + "PublicDescription": "Cycles when Direct2UPI was Disabled : Cisgress D2U Ignored : Counts cisgress d2K that was not honored due to directory constraints", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles when Direct2UPI was Disabled : Egress Ignored D2U", + "EventCode": "0x1A", + "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE.EGRESS", + "PerPkg": "1", + "PublicDescription": "Cycles when Direct2UPI was Disabled : Egress Ignored D2U : Counts the number of time D2K was not honoured by egress due to directory state constraints", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles when Direct2UPI was Disabled : Non Cisgress D2U Ignored", + "EventCode": "0x1A", + "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE.NON_CISGRESS", + "PerPkg": "1", + "PublicDescription": "Cycles when Direct2UPI was Disabled : Non Cisgress D2U Ignored : Counts non cisgress d2K that was not honored due to directory constraints", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages sent direct to the Intel UPI", + "EventCode": "0x19", + "EventName": "UNC_M2M_DIRECT2UPI_TAKEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of times egress did D2K (Direct to KTI)", + "UMask": "0x7", + "Unit": "M2M" + }, + { + "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden", + "EventCode": "0x1c", + "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "Number of times a direct to UPI transaction was overridden.", + "EventCode": "0x1C", + "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE.CISGRESS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit : On NonDirty Line in A State", + "EventCode": "0x1d", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit : On NonDirty Line in I State", + "EventCode": "0x1d", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit : On NonDirty Line in L State", + "EventCode": "0x1d", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit : On NonDirty Line in S State", + "EventCode": "0x1d", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit : On Dirty Line in A State", + "EventCode": "0x1d", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit : On Dirty Line in I State", + "EventCode": "0x1d", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit : On Dirty Line in L State", + "EventCode": "0x1d", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit : On Dirty Line in S State", + "EventCode": "0x1d", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)", + "EventCode": "0x20", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of hit data returns to egress with any directory to non persistent memory", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)", + "EventCode": "0x20", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", + "PerPkg": "1", + "PublicDescription": "Counts the number of hit data returns to egress with directory A to non persistent memory", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)", + "EventCode": "0x20", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", + "PerPkg": "1", + "PublicDescription": "Counts the number of hit data returns to egress with directory I to non persistent memory", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)", + "EventCode": "0x20", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", + "PerPkg": "1", + "PublicDescription": "Counts the number of hit data returns to egress with directory S to non persistent memory", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss : On NonDirty Line in A State", + "EventCode": "0x1e", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss : On NonDirty Line in I State", + "EventCode": "0x1e", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss : On NonDirty Line in L State", + "EventCode": "0x1e", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss : On NonDirty Line in S State", + "EventCode": "0x1e", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss : On Dirty Line in A State", + "EventCode": "0x1e", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss : On Dirty Line in I State", + "EventCode": "0x1e", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss : On Dirty Line in L State", + "EventCode": "0x1e", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss : On Dirty Line in S State", + "EventCode": "0x1e", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from A to I", + "EventCode": "0x21", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I", + "PerPkg": "1", + "UMask": "0x320", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from A to S", + "EventCode": "0x21", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S", + "PerPkg": "1", + "UMask": "0x340", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from/to Any state", + "EventCode": "0x21", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", + "PerPkg": "1", + "UMask": "0x301", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.A_TO_I_HIT_NON_PMM", + "PerPkg": "1", + "PublicDescription": "Counts 1lm or 2lm hit data returns that would result in directory update from A to I to non persistent memory (DRAM or HBM)", + "UMask": "0x120", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.A_TO_I_MISS_NON_PMM", + "PerPkg": "1", + "PublicDescription": "Counts 2lm miss data returns that would result in directory update from A to I to non persistent memory (DRAM or HBM)", + "UMask": "0x220", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.A_TO_S_HIT_NON_PMM", + "PerPkg": "1", + "PublicDescription": "Counts 1lm or 2lm hit data returns that would result in directory update from A to S to non persistent memory (DRAM or HBM)", + "UMask": "0x140", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.A_TO_S_MISS_NON_PMM", + "PerPkg": "1", + "PublicDescription": "Counts 2lm miss data returns that would result in directory update from A to S to non persistent memory (DRAM or HBM)", + "UMask": "0x240", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.HIT_NON_PMM", + "PerPkg": "1", + "PublicDescription": "Counts any 1lm or 2lm hit data return that would result in directory update to non persistent memory (DRAM or HBM)", + "UMask": "0x101", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from I to A", + "EventCode": "0x21", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A", + "PerPkg": "1", + "UMask": "0x304", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from I to S", + "EventCode": "0x21", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S", + "PerPkg": "1", + "UMask": "0x302", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.I_TO_A_HIT_NON_PMM", + "PerPkg": "1", + "PublicDescription": "Counts 1lm or 2lm hit data returns that would result in directory update from I to A to non persistent memory (DRAM or HBM)", + "UMask": "0x104", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.I_TO_A_MISS_NON_PMM", + "PerPkg": "1", + "PublicDescription": "Counts 2lm miss data returns that would result in directory update from I to A to non persistent memory (DRAM or HBM)", + "UMask": "0x204", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.I_TO_S_HIT_NON_PMM", + "PerPkg": "1", + "PublicDescription": "Counts 1lm or 2lm hit data returns that would result in directory update from I to S to non persistent memory (DRAM or HBM)", + "UMask": "0x102", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.I_TO_S_MISS_NON_PMM", + "PerPkg": "1", + "PublicDescription": "Counts 2lm miss data returns that would result in directory update from I to S to non persistent memory (DRAM or HBM)", + "UMask": "0x202", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.MISS_NON_PMM", + "PerPkg": "1", + "PublicDescription": "Counts any 2lm miss data return that would result in directory update to non persistent memory (DRAM or HBM)", + "UMask": "0x201", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from S to A", + "EventCode": "0x21", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A", + "PerPkg": "1", + "UMask": "0x310", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from S to I", + "EventCode": "0x21", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I", + "PerPkg": "1", + "UMask": "0x308", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.S_TO_A_HIT_NON_PMM", + "PerPkg": "1", + "PublicDescription": "Counts 1lm or 2lm hit data returns that would result in directory update from S to A to non persistent memory (DRAM or HBM)", + "UMask": "0x110", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.S_TO_A_MISS_NON_PMM", + "PerPkg": "1", + "PublicDescription": "Counts 2lm miss data returns that would result in directory update from S to A to non persistent memory (DRAM or HBM)", + "UMask": "0x210", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.S_TO_I_HIT_NON_PMM", + "PerPkg": "1", + "PublicDescription": "Counts 1lm or 2lm hit data returns that would result in directory update from S to I to non persistent memory (DRAM or HBM)", + "UMask": "0x108", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.S_TO_I_MISS_NON_PMM", + "PerPkg": "1", + "PublicDescription": "Counts 2lm miss data returns that would result in directory update from S to I to non persistent memory (DRAM or HBM)", + "UMask": "0x208", + "Unit": "M2M" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Down", + "EventCode": "0xba", + "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x80000004", + "Unit": "M2M" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Up", + "EventCode": "0xba", + "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x80000001", + "Unit": "M2M" + }, + { + "BriefDescription": "Count when Starve Glocab counter is at 7", + "EventCode": "0x44", + "EventName": "UNC_M2M_IGR_STARVE_WINNER.MASK7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Reads to iMC issued", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.ALL", + "PerPkg": "1", + "UMask": "0x304", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.CH0.TO_NM1LM", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.CH0.TO_NM1LM", + "PerPkg": "1", + "UMask": "0x108", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.CH0.TO_NMCache", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.CH0.TO_NMCache", + "PerPkg": "1", + "UMask": "0x110", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.CH0_ALL", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.CH0_ALL", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "UMask": "0x104", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.CH0_FROM_TGR", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR", + "PerPkg": "1", + "UMask": "0x140", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.CH0_ISOCH", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.CH0_ISOCH", + "PerPkg": "1", + "UMask": "0x102", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.CH0_NORMAL", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.CH0_NORMAL", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "UMask": "0x101", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE", + "PerPkg": "1", + "UMask": "0x110", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM", + "PerPkg": "1", + "UMask": "0x108", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.CH0_TO_PMM", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.CH0_TO_PMM", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "UMask": "0x120", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.CH1.TO_NM1LM", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.CH1.TO_NM1LM", + "PerPkg": "1", + "UMask": "0x208", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.CH1.TO_NMCache", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.CH1.TO_NMCache", + "PerPkg": "1", + "UMask": "0x210", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.CH1_ALL", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.CH1_ALL", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "UMask": "0x204", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.CH1_FROM_TGR", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR", + "PerPkg": "1", + "UMask": "0x240", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.CH1_ISOCH", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.CH1_ISOCH", + "PerPkg": "1", + "UMask": "0x202", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.CH1_NORMAL", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.CH1_NORMAL", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "UMask": "0x201", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE", + "PerPkg": "1", + "UMask": "0x210", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM", + "PerPkg": "1", + "UMask": "0x208", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.CH1_TO_PMM", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.CH1_TO_PMM", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "UMask": "0x220", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.FROM_TGR", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.FROM_TGR", + "PerPkg": "1", + "UMask": "0x340", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.ISOCH", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.ISOCH", + "PerPkg": "1", + "UMask": "0x302", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.NORMAL", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.NORMAL", + "PerPkg": "1", + "UMask": "0x301", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.TO_DDR_AS_CACHE", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_CACHE", + "PerPkg": "1", + "UMask": "0x310", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.TO_DDR_AS_MEM", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_MEM", + "PerPkg": "1", + "UMask": "0x308", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.TO_NM1LM", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.TO_NM1LM", + "PerPkg": "1", + "UMask": "0x308", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.TO_NMCACHE", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.TO_NMCACHE", + "PerPkg": "1", + "UMask": "0x310", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_READS.TO_PMM", + "EventCode": "0x24", + "EventName": "UNC_M2M_IMC_READS.TO_PMM", + "PerPkg": "1", + "UMask": "0x320", + "Unit": "M2M" + }, + { + "BriefDescription": "All Writes - All Channels", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.ALL", + "PerPkg": "1", + "UMask": "0x1810", + "Unit": "M2M" + }, + { + "BriefDescription": "Non-Inclusive - Ch0", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.CH0.NI", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_WRITES.CH0_ALL", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.CH0_ALL", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "UMask": "0x810", + "Unit": "M2M" + }, + { + "BriefDescription": "From TGR - Ch0", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_WRITES.CH0_FULL", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "UMask": "0x801", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH", + "PerPkg": "1", + "UMask": "0x804", + "Unit": "M2M" + }, + { + "BriefDescription": "Non-Inclusive - Ch0", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.CH0_NI", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Non-Inclusive Miss - Ch0", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_WRITES.CH0_PARTIAL", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "UMask": "0x802", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH", + "PerPkg": "1", + "UMask": "0x808", + "Unit": "M2M" + }, + { + "BriefDescription": "DDR, acting as Cache - Ch0", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_CACHE", + "PerPkg": "1", + "UMask": "0x840", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM", + "PerPkg": "1", + "UMask": "0x820", + "Unit": "M2M" + }, + { + "BriefDescription": "PMM - Ch0", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_PMM", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "PMM - Ch0 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC", + "UMask": "0x880", + "Unit": "M2M" + }, + { + "BriefDescription": "Non-Inclusive - Ch1", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.CH1.NI", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "All Writes - Ch1", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.CH1_ALL", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "UMask": "0x1010", + "Unit": "M2M" + }, + { + "BriefDescription": "From TGR - Ch1", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Full Line Non-ISOCH - Ch1", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "UMask": "0x1001", + "Unit": "M2M" + }, + { + "BriefDescription": "ISOCH Full Line - Ch1", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH", + "PerPkg": "1", + "UMask": "0x1004", + "Unit": "M2M" + }, + { + "BriefDescription": "Non-Inclusive - Ch1", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.CH1_NI", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Non-Inclusive Miss - Ch1", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Partial Non-ISOCH - Ch1", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "UMask": "0x1002", + "Unit": "M2M" + }, + { + "BriefDescription": "ISOCH Partial - Ch1", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH", + "PerPkg": "1", + "UMask": "0x1008", + "Unit": "M2M" + }, + { + "BriefDescription": "DDR, acting as Cache - Ch1", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_CACHE", + "PerPkg": "1", + "UMask": "0x1040", + "Unit": "M2M" + }, + { + "BriefDescription": "DDR - Ch1", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_MEM", + "PerPkg": "1", + "UMask": "0x1020", + "Unit": "M2M" + }, + { + "BriefDescription": "PMM - Ch1", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_PMM", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "PMM - Ch1 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC", + "UMask": "0x1080", + "Unit": "M2M" + }, + { + "BriefDescription": "From TGR - All Channels", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.FROM_TGR", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Full Non-ISOCH - All Channels", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.FULL", + "PerPkg": "1", + "UMask": "0x1801", + "Unit": "M2M" + }, + { + "BriefDescription": "ISOCH Full Line - All Channels", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH", + "PerPkg": "1", + "UMask": "0x1804", + "Unit": "M2M" + }, + { + "BriefDescription": "Non-Inclusive - All Channels", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.NI", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Non-Inclusive Miss - All Channels", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.NI_MISS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Partial Non-ISOCH - All Channels", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", + "PerPkg": "1", + "UMask": "0x1802", + "Unit": "M2M" + }, + { + "BriefDescription": "ISOCH Partial - All Channels", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH", + "PerPkg": "1", + "UMask": "0x1808", + "Unit": "M2M" + }, + { + "BriefDescription": "DDR, acting as Cache - All Channels", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_CACHE", + "PerPkg": "1", + "UMask": "0x1840", + "Unit": "M2M" + }, + { + "BriefDescription": "DDR - All Channels", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_MEM", + "PerPkg": "1", + "UMask": "0x1820", + "Unit": "M2M" + }, + { + "BriefDescription": "PMM - All Channels", + "EventCode": "0x25", + "EventName": "UNC_M2M_IMC_WRITES.TO_PMM", + "PerPkg": "1", + "UMask": "0x1880", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS", + "EventCode": "0x5c", + "EventName": "UNC_M2M_PREFCAM_CIS_DROPS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped", + "EventCode": "0x58", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_UPI", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped", + "EventCode": "0x58", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped", + "EventCode": "0x58", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_UPI", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped", + "EventCode": "0x58", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped : UPI - All Channels", + "EventCode": "0x58", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.UPI_ALLCH", + "PerPkg": "1", + "UMask": "0xa", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped", + "EventCode": "0x58", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "M2M" + }, + { + "BriefDescription": ": UPI - All Channels", + "EventCode": "0x5d", + "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.UPI_ALLCH", + "PerPkg": "1", + "UMask": "0xa", + "Unit": "M2M" + }, + { + "BriefDescription": ": XPT - All Channels", + "EventCode": "0x5d", + "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPT_ALLCH", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Not Merged with CAMed Prefetches", + "EventCode": "0x5E", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.RD_MERGED", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Not Merged with CAMed Prefetches", + "EventCode": "0x5E", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.WR_MERGED", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Not Merged with CAMed Prefetches", + "EventCode": "0x5E", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.WR_SQUASHED", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0", + "EventCode": "0x56", + "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_UPI", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0", + "EventCode": "0x56", + "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 1", + "EventCode": "0x56", + "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_UPI", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1", + "EventCode": "0x56", + "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels", + "EventCode": "0x56", + "EventName": "UNC_M2M_PREFCAM_INSERTS.UPI_ALLCH", + "PerPkg": "1", + "UMask": "0xa", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels", + "EventCode": "0x56", + "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH", + "PerPkg": "1", + "PublicDescription": "Prefetch CAM Inserts : XPT -All Channels", + "UMask": "0x5", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Occupancy : All Channels", + "EventCode": "0x54", + "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Occupancy : Channel 0", + "EventCode": "0x54", + "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Occupancy : Channel 1", + "EventCode": "0x54", + "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "All Channels", + "EventCode": "0x5F", + "EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": ": Channel 0", + "EventCode": "0x5f", + "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": ": Channel 1", + "EventCode": "0x5f", + "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "EventCode": "0x62", + "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", + "EventCode": "0x62", + "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT", + "EventCode": "0x62", + "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", + "EventCode": "0x62", + "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches", + "EventCode": "0x60", + "EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) : AD Ingress (from CMS) Allocations", + "EventCode": "0x02", + "EventName": "UNC_M2M_RxC_AD_INSERTS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Occupancy", + "EventCode": "0x03", + "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Clean NearMem Read Hit", + "EventCode": "0x1F", + "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN", + "PerPkg": "1", + "PublicDescription": "Counts clean full line read hits (reads and RFOs).", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Dirty NearMem Read Hit", + "EventCode": "0x1F", + "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY", + "PerPkg": "1", + "PublicDescription": "Counts dirty full line read hits (reads and RFOs).", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tag Hit : Clean NearMem Underfill Hit", + "EventCode": "0x1F", + "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN", + "PerPkg": "1", + "PublicDescription": "Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean underfill hits due to a partial write", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Tag Hit : Dirty NearMem Underfill Hit", + "EventCode": "0x1F", + "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY", + "PerPkg": "1", + "PublicDescription": "Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty underfill read hits due to a partial write", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_TAG_MISS", + "EventCode": "0x4b", + "EventName": "UNC_M2M_TAG_MISS", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "Number AD Ingress Credits", + "EventCode": "0x2e", + "EventName": "UNC_M2M_TGR_AD_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number BL Ingress Credits", + "EventCode": "0x2f", + "EventName": "UNC_M2M_TGR_BL_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Inserts : Channel 0", + "EventCode": "0x32", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x104", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Inserts : Channel 1", + "EventCode": "0x32", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x204", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Occupancy : Channel 0", + "EventCode": "0x33", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Occupancy : Channel 1", + "EventCode": "0x33", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "WPQ Flush : Channel 0", + "EventCode": "0x42", + "EventName": "UNC_M2M_WPQ_FLUSH.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "WPQ Flush : Channel 1", + "EventCode": "0x42", + "EventName": "UNC_M2M_WPQ_FLUSH.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0", + "EventCode": "0x37", + "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1", + "EventCode": "0x37", + "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 0", + "EventCode": "0x38", + "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 1", + "EventCode": "0x38", + "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts : Channel 0", + "EventCode": "0x40", + "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts : Channel 1", + "EventCode": "0x40", + "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty : Channel 0", + "EventCode": "0x35", + "EventName": "UNC_M2M_WR_TRACKER_NE.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty : Channel 1", + "EventCode": "0x35", + "EventName": "UNC_M2M_WR_TRACKER_NE.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty : Mirror", + "EventCode": "0x35", + "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty", + "EventCode": "0x35", + "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty", + "EventCode": "0x35", + "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0", + "EventCode": "0x4d", + "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1", + "EventCode": "0x4d", + "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 0", + "EventCode": "0x4c", + "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 1", + "EventCode": "0x4c", + "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Posted Inserts : Channel 0", + "EventCode": "0x48", + "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Posted Inserts : Channel 1", + "EventCode": "0x48", + "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Posted Occupancy : Channel 0", + "EventCode": "0x47", + "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Posted Occupancy : Channel 1", + "EventCode": "0x47", + "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CBox AD Credits Empty : Requests", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ", + "PerPkg": "1", + "PublicDescription": "CBox AD Credits Empty : Requests : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty : Snoops", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP", + "PerPkg": "1", + "PublicDescription": "CBox AD Credits Empty : Snoops : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty : VNA Messages", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "CBox AD Credits Empty : VNA Messages : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty : Writebacks", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB", + "PerPkg": "1", + "PublicDescription": "CBox AD Credits Empty : Writebacks : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M3UPI Clockticks", + "EventCode": "0x01", + "EventName": "UNC_M3UPI_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Number of M2UPI clock cycles while the event is enabled", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M3UPI CMS Clockticks", + "EventCode": "0xc0", + "EventName": "UNC_M3UPI_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "D2C Sent", + "EventCode": "0x2b", + "EventName": "UNC_M3UPI_D2C_SENT", + "PerPkg": "1", + "PublicDescription": "D2C Sent : Count cases BL sends direct to core", + "Unit": "M3UPI" + }, + { + "BriefDescription": "D2U Sent", + "EventCode": "0x2a", + "EventName": "UNC_M3UPI_D2U_SENT", + "PerPkg": "1", + "PublicDescription": "D2U Sent : Cases where SMI3 sends D2U command", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Down", + "EventCode": "0xba", + "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Up", + "EventCode": "0xba", + "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO1_NCB", + "PerPkg": "1", + "PublicDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only) : No vn0 and vna credits available to send to M2", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty : IIO2", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB", + "PerPkg": "1", + "PublicDescription": "M2 BL Credits Empty : IIO2 : No vn0 and vna credits available to send to M2", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty : IIO3", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB", + "PerPkg": "1", + "PublicDescription": "M2 BL Credits Empty : IIO3 : No vn0 and vna credits available to send to M2", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty : IIO4", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB", + "PerPkg": "1", + "PublicDescription": "M2 BL Credits Empty : IIO4 : No vn0 and vna credits available to send to M2", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty : IIO5", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB", + "PerPkg": "1", + "PublicDescription": "M2 BL Credits Empty : IIO5 : No vn0 and vna credits available to send to M2", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS", + "PerPkg": "1", + "PublicDescription": "M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together : No vn0 and vna credits available to send to M2", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty : Selected M2p BL NCS credits", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL", + "PerPkg": "1", + "PublicDescription": "M2 BL Credits Empty : Selected M2p BL NCS credits : No vn0 and vna credits available to send to M2", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty : IIO5", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.UBOX_NCB", + "PerPkg": "1", + "PublicDescription": "M2 BL Credits Empty : IIO5 : No vn0 and vna credits available to send to M2", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received : AD - Slot 0", + "EventCode": "0x3e", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0", + "PerPkg": "1", + "PublicDescription": "Multi Slot Flit Received : AD - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received : AD - Slot 1", + "EventCode": "0x3e", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1", + "PerPkg": "1", + "PublicDescription": "Multi Slot Flit Received : AD - Slot 1 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received : AD - Slot 2", + "EventCode": "0x3e", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2", + "PerPkg": "1", + "PublicDescription": "Multi Slot Flit Received : AD - Slot 2 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received : AK - Slot 0", + "EventCode": "0x3e", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0", + "PerPkg": "1", + "PublicDescription": "Multi Slot Flit Received : AK - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received : AK - Slot 2", + "EventCode": "0x3e", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2", + "PerPkg": "1", + "PublicDescription": "Multi Slot Flit Received : AK - Slot 2 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received : BL - Slot 0", + "EventCode": "0x3e", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0", + "PerPkg": "1", + "PublicDescription": "Multi Slot Flit Received : BL - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0 : REQ on AD", + "EventCode": "0x4b", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN0 : REQ on AD : VN0 message requested but lost arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0 : RSP on AD", + "EventCode": "0x4b", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN0 : RSP on AD : VN0 message requested but lost arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0 : SNP on AD", + "EventCode": "0x4b", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN0 : SNP on AD : VN0 message requested but lost arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0 : NCB on BL", + "EventCode": "0x4b", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN0 : NCB on BL : VN0 message requested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0 : NCS on BL", + "EventCode": "0x4b", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN0 : NCS on BL : VN0 message requested but lost arbitration : Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0 : RSP on BL", + "EventCode": "0x4b", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN0 : RSP on BL : VN0 message requested but lost arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0 : WB on BL", + "EventCode": "0x4b", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN0 : WB on BL : VN0 message requested but lost arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1 : REQ on AD", + "EventCode": "0x4c", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN1 : REQ on AD : VN1 message requested but lost arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1 : RSP on AD", + "EventCode": "0x4c", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN1 : RSP on AD : VN1 message requested but lost arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1 : SNP on AD", + "EventCode": "0x4c", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN1 : SNP on AD : VN1 message requested but lost arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1 : NCB on BL", + "EventCode": "0x4c", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN1 : NCB on BL : VN1 message requested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1 : NCS on BL", + "EventCode": "0x4c", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN1 : NCS on BL : VN1 message requested but lost arbitration : Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1 : RSP on BL", + "EventCode": "0x4c", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN1 : RSP on BL : VN1 message requested but lost arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1 : WB on BL", + "EventCode": "0x4c", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN1 : WB on BL : VN1 message requested but lost arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0", + "EventCode": "0x4d", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN0", + "PerPkg": "1", + "PublicDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0 : AD and BL messages won arbitration concurrently / in parallel", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1", + "EventCode": "0x4d", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN1", + "PerPkg": "1", + "PublicDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1 : AD and BL messages won arbitration concurrently / in parallel", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous : Max Parallel Win", + "EventCode": "0x4d", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.ALL_PARALLEL_WIN", + "PerPkg": "1", + "PublicDescription": "Arb Miscellaneous : Max Parallel Win : VN0 and VN1 arbitration sub-pipelines both produced AD and BL winners (maximum possible parallel winners)", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN0", + "EventCode": "0x4d", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0", + "PerPkg": "1", + "PublicDescription": "Arb Miscellaneous : No Progress on Pending AD VN0 : Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN1", + "EventCode": "0x4d", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1", + "PerPkg": "1", + "PublicDescription": "Arb Miscellaneous : No Progress on Pending AD VN1 : Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN0", + "EventCode": "0x4d", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0", + "PerPkg": "1", + "PublicDescription": "Arb Miscellaneous : No Progress on Pending BL VN0 : Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN1", + "EventCode": "0x4d", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1", + "PerPkg": "1", + "PublicDescription": "Arb Miscellaneous : No Progress on Pending BL VN1 : Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win", + "EventCode": "0x4d", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.VN01_PARALLEL_WIN", + "PerPkg": "1", + "PublicDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win : VN0 and VN1 arbitration sub-pipelines had parallel winners (at least one AD or BL on each side)", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0 : REQ on AD", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN0 : REQ on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0 : RSP on AD", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN0 : RSP on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0 : SNP on AD", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN0 : SNP on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0 : NCB on BL", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN0 : NCB on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0 : NCS on BL", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN0 : NCS on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0 : RSP on BL", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN0 : RSP on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0 : WB on BL", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN0 : WB on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1 : REQ on AD", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN1 : REQ on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1 : RSP on AD", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN1 : RSP on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1 : SNP on AD", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN1 : SNP on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1 : NCB on BL", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN1 : NCB on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1 : NCS on BL", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN1 : NCS on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1 : RSP on BL", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN1 : RSP on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1 : WB on BL", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN1 : WB on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0 : REQ on AD", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN0 : REQ on AD : VN0 message was not able to request arbitration while some other message won arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0 : RSP on AD", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN0 : RSP on AD : VN0 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0 : SNP on AD", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN0 : SNP on AD : VN0 message was not able to request arbitration while some other message won arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0 : NCB on BL", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN0 : NCB on BL : VN0 message was not able to request arbitration while some other message won arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0 : NCS on BL", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN0 : NCS on BL : VN0 message was not able to request arbitration while some other message won arbitration : Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0 : RSP on BL", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN0 : RSP on BL : VN0 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0 : WB on BL", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN0 : WB on BL : VN0 message was not able to request arbitration while some other message won arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1 : REQ on AD", + "EventCode": "0x4a", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN1 : REQ on AD : VN1 message was not able to request arbitration while some other message won arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1 : RSP on AD", + "EventCode": "0x4a", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN1 : RSP on AD : VN1 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1 : SNP on AD", + "EventCode": "0x4a", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN1 : SNP on AD : VN1 message was not able to request arbitration while some other message won arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1 : NCB on BL", + "EventCode": "0x4a", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN1 : NCB on BL : VN1 message was not able to request arbitration while some other message won arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1 : NCS on BL", + "EventCode": "0x4a", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN1 : NCS on BL : VN1 message was not able to request arbitration while some other message won arbitration : Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1 : RSP on BL", + "EventCode": "0x4a", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN1 : RSP on BL : VN1 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1 : WB on BL", + "EventCode": "0x4a", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN1 : WB on BL : VN1 message was not able to request arbitration while some other message won arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL Arb", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB", + "PerPkg": "1", + "PublicDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL Arb : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to slot 0 of independent flit while bl message is in arbitration", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE", + "PerPkg": "1", + "PublicDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to slot 0 of independent flit while pipeline is idle", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 1", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT", + "PerPkg": "1", + "PublicDescription": "Ingress Queue Bypasses : AD + BL to Slot 1 : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to flit slot 1 while merging with bl message in same flit", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 2", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT", + "PerPkg": "1", + "PublicDescription": "Ingress Queue Bypasses : AD + BL to Slot 2 : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to flit slot 2 while merging with bl message in same flit", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events : Any In BGF FIFO", + "EventCode": "0x5f", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO", + "PerPkg": "1", + "PublicDescription": "Miscellaneous Credit Events : Any In BGF FIFO : Indication that at least one packet (flit) is in the bgf (fifo only)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events : Any in BGF Path", + "EventCode": "0x5f", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH", + "PerPkg": "1", + "PublicDescription": "Miscellaneous Credit Events : Any in BGF Path : Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events", + "EventCode": "0x5f", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT1_FOR_D2K", + "PerPkg": "1", + "PublicDescription": "Miscellaneous Credit Events : d2k credit count is less than 1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events", + "EventCode": "0x5f", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT2_FOR_D2K", + "PerPkg": "1", + "PublicDescription": "Miscellaneous Credit Events : d2k credit count is less than 2", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events : No D2K For Arb", + "EventCode": "0x5f", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN0_NO_D2K_FOR_ARB", + "PerPkg": "1", + "PublicDescription": "Miscellaneous Credit Events : No D2K For Arb : VN0 BL RSP message was blocked from arbitration request due to lack of D2K CMP credit", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events", + "EventCode": "0x5f", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN1_NO_D2K_FOR_ARB", + "PerPkg": "1", + "PublicDescription": "Miscellaneous Credit Events : VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy : Credits Consumed", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.CONSUMED", + "PerPkg": "1", + "PublicDescription": "Credit Occupancy : Credits Consumed : number of remote vna credits consumed per cycle", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy : D2K Credits", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD", + "PerPkg": "1", + "PublicDescription": "Credit Occupancy : D2K Credits : D2K completion fifo credit occupancy (credits in use), accumulated across all cycles", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy : Packets in BGF FIFO", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO", + "PerPkg": "1", + "PublicDescription": "Credit Occupancy : Packets in BGF FIFO : Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy : Packets in BGF Path", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH", + "PerPkg": "1", + "PublicDescription": "Credit Occupancy : Packets in BGF Path : Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO", + "PerPkg": "1", + "PublicDescription": "Credit Occupancy : count of bl messages in pump-1-pending state, in completion fifo only", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL", + "PerPkg": "1", + "PublicDescription": "Credit Occupancy : count of bl messages in pump-1-pending state, in marker table and in fifo", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy : Transmit Credits", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD", + "PerPkg": "1", + "PublicDescription": "Credit Occupancy : Transmit Credits : Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy : VNA In Use", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE", + "PerPkg": "1", + "PublicDescription": "Credit Occupancy : VNA In Use : Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent : All", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.ALL", + "PerPkg": "1", + "PublicDescription": "Data Flit Not Sent : All : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but could not be sent for any reason, e.g. low credits, low tsv, stall injection", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent : No BGF Credits", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_BGF", + "PerPkg": "1", + "PublicDescription": "Data Flit Not Sent : No BGF Credits : Data flit is ready for transmission but could not be sent", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent : No TxQ Credits", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_TXQ", + "PerPkg": "1", + "PublicDescription": "Data Flit Not Sent : No TxQ Credits : Data flit is ready for transmission but could not be sent", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent : TSV High", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.TSV_HI", + "PerPkg": "1", + "PublicDescription": "Data Flit Not Sent : TSV High : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but was not sent while tsv high", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent : Cycle valid for Flit", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.VALID_FOR_FLIT", + "PerPkg": "1", + "PublicDescription": "Data Flit Not Sent : Cycle valid for Flit : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but was not sent while cycle is valid for flit transmission", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 0", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT", + "PerPkg": "1", + "PublicDescription": "Generating BL Data Flit Sequence : Wait on Pump 0 : generating bl data flit sequence; waiting for data pump 0", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT", + "PerPkg": "1", + "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is at capacity (pending table plus completion fifo at limit)", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY", + "PerPkg": "1", + "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is tracking at least one message", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL", + "PerPkg": "1", + "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending completion fifo is full", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0", + "PerPkg": "1", + "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO", + "PerPkg": "1", + "PublicDescription": "Generating BL Data Flit Sequence : a bl message finished but is in limbo and moved to pump-1-pending logic", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 1", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT", + "PerPkg": "1", + "PublicDescription": "Generating BL Data Flit Sequence : Wait on Pump 1 : generating bl data flit sequence; waiting for data pump 1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF", + "PerPkg": "1", + "PublicDescription": ": slot 2 request naturally serviced during hold-off period", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE", + "PerPkg": "1", + "PublicDescription": ": slot 2 request forcibly serviced during service window", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED", + "PerPkg": "1", + "PublicDescription": ": slot 2 request received from link layer while idle (with no slot 2 request active immediately prior)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN", + "PerPkg": "1", + "PublicDescription": ": slot 2 request withdrawn during hold-off period or service window", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit : All", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit : Needs Data Flit", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA", + "PerPkg": "1", + "PublicDescription": "Slotting BL Message Into Header Flit : Needs Data Flit : BL message requires data flit sequence", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 0", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT", + "PerPkg": "1", + "PublicDescription": "Slotting BL Message Into Header Flit : Wait on Pump 0 : Waiting for header pump 0", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ", + "PerPkg": "1", + "PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 : Header pump 1 is not required for flit", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE", + "PerPkg": "1", + "PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble : Header pump 1 is not required for flit but flit transmission delayed", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL", + "PerPkg": "1", + "PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail : Header pump 1 is not required for flit and not available", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 1", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT", + "PerPkg": "1", + "PublicDescription": "Slotting BL Message Into Header Flit : Wait on Pump 1 : Waiting for header pump 1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1 : Accumulate", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 1 : Accumulate : Events related to Header Flit Generation - Set 1 : Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1 : Accumulate Ready", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 1 : Accumulate Ready : Events related to Header Flit Generation - Set 1 : header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1 : Accumulate Wasted", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 1 : Accumulate Wasted : Events related to Header Flit Generation - Set 1 : Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked : Events related to Header Flit Generation - Set 1 : Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_AFTER", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: message was slotted only after run-ahead was over; run-ahead mode definitely wasted", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Message", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_DURING", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 1 : Run-Ahead - Message : Events related to Header Flit Generation - Set 1 : run-ahead mode: one message slotted during run-ahead", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_AFTER", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: second message slotted immediately after run-ahead; potential run-ahead success", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_SENT", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: two (or three) message flit sent immediately after run-ahead; complete run-ahead success", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 2 : Parallel Ok", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 2 : Parallel Ok : Events related to Header Flit Generation - Set 2 : new header flit construction may proceed in parallel with data flit sequence", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 2 : Parallel Flit Finished", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_FLIT", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 2 : Parallel Flit Finished : Events related to Header Flit Generation - Set 2 : header flit finished assembly in parallel with data flit sequence", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 2 : Parallel Message", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_MSG", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 2 : Parallel Message : Events related to Header Flit Generation - Set 2 : message is slotted into header flit in parallel with data flit sequence", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 2 : Rate-matching Stall : Events related to Header Flit Generation - Set 2 : Rate-matching stall injected", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall - No Message", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 2 : Rate-matching Stall - No Message : Events related to Header Flit Generation - Set 2 : Rate matching stall injected, but no additional message slotted during stall cycle", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit : One Message", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG", + "PerPkg": "1", + "PublicDescription": "Sent Header Flit : One Message : One message in flit; VNA or non-VNA flit", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit : One Message in non-VNA", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG_VNX", + "PerPkg": "1", + "PublicDescription": "Sent Header Flit : One Message in non-VNA : One message in flit; non-VNA flit", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit : Two Messages", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.2_MSGS", + "PerPkg": "1", + "PublicDescription": "Sent Header Flit : Two Messages : Two messages in flit; VNA flit", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit : Three Messages", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.3_MSGS", + "PerPkg": "1", + "PublicDescription": "Sent Header Flit : Three Messages : Three messages in flit; VNA flit", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit : One Slot Taken", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit : Two Slots Taken", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_2", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit : All Slots Taken", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_3", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent : All", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.ALL", + "PerPkg": "1", + "PublicDescription": "Header Not Sent : All : header flit is ready for transmission but could not be sent : header flit is ready for transmission but could not be sent for any reason, e.g. no credits, low tsv, stall injection", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent : No BGF Credits", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_CRD", + "PerPkg": "1", + "PublicDescription": "Header Not Sent : No BGF Credits : header flit is ready for transmission but could not be sent : No BGF credits available", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent : No BGF Credits + No Extra Message Slotted", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_NO_MSG", + "PerPkg": "1", + "PublicDescription": "Header Not Sent : No BGF Credits + No Extra Message Slotted : header flit is ready for transmission but could not be sent : No BGF credits available; no additional message slotted into flit", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent : No TxQ Credits", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_CRD", + "PerPkg": "1", + "PublicDescription": "Header Not Sent : No TxQ Credits : header flit is ready for transmission but could not be sent : No TxQ credits available", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent : No TxQ Credits + No Extra Message Slotted", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_NO_MSG", + "PerPkg": "1", + "PublicDescription": "Header Not Sent : No TxQ Credits + No Extra Message Slotted : header flit is ready for transmission but could not be sent : No TxQ credits available; no additional message slotted into flit", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent : TSV High", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.TSV_HI", + "PerPkg": "1", + "PublicDescription": "Header Not Sent : TSV High : header flit is ready for transmission but could not be sent : header flit is ready for transmission but was not sent while tsv high", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent : Cycle valid for Flit", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.VALID_FOR_FLIT", + "PerPkg": "1", + "PublicDescription": "Header Not Sent : Cycle valid for Flit : header flit is ready for transmission but could not be sent : header flit is ready for transmission but was not sent while cycle is valid for flit transmission", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held : Can't Slot AD", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD", + "PerPkg": "1", + "PublicDescription": "Message Held : Can't Slot AD : some AD message could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1})", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held : Can't Slot BL", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL", + "PerPkg": "1", + "PublicDescription": "Message Held : Can't Slot BL : some BL message could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1})", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held : Parallel Attempt", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT", + "PerPkg": "1", + "PublicDescription": "Message Held : Parallel Attempt : ad and bl messages attempted to slot into the same flit in parallel", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held : Parallel Success", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS", + "PerPkg": "1", + "PublicDescription": "Message Held : Parallel Success : ad and bl messages were actually slotted into the same flit in paralle", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held : VN0", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_HELD.VN0", + "PerPkg": "1", + "PublicDescription": "Message Held : VN0 : vn0 message(s) that couldn't be slotted into last vn0 flit are held in slotting stage while processing vn1 flit", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held : VN1", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_HELD.VN1", + "PerPkg": "1", + "PublicDescription": "Message Held : VN1 : vn1 message(s) that couldn't be slotted into last vn1 flit are held in slotting stage while processing vn0 flit", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit : REQ on AD", + "EventCode": "0x4e", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "VN0 message can't slot into flit : REQ on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit : RSP on AD", + "EventCode": "0x4e", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "VN0 message can't slot into flit : RSP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit : SNP on AD", + "EventCode": "0x4e", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "VN0 message can't slot into flit : SNP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit : NCB on BL", + "EventCode": "0x4e", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "VN0 message can't slot into flit : NCB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit : NCS on BL", + "EventCode": "0x4e", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "VN0 message can't slot into flit : NCS on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit : RSP on BL", + "EventCode": "0x4e", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "VN0 message can't slot into flit : RSP on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit : WB on BL", + "EventCode": "0x4e", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "VN0 message can't slot into flit : WB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit : REQ on AD", + "EventCode": "0x4f", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "VN1 message can't slot into flit : REQ on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit : RSP on AD", + "EventCode": "0x4f", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "VN1 message can't slot into flit : RSP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit : SNP on AD", + "EventCode": "0x4f", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "VN1 message can't slot into flit : SNP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit : NCB on BL", + "EventCode": "0x4f", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "VN1 message can't slot into flit : NCB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit : NCS on BL", + "EventCode": "0x4f", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "VN1 message can't slot into flit : NCS on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit : RSP on BL", + "EventCode": "0x4f", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "VN1 message can't slot into flit : RSP on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit : WB on BL", + "EventCode": "0x4f", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "VN1 message can't slot into flit : WB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits : Any In Use", + "EventCode": "0x5a", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE", + "PerPkg": "1", + "PublicDescription": "Remote VNA Credits : Any In Use : At least one remote vna credit is in use", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits : Corrected", + "EventCode": "0x5a", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED", + "PerPkg": "1", + "PublicDescription": "Remote VNA Credits : Corrected : Number of remote vna credits corrected (local return) per cycle", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits : Level < 1", + "EventCode": "0x5a", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1", + "PerPkg": "1", + "PublicDescription": "Remote VNA Credits : Level < 1 : Remote vna credit level is less than 1 (i.e. no vna credits available)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits : Level < 10", + "EventCode": "0x5a", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT10", + "PerPkg": "1", + "PublicDescription": "Remote VNA Credits : Level < 10 : remote vna credit level is less than 10; parallel vn0/vn1 arb not possible", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits : Level < 4", + "EventCode": "0x5a", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4", + "PerPkg": "1", + "PublicDescription": "Remote VNA Credits : Level < 4 : Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits : Level < 5", + "EventCode": "0x5a", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5", + "PerPkg": "1", + "PublicDescription": "Remote VNA Credits : Level < 5 : Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5", + "PerPkg": "1", + "PublicDescription": ": remote vna credit count was less than 5 and allocation to ad or bl messages was required", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10", + "PerPkg": "1", + "PublicDescription": ": remote vna credit count was less than 10 and allocation to vn0 or vn1 was required", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD", + "PerPkg": "1", + "PublicDescription": ": on vn0, remote vna credits were allocated only to ad messages, not to bl", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL", + "PerPkg": "1", + "PublicDescription": ": on vn0, remote vna credits were allocated only to bl messages, not to ad", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY", + "PerPkg": "1", + "PublicDescription": ": remote vna credits were allocated only to vn0, not to vn1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD", + "PerPkg": "1", + "PublicDescription": ": on vn1, remote vna credits were allocated only to ad messages, not to bl", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL", + "PerPkg": "1", + "PublicDescription": ": on vn1, remote vna credits were allocated only to bl messages, not to ad", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY", + "PerPkg": "1", + "PublicDescription": ": remote vna credits were allocated only to vn1, not to vn0", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD : VN0 REQ Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "Failed ARB for AD : VN0 REQ Messages : AD arb but no win; arb request asserted but not won", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD : VN0 RSP Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "Failed ARB for AD : VN0 RSP Messages : AD arb but no win; arb request asserted but not won", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD : VN0 SNP Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "Failed ARB for AD : VN0 SNP Messages : AD arb but no win; arb request asserted but not won", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD : VN0 WB Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB", + "PerPkg": "1", + "PublicDescription": "Failed ARB for AD : VN0 WB Messages : AD arb but no win; arb request asserted but not won", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD : VN1 REQ Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "Failed ARB for AD : VN1 REQ Messages : AD arb but no win; arb request asserted but not won", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD : VN1 RSP Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "Failed ARB for AD : VN1 RSP Messages : AD arb but no win; arb request asserted but not won", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD : VN1 SNP Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "Failed ARB for AD : VN1 SNP Messages : AD arb but no win; arb request asserted but not won", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD : VN1 WB Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB", + "PerPkg": "1", + "PublicDescription": "Failed ARB for AD : VN1 WB Messages : AD arb but no win; arb request asserted but not won", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "EventCode": "0x2c", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0", + "PerPkg": "1", + "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "EventCode": "0x2c", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1", + "PerPkg": "1", + "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "EventCode": "0x2c", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2", + "PerPkg": "1", + "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "EventCode": "0x2c", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP", + "PerPkg": "1", + "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty : VN0 REQ Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Not Empty : VN0 REQ Messages : Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty : VN0 RSP Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Not Empty : VN0 RSP Messages : Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty : VN0 SNP Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Not Empty : VN0 SNP Messages : Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty : VN0 WB Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Not Empty : VN0 WB Messages : Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty : VN1 REQ Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Not Empty : VN1 REQ Messages : Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty : VN1 RSP Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Not Empty : VN1 RSP Messages : Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty : VN1 SNP Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Not Empty : VN1 SNP Messages : Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty : VN1 WB Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Not Empty : VN1 WB Messages : Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts : VN0 REQ Messages", + "EventCode": "0x2d", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Inserts : VN0 REQ Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts : VN0 RSP Messages", + "EventCode": "0x2d", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Inserts : VN0 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts : VN0 SNP Messages", + "EventCode": "0x2d", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Inserts : VN0 SNP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts : VN0 WB Messages", + "EventCode": "0x2d", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Inserts : VN0 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts : VN1 REQ Messages", + "EventCode": "0x2d", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Inserts : VN1 REQ Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts : VN1 RSP Messages", + "EventCode": "0x2d", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Inserts : VN1 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts : VN1 SNP Messages", + "EventCode": "0x2d", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Inserts : VN1 SNP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy : VN0 REQ Messages", + "EventCode": "0x1c", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy : VN0 RSP Messages", + "EventCode": "0x1c", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy : VN0 SNP Messages", + "EventCode": "0x1c", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy : VN0 WB Messages", + "EventCode": "0x1c", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy : VN1 REQ Messages", + "EventCode": "0x1c", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy : VN1 RSP Messages", + "EventCode": "0x1c", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy : VN1 SNP Messages", + "EventCode": "0x1c", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AK Flow Q Inserts", + "EventCode": "0x2f", + "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AK Flow Q Occupancy", + "EventCode": "0x1e", + "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL : VN0 NCB Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB", + "PerPkg": "1", + "PublicDescription": "Failed ARB for BL : VN0 NCB Messages : BL arb but no win; arb request asserted but not won", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL : VN0 NCS Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS", + "PerPkg": "1", + "PublicDescription": "Failed ARB for BL : VN0 NCS Messages : BL arb but no win; arb request asserted but not won", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL : VN0 RSP Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "Failed ARB for BL : VN0 RSP Messages : BL arb but no win; arb request asserted but not won", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL : VN0 WB Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB", + "PerPkg": "1", + "PublicDescription": "Failed ARB for BL : VN0 WB Messages : BL arb but no win; arb request asserted but not won", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL : VN1 NCS Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB", + "PerPkg": "1", + "PublicDescription": "Failed ARB for BL : VN1 NCS Messages : BL arb but no win; arb request asserted but not won", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL : VN1 NCB Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS", + "PerPkg": "1", + "PublicDescription": "Failed ARB for BL : VN1 NCB Messages : BL arb but no win; arb request asserted but not won", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL : VN1 RSP Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "Failed ARB for BL : VN1 RSP Messages : BL arb but no win; arb request asserted but not won", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL : VN1 WB Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB", + "PerPkg": "1", + "PublicDescription": "Failed ARB for BL : VN1 WB Messages : BL arb but no win; arb request asserted but not won", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty : VN0 REQ Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Not Empty : VN0 REQ Messages : Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty : VN0 RSP Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Not Empty : VN0 RSP Messages : Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty : VN0 SNP Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Not Empty : VN0 SNP Messages : Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty : VN0 WB Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Not Empty : VN0 WB Messages : Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty : VN1 REQ Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Not Empty : VN1 REQ Messages : Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty : VN1 RSP Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Not Empty : VN1 RSP Messages : Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty : VN1 SNP Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Not Empty : VN1 SNP Messages : Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty : VN1 WB Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Not Empty : VN1 WB Messages : Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts : VN0 RSP Messages", + "EventCode": "0x2e", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Inserts : VN0 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts : VN0 WB Messages", + "EventCode": "0x2e", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Inserts : VN0 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts : VN0 NCS Messages", + "EventCode": "0x2e", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Inserts : VN0 NCS Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts : VN0 NCB Messages", + "EventCode": "0x2e", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Inserts : VN0 NCB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts : VN1 RSP Messages", + "EventCode": "0x2e", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Inserts : VN1 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts : VN1 WB Messages", + "EventCode": "0x2e", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Inserts : VN1 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts : VN1_NCB Messages", + "EventCode": "0x2e", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Inserts : VN1_NCB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts : VN1_NCS Messages", + "EventCode": "0x2e", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Inserts : VN1_NCS Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages", + "EventCode": "0x1d", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN0 NCS Messages", + "EventCode": "0x1d", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages", + "EventCode": "0x1d", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages", + "EventCode": "0x1d", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages", + "EventCode": "0x1d", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN1_NCB Messages", + "EventCode": "0x1d", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages", + "EventCode": "0x1d", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages", + "EventCode": "0x1d", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages", + "EventCode": "0x1f", + "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_LOCAL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages", + "EventCode": "0x1f", + "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_THROUGH", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages", + "EventCode": "0x1f", + "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_WRPULL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages", + "EventCode": "0x1f", + "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_LOCAL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages", + "EventCode": "0x1f", + "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_THROUGH", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages", + "EventCode": "0x1f", + "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_WRPULL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty : VN0 REQ Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "UPI0 AD Credits Empty : VN0 REQ Messages : No credits available to send to UPIs on the AD Ring", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty : VN0 RSP Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "UPI0 AD Credits Empty : VN0 RSP Messages : No credits available to send to UPIs on the AD Ring", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty : VN0 SNP Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "UPI0 AD Credits Empty : VN0 SNP Messages : No credits available to send to UPIs on the AD Ring", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty : VN1 REQ Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "UPI0 AD Credits Empty : VN1 REQ Messages : No credits available to send to UPIs on the AD Ring", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty : VN1 RSP Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "UPI0 AD Credits Empty : VN1 RSP Messages : No credits available to send to UPIs on the AD Ring", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty : VN1 SNP Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "UPI0 AD Credits Empty : VN1 SNP Messages : No credits available to send to UPIs on the AD Ring", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty : VNA", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "UPI0 AD Credits Empty : VNA : No credits available to send to UPIs on the AD Ring", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty : VN0 RSP Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB", + "PerPkg": "1", + "PublicDescription": "UPI0 BL Credits Empty : VN0 RSP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty : VN0 REQ Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "UPI0 BL Credits Empty : VN0 REQ Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty : VN0 SNP Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB", + "PerPkg": "1", + "PublicDescription": "UPI0 BL Credits Empty : VN0 SNP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty : VN1 RSP Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB", + "PerPkg": "1", + "PublicDescription": "UPI0 BL Credits Empty : VN1 RSP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty : VN1 REQ Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "UPI0 BL Credits Empty : VN1 REQ Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty : VN1 SNP Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB", + "PerPkg": "1", + "PublicDescription": "UPI0 BL Credits Empty : VN1 SNP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty : VNA", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "UPI0 BL Credits Empty : VNA : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "FlowQ Generated Prefetch", + "EventCode": "0x29", + "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN", + "PerPkg": "1", + "PublicDescription": "FlowQ Generated Prefetch : Count cases where FlowQ causes spawn of Prefetch to iMC/SMI3 target", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used : WB on BL", + "EventCode": "0x5b", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB", + "PerPkg": "1", + "PublicDescription": "VN0 Credit Used : WB on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used : NCB on BL", + "EventCode": "0x5b", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "VN0 Credit Used : NCB on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used : REQ on AD", + "EventCode": "0x5b", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ", + "PerPkg": "1", + "PublicDescription": "VN0 Credit Used : REQ on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used : RSP on AD", + "EventCode": "0x5b", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP", + "PerPkg": "1", + "PublicDescription": "VN0 Credit Used : RSP on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used : SNP on AD", + "EventCode": "0x5b", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP", + "PerPkg": "1", + "PublicDescription": "VN0 Credit Used : SNP on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used : RSP on BL", + "EventCode": "0x5b", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB", + "PerPkg": "1", + "PublicDescription": "VN0 Credit Used : RSP on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits : WB on BL", + "EventCode": "0x5d", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB", + "PerPkg": "1", + "PublicDescription": "VN0 No Credits : WB on BL : Number of Cycles there were no VN0 Credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits : NCB on BL", + "EventCode": "0x5d", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS", + "PerPkg": "1", + "PublicDescription": "VN0 No Credits : NCB on BL : Number of Cycles there were no VN0 Credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits : REQ on AD", + "EventCode": "0x5d", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ", + "PerPkg": "1", + "PublicDescription": "VN0 No Credits : REQ on AD : Number of Cycles there were no VN0 Credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits : RSP on AD", + "EventCode": "0x5d", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP", + "PerPkg": "1", + "PublicDescription": "VN0 No Credits : RSP on AD : Number of Cycles there were no VN0 Credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits : SNP on AD", + "EventCode": "0x5d", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP", + "PerPkg": "1", + "PublicDescription": "VN0 No Credits : SNP on AD : Number of Cycles there were no VN0 Credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits : RSP on BL", + "EventCode": "0x5d", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB", + "PerPkg": "1", + "PublicDescription": "VN0 No Credits : RSP on BL : Number of Cycles there were no VN0 Credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used : WB on BL", + "EventCode": "0x5c", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB", + "PerPkg": "1", + "PublicDescription": "VN1 Credit Used : WB on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used : NCB on BL", + "EventCode": "0x5c", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "VN1 Credit Used : NCB on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used : REQ on AD", + "EventCode": "0x5c", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ", + "PerPkg": "1", + "PublicDescription": "VN1 Credit Used : REQ on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used : RSP on AD", + "EventCode": "0x5c", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP", + "PerPkg": "1", + "PublicDescription": "VN1 Credit Used : RSP on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used : SNP on AD", + "EventCode": "0x5c", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP", + "PerPkg": "1", + "PublicDescription": "VN1 Credit Used : SNP on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used : RSP on BL", + "EventCode": "0x5c", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB", + "PerPkg": "1", + "PublicDescription": "VN1 Credit Used : RSP on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits : WB on BL", + "EventCode": "0x5e", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB", + "PerPkg": "1", + "PublicDescription": "VN1 No Credits : WB on BL : Number of Cycles there were no VN1 Credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits : NCB on BL", + "EventCode": "0x5e", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS", + "PerPkg": "1", + "PublicDescription": "VN1 No Credits : NCB on BL : Number of Cycles there were no VN1 Credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits : REQ on AD", + "EventCode": "0x5e", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ", + "PerPkg": "1", + "PublicDescription": "VN1 No Credits : REQ on AD : Number of Cycles there were no VN1 Credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits : RSP on AD", + "EventCode": "0x5e", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP", + "PerPkg": "1", + "PublicDescription": "VN1 No Credits : RSP on AD : Number of Cycles there were no VN1 Credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits : SNP on AD", + "EventCode": "0x5e", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP", + "PerPkg": "1", + "PublicDescription": "VN1 No Credits : SNP on AD : Number of Cycles there were no VN1 Credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits : RSP on BL", + "EventCode": "0x5e", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB", + "PerPkg": "1", + "PublicDescription": "VN1 No Credits : RSP on BL : Number of Cycles there were no VN1 Credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0", + "EventCode": "0x7e", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0", + "PerPkg": "1", + "UMask": "0x82", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1", + "EventCode": "0x7e", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1", + "PerPkg": "1", + "UMask": "0xa0", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0", + "EventCode": "0x7e", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0", + "PerPkg": "1", + "UMask": "0x81", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1", + "EventCode": "0x7e", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1", + "PerPkg": "1", + "UMask": "0x90", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0", + "EventCode": "0x7e", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0", + "PerPkg": "1", + "UMask": "0x84", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1", + "EventCode": "0x7e", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1", + "PerPkg": "1", + "UMask": "0xc0", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0", + "EventCode": "0x7e", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1", + "EventCode": "0x7e", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0", + "EventCode": "0x7e", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1", + "EventCode": "0x7e", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0", + "EventCode": "0x7e", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1", + "EventCode": "0x7e", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0", + "EventCode": "0x7d", + "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1", + "EventCode": "0x7d", + "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0", + "EventCode": "0x7d", + "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1", + "EventCode": "0x7d", + "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0", + "EventCode": "0x7d", + "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1", + "EventCode": "0x7d", + "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0", + "EventCode": "0x7d", + "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1", + "EventCode": "0x7d", + "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARB", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_XPT_PFTCH.ARB", + "PerPkg": "1", + "PublicDescription": ": xpt prefetch message is making arbitration request", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARRIVED", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_XPT_PFTCH.ARRIVED", + "PerPkg": "1", + "PublicDescription": ": xpt prefetch message arrived in ingress pipeline", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_XPT_PFTCH.BYPASS", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_XPT_PFTCH.BYPASS", + "PerPkg": "1", + "PublicDescription": ": xpt prefetch message took bypass path", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_XPT_PFTCH.FLITTED", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_XPT_PFTCH.FLITTED", + "PerPkg": "1", + "PublicDescription": ": xpt prefetch message was slotted into flit (non bypass)", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_ARB", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_ARB", + "PerPkg": "1", + "PublicDescription": ": xpt prefetch message lost arbitration", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_OLD", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_OLD", + "PerPkg": "1", + "PublicDescription": ": xpt prefetch message was dropped because it became too old", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL", + "PerPkg": "1", + "PublicDescription": ": xpt prefetch message was dropped because it was overwritten by new message while prefetch queue was full", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (AD Bouncable)", + "EventCode": "0x47", + "EventName": "UNC_MDF_CRS_TxR_INSERTS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "AD Bouncable : Number of allocations into the CRS Egress", + "UMask": "0x1", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (AD credited)", + "EventCode": "0x47", + "EventName": "UNC_MDF_CRS_TxR_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "AD credited : Number of allocations into the CRS Egress", + "UMask": "0x2", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (AK)", + "EventCode": "0x47", + "EventName": "UNC_MDF_CRS_TxR_INSERTS.AK", + "PerPkg": "1", + "PublicDescription": "AK : Number of allocations into the CRS Egress", + "UMask": "0x10", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (AKC)", + "EventCode": "0x47", + "EventName": "UNC_MDF_CRS_TxR_INSERTS.AKC", + "PerPkg": "1", + "PublicDescription": "AKC : Number of allocations into the CRS Egress", + "UMask": "0x40", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (BL Bouncable)", + "EventCode": "0x47", + "EventName": "UNC_MDF_CRS_TxR_INSERTS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "BL Bouncable : Number of allocations into the CRS Egress", + "UMask": "0x4", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (BL credited)", + "EventCode": "0x47", + "EventName": "UNC_MDF_CRS_TxR_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "BL credited : Number of allocations into the CRS Egress", + "UMask": "0x8", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of allocations into the CRS Egress used to queue up requests destined to the mesh (IV)", + "EventCode": "0x47", + "EventName": "UNC_MDF_CRS_TxR_INSERTS.IV", + "PerPkg": "1", + "PublicDescription": "IV : Number of allocations into the CRS Egress", + "UMask": "0x20", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of cycles incoming messages from the vertical ring that are bounced at the SBO\r\nIngress (V-EMIB) (AD)", + "EventCode": "0x4B", + "EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.AD", + "PerPkg": "1", + "PublicDescription": "AD : Number of cycles incoming messages from the vertical ring that are bounced at the SBO", + "UMask": "0x1", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of cycles incoming messages from the vertical ring that are bounced at the SBO\r\nIngress (V-EMIB) (AK)", + "EventCode": "0x4B", + "EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.AK", + "PerPkg": "1", + "PublicDescription": "AK : Number of cycles incoming messages from the vertical ring that are bounced at the SBO", + "UMask": "0x4", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of cycles incoming messages from the vertical ring that are bounced at the SBO\r\nIngress (V-EMIB) (AKC)", + "EventCode": "0x4B", + "EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.AKC", + "PerPkg": "1", + "PublicDescription": "AKC : Number of cycles incoming messages from the vertical ring that are bounced at the SBO", + "UMask": "0x10", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of cycles incoming messages from the vertical ring that are bounced at the SBO\r\nIngress (V-EMIB) (BL)", + "EventCode": "0x4B", + "EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.BL", + "PerPkg": "1", + "PublicDescription": "BL : Number of cycles incoming messages from the vertical ring that are bounced at the SBO", + "UMask": "0x2", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of cycles incoming messages from the vertical ring that are bounced at the SBO\r\nIngress (V-EMIB) (IV)", + "EventCode": "0x4B", + "EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.IV", + "PerPkg": "1", + "PublicDescription": "IV : Number of cycles incoming messages from the vertical ring that are bounced at the SBO", + "UMask": "0x8", + "Unit": "MDF" + }, + { + "BriefDescription": "Counts the number of cycles when the distress signals are asserted based on SBO Ingress threshold", + "EventCode": "0x15", + "EventName": "UNC_MDF_FAST_ASSERTED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "AD bnc : Counts the number of cycles when the distress signals are asserted based on SBO Ingress threshold", + "UMask": "0x1", + "Unit": "MDF" + }, + { + "BriefDescription": "Counts the number of cycles when the distress signals are asserted based on SBO Ingress threshold", + "EventCode": "0x15", + "EventName": "UNC_MDF_FAST_ASSERTED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "BL bnc : Counts the number of cycles when the distress signals are asserted based on SBO Ingress threshold", + "UMask": "0x2", + "Unit": "MDF" + }, + { + "BriefDescription": "UPI Clockticks", + "EventCode": "0x01", + "EventName": "UNC_UPI_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Number of UPI LL clock cycles while the event is enabled", + "Unit": "UPI" + }, + { + "BriefDescription": "Direct packet attempts : D2C", + "EventCode": "0x12", + "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C", + "PerPkg": "1", + "PublicDescription": "Direct packet attempts : D2C : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "Direct packet attempts : D2K", + "EventCode": "0x12", + "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K", + "PerPkg": "1", + "PublicDescription": "Direct packet attempts : D2K : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles in L1", + "EventCode": "0x21", + "EventName": "UNC_UPI_L1_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Cycles in L1 : Number of UPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a UPI link. Use edge detect to count the number of instances when the UPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "EventCode": "0x16", + "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1", + "EventCode": "0x20", + "EventName": "UNC_UPI_PHY_INIT_CYCLES", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "L1 Req Nack", + "EventCode": "0x23", + "EventName": "UNC_UPI_POWER_L1_NACK", + "PerPkg": "1", + "PublicDescription": "L1 Req Nack : Counts the number of times a link sends/receives a LinkReqNAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx originally requested the power change). A Tx LinkReqNAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).", + "Unit": "UPI" + }, + { + "BriefDescription": "L1 Req (same as L1 Ack).", + "EventCode": "0x22", + "EventName": "UNC_UPI_POWER_L1_REQ", + "PerPkg": "1", + "PublicDescription": "L1 Req (same as L1 Ack). : Counts the number of times a link sends/receives a LinkReqAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqAck refers to receiving an Ack (meaning this agent's Tx originally requested the power change). A Tx LinkReqAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles in L0p", + "EventCode": "0x25", + "EventName": "UNC_UPI_RxL0P_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles in L0", + "EventCode": "0x24", + "EventName": "UNC_UPI_RxL0_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Cycles in L0 : Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_ANY_FLITS.DATA", + "EventCode": "0x4B", + "EventName": "UNC_UPI_RxL_ANY_FLITS.DATA", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_ANY_FLITS.LLCRD", + "EventCode": "0x4B", + "EventName": "UNC_UPI_RxL_ANY_FLITS.LLCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_ANY_FLITS.LLCTRL", + "EventCode": "0x4B", + "EventName": "UNC_UPI_RxL_ANY_FLITS.LLCTRL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_ANY_FLITS.NULL", + "EventCode": "0x4B", + "EventName": "UNC_UPI_RxL_ANY_FLITS.NULL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_ANY_FLITS.PROTHDR", + "EventCode": "0x4B", + "EventName": "UNC_UPI_RxL_ANY_FLITS.PROTHDR", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_ANY_FLITS.SLOT0", + "EventCode": "0x4B", + "EventName": "UNC_UPI_RxL_ANY_FLITS.SLOT0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_ANY_FLITS.SLOT1", + "EventCode": "0x4B", + "EventName": "UNC_UPI_RxL_ANY_FLITS.SLOT1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_ANY_FLITS.SLOT2", + "EventCode": "0x4B", + "EventName": "UNC_UPI_RxL_ANY_FLITS.SLOT2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", + "PerPkg": "1", + "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0xe", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC", + "PerPkg": "1", + "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x10e", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", + "PerPkg": "1", + "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0xf", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC", + "PerPkg": "1", + "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x10f", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 0", + "EventCode": "0x31", + "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", + "PerPkg": "1", + "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 0 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 1", + "EventCode": "0x31", + "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", + "PerPkg": "1", + "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 1 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 2", + "EventCode": "0x31", + "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", + "PerPkg": "1", + "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 2 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "CRC Errors Detected", + "EventCode": "0x0b", + "EventName": "UNC_UPI_RxL_CRC_ERRORS", + "PerPkg": "1", + "PublicDescription": "CRC Errors Detected : Number of CRC errors detected in the UPI Agent. Each UPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the UPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).", + "Unit": "UPI" + }, + { + "BriefDescription": "LLR Requests Sent", + "EventCode": "0x08", + "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT", + "PerPkg": "1", + "PublicDescription": "LLR Requests Sent : Number of LLR Requests were transmitted. This should generally be <= the number of CRC errors detected. If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs..", + "Unit": "UPI" + }, + { + "BriefDescription": "VN0 Credit Consumed", + "EventCode": "0x39", + "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0", + "PerPkg": "1", + "PublicDescription": "VN0 Credit Consumed : Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", + "Unit": "UPI" + }, + { + "BriefDescription": "VN1 Credit Consumed", + "EventCode": "0x3a", + "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1", + "PerPkg": "1", + "PublicDescription": "VN1 Credit Consumed : Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", + "Unit": "UPI" + }, + { + "BriefDescription": "VNA Credit Consumed", + "EventCode": "0x38", + "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : All Data", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", + "PerPkg": "1", + "PublicDescription": "Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c).", + "UMask": "0xf", + "Unit": "UPI" + }, + { + "BriefDescription": "Null FLITs received from any slot", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", + "PerPkg": "1", + "UMask": "0x27", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : Data", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.DATA", + "PerPkg": "1", + "PublicDescription": "Valid Flits Received : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : Idle", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.IDLE", + "PerPkg": "1", + "PublicDescription": "Valid Flits Received : Idle : Shows legal flit time (hides impact of L0p and L0c).", + "UMask": "0x47", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : LLCRD Not Empty", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.LLCRD", + "PerPkg": "1", + "PublicDescription": "Valid Flits Received : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : LLCTRL", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.LLCTRL", + "PerPkg": "1", + "PublicDescription": "Valid Flits Received : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.", + "UMask": "0x40", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : All Non Data", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", + "PerPkg": "1", + "PublicDescription": "Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c).", + "UMask": "0x97", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Empty", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.NULL", + "PerPkg": "1", + "PublicDescription": "Valid Flits Received : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : Protocol Header", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.PROTHDR", + "PerPkg": "1", + "PublicDescription": "Valid Flits Received : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)", + "UMask": "0x80", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : Slot 0", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.SLOT0", + "PerPkg": "1", + "PublicDescription": "Valid Flits Received : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : Slot 1", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.SLOT1", + "PerPkg": "1", + "PublicDescription": "Valid Flits Received : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : Slot 2", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.SLOT2", + "PerPkg": "1", + "PublicDescription": "Valid Flits Received : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Flit Buffer Allocations : Slot 0", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT0", + "PerPkg": "1", + "PublicDescription": "RxQ Flit Buffer Allocations : Slot 0 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Flit Buffer Allocations : Slot 1", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT1", + "PerPkg": "1", + "PublicDescription": "RxQ Flit Buffer Allocations : Slot 1 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Flit Buffer Allocations : Slot 2", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT2", + "PerPkg": "1", + "PublicDescription": "RxQ Flit Buffer Allocations : Slot 2 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets : Slot 0", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0", + "PerPkg": "1", + "PublicDescription": "RxQ Occupancy - All Packets : Slot 0 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets : Slot 1", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1", + "PerPkg": "1", + "PublicDescription": "RxQ Occupancy - All Packets : Slot 1 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets : Slot 2", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2", + "PerPkg": "1", + "PublicDescription": "RxQ Occupancy - All Packets : Slot 2 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "EventCode": "0x2a", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "EventCode": "0x2a", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "EventCode": "0x2a", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "EventCode": "0x2a", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "EventCode": "0x2a", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "EventCode": "0x2a", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "EventCode": "0x2a", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "EventCode": "0x2a", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles in L0p", + "EventCode": "0x27", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "EventCode": "0x28", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "EventCode": "0x29", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles in L0", + "EventCode": "0x26", + "EventName": "UNC_UPI_TxL0_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Cycles in L0 : Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL_ANY_FLITS.DATA", + "EventCode": "0x4A", + "EventName": "UNC_UPI_TxL_ANY_FLITS.DATA", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL_ANY_FLITS.LLCRD", + "EventCode": "0x4A", + "EventName": "UNC_UPI_TxL_ANY_FLITS.LLCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL_ANY_FLITS.LLCTRL", + "EventCode": "0x4A", + "EventName": "UNC_UPI_TxL_ANY_FLITS.LLCTRL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL_ANY_FLITS.NULL", + "EventCode": "0x4A", + "EventName": "UNC_UPI_TxL_ANY_FLITS.NULL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL_ANY_FLITS.PROTHDR", + "EventCode": "0x4A", + "EventName": "UNC_UPI_TxL_ANY_FLITS.PROTHDR", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL_ANY_FLITS.SLOT0", + "EventCode": "0x4A", + "EventName": "UNC_UPI_TxL_ANY_FLITS.SLOT0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL_ANY_FLITS.SLOT1", + "EventCode": "0x4A", + "EventName": "UNC_UPI_TxL_ANY_FLITS.SLOT1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL_ANY_FLITS.SLOT2", + "EventCode": "0x4A", + "EventName": "UNC_UPI_TxL_ANY_FLITS.SLOT2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", + "PerPkg": "1", + "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0xe", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC", + "PerPkg": "1", + "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x10e", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", + "PerPkg": "1", + "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0xf", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC", + "PerPkg": "1", + "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x10f", + "Unit": "UPI" + }, + { + "BriefDescription": "Tx Flit Buffer Bypassed", + "EventCode": "0x41", + "EventName": "UNC_UPI_TxL_BYPASSED", + "PerPkg": "1", + "PublicDescription": "Tx Flit Buffer Bypassed : Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the UPI Link. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : All Data", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : All Data : Counts number of data flits across this UPI link.", + "UMask": "0xf", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : All LLCRD Not Empty", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.ALL_LLCRD", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : All Data : Shows legal flit time (hides impact of L0p and L0c).", + "UMask": "0x17", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : All LLCTRL", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.ALL_LLCTRL", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : All LLCTRL : Shows legal flit time (hides impact of L0p and L0c).", + "UMask": "0x47", + "Unit": "UPI" + }, + { + "BriefDescription": "All Null Flits", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", + "PerPkg": "1", + "UMask": "0x27", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : All Protocol Header", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.ALL_PROTHDR", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : All ProtDDR : Shows legal flit time (hides impact of L0p and L0c).", + "UMask": "0x87", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : Data", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.DATA", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : Idle", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.IDLE", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : Idle : Shows legal flit time (hides impact of L0p and L0c).", + "UMask": "0x47", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : LLCRD Not Empty", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.LLCRD", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : LLCTRL", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.LLCTRL", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.", + "UMask": "0x40", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : All Non Data", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c).", + "UMask": "0x97", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.NULL", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : Protocol Header", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.PROTHDR", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)", + "UMask": "0x80", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : Slot 0", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.SLOT0", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : Slot 1", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.SLOT1", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : Slot 2", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.SLOT2", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "Tx Flit Buffer Allocations", + "EventCode": "0x40", + "EventName": "UNC_UPI_TxL_INSERTS", + "PerPkg": "1", + "PublicDescription": "Tx Flit Buffer Allocations : Number of allocations into the UPI Tx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", + "Unit": "UPI" + }, + { + "BriefDescription": "Tx Flit Buffer Occupancy", + "EventCode": "0x42", + "EventName": "UNC_UPI_TxL_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Tx Flit Buffer Occupancy : Accumulates the number of flits in the TxQ. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "EventCode": "0x45", + "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "VNA Credits Pending Return - Occupancy", + "EventCode": "0x44", + "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "VNA Credits Pending Return - Occupancy : Number of VNA credits in the Rx side that are waitng to be returned back across the link.", + "Unit": "UPI" + }, + { + "BriefDescription": "Message Received : Doorbell", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received : Interrupt", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.INT_PRIO", + "PerPkg": "1", + "PublicDescription": "Message Received : Interrupt : Interrupts", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received : IPI", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", + "PerPkg": "1", + "PublicDescription": "Message Received : IPI : Inter Processor Interrupts", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received : MSI", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", + "PerPkg": "1", + "PublicDescription": "Message Received : MSI : Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received : VLW", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", + "PerPkg": "1", + "PublicDescription": "Message Received : VLW : Virtual Logical Wire (legacy) message were received from Uncore.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", + "EventCode": "0x4d", + "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", + "EventCode": "0x4d", + "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB", + "EventCode": "0x4d", + "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS", + "EventCode": "0x4d", + "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", + "EventCode": "0x4d", + "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", + "EventCode": "0x4d", + "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB", + "EventCode": "0x4d", + "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS", + "EventCode": "0x4d", + "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", + "EventCode": "0x4e", + "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", + "EventCode": "0x4e", + "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", + "EventCode": "0x4e", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", + "EventCode": "0x4e", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", + "EventCode": "0x4e", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", + "EventCode": "0x4e", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", + "EventCode": "0x4e", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", + "EventCode": "0x4e", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", + "EventCode": "0x4f", + "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", + "EventCode": "0x4f", + "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK", + "EventCode": "0x45", + "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", + "PerPkg": "1", + "PublicDescription": "Cycles PHOLD Assert to Ack : Assert to ACK : PHOLD cycles.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "EventCode": "0x4c", + "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_RACU_DRNG.RDRAND", + "EventCode": "0x4c", + "EventName": "UNC_U_RACU_DRNG.RDRAND", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_RACU_DRNG.RDSEED", + "EventCode": "0x4c", + "EventName": "UNC_U_RACU_DRNG.RDSEED", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "RACU Request", + "EventCode": "0x46", + "EventName": "UNC_U_RACU_REQUESTS", + "PerPkg": "1", + "PublicDescription": "RACU Request : Number outstanding register requests within message channel tracker", + "Unit": "UBOX" + } +] diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-io.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-io.json new file mode 100644 index 000000000000..8b5f54fed103 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-io.json @@ -0,0 +1,3651 @@ +[ + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN", + "PerPkg": "1", + "UMask": "0x22", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN", + "PerPkg": "1", + "UMask": "0x23", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN", + "PerPkg": "1", + "UMask": "0x25", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN", + "PerPkg": "1", + "UMask": "0x26", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN", + "PerPkg": "1", + "UMask": "0x27", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART0_FREERUN", + "PerPkg": "1", + "UMask": "0x30", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART1_FREERUN", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART2_FREERUN", + "PerPkg": "1", + "UMask": "0x32", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART3_FREERUN", + "PerPkg": "1", + "UMask": "0x33", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART4_FREERUN", + "PerPkg": "1", + "UMask": "0x34", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART5_FREERUN", + "PerPkg": "1", + "UMask": "0x35", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART6_FREERUN", + "PerPkg": "1", + "UMask": "0x36", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART7_FREERUN", + "PerPkg": "1", + "UMask": "0x37", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "IIO Clockticks", + "EventCode": "0x01", + "EventName": "UNC_IIO_CLOCKTICKS", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": "Number of IIO clock cycles while the event is enabled", + "Unit": "IIO" + }, + { + "BriefDescription": "Free running counter that increments for IIO clocktick", + "EventCode": "0xff", + "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xff", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0001", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x7001004", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0002", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1", + "UMask": "0x7002004", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0004", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2", + "UMask": "0x7004004", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0008", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3", + "UMask": "0x7008004", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0010", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4", + "UMask": "0x7010004", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0020", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5", + "UMask": "0x7020004", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0040", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6", + "UMask": "0x7040004", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0080", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7", + "UMask": "0x7080004", + "Unit": "IIO" + }, + { + "BriefDescription": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "FCMask": "0x07", + "PerPkg": "1", + "UMask": "0xff", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy : Part 0", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": "x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x7000001", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy : Part 1", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": "x4 card is plugged in to slot 1", + "UMask": "0x7000002", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy : Part 2", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": "x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "UMask": "0x7000004", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy : Part 3", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": "x4 card is plugged in to slot 3", + "UMask": "0x7000008", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy : Part 4", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": "x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x7000010", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy : Part 5", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": "x4 card is plugged in to slot 1", + "UMask": "0x7000020", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy : Part 6", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": "x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "UMask": "0x7000040", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy : Part 7", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": "x4 card is plugged in to slot 3", + "UMask": "0x7000080", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0-7", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.ALL_PARTS", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00ff", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0001", + "PublicDescription": "Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x7001004", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part1", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0002", + "PublicDescription": "Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x7002004", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part2", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0004", + "PublicDescription": "Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "UMask": "0x7004004", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part3", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0008", + "PublicDescription": "Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x7008004", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Cards MMIO space", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0010", + "PublicDescription": "Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x7010004", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Cards MMIO space", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0020", + "PublicDescription": "Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x7020004", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Cards MMIO space", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0040", + "PublicDescription": "Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "UMask": "0x7040004", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Cards MMIO space", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0080", + "PublicDescription": "Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x7080004", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made to IIO Part0-7 by the CPU", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.ALL_PARTS", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00ff", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0100", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0200", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made to IIO Part0 by the CPU", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0001", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made to IIO Part1 by the CPU", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0002", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made to IIO Part2 by the CPU", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0004", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made to IIO Part3 by the CPU", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0008", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0010", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0020", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0040", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0080", + "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0001", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x7001008", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0002", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x7002008", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0004", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "UMask": "0x7004008", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0008", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x7008008", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0010", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x7010008", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0020", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x7020008", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0040", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "UMask": "0x7040008", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0080", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x7080008", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0001", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x7001002", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0002", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x7002002", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0004", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "UMask": "0x7004002", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0008", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x7008002", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0010", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x7010002", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0020", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x7020002", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0040", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "UMask": "0x7040002", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0080", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x7080002", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.ALL_PARTS", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xff", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0001", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0002", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0004", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0008", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0010", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0020", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0040", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0080", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by IIO Part0-7 to Memory", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00ff", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by IIO Part0 to Memory", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0001", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by IIO Part1 to Memory", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0002", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by IIO Part2 to Memory", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0004", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by IIO Part3 to Memory", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0008", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0010", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0020", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0040", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0080", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made by IIO Part0-7 to Memory", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00ff", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made by IIO Part0 to Memory", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0001", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made by IIO Part1 to Memory", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0002", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made by IIO Part2 to Memory", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0004", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made by IIO Part3 to Memory", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0008", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0010", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0020", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0040", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0080", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0001", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0002", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0004", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0008", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0010", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0020", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0040", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0080", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests : Passing data to be written", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "Incoming arbitration requests : Passing data to be written : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests", + "UMask": "0x70ff020", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests : Issuing final read or write of line", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "Incoming arbitration requests : Issuing final read or write of line : How often different queues (e.g. channel / fc) ask to send request into pipeline", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests : Processing response from IOMMU", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "Incoming arbitration requests : Processing response from IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests : Issuing to IOMMU", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "Incoming arbitration requests : Issuing to IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests : Request Ownership", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "Incoming arbitration requests : Request Ownership : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests", + "UMask": "0x70ff004", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests : Writing line", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "Incoming arbitration requests : Writing line : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests", + "UMask": "0x70ff010", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests granted : Passing data to be written", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.DATA", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "Incoming arbitration requests granted : Passing data to be written : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests", + "UMask": "0x70ff020", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests granted : Issuing final read or write of line", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "Incoming arbitration requests granted : Issuing final read or write of line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline", + "UMask": "0x70ff008", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests granted : Processing response from IOMMU", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "Incoming arbitration requests granted : Processing response from IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline", + "UMask": "0x70ff002", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests granted : Issuing to IOMMU", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "Incoming arbitration requests granted : Issuing to IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline", + "UMask": "0x70ff001", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests granted : Request Ownership", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "Incoming arbitration requests granted : Request Ownership : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests", + "UMask": "0x70ff004", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests granted : Writing line", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "Incoming arbitration requests granted : Writing line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests", + "UMask": "0x70ff010", + "Unit": "IIO" + }, + { + "BriefDescription": ": Context cache hits", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": ": Context cache hits : Counts each time a first look up of the transaction hits the RCC.", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": ": Context cache lookups", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": ": Context cache lookups : Counts each time a transaction looks up root context cache.", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOTLB lookups first", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": ": IOTLB lookups first : Some transactions have to look up IOTLB multiple times. Counts the first time a request looks up IOTLB.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "IOTLB Fills (same as IOTLB miss)", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.MISSES", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": "IOTLB Fills (same as IOTLB miss) : When a transaction misses IOTLB, it does a page walk to look up memory and bring in the relevant page translation. Counts when this page translation is written to IOTLB.", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOMMU memory access", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES", + "PerPkg": "1", + "PublicDescription": ": IOMMU memory access : IOMMU sends out memory fetches when it misses the cache look up which is indicated by this signal. M2IOSF only uses low priority channel", + "UMask": "0xc0", + "Unit": "IIO" + }, + { + "BriefDescription": ": PWC Hit to a 2M page", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS", + "PerPkg": "1", + "PublicDescription": ": PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": ": PWT Hit to a 256T page", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_256T_HITS", + "PerPkg": "1", + "PublicDescription": ": PWT Hit to a 256T page : Counts each time a transaction's first look up hits the SLPWC at the 512G level", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": ": PWC Hit to a 4K page", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS", + "PerPkg": "1", + "PublicDescription": ": PWC Hit to a 4K page : Counts each time a transaction's first look up hits the SLPWC at the 4K level", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": ": PWC Hit to a 1G page", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS", + "PerPkg": "1", + "PublicDescription": ": PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": ": PageWalk cache fill", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS", + "PerPkg": "1", + "PublicDescription": ": PageWalk cache fill : When a transaction misses SLPWC, it does a page walk to look up memory and bring in the relevant page translation. When this page translation is written to SLPWC, ObsPwcFillValid_nnnH is asserted.", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": ": PageWalk cache lookup", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS", + "PerPkg": "1", + "PublicDescription": ": PageWalk cache lookup : Counts each time a transaction looks up second level page walk cache.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": ": PWC Hit to a 2M page", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.SLPWC_1G_HITS", + "PerPkg": "1", + "PublicDescription": ": PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": ": PWC Hit to a 2M page", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.SLPWC_256T_HITS", + "PerPkg": "1", + "PublicDescription": ": PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": ": PWC Hit to a 1G page", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.SLPWC_512G_HITS", + "PerPkg": "1", + "PublicDescription": ": PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": ": Global IOTLB invalidation cycles", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.PWT_OCCUPANCY_MSB", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": ": Global IOTLB invalidation cycles : Indicates that IOMMU is doing global invalidation.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus : Asserted if all bits specified by mask match", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if all bits specified by mask match", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if all bits specified by mask match", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus : PCIE bus", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": "AND Mask/match for debug bus : PCIE bus : Asserted if all bits specified by mask match", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if all bits specified by mask match", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if all bits specified by mask match", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus : Asserted if any bits specified by mask match", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if any bits specified by mask match", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if any bits specified by mask match", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus : PCIE bus", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": "OR Mask/match for debug bus : PCIE bus : Asserted if any bits specified by mask match", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if any bits specified by mask match", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if any bits specified by mask match", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number requests PCIe makes of the main die : All", + "EventCode": "0x85", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FFF", + "PublicDescription": "Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Abort", + "EventCode": "0x8e", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Confined P2P", + "EventCode": "0x8e", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Local P2P", + "EventCode": "0x8e", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Multi-cast", + "EventCode": "0x8e", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Memory", + "EventCode": "0x8e", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : MsgB", + "EventCode": "0x8e", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Remote P2P", + "EventCode": "0x8e", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Ubox", + "EventCode": "0x8e", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "ITC address map 1", + "EventCode": "0x8f", + "EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU", + "Unit": "IIO" + }, + { + "BriefDescription": "Outbound cacheline requests issued : 64B requests issued to device", + "EventCode": "0xd0", + "EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "Outbound cacheline requests issued : 64B requests issued to device : Each outbound cacheline granular request may need to make multiple passes through the pipeline. Each time a cacheline completes all its passes it advances line", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Outbound TLP (transaction layer packet) requests issued : To device", + "EventCode": "0xd1", + "EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "Outbound TLP (transaction layer packet) requests issued : To device : Each time an outbound completes all its passes it advances the pointer", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "PWT occupancy. Does not include 9th bit of occupancy (will undercount if PWT is greater than 255 per cycle).", + "EventCode": "0x42", + "EventName": "UNC_IIO_PWT_OCCUPANCY", + "PerPkg": "1", + "PortMask": "0x0000", + "PublicDescription": "PWT occupancy : Indicates how many page walks are outstanding at any point in time.", + "UMask": "0xff", + "Unit": "IIO" + }, + { + "BriefDescription": "Request Ownership : PCIe Request complete", + "EventCode": "0x91", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "Request Ownership : PCIe Request complete : Only for posted requests : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.", + "UMask": "0x70ff020", + "Unit": "IIO" + }, + { + "BriefDescription": "Request Ownership : Writing line", + "EventCode": "0x91", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "Request Ownership : Writing line : Only for posted requests : Only for posted requests", + "UMask": "0x70ff008", + "Unit": "IIO" + }, + { + "BriefDescription": "Request Ownership : Issuing final read or write of line", + "EventCode": "0x91", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "Request Ownership : Issuing final read or write of line : Only for posted requests", + "UMask": "0x70ff004", + "Unit": "IIO" + }, + { + "BriefDescription": "Request Ownership : Passing data to be written", + "EventCode": "0x91", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "Request Ownership : Passing data to be written : Only for posted requests : Only for posted requests", + "UMask": "0x70ff010", + "Unit": "IIO" + }, + { + "BriefDescription": "Processing response from IOMMU : Passing data to be written", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "Processing response from IOMMU : Passing data to be written : Only for posted requests", + "UMask": "0x70ff008", + "Unit": "IIO" + }, + { + "BriefDescription": "Processing response from IOMMU : Issuing final read or write of line", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "UMask": "0x70ff002", + "Unit": "IIO" + }, + { + "BriefDescription": "Processing response from IOMMU : Request Ownership", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "Processing response from IOMMU : Request Ownership : Only for posted requests", + "UMask": "0x70ff001", + "Unit": "IIO" + }, + { + "BriefDescription": "Processing response from IOMMU : Writing line", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "Processing response from IOMMU : Writing line : Only for posted requests", + "UMask": "0x70ff004", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request - pass complete : Passing data to be written", + "EventCode": "0x90", + "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "PCIe Request - pass complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests", + "UMask": "0x70ff020", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request - pass complete : Issuing final read or write of line", + "EventCode": "0x90", + "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "PCIe Request - pass complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request - pass complete : Request Ownership", + "EventCode": "0x90", + "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "PCIe Request - pass complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests", + "UMask": "0x70ff004", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request - pass complete : Writing line", + "EventCode": "0x90", + "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x00FF", + "PublicDescription": "PCIe Request - pass complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests", + "UMask": "0x70ff010", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0001", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0002", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0004", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0008", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0010", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0020", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0040", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0080", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0001", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0002", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0004", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0008", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0010", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0020", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0040", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0080", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0001", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x7001002", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0002", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x7002002", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0004", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x7004002", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0008", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x7008002", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0010", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x7010002", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0020", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x7020002", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0040", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x7040002", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0080", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x7080002", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0001", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0002", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0004", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0008", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0010", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0020", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0040", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0080", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part0 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0001", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part1 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0002", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0004", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0008", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0010", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0020", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0040", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0080", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0001", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0002", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0004", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0008", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0010", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0020", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0040", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0080", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0001", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0002", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0004", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0008", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0010", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0020", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0040", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0080", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "M2P Clockticks", + "EventCode": "0x01", + "EventName": "UNC_M2P_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Number of M2P clock cycles while the event is enabled", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Clockticks", + "EventCode": "0xc0", + "EventName": "UNC_M2P_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Down", + "EventCode": "0xba", + "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Up", + "EventCode": "0xba", + "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS", + "EventCode": "0x34", + "EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the DRS message class.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB", + "EventCode": "0x34", + "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCB message class.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS", + "EventCode": "0x34", + "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCS message class.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCB", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCS", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCB", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCS", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCB", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCS", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCB", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCS", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCB", + "EventCode": "0x47", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCS", + "EventCode": "0x47", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCB", + "EventCode": "0x47", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCS", + "EventCode": "0x47", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCB", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCS", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCB", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCS", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCB", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCS", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCB", + "EventCode": "0x1a", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCS", + "EventCode": "0x1a", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCB", + "EventCode": "0x1a", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCS", + "EventCode": "0x1a", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Shared Credits Returned : Agent0", + "EventCode": "0x17", + "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Shared Credits Returned : Agent1", + "EventCode": "0x17", + "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Shared Credits Returned : Agent2", + "EventCode": "0x17", + "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent0", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent1", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent2", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent3", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent4", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent5", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCB", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCS", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCB", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCS", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCB", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCS", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCB", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCS", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCB", + "EventCode": "0x41", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCS", + "EventCode": "0x41", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCB", + "EventCode": "0x41", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCS", + "EventCode": "0x41", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCB", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCS", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCB", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCS", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCB", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCS", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCB", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCS", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCB", + "EventCode": "0x4b", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCS", + "EventCode": "0x4b", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCB", + "EventCode": "0x4b", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCS", + "EventCode": "0x4b", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "P2P Credit Occupancy : All", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "P2P Credit Occupancy : Local NCB", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "P2P Credit Occupancy : Local NCS", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "P2P Credit Occupancy : Remote NCB", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "P2P Credit Occupancy : Remote NCS", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Dedicated Credits Received : All", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Dedicated Credits Received : Local NCB", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Dedicated Credits Received : Local NCS", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Dedicated Credits Received : Remote NCB", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Dedicated Credits Received : Remote NCS", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Shared Credits Received : All", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Shared Credits Received : Local NCB", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Shared Credits Received : Local NCS", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Shared Credits Received : Remote NCB", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Shared Credits Received : Remote NCS", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - DRS", + "EventCode": "0x48", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_DRS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCB", + "EventCode": "0x48", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCB", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCS", + "EventCode": "0x48", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - DRS", + "EventCode": "0x48", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_DRS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCB", + "EventCode": "0x48", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCS", + "EventCode": "0x48", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - DRS", + "EventCode": "0x49", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_DRS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCB", + "EventCode": "0x49", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCB", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCS", + "EventCode": "0x49", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 - NCB", + "EventCode": "0x1b", + "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 - NCS", + "EventCode": "0x1b", + "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 - NCB", + "EventCode": "0x1b", + "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 - NCS", + "EventCode": "0x1b", + "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 - NCB", + "EventCode": "0x1b", + "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 - NCS", + "EventCode": "0x1b", + "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Shared Credits Returned : Agent0", + "EventCode": "0x18", + "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Shared Credits Returned : Agent1", + "EventCode": "0x18", + "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Shared Credits Returned : Agent2", + "EventCode": "0x18", + "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent0", + "EventCode": "0x45", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent1", + "EventCode": "0x45", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent2", + "EventCode": "0x45", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - DRS", + "EventCode": "0x42", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_DRS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - NCB", + "EventCode": "0x42", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCB", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - NCS", + "EventCode": "0x42", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - DRS", + "EventCode": "0x42", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_DRS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - NCB", + "EventCode": "0x42", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - NCS", + "EventCode": "0x42", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - DRS", + "EventCode": "0x43", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_DRS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - NCB", + "EventCode": "0x43", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCB", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - NCS", + "EventCode": "0x43", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - DRS", + "EventCode": "0x4c", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_DRS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCB", + "EventCode": "0x4c", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCB", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCS", + "EventCode": "0x4c", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - DRS", + "EventCode": "0x4c", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_DRS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCB", + "EventCode": "0x4c", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCS", + "EventCode": "0x4c", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - DRS", + "EventCode": "0x4d", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_DRS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCB", + "EventCode": "0x4d", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCB", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCS", + "EventCode": "0x4d", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.ALL", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCB", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCS", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.ALL", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCB", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCS", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "UNC_M2P_TxC_CREDITS.PMM", + "EventCode": "0x2d", + "EventName": "UNC_M2P_TxC_CREDITS.PMM", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ", + "EventCode": "0x2d", + "EventName": "UNC_M2P_TxC_CREDITS.PRQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_0", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_1", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_0", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_1", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x8", + "Unit": "M2PCIe" + } +] diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-memory.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-memory.json index b77fd0f7ab50..225333561295 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-memory.json @@ -1,427 +1,3254 @@ [ + { + "BriefDescription": "Cycles - at UCLK", + "EventCode": "0x01", + "EventName": "UNC_M2HBM_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "CMS Clockticks", + "EventCode": "0xc0", + "EventName": "UNC_M2HBM_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled", + "EventCode": "0x17", + "EventName": "UNC_M2HBM_DIRECT2CORE_NOT_TAKEN_DIRSTATE", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Cycles when direct to core mode, which bypasses the CHA, was disabled : Non Cisgress", + "EventCode": "0x17", + "EventName": "UNC_M2HBM_DIRECT2CORE_NOT_TAKEN_DIRSTATE.NON_CISGRESS", + "PerPkg": "1", + "PublicDescription": "Counts the number of time non cisgress D2C was not honoured by egress due to directory state constraints", + "UMask": "0x2", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Counts the time when FM didn't do d2c for fill reads (cross tile case)", + "EventCode": "0x4a", + "EventName": "UNC_M2HBM_DIRECT2CORE_NOT_TAKEN_NOTFORKED", + "PerPkg": "1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Number of reads in which direct to core transaction were overridden", + "EventCode": "0x18", + "EventName": "UNC_M2HBM_DIRECT2CORE_TXN_OVERRIDE", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Number of reads in which direct to core transaction was overridden : Cisgress", + "EventCode": "0x18", + "EventName": "UNC_M2HBM_DIRECT2CORE_TXN_OVERRIDE.CISGRESS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden", + "EventCode": "0x1b", + "EventName": "UNC_M2HBM_DIRECT2UPI_NOT_TAKEN_CREDITS", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Cycles when direct to Intel UPI was disabled", + "EventCode": "0x1a", + "EventName": "UNC_M2HBM_DIRECT2UPI_NOT_TAKEN_DIRSTATE", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Cycles when Direct2UPI was Disabled : Cisgress D2U Ignored", + "EventCode": "0x1A", + "EventName": "UNC_M2HBM_DIRECT2UPI_NOT_TAKEN_DIRSTATE.CISGRESS", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts cisgress d2K that was not honored due to directory constraints", + "UMask": "0x4", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Cycles when Direct2UPI was Disabled : Egress Ignored D2U", + "EventCode": "0x1A", + "EventName": "UNC_M2HBM_DIRECT2UPI_NOT_TAKEN_DIRSTATE.EGRESS", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts the number of time D2K was not honoured by egress due to directory state constraints", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Cycles when Direct2UPI was Disabled : Non Cisgress D2U Ignored", + "EventCode": "0x1A", + "EventName": "UNC_M2HBM_DIRECT2UPI_NOT_TAKEN_DIRSTATE.NON_CISGRESS", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts non cisgress d2K that was not honored due to directory constraints", + "UMask": "0x2", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden", + "EventCode": "0x1c", + "EventName": "UNC_M2HBM_DIRECT2UPI_TXN_OVERRIDE", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Number of times a direct to UPI transaction was overridden.", + "EventCode": "0x1c", + "EventName": "UNC_M2HBM_DIRECT2UPI_TXN_OVERRIDE.CISGRESS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Directory Hit : On NonDirty Line in A State", + "EventCode": "0x1d", + "EventName": "UNC_M2HBM_DIRECTORY_HIT.CLEAN_A", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Directory Hit : On NonDirty Line in I State", + "EventCode": "0x1d", + "EventName": "UNC_M2HBM_DIRECTORY_HIT.CLEAN_I", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Directory Hit : On NonDirty Line in L State", + "EventCode": "0x1d", + "EventName": "UNC_M2HBM_DIRECTORY_HIT.CLEAN_P", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Directory Hit : On NonDirty Line in S State", + "EventCode": "0x1d", + "EventName": "UNC_M2HBM_DIRECTORY_HIT.CLEAN_S", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Directory Hit : On Dirty Line in A State", + "EventCode": "0x1d", + "EventName": "UNC_M2HBM_DIRECTORY_HIT.DIRTY_A", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Directory Hit : On Dirty Line in I State", + "EventCode": "0x1d", + "EventName": "UNC_M2HBM_DIRECTORY_HIT.DIRTY_I", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Directory Hit : On Dirty Line in L State", + "EventCode": "0x1d", + "EventName": "UNC_M2HBM_DIRECTORY_HIT.DIRTY_P", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Directory Hit : On Dirty Line in S State", + "EventCode": "0x1d", + "EventName": "UNC_M2HBM_DIRECTORY_HIT.DIRTY_S", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)", + "EventCode": "0x20", + "EventName": "UNC_M2HBM_DIRECTORY_LOOKUP.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of hit data returns to egress with any directory to non persistent memory", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)", + "EventCode": "0x20", + "EventName": "UNC_M2HBM_DIRECTORY_LOOKUP.STATE_A", + "PerPkg": "1", + "PublicDescription": "Counts the number of hit data returns to egress with directory A to non persistent memory", + "UMask": "0x8", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)", + "EventCode": "0x20", + "EventName": "UNC_M2HBM_DIRECTORY_LOOKUP.STATE_I", + "PerPkg": "1", + "PublicDescription": "Counts the number of hit data returns to egress with directory I to non persistent memory", + "UMask": "0x2", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)", + "EventCode": "0x20", + "EventName": "UNC_M2HBM_DIRECTORY_LOOKUP.STATE_S", + "PerPkg": "1", + "PublicDescription": "Counts the number of hit data returns to egress with directory S to non persistent memory", + "UMask": "0x4", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Directory Miss : On NonDirty Line in A State", + "EventCode": "0x1e", + "EventName": "UNC_M2HBM_DIRECTORY_MISS.CLEAN_A", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Directory Miss : On NonDirty Line in I State", + "EventCode": "0x1e", + "EventName": "UNC_M2HBM_DIRECTORY_MISS.CLEAN_I", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Directory Miss : On NonDirty Line in L State", + "EventCode": "0x1e", + "EventName": "UNC_M2HBM_DIRECTORY_MISS.CLEAN_P", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Directory Miss : On NonDirty Line in S State", + "EventCode": "0x1e", + "EventName": "UNC_M2HBM_DIRECTORY_MISS.CLEAN_S", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Directory Miss : On Dirty Line in A State", + "EventCode": "0x1e", + "EventName": "UNC_M2HBM_DIRECTORY_MISS.DIRTY_A", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Directory Miss : On Dirty Line in I State", + "EventCode": "0x1e", + "EventName": "UNC_M2HBM_DIRECTORY_MISS.DIRTY_I", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Directory Miss : On Dirty Line in L State", + "EventCode": "0x1e", + "EventName": "UNC_M2HBM_DIRECTORY_MISS.DIRTY_P", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Directory Miss : On Dirty Line in S State", + "EventCode": "0x1e", + "EventName": "UNC_M2HBM_DIRECTORY_MISS.DIRTY_S", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from A to I", + "EventCode": "0x21", + "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.A2I", + "PerPkg": "1", + "UMask": "0x320", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from A to S", + "EventCode": "0x21", + "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.A2S", + "PerPkg": "1", + "UMask": "0x340", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from/to Any state", + "EventCode": "0x21", + "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.ANY", + "PerPkg": "1", + "UMask": "0x301", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.A_TO_I_HIT_NON_PMM", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts 1lm or 2lm hit data returns that would result in directory update from A to I to non persistent memory", + "UMask": "0x120", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.A_TO_I_MISS_NON_PMM", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts 2lm miss data returns that would result in directory update from A to I to non persistent memory", + "UMask": "0x220", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.A_TO_S_HIT_NON_PMM", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts 1lm or 2lm hit data returns that would result in directory update from A to S to non persistent memory", + "UMask": "0x140", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.A_TO_S_MISS_NON_PMM", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts 2lm miss data returns that would result in directory update from A to S to non persistent memory", + "UMask": "0x240", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.HIT_NON_PMM", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts any 1lm or 2lm hit data return that would result in directory update to non persistent memory", + "UMask": "0x101", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from I to A", + "EventCode": "0x21", + "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.I2A", + "PerPkg": "1", + "UMask": "0x304", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from I to S", + "EventCode": "0x21", + "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.I2S", + "PerPkg": "1", + "UMask": "0x302", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.I_TO_A_HIT_NON_PMM", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts 1lm or 2lm hit data returns that would result in directory update from I to A to non persistent memory", + "UMask": "0x104", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.I_TO_A_MISS_NON_PMM", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts 2lm miss data returns that would result in directory update from I to A to non persistent memory", + "UMask": "0x204", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.I_TO_S_HIT_NON_PMM", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts 1lm or 2lm hit data returns that would result in directory update from I to S to non persistent memory", + "UMask": "0x102", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.I_TO_S_MISS_NON_PMM", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts 2lm miss data returns that would result in directory update from I to S to non persistent memory", + "UMask": "0x202", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.MISS_NON_PMM", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts any 2lm miss data return that would result in directory update to non persistent memory", + "UMask": "0x201", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from S to A", + "EventCode": "0x21", + "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.S2A", + "PerPkg": "1", + "UMask": "0x310", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from S to I", + "EventCode": "0x21", + "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.S2I", + "PerPkg": "1", + "UMask": "0x308", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.S_TO_A_HIT_NON_PMM", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts 1lm or 2lm hit data returns that would result in directory update from S to A to non persistent memory", + "UMask": "0x110", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.S_TO_A_MISS_NON_PMM", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts 2lm miss data returns that would result in directory update from S to A to non persistent memory", + "UMask": "0x210", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.S_TO_I_HIT_NON_PMM", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts 1lm or 2lm hit data returns that would result in directory update from S to I to non persistent memory", + "UMask": "0x108", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates", + "EventCode": "0x21", + "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.S_TO_I_MISS_NON_PMM", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts 2lm miss data returns that would result in directory update from S to I to non persistent memory", + "UMask": "0x208", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Count distress signalled on AkAd cmp message", + "EventCode": "0x67", + "EventName": "UNC_M2HBM_DISTRESS.AD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Count distress signalled on any packet type", + "EventCode": "0x67", + "EventName": "UNC_M2HBM_DISTRESS.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Count distress signalled on Bl Cmp message", + "EventCode": "0x67", + "EventName": "UNC_M2HBM_DISTRESS.BL_CMP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Count distress signalled on NM fill write message", + "EventCode": "0x67", + "EventName": "UNC_M2HBM_DISTRESS.CROSSTILE_NMWR", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Count distress signalled on D2Cha message", + "EventCode": "0x67", + "EventName": "UNC_M2HBM_DISTRESS.D2CHA", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Count distress signalled on D2c message", + "EventCode": "0x67", + "EventName": "UNC_M2HBM_DISTRESS.D2CORE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Count distress signalled on D2k message", + "EventCode": "0x67", + "EventName": "UNC_M2HBM_DISTRESS.D2UPI", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Down", + "EventCode": "0xba", + "EventName": "UNC_M2HBM_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x80000004", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Up", + "EventCode": "0xba", + "EventName": "UNC_M2HBM_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x80000001", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Count when Starve Glocab counter is at 7", + "EventCode": "0x44", + "EventName": "UNC_M2HBM_IGR_STARVE_WINNER.MASK7", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "UMask": "0x80", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Reads to iMC issued", + "EventCode": "0x24", + "EventName": "UNC_M2HBM_IMC_READS.ALL", + "PerPkg": "1", + "UMask": "0x304", + "Unit": "M2HBM" + }, + { + "BriefDescription": "UNC_M2HBM_IMC_READS.CH0.ALL", + "EventCode": "0x24", + "EventName": "UNC_M2HBM_IMC_READS.CH0.ALL", + "PerPkg": "1", + "UMask": "0x104", + "Unit": "M2HBM" + }, + { + "BriefDescription": "UNC_M2HBM_IMC_READS.CH0.NORMAL", + "EventCode": "0x24", + "EventName": "UNC_M2HBM_IMC_READS.CH0.NORMAL", + "PerPkg": "1", + "UMask": "0x101", + "Unit": "M2HBM" + }, + { + "BriefDescription": "UNC_M2HBM_IMC_READS.CH0_ALL", + "EventCode": "0x24", + "EventName": "UNC_M2HBM_IMC_READS.CH0_ALL", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "UMask": "0x104", + "Unit": "M2HBM" + }, + { + "BriefDescription": "UNC_M2HBM_IMC_READS.CH0_FROM_TGR", + "EventCode": "0x24", + "EventName": "UNC_M2HBM_IMC_READS.CH0_FROM_TGR", + "PerPkg": "1", + "UMask": "0x140", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Critical Priority - Ch0", + "EventCode": "0x24", + "EventName": "UNC_M2HBM_IMC_READS.CH0_ISOCH", + "PerPkg": "1", + "UMask": "0x102", + "Unit": "M2HBM" + }, + { + "BriefDescription": "UNC_M2HBM_IMC_READS.CH0_NORMAL", + "EventCode": "0x24", + "EventName": "UNC_M2HBM_IMC_READS.CH0_NORMAL", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "UMask": "0x101", + "Unit": "M2HBM" + }, + { + "BriefDescription": "UNC_M2HBM_IMC_READS.CH1.ALL", + "EventCode": "0x24", + "EventName": "UNC_M2HBM_IMC_READS.CH1.ALL", + "PerPkg": "1", + "UMask": "0x204", + "Unit": "M2HBM" + }, + { + "BriefDescription": "UNC_M2HBM_IMC_READS.CH1.NORMAL", + "EventCode": "0x24", + "EventName": "UNC_M2HBM_IMC_READS.CH1.NORMAL", + "PerPkg": "1", + "UMask": "0x201", + "Unit": "M2HBM" + }, + { + "BriefDescription": "UNC_M2HBM_IMC_READS.CH1_ALL", + "EventCode": "0x24", + "EventName": "UNC_M2HBM_IMC_READS.CH1_ALL", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "UMask": "0x204", + "Unit": "M2HBM" + }, + { + "BriefDescription": "From TGR - Ch1", + "EventCode": "0x24", + "EventName": "UNC_M2HBM_IMC_READS.CH1_FROM_TGR", + "PerPkg": "1", + "UMask": "0x240", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Critical Priority - Ch1", + "EventCode": "0x24", + "EventName": "UNC_M2HBM_IMC_READS.CH1_ISOCH", + "PerPkg": "1", + "UMask": "0x202", + "Unit": "M2HBM" + }, + { + "BriefDescription": "UNC_M2HBM_IMC_READS.CH1_NORMAL", + "EventCode": "0x24", + "EventName": "UNC_M2HBM_IMC_READS.CH1_NORMAL", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "UMask": "0x201", + "Unit": "M2HBM" + }, + { + "BriefDescription": "From TGR - All Channels", + "EventCode": "0x24", + "EventName": "UNC_M2HBM_IMC_READS.FROM_TGR", + "PerPkg": "1", + "UMask": "0x340", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Critical Priority - All Channels", + "EventCode": "0x24", + "EventName": "UNC_M2HBM_IMC_READS.ISOCH", + "PerPkg": "1", + "UMask": "0x302", + "Unit": "M2HBM" + }, + { + "BriefDescription": "UNC_M2HBM_IMC_READS.NORMAL", + "EventCode": "0x24", + "EventName": "UNC_M2HBM_IMC_READS.NORMAL", + "PerPkg": "1", + "UMask": "0x301", + "Unit": "M2HBM" + }, + { + "BriefDescription": "All Writes - All Channels", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.ALL", + "PerPkg": "1", + "UMask": "0x1810", + "Unit": "M2HBM" + }, + { + "BriefDescription": "UNC_M2HBM_IMC_WRITES.CH0.ALL", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.CH0.ALL", + "PerPkg": "1", + "UMask": "0x810", + "Unit": "M2HBM" + }, + { + "BriefDescription": "UNC_M2HBM_IMC_WRITES.CH0.FULL", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.CH0.FULL", + "PerPkg": "1", + "UMask": "0x801", + "Unit": "M2HBM" + }, + { + "BriefDescription": "UNC_M2HBM_IMC_WRITES.CH0.PARTIAL", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.CH0.PARTIAL", + "PerPkg": "1", + "UMask": "0x802", + "Unit": "M2HBM" + }, + { + "BriefDescription": "UNC_M2HBM_IMC_WRITES.CH0_ALL", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.CH0_ALL", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "UMask": "0x810", + "Unit": "M2HBM" + }, + { + "BriefDescription": "From TGR - Ch0", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.CH0_FROM_TGR", + "PerPkg": "1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "UNC_M2HBM_IMC_WRITES.CH0_FULL", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.CH0_FULL", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "UMask": "0x801", + "Unit": "M2HBM" + }, + { + "BriefDescription": "ISOCH Full Line - Ch0", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.CH0_FULL_ISOCH", + "PerPkg": "1", + "UMask": "0x804", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Non-Inclusive - Ch0", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.CH0_NI", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Non-Inclusive Miss - Ch0", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.CH0_NI_MISS", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "Unit": "M2HBM" + }, + { + "BriefDescription": "UNC_M2HBM_IMC_WRITES.CH0_PARTIAL", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.CH0_PARTIAL", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "UMask": "0x802", + "Unit": "M2HBM" + }, + { + "BriefDescription": "ISOCH Partial - Ch0", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.CH0_PARTIAL_ISOCH", + "PerPkg": "1", + "UMask": "0x808", + "Unit": "M2HBM" + }, + { + "BriefDescription": "All Writes - Ch1", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.CH1.ALL", + "PerPkg": "1", + "UMask": "0x1010", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Full Line Non-ISOCH - Ch1", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.CH1.FULL", + "PerPkg": "1", + "UMask": "0x1001", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Partial Non-ISOCH - Ch1", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.CH1.PARTIAL", + "PerPkg": "1", + "UMask": "0x1002", + "Unit": "M2HBM" + }, + { + "BriefDescription": "All Writes - Ch1", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.CH1_ALL", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "UMask": "0x1010", + "Unit": "M2HBM" + }, + { + "BriefDescription": "From TGR - Ch1", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.CH1_FROM_TGR", + "PerPkg": "1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Full Line Non-ISOCH - Ch1", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.CH1_FULL", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "UMask": "0x1001", + "Unit": "M2HBM" + }, + { + "BriefDescription": "ISOCH Full Line - Ch1", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.CH1_FULL_ISOCH", + "PerPkg": "1", + "UMask": "0x1004", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Non-Inclusive - Ch1", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.CH1_NI", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Non-Inclusive Miss - Ch1", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.CH1_NI_MISS", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Partial Non-ISOCH - Ch1", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.CH1_PARTIAL", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "UMask": "0x1002", + "Unit": "M2HBM" + }, + { + "BriefDescription": "ISOCH Partial - Ch1", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.CH1_PARTIAL_ISOCH", + "PerPkg": "1", + "UMask": "0x1008", + "Unit": "M2HBM" + }, + { + "BriefDescription": "From TGR - All Channels", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.FROM_TGR", + "PerPkg": "1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Full Non-ISOCH - All Channels", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.FULL", + "PerPkg": "1", + "UMask": "0x1801", + "Unit": "M2HBM" + }, + { + "BriefDescription": "ISOCH Full Line - All Channels", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.FULL_ISOCH", + "PerPkg": "1", + "UMask": "0x1804", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Non-Inclusive - All Channels", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.NI", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Non-Inclusive Miss - All Channels", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.NI_MISS", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Partial Non-ISOCH - All Channels", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.PARTIAL", + "PerPkg": "1", + "UMask": "0x1802", + "Unit": "M2HBM" + }, + { + "BriefDescription": "ISOCH Partial - All Channels", + "EventCode": "0x25", + "EventName": "UNC_M2HBM_IMC_WRITES.PARTIAL_ISOCH", + "PerPkg": "1", + "UMask": "0x1808", + "Unit": "M2HBM" + }, + { + "BriefDescription": "UNC_M2HBM_PREFCAM_CIS_DROPS", + "EventCode": "0x5c", + "EventName": "UNC_M2HBM_PREFCAM_CIS_DROPS", + "PerPkg": "1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Data Prefetches Dropped", + "EventCode": "0x58", + "EventName": "UNC_M2HBM_PREFCAM_DEMAND_DROPS.CH0_UPI", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Data Prefetches Dropped", + "EventCode": "0x58", + "EventName": "UNC_M2HBM_PREFCAM_DEMAND_DROPS.CH0_XPT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Data Prefetches Dropped", + "EventCode": "0x58", + "EventName": "UNC_M2HBM_PREFCAM_DEMAND_DROPS.CH1_UPI", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Data Prefetches Dropped", + "EventCode": "0x58", + "EventName": "UNC_M2HBM_PREFCAM_DEMAND_DROPS.CH1_XPT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Data Prefetches Dropped : UPI - All Channels", + "EventCode": "0x58", + "EventName": "UNC_M2HBM_PREFCAM_DEMAND_DROPS.UPI_ALLCH", + "PerPkg": "1", + "UMask": "0xa", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Data Prefetches Dropped", + "EventCode": "0x58", + "EventName": "UNC_M2HBM_PREFCAM_DEMAND_DROPS.XPT_ALLCH", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "M2HBM" + }, + { + "BriefDescription": ": UPI - All Channels", + "EventCode": "0x5d", + "EventName": "UNC_M2HBM_PREFCAM_DEMAND_MERGE.UPI_ALLCH", + "PerPkg": "1", + "UMask": "0xa", + "Unit": "M2HBM" + }, + { + "BriefDescription": ": XPT - All Channels", + "EventCode": "0x5d", + "EventName": "UNC_M2HBM_PREFCAM_DEMAND_MERGE.XPT_ALLCH", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Demands Not Merged with CAMed Prefetches", + "EventCode": "0x5e", + "EventName": "UNC_M2HBM_PREFCAM_DEMAND_NO_MERGE.RD_MERGED", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Demands Not Merged with CAMed Prefetches", + "EventCode": "0x5e", + "EventName": "UNC_M2HBM_PREFCAM_DEMAND_NO_MERGE.WR_MERGED", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Demands Not Merged with CAMed Prefetches", + "EventCode": "0x5e", + "EventName": "UNC_M2HBM_PREFCAM_DEMAND_NO_MERGE.WR_SQUASHED", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0", + "EventCode": "0x56", + "EventName": "UNC_M2HBM_PREFCAM_INSERTS.CH0_UPI", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0", + "EventCode": "0x56", + "EventName": "UNC_M2HBM_PREFCAM_INSERTS.CH0_XPT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 1", + "EventCode": "0x56", + "EventName": "UNC_M2HBM_PREFCAM_INSERTS.CH1_UPI", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1", + "EventCode": "0x56", + "EventName": "UNC_M2HBM_PREFCAM_INSERTS.CH1_XPT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels", + "EventCode": "0x56", + "EventName": "UNC_M2HBM_PREFCAM_INSERTS.UPI_ALLCH", + "PerPkg": "1", + "UMask": "0xa", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels", + "EventCode": "0x56", + "EventName": "UNC_M2HBM_PREFCAM_INSERTS.XPT_ALLCH", + "PerPkg": "1", + "PublicDescription": "Prefetch CAM Inserts : XPT -All Channels", + "UMask": "0x5", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Prefetch CAM Occupancy : All Channels", + "EventCode": "0x54", + "EventName": "UNC_M2HBM_PREFCAM_OCCUPANCY.ALLCH", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Prefetch CAM Occupancy : Channel 0", + "EventCode": "0x54", + "EventName": "UNC_M2HBM_PREFCAM_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Prefetch CAM Occupancy : Channel 1", + "EventCode": "0x54", + "EventName": "UNC_M2HBM_PREFCAM_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2HBM" + }, + { + "BriefDescription": "All Channels", + "EventCode": "0x5f", + "EventName": "UNC_M2HBM_PREFCAM_RESP_MISS.ALLCH", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2HBM" + }, + { + "BriefDescription": ": Channel 0", + "EventCode": "0x5f", + "EventName": "UNC_M2HBM_PREFCAM_RESP_MISS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": ": Channel 1", + "EventCode": "0x5f", + "EventName": "UNC_M2HBM_PREFCAM_RESP_MISS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2HBM" + }, + { + "BriefDescription": "UNC_M2HBM_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "EventCode": "0x62", + "EventName": "UNC_M2HBM_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2HBM" + }, + { + "BriefDescription": "UNC_M2HBM_PREFCAM_RxC_DEALLOCS.CIS", + "EventCode": "0x62", + "EventName": "UNC_M2HBM_PREFCAM_RxC_DEALLOCS.CIS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2HBM" + }, + { + "BriefDescription": "UNC_M2HBM_PREFCAM_RxC_DEALLOCS.SQUASHED", + "EventCode": "0x62", + "EventName": "UNC_M2HBM_PREFCAM_RxC_DEALLOCS.SQUASHED", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "UNC_M2HBM_PREFCAM_RxC_OCCUPANCY", + "EventCode": "0x60", + "EventName": "UNC_M2HBM_PREFCAM_RxC_OCCUPANCY", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "Unit": "M2HBM" + }, + { + "BriefDescription": "AD Ingress (from CMS) : AD Ingress (from CMS) Allocations", + "EventCode": "0x02", + "EventName": "UNC_M2HBM_RxC_AD.INSERTS", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "AD Ingress (from CMS) : AD Ingress (from CMS) Allocations", + "EventCode": "0x02", + "EventName": "UNC_M2HBM_RxC_AD_INSERTS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "AD Ingress (from CMS) Occupancy", + "EventCode": "0x03", + "EventName": "UNC_M2HBM_RxC_AD_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "BL Ingress (from CMS) : BL Ingress (from CMS) Allocations", + "EventCode": "0x04", + "EventName": "UNC_M2HBM_RxC_BL.INSERTS", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts anytime a BL packet is added to Ingress", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "BL Ingress (from CMS) : BL Ingress (from CMS) Allocations", + "EventCode": "0x04", + "EventName": "UNC_M2HBM_RxC_BL_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts anytime a BL packet is added to Ingress", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "BL Ingress (from CMS) Occupancy", + "EventCode": "0x05", + "EventName": "UNC_M2HBM_RxC_BL_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Number AD Ingress Credits", + "EventCode": "0x2e", + "EventName": "UNC_M2HBM_TGR_AD_CREDITS", + "PerPkg": "1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Number BL Ingress Credits", + "EventCode": "0x2f", + "EventName": "UNC_M2HBM_TGR_BL_CREDITS", + "PerPkg": "1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Tracker Inserts : Channel 0", + "EventCode": "0x32", + "EventName": "UNC_M2HBM_TRACKER_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x104", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Tracker Inserts : Channel 1", + "EventCode": "0x32", + "EventName": "UNC_M2HBM_TRACKER_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x204", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Tracker Occupancy : Channel 0", + "EventCode": "0x33", + "EventName": "UNC_M2HBM_TRACKER_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Tracker Occupancy : Channel 1", + "EventCode": "0x33", + "EventName": "UNC_M2HBM_TRACKER_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2HBM" + }, + { + "BriefDescription": "AD Egress (to CMS) : AD Egress (to CMS) Allocations", + "EventCode": "0x06", + "EventName": "UNC_M2HBM_TxC_AD.INSERTS", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts anytime a AD packet is added to Egress", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "AD Egress (to CMS) : AD Egress (to CMS) Allocations", + "EventCode": "0x06", + "EventName": "UNC_M2HBM_TxC_AD_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts anytime a AD packet is added to Egress", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "AD Egress (to CMS) Occupancy", + "EventCode": "0x07", + "EventName": "UNC_M2HBM_TxC_AD_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "BL Egress (to CMS) : Inserts - CMS0 - Near Side", + "EventCode": "0x0E", + "EventName": "UNC_M2HBM_TxC_BL.INSERTS_CMS0", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts the number of BL transactions to CMS add port 0", + "UMask": "0x101", + "Unit": "M2HBM" + }, + { + "BriefDescription": "BL Egress (to CMS) : Inserts - CMS1 - Far Side", + "EventCode": "0x0E", + "EventName": "UNC_M2HBM_TxC_BL.INSERTS_CMS1", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts the number of BL transactions to CMS add port 1", + "UMask": "0x201", + "Unit": "M2HBM" + }, + { + "BriefDescription": "BL Egress (to CMS) Occupancy : All", + "EventCode": "0x0f", + "EventName": "UNC_M2HBM_TxC_BL_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2HBM" + }, + { + "BriefDescription": "BL Egress (to CMS) Occupancy : Common Mesh Stop - Near Side", + "EventCode": "0x0f", + "EventName": "UNC_M2HBM_TxC_BL_OCCUPANCY.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "BL Egress (to CMS) Occupancy : Common Mesh Stop - Far Side", + "EventCode": "0x0f", + "EventName": "UNC_M2HBM_TxC_BL_OCCUPANCY.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2HBM" + }, + { + "BriefDescription": "WPQ Flush : Channel 0", + "EventCode": "0x42", + "EventName": "UNC_M2HBM_WPQ_FLUSH.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "WPQ Flush : Channel 1", + "EventCode": "0x42", + "EventName": "UNC_M2HBM_WPQ_FLUSH.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2HBM" + }, + { + "BriefDescription": "M2M and iMC WPQ Cycles w/Credits - Regular : Channel 0", + "EventCode": "0x37", + "EventName": "UNC_M2HBM_WPQ_NO_REG_CRD.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "M2M and iMC WPQ Cycles w/Credits - Regular : Channel 1", + "EventCode": "0x37", + "EventName": "UNC_M2HBM_WPQ_NO_REG_CRD.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2HBM" + }, + { + "BriefDescription": "M2M and iMC WPQ Cycles w/Credits - Special : Channel 0", + "EventCode": "0x38", + "EventName": "UNC_M2HBM_WPQ_NO_SPEC_CRD.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "M2M and iMC WPQ Cycles w/Credits - Special : Channel 1", + "EventCode": "0x38", + "EventName": "UNC_M2HBM_WPQ_NO_SPEC_CRD.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Write Tracker Inserts : Channel 0", + "EventCode": "0x40", + "EventName": "UNC_M2HBM_WR_TRACKER_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Write Tracker Inserts : Channel 1", + "EventCode": "0x40", + "EventName": "UNC_M2HBM_WR_TRACKER_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0", + "EventCode": "0x4d", + "EventName": "UNC_M2HBM_WR_TRACKER_NONPOSTED_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1", + "EventCode": "0x4d", + "EventName": "UNC_M2HBM_WR_TRACKER_NONPOSTED_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 0", + "EventCode": "0x4c", + "EventName": "UNC_M2HBM_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 1", + "EventCode": "0x4c", + "EventName": "UNC_M2HBM_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Write Tracker Posted Inserts : Channel 0", + "EventCode": "0x48", + "EventName": "UNC_M2HBM_WR_TRACKER_POSTED_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Write Tracker Posted Inserts : Channel 1", + "EventCode": "0x48", + "EventName": "UNC_M2HBM_WR_TRACKER_POSTED_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Write Tracker Posted Occupancy : Channel 0", + "EventCode": "0x47", + "EventName": "UNC_M2HBM_WR_TRACKER_POSTED_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Write Tracker Posted Occupancy : Channel 1", + "EventCode": "0x47", + "EventName": "UNC_M2HBM_WR_TRACKER_POSTED_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2HBM" + }, + { + "BriefDescription": "Activate due to read, write, underfill, or bypass", + "EventCode": "0x02", + "EventName": "UNC_MCHBM_ACT_COUNT.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.", + "UMask": "0xff", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Activate due to read", + "EventCode": "0x02", + "EventName": "UNC_MCHBM_ACT_COUNT.RD", + "PerPkg": "1", + "PublicDescription": "Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.", + "UMask": "0x11", + "Unit": "MCHBM" + }, + { + "BriefDescription": "HBM Activate Count : Activate due to Read in PCH0", + "EventCode": "0x02", + "EventName": "UNC_MCHBM_ACT_COUNT.RD_PCH0", + "PerPkg": "1", + "PublicDescription": "Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.", + "UMask": "0x1", + "Unit": "MCHBM" + }, + { + "BriefDescription": "HBM Activate Count : Activate due to Read in PCH1", + "EventCode": "0x02", + "EventName": "UNC_MCHBM_ACT_COUNT.RD_PCH1", + "PerPkg": "1", + "PublicDescription": "Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.", + "UMask": "0x10", + "Unit": "MCHBM" + }, + { + "BriefDescription": "HBM Activate Count : Underfill Read transaction on Page Empty or Page Miss", + "EventCode": "0x02", + "EventName": "UNC_MCHBM_ACT_COUNT.UFILL", + "PerPkg": "1", + "PublicDescription": "Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.", + "UMask": "0x44", + "Unit": "MCHBM" + }, + { + "BriefDescription": "HBM Activate Count", + "EventCode": "0x02", + "EventName": "UNC_MCHBM_ACT_COUNT.UFILL_PCH0", + "PerPkg": "1", + "PublicDescription": "Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.", + "UMask": "0x4", + "Unit": "MCHBM" + }, + { + "BriefDescription": "HBM Activate Count", + "EventCode": "0x02", + "EventName": "UNC_MCHBM_ACT_COUNT.UFILL_PCH1", + "PerPkg": "1", + "PublicDescription": "Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.", + "UMask": "0x40", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Activate due to write", + "EventCode": "0x02", + "EventName": "UNC_MCHBM_ACT_COUNT.WR", + "PerPkg": "1", + "PublicDescription": "Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.", + "UMask": "0x22", + "Unit": "MCHBM" + }, + { + "BriefDescription": "HBM Activate Count : Activate due to Write in PCH0", + "EventCode": "0x02", + "EventName": "UNC_MCHBM_ACT_COUNT.WR_PCH0", + "PerPkg": "1", + "PublicDescription": "Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.", + "UMask": "0x2", + "Unit": "MCHBM" + }, + { + "BriefDescription": "HBM Activate Count : Activate due to Write in PCH1", + "EventCode": "0x02", + "EventName": "UNC_MCHBM_ACT_COUNT.WR_PCH1", + "PerPkg": "1", + "PublicDescription": "Counts the number of HBM Activate commands sent on this channel. Activate commands are issued to open up a page on the HBM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.", + "UMask": "0x20", + "Unit": "MCHBM" + }, + { + "BriefDescription": "All CAS commands issued", + "EventCode": "0x05", + "EventName": "UNC_MCHBM_CAS_COUNT.ALL", + "PerPkg": "1", + "UMask": "0xff", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Pseudo Channel 0", + "EventCode": "0x05", + "EventName": "UNC_MCHBM_CAS_COUNT.PCH0", + "PerPkg": "1", + "PublicDescription": "HBM RD_CAS and WR_CAS Commands", + "UMask": "0x40", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Pseudo Channel 1", + "EventCode": "0x05", + "EventName": "UNC_MCHBM_CAS_COUNT.PCH1", + "PerPkg": "1", + "PublicDescription": "HBM RD_CAS and WR_CAS Commands", + "UMask": "0x80", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Read CAS commands issued (regular and underfill)", + "EventCode": "0x05", + "EventName": "UNC_MCHBM_CAS_COUNT.RD", + "PerPkg": "1", + "UMask": "0xcf", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Regular read CAS commands with precharge", + "EventCode": "0x05", + "EventName": "UNC_MCHBM_CAS_COUNT.RD_PRE_REG", + "PerPkg": "1", + "UMask": "0xc2", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Underfill read CAS commands with precharge", + "EventCode": "0x05", + "EventName": "UNC_MCHBM_CAS_COUNT.RD_PRE_UNDERFILL", + "PerPkg": "1", + "UMask": "0xc8", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Regular read CAS commands issued (does not include underfills)", + "EventCode": "0x05", + "EventName": "UNC_MCHBM_CAS_COUNT.RD_REG", + "PerPkg": "1", + "UMask": "0xc1", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Underfill read CAS commands issued", + "EventCode": "0x05", + "EventName": "UNC_MCHBM_CAS_COUNT.RD_UNDERFILL", + "PerPkg": "1", + "UMask": "0xc4", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Write CAS commands issued", + "EventCode": "0x05", + "EventName": "UNC_MCHBM_CAS_COUNT.WR", + "PerPkg": "1", + "UMask": "0xf0", + "Unit": "MCHBM" + }, + { + "BriefDescription": "HBM RD_CAS and WR_CAS Commands. : HBM WR_CAS commands w/o auto-pre", + "EventCode": "0x05", + "EventName": "UNC_MCHBM_CAS_COUNT.WR_NONPRE", + "PerPkg": "1", + "UMask": "0xd0", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Write CAS commands with precharge", + "EventCode": "0x05", + "EventName": "UNC_MCHBM_CAS_COUNT.WR_PRE", + "PerPkg": "1", + "UMask": "0xe0", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Pseudo Channel 0", + "EventCode": "0x06", + "EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.PCH0", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Pseudo Channel 1", + "EventCode": "0x06", + "EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.PCH1", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Read CAS Command in Interleaved Mode (32B)", + "EventCode": "0x06", + "EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.RD_32B", + "PerPkg": "1", + "UMask": "0xc8", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Read CAS Command in Regular Mode (64B) in Pseudochannel 0", + "EventCode": "0x06", + "EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.RD_64B", + "PerPkg": "1", + "UMask": "0xc1", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Underfill Read CAS Command in Interleaved Mode (32B)", + "EventCode": "0x06", + "EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.RD_UFILL_32B", + "PerPkg": "1", + "UMask": "0xd0", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Underfill Read CAS Command in Regular Mode (64B) in Pseudochannel 1", + "EventCode": "0x06", + "EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.RD_UFILL_64B", + "PerPkg": "1", + "UMask": "0xc2", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Write CAS Command in Interleaved Mode (32B)", + "EventCode": "0x06", + "EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.WR_32B", + "PerPkg": "1", + "UMask": "0xe0", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Write CAS Command in Regular Mode (64B) in Pseudochannel 0", + "EventCode": "0x06", + "EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.WR_64B", + "PerPkg": "1", + "UMask": "0xc4", + "Unit": "MCHBM" + }, + { + "BriefDescription": "IMC Clockticks at DCLK frequency", + "EventCode": "0x01", + "EventName": "UNC_MCHBM_CLOCKTICKS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "MCHBM" + }, + { + "BriefDescription": "HBM Precharge All Commands", + "EventCode": "0x44", + "EventName": "UNC_MCHBM_HBM_PREALL.PCH0", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that the precharge all command was sent.", + "UMask": "0x1", + "Unit": "MCHBM" + }, + { + "BriefDescription": "HBM Precharge All Commands", + "EventCode": "0x44", + "EventName": "UNC_MCHBM_HBM_PREALL.PCH1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that the precharge all command was sent.", + "UMask": "0x2", + "Unit": "MCHBM" + }, + { + "BriefDescription": "All Precharge Commands", + "EventCode": "0x44", + "EventName": "UNC_MCHBM_HBM_PRE_ALL", + "PerPkg": "1", + "PublicDescription": "Precharge All Commands: Counts the number of times that the precharge all command was sent.", + "UMask": "0x3", + "Unit": "MCHBM" + }, + { + "BriefDescription": "IMC Clockticks at HCLK frequency", + "EventCode": "0x01", + "EventName": "UNC_MCHBM_HCLOCKTICKS", + "PerPkg": "1", + "Unit": "MCHBM" + }, + { + "BriefDescription": "All precharge events", + "EventCode": "0x03", + "EventName": "UNC_MCHBM_PRE_COUNT.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of HBM Precharge commands sent on this channel.", + "UMask": "0xff", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Precharge from MC page table", + "EventCode": "0x03", + "EventName": "UNC_MCHBM_PRE_COUNT.PGT", + "PerPkg": "1", + "PublicDescription": "Counts the number of HBM Precharge commands sent on this channel.", + "UMask": "0x88", + "Unit": "MCHBM" + }, + { + "BriefDescription": "HBM Precharge commands. : Precharges from Page Table", + "EventCode": "0x03", + "EventName": "UNC_MCHBM_PRE_COUNT.PGT_PCH0", + "PerPkg": "1", + "PublicDescription": "Counts the number of HBM Precharge commands sent on this channel. : Equivalent to PAGE_EMPTY", + "UMask": "0x8", + "Unit": "MCHBM" + }, + { + "BriefDescription": "HBM Precharge commands.", + "EventCode": "0x03", + "EventName": "UNC_MCHBM_PRE_COUNT.PGT_PCH1", + "PerPkg": "1", + "PublicDescription": "Counts the number of HBM Precharge commands sent on this channel.", + "UMask": "0x80", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Precharge due to read on page miss", + "EventCode": "0x03", + "EventName": "UNC_MCHBM_PRE_COUNT.RD", + "PerPkg": "1", + "PublicDescription": "Counts the number of HBM Precharge commands sent on this channel.", + "UMask": "0x11", + "Unit": "MCHBM" + }, + { + "BriefDescription": "HBM Precharge commands. : Precharge due to read", + "EventCode": "0x03", + "EventName": "UNC_MCHBM_PRE_COUNT.RD_PCH0", + "PerPkg": "1", + "PublicDescription": "Counts the number of HBM Precharge commands sent on this channel. : Precharge from read bank scheduler", + "UMask": "0x1", + "Unit": "MCHBM" + }, + { + "BriefDescription": "HBM Precharge commands.", + "EventCode": "0x03", + "EventName": "UNC_MCHBM_PRE_COUNT.RD_PCH1", + "PerPkg": "1", + "PublicDescription": "Counts the number of HBM Precharge commands sent on this channel.", + "UMask": "0x10", + "Unit": "MCHBM" + }, + { + "BriefDescription": "HBM Precharge commands.", + "EventCode": "0x03", + "EventName": "UNC_MCHBM_PRE_COUNT.UFILL", + "PerPkg": "1", + "PublicDescription": "Counts the number of HBM Precharge commands sent on this channel.", + "UMask": "0x44", + "Unit": "MCHBM" + }, + { + "BriefDescription": "HBM Precharge commands.", + "EventCode": "0x03", + "EventName": "UNC_MCHBM_PRE_COUNT.UFILL_PCH0", + "PerPkg": "1", + "PublicDescription": "Counts the number of HBM Precharge commands sent on this channel.", + "UMask": "0x4", + "Unit": "MCHBM" + }, + { + "BriefDescription": "HBM Precharge commands.", + "EventCode": "0x03", + "EventName": "UNC_MCHBM_PRE_COUNT.UFILL_PCH1", + "PerPkg": "1", + "PublicDescription": "Counts the number of HBM Precharge commands sent on this channel.", + "UMask": "0x40", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Precharge due to write on page miss", + "EventCode": "0x03", + "EventName": "UNC_MCHBM_PRE_COUNT.WR", + "PerPkg": "1", + "PublicDescription": "Counts the number of HBM Precharge commands sent on this channel.", + "UMask": "0x22", + "Unit": "MCHBM" + }, + { + "BriefDescription": "HBM Precharge commands. : Precharge due to write", + "EventCode": "0x03", + "EventName": "UNC_MCHBM_PRE_COUNT.WR_PCH0", + "PerPkg": "1", + "PublicDescription": "Counts the number of HBM Precharge commands sent on this channel. : Precharge from write bank scheduler", + "UMask": "0x2", + "Unit": "MCHBM" + }, + { + "BriefDescription": "HBM Precharge commands.", + "EventCode": "0x03", + "EventName": "UNC_MCHBM_PRE_COUNT.WR_PCH1", + "PerPkg": "1", + "PublicDescription": "Counts the number of HBM Precharge commands sent on this channel.", + "UMask": "0x20", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Counts the number of cycles where the read buffer has greater than UMASK elements. NOTE: Umask must be set to the maximum number of elements in the queue (24 entries for SPR).", + "EventCode": "0x19", + "EventName": "UNC_MCHBM_RDB_FULL", + "PerPkg": "1", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Counts the number of inserts into the read buffer.", + "EventCode": "0x17", + "EventName": "UNC_MCHBM_RDB_INSERTS", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Read Data Buffer Inserts", + "EventCode": "0x17", + "EventName": "UNC_MCHBM_RDB_INSERTS.PCH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Read Data Buffer Inserts", + "EventCode": "0x17", + "EventName": "UNC_MCHBM_RDB_INSERTS.PCH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Counts the number of elements in the read buffer per cycle.", + "EventCode": "0x1a", + "EventName": "UNC_MCHBM_RDB_OCCUPANCY", + "PerPkg": "1", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Read Pending Queue Allocations", + "EventCode": "0x10", + "EventName": "UNC_MCHBM_RPQ_INSERTS.PCH0", + "PerPkg": "1", + "PublicDescription": "Read Pending Queue Allocations: Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.", + "UMask": "0x1", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Read Pending Queue Allocations", + "EventCode": "0x10", + "EventName": "UNC_MCHBM_RPQ_INSERTS.PCH1", + "PerPkg": "1", + "PublicDescription": "Read Pending Queue Allocations: Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.", + "UMask": "0x2", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Read Pending Queue Occupancy", + "EventCode": "0x80", + "EventName": "UNC_MCHBM_RPQ_OCCUPANCY_PCH0", + "PerPkg": "1", + "PublicDescription": "Read Pending Queue Occupancy: Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Read Pending Queue Occupancy", + "EventCode": "0x81", + "EventName": "UNC_MCHBM_RPQ_OCCUPANCY_PCH1", + "PerPkg": "1", + "PublicDescription": "Read Pending Queue Occupancy: Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Write Pending Queue Allocations", + "EventCode": "0x20", + "EventName": "UNC_MCHBM_WPQ_INSERTS.PCH0", + "PerPkg": "1", + "PublicDescription": "Write Pending Queue Allocations: Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.", + "UMask": "0x1", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Write Pending Queue Allocations", + "EventCode": "0x20", + "EventName": "UNC_MCHBM_WPQ_INSERTS.PCH1", + "PerPkg": "1", + "PublicDescription": "Write Pending Queue Allocations: Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.", + "UMask": "0x2", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Write Pending Queue Occupancy", + "EventCode": "0x82", + "EventName": "UNC_MCHBM_WPQ_OCCUPANCY_PCH0", + "PerPkg": "1", + "PublicDescription": "Write Pending Queue Occupancy: Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to memory. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Write Pending Queue Occupancy", + "EventCode": "0x83", + "EventName": "UNC_MCHBM_WPQ_OCCUPANCY_PCH1", + "PerPkg": "1", + "PublicDescription": "Write Pending Queue Occupancy: Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to memory. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "EventCode": "0x23", + "EventName": "UNC_MCHBM_WPQ_READ_HIT", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "EventCode": "0x23", + "EventName": "UNC_MCHBM_WPQ_READ_HIT.PCH0", + "PerPkg": "1", + "PublicDescription": "Write Pending Queue CAM Match: Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.", + "UMask": "0x1", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "EventCode": "0x23", + "EventName": "UNC_MCHBM_WPQ_READ_HIT.PCH1", + "PerPkg": "1", + "PublicDescription": "Write Pending Queue CAM Match: Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.", + "UMask": "0x2", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "EventCode": "0x24", + "EventName": "UNC_MCHBM_WPQ_WRITE_HIT", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "EventCode": "0x24", + "EventName": "UNC_MCHBM_WPQ_WRITE_HIT.PCH0", + "PerPkg": "1", + "PublicDescription": "Write Pending Queue CAM Match: Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.", + "UMask": "0x1", + "Unit": "MCHBM" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "EventCode": "0x24", + "EventName": "UNC_MCHBM_WPQ_WRITE_HIT.PCH1", + "PerPkg": "1", + "PublicDescription": "Write Pending Queue CAM Match: Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.", + "UMask": "0x2", + "Unit": "MCHBM" + }, { "BriefDescription": "Activate due to read, write, underfill, or bypass", "EventCode": "0x02", "EventName": "UNC_M_ACT_COUNT.ALL", "PerPkg": "1", - "PublicDescription": "DRAM Activate Count : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.", - "UMask": "0xff", + "PublicDescription": "DRAM Activate Count : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.", + "UMask": "0xff", + "Unit": "iMC" + }, + { + "BriefDescription": "All DRAM CAS commands issued", + "EventCode": "0x05", + "EventName": "UNC_M_CAS_COUNT.ALL", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : All DRAM Read and Write actions : DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM CAS commands issued on this channel.", + "UMask": "0xff", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 0", + "EventCode": "0x05", + "EventName": "UNC_M_CAS_COUNT.PCH0", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 0 : DRAM RD_CAS and WR_CAS Commands", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 1", + "EventCode": "0x05", + "EventName": "UNC_M_CAS_COUNT.PCH1", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 1 : DRAM RD_CAS and WR_CAS Commands", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "All DRAM read CAS commands issued (including underfills)", + "EventCode": "0x05", + "EventName": "UNC_M_CAS_COUNT.RD", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM Read CAS commands issued on this channel. This includes underfills.", + "UMask": "0xcf", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.", + "EventCode": "0x05", + "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands", + "UMask": "0xc2", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.", + "EventCode": "0x05", + "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands", + "UMask": "0xc8", + "Unit": "iMC" + }, + { + "BriefDescription": "All DRAM read CAS commands issued (does not include underfills)", + "EventCode": "0x05", + "EventName": "UNC_M_CAS_COUNT.RD_REG", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/out auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the total number or DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with implicit Precharge. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).", + "UMask": "0xc1", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM underfill read CAS commands issued", + "EventCode": "0x05", + "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : Underfill Read Issued : DRAM RD_CAS and WR_CAS Commands", + "UMask": "0xc4", + "Unit": "iMC" + }, + { + "BriefDescription": "All DRAM write CAS commands issued", + "EventCode": "0x05", + "EventName": "UNC_M_CAS_COUNT.WR", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM Write CAS commands issued on this channel.", + "UMask": "0xf0", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre", + "EventCode": "0x05", + "EventName": "UNC_M_CAS_COUNT.WR_NONPRE", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre : DRAM RD_CAS and WR_CAS Commands", + "UMask": "0xd0", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.", + "EventCode": "0x05", + "EventName": "UNC_M_CAS_COUNT.WR_PRE", + "PerPkg": "1", + "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands", + "UMask": "0xe0", + "Unit": "iMC" + }, + { + "BriefDescription": "Pseudo Channel 0", + "EventCode": "0x06", + "EventName": "UNC_M_CAS_ISSUED_REQ_LEN.PCH0", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "Pseudo Channel 1", + "EventCode": "0x06", + "EventName": "UNC_M_CAS_ISSUED_REQ_LEN.PCH1", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS Command in Interleaved Mode (32B)", + "EventCode": "0x06", + "EventName": "UNC_M_CAS_ISSUED_REQ_LEN.RD_32B", + "PerPkg": "1", + "UMask": "0xc8", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS Command in Regular Mode (64B) in Pseudochannel 0", + "EventCode": "0x06", + "EventName": "UNC_M_CAS_ISSUED_REQ_LEN.RD_64B", + "PerPkg": "1", + "UMask": "0xc1", + "Unit": "iMC" + }, + { + "BriefDescription": "Underfill Read CAS Command in Interleaved Mode (32B)", + "EventCode": "0x06", + "EventName": "UNC_M_CAS_ISSUED_REQ_LEN.RD_UFILL_32B", + "PerPkg": "1", + "UMask": "0xd0", + "Unit": "iMC" + }, + { + "BriefDescription": "Underfill Read CAS Command in Regular Mode (64B) in Pseudochannel 1", + "EventCode": "0x06", + "EventName": "UNC_M_CAS_ISSUED_REQ_LEN.RD_UFILL_64B", + "PerPkg": "1", + "UMask": "0xc2", + "Unit": "iMC" + }, + { + "BriefDescription": "Write CAS Command in Interleaved Mode (32B)", + "EventCode": "0x06", + "EventName": "UNC_M_CAS_ISSUED_REQ_LEN.WR_32B", + "PerPkg": "1", + "UMask": "0xe0", + "Unit": "iMC" + }, + { + "BriefDescription": "Write CAS Command in Regular Mode (64B) in Pseudochannel 0", + "EventCode": "0x06", + "EventName": "UNC_M_CAS_ISSUED_REQ_LEN.WR_64B", + "PerPkg": "1", + "UMask": "0xc4", + "Unit": "iMC" + }, + { + "BriefDescription": "IMC Clockticks at DCLK frequency", + "EventCode": "0x01", + "EventName": "UNC_M_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Number of DRAM DCLK clock cycles while the event is enabled", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge All Commands", + "EventCode": "0x44", + "EventName": "UNC_M_DRAM_PRE_ALL", + "PerPkg": "1", + "PublicDescription": "DRAM Precharge All Commands : Counts the number of times that the precharge all command was sent.", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "IMC Clockticks at HCLK frequency", + "EventCode": "0x01", + "EventName": "UNC_M_HCLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Number of DRAM HCLK clock cycles while the event is enabled", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_PCLS.RD", + "EventCode": "0xa0", + "EventName": "UNC_M_PCLS.RD", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_PCLS.TOTAL", + "EventCode": "0xa0", + "EventName": "UNC_M_PCLS.TOTAL", + "PerPkg": "1", + "UMask": "0xf", + "Unit": "iMC" + }, + { + "BriefDescription": "UNC_M_PCLS.WR", + "EventCode": "0xa0", + "EventName": "UNC_M_PCLS.WR", + "PerPkg": "1", + "UMask": "0xa", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Read Pending Queue inserts", + "EventCode": "0xe3", + "EventName": "UNC_M_PMM_RPQ_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts number of read requests allocated in the PMM Read Pending Queue.", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Read Pending Queue occupancy", + "EventCode": "0xe0", + "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH0", + "PerPkg": "1", + "PublicDescription": "Accumulates the per cycle occupancy of the PMM Read Pending Queue.", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Read Pending Queue occupancy", + "EventCode": "0xe0", + "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH1", + "PerPkg": "1", + "PublicDescription": "Accumulates the per cycle occupancy of the PMM Read Pending Queue.", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Read Pending Queue Occupancy", + "EventCode": "0xE0", + "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT_SCH0", + "PerPkg": "1", + "PublicDescription": "PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue.", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Read Pending Queue Occupancy", + "EventCode": "0xE0", + "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT_SCH1", + "PerPkg": "1", + "PublicDescription": "PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue.", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Read Pending Queue Occupancy", + "EventCode": "0xe0", + "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT_SCH0", + "PerPkg": "1", + "PublicDescription": "Accumulates the per cycle occupancy of the PMM Read Pending Queue.", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Read Pending Queue Occupancy", + "EventCode": "0xe0", + "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT_SCH1", + "PerPkg": "1", + "PublicDescription": "Accumulates the per cycle occupancy of the PMM Read Pending Queue.", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM (for IXP) Write Queue Cycles Not Empty", + "EventCode": "0xe5", + "EventName": "UNC_M_PMM_WPQ_CYCLES_NE", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Write Pending Queue inserts", + "EventCode": "0xe7", + "EventName": "UNC_M_PMM_WPQ_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts number of write requests allocated in the PMM Write Pending Queue.", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Write Pending Queue Occupancy", + "EventCode": "0xe4", + "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL", + "PerPkg": "1", + "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the Write Pending Queue to the PMM DIMM.", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Write Pending Queue Occupancy", + "EventCode": "0xE4", + "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH0", + "PerPkg": "1", + "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue.", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM Write Pending Queue Occupancy", + "EventCode": "0xE4", + "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH1", + "PerPkg": "1", + "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue.", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM (for IXP) Write Pending Queue Occupancy", + "EventCode": "0xe4", + "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.CAS", + "PerPkg": "1", + "PublicDescription": "PMM (for IXP) Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the Write Pending Queue to the IXP DIMM.", + "UMask": "0xc", + "Unit": "iMC" + }, + { + "BriefDescription": "PMM (for IXP) Write Pending Queue Occupancy", + "EventCode": "0xe4", + "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.PWR", + "PerPkg": "1", + "PublicDescription": "PMM (for IXP) Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the Write Pending Queue to the IXP DIMM.", + "UMask": "0x30", + "Unit": "iMC" + }, + { + "BriefDescription": "Channel PPD Cycles", + "EventCode": "0x85", + "EventName": "UNC_M_POWER_CHANNEL_PPD", + "PerPkg": "1", + "PublicDescription": "Channel PPD Cycles : Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "EventCode": "0x47", + "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_0", + "PerPkg": "1", + "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "EventCode": "0x47", + "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_1", + "PerPkg": "1", + "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "EventCode": "0x47", + "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_2", + "PerPkg": "1", + "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "EventCode": "0x47", + "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_3", + "PerPkg": "1", + "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0", + "EventCode": "0x86", + "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT0", + "PerPkg": "1", + "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. : Thermal throttling is performed per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by ID.", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Throttle Cycles for Rank 0", + "EventCode": "0x86", + "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT1", + "PerPkg": "1", + "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Clock-Enabled Self-Refresh", + "EventCode": "0x43", + "EventName": "UNC_M_POWER_SELF_REFRESH", + "PerPkg": "1", + "PublicDescription": "Clock-Enabled Self-Refresh : Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.", + "Unit": "iMC" + }, + { + "BriefDescription": "Precharge due to read, write, underfill, or PGT.", + "EventCode": "0x03", + "EventName": "UNC_M_PRE_COUNT.ALL", + "PerPkg": "1", + "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", + "UMask": "0xff", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands. : Precharge due to (?)", + "EventCode": "0x03", + "EventName": "UNC_M_PRE_COUNT.PGT", + "PerPkg": "1", + "PublicDescription": "DRAM Precharge commands. : Precharge due to (?) : Counts the number of DRAM Precharge commands sent on this channel.", + "UMask": "0x88", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands. : Precharges from Page Table", + "EventCode": "0x03", + "EventName": "UNC_M_PRE_COUNT.PGT_PCH0", + "PerPkg": "1", + "PublicDescription": "DRAM Precharge commands. : Precharges from Page Table : Counts the number of DRAM Precharge commands sent on this channel. : Equivalent to PAGE_EMPTY", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands.", + "EventCode": "0x03", + "EventName": "UNC_M_PRE_COUNT.PGT_PCH1", + "PerPkg": "1", + "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": "Precharge due to read on page miss", + "EventCode": "0x03", + "EventName": "UNC_M_PRE_COUNT.RD", + "PerPkg": "1", + "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", + "UMask": "0x11", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands. : Precharge due to read", + "EventCode": "0x03", + "EventName": "UNC_M_PRE_COUNT.RD_PCH0", + "PerPkg": "1", + "PublicDescription": "DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "All DRAM CAS commands issued", - "EventCode": "0x05", - "EventName": "UNC_M_CAS_COUNT.ALL", + "BriefDescription": "DRAM Precharge commands.", + "EventCode": "0x03", + "EventName": "UNC_M_PRE_COUNT.RD_PCH1", "PerPkg": "1", - "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : All DRAM Read and Write actions : DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM CAS commands issued on this channel.", - "UMask": "0xff", + "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", + "UMask": "0x10", "Unit": "iMC" }, { - "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 0", - "EventCode": "0x05", - "EventName": "UNC_M_CAS_COUNT.PCH0", + "BriefDescription": "DRAM Precharge commands.", + "EventCode": "0x03", + "EventName": "UNC_M_PRE_COUNT.UFILL", "PerPkg": "1", - "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 0 : DRAM RD_CAS and WR_CAS Commands", + "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", + "UMask": "0x44", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands.", + "EventCode": "0x03", + "EventName": "UNC_M_PRE_COUNT.UFILL_PCH0", + "PerPkg": "1", + "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands.", + "EventCode": "0x03", + "EventName": "UNC_M_PRE_COUNT.UFILL_PCH1", + "PerPkg": "1", + "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", "UMask": "0x40", "Unit": "iMC" }, { - "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 1", - "EventCode": "0x05", - "EventName": "UNC_M_CAS_COUNT.PCH1", + "BriefDescription": "Precharge due to write on page miss", + "EventCode": "0x03", + "EventName": "UNC_M_PRE_COUNT.WR", + "PerPkg": "1", + "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", + "UMask": "0x22", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands. : Precharge due to write", + "EventCode": "0x03", + "EventName": "UNC_M_PRE_COUNT.WR_PCH0", + "PerPkg": "1", + "PublicDescription": "DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands.", + "EventCode": "0x03", + "EventName": "UNC_M_PRE_COUNT.WR_PCH1", + "PerPkg": "1", + "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "Counts the number of cycles where the read buffer has greater than UMASK elements. This includes reads to both DDR and PMEM. NOTE: Umask must be set to the maximum number of elements in the queue (24 entries for SPR).", + "EventCode": "0x19", + "EventName": "UNC_M_RDB_FULL", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Counts the number of inserts into the read buffer destined for DDR. Does not count reads destined for PMEM.", + "EventCode": "0x17", + "EventName": "UNC_M_RDB_INSERTS", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Data Buffer Inserts", + "EventCode": "0x17", + "EventName": "UNC_M_RDB_INSERTS.PCH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Data Buffer Inserts", + "EventCode": "0x17", + "EventName": "UNC_M_RDB_INSERTS.PCH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Counts the number of cycles where there's at least one element in the read buffer. This includes reads to both DDR and PMEM.", + "EventCode": "0x18", + "EventName": "UNC_M_RDB_NE", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Data Buffer Not Empty", + "EventCode": "0x18", + "EventName": "UNC_M_RDB_NE.PCH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Data Buffer Not Empty", + "EventCode": "0x18", + "EventName": "UNC_M_RDB_NE.PCH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Counts the number of cycles where there's at least one element in the read buffer. This includes reads to both DDR and PMEM.", + "EventCode": "0x18", + "EventName": "UNC_M_RDB_NOT_EMPTY", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "iMC" + }, + { + "BriefDescription": "Counts the number of elements in the read buffer, including reads to both DDR and PMEM.", + "EventCode": "0x1a", + "EventName": "UNC_M_RDB_OCCUPANCY", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Allocations", + "EventCode": "0x10", + "EventName": "UNC_M_RPQ_INSERTS.PCH0", + "PerPkg": "1", + "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Allocations", + "EventCode": "0x10", + "EventName": "UNC_M_RPQ_INSERTS.PCH1", + "PerPkg": "1", + "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Occupancy", + "EventCode": "0x80", + "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0", + "PerPkg": "1", + "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Occupancy", + "EventCode": "0x81", + "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1", + "PerPkg": "1", + "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard accepts", + "EventCode": "0xd2", + "EventName": "UNC_M_SB_ACCESSES.ACCEPTS", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses : Write Accepts", + "EventCode": "0xd2", + "EventName": "UNC_M_SB_ACCESSES.FM_RD_CMPS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses : Write Rejects", + "EventCode": "0xd2", + "EventName": "UNC_M_SB_ACCESSES.FM_WR_CMPS", "PerPkg": "1", - "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Channel 1 : DRAM RD_CAS and WR_CAS Commands", "UMask": "0x80", "Unit": "iMC" }, { - "BriefDescription": "All DRAM read CAS commands issued (including underfills)", - "EventCode": "0x05", - "EventName": "UNC_M_CAS_COUNT.RD", + "BriefDescription": "Scoreboard Accesses : FM read completions", + "EventCode": "0xd2", + "EventName": "UNC_M_SB_ACCESSES.NM_RD_CMPS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses : FM write completions", + "EventCode": "0xd2", + "EventName": "UNC_M_SB_ACCESSES.NM_WR_CMPS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses : Read Accepts", + "EventCode": "0xd2", + "EventName": "UNC_M_SB_ACCESSES.RD_ACCEPTS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses : Read Rejects", + "EventCode": "0xd2", + "EventName": "UNC_M_SB_ACCESSES.RD_REJECTS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard rejects", + "EventCode": "0xd2", + "EventName": "UNC_M_SB_ACCESSES.REJECTS", + "PerPkg": "1", + "UMask": "0xa", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses : NM read completions", + "EventCode": "0xd2", + "EventName": "UNC_M_SB_ACCESSES.WR_ACCEPTS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Accesses : NM write completions", + "EventCode": "0xd2", + "EventName": "UNC_M_SB_ACCESSES.WR_REJECTS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": ": Alloc", + "EventCode": "0xd9", + "EventName": "UNC_M_SB_CANARY.ALLOC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "iMC" + }, + { + "BriefDescription": ": Dealloc", + "EventCode": "0xd9", + "EventName": "UNC_M_SB_CANARY.DEALLOC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "iMC" + }, + { + "BriefDescription": ": Near Mem Write Starved", + "EventCode": "0xd9", + "EventName": "UNC_M_SB_CANARY.FM_RD_STARVED", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": ": Far Mem Write Starved", + "EventCode": "0xd9", + "EventName": "UNC_M_SB_CANARY.FM_TGR_WR_STARVED", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "iMC" + }, + { + "BriefDescription": ": Far Mem Read Starved", + "EventCode": "0xd9", + "EventName": "UNC_M_SB_CANARY.FM_WR_STARVED", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "iMC" + }, + { + "BriefDescription": ": Valid", + "EventCode": "0xd9", + "EventName": "UNC_M_SB_CANARY.NM_RD_STARVED", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": ": Near Mem Read Starved", + "EventCode": "0xd9", + "EventName": "UNC_M_SB_CANARY.NM_WR_STARVED", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": ": Reject", + "EventCode": "0xd9", + "EventName": "UNC_M_SB_CANARY.VLD", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Cycles Full", + "EventCode": "0xd1", + "EventName": "UNC_M_SB_CYCLES_FULL", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Cycles Not-Empty", + "EventCode": "0xd0", + "EventName": "UNC_M_SB_CYCLES_NE", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Inserts : Block region reads", + "EventCode": "0xd6", + "EventName": "UNC_M_SB_INSERTS.BLOCK_RDS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Inserts : Block region writes", + "EventCode": "0xd6", + "EventName": "UNC_M_SB_INSERTS.BLOCK_WRS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Inserts : Persistent Mem reads", + "EventCode": "0xd6", + "EventName": "UNC_M_SB_INSERTS.PMM_RDS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": "Scoreboard Inserts : Persistent Mem writes", + "EventCode": "0xd6", + "EventName": "UNC_M_SB_INSERTS.PMM_WRS", "PerPkg": "1", - "PublicDescription": "DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM Read CAS commands issued on this channel. This includes underfills.", - "UMask": "0xcf", + "UMask": "0x8", "Unit": "iMC" }, { - "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.", - "EventCode": "0x05", - "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG", + "BriefDescription": "Scoreboard Inserts : Reads", + "EventCode": "0xd6", + "EventName": "UNC_M_SB_INSERTS.RDS", "PerPkg": "1", - "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands", - "UMask": "0xc2", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.", - "EventCode": "0x05", - "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL", + "BriefDescription": "Scoreboard Inserts : Writes", + "EventCode": "0xd6", + "EventName": "UNC_M_SB_INSERTS.WRS", "PerPkg": "1", - "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands", - "UMask": "0xc8", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "All DRAM read CAS commands issued (does not include underfills)", - "EventCode": "0x05", - "EventName": "UNC_M_CAS_COUNT.RD_REG", + "BriefDescription": "Scoreboard Occupancy : Block region reads", + "EventCode": "0xd5", + "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_RDS", "PerPkg": "1", - "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/out auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the total number or DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with implicit Precharge. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).", - "UMask": "0xc1", + "UMask": "0x20", "Unit": "iMC" }, { - "BriefDescription": "DRAM underfill read CAS commands issued", - "EventCode": "0x05", - "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", + "BriefDescription": "Scoreboard Occupancy : Block region writes", + "EventCode": "0xd5", + "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_WRS", "PerPkg": "1", - "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : Underfill Read Issued : DRAM RD_CAS and WR_CAS Commands", - "UMask": "0xc4", + "UMask": "0x40", "Unit": "iMC" }, { - "BriefDescription": "All DRAM write CAS commands issued", - "EventCode": "0x05", - "EventName": "UNC_M_CAS_COUNT.WR", + "BriefDescription": "Scoreboard Occupancy : Persistent Mem reads", + "EventCode": "0xd5", + "EventName": "UNC_M_SB_OCCUPANCY.PMM_RDS", "PerPkg": "1", - "PublicDescription": "DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM Write CAS commands issued on this channel.", - "UMask": "0xf0", + "UMask": "0x4", "Unit": "iMC" }, { - "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre", - "EventCode": "0x05", - "EventName": "UNC_M_CAS_COUNT.WR_NONPRE", + "BriefDescription": "Scoreboard Occupancy : Persistent Mem writes", + "EventCode": "0xd5", + "EventName": "UNC_M_SB_OCCUPANCY.PMM_WRS", "PerPkg": "1", - "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre : DRAM RD_CAS and WR_CAS Commands", - "UMask": "0xd0", + "UMask": "0x8", "Unit": "iMC" }, { - "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.", - "EventCode": "0x05", - "EventName": "UNC_M_CAS_COUNT.WR_PRE", + "BriefDescription": "Scoreboard Occupancy : Reads", + "EventCode": "0xd5", + "EventName": "UNC_M_SB_OCCUPANCY.RDS", "PerPkg": "1", - "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands", - "UMask": "0xe0", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "IMC Clockticks at DCLK frequency", - "EventCode": "0x01", - "EventName": "UNC_M_CLOCKTICKS", + "BriefDescription": "Scoreboard Prefetch Inserts : All", + "EventCode": "0xda", + "EventName": "UNC_M_SB_PREF_INSERTS.ALL", "PerPkg": "1", - "PublicDescription": "Number of DRAM DCLK clock cycles while the event is enabled", "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "IMC Clockticks at HCLK frequency", - "EventCode": "0x01", - "EventName": "UNC_M_HCLOCKTICKS", + "BriefDescription": "Scoreboard Prefetch Inserts : DDR4", + "EventCode": "0xda", + "EventName": "UNC_M_SB_PREF_INSERTS.DDR", "PerPkg": "1", - "PublicDescription": "Number of DRAM HCLK clock cycles while the event is enabled", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "PMM Read Pending Queue inserts", - "EventCode": "0xe3", - "EventName": "UNC_M_PMM_RPQ_INSERTS", + "BriefDescription": "Scoreboard Prefetch Inserts : PMM", + "EventCode": "0xda", + "EventName": "UNC_M_SB_PREF_INSERTS.PMM", "PerPkg": "1", - "PublicDescription": "Counts number of read requests allocated in the PMM Read Pending Queue.", + "UMask": "0x4", "Unit": "iMC" }, { - "BriefDescription": "PMM Read Pending Queue occupancy", - "EventCode": "0xe0", - "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH0", + "BriefDescription": "Scoreboard Prefetch Occupancy : All", + "EventCode": "0xdb", + "EventName": "UNC_M_SB_PREF_OCCUPANCY.ALL", "PerPkg": "1", - "PublicDescription": "Accumulates the per cycle occupancy of the PMM Read Pending Queue.", "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "PMM Read Pending Queue occupancy", - "EventCode": "0xe0", - "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH1", + "BriefDescription": "Scoreboard Prefetch Occupancy : DDR4", + "EventCode": "0xdb", + "EventName": "UNC_M_SB_PREF_OCCUPANCY.DDR", "PerPkg": "1", - "PublicDescription": "Accumulates the per cycle occupancy of the PMM Read Pending Queue.", "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "PMM Read Pending Queue Occupancy", - "EventCode": "0xE0", - "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT_SCH0", + "BriefDescription": "Scoreboard Prefetch Occupancy : Persistent Mem", + "EventCode": "0xDB", + "EventName": "UNC_M_SB_PREF_OCCUPANCY.PMM", + "FCMask": "0x00000000", "PerPkg": "1", - "PublicDescription": "PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue.", - "UMask": "0x10", + "PortMask": "0x00000000", + "UMask": "0x4", "Unit": "iMC" }, { - "BriefDescription": "PMM Read Pending Queue Occupancy", - "EventCode": "0xE0", - "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT_SCH1", + "BriefDescription": "Number of Scoreboard Requests Rejected", + "EventCode": "0xd4", + "EventName": "UNC_M_SB_REJECT.CANARY", "PerPkg": "1", - "PublicDescription": "PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue.", - "UMask": "0x20", + "UMask": "0x8", "Unit": "iMC" }, { - "BriefDescription": "PMM Read Pending Queue Occupancy", - "EventCode": "0xe0", - "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT_SCH0", + "BriefDescription": "Number of Scoreboard Requests Rejected", + "EventCode": "0xd4", + "EventName": "UNC_M_SB_REJECT.DDR_EARLY_CMP", "PerPkg": "1", - "PublicDescription": "Accumulates the per cycle occupancy of the PMM Read Pending Queue.", - "UMask": "0x4", + "UMask": "0x20", "Unit": "iMC" }, { - "BriefDescription": "PMM Read Pending Queue Occupancy", - "EventCode": "0xe0", - "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT_SCH1", + "BriefDescription": "Number of Scoreboard Requests Rejected : FM requests rejected due to full address conflict", + "EventCode": "0xd4", + "EventName": "UNC_M_SB_REJECT.FM_ADDR_CNFLT", "PerPkg": "1", - "PublicDescription": "Accumulates the per cycle occupancy of the PMM Read Pending Queue.", - "UMask": "0x8", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "PMM Write Pending Queue inserts", - "EventCode": "0xe7", - "EventName": "UNC_M_PMM_WPQ_INSERTS", + "BriefDescription": "Number of Scoreboard Requests Rejected : NM requests rejected due to set conflict", + "EventCode": "0xd4", + "EventName": "UNC_M_SB_REJECT.NM_SET_CNFLT", "PerPkg": "1", - "PublicDescription": "Counts number of write requests allocated in the PMM Write Pending Queue.", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "PMM Write Pending Queue Occupancy", - "EventCode": "0xe4", - "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL", + "BriefDescription": "Number of Scoreboard Requests Rejected : Patrol requests rejected due to set conflict", + "EventCode": "0xd4", + "EventName": "UNC_M_SB_REJECT.PATROL_SET_CNFLT", "PerPkg": "1", - "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the Write Pending Queue to the PMM DIMM.", - "UMask": "0x3", + "UMask": "0x4", "Unit": "iMC" }, { - "BriefDescription": "PMM Write Pending Queue Occupancy", - "EventCode": "0xE4", - "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH0", + "BriefDescription": ": Far Mem Read - Set", + "EventCode": "0xd7", + "EventName": "UNC_M_SB_STRV_ALLOC.FM_RD", "PerPkg": "1", - "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue.", - "UMask": "0x1", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "PMM Write Pending Queue Occupancy", - "EventCode": "0xE4", - "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH1", + "BriefDescription": ": Near Mem Read - Clear", + "EventCode": "0xd7", + "EventName": "UNC_M_SB_STRV_ALLOC.FM_TGR", "PerPkg": "1", - "PublicDescription": "PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue.", - "UMask": "0x2", + "UMask": "0x10", "Unit": "iMC" }, { - "BriefDescription": "Channel PPD Cycles", - "EventCode": "0x85", - "EventName": "UNC_M_POWER_CHANNEL_PPD", + "BriefDescription": ": Far Mem Write - Set", + "EventCode": "0xd7", + "EventName": "UNC_M_SB_STRV_ALLOC.FM_WR", "PerPkg": "1", - "PublicDescription": "Channel PPD Cycles : Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.", + "UMask": "0x8", "Unit": "iMC" }, { - "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", - "EventCode": "0x47", - "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_0", + "BriefDescription": ": Near Mem Read - Set", + "EventCode": "0xd7", + "EventName": "UNC_M_SB_STRV_ALLOC.NM_RD", "PerPkg": "1", - "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).", "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", - "EventCode": "0x47", - "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_1", + "BriefDescription": ": Near Mem Write - Set", + "EventCode": "0xd7", + "EventName": "UNC_M_SB_STRV_ALLOC.NM_WR", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "iMC" + }, + { + "BriefDescription": ": Far Mem Read - Set", + "EventCode": "0xde", + "EventName": "UNC_M_SB_STRV_DEALLOC.FM_RD", "PerPkg": "1", - "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).", "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", - "EventCode": "0x47", - "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_2", + "BriefDescription": ": Near Mem Read - Clear", + "EventCode": "0xde", + "EventName": "UNC_M_SB_STRV_DEALLOC.FM_TGR", "PerPkg": "1", - "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).", - "UMask": "0x4", + "UMask": "0x10", "Unit": "iMC" }, { - "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", - "EventCode": "0x47", - "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_3", + "BriefDescription": ": Far Mem Write - Set", + "EventCode": "0xde", + "EventName": "UNC_M_SB_STRV_DEALLOC.FM_WR", "PerPkg": "1", - "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).", "UMask": "0x8", "Unit": "iMC" }, { - "BriefDescription": "Clock-Enabled Self-Refresh", - "EventCode": "0x43", - "EventName": "UNC_M_POWER_SELF_REFRESH", + "BriefDescription": ": Near Mem Read - Set", + "EventCode": "0xde", + "EventName": "UNC_M_SB_STRV_DEALLOC.NM_RD", "PerPkg": "1", - "PublicDescription": "Clock-Enabled Self-Refresh : Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "Precharge due to read, write, underfill, or PGT.", - "EventCode": "0x03", - "EventName": "UNC_M_PRE_COUNT.ALL", + "BriefDescription": ": Near Mem Write - Set", + "EventCode": "0xde", + "EventName": "UNC_M_SB_STRV_DEALLOC.NM_WR", "PerPkg": "1", - "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", - "UMask": "0xff", + "UMask": "0x4", "Unit": "iMC" }, { - "BriefDescription": "DRAM Precharge commands. : Precharge due to (?)", - "EventCode": "0x03", - "EventName": "UNC_M_PRE_COUNT.PGT", + "BriefDescription": ": Far Mem Read", + "EventCode": "0xd8", + "EventName": "UNC_M_SB_STRV_OCC.FM_RD", "PerPkg": "1", - "PublicDescription": "DRAM Precharge commands. : Precharge due to (?) : Counts the number of DRAM Precharge commands sent on this channel.", - "UMask": "0x88", + "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "DRAM Precharge commands. : Prechages from Page Table", - "EventCode": "0x03", - "EventName": "UNC_M_PRE_COUNT.PGT_PCH0", + "BriefDescription": ": Near Mem Read - Clear", + "EventCode": "0xd8", + "EventName": "UNC_M_SB_STRV_OCC.FM_TGR", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "iMC" + }, + { + "BriefDescription": ": Far Mem Write", + "EventCode": "0xd8", + "EventName": "UNC_M_SB_STRV_OCC.FM_WR", "PerPkg": "1", - "PublicDescription": "DRAM Precharge commands. : Prechages from Page Table : Counts the number of DRAM Precharge commands sent on this channel. : Equivalent to PAGE_EMPTY", "UMask": "0x8", "Unit": "iMC" }, { - "BriefDescription": "DRAM Precharge commands.", - "EventCode": "0x03", - "EventName": "UNC_M_PRE_COUNT.PGT_PCH1", + "BriefDescription": ": Near Mem Read", + "EventCode": "0xd8", + "EventName": "UNC_M_SB_STRV_OCC.NM_RD", "PerPkg": "1", - "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", - "UMask": "0x80", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "Precharge due to read on page miss", - "EventCode": "0x03", - "EventName": "UNC_M_PRE_COUNT.RD", + "BriefDescription": ": Near Mem Write", + "EventCode": "0xd8", + "EventName": "UNC_M_SB_STRV_OCC.NM_WR", "PerPkg": "1", - "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", - "UMask": "0x11", + "UMask": "0x4", "Unit": "iMC" }, { - "BriefDescription": "DRAM Precharge commands. : Precharge due to read", - "EventCode": "0x03", - "EventName": "UNC_M_PRE_COUNT.RD_PCH0", + "BriefDescription": "UNC_M_SB_TAGGED.DDR4_CMP", + "EventCode": "0xdd", + "EventName": "UNC_M_SB_TAGGED.DDR4_CMP", "PerPkg": "1", - "PublicDescription": "DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler", - "UMask": "0x1", + "UMask": "0x8", "Unit": "iMC" }, { - "BriefDescription": "DRAM Precharge commands.", - "EventCode": "0x03", - "EventName": "UNC_M_PRE_COUNT.RD_PCH1", + "BriefDescription": "UNC_M_SB_TAGGED.NEW", + "EventCode": "0xdd", + "EventName": "UNC_M_SB_TAGGED.NEW", "PerPkg": "1", - "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", - "UMask": "0x10", + "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "DRAM Precharge commands.", - "EventCode": "0x03", - "EventName": "UNC_M_PRE_COUNT.UFILL", + "BriefDescription": "UNC_M_SB_TAGGED.OCC", + "EventCode": "0xdd", + "EventName": "UNC_M_SB_TAGGED.OCC", "PerPkg": "1", - "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", - "UMask": "0x44", + "UMask": "0x80", "Unit": "iMC" }, { - "BriefDescription": "DRAM Precharge commands.", - "EventCode": "0x03", - "EventName": "UNC_M_PRE_COUNT.UFILL_PCH0", + "BriefDescription": "UNC_M_SB_TAGGED.PMM0_CMP", + "EventCode": "0xdd", + "EventName": "UNC_M_SB_TAGGED.PMM0_CMP", "PerPkg": "1", - "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", - "UMask": "0x4", + "UMask": "0x10", "Unit": "iMC" }, { - "BriefDescription": "DRAM Precharge commands.", - "EventCode": "0x03", - "EventName": "UNC_M_PRE_COUNT.UFILL_PCH1", + "BriefDescription": "UNC_M_SB_TAGGED.PMM1_CMP", + "EventCode": "0xdd", + "EventName": "UNC_M_SB_TAGGED.PMM1_CMP", "PerPkg": "1", - "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", - "UMask": "0x40", + "UMask": "0x20", "Unit": "iMC" }, { - "BriefDescription": "Precharge due to write on page miss", - "EventCode": "0x03", - "EventName": "UNC_M_PRE_COUNT.WR", + "BriefDescription": "UNC_M_SB_TAGGED.PMM2_CMP", + "EventCode": "0xdd", + "EventName": "UNC_M_SB_TAGGED.PMM2_CMP", "PerPkg": "1", - "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", - "UMask": "0x22", + "UMask": "0x40", "Unit": "iMC" }, { - "BriefDescription": "DRAM Precharge commands. : Precharge due to write", - "EventCode": "0x03", - "EventName": "UNC_M_PRE_COUNT.WR_PCH0", + "BriefDescription": "UNC_M_SB_TAGGED.RD_HIT", + "EventCode": "0xdd", + "EventName": "UNC_M_SB_TAGGED.RD_HIT", "PerPkg": "1", - "PublicDescription": "DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler", "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "DRAM Precharge commands.", - "EventCode": "0x03", - "EventName": "UNC_M_PRE_COUNT.WR_PCH1", + "BriefDescription": "UNC_M_SB_TAGGED.RD_MISS", + "EventCode": "0xdd", + "EventName": "UNC_M_SB_TAGGED.RD_MISS", "PerPkg": "1", - "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", - "UMask": "0x20", + "UMask": "0x4", "Unit": "iMC" }, { - "BriefDescription": "Read Pending Queue Allocations", - "EventCode": "0x10", - "EventName": "UNC_M_RPQ_INSERTS.PCH0", + "BriefDescription": "2LM Tag check hit in near memory cache (DDR4)", + "EventCode": "0xd3", + "EventName": "UNC_M_TAGCHK.HIT", "PerPkg": "1", - "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.", "UMask": "0x1", "Unit": "iMC" }, { - "BriefDescription": "Read Pending Queue Allocations", - "EventCode": "0x10", - "EventName": "UNC_M_RPQ_INSERTS.PCH1", + "BriefDescription": "2LM Tag check miss, no data at this line", + "EventCode": "0xd3", + "EventName": "UNC_M_TAGCHK.MISS_CLEAN", "PerPkg": "1", - "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.", "UMask": "0x2", "Unit": "iMC" }, { - "BriefDescription": "Read Pending Queue Occupancy", - "EventCode": "0x80", - "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0", + "BriefDescription": "2LM Tag check miss, existing data may be evicted to PMM", + "EventCode": "0xd3", + "EventName": "UNC_M_TAGCHK.MISS_DIRTY", "PerPkg": "1", - "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.", + "UMask": "0x4", "Unit": "iMC" }, { - "BriefDescription": "Read Pending Queue Occupancy", - "EventCode": "0x81", - "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1", + "BriefDescription": "2LM Tag check hit due to memory read (bug?)", + "EventCode": "0xd3", + "EventName": "UNC_M_TAGCHK.NM_RD_HIT", "PerPkg": "1", - "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.", + "UMask": "0x8", + "Unit": "iMC" + }, + { + "BriefDescription": "2LM Tag check hit due to memory write (bug?)", + "EventCode": "0xd3", + "EventName": "UNC_M_TAGCHK.NM_WR_HIT", + "PerPkg": "1", + "UMask": "0x10", "Unit": "iMC" }, { @@ -457,5 +3284,25 @@ "PerPkg": "1", "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.", "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "EventCode": "0x23", + "EventName": "UNC_M_WPQ_READ_HIT", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue CAM Match", + "EventCode": "0x24", + "EventName": "UNC_M_WPQ_WRITE_HIT", + "FCMask": "0x00000000", + "PerPkg": "1", + "PortMask": "0x00000000", + "PublicDescription": "Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.", + "Unit": "iMC" } ] diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-other.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-other.json deleted file mode 100644 index 11c037e8291d..000000000000 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-other.json +++ /dev/null @@ -1,4525 +0,0 @@ -[ - { - "BriefDescription": "CHA Clockticks", - "EventCode": "0x01", - "EventName": "UNC_CHA_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Number of CHA clock cycles while the event is enabled", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Clockticks", - "EventCode": "0xc0", - "EventName": "UNC_CHA_CMS_CLOCKTICKS", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed", - "EventCode": "0x53", - "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP", - "PerPkg": "1", - "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed", - "EventCode": "0x53", - "EventName": "UNC_CHA_DIR_LOOKUP.SNP", - "PerPkg": "1", - "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe", - "EventCode": "0x54", - "EventName": "UNC_CHA_DIR_UPDATE.HA", - "PerPkg": "1", - "PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe", - "EventCode": "0x54", - "EventName": "UNC_CHA_DIR_UPDATE.TOR", - "PerPkg": "1", - "PublicDescription": "Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions", - "UMask": "0x1bc1ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache and Snoop Filter Lookups; Snoop Requests from a Remote Socket", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.", - "UMask": "0x1c19ff", - "Unit": "CHA" - }, - { - "BriefDescription": "All LLC lines in E state that are victimized on a fill", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "All LLC lines in M state that are victimized on a fill", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "All LLC lines in S state that are victimized on a fill", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "OSB Snoop Broadcast : Local InvItoE", - "EventCode": "0x55", - "EventName": "UNC_CHA_OSB.LOCAL_INVITOE", - "PerPkg": "1", - "PublicDescription": "OSB Snoop Broadcast : Local InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "OSB Snoop Broadcast : Local Rd", - "EventCode": "0x55", - "EventName": "UNC_CHA_OSB.LOCAL_READ", - "PerPkg": "1", - "PublicDescription": "OSB Snoop Broadcast : Local Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Requests for exclusive ownership of a cache line without receiving data", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.INVITOE", - "PerPkg": "1", - "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", - "UMask": "0x30", - "Unit": "CHA" - }, - { - "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", - "PerPkg": "1", - "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Read requests made into the CHA", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.READS", - "PerPkg": "1", - "PublicDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) .", - "UMask": "0x3", - "Unit": "CHA" - }, - { - "BriefDescription": "Read requests from a unit on this socket", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", - "PerPkg": "1", - "PublicDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Read requests from a remote socket", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Write requests made into the CHA", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.WRITES", - "PerPkg": "1", - "PublicDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", - "UMask": "0xc", - "Unit": "CHA" - }, - { - "BriefDescription": "Write Requests from a unit on this socket", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", - "PerPkg": "1", - "PublicDescription": "Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Read and Write Requests; Writes Remote", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.ALL", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "UMask": "0xc001ffff", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DDR Access", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.DDR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DDR Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : SF/LLC Evictions", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.EVICT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : SF/LLC Evictions : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Just Hits", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.HIT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Just Hits : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; All from Local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests from IA Cores", - "UMask": "0xc001ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts;CLFlush from Local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; CLFlush events that are initiated from the Core", - "UMask": "0xc8c7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts;CLFlushOpt from Local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; CLFlushOpt events that are initiated from the Core", - "UMask": "0xc8d7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; CRd from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Code read from local IA that misses in the snoop filter", - "UMask": "0xc80fff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; CRd Pref from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter", - "UMask": "0xc88fff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; DRd from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", - "UMask": "0xc817ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc837ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; DRd Opt from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read opt from local IA that misses in the snoop filter", - "UMask": "0xc827ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; DRd Opt Pref from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read opt prefetch from local IA that misses in the snoop filter", - "UMask": "0xc8a7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; DRd Pref from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read prefetch from local IA that misses in the snoop filter", - "UMask": "0xc897ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; Hits from Local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "UMask": "0xc001fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; CRd hits from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Code read from local IA that hits in the snoop filter", - "UMask": "0xc80ffd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; CRd Pref hits from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Code read prefetch from local IA that hits in the snoop filter", - "UMask": "0xc88ffd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; DRd hits from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read from local IA that hits in the snoop filter", - "UMask": "0xc817fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to page walks that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc837fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; DRd Opt hits from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read opt from local IA that hits in the snoop filter", - "UMask": "0xc827fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; DRd Opt Pref hits from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read opt prefetch from local IA that hits in the snoop filter", - "UMask": "0xc8a7fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; DRd Pref hits from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read prefetch from local IA that hits in the snoop filter", - "UMask": "0xc897fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc47fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; LLCPrefCode hits from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Last level cache prefetch code read from local IA that hits in the snoop filter", - "UMask": "0xcccffd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; LLCPrefData hits from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Last level cache prefetch data read from local IA that hits in the snoop filter", - "UMask": "0xccd7fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; LLCPrefRFO hits from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Last level cache prefetch read for ownership from local IA that hits in the snoop filter", - "UMask": "0xccc7fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; RFO hits from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Read for ownership from local IA that hits in the snoop filter", - "UMask": "0xc807fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; RFO Pref hits from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that hits in the snoop filter", - "UMask": "0xc887fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts;ItoM from Local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; ItoM events that are initiated from the Core", - "UMask": "0xcc47ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcd47ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; LLCPrefCode from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Last level cache prefetch code read from local IA.", - "UMask": "0xcccfff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; LLCPrefData from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Last level cache prefetch data read from local IA.", - "UMask": "0xccd7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; LLCPrefRFO from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Last level cache prefetch read for ownership from local IA that misses in the snoop filter", - "UMask": "0xccc7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; misses from Local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts for CRd misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", - "PerPkg": "1", - "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode CRd", - "UMask": "0xc80ffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc80efe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; CRd Pref misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter", - "UMask": "0xc88ffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc88efe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc88f7e01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc80f7e01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts for DRd misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", - "PerPkg": "1", - "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd", - "UMask": "0xc817fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc837fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts for DRds issued by IA Cores targeting DDR Mem that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", - "PerPkg": "1", - "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target DDR memory", - "UMask": "0xc8178601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts for DRd misses from local IA targeting local memory", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", - "PerPkg": "1", - "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target local memory", - "UMask": "0xc816fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8168601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8168a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; DRd Opt misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read opt from local IA that misses in the snoop filter", - "UMask": "0xc827fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; DRd Opt Pref misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read opt prefetch from local IA that misses in the snoop filter", - "UMask": "0xc8a7fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts for DRds issued by iA Cores targeting PMM Mem that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM", - "PerPkg": "1", - "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target PMM memory", - "UMask": "0xc8178a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts for DRd Pref misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", - "PerPkg": "1", - "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF", - "UMask": "0xc897fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_DDR", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8978601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts for DRd Pref misses from local IA targeting local memory", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", - "PerPkg": "1", - "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target local memory", - "UMask": "0xc896fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_DDR", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8968601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_PMM", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8968a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_PMM", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8978a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts for DRd Pref misses from local IA targeting remote memory", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", - "PerPkg": "1", - "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target remote memory", - "UMask": "0xc8977e01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_DDR", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8970601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_PMM", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8970a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts for DRd misses from local IA targeting remote memory", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", - "PerPkg": "1", - "PublicDescription": "Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and target remote memory", - "UMask": "0xc8177e01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8170601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8170a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc47fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; LLCPrefCode misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Last level cache prefetch code read from local IA that misses in the snoop filter", - "UMask": "0xcccffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; LLCPrefData misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Last level cache prefetch data read from local IA that misses in the snoop filter", - "UMask": "0xccd7fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; LLCPrefRFO misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Last level cache prefetch read for ownership from local IA that misses in the snoop filter", - "UMask": "0xccc7fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8668601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_PMM", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8668a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86e8601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_PMM", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86e8a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8670601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_PMM", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8670a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86f0601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_PMM", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86f0a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; RFO misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Read for ownership from local IA that misses in the snoop filter", - "UMask": "0xc807fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts RFO misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Read for ownership from local IA that misses in the snoop filter", - "UMask": "0xc806fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; RFO pref misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter", - "UMask": "0xc887fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; RFO prefetch misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter", - "UMask": "0xc886fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; RFO prefetch misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter", - "UMask": "0xc8877e01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; RFO misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts Read for ownership from local IA that misses in the snoop filter", - "UMask": "0xc8077e01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc877de01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86ffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc867fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8678601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_PMM", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8678a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86f8601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_PMM", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86f8a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc87fde01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; RFO from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Read for ownership from local IA that misses in the snoop filter", - "UMask": "0xc807ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; RFO pref from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter", - "UMask": "0xc887ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts;SpecItoM from Local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; SpecItoM events that are initiated from the Core", - "UMask": "0xcc57ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE", - "PerPkg": "1", - "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc3fff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI", - "PerPkg": "1", - "PublicDescription": "WbMtoIs issued by iA Cores . (Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc27ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86fff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc867ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; All from local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8c3ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; Hits from local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; ItoM hits from local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc43fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcd43fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; RdCur and FsRdCur hits from local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8f3fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; RFO hits from local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc803fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts for ItoM from local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", - "PerPkg": "1", - "PublicDescription": "Inserts into the TOR from local IO with the opcode ItoM", - "UMask": "0xcc43ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts for ItoMCacheNears from IO devices.", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", - "PerPkg": "1", - "PublicDescription": "Inserts into the TOR from local IO devices with the opcode ItoMCacheNears. This event indicates a partial write request.", - "UMask": "0xcd43ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; Misses from local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; ItoM misses from local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc43fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcd43fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; RdCur and FsRdCur misses from local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8f3fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; RFO misses from local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc803fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts for RdCur from local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", - "PerPkg": "1", - "PublicDescription": "Inserts into the TOR from local IO with the opcode RdCur", - "UMask": "0xc8f3ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; RFO from local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc803ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc23ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : IPQ", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IPQ", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : IPQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : IRQ - iA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : IRQ - iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : From an iA Core", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : IRQ - Non iA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : IRQ - Non iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Just ISOC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.ISOC", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Just ISOC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Just Local Targets", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Just Local Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All from Local iA and IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All from Local iA and IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All locally initiated requests", - "UMask": "0xc000ff05", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All from Local iA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All from Local iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All locally initiated requests from iA Cores", - "UMask": "0xc000ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All from Local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All from Local IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All locally generated IO traffic", - "UMask": "0xc000ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Just Misses", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.MISS", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Just Misses : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : MMCFG Access", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.MMCFG", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : MMCFG Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : MMIO Access", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.MMIO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : MMIO Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Just NonCoherent", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.NONCOH", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Just NonCoherent : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : PMM Access", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.PMM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : PM Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : PRQ - IOSF", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : PRQ - IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : From a PCIe Device", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : PRQ - Non IOSF", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : PRQ - Non IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Just Remote Targets", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.REMOTE_TGT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Just Remote Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All from Remote", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All from Remote : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All remote requests (e.g. snoops, writebacks) that came from remote sockets", - "UMask": "0xc001ffc8", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All Snoops from Remote", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.REM_SNPS", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All Snoops from Remote : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. : All snoops to this LLC that came from remote sockets", - "UMask": "0xc001ff08", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RRQ", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.RRQ", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RRQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; All Snoops from Remote", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.SNPS_FROM_REM", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. All snoops to this LLC that came from remote sockets.", - "UMask": "0xc001ff08", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WBQ", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.WBQ", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WBQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "UMask": "0xc001ffff", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DDR Access", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DDR Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : SF/LLC Evictions", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : SF/LLC Evictions : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Just Hits", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Just Hits : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; All from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8c7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8d7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; CRd from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Code read from local IA that misses in the snoop filter", - "UMask": "0xc80fff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; CRd Pref from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter", - "UMask": "0xc88fff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; DRd from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", - "UMask": "0xc817ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; DRd Opt from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read opt from local IA that misses in the snoop filter", - "UMask": "0xc827ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; DRd Opt Pref from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read opt prefetch from local IA that misses in the snoop filter", - "UMask": "0xc8a7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; DRd Pref from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter", - "UMask": "0xc897ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; Hits from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; CRd hits from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Code read from local IA that hits in the snoop filter", - "UMask": "0xc80ffd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; CRd Pref hits from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that hits in the snoop filter", - "UMask": "0xc88ffd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; DRd hits from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read from local IA that hits in the snoop filter", - "UMask": "0xc817fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; DRd Opt hits from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read opt from local IA that hits in the snoop filter", - "UMask": "0xc827fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; DRd Opt Pref hits from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read opt prefetch from local IA that hits in the snoop filter", - "UMask": "0xc8a7fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; DRd Pref hits from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that hits in the snoop filter", - "UMask": "0xc897fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc47fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; LLCPrefCode hits from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Last level cache prefetch code read from local IA that hits in the snoop filter", - "UMask": "0xcccffd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; LLCPrefData hits from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Last level cache prefetch data read from local IA that hits in the snoop filter", - "UMask": "0xccd7fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; LLCPrefRFO hits from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Last level cache prefetch read for ownership from local IA that hits in the snoop filter", - "UMask": "0xccc7fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; RFO hits from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Read for ownership from local IA that hits in the snoop filter", - "UMask": "0xc807fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; RFO Pref hits from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that hits in the snoop filter", - "UMask": "0xc887fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc47ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcd47ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; LLCPrefCode from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Last level cache prefetch data read from local IA.", - "UMask": "0xcccfff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; LLCPrefData from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Last level cache prefetch data read from local IA that misses in the snoop filter", - "UMask": "0xccd7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; LLCPrefRFO from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Last level cache prefetch read for ownership from local IA that misses in the snoop filter", - "UMask": "0xccc7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; Misses from Local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; CRd misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Code read from local IA that misses in the snoop filter", - "UMask": "0xc80ffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc80efe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; CRd Pref misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter", - "UMask": "0xc88ffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc88efe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc88f7e01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc80f7e01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy for DRd misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", - "PerPkg": "1", - "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd", - "UMask": "0xc817fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy for DRds issued by iA Cores targeting DDR Mem that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", - "PerPkg": "1", - "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target DDR memory", - "UMask": "0xc8178601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy for DRd misses from local IA targeting local memory", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL", - "PerPkg": "1", - "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target local memory", - "UMask": "0xc816fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8168601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8168a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; DRd Opt misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read opt from local IA that misses in the snoop filter", - "UMask": "0xc827fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; DRd Opt Pref misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read opt prefetch from local IA that misses in the snoop filter", - "UMask": "0xc8a7fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy for DRds issued by iA Cores targeting PMM Mem that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM", - "PerPkg": "1", - "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target PMM memory", - "UMask": "0xc8178a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter", - "UMask": "0xc897fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8978601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter", - "UMask": "0xc896fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8968601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8968a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8978a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter", - "UMask": "0xc8977e01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8970601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8970a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy for DRd misses from local IA targeting remote memory", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE", - "PerPkg": "1", - "PublicDescription": "Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target remote memory", - "UMask": "0xc8177e01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8170601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8170a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc47fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; LLCPrefCode misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Last level cache prefetch code read from local IA that misses in the snoop filter", - "UMask": "0xcccffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; LLCPrefData misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Last level cache prefetch data read from local IA that misses in the snoop filter", - "UMask": "0xccd7fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; LLCPrefRFO misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Last level cache prefetch read for ownership from local IA that misses in the snoop filter", - "UMask": "0xccc7fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8668601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8668a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86e8601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86e8a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8670601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8670a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86f0601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86f0a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; RFO misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Read for ownership from local IA that misses in the snoop filter", - "UMask": "0xc807fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; RFO misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Read for ownership from local IA that misses in the snoop filter", - "UMask": "0xc806fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter", - "UMask": "0xc887fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter", - "UMask": "0xc886fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; RFO prefetch misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter", - "UMask": "0xc8877e01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; RFO misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Read for ownership from local IA that misses in the snoop filter", - "UMask": "0xc8077e01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc877de01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86ffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc867fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8678601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8678a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86f8601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86f8a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc87fde01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; RFO from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Read for ownership from local IA that misses in the snoop filter", - "UMask": "0xc807ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; RFO prefetch from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter", - "UMask": "0xc887ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc57ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc27ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86fff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc867ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; All from local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Devices", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8c3ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; Hits from local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; ITOM hits from local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc43fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcd43fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; RdCur and FsRdCur hits from local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8f3fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; RFO hits from local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc803fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; ITOM from local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc43ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; Misses from local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; ITOM misses from local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc43fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcd43fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; RdCur and FsRdCur misses from local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8f3fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; RFO misses from local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc803fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; RdCur and FsRdCur from local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8f3ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; ItoM from local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc803ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc23ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : IPQ", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : IPQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : IRQ - iA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : IRQ - iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : From an iA Core", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : IRQ - Non iA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : IRQ - Non iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Just ISOC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Just ISOC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Just Local Targets", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Just Local Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All from Local iA and IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All from Local iA and IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All locally initiated requests", - "UMask": "0xc000ff05", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All from Local iA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All from Local iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All locally initiated requests from iA Cores", - "UMask": "0xc000ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All from Local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All from Local IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All locally generated IO traffic", - "UMask": "0xc000ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Just Misses", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Just Misses : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : MMCFG Access", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : MMCFG Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : MMIO Access", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.MMIO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : MMIO Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Just NonCoherent", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Just NonCoherent : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : PMM Access", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : PMM Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : PRQ - IOSF", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : PRQ - IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : From a PCIe Device", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : PRQ - Non IOSF", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : PRQ - Non IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Just Remote Targets", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.REMOTE_TGT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Just Remote Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All from Remote", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.REM_ALL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All from Remote : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All remote requests (e.g. snoops, writebacks) that came from remote sockets", - "UMask": "0xc001ffc8", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All Snoops from Remote", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.REM_SNPS", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All Snoops from Remote : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T : All snoops to this LLC that came from remote sockets", - "UMask": "0xc001ff08", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RRQ", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.RRQ", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RRQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; All Snoops from Remote", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.SNPS_FROM_REM", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. All snoops to this LLC that came from remote sockets.", - "UMask": "0xc001ff08", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WBQ", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.WBQ", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WBQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "IIO Clockticks", - "EventCode": "0x01", - "EventName": "UNC_IIO_CLOCKTICKS", - "PerPkg": "1", - "PortMask": "0x0000", - "PublicDescription": "Number of IIO clock cycles while the event is enabled", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", - "FCMask": "0x04", - "PerPkg": "1", - "UMask": "0xff", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0100", - "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0200", - "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of 4 bytes made to IIO Part0 by the CPU", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0001", - "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of 4 bytes made to IIO Part1 by the CPU", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0002", - "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of 4 bytes made to IIO Part2 by the CPU", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0004", - "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of 4 bytes made to IIO Part3 by the CPU", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0008", - "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0010", - "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0020", - "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0040", - "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Cards MMIO space", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0080", - "PublicDescription": "Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0001", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0002", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0004", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0008", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0010", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0020", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0040", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0080", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for 4 bytes made by IIO Part0-7 to Memory", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x00ff", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for 4 bytes made by IIO Part0 to Memory", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0001", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for 4 bytes made by IIO Part1 to Memory", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0002", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for 4 bytes made by IIO Part2 to Memory", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0004", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for 4 bytes made by IIO Part3 to Memory", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0008", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card reading from DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0010", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card reading from DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0020", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card reading from DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0040", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card reading from DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0080", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of 4 bytes made by IIO Part0-7 to Memory", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x00ff", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of 4 bytes made by IIO Part0 to Memory", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0001", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of 4 bytes made by IIO Part1 to Memory", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0002", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of 4 bytes made by IIO Part2 to Memory", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0004", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of 4 bytes made by IIO Part3 to Memory", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0008", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0010", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0020", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0040", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0080", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0001", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0002", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0004", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0008", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0010", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0020", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0040", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0080", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": ": Context cache hits", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS", - "PerPkg": "1", - "PortMask": "0x0000", - "PublicDescription": ": Context cache hits : Counts each time a first look up of the transaction hits the RCC.", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": ": Context cache lookups", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS", - "PerPkg": "1", - "PortMask": "0x0000", - "PublicDescription": ": Context cache lookups : Counts each time a transaction looks up root context cache.", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": ": IOTLB lookups first", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS", - "PerPkg": "1", - "PortMask": "0x0000", - "PublicDescription": ": IOTLB lookups first : Some transactions have to look up IOTLB multiple times. Counts the first time a request looks up IOTLB.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "IOTLB Fills (same as IOTLB miss)", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.MISSES", - "PerPkg": "1", - "PortMask": "0x0000", - "PublicDescription": "IOTLB Fills (same as IOTLB miss) : When a transaction misses IOTLB, it does a page walk to look up memory and bring in the relevant page translation. Counts when this page translation is written to IOTLB.", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": ": IOMMU memory access", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES", - "PerPkg": "1", - "PublicDescription": ": IOMMU memory access : IOMMU sends out memory fetches when it misses the cache look up which is indicated by this signal. M2IOSF only uses low priority channel", - "UMask": "0xc0", - "Unit": "IIO" - }, - { - "BriefDescription": ": PWC Hit to a 2M page", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS", - "PerPkg": "1", - "PublicDescription": ": PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": ": PWT Hit to a 256T page", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.PWC_256T_HITS", - "PerPkg": "1", - "PublicDescription": ": PWT Hit to a 256T page : Counts each time a transaction's first look up hits the SLPWC at the 512G level", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": ": PWC Hit to a 4K page", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS", - "PerPkg": "1", - "PublicDescription": ": PWC Hit to a 4K page : Counts each time a transaction's first look up hits the SLPWC at the 4K level", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": ": PWC Hit to a 1G page", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS", - "PerPkg": "1", - "PublicDescription": ": PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": ": Global IOTLB invalidation cycles", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.PWT_OCCUPANCY_MSB", - "PerPkg": "1", - "PortMask": "0x0000", - "PublicDescription": ": Global IOTLB invalidation cycles : Indicates that IOMMU is doing global invalidation.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "PWT occupancy. Does not include 9th bit of occupancy (will undercount if PWT is greater than 255 per cycle).", - "EventCode": "0x42", - "EventName": "UNC_IIO_PWT_OCCUPANCY", - "PerPkg": "1", - "PortMask": "0x0000", - "PublicDescription": "PWT occupancy : Indicates how many page walks are outstanding at any point in time.", - "UMask": "0xff", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0001", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0002", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0004", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0008", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0010", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0020", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0040", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0080", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0001", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0002", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0004", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0008", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0010", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0020", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0040", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0080", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part0 to Memory", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0001", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part1 to Memory", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0002", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0004", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0008", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0010", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0020", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0040", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0080", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0001", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0002", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0004", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0008", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0010", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0020", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0040", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0080", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0001", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0002", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0004", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0008", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0010", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0020", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0040", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x0080", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "IRP Clockticks", - "EventCode": "0x01", - "EventName": "UNC_I_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Number of IRP clock cycles while the event is enabled", - "Unit": "IRP" - }, - { - "BriefDescription": "FAF - request insert from TC.", - "EventCode": "0x18", - "EventName": "UNC_I_FAF_INSERTS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "FAF occupancy", - "EventCode": "0x19", - "EventName": "UNC_I_FAF_OCCUPANCY", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "FAF allocation -- sent to ADQ", - "EventCode": "0x16", - "EventName": "UNC_I_FAF_TRANSACTIONS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)", - "EventCode": "0x20", - "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1 : Lost Forward", - "EventCode": "0x1f", - "EventName": "UNC_I_MISC1.LOST_FWD", - "PerPkg": "1", - "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound write (fast path) requests received by the IRP.", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.WR_PREF", - "PerPkg": "1", - "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "M2M Clockticks", - "EventCode": "0x01", - "EventName": "UNC_M2M_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Clockticks of the mesh to memory (M2M)", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled", - "EventCode": "0x17", - "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", - "PerPkg": "1", - "UMask": "0x7", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages sent direct to core (bypassing the CHA)", - "EventCode": "0x16", - "EventName": "UNC_M2M_DIRECT2CORE_TAKEN", - "PerPkg": "1", - "UMask": "0x7", - "Unit": "M2M" - }, - { - "BriefDescription": "Number of reads in which direct to core transaction were overridden", - "EventCode": "0x18", - "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden", - "EventCode": "0x1b", - "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS", - "PerPkg": "1", - "UMask": "0x7", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles when direct to Intel UPI was disabled", - "EventCode": "0x1a", - "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE", - "PerPkg": "1", - "UMask": "0x7", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages sent direct to the Intel UPI", - "EventCode": "0x19", - "EventName": "UNC_M2M_DIRECT2UPI_TAKEN", - "PerPkg": "1", - "UMask": "0x7", - "Unit": "M2M" - }, - { - "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden", - "EventCode": "0x1c", - "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)", - "EventCode": "0x20", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)", - "EventCode": "0x20", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)", - "EventCode": "0x20", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)", - "EventCode": "0x20", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory update from A to I", - "EventCode": "0x21", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I", - "PerPkg": "1", - "UMask": "0x320", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory update from A to S", - "EventCode": "0x21", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S", - "PerPkg": "1", - "UMask": "0x340", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory update from/to Any state", - "EventCode": "0x21", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", - "PerPkg": "1", - "UMask": "0x301", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory update from I to A", - "EventCode": "0x21", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A", - "PerPkg": "1", - "UMask": "0x304", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory update from I to S", - "EventCode": "0x21", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S", - "PerPkg": "1", - "UMask": "0x302", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory update from S to A", - "EventCode": "0x21", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A", - "PerPkg": "1", - "UMask": "0x310", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory update from S to I", - "EventCode": "0x21", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I", - "PerPkg": "1", - "UMask": "0x308", - "Unit": "M2M" - }, - { - "BriefDescription": "UNC_M2M_IMC_READS.TO_PMM", - "EventCode": "0x24", - "EventName": "UNC_M2M_IMC_READS.TO_PMM", - "PerPkg": "1", - "UMask": "0x320", - "Unit": "M2M" - }, - { - "BriefDescription": "PMM - All Channels", - "EventCode": "0x25", - "EventName": "UNC_M2M_IMC_WRITES.TO_PMM", - "PerPkg": "1", - "UMask": "0x1880", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped", - "EventCode": "0x58", - "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_UPI", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped", - "EventCode": "0x58", - "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped", - "EventCode": "0x58", - "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_UPI", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped", - "EventCode": "0x58", - "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped", - "EventCode": "0x58", - "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH", - "PerPkg": "1", - "UMask": "0x5", - "Unit": "M2M" - }, - { - "BriefDescription": ": UPI - All Channels", - "EventCode": "0x5d", - "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.UPI_ALLCH", - "PerPkg": "1", - "UMask": "0xa", - "Unit": "M2M" - }, - { - "BriefDescription": ": XPT - All Channels", - "EventCode": "0x5d", - "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPT_ALLCH", - "PerPkg": "1", - "UMask": "0x5", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels", - "EventCode": "0x56", - "EventName": "UNC_M2M_PREFCAM_INSERTS.UPI_ALLCH", - "PerPkg": "1", - "UMask": "0xa", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels", - "EventCode": "0x56", - "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH", - "PerPkg": "1", - "PublicDescription": "Prefetch CAM Inserts : XPT -All Channels", - "UMask": "0x5", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Ingress (from CMS) : AD Ingress (from CMS) Allocations", - "EventCode": "0x02", - "EventName": "UNC_M2M_RxC_AD_INSERTS", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Ingress (from CMS) Occupancy", - "EventCode": "0x03", - "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Inserts : Channel 0", - "EventCode": "0x32", - "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", - "PerPkg": "1", - "UMask": "0x104", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Inserts : Channel 1", - "EventCode": "0x32", - "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", - "PerPkg": "1", - "UMask": "0x204", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Occupancy : Channel 0", - "EventCode": "0x33", - "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Occupancy : Channel 1", - "EventCode": "0x33", - "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2P Clockticks", - "EventCode": "0x01", - "EventName": "UNC_M2P_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Number of M2P clock cycles while the event is enabled", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Clockticks", - "EventCode": "0xc0", - "EventName": "UNC_M2P_CMS_CLOCKTICKS", - "PerPkg": "1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M3UPI Clockticks", - "EventCode": "0x01", - "EventName": "UNC_M3UPI_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Number of M2UPI clock cycles while the event is enabled", - "Unit": "M3UPI" - }, - { - "BriefDescription": "M3UPI CMS Clockticks", - "EventCode": "0xc0", - "EventName": "UNC_M3UPI_CMS_CLOCKTICKS", - "PerPkg": "1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "D2C Sent", - "EventCode": "0x2b", - "EventName": "UNC_M3UPI_D2C_SENT", - "PerPkg": "1", - "PublicDescription": "D2C Sent : Count cases BL sends direct to core", - "Unit": "M3UPI" - }, - { - "BriefDescription": "D2U Sent", - "EventCode": "0x2a", - "EventName": "UNC_M3UPI_D2U_SENT", - "PerPkg": "1", - "PublicDescription": "D2U Sent : Cases where SMI3 sends D2U command", - "Unit": "M3UPI" - }, - { - "BriefDescription": "FlowQ Generated Prefetch", - "EventCode": "0x29", - "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN", - "PerPkg": "1", - "PublicDescription": "FlowQ Generated Prefetch : Count cases where FlowQ causes spawn of Prefetch to iMC/SMI3 target", - "Unit": "M3UPI" - }, - { - "BriefDescription": "All CAS commands issued", - "EventCode": "0x05", - "EventName": "UNC_MCHBM_CAS_COUNT.ALL", - "PerPkg": "1", - "UMask": "0xff", - "Unit": "MCHBM" - }, - { - "BriefDescription": "Read CAS commands issued (regular and underfill)", - "EventCode": "0x05", - "EventName": "UNC_MCHBM_CAS_COUNT.RD", - "PerPkg": "1", - "UMask": "0xcf", - "Unit": "MCHBM" - }, - { - "BriefDescription": "Regular read CAS commands issued (does not include underfills)", - "EventCode": "0x05", - "EventName": "UNC_MCHBM_CAS_COUNT.RD_REG", - "PerPkg": "1", - "UMask": "0xc1", - "Unit": "MCHBM" - }, - { - "BriefDescription": "Underfill read CAS commands issued", - "EventCode": "0x05", - "EventName": "UNC_MCHBM_CAS_COUNT.RD_UNDERFILL", - "PerPkg": "1", - "UMask": "0xc4", - "Unit": "MCHBM" - }, - { - "BriefDescription": "Write CAS commands issued", - "EventCode": "0x05", - "EventName": "UNC_MCHBM_CAS_COUNT.WR", - "PerPkg": "1", - "UMask": "0xf0", - "Unit": "MCHBM" - }, - { - "BriefDescription": "UPI Clockticks", - "EventCode": "0x01", - "EventName": "UNC_UPI_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Number of UPI LL clock cycles while the event is enabled", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Direct packet attempts : D2C", - "EventCode": "0x12", - "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C", - "PerPkg": "1", - "PublicDescription": "Direct packet attempts : D2C : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Cycles in L1", - "EventCode": "0x21", - "EventName": "UNC_UPI_L1_POWER_CYCLES", - "PerPkg": "1", - "PublicDescription": "Cycles in L1 : Number of UPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a UPI link. Use edge detect to count the number of instances when the UPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass", - "EventCode": "0x05", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", - "PerPkg": "1", - "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0xe", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode", - "EventCode": "0x05", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC", - "PerPkg": "1", - "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x10e", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard", - "EventCode": "0x05", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", - "PerPkg": "1", - "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0xf", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode", - "EventCode": "0x05", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC", - "PerPkg": "1", - "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x10f", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 0", - "EventCode": "0x31", - "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", - "PerPkg": "1", - "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 0 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 1", - "EventCode": "0x31", - "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", - "PerPkg": "1", - "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 1 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 2", - "EventCode": "0x31", - "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", - "PerPkg": "1", - "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 2 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received : All Data", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", - "PerPkg": "1", - "PublicDescription": "Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c).", - "UMask": "0xf", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Null FLITs received from any slot", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", - "PerPkg": "1", - "UMask": "0x27", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received : Data", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.DATA", - "PerPkg": "1", - "PublicDescription": "Valid Flits Received : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received : Idle", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.IDLE", - "PerPkg": "1", - "PublicDescription": "Valid Flits Received : Idle : Shows legal flit time (hides impact of L0p and L0c).", - "UMask": "0x47", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received : LLCRD Not Empty", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.LLCRD", - "PerPkg": "1", - "PublicDescription": "Valid Flits Received : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2", - "UMask": "0x10", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received : LLCTRL", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.LLCTRL", - "PerPkg": "1", - "PublicDescription": "Valid Flits Received : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.", - "UMask": "0x40", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received : All Non Data", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", - "PerPkg": "1", - "PublicDescription": "Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c).", - "UMask": "0x97", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Empty", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.NULL", - "PerPkg": "1", - "PublicDescription": "Valid Flits Received : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.", - "UMask": "0x20", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received : Protocol Header", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.PROTHDR", - "PerPkg": "1", - "PublicDescription": "Valid Flits Received : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)", - "UMask": "0x80", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received : Slot 0", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.SLOT0", - "PerPkg": "1", - "PublicDescription": "Valid Flits Received : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received : Slot 1", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.SLOT1", - "PerPkg": "1", - "PublicDescription": "Valid Flits Received : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received : Slot 2", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.SLOT2", - "PerPkg": "1", - "PublicDescription": "Valid Flits Received : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Flit Buffer Allocations : Slot 0", - "EventCode": "0x30", - "EventName": "UNC_UPI_RxL_INSERTS.SLOT0", - "PerPkg": "1", - "PublicDescription": "RxQ Flit Buffer Allocations : Slot 0 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Flit Buffer Allocations : Slot 1", - "EventCode": "0x30", - "EventName": "UNC_UPI_RxL_INSERTS.SLOT1", - "PerPkg": "1", - "PublicDescription": "RxQ Flit Buffer Allocations : Slot 1 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Flit Buffer Allocations : Slot 2", - "EventCode": "0x30", - "EventName": "UNC_UPI_RxL_INSERTS.SLOT2", - "PerPkg": "1", - "PublicDescription": "RxQ Flit Buffer Allocations : Slot 2 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Occupancy - All Packets : Slot 0", - "EventCode": "0x32", - "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0", - "PerPkg": "1", - "PublicDescription": "RxQ Occupancy - All Packets : Slot 0 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Occupancy - All Packets : Slot 1", - "EventCode": "0x32", - "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1", - "PerPkg": "1", - "PublicDescription": "RxQ Occupancy - All Packets : Slot 1 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Occupancy - All Packets : Slot 2", - "EventCode": "0x32", - "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2", - "PerPkg": "1", - "PublicDescription": "RxQ Occupancy - All Packets : Slot 2 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Cycles in L0p", - "EventCode": "0x27", - "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", - "PerPkg": "1", - "PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass", - "EventCode": "0x04", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", - "PerPkg": "1", - "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0xe", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode", - "EventCode": "0x04", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC", - "PerPkg": "1", - "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x10e", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard", - "EventCode": "0x04", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", - "PerPkg": "1", - "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0xf", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode", - "EventCode": "0x04", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC", - "PerPkg": "1", - "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x10f", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Tx Flit Buffer Bypassed", - "EventCode": "0x41", - "EventName": "UNC_UPI_TxL_BYPASSED", - "PerPkg": "1", - "PublicDescription": "Tx Flit Buffer Bypassed : Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the UPI Link. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent : All Data", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", - "PerPkg": "1", - "PublicDescription": "Valid Flits Sent : All Data : Counts number of data flits across this UPI link.", - "UMask": "0xf", - "Unit": "UPI LL" - }, - { - "BriefDescription": "All Null Flits", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", - "PerPkg": "1", - "UMask": "0x27", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent : Data", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.DATA", - "PerPkg": "1", - "PublicDescription": "Valid Flits Sent : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent : Idle", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.IDLE", - "PerPkg": "1", - "PublicDescription": "Valid Flits Sent : Idle : Shows legal flit time (hides impact of L0p and L0c).", - "UMask": "0x47", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent : LLCRD Not Empty", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.LLCRD", - "PerPkg": "1", - "PublicDescription": "Valid Flits Sent : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2", - "UMask": "0x10", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent : LLCTRL", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.LLCTRL", - "PerPkg": "1", - "PublicDescription": "Valid Flits Sent : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.", - "UMask": "0x40", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent : All Non Data", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", - "PerPkg": "1", - "PublicDescription": "Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c).", - "UMask": "0x97", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.NULL", - "PerPkg": "1", - "PublicDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.", - "UMask": "0x20", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent : Protocol Header", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.PROTHDR", - "PerPkg": "1", - "PublicDescription": "Valid Flits Sent : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)", - "UMask": "0x80", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent : Slot 0", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.SLOT0", - "PerPkg": "1", - "PublicDescription": "Valid Flits Sent : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent : Slot 1", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.SLOT1", - "PerPkg": "1", - "PublicDescription": "Valid Flits Sent : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent : Slot 2", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.SLOT2", - "PerPkg": "1", - "PublicDescription": "Valid Flits Sent : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Tx Flit Buffer Allocations", - "EventCode": "0x40", - "EventName": "UNC_UPI_TxL_INSERTS", - "PerPkg": "1", - "PublicDescription": "Tx Flit Buffer Allocations : Number of allocations into the UPI Tx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Tx Flit Buffer Occupancy", - "EventCode": "0x42", - "EventName": "UNC_UPI_TxL_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Tx Flit Buffer Occupancy : Accumulates the number of flits in the TxQ. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.", - "Unit": "UPI LL" - } -] diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-power.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-power.json index b1d5a605e0a7..8948e85074f0 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-power.json @@ -7,6 +7,66 @@ "PublicDescription": "Number of PCU PCLK Clock cycles while the event is enabled", "Unit": "PCU" }, + { + "BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES", + "EventCode": "0x60", + "EventName": "UNC_P_CORE_TRANSITION_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "UNC_P_DEMOTIONS", + "EventCode": "0x30", + "EventName": "UNC_P_DEMOTIONS", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "Phase Shed 0 Cycles", + "EventCode": "0x75", + "EventName": "UNC_P_FIVR_PS_PS0_CYCLES", + "PerPkg": "1", + "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-shedding power state 0", + "Unit": "PCU" + }, + { + "BriefDescription": "Phase Shed 1 Cycles", + "EventCode": "0x76", + "EventName": "UNC_P_FIVR_PS_PS1_CYCLES", + "PerPkg": "1", + "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-shedding power state 1", + "Unit": "PCU" + }, + { + "BriefDescription": "Phase Shed 2 Cycles", + "EventCode": "0x77", + "EventName": "UNC_P_FIVR_PS_PS2_CYCLES", + "PerPkg": "1", + "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-shedding power state 2", + "Unit": "PCU" + }, + { + "BriefDescription": "Phase Shed 3 Cycles", + "EventCode": "0x78", + "EventName": "UNC_P_FIVR_PS_PS3_CYCLES", + "PerPkg": "1", + "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-shedding power state 3", + "Unit": "PCU" + }, + { + "BriefDescription": "AVX256 Frequency Clipping", + "EventCode": "0x49", + "EventName": "UNC_P_FREQ_CLIP_AVX256", + "PerPkg": "1", + "Unit": "PCU" + }, + { + "BriefDescription": "AVX512 Frequency Clipping", + "EventCode": "0x4a", + "EventName": "UNC_P_FREQ_CLIP_AVX512", + "PerPkg": "1", + "Unit": "PCU" + }, { "BriefDescription": "Thermal Strongest Upper Limit Cycles", "EventCode": "0x04", @@ -23,6 +83,14 @@ "PublicDescription": "Power Strongest Upper Limit Cycles : Counts the number of cycles when power is the upper limit on frequency.", "Unit": "PCU" }, + { + "BriefDescription": "IO P Limit Strongest Lower Limit Cycles", + "EventCode": "0x73", + "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", + "PerPkg": "1", + "PublicDescription": "IO P Limit Strongest Lower Limit Cycles : Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.", + "Unit": "PCU" + }, { "BriefDescription": "Cycles spent changing Frequency", "EventCode": "0x74", @@ -31,6 +99,22 @@ "PublicDescription": "Cycles spent changing Frequency : Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.", "Unit": "PCU" }, + { + "BriefDescription": "Memory Phase Shedding Cycles", + "EventCode": "0x2f", + "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", + "PerPkg": "1", + "PublicDescription": "Memory Phase Shedding Cycles : Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.", + "Unit": "PCU" + }, + { + "BriefDescription": "Package C State Residency - C0", + "EventCode": "0x2a", + "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES", + "PerPkg": "1", + "PublicDescription": "Package C State Residency - C0 : Counts the number of cycles when the package was in C0. This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert). Residency events do not include transition times.", + "Unit": "PCU" + }, { "BriefDescription": "Package C State Residency - C2E", "EventCode": "0x2b", @@ -47,6 +131,13 @@ "PublicDescription": "Package C State Residency - C6 : Counts the number of cycles when the package was in C6. This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert). Residency events do not include transition times.", "Unit": "PCU" }, + { + "BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES", + "EventCode": "0x06", + "EventName": "UNC_P_PMAX_THROTTLED_CYCLES", + "PerPkg": "1", + "Unit": "PCU" + }, { "BriefDescription": "Number of cores in C0", "EventCode": "0x35", @@ -86,5 +177,21 @@ "PerPkg": "1", "PublicDescription": "Internal Prochot : Counts the number of cycles that we are in Internal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.", "Unit": "PCU" + }, + { + "BriefDescription": "Total Core C State Transition Cycles", + "EventCode": "0x72", + "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", + "PerPkg": "1", + "PublicDescription": "Total Core C State Transition Cycles : Number of cycles spent performing core C state transitions across all cores.", + "Unit": "PCU" + }, + { + "BriefDescription": "VR Hot", + "EventCode": "0x42", + "EventName": "UNC_P_VR_HOT_CYCLES", + "PerPkg": "1", + "PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR is hot. Does not cover DRAM VRs", + "Unit": "PCU" } ] -- cgit v1.2.3-58-ga151 From dbe9d887d3015a95c8d10dd47ce3e241a5167772 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 13 Apr 2023 06:29:30 -0700 Subject: perf vendor events intel: Add grandridge Add v1.00 from: https://github.com/intel/perfmon/pull/69 Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230413132949.3487664-3-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../perf/pmu-events/arch/x86/grandridge/cache.json | 155 +++++++++++++++++++++ .../pmu-events/arch/x86/grandridge/frontend.json | 16 +++ .../pmu-events/arch/x86/grandridge/memory.json | 20 +++ .../perf/pmu-events/arch/x86/grandridge/other.json | 20 +++ .../pmu-events/arch/x86/grandridge/pipeline.json | 96 +++++++++++++ .../arch/x86/grandridge/virtual-memory.json | 24 ++++ tools/perf/pmu-events/arch/x86/mapfile.csv | 1 + 7 files changed, 332 insertions(+) create mode 100644 tools/perf/pmu-events/arch/x86/grandridge/cache.json create mode 100644 tools/perf/pmu-events/arch/x86/grandridge/frontend.json create mode 100644 tools/perf/pmu-events/arch/x86/grandridge/memory.json create mode 100644 tools/perf/pmu-events/arch/x86/grandridge/other.json create mode 100644 tools/perf/pmu-events/arch/x86/grandridge/pipeline.json create mode 100644 tools/perf/pmu-events/arch/x86/grandridge/virtual-memory.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/grandridge/cache.json b/tools/perf/pmu-events/arch/x86/grandridge/cache.json new file mode 100644 index 000000000000..7f0dc65a55d2 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/grandridge/cache.json @@ -0,0 +1,155 @@ +[ + { + "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.", + "EventCode": "0x2e", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", + "SampleAfterValue": "200003", + "UMask": "0x41" + }, + { + "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.", + "EventCode": "0x2e", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", + "SampleAfterValue": "200003", + "UMask": "0x4f" + }, + { + "BriefDescription": "Counts the number of load ops retired.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "1", + "SampleAfterValue": "200003", + "UMask": "0x81" + }, + { + "BriefDescription": "Counts the number of store ops retired.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PEBS": "1", + "SampleAfterValue": "200003", + "UMask": "0x82" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024", + "MSRIndex": "0x3F6", + "MSRValue": "0x400", + "PEBS": "2", + "SampleAfterValue": "1000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "SampleAfterValue": "1000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "SampleAfterValue": "1000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048", + "MSRIndex": "0x3F6", + "MSRValue": "0x800", + "PEBS": "2", + "SampleAfterValue": "1000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "SampleAfterValue": "1000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "SampleAfterValue": "1000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "SampleAfterValue": "1000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "SampleAfterValue": "1000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "SampleAfterValue": "1000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "SampleAfterValue": "1000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", + "PEBS": "2", + "SampleAfterValue": "1000003", + "UMask": "0x6" + } +] diff --git a/tools/perf/pmu-events/arch/x86/grandridge/frontend.json b/tools/perf/pmu-events/arch/x86/grandridge/frontend.json new file mode 100644 index 000000000000..be8f1c7e195c --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/grandridge/frontend.json @@ -0,0 +1,16 @@ +[ + { + "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.", + "EventCode": "0x80", + "EventName": "ICACHE.ACCESSES", + "SampleAfterValue": "200003", + "UMask": "0x3" + }, + { + "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "SampleAfterValue": "200003", + "UMask": "0x2" + } +] diff --git a/tools/perf/pmu-events/arch/x86/grandridge/memory.json b/tools/perf/pmu-events/arch/x86/grandridge/memory.json new file mode 100644 index 000000000000..79d8af45100c --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/grandridge/memory.json @@ -0,0 +1,20 @@ +[ + { + "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_RFO.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00002", + "SampleAfterValue": "100003", + "UMask": "0x1" + } +] diff --git a/tools/perf/pmu-events/arch/x86/grandridge/other.json b/tools/perf/pmu-events/arch/x86/grandridge/other.json new file mode 100644 index 000000000000..2414f6ff53b0 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/grandridge/other.json @@ -0,0 +1,20 @@ +[ + { + "BriefDescription": "Counts demand data reads that have any type of response.", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10002", + "SampleAfterValue": "100003", + "UMask": "0x1" + } +] diff --git a/tools/perf/pmu-events/arch/x86/grandridge/pipeline.json b/tools/perf/pmu-events/arch/x86/grandridge/pipeline.json new file mode 100644 index 000000000000..41212957ef21 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/grandridge/pipeline.json @@ -0,0 +1,96 @@ +[ + { + "BriefDescription": "Counts the total number of branch instructions retired for all branch types.", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", + "EventName": "CPU_CLK_UNHALTED.CORE", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.THREAD_P]", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.CORE_P", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", + "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.CORE_P]", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Fixed Counter: Counts the number of instructions retired", + "EventName": "INST_RETIRED.ANY", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of instructions retired", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.ANY_P", + "PEBS": "1", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.ALL", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", + "SampleAfterValue": "1000003" + }, + { + "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.ALL", + "SampleAfterValue": "1000003" + }, + { + "BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.ALL", + "SampleAfterValue": "1000003" + }, + { + "BriefDescription": "Counts the number of consumed retirement slots. Similar to UOPS_RETIRED.ALL", + "EventCode": "0x72", + "EventName": "TOPDOWN_RETIRING.ALL", + "PEBS": "1", + "SampleAfterValue": "1000003" + } +] diff --git a/tools/perf/pmu-events/arch/x86/grandridge/virtual-memory.json b/tools/perf/pmu-events/arch/x86/grandridge/virtual-memory.json new file mode 100644 index 000000000000..bd5f2b634c98 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/grandridge/virtual-memory.json @@ -0,0 +1,24 @@ +[ + { + "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G page.", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "SampleAfterValue": "1000003", + "UMask": "0xe" + }, + { + "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G page.", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "SampleAfterValue": "1000003", + "UMask": "0xe" + }, + { + "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.", + "SampleAfterValue": "200003", + "UMask": "0xe" + } +] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 437eeecfaf64..c2b83cbae225 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -9,6 +9,7 @@ GenuineIntel-6-55-[56789ABCDEF],v1.17,cascadelakex,core GenuineIntel-6-9[6C],v1.03,elkhartlake,core GenuineIntel-6-5[CF],v13,goldmont,core GenuineIntel-6-7A,v1.01,goldmontplus,core +GenuineIntel-6-B6,v1.00,grandridge,core GenuineIntel-6-A[DE],v1.01,graniterapids,core GenuineIntel-6-(3C|45|46),v33,haswell,core GenuineIntel-6-3F,v27,haswellx,core -- cgit v1.2.3-58-ga151 From 98806c08f995e850f4427e30852a7012f4f1c869 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 13 Apr 2023 06:29:31 -0700 Subject: perf vendor events intel: Add sierraforest Add v1.00 from: https://github.com/intel/perfmon/pull/69 Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230413132949.3487664-4-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/x86/mapfile.csv | 1 + .../pmu-events/arch/x86/sierraforest/cache.json | 155 +++++++++++++++++++++ .../pmu-events/arch/x86/sierraforest/frontend.json | 16 +++ .../pmu-events/arch/x86/sierraforest/memory.json | 20 +++ .../pmu-events/arch/x86/sierraforest/other.json | 20 +++ .../pmu-events/arch/x86/sierraforest/pipeline.json | 96 +++++++++++++ .../arch/x86/sierraforest/virtual-memory.json | 24 ++++ 7 files changed, 332 insertions(+) create mode 100644 tools/perf/pmu-events/arch/x86/sierraforest/cache.json create mode 100644 tools/perf/pmu-events/arch/x86/sierraforest/frontend.json create mode 100644 tools/perf/pmu-events/arch/x86/sierraforest/memory.json create mode 100644 tools/perf/pmu-events/arch/x86/sierraforest/other.json create mode 100644 tools/perf/pmu-events/arch/x86/sierraforest/pipeline.json create mode 100644 tools/perf/pmu-events/arch/x86/sierraforest/virtual-memory.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index c2b83cbae225..66c37a3cbf43 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -24,6 +24,7 @@ GenuineIntel-6-1[AEF],v3,nehalemep,core GenuineIntel-6-2E,v3,nehalemex,core GenuineIntel-6-2A,v19,sandybridge,core GenuineIntel-6-(8F|CF),v1.12,sapphirerapids,core +GenuineIntel-6-AF,v1.00,sierraforest,core GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v55,skylake,core GenuineIntel-6-55-[01234],v1.29,skylakex,core diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/cache.json b/tools/perf/pmu-events/arch/x86/sierraforest/cache.json new file mode 100644 index 000000000000..7f0dc65a55d2 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sierraforest/cache.json @@ -0,0 +1,155 @@ +[ + { + "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.", + "EventCode": "0x2e", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", + "SampleAfterValue": "200003", + "UMask": "0x41" + }, + { + "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.", + "EventCode": "0x2e", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", + "SampleAfterValue": "200003", + "UMask": "0x4f" + }, + { + "BriefDescription": "Counts the number of load ops retired.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "1", + "SampleAfterValue": "200003", + "UMask": "0x81" + }, + { + "BriefDescription": "Counts the number of store ops retired.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PEBS": "1", + "SampleAfterValue": "200003", + "UMask": "0x82" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024", + "MSRIndex": "0x3F6", + "MSRValue": "0x400", + "PEBS": "2", + "SampleAfterValue": "1000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "SampleAfterValue": "1000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "SampleAfterValue": "1000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048", + "MSRIndex": "0x3F6", + "MSRValue": "0x800", + "PEBS": "2", + "SampleAfterValue": "1000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "SampleAfterValue": "1000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "SampleAfterValue": "1000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "SampleAfterValue": "1000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "SampleAfterValue": "1000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "SampleAfterValue": "1000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "SampleAfterValue": "1000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", + "PEBS": "2", + "SampleAfterValue": "1000003", + "UMask": "0x6" + } +] diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/frontend.json b/tools/perf/pmu-events/arch/x86/sierraforest/frontend.json new file mode 100644 index 000000000000..be8f1c7e195c --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sierraforest/frontend.json @@ -0,0 +1,16 @@ +[ + { + "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.", + "EventCode": "0x80", + "EventName": "ICACHE.ACCESSES", + "SampleAfterValue": "200003", + "UMask": "0x3" + }, + { + "BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "SampleAfterValue": "200003", + "UMask": "0x2" + } +] diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/memory.json b/tools/perf/pmu-events/arch/x86/sierraforest/memory.json new file mode 100644 index 000000000000..79d8af45100c --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sierraforest/memory.json @@ -0,0 +1,20 @@ +[ + { + "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_RFO.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00002", + "SampleAfterValue": "100003", + "UMask": "0x1" + } +] diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/other.json b/tools/perf/pmu-events/arch/x86/sierraforest/other.json new file mode 100644 index 000000000000..2414f6ff53b0 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sierraforest/other.json @@ -0,0 +1,20 @@ +[ + { + "BriefDescription": "Counts demand data reads that have any type of response.", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10002", + "SampleAfterValue": "100003", + "UMask": "0x1" + } +] diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/pipeline.json b/tools/perf/pmu-events/arch/x86/sierraforest/pipeline.json new file mode 100644 index 000000000000..41212957ef21 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sierraforest/pipeline.json @@ -0,0 +1,96 @@ +[ + { + "BriefDescription": "Counts the total number of branch instructions retired for all branch types.", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", + "EventName": "CPU_CLK_UNHALTED.CORE", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.THREAD_P]", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.CORE_P", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", + "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_CLK_UNHALTED.CORE_P]", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Fixed Counter: Counts the number of instructions retired", + "EventName": "INST_RETIRED.ANY", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of instructions retired", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.ANY_P", + "PEBS": "1", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.ALL", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", + "SampleAfterValue": "1000003" + }, + { + "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.ALL", + "SampleAfterValue": "1000003" + }, + { + "BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.ALL", + "SampleAfterValue": "1000003" + }, + { + "BriefDescription": "Counts the number of consumed retirement slots. Similar to UOPS_RETIRED.ALL", + "EventCode": "0x72", + "EventName": "TOPDOWN_RETIRING.ALL", + "PEBS": "1", + "SampleAfterValue": "1000003" + } +] diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/virtual-memory.json b/tools/perf/pmu-events/arch/x86/sierraforest/virtual-memory.json new file mode 100644 index 000000000000..bd5f2b634c98 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sierraforest/virtual-memory.json @@ -0,0 +1,24 @@ +[ + { + "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G page.", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "SampleAfterValue": "1000003", + "UMask": "0xe" + }, + { + "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G page.", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "SampleAfterValue": "1000003", + "UMask": "0xe" + }, + { + "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.", + "SampleAfterValue": "200003", + "UMask": "0xe" + } +] -- cgit v1.2.3-58-ga151 From 759e81507e82375475c6ff1cd328b2e4bb10aee6 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 13 Apr 2023 06:29:32 -0700 Subject: perf vendor events intel: Fix uncore topics for alderlake Move events from 'uncore-other' topic classification to interconnect. Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230413132949.3487664-5-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/x86/alderlake/uncore-interconnect.json | 90 ++++++++++++++++++++++ .../arch/x86/alderlake/uncore-other.json | 88 --------------------- .../arch/x86/alderlaken/uncore-interconnect.json | 26 +++++++ .../arch/x86/alderlaken/uncore-other.json | 24 ------ 4 files changed, 116 insertions(+), 112 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/alderlake/uncore-interconnect.json create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/uncore-interconnect.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/alderlake/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/alderlake/uncore-interconnect.json new file mode 100644 index 000000000000..34fc052d00e4 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/alderlake/uncore-interconnect.json @@ -0,0 +1,90 @@ +[ + { + "BriefDescription": "Number of requests allocated in Coherency Tracker.", + "EventCode": "0x84", + "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core.", + "EventCode": "0x85", + "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core.", + "EventCode": "0x85", + "EventName": "UNC_ARB_DAT_OCCUPANCY.RD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_REQ_TRK_REQUEST.DRD", + "EventCode": "0x81", + "EventName": "UNC_ARB_DAT_REQUESTS.RD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL", + "EventCode": "0x85", + "EventName": "UNC_ARB_IFA_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_OCCUPANCY.RD]", + "EventCode": "0x80", + "EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_REQUESTS.RD]", + "EventCode": "0x81", + "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_OCCUPANCY.DRD]", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.RD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_REQUEST.DRD]", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.RD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + } +] diff --git a/tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json b/tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json index 5f3b4c6e2e39..2af92e43b28a 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json @@ -1,92 +1,4 @@ [ - { - "BriefDescription": "Number of requests allocated in Coherency Tracker.", - "EventCode": "0x84", - "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core.", - "EventCode": "0x85", - "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core.", - "EventCode": "0x85", - "EventName": "UNC_ARB_DAT_OCCUPANCY.RD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "ARB" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_REQ_TRK_REQUEST.DRD", - "EventCode": "0x81", - "EventName": "UNC_ARB_DAT_REQUESTS.RD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "ARB" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL", - "EventCode": "0x85", - "EventName": "UNC_ARB_IFA_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_OCCUPANCY.RD]", - "EventCode": "0x80", - "EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "ARB" - }, - { - "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_REQUESTS.RD]", - "EventCode": "0x81", - "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "ARB" - }, - { - "BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.", - "EventCode": "0x80", - "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_OCCUPANCY.DRD]", - "EventCode": "0x80", - "EventName": "UNC_ARB_TRK_OCCUPANCY.RD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "ARB" - }, - { - "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_REQUEST.DRD]", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.RD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "ARB" - }, { "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.", "EventCode": "0xff", diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-interconnect.json new file mode 100644 index 000000000000..4af695a5e755 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-interconnect.json @@ -0,0 +1,26 @@ +[ + { + "BriefDescription": "Number of requests allocated in Coherency Tracker.", + "EventCode": "0x84", + "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + } +] diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/uncore-other.json b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-other.json index f9e7777cd2be..2af92e43b28a 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-other.json @@ -1,28 +1,4 @@ [ - { - "BriefDescription": "Number of requests allocated in Coherency Tracker.", - "EventCode": "0x84", - "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.", - "EventCode": "0x80", - "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, { "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.", "EventCode": "0xff", -- cgit v1.2.3-58-ga151 From 141825578a2467294752d2952c166116e32af2ca Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 13 Apr 2023 06:29:33 -0700 Subject: perf vendor events intel: Fix uncore topics for broadwell Reduce the number of 'uncore-other' topic classifications, move to cache and interconnect. Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230413132949.3487664-6-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/x86/broadwell/uncore-cache.json | 30 +++++------ .../arch/x86/broadwell/uncore-interconnect.json | 61 ++++++++++++++++++++++ .../arch/x86/broadwell/uncore-other.json | 59 --------------------- 3 files changed, 76 insertions(+), 74 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/broadwell/uncore-interconnect.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json b/tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json index fcb15b880bad..c5cc43825cb9 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json @@ -6,7 +6,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.", "UMask": "0x86", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup any request that access cache and found line in I-state", @@ -15,7 +15,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.", "UMask": "0x88", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup any request that access cache and found line in M-state", @@ -24,7 +24,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.", "UMask": "0x81", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state", @@ -33,7 +33,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.", "UMask": "0x8f", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state", @@ -42,7 +42,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.", "UMask": "0x16", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup read request that access cache and found line in I-state", @@ -51,7 +51,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup read request that access cache and found line in I-state.", "UMask": "0x18", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup read request that access cache and found line in M-state", @@ -60,7 +60,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup read request that access cache and found line in M-state.", "UMask": "0x11", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state", @@ -69,7 +69,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.", "UMask": "0x1f", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state", @@ -78,7 +78,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.", "UMask": "0x26", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup write request that access cache and found line in M-state", @@ -87,7 +87,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.", "UMask": "0x21", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state", @@ -96,7 +96,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.", "UMask": "0x2f", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.", @@ -104,7 +104,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", "PerPkg": "1", "UMask": "0x48", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.", @@ -112,7 +112,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", "PerPkg": "1", "UMask": "0x44", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.", @@ -120,7 +120,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", "PerPkg": "1", "UMask": "0x81", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.", @@ -128,6 +128,6 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", "PerPkg": "1", "UMask": "0x41", - "Unit": "CBO" + "Unit": "CBOX" } ] diff --git a/tools/perf/pmu-events/arch/x86/broadwell/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/broadwell/uncore-interconnect.json new file mode 100644 index 000000000000..64af685274a2 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwell/uncore-interconnect.json @@ -0,0 +1,61 @@ +[ + { + "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.", + "EventCode": "0x84", + "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle counts number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;", + "CounterMask": "1", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT", + "PerPkg": "1", + "PublicDescription": "Each cycle count number of valid coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of Core coherent Data Read entries allocated in DirectData mode", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT", + "PerPkg": "1", + "PublicDescription": "Number of Core coherent Data Read entries allocated in DirectData mode.", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "ARB" + } +] diff --git a/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json b/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json index 368a958a18a0..58be90d7cc93 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json @@ -1,63 +1,4 @@ [ - { - "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.", - "EventCode": "0x84", - "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Each cycle counts number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.", - "EventCode": "0x80", - "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;", - "CounterMask": "1", - "EventCode": "0x80", - "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.", - "EventCode": "0x80", - "EventName": "UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT", - "PerPkg": "1", - "PublicDescription": "Each cycle count number of valid coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.", - "UMask": "0x2", - "Unit": "ARB" - }, - { - "BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Number of Core coherent Data Read entries allocated in DirectData mode", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT", - "PerPkg": "1", - "PublicDescription": "Number of Core coherent Data Read entries allocated in DirectData mode.", - "UMask": "0x2", - "Unit": "ARB" - }, - { - "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "ARB" - }, { "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles", "EventCode": "0xff", -- cgit v1.2.3-58-ga151 From 55b7bcef861c1345deb09c71d626e88174a20703 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 13 Apr 2023 06:29:34 -0700 Subject: perf vendor events intel: Fix uncore topics for broadwellde Remove 'uncore-other' topic classification, move to cache, interconnect and io. Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230413132949.3487664-7-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/x86/broadwellde/uncore-cache.json | 324 +++--- .../arch/x86/broadwellde/uncore-interconnect.json | 614 ++++++++++ .../pmu-events/arch/x86/broadwellde/uncore-io.json | 555 ++++++++++ .../arch/x86/broadwellde/uncore-other.json | 1167 -------------------- 4 files changed, 1331 insertions(+), 1329 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/broadwellde/uncore-interconnect.json create mode 100644 tools/perf/pmu-events/arch/x86/broadwellde/uncore-io.json delete mode 100644 tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json index 2bf23ef7bfac..56bba6d4e0f6 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json @@ -4,13 +4,13 @@ "EventCode": "0xA", "EventName": "UNC_C_BOUNCE_CONTROL", "PerPkg": "1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Uncore Clocks", "EventName": "UNC_C_CLOCKTICKS", "PerPkg": "1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Counter 0 Occupancy", @@ -18,7 +18,7 @@ "EventName": "UNC_C_COUNTER0_OCCUPANCY", "PerPkg": "1", "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "FaST wire asserted", @@ -26,7 +26,7 @@ "EventName": "UNC_C_FAST_ASSERTED", "PerPkg": "1", "PublicDescription": "Counts the number of cycles either the local distress or incoming distress signals are asserted. Incoming distress includes both up and dn.", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; Any Request", @@ -35,7 +35,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.", "UMask": "0x11", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; Data Read Request", @@ -44,7 +44,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; Lookups that Match NID", @@ -53,7 +53,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x41", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; Any Read Request", @@ -62,7 +62,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions", "UMask": "0x21", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; External Snoop Request", @@ -71,7 +71,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ.", "UMask": "0x9", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; Write Requests", @@ -80,7 +80,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.", "UMask": "0x5", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized; Lines in E state", @@ -89,7 +89,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized", @@ -98,7 +98,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized; Lines in S State", @@ -107,7 +107,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized", @@ -116,7 +116,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized; Lines in M state", @@ -125,7 +125,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized; Victimized Lines that Match NID", @@ -134,7 +134,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=0", @@ -143,7 +143,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc; Clean Victim with raw CV=0", @@ -152,7 +152,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc; RFO HitS", @@ -161,7 +161,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.; Number of times that an RFO hit in S state. This is useful for determining if it might be good for a workload to use RspIWB instead of RspSWB.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc; Silent Snoop Eviction", @@ -170,7 +170,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc", @@ -179,7 +179,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc; Write Combining Aliasing", @@ -188,7 +188,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LRU Queue; LRU Age 0", @@ -197,7 +197,7 @@ "PerPkg": "1", "PublicDescription": "How often age was set to 0", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LRU Queue; LRU Age 1", @@ -206,7 +206,7 @@ "PerPkg": "1", "PublicDescription": "How often age was set to 1", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LRU Queue; LRU Age 2", @@ -215,7 +215,7 @@ "PerPkg": "1", "PublicDescription": "How often age was set to 2", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LRU Queue; LRU Age 3", @@ -224,7 +224,7 @@ "PerPkg": "1", "PublicDescription": "How often age was set to 3", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LRU Queue; LRU Bits Decremented", @@ -233,7 +233,7 @@ "PerPkg": "1", "PublicDescription": "How often all LRU bits were decremented by 1", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LRU Queue; Non-0 Aged Victim", @@ -242,7 +242,7 @@ "PerPkg": "1", "PublicDescription": "How often we picked a victim that had a non-zero age", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; All", @@ -251,7 +251,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0xf", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Down", @@ -260,7 +260,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0xc", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Up", @@ -269,7 +269,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Down and Even", @@ -278,7 +278,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Down and Odd", @@ -287,7 +287,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Up and Even", @@ -296,7 +296,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Up and Odd", @@ -305,7 +305,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; All", @@ -314,7 +314,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0xf", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Down", @@ -323,7 +323,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0xc", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Up", @@ -332,7 +332,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Down and Even", @@ -341,7 +341,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Down and Odd", @@ -350,7 +350,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Up and Even", @@ -359,7 +359,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Up and Odd", @@ -368,7 +368,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Down", @@ -377,7 +377,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0xf", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Down", @@ -386,7 +386,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0xc", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Up", @@ -395,7 +395,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Down and Even", @@ -404,7 +404,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Down and Odd", @@ -413,7 +413,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Up and Even", @@ -422,7 +422,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Up and Odd", @@ -431,7 +431,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of LLC responses that bounced on the Ring.; AD", @@ -439,7 +439,7 @@ "EventName": "UNC_C_RING_BOUNCES.AD", "PerPkg": "1", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of LLC responses that bounced on the Ring.; AK", @@ -447,7 +447,7 @@ "EventName": "UNC_C_RING_BOUNCES.AK", "PerPkg": "1", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of LLC responses that bounced on the Ring.; BL", @@ -455,7 +455,7 @@ "EventName": "UNC_C_RING_BOUNCES.BL", "PerPkg": "1", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.", @@ -463,7 +463,7 @@ "EventName": "UNC_C_RING_BOUNCES.IV", "PerPkg": "1", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Any", @@ -472,7 +472,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity", "UMask": "0xf", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Any", @@ -481,7 +481,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity", "UMask": "0xc", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Down", @@ -490,7 +490,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters for Down polarity", "UMask": "0xcc", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Any", @@ -499,7 +499,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD", @@ -507,7 +507,7 @@ "EventName": "UNC_C_RING_SINK_STARVED.AD", "PerPkg": "1", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK", @@ -515,7 +515,7 @@ "EventName": "UNC_C_RING_SINK_STARVED.AK", "PerPkg": "1", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL", @@ -523,7 +523,7 @@ "EventName": "UNC_C_RING_SINK_STARVED.BL", "PerPkg": "1", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "IV", @@ -531,14 +531,14 @@ "EventName": "UNC_C_RING_SINK_STARVED.IV", "PerPkg": "1", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic.", "EventCode": "0x7", "EventName": "UNC_C_RING_SRC_THRTL", "PerPkg": "1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ", @@ -547,7 +547,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally startved and therefore we are blocking the IRQ.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ", @@ -556,7 +556,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IRQ is externally starved and therefore we are blocking the IPQ.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID", @@ -565,7 +565,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; Number of times that the ISMQ Bid.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; PRQ", @@ -574,7 +574,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Allocations; IPQ", @@ -583,7 +583,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Allocations; IRQ", @@ -592,7 +592,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Allocations; IRQ Rejected", @@ -601,7 +601,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Allocations; PRQ", @@ -610,7 +610,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Allocations; PRQ", @@ -619,7 +619,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Internal Starvation Cycles; IPQ", @@ -628,7 +628,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IPQ in Internal Starvation.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Internal Starvation Cycles; IRQ", @@ -637,7 +637,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IRQ in Internal Starvation.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ", @@ -646,7 +646,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the ISMQ in Internal Starvation.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Internal Starvation Cycles; PRQ", @@ -655,7 +655,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; Address Conflict", @@ -664,7 +664,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from an address conflicts. Address conflicts out of the IPQ should be rare. They will generally only occur if two different sockets are sending requests to the same address at the same time. This is a true conflict case, unlike the IPQ Address Conflict which is commonly caused by prefetching characteristics.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; Any Reject", @@ -673,7 +673,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject. TOR rejects from the IPQ can be caused by the Egress being full or Address Conflicts.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; No Egress Credits", @@ -682,7 +682,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from the Egress being full. IPQ requests make use of the AD Egress for regular responses, the BL egress to forward data, and the AK egress to return credits.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; No QPI Credits", @@ -691,7 +691,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; No AD Sbo Credits", @@ -700,7 +700,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; Target Node Filter", @@ -709,7 +709,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; Address Conflict", @@ -718,7 +718,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the IRQ was retried because of an address match in the TOR. In order to maintain coherency, requests to the same address are not allowed to pass each other up in the Cbo. Therefore, if there is an outstanding request to a given address, one cannot issue another request to that address until it is complete. This comes up most commonly with prefetches. Outstanding prefetches occasionally will not complete their memory fetch and a demand request to the same address will then sit in the IRQ and get retried until the prefetch fills the data into the LLC. Therefore, it will not be uncommon to see this case in high bandwidth streaming workloads when the LLC Prefetcher in the core is enabled.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; Any Reject", @@ -727,7 +727,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of IRQ retries that occur. Requests from the IRQ are retried if they are rejected from the TOR pipeline for a variety of reasons. Some of the most common reasons include if the Egress is full, there are no RTIDs, or there is a Physical Address match to another outstanding request.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No Egress Credits", @@ -736,7 +736,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the IRQ was retried because it failed to acquire an entry in the Egress. The egress is the buffer that queues up for allocating onto the ring. IRQ requests can make use of all four rings and all four Egresses. If any of the queues that a given request needs to make use of are full, the request will be retried.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits", @@ -745,7 +745,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO. There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects", @@ -754,7 +754,7 @@ "PerPkg": "1", "PublicDescription": "Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No QPI Credits", @@ -763,7 +763,7 @@ "PerPkg": "1", "PublicDescription": "Number of requests rejects because of lack of QPI Ingress credits. These credits are required in order to send transactions to the QPI agent. Please see the QPI_IGR_CREDITS events for more information.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No RTIDs", @@ -772,7 +772,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that requests from the IRQ were retried because there were no RTIDs available. RTIDs are required after a request misses the LLC and needs to send snoops and/or requests to memory. If there are no RTIDs available, requests will queue up in the IRQ and retry until one becomes available. Note that there are multiple RTID pools for the different sockets. There may be cases where the local RTIDs are all used, but requests destined for remote memory can still acquire an RTID because there are remote RTIDs available. This event does not provide any filtering for this case.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No AD Sbo Credits", @@ -781,7 +781,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No BL Sbo Credits", @@ -790,7 +790,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an BL packet to the Sbo.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; Target Node Filter", @@ -799,7 +799,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; Any Reject", @@ -808,7 +808,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the total number of times that a request from the ISMQ retried because of a TOR reject. ISMQ requests generally will not need to retry (or at least ISMQ retries are less common than IRQ retries). ISMQ requests will retry if they are not able to acquire a needed Egress credit to get onto the ring, or for cache evictions that need to acquire an RTID. Most ISMQ requests already have an RTID, so eviction retries will be less common here.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; No Egress Credits", @@ -817,7 +817,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by a lack of Egress credits. The egress is the buffer that queues up for allocating onto the ring. If any of the Egress queues that a given request needs to make use of are full, the request will be retried.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; No IIO Credits", @@ -826,7 +826,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO. There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries", @@ -835,7 +835,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; No QPI Credits", @@ -844,7 +844,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; No RTIDs", @@ -853,7 +853,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by no RTIDs. M-state cache evictions are serviced through the ISMQ, and must acquire an RTID in order to write back to memory. If no RTIDs are available, they will be retried.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries", @@ -862,7 +862,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.", "UMask": "0x80", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Request Queue Rejects; No AD Sbo Credits", @@ -871,7 +871,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an AD packet to the Sbo.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Request Queue Rejects; No BL Sbo Credits", @@ -880,7 +880,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an BL packet to the Sbo.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Request Queue Rejects; Target Node Filter", @@ -889,7 +889,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the ISMQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Occupancy; IPQ", @@ -898,7 +898,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Occupancy; IRQ", @@ -907,7 +907,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Occupancy; IRQ Rejected", @@ -916,7 +916,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Occupancy; PRQ Rejects", @@ -925,7 +925,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "SBo Credits Acquired; For AD Ring", @@ -934,7 +934,7 @@ "PerPkg": "1", "PublicDescription": "Number of Sbo credits acquired in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "SBo Credits Acquired; For BL Ring", @@ -943,7 +943,7 @@ "PerPkg": "1", "PublicDescription": "Number of Sbo credits acquired in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "SBo Credits Occupancy; For AD Ring", @@ -952,7 +952,7 @@ "PerPkg": "1", "PublicDescription": "Number of Sbo credits in use in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "SBo Credits Occupancy; For BL Ring", @@ -961,7 +961,7 @@ "PerPkg": "1", "PublicDescription": "Number of Sbo credits in use in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; All", @@ -970,7 +970,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Evictions", @@ -979,7 +979,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Eviction transactions inserted into the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Local Memory", @@ -988,7 +988,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x28", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched", @@ -997,7 +997,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisfied by an opcode, inserted into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x21", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Misses to Local Memory", @@ -1006,7 +1006,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x2a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode Matched", @@ -1015,7 +1015,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisfied by an opcode, inserted into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x23", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Miss Opcode Match", @@ -1024,7 +1024,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Misses to Remote Memory", @@ -1033,7 +1033,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x8a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode Matched", @@ -1042,7 +1042,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisfied by an opcode, inserted into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x83", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID Matched", @@ -1051,7 +1051,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x48", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID Matched Evictions", @@ -1060,7 +1060,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction transactions inserted into the TOR.", "UMask": "0x44", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID Matched Miss All", @@ -1069,7 +1069,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.", "UMask": "0x4a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss", @@ -1078,7 +1078,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode.", "UMask": "0x43", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID and Opcode Matched", @@ -1087,7 +1087,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode.", "UMask": "0x41", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID Matched Writebacks", @@ -1096,7 +1096,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transactions inserted into the TOR.", "UMask": "0x50", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Opcode Match", @@ -1105,7 +1105,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Remote Memory", @@ -1114,7 +1114,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x88", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched", @@ -1123,7 +1123,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisfied by an opcode, inserted into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x81", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Writebacks", @@ -1132,7 +1132,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Write transactions inserted into the TOR. This does not include RFO, but actual operations that contain data being sent from the core.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Any", @@ -1141,7 +1141,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All valid TOR entries. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Evictions", @@ -1150,7 +1150,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding eviction transactions in the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy", @@ -1159,7 +1159,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x28", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched", @@ -1168,7 +1168,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisfied by an opcode, in the TOR that are satisfied by locally HOMed memory.", "UMask": "0x21", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Miss All", @@ -1177,7 +1177,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding miss requests in the TOR. 'Miss' means the allocation requires an RTID. This generally means that the request was sent to memory or MMIO.", "UMask": "0xa", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy", @@ -1186,7 +1186,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x2a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcode Matched", @@ -1195,7 +1195,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisfied by an opcode, in the TOR that are satisfied by locally HOMed memory.", "UMask": "0x23", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Miss Opcode Match", @@ -1204,7 +1204,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO.", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy", @@ -1213,7 +1213,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x8a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opcode Matched", @@ -1222,7 +1222,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisfied by an opcode, in the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x83", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID Matched", @@ -1231,7 +1231,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of NID matched outstanding requests in the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x48", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID Matched Evictions", @@ -1240,7 +1240,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding NID matched eviction transactions in the TOR .", "UMask": "0x44", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID Matched", @@ -1249,7 +1249,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID.", "UMask": "0x4a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss", @@ -1258,7 +1258,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID and an opcode.", "UMask": "0x43", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID and Opcode Matched", @@ -1267,7 +1267,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match a NID and an opcode.", "UMask": "0x41", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID Matched Writebacks", @@ -1276,7 +1276,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); NID matched write transactions int the TOR.", "UMask": "0x50", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Opcode Match", @@ -1285,7 +1285,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc).", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy", @@ -1294,7 +1294,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x88", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Remote Memory - Opcode Matched", @@ -1303,7 +1303,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisfied by an opcode, in the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x81", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Writebacks", @@ -1312,7 +1312,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Write transactions in the TOR. This does not include RFO, but actual operations that contain data being sent from the core.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Onto AD Ring", @@ -1320,7 +1320,7 @@ "EventName": "UNC_C_TxR_ADS_USED.AD", "PerPkg": "1", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Onto AK Ring", @@ -1328,7 +1328,7 @@ "EventName": "UNC_C_TxR_ADS_USED.AK", "PerPkg": "1", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Onto BL Ring", @@ -1336,7 +1336,7 @@ "EventName": "UNC_C_TxR_ADS_USED.BL", "PerPkg": "1", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; AD - Cachebo", @@ -1345,7 +1345,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; AD - Corebo", @@ -1354,7 +1354,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AD ring. This is commonly used for outbound requests.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; AK - Cachebo", @@ -1363,7 +1363,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AK ring. This is commonly used for credit returns and GO responses.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; AK - Corebo", @@ -1372,7 +1372,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AK ring. This is commonly used for snoop responses coming from the core and destined for a Cachebo.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; BL - Cacheno", @@ -1381,7 +1381,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the BL ring. This is commonly used to send data from the cache to various destinations.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; BL - Corebo", @@ -1390,7 +1390,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring. This is commonly used for transferring writeback data to the cache.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; IV - Cachebo", @@ -1399,7 +1399,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the IV ring. This is commonly used for snoops to the cores.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Injection Starvation; Onto AD Ring (to core)", @@ -1408,7 +1408,7 @@ "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the core AD egress spent in starvation", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Injection Starvation; Onto AK Ring", @@ -1417,7 +1417,7 @@ "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both AK egresses spent in starvation", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Injection Starvation; Onto BL Ring", @@ -1426,7 +1426,7 @@ "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both BL egresses spent in starvation", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Injection Starvation; Onto IV Ring", @@ -1435,7 +1435,7 @@ "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the cachebo IV egress spent in starvation", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BT Cycles Not Empty", diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-interconnect.json new file mode 100644 index 000000000000..8a327e0f1441 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-interconnect.json @@ -0,0 +1,614 @@ +[ + { + "BriefDescription": "Total Write Cache Occupancy; Any Source", + "EventCode": "0x12", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Total Write Cache Occupancy; Select Source", + "EventCode": "0x12", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Clocks in the IRP", + "EventName": "UNC_I_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Number of clocks in the IRP.", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; CLFlush", + "EventCode": "0x13", + "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; CRd", + "EventCode": "0x13", + "EventName": "UNC_I_COHERENT_OPS.CRD", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; DRd", + "EventCode": "0x13", + "EventName": "UNC_I_COHERENT_OPS.DRD", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; PCIDCAHin5t", + "EventCode": "0x13", + "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; PCIRdCur", + "EventCode": "0x13", + "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; PCIItoM", + "EventCode": "0x13", + "EventName": "UNC_I_COHERENT_OPS.PCITOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; RFO", + "EventCode": "0x13", + "EventName": "UNC_I_COHERENT_OPS.RFO", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; WbMtoI", + "EventCode": "0x13", + "EventName": "UNC_I_COHERENT_OPS.WBMTOI", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", + "PerPkg": "1", + "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.2ND_RD_INSERT", + "PerPkg": "1", + "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.2ND_WR_INSERT", + "PerPkg": "1", + "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Fastpath Rejects", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.FAST_REJ", + "PerPkg": "1", + "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Fastpath Requests", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.FAST_REQ", + "PerPkg": "1", + "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Requests", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.FAST_XFER", + "PerPkg": "1", + "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.PF_ACK_HINT", + "PerPkg": "1", + "PublicDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Prefetch TimeOut", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.PF_TIMEOUT", + "PerPkg": "1", + "PublicDescription": "Indicates the fetch for a previous prefetch wasn't accepted by the prefetch. This happens in the case of a prefetch TimeOut", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Data Throttled", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.DATA_THROTTLE", + "PerPkg": "1", + "PublicDescription": "IRP throttled switch data", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.LOST_FWD", + "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Received Invalid", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", + "PerPkg": "1", + "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Received Valid", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", + "PerPkg": "1", + "PublicDescription": "Secondary received a transfer that did have sufficient MESI state", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SLOW_E", + "PerPkg": "1", + "PublicDescription": "Secondary received a transfer that did have sufficient MESI state", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SLOW_I", + "PerPkg": "1", + "PublicDescription": "Snoop took cacheline ownership before write from data was committed.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SLOW_M", + "PerPkg": "1", + "PublicDescription": "Snoop took cacheline ownership before write from data was committed.", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SLOW_S", + "PerPkg": "1", + "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "AK Ingress Occupancy", + "EventCode": "0xA", + "EventName": "UNC_I_RxR_AK_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the AK Ingress. This queue is where the IRP receives responses from R2PCIe (the ring).", + "Unit": "IRP" + }, + { + "BriefDescription": "UNC_I_RxR_BL_DRS_CYCLES_FULL", + "EventCode": "0x4", + "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "BL Ingress Occupancy - DRS", + "EventCode": "0x1", + "EventName": "UNC_I_RxR_BL_DRS_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "UNC_I_RxR_BL_DRS_OCCUPANCY", + "EventCode": "0x7", + "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "UNC_I_RxR_BL_NCB_CYCLES_FULL", + "EventCode": "0x5", + "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "BL Ingress Occupancy - NCB", + "EventCode": "0x2", + "EventName": "UNC_I_RxR_BL_NCB_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "UNC_I_RxR_BL_NCB_OCCUPANCY", + "EventCode": "0x8", + "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "UNC_I_RxR_BL_NCS_CYCLES_FULL", + "EventCode": "0x6", + "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "BL Ingress Occupancy - NCS", + "EventCode": "0x3", + "EventName": "UNC_I_RxR_BL_NCS_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "UNC_I_RxR_BL_NCS_OCCUPANCY", + "EventCode": "0x9", + "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Hit E or S", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.HIT_ES", + "PerPkg": "1", + "PublicDescription": "Snoop Responses : Hit E or S", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Hit I", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.HIT_I", + "PerPkg": "1", + "PublicDescription": "Snoop Responses : Hit I", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Hit M", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.HIT_M", + "PerPkg": "1", + "PublicDescription": "Snoop Responses : Hit M", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Miss", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.MISS", + "PerPkg": "1", + "PublicDescription": "Snoop Responses : Miss", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; SnpCode", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.SNPCODE", + "PerPkg": "1", + "PublicDescription": "Snoop Responses : SnpCode", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; SnpData", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.SNPDATA", + "PerPkg": "1", + "PublicDescription": "Snoop Responses : SnpData", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; SnpInv", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.SNPINV", + "PerPkg": "1", + "PublicDescription": "Snoop Responses : SnpInv", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Atomic", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.ATOMIC", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Other", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.OTHER", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions.", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Read Prefetches", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.RD_PREF", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Reads", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.READS", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Writes", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.WRITES", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Write Prefetches", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of write prefetches.", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "No AD Egress Credit Stalls", + "EventCode": "0x18", + "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.", + "Unit": "IRP" + }, + { + "BriefDescription": "No BL Egress Credit Stalls", + "EventCode": "0x19", + "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "EventCode": "0xE", + "EventName": "UNC_I_TxR_DATA_INSERTS_NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "EventCode": "0xF", + "EventName": "UNC_I_TxR_DATA_INSERTS_NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Request Queue Occupancy", + "EventCode": "0xD", + "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.", + "Unit": "IRP" + }, + { + "BriefDescription": "VLW Received", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.DISABLE", + "PerPkg": "1", + "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.ENABLE", + "PerPkg": "1", + "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE", + "PerPkg": "1", + "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE", + "PerPkg": "1", + "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", + "EventCode": "0x45", + "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", + "PerPkg": "1", + "PublicDescription": "PHOLD cycles. Filter from source CoreID.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "RACU Request", + "EventCode": "0x46", + "EventName": "UNC_U_RACU_REQUESTS", + "PerPkg": "1", + "PublicDescription": "Number outstanding register requests within message channel tracker", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Correctable Machine Check", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.CMC", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one or all cores", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Livelock", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.LIVELOCK", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; LTError", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.LTERROR", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Monitor T0", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Monitor T1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Other", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.OTHER", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one or all cores; PREQ, PSMI, P2U, Thermal, PCUSMI, PMI", + "UMask": "0x80", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Trap", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.TRAP", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one or all cores", + "UMask": "0x40", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.UMC", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one or all cores", + "UMask": "0x20", + "Unit": "UBOX" + } +] diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-io.json b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-io.json new file mode 100644 index 000000000000..01e04daf03da --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-io.json @@ -0,0 +1,555 @@ +[ + { + "BriefDescription": "Number of uclks in domain", + "EventCode": "0x1", + "EventName": "UNC_R2_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts the number of uclks in the R2PCIe uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI0", + "EventCode": "0x2D", + "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI1", + "EventCode": "0x2D", + "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI0", + "EventCode": "0x2D", + "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI1", + "EventCode": "0x2D", + "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; DRS", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; NCB", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; NCS", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; DRS", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; NCB", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; NCS", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; All", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xf", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xc", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x3", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise and Even", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "AK Ingress Bounced; Dn", + "EventCode": "0x12", + "EventName": "UNC_R2_RING_AK_BOUNCES.DN", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "AK Ingress Bounced; Up", + "EventCode": "0x12", + "EventName": "UNC_R2_RING_AK_BOUNCES.UP", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; All", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xf", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xc", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x3", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise and Even", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; All", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xf", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xc", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x3", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise and Even", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 IV Ring in Use; Any", + "EventCode": "0xA", + "EventName": "UNC_R2_RING_IV_USED.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", + "UMask": "0xf", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 IV Ring in Use; Counterclockwise", + "EventCode": "0xA", + "EventName": "UNC_R2_RING_IV_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", + "UMask": "0xc", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 IV Ring in Use; Clockwise", + "EventCode": "0xA", + "EventName": "UNC_R2_RING_IV_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", + "UMask": "0x3", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NCB", + "EventCode": "0x10", + "EventName": "UNC_R2_RxR_CYCLES_NE.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NCS", + "EventCode": "0x10", + "EventName": "UNC_R2_RxR_CYCLES_NE.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Allocations; NCB", + "EventCode": "0x11", + "EventName": "UNC_R2_RxR_INSERTS.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Allocations; NCS", + "EventCode": "0x11", + "EventName": "UNC_R2_RxR_INSERTS.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; DRS", + "EventCode": "0x13", + "EventName": "UNC_R2_RxR_OCCUPANCY.DRS", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "SBo0 Credits Acquired; For AD Ring", + "EventCode": "0x28", + "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.AD", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "SBo0 Credits Acquired; For BL Ring", + "EventCode": "0x28", + "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.BL", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "SBo0 Credits Occupancy; For AD Ring", + "EventCode": "0x2A", + "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.AD", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "SBo0 Credits Occupancy; For BL Ring", + "EventCode": "0x2A", + "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.BL", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring", + "EventCode": "0x2C", + "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD", + "PerPkg": "1", + "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring", + "EventCode": "0x2C", + "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL", + "PerPkg": "1", + "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring", + "EventCode": "0x2C", + "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD", + "PerPkg": "1", + "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring", + "EventCode": "0x2C", + "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL", + "PerPkg": "1", + "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; AD", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AD Egress Queue", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; AK", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.AK", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AK Egress Queue", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; BL", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.BL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; BL Egress Queue", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; AD", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AD Egress Queue", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; AK", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.AK", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AK Egress Queue", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; BL", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.BL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; BL Egress Queue", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; AD CCW", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.DN_AD", + "PerPkg": "1", + "PublicDescription": "AD CounterClockwise Egress Queue", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; AK CCW", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.DN_AK", + "PerPkg": "1", + "PublicDescription": "AK CounterClockwise Egress Queue", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; BL CCW", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.DN_BL", + "PerPkg": "1", + "PublicDescription": "BL CounterClockwise Egress Queue", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; AK CCW", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.UP_AD", + "PerPkg": "1", + "PublicDescription": "BL CounterClockwise Egress Queue", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; BL CW", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.UP_AK", + "PerPkg": "1", + "PublicDescription": "AD Clockwise Egress Queue", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; BL CCW", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.UP_BL", + "PerPkg": "1", + "PublicDescription": "AD CounterClockwise Egress Queue", + "UMask": "0x10", + "Unit": "R2PCIe" + } +] diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json deleted file mode 100644 index fea3dea67f38..000000000000 --- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-other.json +++ /dev/null @@ -1,1167 +0,0 @@ -[ - { - "BriefDescription": "Total Write Cache Occupancy; Any Source", - "EventCode": "0x12", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Total Write Cache Occupancy; Select Source", - "EventCode": "0x12", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Clocks in the IRP", - "EventName": "UNC_I_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Number of clocks in the IRP.", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; CLFlush", - "EventCode": "0x13", - "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x80", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; CRd", - "EventCode": "0x13", - "EventName": "UNC_I_COHERENT_OPS.CRD", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; DRd", - "EventCode": "0x13", - "EventName": "UNC_I_COHERENT_OPS.DRD", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; PCIDCAHin5t", - "EventCode": "0x13", - "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; PCIRdCur", - "EventCode": "0x13", - "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; PCIItoM", - "EventCode": "0x13", - "EventName": "UNC_I_COHERENT_OPS.PCITOM", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; RFO", - "EventCode": "0x13", - "EventName": "UNC_I_COHERENT_OPS.RFO", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; WbMtoI", - "EventCode": "0x13", - "EventName": "UNC_I_COHERENT_OPS.WBMTOI", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary", - "EventCode": "0x14", - "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", - "PerPkg": "1", - "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary", - "EventCode": "0x14", - "EventName": "UNC_I_MISC0.2ND_RD_INSERT", - "PerPkg": "1", - "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary", - "EventCode": "0x14", - "EventName": "UNC_I_MISC0.2ND_WR_INSERT", - "PerPkg": "1", - "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Fastpath Rejects", - "EventCode": "0x14", - "EventName": "UNC_I_MISC0.FAST_REJ", - "PerPkg": "1", - "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Fastpath Requests", - "EventCode": "0x14", - "EventName": "UNC_I_MISC0.FAST_REQ", - "PerPkg": "1", - "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Requests", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary", - "EventCode": "0x14", - "EventName": "UNC_I_MISC0.FAST_XFER", - "PerPkg": "1", - "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary", - "EventCode": "0x14", - "EventName": "UNC_I_MISC0.PF_ACK_HINT", - "PerPkg": "1", - "PublicDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Prefetch TimeOut", - "EventCode": "0x14", - "EventName": "UNC_I_MISC0.PF_TIMEOUT", - "PerPkg": "1", - "PublicDescription": "Indicates the fetch for a previous prefetch wasn't accepted by the prefetch. This happens in the case of a prefetch TimeOut", - "UMask": "0x80", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Data Throttled", - "EventCode": "0x15", - "EventName": "UNC_I_MISC1.DATA_THROTTLE", - "PerPkg": "1", - "PublicDescription": "IRP throttled switch data", - "UMask": "0x80", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1", - "EventCode": "0x15", - "EventName": "UNC_I_MISC1.LOST_FWD", - "PerPkg": "1", - "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Received Invalid", - "EventCode": "0x15", - "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", - "PerPkg": "1", - "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Received Valid", - "EventCode": "0x15", - "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", - "PerPkg": "1", - "PublicDescription": "Secondary received a transfer that did have sufficient MESI state", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line", - "EventCode": "0x15", - "EventName": "UNC_I_MISC1.SLOW_E", - "PerPkg": "1", - "PublicDescription": "Secondary received a transfer that did have sufficient MESI state", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line", - "EventCode": "0x15", - "EventName": "UNC_I_MISC1.SLOW_I", - "PerPkg": "1", - "PublicDescription": "Snoop took cacheline ownership before write from data was committed.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line", - "EventCode": "0x15", - "EventName": "UNC_I_MISC1.SLOW_M", - "PerPkg": "1", - "PublicDescription": "Snoop took cacheline ownership before write from data was committed.", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line", - "EventCode": "0x15", - "EventName": "UNC_I_MISC1.SLOW_S", - "PerPkg": "1", - "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "AK Ingress Occupancy", - "EventCode": "0xA", - "EventName": "UNC_I_RxR_AK_INSERTS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the AK Ingress. This queue is where the IRP receives responses from R2PCIe (the ring).", - "Unit": "IRP" - }, - { - "BriefDescription": "UNC_I_RxR_BL_DRS_CYCLES_FULL", - "EventCode": "0x4", - "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "BL Ingress Occupancy - DRS", - "EventCode": "0x1", - "EventName": "UNC_I_RxR_BL_DRS_INSERTS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "UNC_I_RxR_BL_DRS_OCCUPANCY", - "EventCode": "0x7", - "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "UNC_I_RxR_BL_NCB_CYCLES_FULL", - "EventCode": "0x5", - "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "BL Ingress Occupancy - NCB", - "EventCode": "0x2", - "EventName": "UNC_I_RxR_BL_NCB_INSERTS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "UNC_I_RxR_BL_NCB_OCCUPANCY", - "EventCode": "0x8", - "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "UNC_I_RxR_BL_NCS_CYCLES_FULL", - "EventCode": "0x6", - "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "BL Ingress Occupancy - NCS", - "EventCode": "0x3", - "EventName": "UNC_I_RxR_BL_NCS_INSERTS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "UNC_I_RxR_BL_NCS_OCCUPANCY", - "EventCode": "0x9", - "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; Hit E or S", - "EventCode": "0x17", - "EventName": "UNC_I_SNOOP_RESP.HIT_ES", - "PerPkg": "1", - "PublicDescription": "Snoop Responses : Hit E or S", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; Hit I", - "EventCode": "0x17", - "EventName": "UNC_I_SNOOP_RESP.HIT_I", - "PerPkg": "1", - "PublicDescription": "Snoop Responses : Hit I", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; Hit M", - "EventCode": "0x17", - "EventName": "UNC_I_SNOOP_RESP.HIT_M", - "PerPkg": "1", - "PublicDescription": "Snoop Responses : Hit M", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; Miss", - "EventCode": "0x17", - "EventName": "UNC_I_SNOOP_RESP.MISS", - "PerPkg": "1", - "PublicDescription": "Snoop Responses : Miss", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; SnpCode", - "EventCode": "0x17", - "EventName": "UNC_I_SNOOP_RESP.SNPCODE", - "PerPkg": "1", - "PublicDescription": "Snoop Responses : SnpCode", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; SnpData", - "EventCode": "0x17", - "EventName": "UNC_I_SNOOP_RESP.SNPDATA", - "PerPkg": "1", - "PublicDescription": "Snoop Responses : SnpData", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; SnpInv", - "EventCode": "0x17", - "EventName": "UNC_I_SNOOP_RESP.SNPINV", - "PerPkg": "1", - "PublicDescription": "Snoop Responses : SnpInv", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Atomic", - "EventCode": "0x16", - "EventName": "UNC_I_TRANSACTIONS.ATOMIC", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Other", - "EventCode": "0x16", - "EventName": "UNC_I_TRANSACTIONS.OTHER", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions.", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Read Prefetches", - "EventCode": "0x16", - "EventName": "UNC_I_TRANSACTIONS.RD_PREF", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Reads", - "EventCode": "0x16", - "EventName": "UNC_I_TRANSACTIONS.READS", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Writes", - "EventCode": "0x16", - "EventName": "UNC_I_TRANSACTIONS.WRITES", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Write Prefetches", - "EventCode": "0x16", - "EventName": "UNC_I_TRANSACTIONS.WR_PREF", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of write prefetches.", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "No AD Egress Credit Stalls", - "EventCode": "0x18", - "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES", - "PerPkg": "1", - "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.", - "Unit": "IRP" - }, - { - "BriefDescription": "No BL Egress Credit Stalls", - "EventCode": "0x19", - "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES", - "PerPkg": "1", - "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Read Requests", - "EventCode": "0xE", - "EventName": "UNC_I_TxR_DATA_INSERTS_NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Read Requests", - "EventCode": "0xF", - "EventName": "UNC_I_TxR_DATA_INSERTS_NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Request Queue Occupancy", - "EventCode": "0xD", - "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.", - "Unit": "IRP" - }, - { - "BriefDescription": "Number of uclks in domain", - "EventCode": "0x1", - "EventName": "UNC_R2_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Counts the number of uclks in the R2PCIe uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI0", - "EventCode": "0x2D", - "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI1", - "EventCode": "0x2D", - "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI0", - "EventCode": "0x2D", - "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI1", - "EventCode": "0x2D", - "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credit Acquired; DRS", - "EventCode": "0x33", - "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credit Acquired; NCB", - "EventCode": "0x33", - "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credit Acquired; NCS", - "EventCode": "0x33", - "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credits in Use; DRS", - "EventCode": "0x32", - "EventName": "UNC_R2_IIO_CREDITS_USED.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credits in Use; NCB", - "EventCode": "0x32", - "EventName": "UNC_R2_IIO_CREDITS_USED.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credits in Use; NCS", - "EventCode": "0x32", - "EventName": "UNC_R2_IIO_CREDITS_USED.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; All", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.ALL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xf", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Counterclockwise", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xc", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CCW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CCW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Clockwise", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x3", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Clockwise and Even", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "AK Ingress Bounced; Dn", - "EventCode": "0x12", - "EventName": "UNC_R2_RING_AK_BOUNCES.DN", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "AK Ingress Bounced; Up", - "EventCode": "0x12", - "EventName": "UNC_R2_RING_AK_BOUNCES.UP", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; All", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.ALL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xf", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Counterclockwise", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xc", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CCW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CCW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Clockwise", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x3", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Clockwise and Even", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; All", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.ALL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xf", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Counterclockwise", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xc", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CCW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CCW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Clockwise", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x3", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Clockwise and Even", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 IV Ring in Use; Any", - "EventCode": "0xA", - "EventName": "UNC_R2_RING_IV_USED.ANY", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", - "UMask": "0xf", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 IV Ring in Use; Counterclockwise", - "EventCode": "0xA", - "EventName": "UNC_R2_RING_IV_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", - "UMask": "0xc", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 IV Ring in Use; Clockwise", - "EventCode": "0xA", - "EventName": "UNC_R2_RING_IV_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", - "UMask": "0x3", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; NCB", - "EventCode": "0x10", - "EventName": "UNC_R2_RxR_CYCLES_NE.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; NCS", - "EventCode": "0x10", - "EventName": "UNC_R2_RxR_CYCLES_NE.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Ingress Allocations; NCB", - "EventCode": "0x11", - "EventName": "UNC_R2_RxR_INSERTS.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Ingress Allocations; NCS", - "EventCode": "0x11", - "EventName": "UNC_R2_RxR_INSERTS.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Ingress Occupancy Accumulator; DRS", - "EventCode": "0x13", - "EventName": "UNC_R2_RxR_OCCUPANCY.DRS", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "SBo0 Credits Acquired; For AD Ring", - "EventCode": "0x28", - "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.AD", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "SBo0 Credits Acquired; For BL Ring", - "EventCode": "0x28", - "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.BL", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "SBo0 Credits Occupancy; For AD Ring", - "EventCode": "0x2A", - "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.AD", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "SBo0 Credits Occupancy; For BL Ring", - "EventCode": "0x2A", - "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.BL", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring", - "EventCode": "0x2C", - "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD", - "PerPkg": "1", - "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring", - "EventCode": "0x2C", - "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL", - "PerPkg": "1", - "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring", - "EventCode": "0x2C", - "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD", - "PerPkg": "1", - "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring", - "EventCode": "0x2C", - "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL", - "PerPkg": "1", - "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Full; AD", - "EventCode": "0x25", - "EventName": "UNC_R2_TxR_CYCLES_FULL.AD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AD Egress Queue", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Full; AK", - "EventCode": "0x25", - "EventName": "UNC_R2_TxR_CYCLES_FULL.AK", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AK Egress Queue", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Full; BL", - "EventCode": "0x25", - "EventName": "UNC_R2_TxR_CYCLES_FULL.BL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; BL Egress Queue", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Not Empty; AD", - "EventCode": "0x23", - "EventName": "UNC_R2_TxR_CYCLES_NE.AD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AD Egress Queue", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Not Empty; AK", - "EventCode": "0x23", - "EventName": "UNC_R2_TxR_CYCLES_NE.AK", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AK Egress Queue", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Not Empty; BL", - "EventCode": "0x23", - "EventName": "UNC_R2_TxR_CYCLES_NE.BL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; BL Egress Queue", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress CCW NACK; AD CCW", - "EventCode": "0x26", - "EventName": "UNC_R2_TxR_NACK_CW.DN_AD", - "PerPkg": "1", - "PublicDescription": "AD CounterClockwise Egress Queue", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress CCW NACK; AK CCW", - "EventCode": "0x26", - "EventName": "UNC_R2_TxR_NACK_CW.DN_AK", - "PerPkg": "1", - "PublicDescription": "AK CounterClockwise Egress Queue", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress CCW NACK; BL CCW", - "EventCode": "0x26", - "EventName": "UNC_R2_TxR_NACK_CW.DN_BL", - "PerPkg": "1", - "PublicDescription": "BL CounterClockwise Egress Queue", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress CCW NACK; AK CCW", - "EventCode": "0x26", - "EventName": "UNC_R2_TxR_NACK_CW.UP_AD", - "PerPkg": "1", - "PublicDescription": "BL CounterClockwise Egress Queue", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress CCW NACK; BL CW", - "EventCode": "0x26", - "EventName": "UNC_R2_TxR_NACK_CW.UP_AK", - "PerPkg": "1", - "PublicDescription": "AD Clockwise Egress Queue", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress CCW NACK; BL CCW", - "EventCode": "0x26", - "EventName": "UNC_R2_TxR_NACK_CW.UP_BL", - "PerPkg": "1", - "PublicDescription": "AD CounterClockwise Egress Queue", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "VLW Received", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", - "PerPkg": "1", - "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x8", - "Unit": "UBOX" - }, - { - "BriefDescription": "Filter Match", - "EventCode": "0x41", - "EventName": "UNC_U_FILTER_MATCH.DISABLE", - "PerPkg": "1", - "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "Filter Match", - "EventCode": "0x41", - "EventName": "UNC_U_FILTER_MATCH.ENABLE", - "PerPkg": "1", - "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "Filter Match", - "EventCode": "0x41", - "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE", - "PerPkg": "1", - "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x8", - "Unit": "UBOX" - }, - { - "BriefDescription": "Filter Match", - "EventCode": "0x41", - "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE", - "PerPkg": "1", - "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x4", - "Unit": "UBOX" - }, - { - "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", - "EventCode": "0x45", - "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", - "PerPkg": "1", - "PublicDescription": "PHOLD cycles. Filter from source CoreID.", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "RACU Request", - "EventCode": "0x46", - "EventName": "UNC_U_RACU_REQUESTS", - "PerPkg": "1", - "PublicDescription": "Number outstanding register requests within message channel tracker", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Correctable Machine Check", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.CMC", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores", - "UMask": "0x10", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Livelock", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.LIVELOCK", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", - "UMask": "0x4", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; LTError", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.LTERROR", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", - "UMask": "0x8", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Monitor T0", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Monitor T1", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Other", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.OTHER", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores; PREQ, PSMI, P2U, Thermal, PCUSMI, PMI", - "UMask": "0x80", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Trap", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.TRAP", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores", - "UMask": "0x40", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.UMC", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores", - "UMask": "0x20", - "Unit": "UBOX" - } -] -- cgit v1.2.3-58-ga151 From c9f485c63d9332d4bc09e2d688613b231f0aa754 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 13 Apr 2023 06:29:35 -0700 Subject: perf vendor events intel: Fix uncore topics for broadwellx Remove 'uncore-other' topic classification, move to cache, interconnect and io. Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Edward Baker Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: http://lore.kernel.org/lkml/20230413132949.3487664-8-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/x86/broadwellx/uncore-cache.json | 358 +- .../arch/x86/broadwellx/uncore-interconnect.json | 4297 ++++++++++++++++---- .../pmu-events/arch/x86/broadwellx/uncore-io.json | 555 +++ .../arch/x86/broadwellx/uncore-other.json | 3242 --------------- 4 files changed, 4226 insertions(+), 4226 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/broadwellx/uncore-io.json delete mode 100644 tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json index f794d2992323..400d784d1457 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json @@ -8,7 +8,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode", @@ -19,7 +19,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode", @@ -30,7 +30,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "MMIO reads. Derived from unc_c_tor_inserts.miss_opcode", @@ -41,7 +41,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "MMIO writes. Derived from unc_c_tor_inserts.miss_opcode", @@ -52,7 +52,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opcode", @@ -63,7 +63,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode", @@ -74,7 +74,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_opcode", @@ -85,7 +85,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode", @@ -96,7 +96,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.miss_opcode", @@ -107,7 +107,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L2 demand and L2 prefetch code references to LLC. Derived from unc_c_tor_inserts.opcode", @@ -118,7 +118,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode", @@ -128,7 +128,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "PCIe read current. Derived from unc_c_tor_inserts.opcode", @@ -139,7 +139,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "PCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode", @@ -150,7 +150,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode", @@ -161,7 +161,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode", @@ -172,20 +172,20 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Bounce Control", "EventCode": "0xA", "EventName": "UNC_C_BOUNCE_CONTROL", "PerPkg": "1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Uncore Clocks", "EventName": "UNC_C_CLOCKTICKS", "PerPkg": "1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Counter 0 Occupancy", @@ -193,7 +193,7 @@ "EventName": "UNC_C_COUNTER0_OCCUPANCY", "PerPkg": "1", "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "FaST wire asserted", @@ -201,7 +201,7 @@ "EventName": "UNC_C_FAST_ASSERTED", "PerPkg": "1", "PublicDescription": "Counts the number of cycles either the local distress or incoming distress signals are asserted. Incoming distress includes both up and dn.", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)", @@ -212,7 +212,7 @@ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.", "ScaleUnit": "64Bytes", "UMask": "0x11", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; Data Read Request", @@ -221,7 +221,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; Lookups that Match NID", @@ -230,7 +230,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x41", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; Any Read Request", @@ -239,7 +239,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions", "UMask": "0x21", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; External Snoop Request", @@ -248,7 +248,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ.", "UMask": "0x9", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; Write Requests", @@ -257,7 +257,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.", "UMask": "0x5", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized; Lines in E state", @@ -266,7 +266,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized", @@ -275,7 +275,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized; Lines in S State", @@ -284,7 +284,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized", @@ -293,7 +293,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "M line evictions from LLC (writebacks to memory)", @@ -303,7 +303,7 @@ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "ScaleUnit": "64Bytes", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized; Victimized Lines that Match NID", @@ -312,7 +312,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=0", @@ -321,7 +321,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc; Clean Victim with raw CV=0", @@ -330,7 +330,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc; RFO HitS", @@ -339,7 +339,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.; Number of times that an RFO hit in S state. This is useful for determining if it might be good for a workload to use RspIWB instead of RspSWB.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc; Silent Snoop Eviction", @@ -348,7 +348,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc", @@ -357,7 +357,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc; Write Combining Aliasing", @@ -366,7 +366,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LRU Queue; LRU Age 0", @@ -375,7 +375,7 @@ "PerPkg": "1", "PublicDescription": "How often age was set to 0", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LRU Queue; LRU Age 1", @@ -384,7 +384,7 @@ "PerPkg": "1", "PublicDescription": "How often age was set to 1", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LRU Queue; LRU Age 2", @@ -393,7 +393,7 @@ "PerPkg": "1", "PublicDescription": "How often age was set to 2", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LRU Queue; LRU Age 3", @@ -402,7 +402,7 @@ "PerPkg": "1", "PublicDescription": "How often age was set to 3", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LRU Queue; LRU Bits Decremented", @@ -411,7 +411,7 @@ "PerPkg": "1", "PublicDescription": "How often all LRU bits were decremented by 1", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LRU Queue; Non-0 Aged Victim", @@ -420,7 +420,7 @@ "PerPkg": "1", "PublicDescription": "How often we picked a victim that had a non-zero age", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; All", @@ -429,7 +429,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0xf", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Down", @@ -438,7 +438,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX-- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0xc", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Down and Even", @@ -447,7 +447,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Down and Odd", @@ -456,7 +456,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Up", @@ -465,7 +465,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Up and Even", @@ -474,7 +474,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Up and Odd", @@ -483,7 +483,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; All", @@ -492,7 +492,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0xf", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Down", @@ -501,7 +501,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0xc", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Down and Even", @@ -510,7 +510,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Down and Odd", @@ -519,7 +519,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Up", @@ -528,7 +528,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Up and Even", @@ -537,7 +537,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Up and Odd", @@ -546,7 +546,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Down", @@ -555,7 +555,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0xf", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Down", @@ -564,7 +564,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0xc", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Down and Even", @@ -573,7 +573,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Down and Odd", @@ -582,7 +582,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Up", @@ -591,7 +591,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Up and Even", @@ -600,7 +600,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Up and Odd", @@ -609,7 +609,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of LLC responses that bounced on the Ring.; AD", @@ -617,7 +617,7 @@ "EventName": "UNC_C_RING_BOUNCES.AD", "PerPkg": "1", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of LLC responses that bounced on the Ring.; AK", @@ -625,7 +625,7 @@ "EventName": "UNC_C_RING_BOUNCES.AK", "PerPkg": "1", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of LLC responses that bounced on the Ring.; BL", @@ -633,7 +633,7 @@ "EventName": "UNC_C_RING_BOUNCES.BL", "PerPkg": "1", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.", @@ -641,7 +641,7 @@ "EventName": "UNC_C_RING_BOUNCES.IV", "PerPkg": "1", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Any", @@ -650,7 +650,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity", "UMask": "0xf", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Any", @@ -659,7 +659,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity", "UMask": "0xc", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Down", @@ -668,7 +668,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters for Down polarity", "UMask": "0xcc", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Any", @@ -677,7 +677,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in BDX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD", @@ -685,7 +685,7 @@ "EventName": "UNC_C_RING_SINK_STARVED.AD", "PerPkg": "1", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK", @@ -693,7 +693,7 @@ "EventName": "UNC_C_RING_SINK_STARVED.AK", "PerPkg": "1", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL", @@ -701,7 +701,7 @@ "EventName": "UNC_C_RING_SINK_STARVED.BL", "PerPkg": "1", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "IV", @@ -709,14 +709,14 @@ "EventName": "UNC_C_RING_SINK_STARVED.IV", "PerPkg": "1", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic.", "EventCode": "0x7", "EventName": "UNC_C_RING_SRC_THRTL", "PerPkg": "1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ", @@ -725,7 +725,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally startved and therefore we are blocking the IRQ.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ", @@ -734,7 +734,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IRQ is externally starved and therefore we are blocking the IPQ.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID", @@ -743,7 +743,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; Number of times that the ISMQ Bid.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; PRQ", @@ -752,7 +752,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Allocations; IPQ", @@ -761,7 +761,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Allocations; IRQ", @@ -770,7 +770,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Allocations; IRQ Rejected", @@ -779,7 +779,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Allocations; PRQ", @@ -788,7 +788,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Allocations; PRQ", @@ -797,7 +797,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Internal Starvation Cycles; IPQ", @@ -806,7 +806,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IPQ in Internal Starvation.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Internal Starvation Cycles; IRQ", @@ -815,7 +815,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IRQ in Internal Starvation.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ", @@ -824,7 +824,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the ISMQ in Internal Starvation.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Internal Starvation Cycles; PRQ", @@ -833,7 +833,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; Address Conflict", @@ -842,7 +842,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from an address conflicts. Address conflicts out of the IPQ should be rare. They will generally only occur if two different sockets are sending requests to the same address at the same time. This is a true conflict case, unlike the IPQ Address Conflict which is commonly caused by prefetching characteristics.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; Any Reject", @@ -851,7 +851,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject. TOR rejects from the IPQ can be caused by the Egress being full or Address Conflicts.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; No Egress Credits", @@ -860,7 +860,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from the Egress being full. IPQ requests make use of the AD Egress for regular responses, the BL egress to forward data, and the AK egress to return credits.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; No QPI Credits", @@ -869,7 +869,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; No AD Sbo Credits", @@ -878,7 +878,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; Target Node Filter", @@ -887,7 +887,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; Address Conflict", @@ -896,7 +896,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the IRQ was retried because of an address match in the TOR. In order to maintain coherency, requests to the same address are not allowed to pass each other up in the Cbo. Therefore, if there is an outstanding request to a given address, one cannot issue another request to that address until it is complete. This comes up most commonly with prefetches. Outstanding prefetches occasionally will not complete their memory fetch and a demand request to the same address will then sit in the IRQ and get retried until the prefetch fills the data into the LLC. Therefore, it will not be uncommon to see this case in high bandwidth streaming workloads when the LLC Prefetcher in the core is enabled.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; Any Reject", @@ -905,7 +905,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of IRQ retries that occur. Requests from the IRQ are retried if they are rejected from the TOR pipeline for a variety of reasons. Some of the most common reasons include if the Egress is full, there are no RTIDs, or there is a Physical Address match to another outstanding request.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No Egress Credits", @@ -914,7 +914,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the IRQ was retried because it failed to acquire an entry in the Egress. The egress is the buffer that queues up for allocating onto the ring. IRQ requests can make use of all four rings and all four Egresses. If any of the queues that a given request needs to make use of are full, the request will be retried.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits", @@ -923,7 +923,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO. There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects", @@ -932,7 +932,7 @@ "PerPkg": "1", "PublicDescription": "Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No QPI Credits", @@ -941,7 +941,7 @@ "PerPkg": "1", "PublicDescription": "Number of requests rejects because of lack of QPI Ingress credits. These credits are required in order to send transactions to the QPI agent. Please see the QPI_IGR_CREDITS events for more information.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No RTIDs", @@ -950,7 +950,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that requests from the IRQ were retried because there were no RTIDs available. RTIDs are required after a request misses the LLC and needs to send snoops and/or requests to memory. If there are no RTIDs available, requests will queue up in the IRQ and retry until one becomes available. Note that there are multiple RTID pools for the different sockets. There may be cases where the local RTIDs are all used, but requests destined for remote memory can still acquire an RTID because there are remote RTIDs available. This event does not provide any filtering for this case.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No AD Sbo Credits", @@ -959,7 +959,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No BL Sbo Credits", @@ -968,7 +968,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an BL packet to the Sbo.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; Target Node Filter", @@ -977,7 +977,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; Any Reject", @@ -986,7 +986,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the total number of times that a request from the ISMQ retried because of a TOR reject. ISMQ requests generally will not need to retry (or at least ISMQ retries are less common than IRQ retries). ISMQ requests will retry if they are not able to acquire a needed Egress credit to get onto the ring, or for cache evictions that need to acquire an RTID. Most ISMQ requests already have an RTID, so eviction retries will be less common here.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; No Egress Credits", @@ -995,7 +995,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by a lack of Egress credits. The egress is the buffer that queues up for allocating onto the ring. If any of the Egress queues that a given request needs to make use of are full, the request will be retried.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; No IIO Credits", @@ -1004,7 +1004,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO. There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries", @@ -1013,7 +1013,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; No QPI Credits", @@ -1022,7 +1022,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; No RTIDs", @@ -1031,7 +1031,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by no RTIDs. M-state cache evictions are serviced through the ISMQ, and must acquire an RTID in order to write back to memory. If no RTIDs are available, they will be retried.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries", @@ -1040,7 +1040,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.", "UMask": "0x80", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Request Queue Rejects; No AD Sbo Credits", @@ -1049,7 +1049,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an AD packet to the Sbo.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Request Queue Rejects; No BL Sbo Credits", @@ -1058,7 +1058,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an BL packet to the Sbo.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Request Queue Rejects; Target Node Filter", @@ -1067,7 +1067,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the ISMQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Occupancy; IPQ", @@ -1076,7 +1076,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Occupancy; IRQ", @@ -1085,7 +1085,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Occupancy; IRQ Rejected", @@ -1094,7 +1094,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Occupancy; PRQ Rejects", @@ -1103,7 +1103,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "SBo Credits Acquired; For AD Ring", @@ -1112,7 +1112,7 @@ "PerPkg": "1", "PublicDescription": "Number of Sbo credits acquired in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "SBo Credits Acquired; For BL Ring", @@ -1121,7 +1121,7 @@ "PerPkg": "1", "PublicDescription": "Number of Sbo credits acquired in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "SBo Credits Occupancy; For AD Ring", @@ -1130,7 +1130,7 @@ "PerPkg": "1", "PublicDescription": "Number of Sbo credits in use in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "SBo Credits Occupancy; For BL Ring", @@ -1139,7 +1139,7 @@ "PerPkg": "1", "PublicDescription": "Number of Sbo credits in use in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; All", @@ -1148,7 +1148,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Evictions", @@ -1157,7 +1157,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Eviction transactions inserted into the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Local Memory", @@ -1166,7 +1166,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x28", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched", @@ -1175,7 +1175,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisfied by an opcode, inserted into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x21", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Misses to Local Memory", @@ -1184,7 +1184,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x2a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode Matched", @@ -1193,7 +1193,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisfied by an opcode, inserted into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x23", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Miss Opcode Match", @@ -1202,7 +1202,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Misses to Remote Memory", @@ -1211,7 +1211,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x8a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode Matched", @@ -1220,7 +1220,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisfied by an opcode, inserted into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x83", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID Matched", @@ -1229,7 +1229,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x48", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID Matched Evictions", @@ -1238,7 +1238,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction transactions inserted into the TOR.", "UMask": "0x44", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID Matched Miss All", @@ -1247,7 +1247,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.", "UMask": "0x4a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss", @@ -1256,7 +1256,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode.", "UMask": "0x43", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID and Opcode Matched", @@ -1265,7 +1265,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode.", "UMask": "0x41", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID Matched Writebacks", @@ -1274,7 +1274,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transactions inserted into the TOR.", "UMask": "0x50", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Opcode Match", @@ -1283,7 +1283,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Remote Memory", @@ -1292,7 +1292,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x88", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched", @@ -1301,7 +1301,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisfied by an opcode, inserted into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x81", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Writebacks", @@ -1310,7 +1310,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Write transactions inserted into the TOR. This does not include RFO, but actual operations that contain data being sent from the core.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Any", @@ -1319,7 +1319,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All valid TOR entries. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Evictions", @@ -1328,7 +1328,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding eviction transactions in the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode", @@ -1338,7 +1338,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO.", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy", @@ -1347,7 +1347,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x28", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched", @@ -1356,7 +1356,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisfied by an opcode, in the TOR that are satisfied by locally HOMed memory.", "UMask": "0x21", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Miss All", @@ -1365,7 +1365,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding miss requests in the TOR. 'Miss' means the allocation requires an RTID. This generally means that the request was sent to memory or MMIO.", "UMask": "0xa", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy", @@ -1374,7 +1374,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x2a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcode Matched", @@ -1383,7 +1383,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisfied by an opcode, in the TOR that are satisfied by locally HOMed memory.", "UMask": "0x23", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Miss Opcode Match", @@ -1392,7 +1392,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO.", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy", @@ -1401,7 +1401,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x8a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opcode Matched", @@ -1410,7 +1410,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisfied by an opcode, in the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x83", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID Matched", @@ -1419,7 +1419,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of NID matched outstanding requests in the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x48", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID Matched Evictions", @@ -1428,7 +1428,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding NID matched eviction transactions in the TOR .", "UMask": "0x44", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID Matched", @@ -1437,7 +1437,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID.", "UMask": "0x4a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss", @@ -1446,7 +1446,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID and an opcode.", "UMask": "0x43", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID and Opcode Matched", @@ -1455,7 +1455,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match a NID and an opcode.", "UMask": "0x41", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID Matched Writebacks", @@ -1464,7 +1464,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); NID matched write transactions int the TOR.", "UMask": "0x50", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Opcode Match", @@ -1473,7 +1473,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc).", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy", @@ -1482,7 +1482,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x88", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Remote Memory - Opcode Matched", @@ -1491,7 +1491,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisfied by an opcode, in the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x81", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Writebacks", @@ -1500,7 +1500,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Write transactions in the TOR. This does not include RFO, but actual operations that contain data being sent from the core.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Onto AD Ring", @@ -1508,7 +1508,7 @@ "EventName": "UNC_C_TxR_ADS_USED.AD", "PerPkg": "1", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Onto AK Ring", @@ -1516,7 +1516,7 @@ "EventName": "UNC_C_TxR_ADS_USED.AK", "PerPkg": "1", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Onto BL Ring", @@ -1524,7 +1524,7 @@ "EventName": "UNC_C_TxR_ADS_USED.BL", "PerPkg": "1", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; AD - Cachebo", @@ -1533,7 +1533,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; AD - Corebo", @@ -1542,7 +1542,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AD ring. This is commonly used for outbound requests.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; AK - Cachebo", @@ -1551,7 +1551,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AK ring. This is commonly used for credit returns and GO responses.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; AK - Corebo", @@ -1560,7 +1560,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AK ring. This is commonly used for snoop responses coming from the core and destined for a Cachebo.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; BL - Cacheno", @@ -1569,7 +1569,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the BL ring. This is commonly used to send data from the cache to various destinations.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; BL - Corebo", @@ -1578,7 +1578,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring. This is commonly used for transferring writeback data to the cache.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; IV - Cachebo", @@ -1587,7 +1587,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the IV ring. This is commonly used for snoops to the cores.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Injection Starvation; Onto AD Ring (to core)", @@ -1596,7 +1596,7 @@ "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the core AD egress spent in starvation", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Injection Starvation; Onto AK Ring", @@ -1605,7 +1605,7 @@ "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both AK egresses spent in starvation", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Injection Starvation; Onto BL Ring", @@ -1614,7 +1614,7 @@ "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both BL egresses spent in starvation", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Injection Starvation; Onto IV Ring", @@ -1623,7 +1623,7 @@ "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the cachebo IV egress spent in starvation", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BT Cycles Not Empty", diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json index 2819c6621089..e61a23f68899 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json @@ -6,7 +6,7 @@ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets.", "ScaleUnit": "8Bytes", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data", @@ -15,1317 +15,4004 @@ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets.", "ScaleUnit": "8Bytes", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { - "BriefDescription": "Number of qfclks", - "EventCode": "0x14", - "EventName": "UNC_Q_CLOCKTICKS", + "BriefDescription": "Total Write Cache Occupancy; Any Source", + "EventCode": "0x12", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", "PerPkg": "1", - "PublicDescription": "Counts the number of clocks in the QPI LL. This clock runs at 1/4th the GT/s speed of the QPI link. For example, a 4GT/s link will have qfclk or 1GHz. BDX does not support dynamic link speeds, so this frequency is fixed.", - "Unit": "QPI LL" + "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.", + "UMask": "0x1", + "Unit": "IRP" }, { - "BriefDescription": "Count of CTO Events", - "EventCode": "0x38", - "EventName": "UNC_Q_CTO_COUNT", + "BriefDescription": "Total Write Cache Occupancy; Select Source", + "EventCode": "0x12", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE", "PerPkg": "1", - "PublicDescription": "Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots. If both slots trigger in a given cycle, the event will increment by 2. You can use edge detect to count the number of cases when both events triggered.", - "Unit": "QPI LL" + "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time.", + "UMask": "0x2", + "Unit": "IRP" }, { - "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress Credits", + "BriefDescription": "Clocks in the IRP", + "EventName": "UNC_I_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Number of clocks in the IRP.", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; CLFlush", "EventCode": "0x13", - "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS", + "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits. Had there been enough credits, the spawn would have worked as the RBT bit was set and the RBT tag matched.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x80", + "Unit": "IRP" }, { - "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss", + "BriefDescription": "Coherent Ops; CRd", "EventCode": "0x13", - "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS", + "EventName": "UNC_I_COHERENT_OPS.CRD", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and there weren't enough Egress credits. The valid bit was set.", - "UMask": "0x20", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x2", + "Unit": "IRP" }, { - "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Invalid", + "BriefDescription": "Coherent Ops; DRd", "EventCode": "0x13", - "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT", + "EventName": "UNC_I_COHERENT_OPS.DRD", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits AND the RBT bit was not set, but the RBT tag matched.", - "UMask": "0x8", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x4", + "Unit": "IRP" }, { - "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid", + "BriefDescription": "Coherent Ops; PCIDCAHin5t", "EventCode": "0x13", - "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS", + "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match, the valid bit was not set and there weren't enough Egress credits.", - "UMask": "0x80", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x20", + "Unit": "IRP" }, { - "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss", + "BriefDescription": "Coherent Ops; PCIRdCur", "EventCode": "0x13", - "EventName": "UNC_Q_DIRECT2CORE.FAILURE_MISS", + "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match although the valid bit was set and there were enough Egress credits.", - "UMask": "0x10", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x1", + "Unit": "IRP" }, { - "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Invalid", + "BriefDescription": "Coherent Ops; PCIItoM", "EventCode": "0x13", - "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT", + "EventName": "UNC_I_COHERENT_OPS.PCITOM", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the route-back table (RBT) specified that the transaction should not trigger a direct2core transaction. This is common for IO transactions. There were enough Egress credits and the RBT tag matched but the valid bit was not set.", - "UMask": "0x4", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x10", + "Unit": "IRP" }, { - "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss and Invalid", + "BriefDescription": "Coherent Ops; RFO", "EventCode": "0x13", - "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS", + "EventName": "UNC_I_COHERENT_OPS.RFO", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and the valid bit was not set although there were enough Egress credits.", - "UMask": "0x40", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x8", + "Unit": "IRP" }, { - "BriefDescription": "Direct 2 Core Spawning; Spawn Success", + "BriefDescription": "Coherent Ops; WbMtoI", "EventCode": "0x13", - "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT", + "EventName": "UNC_I_COHERENT_OPS.WBMTOI", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn was successful. There were sufficient credits, the RBT valid bit was set and there was an RBT tag match. The message was marked to spawn direct2core.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x40", + "Unit": "IRP" }, { - "BriefDescription": "Cycles in L1", - "EventCode": "0x12", - "EventName": "UNC_Q_L1_POWER_CYCLES", + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", "PerPkg": "1", - "PublicDescription": "Number of QPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a QPI link. Use edge detect to count the number of instances when the QPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.", - "Unit": "QPI LL" + "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary", + "UMask": "0x10", + "Unit": "IRP" }, { - "BriefDescription": "Cycles in L0p", - "EventCode": "0x10", - "EventName": "UNC_Q_RxL0P_POWER_CYCLES", + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.2ND_RD_INSERT", "PerPkg": "1", - "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.", - "Unit": "QPI LL" + "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary", + "UMask": "0x4", + "Unit": "IRP" }, { - "BriefDescription": "Cycles in L0", - "EventCode": "0xF", - "EventName": "UNC_Q_RxL0_POWER_CYCLES", + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.2ND_WR_INSERT", "PerPkg": "1", - "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", - "Unit": "QPI LL" + "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary", + "UMask": "0x8", + "Unit": "IRP" }, { - "BriefDescription": "Rx Flit Buffer Bypassed", - "EventCode": "0x9", - "EventName": "UNC_Q_RxL_BYPASSED", + "BriefDescription": "Misc Events - Set 0; Fastpath Rejects", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.FAST_REJ", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", - "Unit": "QPI LL" + "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", + "UMask": "0x2", + "Unit": "IRP" }, { - "BriefDescription": "CRC Errors Detected; LinkInit", - "EventCode": "0x3", - "EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT", + "BriefDescription": "Misc Events - Set 0; Fastpath Requests", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.FAST_REQ", "PerPkg": "1", - "PublicDescription": "Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during link initialization.", + "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Requests", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "IRP" }, { - "BriefDescription": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP", - "EventCode": "0x3", - "EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP", + "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.FAST_XFER", "PerPkg": "1", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary", + "UMask": "0x20", + "Unit": "IRP" }, { - "BriefDescription": "VN0 Credit Consumed; DRS", - "EventCode": "0x1E", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS", + "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.PF_ACK_HINT", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the DRS message class.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary", + "UMask": "0x40", + "Unit": "IRP" }, { - "BriefDescription": "VN0 Credit Consumed; HOM", - "EventCode": "0x1E", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM", + "BriefDescription": "Misc Events - Set 0; Prefetch TimeOut", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.PF_TIMEOUT", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the HOM message class.", - "UMask": "0x8", - "Unit": "QPI LL" + "PublicDescription": "Indicates the fetch for a previous prefetch wasn't accepted by the prefetch. This happens in the case of a prefetch TimeOut", + "UMask": "0x80", + "Unit": "IRP" }, { - "BriefDescription": "VN0 Credit Consumed; NCB", - "EventCode": "0x1E", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB", + "BriefDescription": "Misc Events - Set 1; Data Throttled", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.DATA_THROTTLE", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCB message class.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "IRP throttled switch data", + "UMask": "0x80", + "Unit": "IRP" }, { - "BriefDescription": "VN0 Credit Consumed; NCS", - "EventCode": "0x1E", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS", + "BriefDescription": "Misc Events - Set 1", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.LOST_FWD", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCS message class.", - "UMask": "0x4", - "Unit": "QPI LL" + "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed", + "UMask": "0x10", + "Unit": "IRP" }, { - "BriefDescription": "VN0 Credit Consumed; NDR", - "EventCode": "0x1E", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR", + "BriefDescription": "Misc Events - Set 1; Received Invalid", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NDR message class.", + "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state", "UMask": "0x20", - "Unit": "QPI LL" + "Unit": "IRP" }, { - "BriefDescription": "VN0 Credit Consumed; SNP", - "EventCode": "0x1E", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP", + "BriefDescription": "Misc Events - Set 1; Received Valid", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the SNP message class.", - "UMask": "0x10", - "Unit": "QPI LL" + "PublicDescription": "Secondary received a transfer that did have sufficient MESI state", + "UMask": "0x40", + "Unit": "IRP" }, { - "BriefDescription": "VN1 Credit Consumed; DRS", - "EventCode": "0x39", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS", + "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SLOW_E", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the DRS message class.", + "PublicDescription": "Secondary received a transfer that did have sufficient MESI state", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SLOW_I", + "PerPkg": "1", + "PublicDescription": "Snoop took cacheline ownership before write from data was committed.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "IRP" }, { - "BriefDescription": "VN1 Credit Consumed; HOM", - "EventCode": "0x39", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM", + "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SLOW_M", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the HOM message class.", + "PublicDescription": "Snoop took cacheline ownership before write from data was committed.", "UMask": "0x8", - "Unit": "QPI LL" + "Unit": "IRP" }, { - "BriefDescription": "VN1 Credit Consumed; NCB", - "EventCode": "0x39", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB", + "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SLOW_S", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCB message class.", + "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "IRP" }, { - "BriefDescription": "VN1 Credit Consumed; NCS", - "EventCode": "0x39", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS", + "BriefDescription": "AK Ingress Occupancy", + "EventCode": "0xA", + "EventName": "UNC_I_RxR_AK_INSERTS", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCS message class.", - "UMask": "0x4", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of allocations into the AK Ingress. This queue is where the IRP receives responses from R2PCIe (the ring).", + "Unit": "IRP" }, { - "BriefDescription": "VN1 Credit Consumed; NDR", - "EventCode": "0x39", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR", + "BriefDescription": "UNC_I_RxR_BL_DRS_CYCLES_FULL", + "EventCode": "0x4", + "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NDR message class.", - "UMask": "0x20", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" }, { - "BriefDescription": "VN1 Credit Consumed; SNP", - "EventCode": "0x39", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP", + "BriefDescription": "BL Ingress Occupancy - DRS", + "EventCode": "0x1", + "EventName": "UNC_I_RxR_BL_DRS_INSERTS", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the SNP message class.", - "UMask": "0x10", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" }, { - "BriefDescription": "VNA Credit Consumed", - "EventCode": "0x1D", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA", + "BriefDescription": "UNC_I_RxR_BL_DRS_OCCUPANCY", + "EventCode": "0x7", + "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", - "Unit": "QPI LL" + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty", - "EventCode": "0xA", - "EventName": "UNC_Q_RxL_CYCLES_NE", + "BriefDescription": "UNC_I_RxR_BL_NCB_CYCLES_FULL", + "EventCode": "0x5", + "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN0", - "EventCode": "0xF", - "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN0", + "BriefDescription": "BL Ingress Occupancy - NCB", + "EventCode": "0x2", + "EventName": "UNC_I_RxR_BL_NCB_INSERTS", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN1", - "EventCode": "0xF", - "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN1", + "BriefDescription": "UNC_I_RxR_BL_NCB_OCCUPANCY", + "EventCode": "0x8", + "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN0", - "EventCode": "0x12", - "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN0", + "BriefDescription": "UNC_I_RxR_BL_NCS_CYCLES_FULL", + "EventCode": "0x6", + "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN1", - "EventCode": "0x12", - "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN1", + "BriefDescription": "BL Ingress Occupancy - NCS", + "EventCode": "0x3", + "EventName": "UNC_I_RxR_BL_NCS_INSERTS", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN0", - "EventCode": "0x10", - "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN0", + "BriefDescription": "UNC_I_RxR_BL_NCS_OCCUPANCY", + "EventCode": "0x9", + "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN1", - "EventCode": "0x10", - "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN1", + "BriefDescription": "Snoop Responses; Hit E or S", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.HIT_ES", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Snoop Responses : Hit E or S", + "UMask": "0x4", + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN0", - "EventCode": "0x11", - "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN0", + "BriefDescription": "Snoop Responses; Hit I", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.HIT_I", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Snoop Responses : Hit I", + "UMask": "0x2", + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN1", - "EventCode": "0x11", - "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN1", + "BriefDescription": "Snoop Responses; Hit M", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.HIT_M", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Snoop Responses : Hit M", + "UMask": "0x8", + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN0", - "EventCode": "0x14", - "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN0", + "BriefDescription": "Snoop Responses; Miss", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.MISS", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only.", + "PublicDescription": "Snoop Responses : Miss", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN1", - "EventCode": "0x14", - "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN1", + "BriefDescription": "Snoop Responses; SnpCode", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.SNPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Snoop Responses : SnpCode", + "UMask": "0x10", + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN0", - "EventCode": "0x13", - "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN0", + "BriefDescription": "Snoop Responses; SnpData", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.SNPDATA", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Snoop Responses : SnpData", + "UMask": "0x20", + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN1", - "EventCode": "0x13", - "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN1", + "BriefDescription": "Snoop Responses; SnpInv", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.SNPINV", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Snoop Responses : SnpInv", + "UMask": "0x40", + "Unit": "IRP" }, { - "BriefDescription": "Flits Received - Group 0; Idle and Null Flits", + "BriefDescription": "Inbound Transaction Count; Atomic", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.ATOMIC", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Other", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.OTHER", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions.", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Read Prefetches", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.RD_PREF", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Reads", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.READS", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Writes", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.WRITES", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Write Prefetches", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of write prefetches.", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "No AD Egress Credit Stalls", + "EventCode": "0x18", + "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.", + "Unit": "IRP" + }, + { + "BriefDescription": "No BL Egress Credit Stalls", + "EventCode": "0x19", + "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "EventCode": "0xE", + "EventName": "UNC_I_TxR_DATA_INSERTS_NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "EventCode": "0xF", + "EventName": "UNC_I_TxR_DATA_INSERTS_NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Request Queue Occupancy", + "EventCode": "0xD", + "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.", + "Unit": "IRP" + }, + { + "BriefDescription": "Number of qfclks", + "EventCode": "0x14", + "EventName": "UNC_Q_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts the number of clocks in the QPI LL. This clock runs at 1/4th the GT/s speed of the QPI link. For example, a 4GT/s link will have qfclk or 1GHz. BDX does not support dynamic link speeds, so this frequency is fixed.", + "Unit": "QPI" + }, + { + "BriefDescription": "Count of CTO Events", + "EventCode": "0x38", + "EventName": "UNC_Q_CTO_COUNT", + "PerPkg": "1", + "PublicDescription": "Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots. If both slots trigger in a given cycle, the event will increment by 2. You can use edge detect to count the number of cases when both events triggered.", + "Unit": "QPI" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress Credits", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits. Had there been enough credits, the spawn would have worked as the RBT bit was set and the RBT tag matched.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and there weren't enough Egress credits. The valid bit was set.", + "UMask": "0x20", + "Unit": "QPI" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Invalid", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits AND the RBT bit was not set, but the RBT tag matched.", + "UMask": "0x8", + "Unit": "QPI" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match, the valid bit was not set and there weren't enough Egress credits.", + "UMask": "0x80", + "Unit": "QPI" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_MISS", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match although the valid bit was set and there were enough Egress credits.", + "UMask": "0x10", + "Unit": "QPI" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Invalid", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the route-back table (RBT) specified that the transaction should not trigger a direct2core transaction. This is common for IO transactions. There were enough Egress credits and the RBT tag matched but the valid bit was not set.", + "UMask": "0x4", + "Unit": "QPI" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss and Invalid", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and the valid bit was not set although there were enough Egress credits.", + "UMask": "0x40", + "Unit": "QPI" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Success", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn was successful. There were sufficient credits, the RBT valid bit was set and there was an RBT tag match. The message was marked to spawn direct2core.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Cycles in L1", + "EventCode": "0x12", + "EventName": "UNC_Q_L1_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of QPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a QPI link. Use edge detect to count the number of instances when the QPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.", + "Unit": "QPI" + }, + { + "BriefDescription": "Cycles in L0p", + "EventCode": "0x10", + "EventName": "UNC_Q_RxL0P_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.", + "Unit": "QPI" + }, + { + "BriefDescription": "Cycles in L0", + "EventCode": "0xF", + "EventName": "UNC_Q_RxL0_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Bypassed", + "EventCode": "0x9", + "EventName": "UNC_Q_RxL_BYPASSED", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "Unit": "QPI" + }, + { + "BriefDescription": "CRC Errors Detected; LinkInit", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT", + "PerPkg": "1", + "PublicDescription": "Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during link initialization.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "VN0 Credit Consumed; DRS", + "EventCode": "0x1E", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the DRS message class.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "VN0 Credit Consumed; HOM", + "EventCode": "0x1E", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the HOM message class.", + "UMask": "0x8", + "Unit": "QPI" + }, + { + "BriefDescription": "VN0 Credit Consumed; NCB", + "EventCode": "0x1E", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCB message class.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "VN0 Credit Consumed; NCS", + "EventCode": "0x1E", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCS message class.", + "UMask": "0x4", + "Unit": "QPI" + }, + { + "BriefDescription": "VN0 Credit Consumed; NDR", + "EventCode": "0x1E", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NDR message class.", + "UMask": "0x20", + "Unit": "QPI" + }, + { + "BriefDescription": "VN0 Credit Consumed; SNP", + "EventCode": "0x1E", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the SNP message class.", + "UMask": "0x10", + "Unit": "QPI" + }, + { + "BriefDescription": "VN1 Credit Consumed; DRS", + "EventCode": "0x39", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the DRS message class.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "VN1 Credit Consumed; HOM", + "EventCode": "0x39", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the HOM message class.", + "UMask": "0x8", + "Unit": "QPI" + }, + { + "BriefDescription": "VN1 Credit Consumed; NCB", + "EventCode": "0x39", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCB message class.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "VN1 Credit Consumed; NCS", + "EventCode": "0x39", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCS message class.", + "UMask": "0x4", + "Unit": "QPI" + }, + { + "BriefDescription": "VN1 Credit Consumed; NDR", + "EventCode": "0x39", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NDR message class.", + "UMask": "0x20", + "Unit": "QPI" + }, + { + "BriefDescription": "VN1 Credit Consumed; SNP", + "EventCode": "0x39", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the SNP message class.", + "UMask": "0x10", + "Unit": "QPI" + }, + { + "BriefDescription": "VNA Credit Consumed", + "EventCode": "0x1D", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty", + "EventCode": "0xA", + "EventName": "UNC_Q_RxL_CYCLES_NE", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN0", + "EventCode": "0xF", + "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN1", + "EventCode": "0xF", + "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN0", + "EventCode": "0x12", + "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN1", + "EventCode": "0x12", + "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN0", + "EventCode": "0x10", + "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN1", + "EventCode": "0x10", + "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN0", + "EventCode": "0x11", + "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN1", + "EventCode": "0x11", + "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN0", + "EventCode": "0x14", + "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN1", + "EventCode": "0x14", + "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN0", + "EventCode": "0x13", + "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN1", + "EventCode": "0x13", + "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 0; Idle and Null Flits", + "EventCode": "0x1", + "EventName": "UNC_Q_RxL_FLITS_G0.IDLE", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits received over QPI that do not hold protocol payload. When QPI is not in a power saving state, it continuously transmits flits across the link. When there are no protocol flits to send, it will send IDLE and NULL flits across. These flits sometimes do carry a payload, such as credit returns, but are generally not considered part of the QPI bandwidth.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data.", + "UMask": "0x18", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 1; DRS Data Flits", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).", + "UMask": "0x8", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 1; DRS Header Flits", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.", + "UMask": "0x10", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 1; HOM Flits", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits received over QPI on the home channel.", + "UMask": "0x6", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits received over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.", + "UMask": "0x4", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 1; HOM Request Flits", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request received over QPI on the home channel. This basically counts the number of remote memory requests received over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 1; SNP Flits", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits received over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are received on the home channel.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.", + "UMask": "0xc", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Coherent data Rx Flits", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers.", + "UMask": "0x4", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Coherent non-data Rx Flits", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.", + "UMask": "0x8", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits received over QPI. This includes extended headers.", + "UMask": "0x10", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations", + "EventCode": "0x8", + "EventName": "UNC_Q_RxL_INSERTS", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN0", + "EventCode": "0x9", + "EventName": "UNC_Q_RxL_INSERTS_DRS.VN0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN1", + "EventCode": "0x9", + "EventName": "UNC_Q_RxL_INSERTS_DRS.VN1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN0", + "EventCode": "0xC", + "EventName": "UNC_Q_RxL_INSERTS_HOM.VN0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN1", + "EventCode": "0xC", + "EventName": "UNC_Q_RxL_INSERTS_HOM.VN1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN0", + "EventCode": "0xA", + "EventName": "UNC_Q_RxL_INSERTS_NCB.VN0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN1", + "EventCode": "0xA", + "EventName": "UNC_Q_RxL_INSERTS_NCB.VN1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN0", + "EventCode": "0xB", + "EventName": "UNC_Q_RxL_INSERTS_NCS.VN0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN1", + "EventCode": "0xB", + "EventName": "UNC_Q_RxL_INSERTS_NCS.VN1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN0", + "EventCode": "0xE", + "EventName": "UNC_Q_RxL_INSERTS_NDR.VN0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN1", + "EventCode": "0xE", + "EventName": "UNC_Q_RxL_INSERTS_NDR.VN1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN0", + "EventCode": "0xD", + "EventName": "UNC_Q_RxL_INSERTS_SNP.VN0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN1", + "EventCode": "0xD", + "EventName": "UNC_Q_RxL_INSERTS_SNP.VN1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets", + "EventCode": "0xB", + "EventName": "UNC_Q_RxL_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - DRS; for VN0", + "EventCode": "0x15", + "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN0", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - DRS; for VN1", + "EventCode": "0x15", + "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - HOM; for VN0", + "EventCode": "0x18", + "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN0", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - HOM; for VN1", + "EventCode": "0x18", + "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - NCB; for VN0", + "EventCode": "0x16", + "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN0", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - NCB; for VN1", + "EventCode": "0x16", + "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - NCS; for VN0", + "EventCode": "0x17", + "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN0", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - NCS; for VN1", + "EventCode": "0x17", + "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - NDR; for VN0", + "EventCode": "0x1A", + "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN0", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - NDR; for VN1", + "EventCode": "0x1A", + "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - SNP; for VN0", + "EventCode": "0x19", + "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN0", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - SNP; for VN1", + "EventCode": "0x19", + "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - HOM", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_DRS", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - DRS", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_HOM", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x8", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - SNP", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCB", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NDR", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCS", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x4", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCS", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NDR", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x20", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCB", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_SNP", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x10", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; Egress Credits", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet because there were insufficient BGF credits. For details on a message class granularity, use the Egress Credit Occupancy events.", + "UMask": "0x40", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; GV", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.GV", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled because a GV transition (frequency transition) was taking place.", + "UMask": "0x80", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - HOM", + "EventCode": "0x3A", + "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_DRS", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - DRS", + "EventCode": "0x3A", + "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_HOM", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x8", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - SNP", + "EventCode": "0x3A", + "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCB", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NDR", + "EventCode": "0x3A", + "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCS", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x4", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCS", + "EventCode": "0x3A", + "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NDR", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x20", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCB", + "EventCode": "0x3A", + "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_SNP", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x10", + "Unit": "QPI" + }, + { + "BriefDescription": "Cycles in L0p", + "EventCode": "0xD", + "EventName": "UNC_Q_TxL0P_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.", + "Unit": "QPI" + }, + { + "BriefDescription": "Cycles in L0", + "EventCode": "0xC", + "EventName": "UNC_Q_TxL0_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", + "Unit": "QPI" + }, + { + "BriefDescription": "Tx Flit Buffer Bypassed", + "EventCode": "0x5", + "EventName": "UNC_Q_TxL_BYPASSED", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.", + "Unit": "QPI" + }, + { + "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full", + "EventCode": "0x2", + "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL", + "PerPkg": "1", + "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is almost full, we block some but not all packets.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full", + "EventCode": "0x2", + "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL", + "PerPkg": "1", + "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is totally full, we are not allowed to send any packets.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Tx Flit Buffer Cycles not Empty", + "EventCode": "0x6", + "EventName": "UNC_Q_TxL_CYCLES_NE", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits", + "EventName": "UNC_Q_TxL_FLITS_G0.DATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits", + "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets.", + "UMask": "0x4", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)", + "EventName": "UNC_Q_TxL_FLITS_G1.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency.", + "UMask": "0x18", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits", + "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).", + "UMask": "0x8", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits", + "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.", + "UMask": "0x10", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 1; HOM Flits", + "EventName": "UNC_Q_TxL_FLITS_G1.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits transmitted over QPI on the home channel.", + "UMask": "0x6", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits", + "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits transmitted over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.", + "UMask": "0x4", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits", + "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request transmitted over QPI on the home channel. This basically counts the number of remote memory requests transmitted over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 1; SNP Flits", + "EventName": "UNC_Q_TxL_FLITS_G1.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits transmitted over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are transmitted on the home channel.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.", + "UMask": "0xc", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Coherent data Tx Flits", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers.", + "UMask": "0x4", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Coherent non-data Tx Flits", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.", + "UMask": "0x8", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits transmitted over QPI. This includes extended headers.", + "UMask": "0x10", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Tx Flit Buffer Allocations", + "EventCode": "0x4", + "EventName": "UNC_Q_TxL_INSERTS", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Tx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", + "Unit": "QPI" + }, + { + "BriefDescription": "Tx Flit Buffer Occupancy", + "EventCode": "0x7", + "EventName": "UNC_Q_TxL_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of flits in the TxQ. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN0", + "EventCode": "0x26", + "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0", + "PerPkg": "1", + "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN1", + "EventCode": "0x26", + "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1", + "PerPkg": "1", + "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN0", + "EventCode": "0x22", + "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN1", + "EventCode": "0x22", + "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0", + "EventCode": "0x28", + "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0", + "PerPkg": "1", + "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1", + "EventCode": "0x28", + "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1", + "PerPkg": "1", + "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0", + "EventCode": "0x24", + "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1", + "EventCode": "0x24", + "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN0", + "EventCode": "0x27", + "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0", + "PerPkg": "1", + "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN1", + "EventCode": "0x27", + "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1", + "PerPkg": "1", + "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN0", + "EventCode": "0x23", + "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for Snoop messages on AD.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN1", + "EventCode": "0x23", + "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for Snoop messages on AD.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR", + "EventCode": "0x29", + "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR", + "EventCode": "0x25", + "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. Local NDR message class to AK Egress.", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN0", + "EventCode": "0x2A", + "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN1", + "EventCode": "0x2A", + "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for Shared VN", + "EventCode": "0x2A", + "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.", + "UMask": "0x4", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN0", + "EventCode": "0x1F", + "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN1", + "EventCode": "0x1F", + "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for Shared VN", + "EventCode": "0x1F", + "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.", + "UMask": "0x4", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN0", + "EventCode": "0x2B", + "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN1", + "EventCode": "0x2B", + "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN0", + "EventCode": "0x20", + "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN1", + "EventCode": "0x20", + "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN0", + "EventCode": "0x2C", + "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN1", + "EventCode": "0x2C", + "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN0", + "EventCode": "0x21", + "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN1", + "EventCode": "0x21", + "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "VNA Credits Returned", + "EventCode": "0x1C", + "EventName": "UNC_Q_VNA_CREDIT_RETURNS", + "PerPkg": "1", + "PublicDescription": "Number of VNA credits returned.", + "Unit": "QPI" + }, + { + "BriefDescription": "VNA Credits Pending Return - Occupancy", + "EventCode": "0x1B", + "EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.", + "Unit": "QPI" + }, + { + "BriefDescription": "Number of uclks in domain", "EventCode": "0x1", - "EventName": "UNC_Q_RxL_FLITS_G0.IDLE", + "EventName": "UNC_R3_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts the number of uclks in the QPI uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles.", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x1F", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 10", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x1F", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 11", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x1F", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 12", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x1F", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 13", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x1F", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14_16", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 14&16", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x1F", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 8", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x1F", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 9", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x1F", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO_15_17", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 15&17", + "UMask": "0x80", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x22", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 0", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x22", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x22", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 2", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x22", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 3", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x22", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 4", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x22", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 5", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x22", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 6", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x22", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 7", + "UMask": "0x80", + "Unit": "R3QPI" + }, + { + "BriefDescription": "HA/R2 AD Credits Empty", + "EventCode": "0x2D", + "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0", + "PerPkg": "1", + "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA0", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "HA/R2 AD Credits Empty", + "EventCode": "0x2D", + "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1", + "PerPkg": "1", + "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "HA/R2 AD Credits Empty", + "EventCode": "0x2D", + "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB", + "PerPkg": "1", + "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCB Messages", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "HA/R2 AD Credits Empty", + "EventCode": "0x2D", + "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS", + "PerPkg": "1", + "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCS Messages", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "IOT Backpressure", + "EventCode": "0xB", + "EventName": "UNC_R3_IOT_BACKPRESSURE.HUB", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "IOT Backpressure", + "EventCode": "0xB", + "EventName": "UNC_R3_IOT_BACKPRESSURE.SAT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "IOT Common Trigger Sequencer - Hi", + "EventCode": "0xD", + "EventName": "UNC_R3_IOT_CTS_HI.CTS2", + "PerPkg": "1", + "PublicDescription": "Debug Mask/Match Tie-Ins", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "IOT Common Trigger Sequencer - Hi", + "EventCode": "0xD", + "EventName": "UNC_R3_IOT_CTS_HI.CTS3", + "PerPkg": "1", + "PublicDescription": "Debug Mask/Match Tie-Ins", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "EventCode": "0xC", + "EventName": "UNC_R3_IOT_CTS_LO.CTS0", + "PerPkg": "1", + "PublicDescription": "Debug Mask/Match Tie-Ins", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "EventCode": "0xC", + "EventName": "UNC_R3_IOT_CTS_LO.CTS1", + "PerPkg": "1", + "PublicDescription": "Debug Mask/Match Tie-Ins", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "EventCode": "0x20", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 HOM Messages", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "EventCode": "0x20", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 NDR Messages", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "EventCode": "0x20", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 SNP Messages", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "EventCode": "0x20", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 HOM Messages", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "EventCode": "0x20", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 NDR Messages", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "EventCode": "0x20", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 SNP Messages", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "EventCode": "0x20", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VNA", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "EventCode": "0x21", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 HOM Messages", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "EventCode": "0x21", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 NDR Messages", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "EventCode": "0x21", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 SNP Messages", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "EventCode": "0x21", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VNA", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "EventCode": "0x2E", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 HOM Messages", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "EventCode": "0x2E", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 NDR Messages", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "EventCode": "0x2E", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 SNP Messages", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "EventCode": "0x2E", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VNA", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "EventCode": "0x2F", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 HOM Messages", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "EventCode": "0x2F", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 NDR Messages", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "EventCode": "0x2F", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 SNP Messages", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "EventCode": "0x2F", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 HOM Messages", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "EventCode": "0x2F", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 NDR Messages", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "EventCode": "0x2F", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 SNP Messages", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "EventCode": "0x2F", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VNA", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; All", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xf", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Counterclockwise", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xc", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Clockwise", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x3", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Clockwise and Even", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; All", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xf", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Counterclockwise", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xc", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Clockwise", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x3", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Clockwise and Even", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; All", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xf", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Counterclockwise", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xc", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Clockwise", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x3", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Clockwise and Even", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 IV Ring in Use; Any", + "EventCode": "0xA", + "EventName": "UNC_R3_RING_IV_USED.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", + "UMask": "0xf", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 IV Ring in Use; Clockwise", + "EventCode": "0xA", + "EventName": "UNC_R3_RING_IV_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", + "UMask": "0x3", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ring Stop Starved; AK", + "EventCode": "0xE", + "EventName": "UNC_R3_RING_SINK_STARVED.AK", + "PerPkg": "1", + "PublicDescription": "Number of cycles the ringstop is in starvation (per ring)", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; HOM", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NDR", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.NDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; SNP", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Cycles Not Empty; DRS", + "EventCode": "0x14", + "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Cycles Not Empty; HOM", + "EventCode": "0x14", + "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Cycles Not Empty; NCB", + "EventCode": "0x14", + "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Cycles Not Empty; NCS", + "EventCode": "0x14", + "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Cycles Not Empty; NDR", + "EventCode": "0x14", + "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Cycles Not Empty; SNP", + "EventCode": "0x14", + "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; DRS", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; HOM", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; NCB", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; NCS", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; NDR", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.NDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; SNP", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Allocations; DRS", + "EventCode": "0x15", + "EventName": "UNC_R3_RxR_INSERTS_VN1.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Allocations; HOM", + "EventCode": "0x15", + "EventName": "UNC_R3_RxR_INSERTS_VN1.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Allocations; NCB", + "EventCode": "0x15", + "EventName": "UNC_R3_RxR_INSERTS_VN1.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Allocations; NCS", + "EventCode": "0x15", + "EventName": "UNC_R3_RxR_INSERTS_VN1.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Allocations; NDR", + "EventCode": "0x15", + "EventName": "UNC_R3_RxR_INSERTS_VN1.NDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Allocations; SNP", + "EventCode": "0x15", + "EventName": "UNC_R3_RxR_INSERTS_VN1.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Occupancy Accumulator; DRS", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.DRS", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Occupancy Accumulator; HOM", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.HOM", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; HOM Ingress Queue", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Occupancy Accumulator; NCB", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCB", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NCB Ingress Queue", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Occupancy Accumulator; NCS", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCS", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NCS Ingress Queue", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Occupancy Accumulator; NDR", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NDR", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NDR Ingress Queue", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Occupancy Accumulator; SNP", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.SNP", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; SNP Ingress Queue", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "SBo0 Credits Acquired; For AD Ring", + "EventCode": "0x28", + "EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.AD", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "SBo0 Credits Acquired; For BL Ring", + "EventCode": "0x28", + "EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.BL", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "SBo0 Credits Occupancy; For AD Ring", + "EventCode": "0x2A", + "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.AD", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "SBo0 Credits Occupancy; For BL Ring", + "EventCode": "0x2A", + "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.BL", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "SBo1 Credits Acquired; For AD Ring", + "EventCode": "0x29", + "EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.AD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits received over QPI that do not hold protocol payload. When QPI is not in a power saving state, it continuously transmits flits across the link. When there are no protocol flits to send, it will send IDLE and NULL flits across. These flits sometimes do carry a payload, such as credit returns, but are generally not considered part of the QPI bandwidth.", + "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)", - "EventCode": "0x2", - "EventName": "UNC_Q_RxL_FLITS_G1.DRS", + "BriefDescription": "SBo1 Credits Acquired; For BL Ring", + "EventCode": "0x29", + "EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.BL", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data.", - "UMask": "0x18", - "Unit": "QPI LL" + "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.", + "UMask": "0x2", + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 1; DRS Data Flits", - "EventCode": "0x2", - "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA", + "BriefDescription": "SBo1 Credits Occupancy; For AD Ring", + "EventCode": "0x2B", + "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.AD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).", - "UMask": "0x8", - "Unit": "QPI LL" + "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.", + "UMask": "0x1", + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 1; DRS Header Flits", - "EventCode": "0x2", - "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA", + "BriefDescription": "SBo1 Credits Occupancy; For BL Ring", + "EventCode": "0x2B", + "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.BL", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.", - "UMask": "0x10", - "Unit": "QPI LL" + "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.", + "UMask": "0x2", + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 1; HOM Flits", - "EventCode": "0x2", - "EventName": "UNC_Q_RxL_FLITS_G1.HOM", + "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring", + "EventCode": "0x2C", + "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_AD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits received over QPI on the home channel.", - "UMask": "0x6", - "Unit": "QPI LL" + "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", + "UMask": "0x1", + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits", - "EventCode": "0x2", - "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ", + "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring", + "EventCode": "0x2C", + "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_BL", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits received over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.", + "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 1; HOM Request Flits", - "EventCode": "0x2", - "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ", + "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring", + "EventCode": "0x2C", + "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_AD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request received over QPI on the home channel. This basically counts the number of remote memory requests received over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.", + "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 1; SNP Flits", - "EventCode": "0x2", - "EventName": "UNC_Q_RxL_FLITS_G1.SNP", + "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring", + "EventCode": "0x2C", + "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_BL", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits received over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are received on the home channel.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", + "UMask": "0x8", + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits", - "EventCode": "0x3", - "EventName": "UNC_Q_RxL_FLITS_G2.NCB", + "BriefDescription": "Egress CCW NACK; AD CCW", + "EventCode": "0x26", + "EventName": "UNC_R3_TxR_NACK.DN_AD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.", - "UMask": "0xc", - "Unit": "QPI LL" + "PublicDescription": "AD CounterClockwise Egress Queue", + "UMask": "0x1", + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 2; Non-Coherent data Rx Flits", - "EventCode": "0x3", - "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA", + "BriefDescription": "Egress CCW NACK; AK CCW", + "EventCode": "0x26", + "EventName": "UNC_R3_TxR_NACK.DN_AK", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers.", + "PublicDescription": "AK CounterClockwise Egress Queue", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 2; Non-Coherent non-data Rx Flits", - "EventCode": "0x3", - "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA", + "BriefDescription": "Egress CCW NACK; BL CCW", + "EventCode": "0x26", + "EventName": "UNC_R3_TxR_NACK.DN_BL", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.", + "PublicDescription": "BL CounterClockwise Egress Queue", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Egress CCW NACK; AK CCW", + "EventCode": "0x26", + "EventName": "UNC_R3_TxR_NACK.UP_AD", + "PerPkg": "1", + "PublicDescription": "BL CounterClockwise Egress Queue", "UMask": "0x8", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits", - "EventCode": "0x3", - "EventName": "UNC_Q_RxL_FLITS_G2.NCS", + "BriefDescription": "Egress CCW NACK; BL CW", + "EventCode": "0x26", + "EventName": "UNC_R3_TxR_NACK.UP_AK", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits received over QPI. This includes extended headers.", + "PublicDescription": "AD Clockwise Egress Queue", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Egress CCW NACK; BL CCW", + "EventCode": "0x26", + "EventName": "UNC_R3_TxR_NACK.UP_BL", + "PerPkg": "1", + "PublicDescription": "AD CounterClockwise Egress Queue", "UMask": "0x10", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD", - "EventCode": "0x3", - "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD", + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.", + "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK", - "EventCode": "0x3", - "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK", + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Message Class", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.", + "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Message Class", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Rx Flit Buffer Allocations", - "EventCode": "0x8", - "EventName": "UNC_Q_RxL_INSERTS", + "BriefDescription": "VN0 Credit Used; DRS Message Class", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.DRS", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", - "Unit": "QPI LL" + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", + "UMask": "0x8", + "Unit": "R3QPI" }, { - "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN0", - "EventCode": "0x9", - "EventName": "UNC_Q_RxL_INSERTS_DRS.VN0", + "BriefDescription": "VN0 Credit Used; HOM Message Class", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.HOM", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits.", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN1", - "EventCode": "0x9", - "EventName": "UNC_Q_RxL_INSERTS_DRS.VN1", + "BriefDescription": "VN0 Credit Used; NCB Message Class", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.NCB", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits.", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; NCS Message Class", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; NDR Message Class", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.NDR", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; SNP Message Class", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN0", - "EventCode": "0xC", - "EventName": "UNC_Q_RxL_INSERTS_HOM.VN0", + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Message Class", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits.", + "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Message Class", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN1", - "EventCode": "0xC", - "EventName": "UNC_Q_RxL_INSERTS_HOM.VN1", + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCB Message Class", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCB", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits.", + "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCS Message Class", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCS", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Message Class", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Message Class", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN0", - "EventCode": "0xA", - "EventName": "UNC_Q_RxL_INSERTS_NCB.VN0", + "BriefDescription": "VN1 Credit Used; DRS Message Class", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.DRS", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits.", + "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; HOM Message Class", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.HOM", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN1", - "EventCode": "0xA", - "EventName": "UNC_Q_RxL_INSERTS_NCB.VN1", + "BriefDescription": "VN1 Credit Used; NCB Message Class", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.NCB", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits.", + "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; NCS Message Class", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; NDR Message Class", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.NDR", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; SNP Message Class", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN0", - "EventCode": "0xB", - "EventName": "UNC_Q_RxL_INSERTS_NCS.VN0", + "BriefDescription": "VNA credit Acquisitions; HOM Message Class", + "EventCode": "0x33", + "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits.", + "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN1", - "EventCode": "0xB", - "EventName": "UNC_Q_RxL_INSERTS_NCS.VN1", + "BriefDescription": "VNA credit Acquisitions; HOM Message Class", + "EventCode": "0x33", + "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits.", + "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; DRS Message Class", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; HOM Message Class", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; NCB Message Class", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; NCS Message Class", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Standard (NCS).", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; NDR Message Class", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; SNP Message Class", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN0", - "EventCode": "0xE", - "EventName": "UNC_Q_RxL_INSERTS_NDR.VN0", + "BriefDescription": "Bounce Control", + "EventCode": "0xA", + "EventName": "UNC_S_BOUNCE_CONTROL", + "PerPkg": "1", + "Unit": "SBOX" + }, + { + "BriefDescription": "Uncore Clocks", + "EventName": "UNC_S_CLOCKTICKS", + "PerPkg": "1", + "Unit": "SBOX" + }, + { + "BriefDescription": "FaST wire asserted", + "EventCode": "0x9", + "EventName": "UNC_S_FAST_ASSERTED", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", + "Unit": "SBOX" + }, + { + "BriefDescription": "AD Ring In Use; All", + "EventCode": "0x1B", + "EventName": "UNC_S_RING_AD_USED.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0xf", + "Unit": "SBOX" + }, + { + "BriefDescription": "AD Ring In Use; Down", + "EventCode": "0x1B", + "EventName": "UNC_S_RING_AD_USED.DOWN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0xc", + "Unit": "SBOX" + }, + { + "BriefDescription": "AD Ring In Use; Down and Event", + "EventCode": "0x1B", + "EventName": "UNC_S_RING_AD_USED.DOWN_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.", + "UMask": "0x4", + "Unit": "SBOX" + }, + { + "BriefDescription": "AD Ring In Use; Down and Odd", + "EventCode": "0x1B", + "EventName": "UNC_S_RING_AD_USED.DOWN_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.", + "UMask": "0x8", + "Unit": "SBOX" + }, + { + "BriefDescription": "AD Ring In Use; Up", + "EventCode": "0x1B", + "EventName": "UNC_S_RING_AD_USED.UP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x3", + "Unit": "SBOX" + }, + { + "BriefDescription": "AD Ring In Use; Up and Even", + "EventCode": "0x1B", + "EventName": "UNC_S_RING_AD_USED.UP_EVEN", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits.", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN1", - "EventCode": "0xE", - "EventName": "UNC_Q_RxL_INSERTS_NDR.VN1", + "BriefDescription": "AD Ring In Use; Up and Odd", + "EventCode": "0x1B", + "EventName": "UNC_S_RING_AD_USED.UP_ODD", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits.", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN0", - "EventCode": "0xD", - "EventName": "UNC_Q_RxL_INSERTS_SNP.VN0", + "BriefDescription": "AK Ring In Use; All", + "EventCode": "0x1C", + "EventName": "UNC_S_RING_AK_USED.ALL", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0xf", + "Unit": "SBOX" }, { - "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN1", - "EventCode": "0xD", - "EventName": "UNC_Q_RxL_INSERTS_SNP.VN1", + "BriefDescription": "AK Ring In Use; Down", + "EventCode": "0x1C", + "EventName": "UNC_S_RING_AK_USED.DOWN", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0xc", + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - All Packets", - "EventCode": "0xB", - "EventName": "UNC_Q_RxL_OCCUPANCY", + "BriefDescription": "AK Ring In Use; Down and Event", + "EventCode": "0x1C", + "EventName": "UNC_S_RING_AK_USED.DOWN_EVEN", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.", + "UMask": "0x4", + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - DRS; for VN0", - "EventCode": "0x15", - "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN0", + "BriefDescription": "AK Ring In Use; Down and Odd", + "EventCode": "0x1C", + "EventName": "UNC_S_RING_AK_USED.DOWN_ODD", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.", + "UMask": "0x8", + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - DRS; for VN1", - "EventCode": "0x15", - "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN1", + "BriefDescription": "AK Ring In Use; Up", + "EventCode": "0x1C", + "EventName": "UNC_S_RING_AK_USED.UP", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x3", + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - HOM; for VN0", - "EventCode": "0x18", - "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN0", + "BriefDescription": "AK Ring In Use; Up and Even", + "EventCode": "0x1C", + "EventName": "UNC_S_RING_AK_USED.UP_EVEN", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only.", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - HOM; for VN1", - "EventCode": "0x18", - "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN1", + "BriefDescription": "AK Ring In Use; Up and Odd", + "EventCode": "0x1C", + "EventName": "UNC_S_RING_AK_USED.UP_ODD", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only.", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - NCB; for VN0", - "EventCode": "0x16", - "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN0", + "BriefDescription": "BL Ring in Use; All", + "EventCode": "0x1D", + "EventName": "UNC_S_RING_BL_USED.ALL", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0xf", + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - NCB; for VN1", - "EventCode": "0x16", - "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN1", + "BriefDescription": "BL Ring in Use; Down", + "EventCode": "0x1D", + "EventName": "UNC_S_RING_BL_USED.DOWN", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0xc", + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - NCS; for VN0", - "EventCode": "0x17", - "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN0", + "BriefDescription": "BL Ring in Use; Down and Event", + "EventCode": "0x1D", + "EventName": "UNC_S_RING_BL_USED.DOWN_EVEN", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.", + "UMask": "0x4", + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - NCS; for VN1", - "EventCode": "0x17", - "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN1", + "BriefDescription": "BL Ring in Use; Down and Odd", + "EventCode": "0x1D", + "EventName": "UNC_S_RING_BL_USED.DOWN_ODD", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.", + "UMask": "0x8", + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - NDR; for VN0", - "EventCode": "0x1A", - "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN0", + "BriefDescription": "BL Ring in Use; Up", + "EventCode": "0x1D", + "EventName": "UNC_S_RING_BL_USED.UP", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only.", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x3", + "Unit": "SBOX" + }, + { + "BriefDescription": "BL Ring in Use; Up and Even", + "EventCode": "0x1D", + "EventName": "UNC_S_RING_BL_USED.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - NDR; for VN1", - "EventCode": "0x1A", - "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN1", + "BriefDescription": "BL Ring in Use; Up and Odd", + "EventCode": "0x1D", + "EventName": "UNC_S_RING_BL_USED.UP_ODD", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only.", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - SNP; for VN0", - "EventCode": "0x19", - "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN0", + "BriefDescription": "Number of LLC responses that bounced on the Ring.", + "EventCode": "0x5", + "EventName": "UNC_S_RING_BOUNCES.AD_CACHE", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - SNP; for VN1", - "EventCode": "0x19", - "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN1", + "BriefDescription": "Number of LLC responses that bounced on the Ring.; Acknowledgements to core", + "EventCode": "0x5", + "EventName": "UNC_S_RING_BOUNCES.AK_CORE", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - HOM", - "EventCode": "0x35", - "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_DRS", + "BriefDescription": "Number of LLC responses that bounced on the Ring.; Data Responses to core", + "EventCode": "0x5", + "EventName": "UNC_S_RING_BOUNCES.BL_CORE", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", - "UMask": "0x1", - "Unit": "QPI LL" + "UMask": "0x4", + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - DRS", - "EventCode": "0x35", - "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_HOM", + "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.", + "EventCode": "0x5", + "EventName": "UNC_S_RING_BOUNCES.IV_CORE", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", "UMask": "0x8", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - SNP", - "EventCode": "0x35", - "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCB", + "BriefDescription": "BL Ring in Use; Any", + "EventCode": "0x1E", + "EventName": "UNC_S_RING_IV_USED.DN", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. There is only 1 IV ring in HSX. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity", + "UMask": "0xc", + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NDR", - "EventCode": "0x35", - "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCS", + "BriefDescription": "BL Ring in Use; Any", + "EventCode": "0x1E", + "EventName": "UNC_S_RING_IV_USED.UP", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", - "UMask": "0x4", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. There is only 1 IV ring in HSX. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity", + "UMask": "0x3", + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCS", - "EventCode": "0x35", - "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NDR", + "BriefDescription": "UNC_S_RING_SINK_STARVED.AD_CACHE", + "EventCode": "0x6", + "EventName": "UNC_S_RING_SINK_STARVED.AD_CACHE", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", - "UMask": "0x20", - "Unit": "QPI LL" + "UMask": "0x1", + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCB", - "EventCode": "0x35", - "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_SNP", + "BriefDescription": "UNC_S_RING_SINK_STARVED.AK_CORE", + "EventCode": "0x6", + "EventName": "UNC_S_RING_SINK_STARVED.AK_CORE", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", - "UMask": "0x10", - "Unit": "QPI LL" + "UMask": "0x2", + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN0; Egress Credits", - "EventCode": "0x35", - "EventName": "UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS", + "BriefDescription": "UNC_S_RING_SINK_STARVED.BL_CORE", + "EventCode": "0x6", + "EventName": "UNC_S_RING_SINK_STARVED.BL_CORE", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet because there were insufficient BGF credits. For details on a message class granularity, use the Egress Credit Occupancy events.", - "UMask": "0x40", - "Unit": "QPI LL" + "UMask": "0x4", + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN0; GV", - "EventCode": "0x35", - "EventName": "UNC_Q_RxL_STALLS_VN0.GV", + "BriefDescription": "UNC_S_RING_SINK_STARVED.IV_CORE", + "EventCode": "0x6", + "EventName": "UNC_S_RING_SINK_STARVED.IV_CORE", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled because a GV transition (frequency transition) was taking place.", - "UMask": "0x80", - "Unit": "QPI LL" + "UMask": "0x8", + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - HOM", - "EventCode": "0x3A", - "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_DRS", + "BriefDescription": "Injection Starvation; AD - Bounces", + "EventCode": "0x15", + "EventName": "UNC_S_RxR_BUSY_STARVED.AD_BNC", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.", + "UMask": "0x2", + "Unit": "SBOX" + }, + { + "BriefDescription": "Injection Starvation; AD - Credits", + "EventCode": "0x15", + "EventName": "UNC_S_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - DRS", - "EventCode": "0x3A", - "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_HOM", + "BriefDescription": "Injection Starvation; BL - Bounces", + "EventCode": "0x15", + "EventName": "UNC_S_RxR_BUSY_STARVED.BL_BNC", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.", "UMask": "0x8", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - SNP", - "EventCode": "0x3A", - "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCB", + "BriefDescription": "Injection Starvation; BL - Credits", + "EventCode": "0x15", + "EventName": "UNC_S_RxR_BUSY_STARVED.BL_CRD", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.", + "UMask": "0x4", + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NDR", - "EventCode": "0x3A", - "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCS", + "BriefDescription": "Bypass; AD - Bounces", + "EventCode": "0x12", + "EventName": "UNC_S_RxR_BYPASS.AD_BNC", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", - "UMask": "0x4", - "Unit": "QPI LL" + "PublicDescription": "Bypass the Sbo Ingress.", + "UMask": "0x2", + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCS", - "EventCode": "0x3A", - "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NDR", + "BriefDescription": "Bypass; AD - Credits", + "EventCode": "0x12", + "EventName": "UNC_S_RxR_BYPASS.AD_CRD", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", - "UMask": "0x20", - "Unit": "QPI LL" + "PublicDescription": "Bypass the Sbo Ingress.", + "UMask": "0x1", + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCB", - "EventCode": "0x3A", - "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_SNP", + "BriefDescription": "Bypass; AK", + "EventCode": "0x12", + "EventName": "UNC_S_RxR_BYPASS.AK", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "PublicDescription": "Bypass the Sbo Ingress.", "UMask": "0x10", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Cycles in L0p", - "EventCode": "0xD", - "EventName": "UNC_Q_TxL0P_POWER_CYCLES", + "BriefDescription": "Bypass; BL - Bounces", + "EventCode": "0x12", + "EventName": "UNC_S_RxR_BYPASS.BL_BNC", "PerPkg": "1", - "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.", - "Unit": "QPI LL" + "PublicDescription": "Bypass the Sbo Ingress.", + "UMask": "0x8", + "Unit": "SBOX" }, { - "BriefDescription": "Cycles in L0", - "EventCode": "0xC", - "EventName": "UNC_Q_TxL0_POWER_CYCLES", + "BriefDescription": "Bypass; BL - Credits", + "EventCode": "0x12", + "EventName": "UNC_S_RxR_BYPASS.BL_CRD", "PerPkg": "1", - "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", - "Unit": "QPI LL" + "PublicDescription": "Bypass the Sbo Ingress.", + "UMask": "0x4", + "Unit": "SBOX" }, { - "BriefDescription": "Tx Flit Buffer Bypassed", - "EventCode": "0x5", - "EventName": "UNC_Q_TxL_BYPASSED", + "BriefDescription": "Bypass; IV", + "EventCode": "0x12", + "EventName": "UNC_S_RxR_BYPASS.IV", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.", - "Unit": "QPI LL" + "PublicDescription": "Bypass the Sbo Ingress.", + "UMask": "0x20", + "Unit": "SBOX" }, { - "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full", - "EventCode": "0x2", - "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL", + "BriefDescription": "Injection Starvation; AD - Bounces", + "EventCode": "0x14", + "EventName": "UNC_S_RxR_CRD_STARVED.AD_BNC", "PerPkg": "1", - "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is almost full, we block some but not all packets.", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full", - "EventCode": "0x2", - "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL", + "BriefDescription": "Injection Starvation; AD - Credits", + "EventCode": "0x14", + "EventName": "UNC_S_RxR_CRD_STARVED.AD_CRD", "PerPkg": "1", - "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is totally full, we are not allowed to send any packets.", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Tx Flit Buffer Cycles not Empty", - "EventCode": "0x6", - "EventName": "UNC_Q_TxL_CYCLES_NE", + "BriefDescription": "Injection Starvation; AK", + "EventCode": "0x14", + "EventName": "UNC_S_RxR_CRD_STARVED.AK", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.", - "Unit": "QPI LL" + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", + "UMask": "0x10", + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits", - "EventName": "UNC_Q_TxL_FLITS_G0.DATA", + "BriefDescription": "Injection Starvation; BL - Bounces", + "EventCode": "0x14", + "EventName": "UNC_S_RxR_CRD_STARVED.BL_BNC", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", + "UMask": "0x8", + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits", - "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA", + "BriefDescription": "Injection Starvation; BL - Credits", + "EventCode": "0x14", + "EventName": "UNC_S_RxR_CRD_STARVED.BL_CRD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets.", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)", - "EventName": "UNC_Q_TxL_FLITS_G1.DRS", + "BriefDescription": "Injection Starvation; IVF Credit", + "EventCode": "0x14", + "EventName": "UNC_S_RxR_CRD_STARVED.IFV", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency.", - "UMask": "0x18", - "Unit": "QPI LL" + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", + "UMask": "0x40", + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits", - "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA", + "BriefDescription": "Injection Starvation; IV", + "EventCode": "0x14", + "EventName": "UNC_S_RxR_CRD_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", + "UMask": "0x20", + "Unit": "SBOX" + }, + { + "BriefDescription": "Ingress Allocations; AD - Bounces", + "EventCode": "0x13", + "EventName": "UNC_S_RxR_INSERTS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", + "UMask": "0x2", + "Unit": "SBOX" + }, + { + "BriefDescription": "Ingress Allocations; AD - Credits", + "EventCode": "0x13", + "EventName": "UNC_S_RxR_INSERTS.AD_CRD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).", - "UMask": "0x8", - "Unit": "QPI LL" + "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", + "UMask": "0x1", + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits", - "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA", + "BriefDescription": "Ingress Allocations; AK", + "EventCode": "0x13", + "EventName": "UNC_S_RxR_INSERTS.AK", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.", + "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", "UMask": "0x10", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 1; HOM Flits", - "EventName": "UNC_Q_TxL_FLITS_G1.HOM", + "BriefDescription": "Ingress Allocations; BL - Bounces", + "EventCode": "0x13", + "EventName": "UNC_S_RxR_INSERTS.BL_BNC", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits transmitted over QPI on the home channel.", - "UMask": "0x6", - "Unit": "QPI LL" + "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", + "UMask": "0x8", + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits", - "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ", + "BriefDescription": "Ingress Allocations; BL - Credits", + "EventCode": "0x13", + "EventName": "UNC_S_RxR_INSERTS.BL_CRD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits transmitted over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.", + "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits", - "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ", + "BriefDescription": "Ingress Allocations; IV", + "EventCode": "0x13", + "EventName": "UNC_S_RxR_INSERTS.IV", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request transmitted over QPI on the home channel. This basically counts the number of remote memory requests transmitted over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.", + "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", + "UMask": "0x20", + "Unit": "SBOX" + }, + { + "BriefDescription": "Ingress Occupancy; AD - Bounces", + "EventCode": "0x11", + "EventName": "UNC_S_RxR_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 1; SNP Flits", - "EventName": "UNC_Q_TxL_FLITS_G1.SNP", + "BriefDescription": "Ingress Occupancy; AD - Credits", + "EventCode": "0x11", + "EventName": "UNC_S_RxR_OCCUPANCY.AD_CRD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits transmitted over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are transmitted on the home channel.", + "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits", - "EventCode": "0x1", - "EventName": "UNC_Q_TxL_FLITS_G2.NCB", + "BriefDescription": "Ingress Occupancy; AK", + "EventCode": "0x11", + "EventName": "UNC_S_RxR_OCCUPANCY.AK", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.", - "UMask": "0xc", - "Unit": "QPI LL" + "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", + "UMask": "0x10", + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 2; Non-Coherent data Tx Flits", - "EventCode": "0x1", - "EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA", + "BriefDescription": "Ingress Occupancy; BL - Bounces", + "EventCode": "0x11", + "EventName": "UNC_S_RxR_OCCUPANCY.BL_BNC", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers.", - "UMask": "0x4", - "Unit": "QPI LL" + "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", + "UMask": "0x8", + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 2; Non-Coherent non-data Tx Flits", - "EventCode": "0x1", - "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA", + "BriefDescription": "Ingress Occupancy; BL - Credits", + "EventCode": "0x11", + "EventName": "UNC_S_RxR_OCCUPANCY.BL_CRD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.", - "UMask": "0x8", - "Unit": "QPI LL" + "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", + "UMask": "0x4", + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits", - "EventCode": "0x1", - "EventName": "UNC_Q_TxL_FLITS_G2.NCS", + "BriefDescription": "Ingress Occupancy; IV", + "EventCode": "0x11", + "EventName": "UNC_S_RxR_OCCUPANCY.IV", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits transmitted over QPI. This includes extended headers.", - "UMask": "0x10", - "Unit": "QPI LL" + "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", + "UMask": "0x20", + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD", - "EventCode": "0x1", - "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD", + "BriefDescription": "UNC_S_TxR_ADS_USED.AD", + "EventCode": "0x4", + "EventName": "UNC_S_TxR_ADS_USED.AD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK", - "EventCode": "0x1", - "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK", + "BriefDescription": "UNC_S_TxR_ADS_USED.AK", + "EventCode": "0x4", + "EventName": "UNC_S_TxR_ADS_USED.AK", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Tx Flit Buffer Allocations", + "BriefDescription": "UNC_S_TxR_ADS_USED.BL", "EventCode": "0x4", - "EventName": "UNC_Q_TxL_INSERTS", + "EventName": "UNC_S_TxR_ADS_USED.BL", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Tx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", - "Unit": "QPI LL" + "UMask": "0x4", + "Unit": "SBOX" }, { - "BriefDescription": "Tx Flit Buffer Occupancy", - "EventCode": "0x7", - "EventName": "UNC_Q_TxL_OCCUPANCY", + "BriefDescription": "Egress Allocations; AD - Bounces", + "EventCode": "0x2", + "EventName": "UNC_S_TxR_INSERTS.AD_BNC", "PerPkg": "1", - "PublicDescription": "Accumulates the number of flits in the TxQ. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.", - "Unit": "QPI LL" + "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", + "UMask": "0x2", + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN0", - "EventCode": "0x26", - "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0", + "BriefDescription": "Egress Allocations; AD - Credits", + "EventCode": "0x2", + "EventName": "UNC_S_TxR_INSERTS.AD_CRD", "PerPkg": "1", - "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.", + "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN1", - "EventCode": "0x26", - "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1", + "BriefDescription": "Egress Allocations; AK", + "EventCode": "0x2", + "EventName": "UNC_S_TxR_INSERTS.AK", "PerPkg": "1", - "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", + "UMask": "0x10", + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN0", - "EventCode": "0x22", - "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0", + "BriefDescription": "Egress Allocations; BL - Bounces", + "EventCode": "0x2", + "EventName": "UNC_S_TxR_INSERTS.BL_BNC", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", + "UMask": "0x8", + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN1", - "EventCode": "0x22", - "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1", + "BriefDescription": "Egress Allocations; BL - Credits", + "EventCode": "0x2", + "EventName": "UNC_S_TxR_INSERTS.BL_CRD", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", + "UMask": "0x4", + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0", - "EventCode": "0x28", - "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0", + "BriefDescription": "Egress Allocations; IV", + "EventCode": "0x2", + "EventName": "UNC_S_TxR_INSERTS.IV", "PerPkg": "1", - "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", + "UMask": "0x20", + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1", - "EventCode": "0x28", - "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1", + "BriefDescription": "Egress Occupancy; AD - Bounces", + "EventCode": "0x1", + "EventName": "UNC_S_TxR_OCCUPANCY.AD_BNC", "PerPkg": "1", - "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD.", + "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0", - "EventCode": "0x24", - "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0", + "BriefDescription": "Egress Occupancy; AD - Credits", + "EventCode": "0x1", + "EventName": "UNC_S_TxR_OCCUPANCY.AD_CRD", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD.", + "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1", - "EventCode": "0x24", - "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1", + "BriefDescription": "Egress Occupancy; AK", + "EventCode": "0x1", + "EventName": "UNC_S_TxR_OCCUPANCY.AK", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", + "UMask": "0x10", + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN0", - "EventCode": "0x27", - "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0", + "BriefDescription": "Egress Occupancy; BL - Bounces", + "EventCode": "0x1", + "EventName": "UNC_S_TxR_OCCUPANCY.BL_BNC", "PerPkg": "1", - "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", + "UMask": "0x8", + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN1", - "EventCode": "0x27", - "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1", + "BriefDescription": "Egress Occupancy; BL - Credits", + "EventCode": "0x1", + "EventName": "UNC_S_TxR_OCCUPANCY.BL_CRD", "PerPkg": "1", - "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", + "UMask": "0x4", + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN0", - "EventCode": "0x23", - "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0", + "BriefDescription": "Egress Occupancy; IV", + "EventCode": "0x1", + "EventName": "UNC_S_TxR_OCCUPANCY.IV", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for Snoop messages on AD.", + "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", + "UMask": "0x20", + "Unit": "SBOX" + }, + { + "BriefDescription": "Injection Starvation; Onto AD Ring", + "EventCode": "0x3", + "EventName": "UNC_S_TxR_STARVED.AD", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN1", - "EventCode": "0x23", - "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1", + "BriefDescription": "Injection Starvation; Onto AK Ring", + "EventCode": "0x3", + "EventName": "UNC_S_TxR_STARVED.AK", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for Snoop messages on AD.", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR", - "EventCode": "0x29", - "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED", + "BriefDescription": "Injection Starvation; Onto BL Ring", + "EventCode": "0x3", + "EventName": "UNC_S_TxR_STARVED.BL", "PerPkg": "1", - "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.", - "Unit": "QPI LL" + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.", + "UMask": "0x4", + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR", - "EventCode": "0x25", - "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY", + "BriefDescription": "Injection Starvation; Onto IV Ring", + "EventCode": "0x3", + "EventName": "UNC_S_TxR_STARVED.IV", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. Local NDR message class to AK Egress.", - "Unit": "QPI LL" + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.", + "UMask": "0x8", + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN0", - "EventCode": "0x2A", - "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0", + "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", + "EventCode": "0xff", + "EventName": "UNC_U_CLOCKTICKS", "PerPkg": "1", - "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.", - "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN1", - "EventCode": "0x2A", - "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1", + "BriefDescription": "VLW Received", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", "PerPkg": "1", - "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x8", + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for Shared VN", - "EventCode": "0x2A", - "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR", + "BriefDescription": "Filter Match", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.DISABLE", "PerPkg": "1", - "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.", - "UMask": "0x4", - "Unit": "QPI LL" + "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x2", + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN0", - "EventCode": "0x1F", - "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0", + "BriefDescription": "Filter Match", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.ENABLE", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.", + "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN1", - "EventCode": "0x1F", - "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1", + "BriefDescription": "Filter Match", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x8", + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for Shared VN", - "EventCode": "0x1F", - "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR", + "BriefDescription": "Filter Match", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.", + "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN0", - "EventCode": "0x2B", - "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0", + "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", + "EventCode": "0x45", + "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", "PerPkg": "1", - "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.", + "PublicDescription": "PHOLD cycles. Filter from source CoreID.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN1", - "EventCode": "0x2B", - "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1", + "BriefDescription": "RACU Request", + "EventCode": "0x46", + "EventName": "UNC_U_RACU_REQUESTS", "PerPkg": "1", - "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Number outstanding register requests within message channel tracker", + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN0", - "EventCode": "0x20", - "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0", + "BriefDescription": "Monitor Sent to T0; Correctable Machine Check", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.CMC", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Events coming from Uncore can be sent to one or all cores", + "UMask": "0x10", + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN1", - "EventCode": "0x20", - "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1", + "BriefDescription": "Monitor Sent to T0; Livelock", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.LIVELOCK", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", + "UMask": "0x4", + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN0", - "EventCode": "0x2C", - "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0", + "BriefDescription": "Monitor Sent to T0; LTError", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.LTERROR", "PerPkg": "1", - "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", + "UMask": "0x8", + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN1", - "EventCode": "0x2C", - "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1", + "BriefDescription": "Monitor Sent to T0; Monitor T0", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0", "PerPkg": "1", - "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", + "UMask": "0x1", + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN0", - "EventCode": "0x21", - "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0", + "BriefDescription": "Monitor Sent to T0; Monitor T1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", + "UMask": "0x2", + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN1", - "EventCode": "0x21", - "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1", + "BriefDescription": "Monitor Sent to T0; Other", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.OTHER", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Events coming from Uncore can be sent to one or all cores; PREQ, PSMI, P2U, Thermal, PCUSMI, PMI", + "UMask": "0x80", + "Unit": "UBOX" }, { - "BriefDescription": "VNA Credits Returned", - "EventCode": "0x1C", - "EventName": "UNC_Q_VNA_CREDIT_RETURNS", + "BriefDescription": "Monitor Sent to T0; Trap", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.TRAP", "PerPkg": "1", - "PublicDescription": "Number of VNA credits returned.", - "Unit": "QPI LL" + "PublicDescription": "Events coming from Uncore can be sent to one or all cores", + "UMask": "0x40", + "Unit": "UBOX" }, { - "BriefDescription": "VNA Credits Pending Return - Occupancy", - "EventCode": "0x1B", - "EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY", + "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.UMC", "PerPkg": "1", - "PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.", - "Unit": "QPI LL" + "PublicDescription": "Events coming from Uncore can be sent to one or all cores", + "UMask": "0x20", + "Unit": "UBOX" } ] diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-io.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-io.json new file mode 100644 index 000000000000..01e04daf03da --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-io.json @@ -0,0 +1,555 @@ +[ + { + "BriefDescription": "Number of uclks in domain", + "EventCode": "0x1", + "EventName": "UNC_R2_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts the number of uclks in the R2PCIe uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI0", + "EventCode": "0x2D", + "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI1", + "EventCode": "0x2D", + "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI0", + "EventCode": "0x2D", + "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI1", + "EventCode": "0x2D", + "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; DRS", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; NCB", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; NCS", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; DRS", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; NCB", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; NCS", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; All", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xf", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xc", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x3", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise and Even", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "AK Ingress Bounced; Dn", + "EventCode": "0x12", + "EventName": "UNC_R2_RING_AK_BOUNCES.DN", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "AK Ingress Bounced; Up", + "EventCode": "0x12", + "EventName": "UNC_R2_RING_AK_BOUNCES.UP", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; All", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xf", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xc", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x3", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise and Even", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; All", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xf", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xc", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x3", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise and Even", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 IV Ring in Use; Any", + "EventCode": "0xA", + "EventName": "UNC_R2_RING_IV_USED.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", + "UMask": "0xf", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 IV Ring in Use; Counterclockwise", + "EventCode": "0xA", + "EventName": "UNC_R2_RING_IV_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", + "UMask": "0xc", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 IV Ring in Use; Clockwise", + "EventCode": "0xA", + "EventName": "UNC_R2_RING_IV_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", + "UMask": "0x3", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NCB", + "EventCode": "0x10", + "EventName": "UNC_R2_RxR_CYCLES_NE.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NCS", + "EventCode": "0x10", + "EventName": "UNC_R2_RxR_CYCLES_NE.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Allocations; NCB", + "EventCode": "0x11", + "EventName": "UNC_R2_RxR_INSERTS.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Allocations; NCS", + "EventCode": "0x11", + "EventName": "UNC_R2_RxR_INSERTS.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; DRS", + "EventCode": "0x13", + "EventName": "UNC_R2_RxR_OCCUPANCY.DRS", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "SBo0 Credits Acquired; For AD Ring", + "EventCode": "0x28", + "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.AD", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "SBo0 Credits Acquired; For BL Ring", + "EventCode": "0x28", + "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.BL", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "SBo0 Credits Occupancy; For AD Ring", + "EventCode": "0x2A", + "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.AD", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "SBo0 Credits Occupancy; For BL Ring", + "EventCode": "0x2A", + "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.BL", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring", + "EventCode": "0x2C", + "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD", + "PerPkg": "1", + "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring", + "EventCode": "0x2C", + "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL", + "PerPkg": "1", + "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring", + "EventCode": "0x2C", + "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD", + "PerPkg": "1", + "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring", + "EventCode": "0x2C", + "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL", + "PerPkg": "1", + "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; AD", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AD Egress Queue", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; AK", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.AK", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AK Egress Queue", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; BL", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.BL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; BL Egress Queue", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; AD", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AD Egress Queue", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; AK", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.AK", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AK Egress Queue", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; BL", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.BL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; BL Egress Queue", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; AD CCW", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.DN_AD", + "PerPkg": "1", + "PublicDescription": "AD CounterClockwise Egress Queue", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; AK CCW", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.DN_AK", + "PerPkg": "1", + "PublicDescription": "AK CounterClockwise Egress Queue", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; BL CCW", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.DN_BL", + "PerPkg": "1", + "PublicDescription": "BL CounterClockwise Egress Queue", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; AK CCW", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.UP_AD", + "PerPkg": "1", + "PublicDescription": "BL CounterClockwise Egress Queue", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; BL CW", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.UP_AK", + "PerPkg": "1", + "PublicDescription": "AD Clockwise Egress Queue", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; BL CCW", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.UP_BL", + "PerPkg": "1", + "PublicDescription": "AD CounterClockwise Egress Queue", + "UMask": "0x10", + "Unit": "R2PCIe" + } +] diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json deleted file mode 100644 index 43def2582617..000000000000 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-other.json +++ /dev/null @@ -1,3242 +0,0 @@ -[ - { - "BriefDescription": "Total Write Cache Occupancy; Any Source", - "EventCode": "0x12", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Total Write Cache Occupancy; Select Source", - "EventCode": "0x12", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Clocks in the IRP", - "EventName": "UNC_I_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Number of clocks in the IRP.", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; CLFlush", - "EventCode": "0x13", - "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x80", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; CRd", - "EventCode": "0x13", - "EventName": "UNC_I_COHERENT_OPS.CRD", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; DRd", - "EventCode": "0x13", - "EventName": "UNC_I_COHERENT_OPS.DRD", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; PCIDCAHin5t", - "EventCode": "0x13", - "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; PCIRdCur", - "EventCode": "0x13", - "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; PCIItoM", - "EventCode": "0x13", - "EventName": "UNC_I_COHERENT_OPS.PCITOM", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; RFO", - "EventCode": "0x13", - "EventName": "UNC_I_COHERENT_OPS.RFO", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; WbMtoI", - "EventCode": "0x13", - "EventName": "UNC_I_COHERENT_OPS.WBMTOI", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary", - "EventCode": "0x14", - "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", - "PerPkg": "1", - "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary", - "EventCode": "0x14", - "EventName": "UNC_I_MISC0.2ND_RD_INSERT", - "PerPkg": "1", - "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary", - "EventCode": "0x14", - "EventName": "UNC_I_MISC0.2ND_WR_INSERT", - "PerPkg": "1", - "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Fastpath Rejects", - "EventCode": "0x14", - "EventName": "UNC_I_MISC0.FAST_REJ", - "PerPkg": "1", - "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Fastpath Requests", - "EventCode": "0x14", - "EventName": "UNC_I_MISC0.FAST_REQ", - "PerPkg": "1", - "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Requests", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary", - "EventCode": "0x14", - "EventName": "UNC_I_MISC0.FAST_XFER", - "PerPkg": "1", - "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary", - "EventCode": "0x14", - "EventName": "UNC_I_MISC0.PF_ACK_HINT", - "PerPkg": "1", - "PublicDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Prefetch TimeOut", - "EventCode": "0x14", - "EventName": "UNC_I_MISC0.PF_TIMEOUT", - "PerPkg": "1", - "PublicDescription": "Indicates the fetch for a previous prefetch wasn't accepted by the prefetch. This happens in the case of a prefetch TimeOut", - "UMask": "0x80", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Data Throttled", - "EventCode": "0x15", - "EventName": "UNC_I_MISC1.DATA_THROTTLE", - "PerPkg": "1", - "PublicDescription": "IRP throttled switch data", - "UMask": "0x80", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1", - "EventCode": "0x15", - "EventName": "UNC_I_MISC1.LOST_FWD", - "PerPkg": "1", - "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Received Invalid", - "EventCode": "0x15", - "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", - "PerPkg": "1", - "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Received Valid", - "EventCode": "0x15", - "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", - "PerPkg": "1", - "PublicDescription": "Secondary received a transfer that did have sufficient MESI state", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line", - "EventCode": "0x15", - "EventName": "UNC_I_MISC1.SLOW_E", - "PerPkg": "1", - "PublicDescription": "Secondary received a transfer that did have sufficient MESI state", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line", - "EventCode": "0x15", - "EventName": "UNC_I_MISC1.SLOW_I", - "PerPkg": "1", - "PublicDescription": "Snoop took cacheline ownership before write from data was committed.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line", - "EventCode": "0x15", - "EventName": "UNC_I_MISC1.SLOW_M", - "PerPkg": "1", - "PublicDescription": "Snoop took cacheline ownership before write from data was committed.", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line", - "EventCode": "0x15", - "EventName": "UNC_I_MISC1.SLOW_S", - "PerPkg": "1", - "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "AK Ingress Occupancy", - "EventCode": "0xA", - "EventName": "UNC_I_RxR_AK_INSERTS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the AK Ingress. This queue is where the IRP receives responses from R2PCIe (the ring).", - "Unit": "IRP" - }, - { - "BriefDescription": "UNC_I_RxR_BL_DRS_CYCLES_FULL", - "EventCode": "0x4", - "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "BL Ingress Occupancy - DRS", - "EventCode": "0x1", - "EventName": "UNC_I_RxR_BL_DRS_INSERTS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "UNC_I_RxR_BL_DRS_OCCUPANCY", - "EventCode": "0x7", - "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "UNC_I_RxR_BL_NCB_CYCLES_FULL", - "EventCode": "0x5", - "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "BL Ingress Occupancy - NCB", - "EventCode": "0x2", - "EventName": "UNC_I_RxR_BL_NCB_INSERTS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "UNC_I_RxR_BL_NCB_OCCUPANCY", - "EventCode": "0x8", - "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "UNC_I_RxR_BL_NCS_CYCLES_FULL", - "EventCode": "0x6", - "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "BL Ingress Occupancy - NCS", - "EventCode": "0x3", - "EventName": "UNC_I_RxR_BL_NCS_INSERTS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "UNC_I_RxR_BL_NCS_OCCUPANCY", - "EventCode": "0x9", - "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; Hit E or S", - "EventCode": "0x17", - "EventName": "UNC_I_SNOOP_RESP.HIT_ES", - "PerPkg": "1", - "PublicDescription": "Snoop Responses : Hit E or S", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; Hit I", - "EventCode": "0x17", - "EventName": "UNC_I_SNOOP_RESP.HIT_I", - "PerPkg": "1", - "PublicDescription": "Snoop Responses : Hit I", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; Hit M", - "EventCode": "0x17", - "EventName": "UNC_I_SNOOP_RESP.HIT_M", - "PerPkg": "1", - "PublicDescription": "Snoop Responses : Hit M", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; Miss", - "EventCode": "0x17", - "EventName": "UNC_I_SNOOP_RESP.MISS", - "PerPkg": "1", - "PublicDescription": "Snoop Responses : Miss", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; SnpCode", - "EventCode": "0x17", - "EventName": "UNC_I_SNOOP_RESP.SNPCODE", - "PerPkg": "1", - "PublicDescription": "Snoop Responses : SnpCode", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; SnpData", - "EventCode": "0x17", - "EventName": "UNC_I_SNOOP_RESP.SNPDATA", - "PerPkg": "1", - "PublicDescription": "Snoop Responses : SnpData", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; SnpInv", - "EventCode": "0x17", - "EventName": "UNC_I_SNOOP_RESP.SNPINV", - "PerPkg": "1", - "PublicDescription": "Snoop Responses : SnpInv", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Atomic", - "EventCode": "0x16", - "EventName": "UNC_I_TRANSACTIONS.ATOMIC", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Other", - "EventCode": "0x16", - "EventName": "UNC_I_TRANSACTIONS.OTHER", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions.", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Read Prefetches", - "EventCode": "0x16", - "EventName": "UNC_I_TRANSACTIONS.RD_PREF", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Reads", - "EventCode": "0x16", - "EventName": "UNC_I_TRANSACTIONS.READS", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Writes", - "EventCode": "0x16", - "EventName": "UNC_I_TRANSACTIONS.WRITES", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Write Prefetches", - "EventCode": "0x16", - "EventName": "UNC_I_TRANSACTIONS.WR_PREF", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of write prefetches.", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "No AD Egress Credit Stalls", - "EventCode": "0x18", - "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES", - "PerPkg": "1", - "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.", - "Unit": "IRP" - }, - { - "BriefDescription": "No BL Egress Credit Stalls", - "EventCode": "0x19", - "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES", - "PerPkg": "1", - "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Read Requests", - "EventCode": "0xE", - "EventName": "UNC_I_TxR_DATA_INSERTS_NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Read Requests", - "EventCode": "0xF", - "EventName": "UNC_I_TxR_DATA_INSERTS_NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Request Queue Occupancy", - "EventCode": "0xD", - "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.", - "Unit": "IRP" - }, - { - "BriefDescription": "Number of uclks in domain", - "EventCode": "0x1", - "EventName": "UNC_R2_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Counts the number of uclks in the R2PCIe uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI0", - "EventCode": "0x2D", - "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI1", - "EventCode": "0x2D", - "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI0", - "EventCode": "0x2D", - "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI1", - "EventCode": "0x2D", - "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credit Acquired; DRS", - "EventCode": "0x33", - "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credit Acquired; NCB", - "EventCode": "0x33", - "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credit Acquired; NCS", - "EventCode": "0x33", - "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credits in Use; DRS", - "EventCode": "0x32", - "EventName": "UNC_R2_IIO_CREDITS_USED.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credits in Use; NCB", - "EventCode": "0x32", - "EventName": "UNC_R2_IIO_CREDITS_USED.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credits in Use; NCS", - "EventCode": "0x32", - "EventName": "UNC_R2_IIO_CREDITS_USED.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; All", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.ALL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xf", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Counterclockwise", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xc", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CCW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CCW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Clockwise", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x3", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Clockwise and Even", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "AK Ingress Bounced; Dn", - "EventCode": "0x12", - "EventName": "UNC_R2_RING_AK_BOUNCES.DN", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "AK Ingress Bounced; Up", - "EventCode": "0x12", - "EventName": "UNC_R2_RING_AK_BOUNCES.UP", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; All", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.ALL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xf", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Counterclockwise", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xc", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CCW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CCW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Clockwise", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x3", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Clockwise and Even", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; All", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.ALL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xf", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Counterclockwise", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xc", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CCW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CCW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Clockwise", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x3", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Clockwise and Even", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 IV Ring in Use; Any", - "EventCode": "0xA", - "EventName": "UNC_R2_RING_IV_USED.ANY", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", - "UMask": "0xf", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 IV Ring in Use; Counterclockwise", - "EventCode": "0xA", - "EventName": "UNC_R2_RING_IV_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", - "UMask": "0xc", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 IV Ring in Use; Clockwise", - "EventCode": "0xA", - "EventName": "UNC_R2_RING_IV_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", - "UMask": "0x3", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; NCB", - "EventCode": "0x10", - "EventName": "UNC_R2_RxR_CYCLES_NE.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; NCS", - "EventCode": "0x10", - "EventName": "UNC_R2_RxR_CYCLES_NE.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Ingress Allocations; NCB", - "EventCode": "0x11", - "EventName": "UNC_R2_RxR_INSERTS.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Ingress Allocations; NCS", - "EventCode": "0x11", - "EventName": "UNC_R2_RxR_INSERTS.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Ingress Occupancy Accumulator; DRS", - "EventCode": "0x13", - "EventName": "UNC_R2_RxR_OCCUPANCY.DRS", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "SBo0 Credits Acquired; For AD Ring", - "EventCode": "0x28", - "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.AD", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "SBo0 Credits Acquired; For BL Ring", - "EventCode": "0x28", - "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.BL", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "SBo0 Credits Occupancy; For AD Ring", - "EventCode": "0x2A", - "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.AD", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "SBo0 Credits Occupancy; For BL Ring", - "EventCode": "0x2A", - "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.BL", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring", - "EventCode": "0x2C", - "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD", - "PerPkg": "1", - "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring", - "EventCode": "0x2C", - "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL", - "PerPkg": "1", - "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring", - "EventCode": "0x2C", - "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD", - "PerPkg": "1", - "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring", - "EventCode": "0x2C", - "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL", - "PerPkg": "1", - "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Full; AD", - "EventCode": "0x25", - "EventName": "UNC_R2_TxR_CYCLES_FULL.AD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AD Egress Queue", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Full; AK", - "EventCode": "0x25", - "EventName": "UNC_R2_TxR_CYCLES_FULL.AK", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AK Egress Queue", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Full; BL", - "EventCode": "0x25", - "EventName": "UNC_R2_TxR_CYCLES_FULL.BL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; BL Egress Queue", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Not Empty; AD", - "EventCode": "0x23", - "EventName": "UNC_R2_TxR_CYCLES_NE.AD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AD Egress Queue", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Not Empty; AK", - "EventCode": "0x23", - "EventName": "UNC_R2_TxR_CYCLES_NE.AK", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AK Egress Queue", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Not Empty; BL", - "EventCode": "0x23", - "EventName": "UNC_R2_TxR_CYCLES_NE.BL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; BL Egress Queue", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress CCW NACK; AD CCW", - "EventCode": "0x26", - "EventName": "UNC_R2_TxR_NACK_CW.DN_AD", - "PerPkg": "1", - "PublicDescription": "AD CounterClockwise Egress Queue", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress CCW NACK; AK CCW", - "EventCode": "0x26", - "EventName": "UNC_R2_TxR_NACK_CW.DN_AK", - "PerPkg": "1", - "PublicDescription": "AK CounterClockwise Egress Queue", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress CCW NACK; BL CCW", - "EventCode": "0x26", - "EventName": "UNC_R2_TxR_NACK_CW.DN_BL", - "PerPkg": "1", - "PublicDescription": "BL CounterClockwise Egress Queue", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress CCW NACK; AK CCW", - "EventCode": "0x26", - "EventName": "UNC_R2_TxR_NACK_CW.UP_AD", - "PerPkg": "1", - "PublicDescription": "BL CounterClockwise Egress Queue", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress CCW NACK; BL CW", - "EventCode": "0x26", - "EventName": "UNC_R2_TxR_NACK_CW.UP_AK", - "PerPkg": "1", - "PublicDescription": "AD Clockwise Egress Queue", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress CCW NACK; BL CCW", - "EventCode": "0x26", - "EventName": "UNC_R2_TxR_NACK_CW.UP_BL", - "PerPkg": "1", - "PublicDescription": "AD CounterClockwise Egress Queue", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Number of uclks in domain", - "EventCode": "0x1", - "EventName": "UNC_R3_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Counts the number of uclks in the QPI uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles.", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x1F", - "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 10", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x1F", - "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 11", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x1F", - "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 12", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x1F", - "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 13", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x1F", - "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14_16", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 14&16", - "UMask": "0x40", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x1F", - "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 8", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x1F", - "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 9", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x1F", - "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO_15_17", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 15&17", - "UMask": "0x80", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x22", - "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 0", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x22", - "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 1", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x22", - "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 2", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x22", - "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 3", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x22", - "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 4", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x22", - "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 5", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x22", - "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 6", - "UMask": "0x40", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x22", - "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 7", - "UMask": "0x80", - "Unit": "R3QPI" - }, - { - "BriefDescription": "HA/R2 AD Credits Empty", - "EventCode": "0x2D", - "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0", - "PerPkg": "1", - "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA0", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "HA/R2 AD Credits Empty", - "EventCode": "0x2D", - "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1", - "PerPkg": "1", - "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA1", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "HA/R2 AD Credits Empty", - "EventCode": "0x2D", - "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB", - "PerPkg": "1", - "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCB Messages", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "HA/R2 AD Credits Empty", - "EventCode": "0x2D", - "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS", - "PerPkg": "1", - "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCS Messages", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "IOT Backpressure", - "EventCode": "0xB", - "EventName": "UNC_R3_IOT_BACKPRESSURE.HUB", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "IOT Backpressure", - "EventCode": "0xB", - "EventName": "UNC_R3_IOT_BACKPRESSURE.SAT", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "IOT Common Trigger Sequencer - Hi", - "EventCode": "0xD", - "EventName": "UNC_R3_IOT_CTS_HI.CTS2", - "PerPkg": "1", - "PublicDescription": "Debug Mask/Match Tie-Ins", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "IOT Common Trigger Sequencer - Hi", - "EventCode": "0xD", - "EventName": "UNC_R3_IOT_CTS_HI.CTS3", - "PerPkg": "1", - "PublicDescription": "Debug Mask/Match Tie-Ins", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "IOT Common Trigger Sequencer - Lo", - "EventCode": "0xC", - "EventName": "UNC_R3_IOT_CTS_LO.CTS0", - "PerPkg": "1", - "PublicDescription": "Debug Mask/Match Tie-Ins", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "IOT Common Trigger Sequencer - Lo", - "EventCode": "0xC", - "EventName": "UNC_R3_IOT_CTS_LO.CTS1", - "PerPkg": "1", - "PublicDescription": "Debug Mask/Match Tie-Ins", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 AD Credits Empty", - "EventCode": "0x20", - "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 HOM Messages", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 AD Credits Empty", - "EventCode": "0x20", - "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 NDR Messages", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 AD Credits Empty", - "EventCode": "0x20", - "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 SNP Messages", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 AD Credits Empty", - "EventCode": "0x20", - "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 HOM Messages", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 AD Credits Empty", - "EventCode": "0x20", - "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 NDR Messages", - "UMask": "0x40", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 AD Credits Empty", - "EventCode": "0x20", - "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 SNP Messages", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 AD Credits Empty", - "EventCode": "0x20", - "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VNA", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 BL Credits Empty", - "EventCode": "0x21", - "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 HOM Messages", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 BL Credits Empty", - "EventCode": "0x21", - "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 NDR Messages", - "UMask": "0x40", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 BL Credits Empty", - "EventCode": "0x21", - "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 SNP Messages", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 BL Credits Empty", - "EventCode": "0x21", - "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VNA", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 AD Credits Empty", - "EventCode": "0x2E", - "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 HOM Messages", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 AD Credits Empty", - "EventCode": "0x2E", - "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 NDR Messages", - "UMask": "0x40", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 AD Credits Empty", - "EventCode": "0x2E", - "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 SNP Messages", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 AD Credits Empty", - "EventCode": "0x2E", - "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VNA", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 BL Credits Empty", - "EventCode": "0x2F", - "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 HOM Messages", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 BL Credits Empty", - "EventCode": "0x2F", - "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 NDR Messages", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 BL Credits Empty", - "EventCode": "0x2F", - "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 SNP Messages", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 BL Credits Empty", - "EventCode": "0x2F", - "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 HOM Messages", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 BL Credits Empty", - "EventCode": "0x2F", - "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 NDR Messages", - "UMask": "0x40", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 BL Credits Empty", - "EventCode": "0x2F", - "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 SNP Messages", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 BL Credits Empty", - "EventCode": "0x2F", - "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VNA", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AD Ring in Use; All", - "EventCode": "0x7", - "EventName": "UNC_R3_RING_AD_USED.ALL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xf", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AD Ring in Use; Counterclockwise", - "EventCode": "0x7", - "EventName": "UNC_R3_RING_AD_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xc", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even", - "EventCode": "0x7", - "EventName": "UNC_R3_RING_AD_USED.CCW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd", - "EventCode": "0x7", - "EventName": "UNC_R3_RING_AD_USED.CCW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AD Ring in Use; Clockwise", - "EventCode": "0x7", - "EventName": "UNC_R3_RING_AD_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x3", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AD Ring in Use; Clockwise and Even", - "EventCode": "0x7", - "EventName": "UNC_R3_RING_AD_USED.CW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd", - "EventCode": "0x7", - "EventName": "UNC_R3_RING_AD_USED.CW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AK Ring in Use; All", - "EventCode": "0x8", - "EventName": "UNC_R3_RING_AK_USED.ALL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xf", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AK Ring in Use; Counterclockwise", - "EventCode": "0x8", - "EventName": "UNC_R3_RING_AK_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xc", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even", - "EventCode": "0x8", - "EventName": "UNC_R3_RING_AK_USED.CCW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd", - "EventCode": "0x8", - "EventName": "UNC_R3_RING_AK_USED.CCW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AK Ring in Use; Clockwise", - "EventCode": "0x8", - "EventName": "UNC_R3_RING_AK_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x3", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AK Ring in Use; Clockwise and Even", - "EventCode": "0x8", - "EventName": "UNC_R3_RING_AK_USED.CW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd", - "EventCode": "0x8", - "EventName": "UNC_R3_RING_AK_USED.CW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 BL Ring in Use; All", - "EventCode": "0x9", - "EventName": "UNC_R3_RING_BL_USED.ALL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xf", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 BL Ring in Use; Counterclockwise", - "EventCode": "0x9", - "EventName": "UNC_R3_RING_BL_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xc", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even", - "EventCode": "0x9", - "EventName": "UNC_R3_RING_BL_USED.CCW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd", - "EventCode": "0x9", - "EventName": "UNC_R3_RING_BL_USED.CCW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 BL Ring in Use; Clockwise", - "EventCode": "0x9", - "EventName": "UNC_R3_RING_BL_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x3", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 BL Ring in Use; Clockwise and Even", - "EventCode": "0x9", - "EventName": "UNC_R3_RING_BL_USED.CW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd", - "EventCode": "0x9", - "EventName": "UNC_R3_RING_BL_USED.CW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 IV Ring in Use; Any", - "EventCode": "0xA", - "EventName": "UNC_R3_RING_IV_USED.ANY", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", - "UMask": "0xf", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 IV Ring in Use; Clockwise", - "EventCode": "0xA", - "EventName": "UNC_R3_RING_IV_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", - "UMask": "0x3", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ring Stop Starved; AK", - "EventCode": "0xE", - "EventName": "UNC_R3_RING_SINK_STARVED.AK", - "PerPkg": "1", - "PublicDescription": "Number of cycles the ringstop is in starvation (per ring)", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; HOM", - "EventCode": "0x10", - "EventName": "UNC_R3_RxR_CYCLES_NE.HOM", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; NDR", - "EventCode": "0x10", - "EventName": "UNC_R3_RxR_CYCLES_NE.NDR", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; SNP", - "EventCode": "0x10", - "EventName": "UNC_R3_RxR_CYCLES_NE.SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Cycles Not Empty; DRS", - "EventCode": "0x14", - "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Cycles Not Empty; HOM", - "EventCode": "0x14", - "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.HOM", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Cycles Not Empty; NCB", - "EventCode": "0x14", - "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Cycles Not Empty; NCS", - "EventCode": "0x14", - "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Cycles Not Empty; NDR", - "EventCode": "0x14", - "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NDR", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Cycles Not Empty; SNP", - "EventCode": "0x14", - "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Allocations; DRS", - "EventCode": "0x11", - "EventName": "UNC_R3_RxR_INSERTS.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Allocations; HOM", - "EventCode": "0x11", - "EventName": "UNC_R3_RxR_INSERTS.HOM", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Allocations; NCB", - "EventCode": "0x11", - "EventName": "UNC_R3_RxR_INSERTS.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Allocations; NCS", - "EventCode": "0x11", - "EventName": "UNC_R3_RxR_INSERTS.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Allocations; NDR", - "EventCode": "0x11", - "EventName": "UNC_R3_RxR_INSERTS.NDR", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Allocations; SNP", - "EventCode": "0x11", - "EventName": "UNC_R3_RxR_INSERTS.SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Allocations; DRS", - "EventCode": "0x15", - "EventName": "UNC_R3_RxR_INSERTS_VN1.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Allocations; HOM", - "EventCode": "0x15", - "EventName": "UNC_R3_RxR_INSERTS_VN1.HOM", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Allocations; NCB", - "EventCode": "0x15", - "EventName": "UNC_R3_RxR_INSERTS_VN1.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Allocations; NCS", - "EventCode": "0x15", - "EventName": "UNC_R3_RxR_INSERTS_VN1.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Allocations; NDR", - "EventCode": "0x15", - "EventName": "UNC_R3_RxR_INSERTS_VN1.NDR", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Allocations; SNP", - "EventCode": "0x15", - "EventName": "UNC_R3_RxR_INSERTS_VN1.SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Occupancy Accumulator; DRS", - "EventCode": "0x13", - "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.DRS", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Occupancy Accumulator; HOM", - "EventCode": "0x13", - "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.HOM", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; HOM Ingress Queue", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Occupancy Accumulator; NCB", - "EventCode": "0x13", - "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCB", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NCB Ingress Queue", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Occupancy Accumulator; NCS", - "EventCode": "0x13", - "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCS", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NCS Ingress Queue", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Occupancy Accumulator; NDR", - "EventCode": "0x13", - "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NDR", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NDR Ingress Queue", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Occupancy Accumulator; SNP", - "EventCode": "0x13", - "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.SNP", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; SNP Ingress Queue", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "SBo0 Credits Acquired; For AD Ring", - "EventCode": "0x28", - "EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.AD", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "SBo0 Credits Acquired; For BL Ring", - "EventCode": "0x28", - "EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.BL", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "SBo0 Credits Occupancy; For AD Ring", - "EventCode": "0x2A", - "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.AD", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "SBo0 Credits Occupancy; For BL Ring", - "EventCode": "0x2A", - "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.BL", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "SBo1 Credits Acquired; For AD Ring", - "EventCode": "0x29", - "EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.AD", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "SBo1 Credits Acquired; For BL Ring", - "EventCode": "0x29", - "EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.BL", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "SBo1 Credits Occupancy; For AD Ring", - "EventCode": "0x2B", - "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.AD", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "SBo1 Credits Occupancy; For BL Ring", - "EventCode": "0x2B", - "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.BL", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring", - "EventCode": "0x2C", - "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_AD", - "PerPkg": "1", - "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring", - "EventCode": "0x2C", - "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_BL", - "PerPkg": "1", - "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring", - "EventCode": "0x2C", - "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_AD", - "PerPkg": "1", - "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring", - "EventCode": "0x2C", - "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_BL", - "PerPkg": "1", - "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Egress CCW NACK; AD CCW", - "EventCode": "0x26", - "EventName": "UNC_R3_TxR_NACK.DN_AD", - "PerPkg": "1", - "PublicDescription": "AD CounterClockwise Egress Queue", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Egress CCW NACK; AK CCW", - "EventCode": "0x26", - "EventName": "UNC_R3_TxR_NACK.DN_AK", - "PerPkg": "1", - "PublicDescription": "AK CounterClockwise Egress Queue", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Egress CCW NACK; BL CCW", - "EventCode": "0x26", - "EventName": "UNC_R3_TxR_NACK.DN_BL", - "PerPkg": "1", - "PublicDescription": "BL CounterClockwise Egress Queue", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Egress CCW NACK; AK CCW", - "EventCode": "0x26", - "EventName": "UNC_R3_TxR_NACK.UP_AD", - "PerPkg": "1", - "PublicDescription": "BL CounterClockwise Egress Queue", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Egress CCW NACK; BL CW", - "EventCode": "0x26", - "EventName": "UNC_R3_TxR_NACK.UP_AK", - "PerPkg": "1", - "PublicDescription": "AD Clockwise Egress Queue", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Egress CCW NACK; BL CCW", - "EventCode": "0x26", - "EventName": "UNC_R3_TxR_NACK.UP_BL", - "PerPkg": "1", - "PublicDescription": "AD CounterClockwise Egress Queue", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class", - "EventCode": "0x37", - "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class", - "EventCode": "0x37", - "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Message Class", - "EventCode": "0x37", - "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Message Class", - "EventCode": "0x37", - "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class", - "EventCode": "0x37", - "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class", - "EventCode": "0x37", - "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Used; DRS Message Class", - "EventCode": "0x36", - "EventName": "UNC_R3_VN0_CREDITS_USED.DRS", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Used; HOM Message Class", - "EventCode": "0x36", - "EventName": "UNC_R3_VN0_CREDITS_USED.HOM", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Used; NCB Message Class", - "EventCode": "0x36", - "EventName": "UNC_R3_VN0_CREDITS_USED.NCB", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Used; NCS Message Class", - "EventCode": "0x36", - "EventName": "UNC_R3_VN0_CREDITS_USED.NCS", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Used; NDR Message Class", - "EventCode": "0x36", - "EventName": "UNC_R3_VN0_CREDITS_USED.NDR", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Used; SNP Message Class", - "EventCode": "0x36", - "EventName": "UNC_R3_VN0_CREDITS_USED.SNP", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Message Class", - "EventCode": "0x39", - "EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Message Class", - "EventCode": "0x39", - "EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCB Message Class", - "EventCode": "0x39", - "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCB", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCS Message Class", - "EventCode": "0x39", - "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCS", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Message Class", - "EventCode": "0x39", - "EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Message Class", - "EventCode": "0x39", - "EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Used; DRS Message Class", - "EventCode": "0x38", - "EventName": "UNC_R3_VN1_CREDITS_USED.DRS", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Used; HOM Message Class", - "EventCode": "0x38", - "EventName": "UNC_R3_VN1_CREDITS_USED.HOM", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Used; NCB Message Class", - "EventCode": "0x38", - "EventName": "UNC_R3_VN1_CREDITS_USED.NCB", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Used; NCS Message Class", - "EventCode": "0x38", - "EventName": "UNC_R3_VN1_CREDITS_USED.NCS", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Used; NDR Message Class", - "EventCode": "0x38", - "EventName": "UNC_R3_VN1_CREDITS_USED.NDR", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Used; SNP Message Class", - "EventCode": "0x38", - "EventName": "UNC_R3_VN1_CREDITS_USED.SNP", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA credit Acquisitions; HOM Message Class", - "EventCode": "0x33", - "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD", - "PerPkg": "1", - "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA credit Acquisitions; HOM Message Class", - "EventCode": "0x33", - "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL", - "PerPkg": "1", - "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA Credit Reject; DRS Message Class", - "EventCode": "0x34", - "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS", - "PerPkg": "1", - "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA Credit Reject; HOM Message Class", - "EventCode": "0x34", - "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM", - "PerPkg": "1", - "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA Credit Reject; NCB Message Class", - "EventCode": "0x34", - "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB", - "PerPkg": "1", - "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA Credit Reject; NCS Message Class", - "EventCode": "0x34", - "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS", - "PerPkg": "1", - "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Standard (NCS).", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA Credit Reject; NDR Message Class", - "EventCode": "0x34", - "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR", - "PerPkg": "1", - "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA Credit Reject; SNP Message Class", - "EventCode": "0x34", - "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP", - "PerPkg": "1", - "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Bounce Control", - "EventCode": "0xA", - "EventName": "UNC_S_BOUNCE_CONTROL", - "PerPkg": "1", - "Unit": "SBO" - }, - { - "BriefDescription": "Uncore Clocks", - "EventName": "UNC_S_CLOCKTICKS", - "PerPkg": "1", - "Unit": "SBO" - }, - { - "BriefDescription": "FaST wire asserted", - "EventCode": "0x9", - "EventName": "UNC_S_FAST_ASSERTED", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", - "Unit": "SBO" - }, - { - "BriefDescription": "AD Ring In Use; All", - "EventCode": "0x1B", - "EventName": "UNC_S_RING_AD_USED.ALL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0xf", - "Unit": "SBO" - }, - { - "BriefDescription": "AD Ring In Use; Down", - "EventCode": "0x1B", - "EventName": "UNC_S_RING_AD_USED.DOWN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0xc", - "Unit": "SBO" - }, - { - "BriefDescription": "AD Ring In Use; Down and Event", - "EventCode": "0x1B", - "EventName": "UNC_S_RING_AD_USED.DOWN_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "AD Ring In Use; Down and Odd", - "EventCode": "0x1B", - "EventName": "UNC_S_RING_AD_USED.DOWN_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "AD Ring In Use; Up", - "EventCode": "0x1B", - "EventName": "UNC_S_RING_AD_USED.UP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x3", - "Unit": "SBO" - }, - { - "BriefDescription": "AD Ring In Use; Up and Even", - "EventCode": "0x1B", - "EventName": "UNC_S_RING_AD_USED.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "AD Ring In Use; Up and Odd", - "EventCode": "0x1B", - "EventName": "UNC_S_RING_AD_USED.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "AK Ring In Use; All", - "EventCode": "0x1C", - "EventName": "UNC_S_RING_AK_USED.ALL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0xf", - "Unit": "SBO" - }, - { - "BriefDescription": "AK Ring In Use; Down", - "EventCode": "0x1C", - "EventName": "UNC_S_RING_AK_USED.DOWN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0xc", - "Unit": "SBO" - }, - { - "BriefDescription": "AK Ring In Use; Down and Event", - "EventCode": "0x1C", - "EventName": "UNC_S_RING_AK_USED.DOWN_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "AK Ring In Use; Down and Odd", - "EventCode": "0x1C", - "EventName": "UNC_S_RING_AK_USED.DOWN_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "AK Ring In Use; Up", - "EventCode": "0x1C", - "EventName": "UNC_S_RING_AK_USED.UP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x3", - "Unit": "SBO" - }, - { - "BriefDescription": "AK Ring In Use; Up and Even", - "EventCode": "0x1C", - "EventName": "UNC_S_RING_AK_USED.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "AK Ring In Use; Up and Odd", - "EventCode": "0x1C", - "EventName": "UNC_S_RING_AK_USED.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "BL Ring in Use; All", - "EventCode": "0x1D", - "EventName": "UNC_S_RING_BL_USED.ALL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0xf", - "Unit": "SBO" - }, - { - "BriefDescription": "BL Ring in Use; Down", - "EventCode": "0x1D", - "EventName": "UNC_S_RING_BL_USED.DOWN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0xc", - "Unit": "SBO" - }, - { - "BriefDescription": "BL Ring in Use; Down and Event", - "EventCode": "0x1D", - "EventName": "UNC_S_RING_BL_USED.DOWN_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "BL Ring in Use; Down and Odd", - "EventCode": "0x1D", - "EventName": "UNC_S_RING_BL_USED.DOWN_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "BL Ring in Use; Up", - "EventCode": "0x1D", - "EventName": "UNC_S_RING_BL_USED.UP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x3", - "Unit": "SBO" - }, - { - "BriefDescription": "BL Ring in Use; Up and Even", - "EventCode": "0x1D", - "EventName": "UNC_S_RING_BL_USED.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "BL Ring in Use; Up and Odd", - "EventCode": "0x1D", - "EventName": "UNC_S_RING_BL_USED.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in BDX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "Number of LLC responses that bounced on the Ring.", - "EventCode": "0x5", - "EventName": "UNC_S_RING_BOUNCES.AD_CACHE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "Number of LLC responses that bounced on the Ring.; Acknowledgements to core", - "EventCode": "0x5", - "EventName": "UNC_S_RING_BOUNCES.AK_CORE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "Number of LLC responses that bounced on the Ring.; Data Responses to core", - "EventCode": "0x5", - "EventName": "UNC_S_RING_BOUNCES.BL_CORE", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.", - "EventCode": "0x5", - "EventName": "UNC_S_RING_BOUNCES.IV_CORE", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "BL Ring in Use; Any", - "EventCode": "0x1E", - "EventName": "UNC_S_RING_IV_USED.DN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. There is only 1 IV ring in HSX. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity", - "UMask": "0xc", - "Unit": "SBO" - }, - { - "BriefDescription": "BL Ring in Use; Any", - "EventCode": "0x1E", - "EventName": "UNC_S_RING_IV_USED.UP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. There is only 1 IV ring in HSX. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity", - "UMask": "0x3", - "Unit": "SBO" - }, - { - "BriefDescription": "UNC_S_RING_SINK_STARVED.AD_CACHE", - "EventCode": "0x6", - "EventName": "UNC_S_RING_SINK_STARVED.AD_CACHE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "UNC_S_RING_SINK_STARVED.AK_CORE", - "EventCode": "0x6", - "EventName": "UNC_S_RING_SINK_STARVED.AK_CORE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "UNC_S_RING_SINK_STARVED.BL_CORE", - "EventCode": "0x6", - "EventName": "UNC_S_RING_SINK_STARVED.BL_CORE", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "UNC_S_RING_SINK_STARVED.IV_CORE", - "EventCode": "0x6", - "EventName": "UNC_S_RING_SINK_STARVED.IV_CORE", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; AD - Bounces", - "EventCode": "0x15", - "EventName": "UNC_S_RxR_BUSY_STARVED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; AD - Credits", - "EventCode": "0x15", - "EventName": "UNC_S_RxR_BUSY_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; BL - Bounces", - "EventCode": "0x15", - "EventName": "UNC_S_RxR_BUSY_STARVED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; BL - Credits", - "EventCode": "0x15", - "EventName": "UNC_S_RxR_BUSY_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "Bypass; AD - Bounces", - "EventCode": "0x12", - "EventName": "UNC_S_RxR_BYPASS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Bypass the Sbo Ingress.", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "Bypass; AD - Credits", - "EventCode": "0x12", - "EventName": "UNC_S_RxR_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Bypass the Sbo Ingress.", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "Bypass; AK", - "EventCode": "0x12", - "EventName": "UNC_S_RxR_BYPASS.AK", - "PerPkg": "1", - "PublicDescription": "Bypass the Sbo Ingress.", - "UMask": "0x10", - "Unit": "SBO" - }, - { - "BriefDescription": "Bypass; BL - Bounces", - "EventCode": "0x12", - "EventName": "UNC_S_RxR_BYPASS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Bypass the Sbo Ingress.", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "Bypass; BL - Credits", - "EventCode": "0x12", - "EventName": "UNC_S_RxR_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Bypass the Sbo Ingress.", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "Bypass; IV", - "EventCode": "0x12", - "EventName": "UNC_S_RxR_BYPASS.IV", - "PerPkg": "1", - "PublicDescription": "Bypass the Sbo Ingress.", - "UMask": "0x20", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; AD - Bounces", - "EventCode": "0x14", - "EventName": "UNC_S_RxR_CRD_STARVED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; AD - Credits", - "EventCode": "0x14", - "EventName": "UNC_S_RxR_CRD_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; AK", - "EventCode": "0x14", - "EventName": "UNC_S_RxR_CRD_STARVED.AK", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", - "UMask": "0x10", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; BL - Bounces", - "EventCode": "0x14", - "EventName": "UNC_S_RxR_CRD_STARVED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; BL - Credits", - "EventCode": "0x14", - "EventName": "UNC_S_RxR_CRD_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; IVF Credit", - "EventCode": "0x14", - "EventName": "UNC_S_RxR_CRD_STARVED.IFV", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", - "UMask": "0x40", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; IV", - "EventCode": "0x14", - "EventName": "UNC_S_RxR_CRD_STARVED.IV", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", - "UMask": "0x20", - "Unit": "SBO" - }, - { - "BriefDescription": "Ingress Allocations; AD - Bounces", - "EventCode": "0x13", - "EventName": "UNC_S_RxR_INSERTS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "Ingress Allocations; AD - Credits", - "EventCode": "0x13", - "EventName": "UNC_S_RxR_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "Ingress Allocations; AK", - "EventCode": "0x13", - "EventName": "UNC_S_RxR_INSERTS.AK", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", - "UMask": "0x10", - "Unit": "SBO" - }, - { - "BriefDescription": "Ingress Allocations; BL - Bounces", - "EventCode": "0x13", - "EventName": "UNC_S_RxR_INSERTS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "Ingress Allocations; BL - Credits", - "EventCode": "0x13", - "EventName": "UNC_S_RxR_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "Ingress Allocations; IV", - "EventCode": "0x13", - "EventName": "UNC_S_RxR_INSERTS.IV", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", - "UMask": "0x20", - "Unit": "SBO" - }, - { - "BriefDescription": "Ingress Occupancy; AD - Bounces", - "EventCode": "0x11", - "EventName": "UNC_S_RxR_OCCUPANCY.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "Ingress Occupancy; AD - Credits", - "EventCode": "0x11", - "EventName": "UNC_S_RxR_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "Ingress Occupancy; AK", - "EventCode": "0x11", - "EventName": "UNC_S_RxR_OCCUPANCY.AK", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", - "UMask": "0x10", - "Unit": "SBO" - }, - { - "BriefDescription": "Ingress Occupancy; BL - Bounces", - "EventCode": "0x11", - "EventName": "UNC_S_RxR_OCCUPANCY.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "Ingress Occupancy; BL - Credits", - "EventCode": "0x11", - "EventName": "UNC_S_RxR_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "Ingress Occupancy; IV", - "EventCode": "0x11", - "EventName": "UNC_S_RxR_OCCUPANCY.IV", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", - "UMask": "0x20", - "Unit": "SBO" - }, - { - "BriefDescription": "UNC_S_TxR_ADS_USED.AD", - "EventCode": "0x4", - "EventName": "UNC_S_TxR_ADS_USED.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "UNC_S_TxR_ADS_USED.AK", - "EventCode": "0x4", - "EventName": "UNC_S_TxR_ADS_USED.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "UNC_S_TxR_ADS_USED.BL", - "EventCode": "0x4", - "EventName": "UNC_S_TxR_ADS_USED.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "Egress Allocations; AD - Bounces", - "EventCode": "0x2", - "EventName": "UNC_S_TxR_INSERTS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "Egress Allocations; AD - Credits", - "EventCode": "0x2", - "EventName": "UNC_S_TxR_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "Egress Allocations; AK", - "EventCode": "0x2", - "EventName": "UNC_S_TxR_INSERTS.AK", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", - "UMask": "0x10", - "Unit": "SBO" - }, - { - "BriefDescription": "Egress Allocations; BL - Bounces", - "EventCode": "0x2", - "EventName": "UNC_S_TxR_INSERTS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "Egress Allocations; BL - Credits", - "EventCode": "0x2", - "EventName": "UNC_S_TxR_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "Egress Allocations; IV", - "EventCode": "0x2", - "EventName": "UNC_S_TxR_INSERTS.IV", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", - "UMask": "0x20", - "Unit": "SBO" - }, - { - "BriefDescription": "Egress Occupancy; AD - Bounces", - "EventCode": "0x1", - "EventName": "UNC_S_TxR_OCCUPANCY.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "Egress Occupancy; AD - Credits", - "EventCode": "0x1", - "EventName": "UNC_S_TxR_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "Egress Occupancy; AK", - "EventCode": "0x1", - "EventName": "UNC_S_TxR_OCCUPANCY.AK", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", - "UMask": "0x10", - "Unit": "SBO" - }, - { - "BriefDescription": "Egress Occupancy; BL - Bounces", - "EventCode": "0x1", - "EventName": "UNC_S_TxR_OCCUPANCY.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "Egress Occupancy; BL - Credits", - "EventCode": "0x1", - "EventName": "UNC_S_TxR_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "Egress Occupancy; IV", - "EventCode": "0x1", - "EventName": "UNC_S_TxR_OCCUPANCY.IV", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", - "UMask": "0x20", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; Onto AD Ring", - "EventCode": "0x3", - "EventName": "UNC_S_TxR_STARVED.AD", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; Onto AK Ring", - "EventCode": "0x3", - "EventName": "UNC_S_TxR_STARVED.AK", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; Onto BL Ring", - "EventCode": "0x3", - "EventName": "UNC_S_TxR_STARVED.BL", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; Onto IV Ring", - "EventCode": "0x3", - "EventName": "UNC_S_TxR_STARVED.IV", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", - "EventCode": "0xff", - "EventName": "UNC_U_CLOCKTICKS", - "PerPkg": "1", - "Unit": "UBOX" - }, - { - "BriefDescription": "VLW Received", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", - "PerPkg": "1", - "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x8", - "Unit": "UBOX" - }, - { - "BriefDescription": "Filter Match", - "EventCode": "0x41", - "EventName": "UNC_U_FILTER_MATCH.DISABLE", - "PerPkg": "1", - "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "Filter Match", - "EventCode": "0x41", - "EventName": "UNC_U_FILTER_MATCH.ENABLE", - "PerPkg": "1", - "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "Filter Match", - "EventCode": "0x41", - "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE", - "PerPkg": "1", - "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x8", - "Unit": "UBOX" - }, - { - "BriefDescription": "Filter Match", - "EventCode": "0x41", - "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE", - "PerPkg": "1", - "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x4", - "Unit": "UBOX" - }, - { - "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", - "EventCode": "0x45", - "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", - "PerPkg": "1", - "PublicDescription": "PHOLD cycles. Filter from source CoreID.", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "RACU Request", - "EventCode": "0x46", - "EventName": "UNC_U_RACU_REQUESTS", - "PerPkg": "1", - "PublicDescription": "Number outstanding register requests within message channel tracker", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Correctable Machine Check", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.CMC", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores", - "UMask": "0x10", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Livelock", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.LIVELOCK", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", - "UMask": "0x4", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; LTError", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.LTERROR", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", - "UMask": "0x8", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Monitor T0", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Monitor T1", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Other", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.OTHER", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores; PREQ, PSMI, P2U, Thermal, PCUSMI, PMI", - "UMask": "0x80", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Trap", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.TRAP", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores", - "UMask": "0x40", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.UMC", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores", - "UMask": "0x20", - "Unit": "UBOX" - } -] -- cgit v1.2.3-58-ga151 From b3eb533ca5c663db8fdd9621b34b3e4c672b70f0 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 13 Apr 2023 06:29:36 -0700 Subject: perf vendor events intel: Fix uncore topics for cascadelakex Remove 'uncore-other' topic classification, move to cache, interconnect, io and memory. Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Edward Baker Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: http://lore.kernel.org/lkml/20230413132949.3487664-9-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/x86/cascadelakex/uncore-cache.json | 10764 ++++++++ .../arch/x86/cascadelakex/uncore-interconnect.json | 11334 ++++++++ .../arch/x86/cascadelakex/uncore-io.json | 4250 +++ .../arch/x86/cascadelakex/uncore-memory.json | 2 +- .../arch/x86/cascadelakex/uncore-other.json | 26344 ------------------- 5 files changed, 26349 insertions(+), 26345 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/cascadelakex/uncore-cache.json create mode 100644 tools/perf/pmu-events/arch/x86/cascadelakex/uncore-interconnect.json create mode 100644 tools/perf/pmu-events/arch/x86/cascadelakex/uncore-io.json delete mode 100644 tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-cache.json b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-cache.json new file mode 100644 index 000000000000..2c880535cc82 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-cache.json @@ -0,0 +1,10764 @@ +[ + { + "BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.ia_miss", + "EventCode": "0x35", + "EventName": "LLC_MISSES.MMIO_READ", + "Filter": "config1=0x40040e33", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss", + "EventCode": "0x35", + "EventName": "LLC_MISSES.MMIO_WRITE", + "Filter": "config1=0x40041e33", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss", + "EventCode": "0x35", + "EventName": "LLC_MISSES.UNCACHEABLE", + "Filter": "config1=0x40e33", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss", + "EventCode": "0x35", + "EventName": "LLC_REFERENCES.STREAMING_FULL", + "Filter": "config1=0x41833", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "ScaleUnit": "64Bytes", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss", + "EventCode": "0x35", + "EventName": "LLC_REFERENCES.STREAMING_PARTIAL", + "Filter": "config1=0x41a33", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "ScaleUnit": "64Bytes", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Bypass; Intermediate bypass Taken", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the intermediate bypass.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Bypass; Not Taken", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Bypass; Taken", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the full bypass.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Uncore cache clock ticks", + "EventName": "UNC_CHA_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts clockticks of the clock controlling the uncore caching and home agent (CHA).", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Clockticks", + "EventCode": "0xC0", + "EventName": "UNC_CHA_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Core PMA Events; C1 State", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.C1_STATE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Core PMA Events; C1 Transition", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.C1_TRANSITION", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Core PMA Events; C6 State", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.C6_STATE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Core PMA Events; C6 Transition", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.C6_TRANSITION", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Core PMA Events; GV", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.GV", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Any Cycle with Multiple Snoops", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0xe2", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Any Single Snoop", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_ONE", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0xe1", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Any Snoop to Remote Node", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0xe4", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Multiple Core Requests", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x42", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Single Core Requests", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.CORE_ONE", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x41", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Core Request to Remote Node", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.CORE_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Multiple Eviction", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x82", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Single Eviction", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x81", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Eviction to Remote Node", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EVICT_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x84", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Multiple External Snoops", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x22", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Single External Snoops", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_ONE", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; External Snoop to Remote Node", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "Counter 0 Occupancy", + "EventCode": "0x1F", + "EventName": "UNC_CHA_COUNTER0_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.", + "Unit": "CHA" + }, + { + "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed", + "EventCode": "0x53", + "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP", + "PerPkg": "1", + "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed", + "EventCode": "0x53", + "EventName": "UNC_CHA_DIR_LOOKUP.SNP", + "PerPkg": "1", + "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe", + "EventCode": "0x54", + "EventName": "UNC_CHA_DIR_UPDATE.HA", + "PerPkg": "1", + "PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe", + "EventCode": "0x54", + "EventName": "UNC_CHA_DIR_UPDATE.TOR", + "PerPkg": "1", + "PublicDescription": "Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements; Down", + "EventCode": "0xAE", + "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements; Up", + "EventCode": "0xAE", + "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "FaST wire asserted; Horizontal", + "EventCode": "0xA5", + "EventName": "UNC_CHA_FAST_ASSERTED.HORZ", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "FaST wire asserted; Vertical", + "EventCode": "0xA5", + "EventName": "UNC_CHA_FAST_ASSERTED.VERT", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.EX_RDS", + "PerPkg": "1", + "PublicDescription": "Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state. This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*)", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; Shared hit and op is RdInvOwn, RdInv, Inv*", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.WBMTOE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*", + "EventCode": "0x5E", + "EventName": "UNC_CHA_HITME_LOOKUP.READ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", + "EventCode": "0x5E", + "EventName": "UNC_CHA_HITME_LOOKUP.WRITE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Misses in HitMe Cache; No SF/LLC HitS/F and op is RdInvOwn", + "EventCode": "0x60", + "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Misses in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*", + "EventCode": "0x60", + "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Misses in HitMe Cache; SF/LLC HitS/F and op is RdInvOwn", + "EventCode": "0x60", + "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Deallocate HitME$ on Reads without RspFwdI*", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a local request", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", + "PerPkg": "1", + "PublicDescription": "Received RspFwdI* for a local request, but converted HitME$ to SF entry", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache on RdInvOwn even if not RspFwdI*", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM", + "PerPkg": "1", + "PublicDescription": "Updated HitME$ on RspFwdI* or local HitM/E received for a remote request", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache to SHARed", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.SHARED", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Left and Even", + "EventCode": "0xA7", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", + "EventCode": "0xA7", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Right and Even", + "EventCode": "0xA7", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", + "EventCode": "0xA7", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Even", + "EventCode": "0xA9", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", + "EventCode": "0xA9", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Right and Even", + "EventCode": "0xA9", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", + "EventCode": "0xA9", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Left and Even", + "EventCode": "0xAB", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", + "EventCode": "0xAB", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Right and Even", + "EventCode": "0xAB", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", + "EventCode": "0xAB", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal IV Ring in Use; Left", + "EventCode": "0xAD", + "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal IV Ring in Use; Right", + "EventCode": "0xAD", + "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Normal priority reads issued to the memory controller from the CHA", + "EventCode": "0x59", + "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", + "PerPkg": "1", + "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "HA to iMC Reads Issued; ISOCH", + "EventCode": "0x59", + "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY", + "PerPkg": "1", + "PublicDescription": "Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", + "PerPkg": "1", + "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Writes Issued to the iMC by the HA; Full Line MIG", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_MIG", + "PerPkg": "1", + "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Full Line", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "PerPkg": "1", + "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Writes Issued to the iMC by the HA; Partial Non-ISOCH", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Writes Issued to the iMC by the HA; Partial MIG", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG", + "PerPkg": "1", + "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.; Filter for memory controller 5 only.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Partial", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "PerPkg": "1", + "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations", + "EventCode": "0x62", + "EventName": "UNC_CHA_IODC_ALLOC.INVITOM", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations dropped due to IODC Full", + "EventCode": "0x62", + "EventName": "UNC_CHA_IODC_ALLOC.IODCFULL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IDOC allocation dropped due to OSB gate", + "EventCode": "0x62", + "EventName": "UNC_CHA_IODC_ALLOC.OSBGATED", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to any reason", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.ALL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to conflicting transaction", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.SNPOUT", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoE", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoI", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOI", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbPushMtoI", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.WBPUSHMTOI", + "PerPkg": "1", + "PublicDescription": "Moved to Cbo section", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Any Request", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Read transactions", + "UMask": "0x3", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Local", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Remote", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.", + "UMask": "0x91", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; External Snoop Request", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ.", + "UMask": "0x9", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Write Requests", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.WRITE", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.", + "UMask": "0x5", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.F_STATE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Local - All Lines", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x2f", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Local - Lines in E State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x22", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Local - Lines in F State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_F", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Local - Lines in M State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Local - Lines in S State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Remote - All Lines", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x8f", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Remote - Lines in E State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x82", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Remote - Lines in F State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_F", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x88", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Remote - Lines in M State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x81", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Remote - Lines in S State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x84", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Lines in E state", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Lines in F State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_F", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Lines in M state", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Lines in S State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc; CV0 Prefetch Miss", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.CV0_PREF_MISS", + "PerPkg": "1", + "PublicDescription": "Miscellaneous events in the Cbo.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc; CV0 Prefetch Victim", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.CV0_PREF_VIC", + "PerPkg": "1", + "PublicDescription": "Miscellaneous events in the Cbo.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Number of times that an RFO hit in S state.", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.RFO_HIT_S", + "PerPkg": "1", + "PublicDescription": "Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc; Silent Snoop Eviction", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE", + "PerPkg": "1", + "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc; Write Combining Aliasing", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.WC_ALIASING", + "PerPkg": "1", + "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB", + "PerPkg": "1", + "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", + "Unit": "CHA" + }, + { + "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in IODC", + "EventCode": "0x64", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.IODC", + "PerPkg": "1", + "PublicDescription": "2LM related events; Counts the number of times CHA saw NM Set conflict in IODC", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in SF/LLC", + "EventCode": "0x64", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC", + "PerPkg": "1", + "PublicDescription": "NM evictions due to another read to the same near memory set in the LLC.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in SF/LLC", + "EventCode": "0x64", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF", + "PerPkg": "1", + "PublicDescription": "NM evictions due to another read to the same near memory set in the SF.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in TOR", + "EventCode": "0x64", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR", + "PerPkg": "1", + "PublicDescription": "No Reject in the CHA due to a pending read to the same near memory set in the TOR.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Memory mode related events; Counts the number of times CHA saw NM Set conflict in TOR and the transaction was rejected", + "EventCode": "0x64", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR_REJECT", + "PerPkg": "1", + "PublicDescription": "Rejects in the CHA due to a pending read to the same near memory set in the TOR.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC0_SMI2", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.EDC0_SMI2", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 2 only.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC1_SMI3", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.EDC1_SMI3", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 3 only.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC2_SMI4", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.EDC2_SMI4", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 4 only.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC3_SMI5", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.EDC3_SMI5", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 5 only.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC0_SMI0", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC0_SMI0", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 0 only.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC1_SMI1", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC1_SMI1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 1 only.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Read requests", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS", + "PerPkg": "1", + "PublicDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) .", + "UMask": "0x3", + "Unit": "CHA" + }, + { + "BriefDescription": "Read requests from a unit on this socket", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Read requests from a remote socket", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Write requests", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES", + "PerPkg": "1", + "PublicDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", + "UMask": "0xc", + "Unit": "CHA" + }, + { + "BriefDescription": "Write Requests from a unit on this socket", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Read and Write Requests; Writes Remote", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD", + "EventCode": "0xA1", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK", + "EventCode": "0xA1", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL", + "EventCode": "0xA1", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV", + "EventCode": "0xA1", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; AD", + "EventCode": "0xA0", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core", + "EventCode": "0xA0", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core", + "EventCode": "0xA0", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.", + "EventCode": "0xA0", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; AD", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; AK", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; BL", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; IV", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; AD", + "EventCode": "0xA2", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core", + "EventCode": "0xA2", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core", + "EventCode": "0xA2", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.", + "EventCode": "0xA2", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Source Throttle", + "EventCode": "0xA4", + "EventName": "UNC_CHA_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; IPQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IPQ", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; IRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IRQ", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; IRQ Rejected", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; PRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.PRQ", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; PRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; RRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.RRQ", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; WBQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.WBQ", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; AD REQ on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; AD RSP on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; Non UPI AK Request", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; BL NCB on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; BL NCS on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; BL RSP on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; BL WB on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; Non UPI IV Request", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; Allow Snoop", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; ANY0", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; HA", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; Merging these two together to make room for ANY_REJECT_*0", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; LLC Victim", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; PhyAddr Match", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; SF Victim", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; Victim", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Merging these two together to make room for ANY_REJECT_*0", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; AD REQ on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; AD RSP on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; Non UPI AK Request", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; BL NCB on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; BL NCS on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; BL RSP on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; BL WB on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; Non UPI IV Request", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; AD REQ on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; AD RSP on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; Non UPI AK Request", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; BL NCB on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; BL NCS on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; BL RSP on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; BL WB on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; Non UPI IV Request", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; ANY0", + "EventCode": "0x25", + "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; HA", + "EventCode": "0x25", + "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; ANY0", + "EventCode": "0x2D", + "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; HA", + "EventCode": "0x2D", + "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy; IPQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ", + "PerPkg": "1", + "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy; IRQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ", + "PerPkg": "1", + "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy; RRQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ", + "PerPkg": "1", + "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy; WBQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ", + "PerPkg": "1", + "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; AD REQ on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; AD RSP on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; Non UPI AK Request", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; BL NCB on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; BL NCS on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; BL RSP on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; BL WB on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; Non UPI IV Request", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; Allow Snoop", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; ANY0", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; HA", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; Merging these two together to make room for ANY_REJECT_*0", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; LLC Victim", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; PhyAddr Match", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; SF Victim", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; Victim", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC OR SF Way", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; AD REQ on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; AD RSP on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; Non UPI AK Request", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; BL NCB on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; BL NCS on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; BL RSP on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; BL WB on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; Non UPI IV Request", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; Allow Snoop", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; ANY0", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; HA", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; Merging these two together to make room for ANY_REJECT_*0", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; LLC Victim", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; PhyAddr Match", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; SF Victim", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; Victim", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; AD REQ on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; AD RSP on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; Non UPI AK Request", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; BL NCB on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; BL NCS on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; BL RSP on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; BL WB on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; Non UPI IV Request", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; Allow Snoop", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; ANY0", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; HA", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; Merging these two together to make room for ANY_REJECT_*0", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; LLC Victim", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; PhyAddr Match", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; SF Victim", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; Victim", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; AD REQ on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; AD RSP on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; Non UPI AK Request", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; BL NCB on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; BL NCS on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; BL RSP on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; BL WB on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; Non UPI IV Request", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; Allow Snoop", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; ANY0", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; HA", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; Merging these two together to make room for ANY_REJECT_*0", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; LLC Victim", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; PhyAddr Match", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; SF Victim", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; Victim", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "EventCode": "0xB4", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "EventCode": "0xB4", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "EventCode": "0xB4", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "EventCode": "0xB4", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AD - Credit", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass; BL - Credit", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; AK - Bounce", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; IFV - Credit", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; IV - Bounce", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AD - Credit", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations; BL - Credit", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop filter capacity evictions for E-state entries.", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.E_STATE", + "PerPkg": "1", + "PublicDescription": "Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop filter capacity evictions for M-state entries.", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.M_STATE", + "PerPkg": "1", + "PublicDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop filter capacity evictions for S-state entries.", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.S_STATE", + "PerPkg": "1", + "PublicDescription": "Counts snoop filter capacity evictions for entries tracking shared lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; All", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of snoops issued by the HA.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; Broadcast snoop for Local Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast snoops issued by the HA. This filter includes only requests coming from local sockets.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; Broadcast snoops for Remote Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast snoops issued by the HA.This filter includes only requests coming from remote sockets.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; Directed snoops for Local Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of directed snoops issued by the HA. This filter includes only requests coming from local sockets.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; Directed snoops for Remote Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of directed snoops issued by the HA. This filter includes only requests coming from remote sockets.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Local Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the local socket.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Remote Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the remote socket.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "RspCnflct* Snoop Responses Received", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCTS", + "PerPkg": "1", + "PublicDescription": "Counts when a a transaction with the opcode type RspCnflct* Snoop Response was received. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent. This triggers conflict resolution hardware. This covers both the opcode RspCnflct and RspCnflctWbI.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received; RspFwd", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD", + "PerPkg": "1", + "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspFwd to a CA request. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "RspI Snoop Responses Received", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPI", + "PerPkg": "1", + "PublicDescription": "Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data).", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "RspIFwd Snoop Responses Received", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD", + "PerPkg": "1", + "PublicDescription": "Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received : RspS", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPS", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received : RspS : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for snoop responses of RspS. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "RspSFwd Snoop Responses Received", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD", + "PerPkg": "1", + "PublicDescription": "Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Rsp*Fwd*WB Snoop Responses Received", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSP_FWD_WB", + "PerPkg": "1", + "PublicDescription": "Counts when a transaction with the opcode type Rsp*Fwd*WB Snoop Response was received which indicates the data was written back to its home socket, and the cacheline was forwarded to the requestor socket. This snoop response is only used in >= 4 socket systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to its home socket to be written back to memory.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Rsp*WB Snoop Responses Received", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB", + "PerPkg": "1", + "PublicDescription": "Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to its home. This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured. This response will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspCnflct", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoops responses of RspConflict to local CA requests. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspFwd", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspFwd to local CA requests. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspI", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoops responses of RspI to local CA requests. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspIFwd", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoop responses of RspIFwd to local CA requests. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspS", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoop responses of RspS to local CA requests. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspSFwd", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspSFwd to local CA requests. This is returned when a remote caching agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of Rsp*Fwd*WB to local CA requests. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; Rsp*WB", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspIWB or RspSWB to local CA requests. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; All", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "UMask": "0xff", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Hits from Local", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ALL_HIT", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x15", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; All from Local iA and IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ALL_IO_IA", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests", + "UMask": "0x35", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Misses from Local", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ALL_MISS", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x25", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; SF/LLC Evictions", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.EVICT", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Hit (Not a Miss)", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.HIT", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; HITs (hit is defined to be not a miss [see below], as a result for any request allocated into the TOR, one of either HIT or MISS must be true)", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; All from Local iA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests from iA Cores", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Hits from Local iA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", + "Filter": "config1=0x40233", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", + "Filter": "config1=0x40433", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", + "Filter": "config1=0x4b233", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", + "Filter": "config1=0x4b433", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefRFO", + "Filter": "config1=0x4b033", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", + "Filter": "config1=0x40033", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "Filter": "config1=0x40233", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Filter": "config1=0x40433", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", + "Filter": "config1=0x4b233", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", + "Filter": "config1=0x4b433", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefRFO", + "Filter": "config1=0x4b033", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", + "Filter": "config1=0x40033", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; All from Local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally generated IO traffic", + "UMask": "0x34", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Hits from Local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x14", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Misses from Local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; ItoM misses from Local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Filter": "config1=0x49033", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that are generated from local IO ItoM requests that miss the LLC. An ItoM request is used by IIO to request a data write without first reading the data for ownership.", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; RdCur misses from Local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RDCUR", + "Filter": "config1=0x43C33", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that are generated from local IO RdCur requests and miss the LLC. A RdCur request is used by IIO to read data without changing state.", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; RFO misses from Local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "Filter": "config1=0x40033", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that are generated from local IO RFO requests that miss the LLC. A read for ownership (RFO) requests a cache line to be cached in E state with the intent to modify.", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; IPQ", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IPQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IPQ_HIT", + "PerPkg": "1", + "UMask": "0x18", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IPQ_MISS", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; IRQ", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IRQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", + "PerPkg": "1", + "UMask": "0x37", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Miss", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.MISS", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; Misses. (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to a local memory controller, in the event that the CHA is the home node)). Basically, if the LLC/SF/MLC complex were not able to service the request without involving another agent...it is a miss. If only IDI snoops were required, it is not a miss (that means the SF/MLC com", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; PRQ", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.PRQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL", + "PerPkg": "1", + "UMask": "0x30", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.RRQ_HIT", + "PerPkg": "1", + "UMask": "0x50", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS", + "PerPkg": "1", + "UMask": "0x60", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.WBQ_HIT", + "PerPkg": "1", + "UMask": "0x90", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.WBQ_MISS", + "PerPkg": "1", + "UMask": "0xa0", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xff", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; All from Local", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All remotely generated requests", + "UMask": "0x37", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Hits from Local", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_HIT", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "UMask": "0x17", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Misses from Local", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_MISS", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "UMask": "0x27", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; SF/LLC Evictions", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Hit (Not a Miss)", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; HITs (hit is defined to be not a miss [see below], as a result for any request allocated into the TOR, one of either HIT or MISS must be true)", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; All from Local iA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; All locally initiated requests from iA Cores", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Hits from Local iA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "Filter": "config1=0x40233", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "Filter": "config1=0x40433", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", + "Filter": "config1=0x4b233", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", + "Filter": "config1=0x4b433", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", + "Filter": "config1=0x4b033", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "Filter": "config1=0x40033", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Misses from Local iA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "Filter": "config1=0x40233", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Filter": "config1=0x40433", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", + "Filter": "config1=0x4b233", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", + "Filter": "config1=0x4b433", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", + "Filter": "config1=0x4b033", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "Filter": "config1=0x40033", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; All from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; All locally generated IO traffic", + "UMask": "0x34", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Hits from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "UMask": "0x14", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Misses from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; ITOM Misses from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", + "Filter": "config1=0x49033", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO ItoM requests that miss the LLC. An ItoM is used by IIO to request a data write without first reading the data for ownership.", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; RDCUR misses from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RDCUR", + "Filter": "config1=0x43C33", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO RdCur requests that miss the LLC. A RdCur request is used by IIO to read data without changing state.", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; RFO misses from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", + "Filter": "config1=0x40033", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO RFO requests that miss the LLC. A read for ownership (RFO) requests data to be cached in E state with the intent to modify.", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; IPQ", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_HIT", + "PerPkg": "1", + "UMask": "0x18", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_MISS", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; IRQ", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", + "PerPkg": "1", + "UMask": "0x37", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Miss", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; Misses. (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to a local memory controller, in the event that the CHA is the home node)). Basically, if the LLC/SF/MLC complex were not able to service the request without involving another agent...it is a miss. If only IDI snoops were required, it is not a miss (that means the SF/MLC com", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; PRQ", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; IV", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.IV", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.IV", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; IV", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.IV", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; IV", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.IV", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; IV", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.IV", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; AD REQ Credits", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; AD RSP VN0 Credits", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; BL NCB Credits", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; BL NCS Credits", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; BL RSP Credits", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; BL DRS Credits", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_WB", + "PerPkg": "1", + "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; VN0 Credits", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; VNA Credits", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VNA", + "PerPkg": "1", + "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; AD REQ VN0 Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_REQ", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; AD RSP VN0 Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_RSP", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCB VN0 Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCB", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCS VN0 Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCS", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL RSP VN0 Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_RSP", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL DRS VN0 Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_WB", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; AD VNA Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_AD", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL VNA Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_BL", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Down and Even", + "EventCode": "0xA6", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Down and Odd", + "EventCode": "0xA6", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Up and Even", + "EventCode": "0xA6", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Up and Odd", + "EventCode": "0xA6", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Down and Even", + "EventCode": "0xA8", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Down and Odd", + "EventCode": "0xA8", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Up and Even", + "EventCode": "0xA8", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Up and Odd", + "EventCode": "0xA8", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Down and Even", + "EventCode": "0xAA", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Down and Odd", + "EventCode": "0xAA", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Up and Even", + "EventCode": "0xAA", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Up and Odd", + "EventCode": "0xAA", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical IV Ring in Use; Down", + "EventCode": "0xAC", + "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical IV Ring in Use; Up", + "EventCode": "0xAC", + "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "WbPushMtoI; Pushed to LLC", + "EventCode": "0x56", + "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when the CHA was received WbPushMtoI; Counts the number of times when the CHA was able to push WbPushMToI to LLC", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "WbPushMtoI; Pushed to Memory", + "EventCode": "0x56", + "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when the CHA was received WbPushMtoI; Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC0_SMI2", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 2 only.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC1_SMI3", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 3 only.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC2_SMI4", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 4 only.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC3_SMI5", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 5 only.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC0_SMI0", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 0 only.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC1_SMI1", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 1 only.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Any RspIFwdFE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response I to Fwd F/E", + "UMask": "0xe4", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response I to Fwd M", + "UMask": "0xf0", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdFE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response S to Fwd F/E", + "UMask": "0xe2", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdM", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response S to Fwd M", + "UMask": "0xe8", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Any RspHitFSE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response any to Hit F/S/E", + "UMask": "0xe1", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdFE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response I to Fwd F/E", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdM", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response I to Fwd M", + "UMask": "0x50", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdFE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response S to Fwd F/E", + "UMask": "0x42", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdM", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response S to Fwd M", + "UMask": "0x48", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Core RspHitFSE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response any to Hit F/S/E", + "UMask": "0x41", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdFE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response I to Fwd F/E", + "UMask": "0x84", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdM", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response I to Fwd M", + "UMask": "0x90", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdFE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response S to Fwd F/E", + "UMask": "0x82", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdM", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response S to Fwd M", + "UMask": "0x88", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Evict RspHitFSE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response any to Hit F/S/E", + "UMask": "0x81", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; External RspIFwdFE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response I to Fwd F/E", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; External RspIFwdM", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response I to Fwd M", + "UMask": "0x30", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; External RspSFwdFE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response S to Fwd F/E", + "UMask": "0x22", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; External RspSFwdM", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response S to Fwd M", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; External RspHitFSE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response any to Hit F/S/E", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CLOCKTICKS", + "Deprecated": "1", + "EventName": "UNC_C_CLOCKTICKS", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_FAST_ASSERTED.HORZ", + "Deprecated": "1", + "EventCode": "0xA5", + "EventName": "UNC_C_FAST_ASSERTED", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.ANY", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.ANY", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.DATA_READ", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOCAL", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.LOCAL", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.REMOTE", + "PerPkg": "1", + "UMask": "0x91", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITE", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.WRITE", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.E_STATE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.F_STATE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.LOCAL", + "PerPkg": "1", + "UMask": "0x2f", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.M_STATE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.REMOTE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.S_STATE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SRC_THRTL", + "Deprecated": "1", + "EventCode": "0xA4", + "EventName": "UNC_C_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.EVICT", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.EVICT", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.HIT", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.HIT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IPQ", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IPQ", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IPQ_HIT", + "PerPkg": "1", + "UMask": "0x18", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IPQ_MISS", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IRQ", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IRQ_HIT", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IRQ_MISS", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.LOC_ALL", + "PerPkg": "1", + "UMask": "0x37", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.LOC_IA", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.LOC_IO", + "PerPkg": "1", + "UMask": "0x34", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.MISS", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.PRQ", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.PRQ", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_HIT", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.PRQ_HIT", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_MISS", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.PRQ_MISS", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.REM_ALL", + "PerPkg": "1", + "UMask": "0x30", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.RRQ_HIT", + "PerPkg": "1", + "UMask": "0x50", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.RRQ_MISS", + "PerPkg": "1", + "UMask": "0x60", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.WBQ_HIT", + "PerPkg": "1", + "UMask": "0x90", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.WBQ_MISS", + "PerPkg": "1", + "UMask": "0xa0", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.EVICT", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.EVICT", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.HIT", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.HIT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IPQ", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IPQ", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_HIT", + "PerPkg": "1", + "UMask": "0x18", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_MISS", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IRQ", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_HIT", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_HIT", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_MISS", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_MISS", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.LOC_ALL", + "PerPkg": "1", + "UMask": "0x37", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IA", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IO", + "PerPkg": "1", + "UMask": "0x34", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.MISS", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.PRQ", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.PRQ", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_HIT", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_MISS", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0", + "Deprecated": "1", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1", + "Deprecated": "1", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2", + "Deprecated": "1", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3", + "Deprecated": "1", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4", + "Deprecated": "1", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5", + "Deprecated": "1", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0", + "Deprecated": "1", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1", + "Deprecated": "1", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2", + "Deprecated": "1", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3", + "Deprecated": "1", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4", + "Deprecated": "1", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5", + "Deprecated": "1", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0", + "Deprecated": "1", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1", + "Deprecated": "1", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2", + "Deprecated": "1", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3", + "Deprecated": "1", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4", + "Deprecated": "1", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5", + "Deprecated": "1", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0", + "Deprecated": "1", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1", + "Deprecated": "1", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2", + "Deprecated": "1", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3", + "Deprecated": "1", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4", + "Deprecated": "1", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5", + "Deprecated": "1", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0", + "Deprecated": "1", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1", + "Deprecated": "1", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2", + "Deprecated": "1", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3", + "Deprecated": "1", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4", + "Deprecated": "1", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5", + "Deprecated": "1", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0", + "Deprecated": "1", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1", + "Deprecated": "1", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2", + "Deprecated": "1", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3", + "Deprecated": "1", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4", + "Deprecated": "1", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5", + "Deprecated": "1", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0", + "Deprecated": "1", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1", + "Deprecated": "1", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2", + "Deprecated": "1", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3", + "Deprecated": "1", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4", + "Deprecated": "1", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5", + "Deprecated": "1", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", + "Deprecated": "1", + "EventCode": "0x57", + "EventName": "UNC_H_BYPASS_CHA_IMC.INTERMEDIATE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", + "Deprecated": "1", + "EventCode": "0x57", + "EventName": "UNC_H_BYPASS_CHA_IMC.NOT_TAKEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.TAKEN", + "Deprecated": "1", + "EventCode": "0x57", + "EventName": "UNC_H_BYPASS_CHA_IMC.TAKEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CMS_CLOCKTICKS", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_H_CLOCK", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C1_STATE", + "Deprecated": "1", + "EventCode": "0x17", + "EventName": "UNC_H_CORE_PMA.C1_STATE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C1_TRANSITION", + "Deprecated": "1", + "EventCode": "0x17", + "EventName": "UNC_H_CORE_PMA.C1_TRANSITION", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C6_STATE", + "Deprecated": "1", + "EventCode": "0x17", + "EventName": "UNC_H_CORE_PMA.C6_STATE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C6_TRANSITION", + "Deprecated": "1", + "EventCode": "0x17", + "EventName": "UNC_H_CORE_PMA.C6_TRANSITION", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.GV", + "Deprecated": "1", + "EventCode": "0x17", + "EventName": "UNC_H_CORE_PMA.GV", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_GTONE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.ANY_GTONE", + "PerPkg": "1", + "UMask": "0xe2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_ONE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.ANY_ONE", + "PerPkg": "1", + "UMask": "0xe1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_REMOTE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.ANY_REMOTE", + "PerPkg": "1", + "UMask": "0xe4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.CORE_GTONE", + "PerPkg": "1", + "UMask": "0x42", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_ONE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.CORE_ONE", + "PerPkg": "1", + "UMask": "0x41", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_REMOTE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.CORE_REMOTE", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.EVICT_GTONE", + "PerPkg": "1", + "UMask": "0x82", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_ONE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.EVICT_ONE", + "PerPkg": "1", + "UMask": "0x81", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_REMOTE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.EVICT_REMOTE", + "PerPkg": "1", + "UMask": "0x84", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_GTONE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.EXT_GTONE", + "PerPkg": "1", + "UMask": "0x22", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_ONE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.EXT_ONE", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_REMOTE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.EXT_REMOTE", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_COUNTER0_OCCUPANCY", + "Deprecated": "1", + "EventCode": "0x1F", + "EventName": "UNC_H_COUNTER0_OCCUPANCY", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP", + "Deprecated": "1", + "EventCode": "0x53", + "EventName": "UNC_H_DIR_LOOKUP.NO_SNP", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP", + "Deprecated": "1", + "EventCode": "0x53", + "EventName": "UNC_H_DIR_LOOKUP.SNP", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA", + "Deprecated": "1", + "EventCode": "0x54", + "EventName": "UNC_H_DIR_UPDATE.HA", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR", + "Deprecated": "1", + "EventCode": "0x54", + "EventName": "UNC_H_DIR_UPDATE.TOR", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Deprecated": "1", + "EventCode": "0xAE", + "EventName": "UNC_H_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Deprecated": "1", + "EventCode": "0xAE", + "EventName": "UNC_H_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS", + "Deprecated": "1", + "EventCode": "0x5F", + "EventName": "UNC_H_HITME_HIT.EX_RDS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.SHARED_OWNREQ", + "Deprecated": "1", + "EventCode": "0x5F", + "EventName": "UNC_H_HITME_HIT.SHARED_OWNREQ", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.WBMTOE", + "Deprecated": "1", + "EventCode": "0x5F", + "EventName": "UNC_H_HITME_HIT.WBMTOE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.WBMTOI_OR_S", + "Deprecated": "1", + "EventCode": "0x5F", + "EventName": "UNC_H_HITME_HIT.WBMTOI_OR_S", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_LOOKUP.READ", + "Deprecated": "1", + "EventCode": "0x5E", + "EventName": "UNC_H_HITME_LOOKUP.READ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_LOOKUP.WRITE", + "Deprecated": "1", + "EventCode": "0x5E", + "EventName": "UNC_H_HITME_LOOKUP.WRITE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN", + "Deprecated": "1", + "EventCode": "0x60", + "EventName": "UNC_H_HITME_MISS.NOTSHARED_RDINVOWN", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.READ_OR_INV", + "Deprecated": "1", + "EventCode": "0x60", + "EventName": "UNC_H_HITME_MISS.READ_OR_INV", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.SHARED_RDINVOWN", + "Deprecated": "1", + "EventCode": "0x60", + "EventName": "UNC_H_HITME_MISS.SHARED_RDINVOWN", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.DEALLOCATE", + "Deprecated": "1", + "EventCode": "0x61", + "EventName": "UNC_H_HITME_UPDATE.DEALLOCATE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", + "Deprecated": "1", + "EventCode": "0x61", + "EventName": "UNC_H_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.RDINVOWN", + "Deprecated": "1", + "EventCode": "0x61", + "EventName": "UNC_H_HITME_UPDATE.RDINVOWN", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.RSPFWDI_REM", + "Deprecated": "1", + "EventCode": "0x61", + "EventName": "UNC_H_HITME_UPDATE.RSPFWDI_REM", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.SHARED", + "Deprecated": "1", + "EventCode": "0x61", + "EventName": "UNC_H_HITME_UPDATE.SHARED", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "Deprecated": "1", + "EventCode": "0xA7", + "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", + "Deprecated": "1", + "EventCode": "0xA7", + "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "Deprecated": "1", + "EventCode": "0xA7", + "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "Deprecated": "1", + "EventCode": "0xA7", + "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "Deprecated": "1", + "EventCode": "0xA9", + "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", + "Deprecated": "1", + "EventCode": "0xA9", + "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "Deprecated": "1", + "EventCode": "0xA9", + "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "Deprecated": "1", + "EventCode": "0xA9", + "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "Deprecated": "1", + "EventCode": "0xAB", + "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", + "Deprecated": "1", + "EventCode": "0xAB", + "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "Deprecated": "1", + "EventCode": "0xAB", + "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "Deprecated": "1", + "EventCode": "0xAB", + "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", + "Deprecated": "1", + "EventCode": "0xAD", + "EventName": "UNC_H_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", + "Deprecated": "1", + "EventCode": "0xAD", + "EventName": "UNC_H_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_READS_COUNT.NORMAL", + "Deprecated": "1", + "EventCode": "0x59", + "EventName": "UNC_H_IMC_READS_COUNT.NORMAL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_READS_COUNT.PRIORITY", + "Deprecated": "1", + "EventCode": "0x59", + "EventName": "UNC_H_IMC_READS_COUNT.PRIORITY", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL", + "Deprecated": "1", + "EventCode": "0x5B", + "EventName": "UNC_H_IMC_WRITES_COUNT.FULL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL_MIG", + "Deprecated": "1", + "EventCode": "0x5B", + "EventName": "UNC_H_IMC_WRITES_COUNT.FULL_MIG", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "Deprecated": "1", + "EventCode": "0x5B", + "EventName": "UNC_H_IMC_WRITES_COUNT.FULL_PRIORITY", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "Deprecated": "1", + "EventCode": "0x5B", + "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG", + "Deprecated": "1", + "EventCode": "0x5B", + "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL_MIG", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "Deprecated": "1", + "EventCode": "0x5B", + "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.INVITOM", + "Deprecated": "1", + "EventCode": "0x62", + "EventName": "UNC_H_IODC_ALLOC.INVITOM", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.IODCFULL", + "Deprecated": "1", + "EventCode": "0x62", + "EventName": "UNC_H_IODC_ALLOC.IODCFULL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.OSBGATED", + "Deprecated": "1", + "EventCode": "0x62", + "EventName": "UNC_H_IODC_ALLOC.OSBGATED", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.ALL", + "Deprecated": "1", + "EventCode": "0x63", + "EventName": "UNC_H_IODC_DEALLOC.ALL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.SNPOUT", + "Deprecated": "1", + "EventCode": "0x63", + "EventName": "UNC_H_IODC_DEALLOC.SNPOUT", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBMTOE", + "Deprecated": "1", + "EventCode": "0x63", + "EventName": "UNC_H_IODC_DEALLOC.WBMTOE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBMTOI", + "Deprecated": "1", + "EventCode": "0x63", + "EventName": "UNC_H_IODC_DEALLOC.WBMTOI", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBPUSHMTOI", + "Deprecated": "1", + "EventCode": "0x63", + "EventName": "UNC_H_IODC_DEALLOC.WBPUSHMTOI", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.CV0_PREF_MISS", + "Deprecated": "1", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.CV0_PREF_MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.CV0_PREF_VIC", + "Deprecated": "1", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.CV0_PREF_VIC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S", + "Deprecated": "1", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.RFO_HIT_S", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RSPI_WAS_FSE", + "Deprecated": "1", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.RSPI_WAS_FSE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.WC_ALIASING", + "Deprecated": "1", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.WC_ALIASING", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_OSB", + "Deprecated": "1", + "EventCode": "0x55", + "EventName": "UNC_H_OSB", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC0_SMI2", + "Deprecated": "1", + "EventCode": "0x58", + "EventName": "UNC_H_READ_NO_CREDITS.EDC0_SMI2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC1_SMI3", + "Deprecated": "1", + "EventCode": "0x58", + "EventName": "UNC_H_READ_NO_CREDITS.EDC1_SMI3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC2_SMI4", + "Deprecated": "1", + "EventCode": "0x58", + "EventName": "UNC_H_READ_NO_CREDITS.EDC2_SMI4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC3_SMI5", + "Deprecated": "1", + "EventCode": "0x58", + "EventName": "UNC_H_READ_NO_CREDITS.EDC3_SMI5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.MC0_SMI0", + "Deprecated": "1", + "EventCode": "0x58", + "EventName": "UNC_H_READ_NO_CREDITS.MC0_SMI0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.MC1_SMI1", + "Deprecated": "1", + "EventCode": "0x58", + "EventName": "UNC_H_READ_NO_CREDITS.MC1_SMI1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "read requests from home agent", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.READS", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "CHA" + }, + { + "BriefDescription": "read requests from local home agent", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.READS_LOCAL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "read requests from remote home agent", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.READS_REMOTE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "write requests from home agent", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.WRITES", + "PerPkg": "1", + "UMask": "0xc", + "Unit": "CHA" + }, + { + "BriefDescription": "write requests from local home agent", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.WRITES_LOCAL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "write requests from remote home agent", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.WRITES_REMOTE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.AD", + "Deprecated": "1", + "EventCode": "0xA1", + "EventName": "UNC_H_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.AK", + "Deprecated": "1", + "EventCode": "0xA1", + "EventName": "UNC_H_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.BL", + "Deprecated": "1", + "EventCode": "0xA1", + "EventName": "UNC_H_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.IV", + "Deprecated": "1", + "EventCode": "0xA1", + "EventName": "UNC_H_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.AD", + "Deprecated": "1", + "EventCode": "0xA0", + "EventName": "UNC_H_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.AK", + "Deprecated": "1", + "EventCode": "0xA0", + "EventName": "UNC_H_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.BL", + "Deprecated": "1", + "EventCode": "0xA0", + "EventName": "UNC_H_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.IV", + "Deprecated": "1", + "EventCode": "0xA0", + "EventName": "UNC_H_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AD", + "Deprecated": "1", + "EventCode": "0xA3", + "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AK", + "Deprecated": "1", + "EventCode": "0xA3", + "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", + "Deprecated": "1", + "EventCode": "0xA3", + "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.BL", + "Deprecated": "1", + "EventCode": "0xA3", + "EventName": "UNC_H_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.IV", + "Deprecated": "1", + "EventCode": "0xA3", + "EventName": "UNC_H_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.AD", + "Deprecated": "1", + "EventCode": "0xA2", + "EventName": "UNC_H_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.AK", + "Deprecated": "1", + "EventCode": "0xA2", + "EventName": "UNC_H_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.BL", + "Deprecated": "1", + "EventCode": "0xA2", + "EventName": "UNC_H_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.IV", + "Deprecated": "1", + "EventCode": "0xA2", + "EventName": "UNC_H_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IPQ", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.IPQ", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.IRQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ_REJ", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.IRQ_REJ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.PRQ", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.PRQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.PRQ_REJ", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.PRQ_REJ", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.RRQ", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.RRQ", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.WBQ", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.WBQ", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x22", + "EventName": "UNC_H_RxC_IPQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x22", + "EventName": "UNC_H_RxC_IPQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x22", + "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x22", + "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x22", + "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x22", + "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ANY0", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.ANY_IPQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.HA", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.VICTIM", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x18", + "EventName": "UNC_H_RxC_IRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x18", + "EventName": "UNC_H_RxC_IRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x18", + "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x18", + "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x18", + "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x18", + "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ANY0", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.ANY_REJECT_IRQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.HA", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.VICTIM", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x24", + "EventName": "UNC_H_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x24", + "EventName": "UNC_H_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x24", + "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x24", + "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x24", + "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x24", + "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x2C", + "EventName": "UNC_H_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x2C", + "EventName": "UNC_H_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x2C", + "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x2C", + "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x2C", + "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x2C", + "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.ANY0", + "Deprecated": "1", + "EventCode": "0x25", + "EventName": "UNC_H_RxC_ISMQ1_REJECT.ANY_ISMQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.HA", + "Deprecated": "1", + "EventCode": "0x25", + "EventName": "UNC_H_RxC_ISMQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.ANY0", + "Deprecated": "1", + "EventCode": "0x2D", + "EventName": "UNC_H_RxC_ISMQ1_RETRY.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.HA", + "Deprecated": "1", + "EventCode": "0x2D", + "EventName": "UNC_H_RxC_ISMQ1_RETRY.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IPQ", + "Deprecated": "1", + "EventCode": "0x11", + "EventName": "UNC_H_RxC_OCCUPANCY.IPQ", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ", + "Deprecated": "1", + "EventCode": "0x11", + "EventName": "UNC_H_RxC_OCCUPANCY.IRQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.RRQ", + "Deprecated": "1", + "EventCode": "0x11", + "EventName": "UNC_H_RxC_OCCUPANCY.RRQ", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.WBQ", + "Deprecated": "1", + "EventCode": "0x11", + "EventName": "UNC_H_RxC_OCCUPANCY.WBQ", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x2E", + "EventName": "UNC_H_RxC_OTHER0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x2E", + "EventName": "UNC_H_RxC_OTHER0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x2E", + "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x2E", + "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x2E", + "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x2E", + "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ANY0", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.HA", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.VICTIM", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x20", + "EventName": "UNC_H_RxC_PRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x20", + "EventName": "UNC_H_RxC_PRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x20", + "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x20", + "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x20", + "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x20", + "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ANY0", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.ANY_PRQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.HA", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.VICTIM", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x2A", + "EventName": "UNC_H_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x2A", + "EventName": "UNC_H_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x2A", + "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x2A", + "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x2A", + "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x2A", + "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.HA", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x26", + "EventName": "UNC_H_RxC_RRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x26", + "EventName": "UNC_H_RxC_RRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x26", + "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x26", + "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x26", + "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x26", + "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ANY0", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.ANY_RRQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.HA", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.VICTIM", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x28", + "EventName": "UNC_H_RxC_WBQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x28", + "EventName": "UNC_H_RxC_WBQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x28", + "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x28", + "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x28", + "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x28", + "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ANY0", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.ANY_WBQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.HA", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.VICTIM", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.AD_BNC", + "Deprecated": "1", + "EventCode": "0xB4", + "EventName": "UNC_H_RxR_BUSY_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.AD_CRD", + "Deprecated": "1", + "EventCode": "0xB4", + "EventName": "UNC_H_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.BL_BNC", + "Deprecated": "1", + "EventCode": "0xB4", + "EventName": "UNC_H_RxR_BUSY_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.BL_CRD", + "Deprecated": "1", + "EventCode": "0xB4", + "EventName": "UNC_H_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AD_BNC", + "Deprecated": "1", + "EventCode": "0xB2", + "EventName": "UNC_H_RxR_BYPASS.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AD_CRD", + "Deprecated": "1", + "EventCode": "0xB2", + "EventName": "UNC_H_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AK_BNC", + "Deprecated": "1", + "EventCode": "0xB2", + "EventName": "UNC_H_RxR_BYPASS.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.BL_BNC", + "Deprecated": "1", + "EventCode": "0xB2", + "EventName": "UNC_H_RxR_BYPASS.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.BL_CRD", + "Deprecated": "1", + "EventCode": "0xB2", + "EventName": "UNC_H_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.IV_BNC", + "Deprecated": "1", + "EventCode": "0xB2", + "EventName": "UNC_H_RxR_BYPASS.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AD_BNC", + "Deprecated": "1", + "EventCode": "0xB3", + "EventName": "UNC_H_RxR_CRD_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AD_CRD", + "Deprecated": "1", + "EventCode": "0xB3", + "EventName": "UNC_H_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AK_BNC", + "Deprecated": "1", + "EventCode": "0xB3", + "EventName": "UNC_H_RxR_CRD_STARVED.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.BL_BNC", + "Deprecated": "1", + "EventCode": "0xB3", + "EventName": "UNC_H_RxR_CRD_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.BL_CRD", + "Deprecated": "1", + "EventCode": "0xB3", + "EventName": "UNC_H_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.IFV", + "Deprecated": "1", + "EventCode": "0xB3", + "EventName": "UNC_H_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.IV_BNC", + "Deprecated": "1", + "EventCode": "0xB3", + "EventName": "UNC_H_RxR_CRD_STARVED.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AD_BNC", + "Deprecated": "1", + "EventCode": "0xB1", + "EventName": "UNC_H_RxR_INSERTS.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AD_CRD", + "Deprecated": "1", + "EventCode": "0xB1", + "EventName": "UNC_H_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AK_BNC", + "Deprecated": "1", + "EventCode": "0xB1", + "EventName": "UNC_H_RxR_INSERTS.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.BL_BNC", + "Deprecated": "1", + "EventCode": "0xB1", + "EventName": "UNC_H_RxR_INSERTS.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.BL_CRD", + "Deprecated": "1", + "EventCode": "0xB1", + "EventName": "UNC_H_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.IV_BNC", + "Deprecated": "1", + "EventCode": "0xB1", + "EventName": "UNC_H_RxR_INSERTS.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AD_BNC", + "Deprecated": "1", + "EventCode": "0xB0", + "EventName": "UNC_H_RxR_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AD_CRD", + "Deprecated": "1", + "EventCode": "0xB0", + "EventName": "UNC_H_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AK_BNC", + "Deprecated": "1", + "EventCode": "0xB0", + "EventName": "UNC_H_RxR_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.BL_BNC", + "Deprecated": "1", + "EventCode": "0xB0", + "EventName": "UNC_H_RxR_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.BL_CRD", + "Deprecated": "1", + "EventCode": "0xB0", + "EventName": "UNC_H_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.IV_BNC", + "Deprecated": "1", + "EventCode": "0xB0", + "EventName": "UNC_H_RxR_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.E_STATE", + "Deprecated": "1", + "EventCode": "0x3D", + "EventName": "UNC_H_SF_EVICTION.E_STATE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.M_STATE", + "Deprecated": "1", + "EventCode": "0x3D", + "EventName": "UNC_H_SF_EVICTION.M_STATE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.S_STATE", + "Deprecated": "1", + "EventCode": "0x3D", + "EventName": "UNC_H_SF_EVICTION.S_STATE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.ALL", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_LOCAL", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.BCST_LOC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_REMOTE", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.BCST_REM", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.DIRECT_LOC", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.DIRECT_REM", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.LOCAL", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.LOCAL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.REMOTE", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.REMOTE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPCNFLCTS", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPFWD", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPFWD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPI", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPI", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPIFWD", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPS", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_WBWB", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSP_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPCNFLCT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPFWD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPI", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPI", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPIFWD", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPS", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPSFWD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_FWD_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "Deprecated": "1", + "EventCode": "0xD0", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "Deprecated": "1", + "EventCode": "0xD0", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "Deprecated": "1", + "EventCode": "0xD0", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "Deprecated": "1", + "EventCode": "0xD0", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "Deprecated": "1", + "EventCode": "0xD0", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "Deprecated": "1", + "EventCode": "0xD0", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "Deprecated": "1", + "EventCode": "0xD2", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "Deprecated": "1", + "EventCode": "0xD2", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "Deprecated": "1", + "EventCode": "0xD2", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "Deprecated": "1", + "EventCode": "0xD2", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "Deprecated": "1", + "EventCode": "0xD2", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "Deprecated": "1", + "EventCode": "0xD2", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "Deprecated": "1", + "EventCode": "0xD4", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "Deprecated": "1", + "EventCode": "0xD4", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "Deprecated": "1", + "EventCode": "0xD4", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "Deprecated": "1", + "EventCode": "0xD4", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "Deprecated": "1", + "EventCode": "0xD4", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "Deprecated": "1", + "EventCode": "0xD4", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "Deprecated": "1", + "EventCode": "0xD6", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "Deprecated": "1", + "EventCode": "0xD6", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "Deprecated": "1", + "EventCode": "0xD6", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "Deprecated": "1", + "EventCode": "0xD6", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "Deprecated": "1", + "EventCode": "0xD6", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "Deprecated": "1", + "EventCode": "0xD6", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC", + "Deprecated": "1", + "EventCode": "0x9D", + "EventName": "UNC_H_TxR_HORZ_ADS_USED.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", + "Deprecated": "1", + "EventCode": "0x9D", + "EventName": "UNC_H_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC", + "Deprecated": "1", + "EventCode": "0x9D", + "EventName": "UNC_H_TxR_HORZ_ADS_USED.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC", + "Deprecated": "1", + "EventCode": "0x9D", + "EventName": "UNC_H_TxR_HORZ_ADS_USED.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", + "Deprecated": "1", + "EventCode": "0x9D", + "EventName": "UNC_H_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AD_BNC", + "Deprecated": "1", + "EventCode": "0x9F", + "EventName": "UNC_H_TxR_HORZ_BYPASS.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", + "Deprecated": "1", + "EventCode": "0x9F", + "EventName": "UNC_H_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AK_BNC", + "Deprecated": "1", + "EventCode": "0x9F", + "EventName": "UNC_H_TxR_HORZ_BYPASS.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.BL_BNC", + "Deprecated": "1", + "EventCode": "0x9F", + "EventName": "UNC_H_TxR_HORZ_BYPASS.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", + "Deprecated": "1", + "EventCode": "0x9F", + "EventName": "UNC_H_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.IV_BNC", + "Deprecated": "1", + "EventCode": "0x9F", + "EventName": "UNC_H_TxR_HORZ_BYPASS.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC", + "Deprecated": "1", + "EventCode": "0x96", + "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", + "Deprecated": "1", + "EventCode": "0x96", + "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC", + "Deprecated": "1", + "EventCode": "0x96", + "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC", + "Deprecated": "1", + "EventCode": "0x96", + "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", + "Deprecated": "1", + "EventCode": "0x96", + "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC", + "Deprecated": "1", + "EventCode": "0x96", + "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC", + "Deprecated": "1", + "EventCode": "0x97", + "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", + "Deprecated": "1", + "EventCode": "0x97", + "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC", + "Deprecated": "1", + "EventCode": "0x97", + "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC", + "Deprecated": "1", + "EventCode": "0x97", + "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", + "Deprecated": "1", + "EventCode": "0x97", + "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC", + "Deprecated": "1", + "EventCode": "0x97", + "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AD_BNC", + "Deprecated": "1", + "EventCode": "0x95", + "EventName": "UNC_H_TxR_HORZ_INSERTS.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", + "Deprecated": "1", + "EventCode": "0x95", + "EventName": "UNC_H_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AK_BNC", + "Deprecated": "1", + "EventCode": "0x95", + "EventName": "UNC_H_TxR_HORZ_INSERTS.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.BL_BNC", + "Deprecated": "1", + "EventCode": "0x95", + "EventName": "UNC_H_TxR_HORZ_INSERTS.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", + "Deprecated": "1", + "EventCode": "0x95", + "EventName": "UNC_H_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.IV_BNC", + "Deprecated": "1", + "EventCode": "0x95", + "EventName": "UNC_H_TxR_HORZ_INSERTS.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AD_BNC", + "Deprecated": "1", + "EventCode": "0x99", + "EventName": "UNC_H_TxR_HORZ_NACK.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AD_CRD", + "Deprecated": "1", + "EventCode": "0x99", + "EventName": "UNC_H_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AK_BNC", + "Deprecated": "1", + "EventCode": "0x99", + "EventName": "UNC_H_TxR_HORZ_NACK.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.BL_BNC", + "Deprecated": "1", + "EventCode": "0x99", + "EventName": "UNC_H_TxR_HORZ_NACK.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.BL_CRD", + "Deprecated": "1", + "EventCode": "0x99", + "EventName": "UNC_H_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.IV_BNC", + "Deprecated": "1", + "EventCode": "0x99", + "EventName": "UNC_H_TxR_HORZ_NACK.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC", + "Deprecated": "1", + "EventCode": "0x94", + "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", + "Deprecated": "1", + "EventCode": "0x94", + "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC", + "Deprecated": "1", + "EventCode": "0x94", + "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC", + "Deprecated": "1", + "EventCode": "0x94", + "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", + "Deprecated": "1", + "EventCode": "0x94", + "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC", + "Deprecated": "1", + "EventCode": "0x94", + "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.AD_BNC", + "Deprecated": "1", + "EventCode": "0x9B", + "EventName": "UNC_H_TxR_HORZ_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.AK_BNC", + "Deprecated": "1", + "EventCode": "0x9B", + "EventName": "UNC_H_TxR_HORZ_STARVED.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.BL_BNC", + "Deprecated": "1", + "EventCode": "0x9B", + "EventName": "UNC_H_TxR_HORZ_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.IV_BNC", + "Deprecated": "1", + "EventCode": "0x9B", + "EventName": "UNC_H_TxR_HORZ_STARVED.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", + "Deprecated": "1", + "EventCode": "0x9C", + "EventName": "UNC_H_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", + "Deprecated": "1", + "EventCode": "0x9C", + "EventName": "UNC_H_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AK_AG0", + "Deprecated": "1", + "EventCode": "0x9C", + "EventName": "UNC_H_TxR_VERT_ADS_USED.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AK_AG1", + "Deprecated": "1", + "EventCode": "0x9C", + "EventName": "UNC_H_TxR_VERT_ADS_USED.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", + "Deprecated": "1", + "EventCode": "0x9C", + "EventName": "UNC_H_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", + "Deprecated": "1", + "EventCode": "0x9C", + "EventName": "UNC_H_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AD_AG0", + "Deprecated": "1", + "EventCode": "0x9E", + "EventName": "UNC_H_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AD_AG1", + "Deprecated": "1", + "EventCode": "0x9E", + "EventName": "UNC_H_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AK_AG0", + "Deprecated": "1", + "EventCode": "0x9E", + "EventName": "UNC_H_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AK_AG1", + "Deprecated": "1", + "EventCode": "0x9E", + "EventName": "UNC_H_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.BL_AG0", + "Deprecated": "1", + "EventCode": "0x9E", + "EventName": "UNC_H_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.BL_AG1", + "Deprecated": "1", + "EventCode": "0x9E", + "EventName": "UNC_H_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.IV", + "Deprecated": "1", + "EventCode": "0x9E", + "EventName": "UNC_H_TxR_VERT_BYPASS.IV_AG1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0", + "Deprecated": "1", + "EventCode": "0x92", + "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1", + "Deprecated": "1", + "EventCode": "0x92", + "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0", + "Deprecated": "1", + "EventCode": "0x92", + "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1", + "Deprecated": "1", + "EventCode": "0x92", + "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0", + "Deprecated": "1", + "EventCode": "0x92", + "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1", + "Deprecated": "1", + "EventCode": "0x92", + "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.IV", + "Deprecated": "1", + "EventCode": "0x92", + "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0", + "Deprecated": "1", + "EventCode": "0x93", + "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1", + "Deprecated": "1", + "EventCode": "0x93", + "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0", + "Deprecated": "1", + "EventCode": "0x93", + "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1", + "Deprecated": "1", + "EventCode": "0x93", + "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0", + "Deprecated": "1", + "EventCode": "0x93", + "EventName": "UNC_H_TxR_VERT_CYCLES_NE.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1", + "Deprecated": "1", + "EventCode": "0x93", + "EventName": "UNC_H_TxR_VERT_CYCLES_NE.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.IV", + "Deprecated": "1", + "EventCode": "0x93", + "EventName": "UNC_H_TxR_VERT_CYCLES_NE.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AD_AG0", + "Deprecated": "1", + "EventCode": "0x91", + "EventName": "UNC_H_TxR_VERT_INSERTS.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AD_AG1", + "Deprecated": "1", + "EventCode": "0x91", + "EventName": "UNC_H_TxR_VERT_INSERTS.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AK_AG0", + "Deprecated": "1", + "EventCode": "0x91", + "EventName": "UNC_H_TxR_VERT_INSERTS.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AK_AG1", + "Deprecated": "1", + "EventCode": "0x91", + "EventName": "UNC_H_TxR_VERT_INSERTS.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.BL_AG0", + "Deprecated": "1", + "EventCode": "0x91", + "EventName": "UNC_H_TxR_VERT_INSERTS.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.BL_AG1", + "Deprecated": "1", + "EventCode": "0x91", + "EventName": "UNC_H_TxR_VERT_INSERTS.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.IV", + "Deprecated": "1", + "EventCode": "0x91", + "EventName": "UNC_H_TxR_VERT_INSERTS.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AD_AG0", + "Deprecated": "1", + "EventCode": "0x98", + "EventName": "UNC_H_TxR_VERT_NACK.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AD_AG1", + "Deprecated": "1", + "EventCode": "0x98", + "EventName": "UNC_H_TxR_VERT_NACK.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AK_AG0", + "Deprecated": "1", + "EventCode": "0x98", + "EventName": "UNC_H_TxR_VERT_NACK.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AK_AG1", + "Deprecated": "1", + "EventCode": "0x98", + "EventName": "UNC_H_TxR_VERT_NACK.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.BL_AG0", + "Deprecated": "1", + "EventCode": "0x98", + "EventName": "UNC_H_TxR_VERT_NACK.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.BL_AG1", + "Deprecated": "1", + "EventCode": "0x98", + "EventName": "UNC_H_TxR_VERT_NACK.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.IV", + "Deprecated": "1", + "EventCode": "0x98", + "EventName": "UNC_H_TxR_VERT_NACK.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0", + "Deprecated": "1", + "EventCode": "0x90", + "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1", + "Deprecated": "1", + "EventCode": "0x90", + "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0", + "Deprecated": "1", + "EventCode": "0x90", + "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1", + "Deprecated": "1", + "EventCode": "0x90", + "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0", + "Deprecated": "1", + "EventCode": "0x90", + "EventName": "UNC_H_TxR_VERT_OCCUPANCY.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1", + "Deprecated": "1", + "EventCode": "0x90", + "EventName": "UNC_H_TxR_VERT_OCCUPANCY.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.IV", + "Deprecated": "1", + "EventCode": "0x90", + "EventName": "UNC_H_TxR_VERT_OCCUPANCY.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AD_AG0", + "Deprecated": "1", + "EventCode": "0x9A", + "EventName": "UNC_H_TxR_VERT_STARVED.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AD_AG1", + "Deprecated": "1", + "EventCode": "0x9A", + "EventName": "UNC_H_TxR_VERT_STARVED.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AK_AG0", + "Deprecated": "1", + "EventCode": "0x9A", + "EventName": "UNC_H_TxR_VERT_STARVED.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AK_AG1", + "Deprecated": "1", + "EventCode": "0x9A", + "EventName": "UNC_H_TxR_VERT_STARVED.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.BL_AG0", + "Deprecated": "1", + "EventCode": "0x9A", + "EventName": "UNC_H_TxR_VERT_STARVED.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.BL_AG1", + "Deprecated": "1", + "EventCode": "0x9A", + "EventName": "UNC_H_TxR_VERT_STARVED.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.IV", + "Deprecated": "1", + "EventCode": "0x9A", + "EventName": "UNC_H_TxR_VERT_STARVED.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", + "Deprecated": "1", + "EventCode": "0xA6", + "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", + "Deprecated": "1", + "EventCode": "0xA6", + "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", + "Deprecated": "1", + "EventCode": "0xA6", + "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", + "Deprecated": "1", + "EventCode": "0xA6", + "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", + "Deprecated": "1", + "EventCode": "0xA8", + "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", + "Deprecated": "1", + "EventCode": "0xA8", + "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", + "Deprecated": "1", + "EventCode": "0xA8", + "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", + "Deprecated": "1", + "EventCode": "0xA8", + "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", + "Deprecated": "1", + "EventCode": "0xAA", + "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", + "Deprecated": "1", + "EventCode": "0xAA", + "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", + "Deprecated": "1", + "EventCode": "0xAA", + "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", + "Deprecated": "1", + "EventCode": "0xAA", + "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_IV_IN_USE.DN", + "Deprecated": "1", + "EventCode": "0xAC", + "EventName": "UNC_H_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_IV_IN_USE.UP", + "Deprecated": "1", + "EventCode": "0xAC", + "EventName": "UNC_H_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WB_PUSH_MTOI.LLC", + "Deprecated": "1", + "EventCode": "0x56", + "EventName": "UNC_H_WB_PUSH_MTOI.LLC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WB_PUSH_MTOI.MEM", + "Deprecated": "1", + "EventCode": "0x56", + "EventName": "UNC_H_WB_PUSH_MTOI.MEM", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2", + "Deprecated": "1", + "EventCode": "0x5A", + "EventName": "UNC_H_WRITE_NO_CREDITS.EDC0_SMI2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3", + "Deprecated": "1", + "EventCode": "0x5A", + "EventName": "UNC_H_WRITE_NO_CREDITS.EDC1_SMI3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4", + "Deprecated": "1", + "EventCode": "0x5A", + "EventName": "UNC_H_WRITE_NO_CREDITS.EDC2_SMI4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5", + "Deprecated": "1", + "EventCode": "0x5A", + "EventName": "UNC_H_WRITE_NO_CREDITS.EDC3_SMI5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0", + "Deprecated": "1", + "EventCode": "0x5A", + "EventName": "UNC_H_WRITE_NO_CREDITS.MC0_SMI0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1", + "Deprecated": "1", + "EventCode": "0x5A", + "EventName": "UNC_H_WRITE_NO_CREDITS.MC1_SMI1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.ANY_RSPI_FWDFE", + "PerPkg": "1", + "UMask": "0xe4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.ANY_RSPI_FWDM", + "PerPkg": "1", + "UMask": "0xf0", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.ANY_RSPS_FWDFE", + "PerPkg": "1", + "UMask": "0xe2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.ANY_RSPS_FWDM", + "PerPkg": "1", + "UMask": "0xe8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.ANY_RSP_HITFSE", + "PerPkg": "1", + "UMask": "0xe1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.CORE_RSPI_FWDFE", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.CORE_RSPI_FWDM", + "PerPkg": "1", + "UMask": "0x50", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.CORE_RSPS_FWDFE", + "PerPkg": "1", + "UMask": "0x42", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.CORE_RSPS_FWDM", + "PerPkg": "1", + "UMask": "0x48", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.CORE_RSP_HITFSE", + "PerPkg": "1", + "UMask": "0x41", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EVICT_RSPI_FWDFE", + "PerPkg": "1", + "UMask": "0x84", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EVICT_RSPI_FWDM", + "PerPkg": "1", + "UMask": "0x90", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EVICT_RSPS_FWDFE", + "PerPkg": "1", + "UMask": "0x82", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EVICT_RSPS_FWDM", + "PerPkg": "1", + "UMask": "0x88", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EVICT_RSP_HITFSE", + "PerPkg": "1", + "UMask": "0x81", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EXT_RSPI_FWDFE", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EXT_RSPI_FWDM", + "PerPkg": "1", + "UMask": "0x30", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EXT_RSPS_FWDFE", + "PerPkg": "1", + "UMask": "0x22", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EXT_RSPS_FWDM", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EXT_RSP_HITFSE", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + } +] diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-interconnect.json new file mode 100644 index 000000000000..725780fb3990 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-interconnect.json @@ -0,0 +1,11334 @@ +[ + { + "BriefDescription": "Total Write Cache Occupancy; Any Source", + "EventCode": "0xF", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Total Write Cache Occupancy; Snoops", + "EventCode": "0xF", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Total IRP occupancy of inbound read and write requests.", + "EventCode": "0xF", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", + "PerPkg": "1", + "PublicDescription": "Total IRP occupancy of inbound read and write requests. This is effectively the sum of read occupancy and write occupancy.", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "IRP Clocks", + "EventCode": "0x1", + "EventName": "UNC_I_CLOCKTICKS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; CLFlush", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; CRd", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.CRD", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; DRd", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.DRD", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; PCIDCAHin5t", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; PCIRdCur", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.PCITOM", + "PerPkg": "1", + "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.RFO", + "PerPkg": "1", + "PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; WbMtoI", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.WBMTOI", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "FAF RF full", + "EventCode": "0x17", + "EventName": "UNC_I_FAF_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.", + "EventCode": "0x18", + "EventName": "UNC_I_FAF_INSERTS", + "PerPkg": "1", + "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.", + "Unit": "IRP" + }, + { + "BriefDescription": "Occupancy of the IRP FAF queue.", + "EventCode": "0x19", + "EventName": "UNC_I_FAF_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.", + "Unit": "IRP" + }, + { + "BriefDescription": "FAF allocation -- sent to ADQ", + "EventCode": "0x16", + "EventName": "UNC_I_FAF_TRANSACTIONS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "All Inserts Inbound (p2p + faf + cset)", + "EventCode": "0x1E", + "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "All Inserts Outbound (BL, AK, Snoops)", + "EventCode": "0x1E", + "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.2ND_RD_INSERT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.2ND_WR_INSERT", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Fastpath Rejects", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.FAST_REJ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Fastpath Requests", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.FAST_REQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.FAST_XFER", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.PF_ACK_HINT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.UNKNOWN", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Lost Forward", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.LOST_FWD", + "PerPkg": "1", + "PublicDescription": "Snoop pulled away ownership before a write was committed", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Received Invalid", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", + "PerPkg": "1", + "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Received Valid", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", + "PerPkg": "1", + "PublicDescription": "Secondary received a transfer that did have sufficient MESI state", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SLOW_E", + "PerPkg": "1", + "PublicDescription": "Secondary received a transfer that did have sufficient MESI state", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SLOW_I", + "PerPkg": "1", + "PublicDescription": "Snoop took cacheline ownership before write from data was committed.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SLOW_M", + "PerPkg": "1", + "PublicDescription": "Snoop took cacheline ownership before write from data was committed.", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SLOW_S", + "PerPkg": "1", + "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Requests", + "EventCode": "0x14", + "EventName": "UNC_I_P2P_INSERTS", + "PerPkg": "1", + "PublicDescription": "P2P requests from the ITC", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Occupancy", + "EventCode": "0x15", + "EventName": "UNC_I_P2P_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "P2P B & S Queue Occupancy", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; P2P completions", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; match if local only", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.LOC", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; match if local and target matches", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; P2P Message", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.MSG", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; P2P reads", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.RD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; Match if remote only", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.REM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; match if remote and target matches", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; P2P Writes", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.WR", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO", + "UMask": "0x7e", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache", + "UMask": "0x74", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache", + "UMask": "0x72", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache", + "UMask": "0x78", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that miss the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_MISS", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that miss the IIO cache", + "UMask": "0x71", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Hit E or S", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_ES", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Hit I", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_I", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Hit M", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_M", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Miss", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.MISS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; SnpCode", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPCODE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; SnpData", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPDATA", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; SnpInv", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPINV", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Atomic", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.ATOMIC", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Other", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.OTHER", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions.", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Read Prefetches", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.RD_PREF", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Reads", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.READS", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Writes", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.WRITES", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound write (fast path) requests received by the IRP.", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "PerPkg": "1", + "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "AK Egress Allocations", + "EventCode": "0xB", + "EventName": "UNC_I_TxC_AK_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL DRS Egress Cycles Full", + "EventCode": "0x5", + "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL DRS Egress Inserts", + "EventCode": "0x2", + "EventName": "UNC_I_TxC_BL_DRS_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL DRS Egress Occupancy", + "EventCode": "0x8", + "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCB Egress Cycles Full", + "EventCode": "0x6", + "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCB Egress Inserts", + "EventCode": "0x3", + "EventName": "UNC_I_TxC_BL_NCB_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCB Egress Occupancy", + "EventCode": "0x9", + "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCS Egress Cycles Full", + "EventCode": "0x7", + "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCS Egress Inserts", + "EventCode": "0x4", + "EventName": "UNC_I_TxC_BL_NCS_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCS Egress Occupancy", + "EventCode": "0xA", + "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "No AD Egress Credit Stalls", + "EventCode": "0x1A", + "EventName": "UNC_I_TxR2_AD_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.", + "Unit": "IRP" + }, + { + "BriefDescription": "No BL Egress Credit Stalls", + "EventCode": "0x1B", + "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "EventCode": "0xD", + "EventName": "UNC_I_TxS_DATA_INSERTS_NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "EventCode": "0xE", + "EventName": "UNC_I_TxS_DATA_INSERTS_NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Request Queue Occupancy", + "EventCode": "0xC", + "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.", + "Unit": "IRP" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Traffic in which the M2M to iMC Bypass was not taken", + "EventCode": "0x22", + "EventName": "UNC_M2M_BYPASS_M2M_Egress.NOT_TAKEN", + "PerPkg": "1", + "PublicDescription": "Counts traffic in which the M2M (Mesh to Memory) to iMC (Memory Controller) bypass was not taken", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC Bypass; Taken", + "EventCode": "0x22", + "EventName": "UNC_M2M_BYPASS_M2M_Egress.TAKEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC Bypass; Not Taken", + "EventCode": "0x21", + "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC Bypass; Taken", + "EventCode": "0x21", + "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles - at UCLK", + "EventName": "UNC_M2M_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Clockticks", + "EventCode": "0xC0", + "EventName": "UNC_M2M_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled", + "EventCode": "0x24", + "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", + "PerPkg": "1", + "PublicDescription": "Counts cycles when direct to core mode (which bypasses the CHA) was disabled", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages sent direct to core (bypassing the CHA)", + "EventCode": "0x23", + "EventName": "UNC_M2M_DIRECT2CORE_TAKEN", + "PerPkg": "1", + "PublicDescription": "Counts when messages were sent direct to core (bypassing the CHA)", + "Unit": "M2M" + }, + { + "BriefDescription": "Number of reads in which direct to core transaction were overridden", + "EventCode": "0x25", + "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", + "PerPkg": "1", + "PublicDescription": "Counts reads in which direct to core transactions (which would have bypassed the CHA) were overridden", + "Unit": "M2M" + }, + { + "BriefDescription": "Number of reads in which direct to Intel(R) UPI transactions were overridden", + "EventCode": "0x28", + "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS", + "PerPkg": "1", + "PublicDescription": "Counts reads in which direct to Intel(R) Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overridden", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles when direct to Intel(R) UPI was disabled", + "EventCode": "0x27", + "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE", + "PerPkg": "1", + "PublicDescription": "Counts cycles when the ability to send messages direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA) was disabled", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages sent direct to the Intel(R) UPI", + "EventCode": "0x26", + "EventName": "UNC_M2M_DIRECT2UPI_TAKEN", + "PerPkg": "1", + "PublicDescription": "Counts when messages were sent direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA)", + "Unit": "M2M" + }, + { + "BriefDescription": "Number of reads that a message sent direct2 Intel(R) UPI was overridden", + "EventCode": "0x29", + "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE", + "PerPkg": "1", + "PublicDescription": "Counts when a read message that was sent direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA) was overridden", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On NonDirty Line in A State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On NonDirty Line in I State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On NonDirty Line in L State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On NonDirty Line in S State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On Dirty Line in A State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On Dirty Line in I State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On Dirty Line in L State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On Dirty Line in S State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in Any State (A, I, S or unused)", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in the A (SnoopAll) state, indicating the cacheline is stored in another socket in any state, and we must snoop the other sockets to make sure we get the latest data. The data may be stored in any state in the local socket.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the I (Invalid) state indicating the cacheline is not stored in another socket, and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the S (Shared) state indicating the cacheline is either stored in another socket in the S(hared) state , and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On NonDirty Line in A State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On NonDirty Line in I State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On NonDirty Line in L State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On NonDirty Line in S State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On Dirty Line in A State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On Dirty Line in I State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On Dirty Line in L State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On Dirty Line in S State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from A to I", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from A (SnoopAll) to I (Invalid)", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from A to S", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from A (SnoopAll) to S (Shared)", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from/to Any state", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory to a new state", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from I to A", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from I (Invalid) to A (SnoopAll)", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from I to S", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from I (Invalid) to S (Shared)", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from S to A", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from S (Shared) to A (SnoopAll)", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from S to I", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from S (Shared) to I (Invalid)", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements; Down", + "EventCode": "0xAE", + "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements; Up", + "EventCode": "0xAE", + "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "FaST wire asserted; Horizontal", + "EventCode": "0xA5", + "EventName": "UNC_M2M_FAST_ASSERTED.HORZ", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "FaST wire asserted; Vertical", + "EventCode": "0xA5", + "EventName": "UNC_M2M_FAST_ASSERTED.VERT", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Left and Even", + "EventCode": "0xA7", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", + "EventCode": "0xA7", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Right and Even", + "EventCode": "0xA7", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", + "EventCode": "0xA7", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Even", + "EventCode": "0xA9", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", + "EventCode": "0xA9", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Right and Even", + "EventCode": "0xA9", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", + "EventCode": "0xA9", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Left and Even", + "EventCode": "0xAB", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", + "EventCode": "0xAB", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Right and Even", + "EventCode": "0xAB", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", + "EventCode": "0xAB", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal IV Ring in Use; Left", + "EventCode": "0xAD", + "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal IV Ring in Use; Right", + "EventCode": "0xAD", + "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Reads to iMC issued", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.ALL", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller).", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC; All, regardless of priority.", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.FROM_TRANSGRESS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC; Critical Priority", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.ISOCH", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Reads to iMC issued at Normal Priority (Non-Isochronous)", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.NORMAL", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller). It only counts normal priority non-isochronous reads.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Read requests to Intel(R) Optane(TM) DC persistent memory issued to the iMC from M2M", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.TO_PMM", + "PerPkg": "1", + "PublicDescription": "M2M Reads Issued to iMC; All, regardless of priority.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Writes to iMC issued", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.ALL", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) issues writes to the iMC (Memory Controller).", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority.", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FROM_TRANSGRESS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC; Full Line Non-ISOCH", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FULL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC; ISOCH Full Line", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority.", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.NI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Partial Non-Isochronous writes to the iMC", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) issues partial writes to the iMC (Memory Controller). It only counts normal priority non-isochronous writes.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC; ISOCH Partial", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Write requests to Intel(R) Optane(TM) DC persistent memory issued to the iMC from M2M", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.TO_PMM", + "PerPkg": "1", + "PublicDescription": "M2M Writes Issued to iMC; All, regardless of priority.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Number Packet Header Matches; MC Match", + "EventCode": "0x4C", + "EventName": "UNC_M2M_PKT_MATCH.MC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Number Packet Header Matches; Mesh Match", + "EventCode": "0x4C", + "EventName": "UNC_M2M_PKT_MATCH.MESH", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - Regular; Channel 0", + "EventCode": "0x4F", + "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - Regular; Channel 1", + "EventCode": "0x4F", + "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - Regular; Channel 2", + "EventCode": "0x4F", + "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0", + "EventCode": "0x51", + "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1", + "EventCode": "0x51", + "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2", + "EventCode": "0x51", + "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Full", + "EventCode": "0x53", + "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Not Empty", + "EventCode": "0x54", + "EventName": "UNC_M2M_PREFCAM_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch requests that got turn into a demand request", + "EventCode": "0x56", + "EventName": "UNC_M2M_PREFCAM_DEMAND_PROMOTIONS", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) promotes a outstanding request in the prefetch queue due to a subsequent demand read request that entered the M2M with the same address. Explanatory Side Note: The Prefetch queue is made of CAM (Content Addressable Memory)", + "Unit": "M2M" + }, + { + "BriefDescription": "Inserts into the Memory Controller Prefetch Queue", + "EventCode": "0x57", + "EventName": "UNC_M2M_PREFCAM_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) receives a prefetch request and inserts it into its outstanding prefetch queue. Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Occupancy", + "EventCode": "0x55", + "EventName": "UNC_M2M_PREFCAM_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD", + "EventCode": "0xA1", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK", + "EventCode": "0xA1", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL", + "EventCode": "0xA1", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV", + "EventCode": "0xA1", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; AD", + "EventCode": "0xA0", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core", + "EventCode": "0xA0", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core", + "EventCode": "0xA0", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.", + "EventCode": "0xA0", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; AD", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; AK", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; BL", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; IV", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; AD", + "EventCode": "0xA2", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core", + "EventCode": "0xA2", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core", + "EventCode": "0xA2", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.", + "EventCode": "0xA2", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Source Throttle", + "EventCode": "0xA4", + "EventName": "UNC_M2M_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0", + "Deprecated": "1", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1", + "Deprecated": "1", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2", + "Deprecated": "1", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 0", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 1", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 2", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 0", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 1", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 2", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Full", + "EventCode": "0x4", + "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Not Empty", + "EventCode": "0x3", + "EventName": "UNC_M2M_RxC_AD_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Queue Inserts", + "EventCode": "0x1", + "EventName": "UNC_M2M_RxC_AD_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts when the a new entry is Received(RxC) and then added to the AD (Address Ring) Ingress Queue from the CMS (Common Mesh Stop). This is generally used for reads, and", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Occupancy", + "EventCode": "0x2", + "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Full", + "EventCode": "0x8", + "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Not Empty", + "EventCode": "0x7", + "EventName": "UNC_M2M_RxC_BL_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Allocations", + "EventCode": "0x5", + "EventName": "UNC_M2M_RxC_BL_INSERTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Occupancy", + "EventCode": "0x6", + "EventName": "UNC_M2M_RxC_BL_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "EventCode": "0xB4", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "EventCode": "0xB4", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "EventCode": "0xB4", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "EventCode": "0xB4", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AD - Credit", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass; BL - Credit", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; AK - Bounce", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; IFV - Credit", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; IV - Bounce", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AD - Credit", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; BL - Credit", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Clean line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode and regular reads to DRAM in 1LM", + "EventCode": "0x2C", + "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN", + "PerPkg": "1", + "PublicDescription": "Tag Hit; Read Hit from NearMem, Clean Line", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Dirty line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode", + "EventCode": "0x2C", + "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY", + "PerPkg": "1", + "PublicDescription": "Tag Hit; Read Hit from NearMem, Dirty Line", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Clean line underfill read hits to Near Memory(DRAM cache) in Memory Mode", + "EventCode": "0x2C", + "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN", + "PerPkg": "1", + "PublicDescription": "Tag Hit; Underfill Rd Hit from NearMem, Clean Line", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Dirty line underfill read hits to Near Memory(DRAM cache) in Memory Mode", + "EventCode": "0x2C", + "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY", + "PerPkg": "1", + "PublicDescription": "Tag Hit; Underfill Rd Hit from NearMem, Dirty Line", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Number AD Ingress Credits", + "EventCode": "0x41", + "EventName": "UNC_M2M_TGR_AD_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number BL Ingress Credits", + "EventCode": "0x42", + "EventName": "UNC_M2M_TGR_BL_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Full; Channel 0", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Full; Channel 1", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Full; Channel 2", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Not Empty; Channel 0", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Not Empty; Channel 1", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Not Empty; Channel 2", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Inserts; Channel 0", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Inserts; Channel 1", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Inserts; Channel 2", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Occupancy; Channel 0", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Occupancy; Channel 1", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Occupancy; Channel 2", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Pending Occupancy", + "EventCode": "0x48", + "EventName": "UNC_M2M_TRACKER_PENDING_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Credit Acquired", + "EventCode": "0xD", + "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Credits Occupancy", + "EventCode": "0xE", + "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Full", + "EventCode": "0xC", + "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Not Empty", + "EventCode": "0xB", + "EventName": "UNC_M2M_TxC_AD_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Allocations", + "EventCode": "0x9", + "EventName": "UNC_M2M_TxC_AD_INSERTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No AD Egress (to CMS) Credits", + "EventCode": "0xF", + "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits", + "EventCode": "0x10", + "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Occupancy", + "EventCode": "0xA", + "EventName": "UNC_M2M_TxC_AD_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound Ring Transactions on AK; CRD Transactions to Cbo", + "EventCode": "0x39", + "EventName": "UNC_M2M_TxC_AK.CRD_CBO", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound Ring Transactions on AK; NDR Transactions", + "EventCode": "0x39", + "EventName": "UNC_M2M_TxC_AK.NDR", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side", + "EventCode": "0x1D", + "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side", + "EventCode": "0x1D", + "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side", + "EventCode": "0x1E", + "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side", + "EventCode": "0x1E", + "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; All", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Near Side", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Far Side", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1", + "PerPkg": "1", + "UMask": "0x88", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1", + "PerPkg": "1", + "UMask": "0xa0", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1", + "PerPkg": "1", + "UMask": "0x90", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty; All", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Near Side", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Far Side", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty; Read Credit Request", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty; Write Compare Request", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty; Write Credit Request", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; All", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Near Side", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Far Side", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; Prefetch Read Cam Hit", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; Read Credit Request", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; Write Compare Request", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; Write Credit Request", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side", + "EventCode": "0x1F", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side", + "EventCode": "0x1F", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side", + "EventCode": "0x20", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side", + "EventCode": "0x20", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy; All", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Near Side", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Far Side", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy; Read Credit Request", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy; Write Compare Request", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy; Write Credit Request", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Sideband", + "EventCode": "0x6B", + "EventName": "UNC_M2M_TxC_AK_SIDEBAND.RD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Sideband", + "EventCode": "0x6B", + "EventName": "UNC_M2M_TxC_AK_SIDEBAND.WR", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_CACHE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_CORE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_UPI", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side", + "EventCode": "0x19", + "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side", + "EventCode": "0x19", + "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side", + "EventCode": "0x1A", + "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side", + "EventCode": "0x1A", + "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Full; All", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Near Side", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Far Side", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Not Empty; All", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Near Side", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Far Side", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Allocations; All", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Near Side", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Far Side", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side", + "EventCode": "0x1B", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side", + "EventCode": "0x1B", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side", + "EventCode": "0x1C", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side", + "EventCode": "0x1C", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Occupancy; All", + "EventCode": "0x16", + "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Near Side", + "EventCode": "0x16", + "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Far Side", + "EventCode": "0x16", + "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; IV", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.IV", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.IV", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; IV", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.IV", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; IV", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.IV", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; IV", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.IV", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Down and Even", + "EventCode": "0xA6", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Down and Odd", + "EventCode": "0xA6", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Up and Even", + "EventCode": "0xA6", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Up and Odd", + "EventCode": "0xA6", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Down and Even", + "EventCode": "0xA8", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Down and Odd", + "EventCode": "0xA8", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Up and Even", + "EventCode": "0xA8", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Up and Odd", + "EventCode": "0xA8", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Down and Even", + "EventCode": "0xAA", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Down and Odd", + "EventCode": "0xAA", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Up and Even", + "EventCode": "0xAA", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Up and Odd", + "EventCode": "0xAA", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical IV Ring in Use; Down", + "EventCode": "0xAC", + "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical IV Ring in Use; Up", + "EventCode": "0xAC", + "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0", + "Deprecated": "1", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1", + "Deprecated": "1", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2", + "Deprecated": "1", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 0", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 1", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 2", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Full; Channel 0", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Full; Channel 1", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Full; Channel 2", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty; Channel 0", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty; Channel 1", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty; Channel 2", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts; Channel 0", + "EventCode": "0x61", + "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts; Channel 1", + "EventCode": "0x61", + "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts; Channel 2", + "EventCode": "0x61", + "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy; Channel 0", + "EventCode": "0x60", + "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy; Channel 1", + "EventCode": "0x60", + "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy; Channel 2", + "EventCode": "0x60", + "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty; Requests", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty; Snoops", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty; VNA Messages", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty; Writebacks", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of uclks in domain", + "EventCode": "0x1", + "EventName": "UNC_M3UPI_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Clockticks", + "EventCode": "0xC0", + "EventName": "UNC_M3UPI_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "D2C Sent", + "EventCode": "0x2B", + "EventName": "UNC_M3UPI_D2C_SENT", + "PerPkg": "1", + "PublicDescription": "Count cases BL sends direct to core", + "Unit": "M3UPI" + }, + { + "BriefDescription": "D2U Sent", + "EventCode": "0x2A", + "EventName": "UNC_M3UPI_D2U_SENT", + "PerPkg": "1", + "PublicDescription": "Cases where SMI3 sends D2U command", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements; Down", + "EventCode": "0xAE", + "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements; Up", + "EventCode": "0xAE", + "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "FaST wire asserted; Horizontal", + "EventCode": "0xA5", + "EventName": "UNC_M3UPI_FAST_ASSERTED.HORZ", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "FaST wire asserted; Vertical", + "EventCode": "0xA5", + "EventName": "UNC_M3UPI_FAST_ASSERTED.VERT", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Left and Even", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Right and Even", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Even", + "EventCode": "0xA9", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", + "EventCode": "0xA9", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Right and Even", + "EventCode": "0xA9", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", + "EventCode": "0xA9", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Left and Even", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Right and Even", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal IV Ring in Use; Left", + "EventCode": "0xAD", + "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal IV Ring in Use; Right", + "EventCode": "0xAD", + "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO0_IIO1_NCB", + "PerPkg": "1", + "PublicDescription": "No vn0 and vna credits available to send to M2", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; IIO2", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB", + "PerPkg": "1", + "PublicDescription": "No vn0 and vna credits available to send to M2", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; IIO3", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB", + "PerPkg": "1", + "PublicDescription": "No vn0 and vna credits available to send to M2", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; IIO4", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB", + "PerPkg": "1", + "PublicDescription": "No vn0 and vna credits available to send to M2", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; IIO5", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB", + "PerPkg": "1", + "PublicDescription": "No vn0 and vna credits available to send to M2", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; All IIO targets for NCS are in single mask. ORs them together", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS", + "PerPkg": "1", + "PublicDescription": "No vn0 and vna credits available to send to M2", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; Selected M2p BL NCS credits", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL", + "PerPkg": "1", + "PublicDescription": "No vn0 and vna credits available to send to M2", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received; AD - Slot 0", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0", + "PerPkg": "1", + "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received; AD - Slot 1", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1", + "PerPkg": "1", + "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received; AD - Slot 2", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2", + "PerPkg": "1", + "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received; AK - Slot 0", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0", + "PerPkg": "1", + "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received; AK - Slot 2", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2", + "PerPkg": "1", + "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received; BL - Slot 0", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0", + "PerPkg": "1", + "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; AD", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; AD", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; AK", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; BL", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; IV", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; AD", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Source Throttle", + "EventCode": "0xA4", + "EventName": "UNC_M3UPI_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; REQ on AD", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "VN0 message requested but lost arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; RSP on AD", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "VN0 message requested but lost arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; SNP on AD", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "VN0 message requested but lost arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; NCB on BL", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "VN0 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; NCS on BL", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "VN0 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; RSP on BL", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "VN0 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; WB on BL", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "VN0 message requested but lost arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; REQ on AD", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "VN1 message requested but lost arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; RSP on AD", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "VN1 message requested but lost arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; SNP on AD", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "VN1 message requested but lost arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; NCB on BL", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "VN1 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; NCS on BL", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "VN1 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; RSP on BL", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "VN1 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; WB on BL", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "VN1 message requested but lost arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; AD, BL Parallel Win", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN", + "PerPkg": "1", + "PublicDescription": "AD and BL messages won arbitration concurrently / in parallel", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN0", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0", + "PerPkg": "1", + "PublicDescription": "Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN1", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1", + "PerPkg": "1", + "PublicDescription": "Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN0", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0", + "PerPkg": "1", + "PublicDescription": "Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN1", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1", + "PerPkg": "1", + "PublicDescription": "Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN0", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN0", + "PerPkg": "1", + "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win to vn0, delaying vn1 win, because vn0 offered parallel ad/bl", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN1", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN1", + "PerPkg": "1", + "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win to vn1, delaying vn0 win, because vn1 offered parallel ad/bl", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; REQ on AD", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; RSP on AD", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; SNP on AD", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; NCB on BL", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; NCS on BL", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; RSP on BL", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; WB on BL", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; REQ on AD", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; RSP on AD", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; SNP on AD", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; NCB on BL", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; NCS on BL", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; RSP on BL", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; WB on BL", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; REQ on AD", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; RSP on AD", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; SNP on AD", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; NCB on BL", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; NCS on BL", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; RSP on BL", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; WB on BL", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; REQ on AD", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; RSP on AD", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; SNP on AD", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; NCB on BL", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; NCS on BL", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; RSP on BL", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; WB on BL", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on BL Arb", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB", + "PerPkg": "1", + "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while bl message is in arbitration", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on Idle", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE", + "PerPkg": "1", + "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while pipeline is idle", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 1", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT", + "PerPkg": "1", + "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 1 while merging with bl message in same flit", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 2", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT", + "PerPkg": "1", + "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 2 while merging with bl message in same flit", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; REQ on AD", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; RSP on AD", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; SNP on AD", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; NCB on BL", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; NCS on BL", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; RSP on BL", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; WB on BL", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; REQ on AD", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; RSP on AD", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; SNP on AD", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; NCB on BL", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; NCS on BL", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; RSP on BL", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; WB on BL", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events; Any In BGF FIFO", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO", + "PerPkg": "1", + "PublicDescription": "Indication that at least one packet (flit) is in the bgf (fifo only)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events; Any in BGF Path", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH", + "PerPkg": "1", + "PublicDescription": "Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events; No D2K For Arb", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.NO_D2K_FOR_ARB", + "PerPkg": "1", + "PublicDescription": "VN0 or VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy; D2K Credits", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD", + "PerPkg": "1", + "PublicDescription": "D2K completion fifo credit occupancy (credits in use), accumulated across all cycles", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy; Packets in BGF FIFO", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO", + "PerPkg": "1", + "PublicDescription": "Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy; Packets in BGF Path", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH", + "PerPkg": "1", + "PublicDescription": "Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO", + "PerPkg": "1", + "PublicDescription": "count of bl messages in pump-1-pending state, in completion fifo only", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL", + "PerPkg": "1", + "PublicDescription": "count of bl messages in pump-1-pending state, in marker table and in fifo", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy; Transmit Credits", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD", + "PerPkg": "1", + "PublicDescription": "Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy; VNA In Use", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE", + "PerPkg": "1", + "PublicDescription": "Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent; All", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.ALL", + "PerPkg": "1", + "PublicDescription": "Data flit is ready for transmission but could not be sent", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent; No BGF Credits", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_BGF", + "PerPkg": "1", + "PublicDescription": "Data flit is ready for transmission but could not be sent", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent; No TxQ Credits", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_TXQ", + "PerPkg": "1", + "PublicDescription": "Data flit is ready for transmission but could not be sent", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 0", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT", + "PerPkg": "1", + "PublicDescription": "generating bl data flit sequence; waiting for data pump 0", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT", + "PerPkg": "1", + "PublicDescription": "pump-1-pending logic is at capacity (pending table plus completion fifo at limit)", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY", + "PerPkg": "1", + "PublicDescription": "pump-1-pending logic is tracking at least one message", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL", + "PerPkg": "1", + "PublicDescription": "pump-1-pending completion fifo is full", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0", + "PerPkg": "1", + "PublicDescription": "pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO", + "PerPkg": "1", + "PublicDescription": "a bl message finished but is in limbo and moved to pump-1-pending logic", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 1", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT", + "PerPkg": "1", + "PublicDescription": "generating bl data flit sequence; waiting for data pump 1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC", + "EventCode": "0x5A", + "EventName": "UNC_M3UPI_RxC_FLITS_MISC", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit; One Message", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG", + "PerPkg": "1", + "PublicDescription": "One message in flit; VNA or non-VNA flit", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit; One Message in non-VNA", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG_VNX", + "PerPkg": "1", + "PublicDescription": "One message in flit; non-VNA flit", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit; Two Messages", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.2_MSGS", + "PerPkg": "1", + "PublicDescription": "Two messages in flit; VNA flit", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit; Three Messages", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.3_MSGS", + "PerPkg": "1", + "PublicDescription": "Three messages in flit; VNA flit", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_2", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_3", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; All", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Needs Data Flit", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA", + "PerPkg": "1", + "PublicDescription": "BL message requires data flit sequence", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 0", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT", + "PerPkg": "1", + "PublicDescription": "Waiting for header pump 0", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ", + "PerPkg": "1", + "PublicDescription": "Header pump 1 is not required for flit", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Bubble", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE", + "PerPkg": "1", + "PublicDescription": "Header pump 1 is not required for flit but flit transmission delayed", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Not Avail", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL", + "PerPkg": "1", + "PublicDescription": "Header pump 1 is not required for flit and not available", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 1", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT", + "PerPkg": "1", + "PublicDescription": "Waiting for header pump 1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Accumulate", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM", + "PerPkg": "1", + "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Accumulate Ready", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ", + "PerPkg": "1", + "PublicDescription": "Events related to Header Flit Generation - Set 1; header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Accumulate Wasted", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED", + "PerPkg": "1", + "PublicDescription": "Events related to Header Flit Generation - Set 1; Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Blocked", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED", + "PerPkg": "1", + "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Message", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG", + "PerPkg": "1", + "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting is in run-ahead to start new flit, and message is actually slotted into new flit", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Parallel Ok", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR", + "PerPkg": "1", + "PublicDescription": "Events related to Header Flit Generation - Set 1; New header flit construction may proceed in parallel with data flit sequence", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Parallel Flit Finished", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_FLIT", + "PerPkg": "1", + "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit finished assembly in parallel with data flit sequence", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Parallel Message", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_MSG", + "PerPkg": "1", + "PublicDescription": "Events related to Header Flit Generation - Set 1; Message is slotted into header flit in parallel with data flit sequence", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL", + "PerPkg": "1", + "PublicDescription": "Events related to Header Flit Generation - Set 2; Rate-matching stall injected", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall - No Message", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG", + "PerPkg": "1", + "PublicDescription": "Events related to Header Flit Generation - Set 2; Rate matching stall injected, but no additional message slotted during stall cycle", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; All", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ALL", + "PerPkg": "1", + "PublicDescription": "header flit is ready for transmission but could not be sent", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; No BGF Credits", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_CRD", + "PerPkg": "1", + "PublicDescription": "header flit is ready for transmission but could not be sent; No BGF credits available", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; No BGF Credits + No Extra Message Slotted", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_NO_MSG", + "PerPkg": "1", + "PublicDescription": "header flit is ready for transmission but could not be sent; No BGF credits available; no additional message slotted into flit", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; No TxQ Credits", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_CRD", + "PerPkg": "1", + "PublicDescription": "header flit is ready for transmission but could not be sent; No TxQ credits available", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; No TxQ Credits + No Extra Message Slotted", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_NO_MSG", + "PerPkg": "1", + "PublicDescription": "header flit is ready for transmission but could not be sent; No TxQ credits available; no additional message slotted into flit", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; Sent - One Slot Taken", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ONE_TAKEN", + "PerPkg": "1", + "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with only one slot taken (two slots free)", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; Sent - Three Slots Taken", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.THREE_TAKEN", + "PerPkg": "1", + "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with three slots taken (no slots free)", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; Sent - Two Slots Taken", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.TWO_TAKEN", + "PerPkg": "1", + "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with only two slots taken (one slots free)", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Can't Slot AD", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD", + "PerPkg": "1", + "PublicDescription": "some AD message could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1})", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Can't Slot BL", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL", + "PerPkg": "1", + "PublicDescription": "some BL message could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1})", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Parallel AD Lost", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_AD_LOST", + "PerPkg": "1", + "PublicDescription": "some AD message lost contest for slot 0 (logical OR of all AD events under INGR_SLOT_LOST_MC_VN{0,1})", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Parallel Attempt", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT", + "PerPkg": "1", + "PublicDescription": "ad and bl messages attempted to slot into the same flit in parallel", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Parallel BL Lost", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_BL_LOST", + "PerPkg": "1", + "PublicDescription": "some BL message lost contest for slot 0 (logical OR of all BL events under INGR_SLOT_LOST_MC_VN{0,1})", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Parallel Success", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS", + "PerPkg": "1", + "PublicDescription": "ad and bl messages were actually slotted into the same flit in paralle", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; VN0", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.VN0", + "PerPkg": "1", + "PublicDescription": "vn0 message(s) that couldn't be slotted into last vn0 flit are held in slotting stage while processing vn1 flit", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; VN1", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.VN1", + "PerPkg": "1", + "PublicDescription": "vn1 message(s) that couldn't be slotted into last vn1 flit are held in slotting stage while processing vn0 flit", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; REQ on AD", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on AD", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; SNP on AD", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCB on BL", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCS on BL", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on BL", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; WB on BL", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; REQ on AD", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on AD", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; SNP on AD", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCB on BL", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCS on BL", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on BL", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; WB on BL", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; REQ on AD", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on AD", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; SNP on AD", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCB on BL", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCS on BL", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on BL", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; WB on BL", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; REQ on AD", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on AD", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; SNP on AD", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCB on BL", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCS on BL", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on BL", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; WB on BL", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; REQ on AD", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; RSP on AD", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; SNP on AD", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; NCB on BL", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; NCS on BL", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; RSP on BL", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; WB on BL", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; REQ on AD", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; RSP on AD", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; SNP on AD", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; NCB on BL", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; NCS on BL", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; RSP on BL", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; WB on BL", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "SMI3 Prefetch Messages; Lost Arbitration", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARB_LOST", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "SMI3 Prefetch Messages; Arrived", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARRIVED", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "SMI3 Prefetch Messages; Dropped - Old", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_OLD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "SMI3 Prefetch Messages; Dropped - Wrap", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_WRAP", + "PerPkg": "1", + "PublicDescription": "Dropped because it was overwritten by new message while prefetch queue was full", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "SMI3 Prefetch Messages; Slotted", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.SLOTTED", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits; Any In Use", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE", + "PerPkg": "1", + "PublicDescription": "At least one remote vna credit is in use", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits; Corrected", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED", + "PerPkg": "1", + "PublicDescription": "Number of remote vna credits corrected (local return) per cycle", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits; Level < 1", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1", + "PerPkg": "1", + "PublicDescription": "Remote vna credit level is less than 1 (i.e. no vna credits available)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits; Level < 4", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4", + "PerPkg": "1", + "PublicDescription": "Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits; Level < 5", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5", + "PerPkg": "1", + "PublicDescription": "Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits; Used", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.USED", + "PerPkg": "1", + "PublicDescription": "Number of remote vna credits consumed per cycle", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AD - Credit", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass; BL - Credit", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; AK - Bounce", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; IFV - Credit", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; IV - Bounce", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AD - Credit", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations; BL - Credit", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN0 REQ Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "AD arb but no win; arb request asserted but not won", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN0 RSP Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "AD arb but no win; arb request asserted but not won", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN0 SNP Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "AD arb but no win; arb request asserted but not won", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN0 WB Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB", + "PerPkg": "1", + "PublicDescription": "AD arb but no win; arb request asserted but not won", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN1 REQ Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "AD arb but no win; arb request asserted but not won", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN1 RSP Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "AD arb but no win; arb request asserted but not won", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN1 SNP Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "AD arb but no win; arb request asserted but not won", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN1 WB Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB", + "PerPkg": "1", + "PublicDescription": "AD arb but no win; arb request asserted but not won", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0", + "PerPkg": "1", + "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1", + "PerPkg": "1", + "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2", + "PerPkg": "1", + "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP", + "PerPkg": "1", + "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN0 REQ Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN0 RSP Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN0 SNP Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN0 WB Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN1 REQ Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN1 RSP Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN1 SNP Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN1 WB Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN0 REQ Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN0 RSP Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN0 SNP Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN0 WB Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN1 REQ Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN1 RSP Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN1 SNP Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN0 REQ Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN0 RSP Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN0 SNP Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN0 WB Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN1 REQ Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN1 RSP Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN1 SNP Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; CHA on VN0", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_CHA", + "PerPkg": "1", + "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to CHA", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN0", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_NON_IDLE", + "PerPkg": "1", + "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of non-idle cycles in issuing Vn0 Snpf", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN0", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI0", + "PerPkg": "1", + "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to peer UPI0", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN0", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI1", + "PerPkg": "1", + "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to peer UPI1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; CHA on VN1", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_CHA", + "PerPkg": "1", + "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to CHA", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN1", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_NON_IDLE", + "PerPkg": "1", + "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of non-idle cycles in issuing Vn1 Snpf", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN1", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI0", + "PerPkg": "1", + "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to peer UPI0", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN1", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI1", + "PerPkg": "1", + "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to peer UPI1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Snoop Arbitration; FlowQ Won", + "EventCode": "0x3D", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_NONSNP", + "PerPkg": "1", + "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn0", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won", + "EventCode": "0x3D", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_VN2SNP", + "PerPkg": "1", + "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ Vn0 SnpF issued when SnpF pending on Vn1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Snoop Arbitration; FlowQ Won", + "EventCode": "0x3D", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_NONSNP", + "PerPkg": "1", + "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won", + "EventCode": "0x3D", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_VN0SNP", + "PerPkg": "1", + "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ Vn1 SnpF issued when SnpF pending on Vn0", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 REQ Messages", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 SNP Messages", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 WB Messages", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_WB", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 REQ Messages", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 SNP Messages", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 WB Messages", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_WB", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - New Message; VN0 REQ Messages", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - New Message; VN0 SNP Messages", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - New Message; VN0 WB Messages", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_WB", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - New Message; VN1 REQ Messages", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - New Message; VN1 SNP Messages", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - New Message; VN1 WB Messages", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_WB", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN0 REQ Messages", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN0 RSP Messages", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN0 SNP Messages", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN0 WB Messages", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_WB", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN1 REQ Messages", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN1 RSP Messages", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN1 SNP Messages", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN1 WB Messages", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_WB", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AK Flow Q Inserts", + "EventCode": "0x2F", + "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AK Flow Q Occupancy", + "EventCode": "0x1E", + "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN0 NCB Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB", + "PerPkg": "1", + "PublicDescription": "BL arb but no win; arb request asserted but not won", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN0 NCS Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS", + "PerPkg": "1", + "PublicDescription": "BL arb but no win; arb request asserted but not won", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN0 RSP Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "BL arb but no win; arb request asserted but not won", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN0 WB Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB", + "PerPkg": "1", + "PublicDescription": "BL arb but no win; arb request asserted but not won", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN1 NCS Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB", + "PerPkg": "1", + "PublicDescription": "BL arb but no win; arb request asserted but not won", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN1 NCB Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS", + "PerPkg": "1", + "PublicDescription": "BL arb but no win; arb request asserted but not won", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN1 RSP Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "BL arb but no win; arb request asserted but not won", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN1 WB Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB", + "PerPkg": "1", + "PublicDescription": "BL arb but no win; arb request asserted but not won", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN0 REQ Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN0 RSP Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN0 SNP Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN0 WB Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN1 REQ Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN1 RSP Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN1 SNP Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN1 WB Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN0 RSP Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN0 WB Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN0 NCS Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN0 NCB Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN1 RSP Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN1 WB Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN1_NCB Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN1_NCS Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN0 NCB Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN0 NCS Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN0 RSP Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN0 WB Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN1_NCS Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN1_NCB Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN1 RSP Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN1 WB Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB Messages", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCB", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for BL - New Message; VN0 NCS Messages", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCS", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB Messages", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_WB", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for BL - New Message; VN1 WB Messages", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCB", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for BL - New Message; VN1 NCB Messages", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCS", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for BL - New Message; VN1 RSP Messages", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_WB", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCB Messages", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCB", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCS Messages", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCS", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 RSP Messages", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 WB Messages", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_WB", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCS Messages", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCB", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCB Messages", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCS", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 RSP Messages", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 WB Messages", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_WB", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; IV", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.IV", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.IV", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; IV", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.IV", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; IV", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.IV", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; IV", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.IV", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VN0 REQ Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPIs on the AD Ring", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VN0 RSP Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPIs on the AD Ring", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VN0 SNP Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPIs on the AD Ring", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VN1 REQ Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPIs on the AD Ring", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VN1 RSP Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPIs on the AD Ring", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VN1 SNP Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPIs on the AD Ring", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VNA", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPIs on the AD Ring", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty; VN0 RSP Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty; VN0 REQ Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty; VN0 SNP Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty; VN1 RSP Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty; VN1 REQ Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty; VN1 SNP Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty; VNA", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Prefetches generated by the flow control queue of the M3UPI unit.", + "EventCode": "0x29", + "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN", + "PerPkg": "1", + "PublicDescription": "Count cases where flow control queue that sits between the Intel(R) Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller)", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Down and Even", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Down and Odd", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Up and Even", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Up and Odd", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Down and Even", + "EventCode": "0xA8", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Down and Odd", + "EventCode": "0xA8", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Up and Even", + "EventCode": "0xA8", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Up and Odd", + "EventCode": "0xA8", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Down and Even", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Down and Odd", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Up and Even", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Up and Odd", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical IV Ring in Use; Down", + "EventCode": "0xAC", + "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical IV Ring in Use; Up", + "EventCode": "0xAC", + "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used; WB on BL", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used; NCB on BL", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used; REQ on AD", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used; RSP on AD", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used; SNP on AD", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used; RSP on BL", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits; WB on BL", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB", + "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN0 Credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits; NCB on BL", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS", + "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN0 Credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits; REQ on AD", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ", + "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN0 Credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits; RSP on AD", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP", + "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN0 Credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits; SNP on AD", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP", + "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN0 Credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits; RSP on BL", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB", + "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN0 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used; WB on BL", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used; NCB on BL", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used; REQ on AD", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used; RSP on AD", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used; SNP on AD", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used; RSP on BL", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits; WB on BL", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB", + "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN1 Credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits; NCB on BL", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS", + "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN1 Credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits; REQ on AD", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ", + "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN1 Credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits; RSP on AD", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP", + "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN1 Credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits; SNP on AD", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP", + "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN1 Credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits; RSP on BL", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB", + "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN1 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_TxC_BL.DRS_UPI", + "Deprecated": "1", + "EventCode": "0x40", + "EventName": "UNC_NoUnit_TxC_BL.DRS_UPI", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Clocks of the Intel(R) Ultra Path Interconnect (UPI)", + "EventCode": "0x1", + "EventName": "UNC_UPI_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts clockticks of the fixed frequency clock controlling the Intel(R) Ultra Path Interconnect (UPI). This clock runs at1/8th the 'GT/s' speed of the UPI link. For example, a 9.6GT/s link will have a fixed Frequency of 1.2 Ghz.", + "Unit": "UPI" + }, + { + "BriefDescription": "Data Response packets that go direct to core", + "EventCode": "0x12", + "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C", + "PerPkg": "1", + "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to core bypassing the CHA.", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_DIRECT_ATTEMPTS.D2U", + "Deprecated": "1", + "EventCode": "0x12", + "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "Data Response packets that go direct to Intel(R) UPI", + "EventCode": "0x12", + "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2U", + "PerPkg": "1", + "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to Intel(R) Ultra Path Interconnect (UPI) bypassing the CHA .", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles Intel(R) UPI is in L1 power mode (shutdown)", + "EventCode": "0x21", + "EventName": "UNC_UPI_L1_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts cycles when the Intel(R) Ultra Path Interconnect (UPI) is in L1 power mode. L1 is a mode that totally shuts down the UPI link. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdown.", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "EventCode": "0x16", + "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1", + "EventCode": "0x20", + "EventName": "UNC_UPI_PHY_INIT_CYCLES", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "L1 Req Nack", + "EventCode": "0x23", + "EventName": "UNC_UPI_POWER_L1_NACK", + "PerPkg": "1", + "PublicDescription": "Counts the number of times a link sends/receives a LinkReqNAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx originally requested the power change). A Tx LinkReqNAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).", + "Unit": "UPI" + }, + { + "BriefDescription": "L1 Req (same as L1 Ack).", + "EventCode": "0x22", + "EventName": "UNC_UPI_POWER_L1_REQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of times a link sends/receives a LinkReqAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqAck refers to receiving an Ack (meaning this agent's Tx originally requested the power change). A Tx LinkReqAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles the Rx of the Intel(R) UPI is in L0p power mode", + "EventCode": "0x25", + "EventName": "UNC_UPI_RxL0P_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts cycles when the receive side (Rx) of the Intel(R) Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles in L0. Receive side.", + "EventCode": "0x24", + "EventName": "UNC_UPI_RxL0_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", + "PerPkg": "1", + "PublicDescription": "Match Message Class - NCB", + "UMask": "0xe", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC", + "PerPkg": "1", + "PublicDescription": "Match Message Class - NCB", + "UMask": "0x10e", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", + "PerPkg": "1", + "PublicDescription": "Match Message Class - NCS", + "UMask": "0xf", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC", + "PerPkg": "1", + "PublicDescription": "Match Message Class - NCS", + "UMask": "0x10f", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Request", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", + "PerPkg": "1", + "PublicDescription": "REQ Message Class", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Request Opcode", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC", + "PerPkg": "1", + "PublicDescription": "Match REQ Opcodes - Specified in Umask[7:4]", + "UMask": "0x108", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Response - Conflict", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT", + "PerPkg": "1", + "UMask": "0x1aa", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Response - Invalid", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI", + "PerPkg": "1", + "UMask": "0x12a", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", + "PerPkg": "1", + "PublicDescription": "Match Message Class -WB", + "UMask": "0xc", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC", + "PerPkg": "1", + "PublicDescription": "Match Message Class -WB", + "UMask": "0x10c", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA", + "PerPkg": "1", + "PublicDescription": "Match Message Class - RSP", + "UMask": "0xa", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", + "PerPkg": "1", + "PublicDescription": "Match Message Class - RSP", + "UMask": "0x10a", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Snoop", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", + "PerPkg": "1", + "PublicDescription": "SNP Message Class", + "UMask": "0x9", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Snoop Opcode", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC", + "PerPkg": "1", + "PublicDescription": "Match SNP Opcodes - Specified in Umask[7:4]", + "UMask": "0x109", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Writeback", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB", + "PerPkg": "1", + "PublicDescription": "Match Message Class -WB", + "UMask": "0xd", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Writeback", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC", + "PerPkg": "1", + "PublicDescription": "Match Message Class -WB", + "UMask": "0x10d", + "Unit": "UPI" + }, + { + "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", + "EventCode": "0x31", + "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", + "PerPkg": "1", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", + "EventCode": "0x31", + "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", + "PerPkg": "1", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer (Receive Queue) and passed directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", + "EventCode": "0x31", + "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", + "PerPkg": "1", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "VN0 Credit Consumed", + "EventCode": "0x39", + "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", + "Unit": "UPI" + }, + { + "BriefDescription": "VN1 Credit Consumed", + "EventCode": "0x3A", + "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", + "Unit": "UPI" + }, + { + "BriefDescription": "VNA Credit Consumed", + "EventCode": "0x38", + "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid data FLITs received from any slot", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", + "PerPkg": "1", + "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel(R) Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.", + "UMask": "0xf", + "Unit": "UPI" + }, + { + "BriefDescription": "Null FLITs received from any slot", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", + "PerPkg": "1", + "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel(R) Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.", + "UMask": "0x27", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received; Data", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.DATA", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received; Idle", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.IDLE", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).", + "UMask": "0x47", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received; LLCRD Not Empty", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.LLCRD", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received; LLCTRL", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.LLCTRL", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.", + "UMask": "0x40", + "Unit": "UPI" + }, + { + "BriefDescription": "Protocol header and credit FLITs received from any slot", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", + "PerPkg": "1", + "PublicDescription": "Counts protocol header and credit FLITs (80 bit FLow control unITs) received from any of the 3 UPI slots on this UPI unit.", + "UMask": "0x97", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.ALL_NULL", + "Deprecated": "1", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.NULL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received; Protocol Header", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.PROTHDR", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)", + "UMask": "0x80", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.PROTHDR", + "Deprecated": "1", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.PROT_HDR", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received; Slot 0", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.SLOT0", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 0 - Other mask bits determine types of headers to count.", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received; Slot 1", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.SLOT1", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 1 - Other mask bits determine types of headers to count.", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received; Slot 2", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.SLOT2", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 2 - Other mask bits determine types of headers to count.", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.NCB", + "PerPkg": "1", + "UMask": "0xc", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.NCS", + "PerPkg": "1", + "UMask": "0xd", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.REQ", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.RSP", + "PerPkg": "1", + "UMask": "0xa", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.SNP", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.WB", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.WB", + "PerPkg": "1", + "UMask": "0xb", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Flit Buffer Allocations; Slot 0", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Flit Buffer Allocations; Slot 1", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Flit Buffer Allocations; Slot 2", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT2", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets; Slot 0", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets; Slot 1", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets; Slot 2", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles in which the Tx of the Intel(R) Ultra Path Interconnect (UPI) is in L0p power mode", + "EventCode": "0x27", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts cycles when the transmit side (Tx) of the Intel(R) Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "EventCode": "0x28", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "EventCode": "0x29", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles in L0. Transmit side.", + "EventCode": "0x26", + "EventName": "UNC_UPI_TxL0_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", + "PerPkg": "1", + "PublicDescription": "Match Message Class - NCB", + "UMask": "0xe", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC", + "PerPkg": "1", + "PublicDescription": "Match Message Class - NCB", + "UMask": "0x10e", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", + "PerPkg": "1", + "PublicDescription": "Match Message Class - NCS", + "UMask": "0xf", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC", + "PerPkg": "1", + "PublicDescription": "Match Message Class - NCS", + "UMask": "0x10f", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Request", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", + "PerPkg": "1", + "PublicDescription": "REQ Message Class", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Request Opcode", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC", + "PerPkg": "1", + "PublicDescription": "Match REQ Opcodes - Specified in Umask[7:4]", + "UMask": "0x108", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Conflict", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT", + "PerPkg": "1", + "UMask": "0x1aa", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Invalid", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI", + "PerPkg": "1", + "UMask": "0x12a", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", + "PerPkg": "1", + "PublicDescription": "Match Message Class -WB", + "UMask": "0xc", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC", + "PerPkg": "1", + "PublicDescription": "Match Message Class -WB", + "UMask": "0x10c", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", + "PerPkg": "1", + "PublicDescription": "Match Message Class - RSP", + "UMask": "0xa", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", + "PerPkg": "1", + "PublicDescription": "Match Message Class - RSP", + "UMask": "0x10a", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", + "PerPkg": "1", + "PublicDescription": "SNP Message Class", + "UMask": "0x9", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop Opcode", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC", + "PerPkg": "1", + "PublicDescription": "Match SNP Opcodes - Specified in Umask[7:4]", + "UMask": "0x109", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB", + "PerPkg": "1", + "PublicDescription": "Match Message Class -WB", + "UMask": "0xd", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC", + "PerPkg": "1", + "PublicDescription": "Match Message Class -WB", + "UMask": "0x10d", + "Unit": "UPI" + }, + { + "BriefDescription": "FLITs that bypassed the TxL Buffer", + "EventCode": "0x41", + "EventName": "UNC_UPI_TxL_BYPASSED", + "PerPkg": "1", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel(R) Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link. However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR mode, increasing latency to transfer out to the link.", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid data FLITs transmitted via any slot", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", + "PerPkg": "1", + "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel(R) Ultra Path Interconnect (UPI) slots on this UPI unit.", + "UMask": "0xf", + "Unit": "UPI" + }, + { + "BriefDescription": "Null FLITs transmitted from any slot", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", + "PerPkg": "1", + "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel(R) Ulra Path Interconnect (UPI) slots on this UPI unit.", + "UMask": "0x27", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent; Data", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.DATA", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "Idle FLITs transmitted", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.IDLE", + "PerPkg": "1", + "PublicDescription": "Counts when the Intel Ultra Path Interconnect(UPI) transmits an idle FLIT(80 bit FLow control unITs). Every UPI cycle must be sending either data FLITs, protocol/credit FLITs or idle FLITs.", + "UMask": "0x47", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent; LLCRD Not Empty", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.LLCRD", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent; LLCTRL", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.LLCTRL", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.", + "UMask": "0x40", + "Unit": "UPI" + }, + { + "BriefDescription": "Protocol header and credit FLITs transmitted across any slot", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", + "PerPkg": "1", + "PublicDescription": "Counts protocol header and credit FLITs (80 bit FLow control unITs) transmitted across any of the 3 UPI (Ultra Path Interconnect) slots on this UPI unit.", + "UMask": "0x97", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.ALL_NULL", + "Deprecated": "1", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.NULL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent; Protocol Header", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.PROTHDR", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)", + "UMask": "0x80", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.PROTHDR", + "Deprecated": "1", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.PROT_HDR", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent; Slot 0", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.SLOT0", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 0 - Other mask bits determine types of headers to count.", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent; Slot 1", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.SLOT1", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 1 - Other mask bits determine types of headers to count.", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent; Slot 2", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.SLOT2", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 2 - Other mask bits determine types of headers to count.", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.DATA_HDR", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.DUAL_SLOT_HDR", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.LOC", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.NCB", + "PerPkg": "1", + "UMask": "0xe", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.NCS", + "PerPkg": "1", + "UMask": "0xf", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.NON_DATA_HDR", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.REM", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.REQ", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_DATA", + "PerPkg": "1", + "UMask": "0xc", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_NODATA", + "PerPkg": "1", + "UMask": "0xa", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.SGL_SLOT_HDR", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.SNP", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.WB", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.WB", + "PerPkg": "1", + "UMask": "0xc", + "Unit": "UPI" + }, + { + "BriefDescription": "Tx Flit Buffer Allocations", + "EventCode": "0x40", + "EventName": "UNC_UPI_TxL_INSERTS", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the UPI Tx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", + "Unit": "UPI" + }, + { + "BriefDescription": "Tx Flit Buffer Occupancy", + "EventCode": "0x42", + "EventName": "UNC_UPI_TxL_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of flits in the TxQ. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "EventCode": "0x45", + "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "VNA Credits Pending Return - Occupancy", + "EventCode": "0x44", + "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.", + "Unit": "UPI" + }, + { + "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", + "EventCode": "0xff", + "EventName": "UNC_U_CLOCKTICKS", + "PerPkg": "1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.INT_PRIO", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received; IPI", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.; Inter Processor Interrupts", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received; MSI", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.; Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received; VLW", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "IDI Lock/SplitLock Cycles", + "EventCode": "0x44", + "EventName": "UNC_U_LOCK_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of times an IDI Lock/SplitLock sequence was started", + "Unit": "UBOX" + }, + { + "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", + "EventCode": "0x45", + "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", + "PerPkg": "1", + "PublicDescription": "PHOLD cycles.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_RACU_DRNG.RDRAND", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.RDRAND", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_RACU_DRNG.RDSEED", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.RDSEED", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "RACU Request", + "EventCode": "0x46", + "EventName": "UNC_U_RACU_REQUESTS", + "PerPkg": "1", + "PublicDescription": "Number outstanding register requests within message channel tracker", + "Unit": "UBOX" + }, + { + "BriefDescription": "UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data", + "EventCode": "0x2", + "EventName": "UPI_DATA_BANDWIDTH_TX", + "PerPkg": "1", + "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel(R) Ultra Path Interconnect (UPI) slots on this UPI unit.", + "ScaleUnit": "7.11E-06Bytes", + "UMask": "0xf", + "Unit": "UPI" + } +] diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-io.json b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-io.json new file mode 100644 index 000000000000..743c91f3d2f0 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-io.json @@ -0,0 +1,4250 @@ +[ + { + "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0", + "EventCode": "0x83", + "EventName": "LLC_MISSES.PCIE_READ", + "FCMask": "0x07", + "Filter": "ch_mask=0x1f", + "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "MetricName": "LLC_MISSES.PCIE_READ", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "ScaleUnit": "4Bytes", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0", + "EventCode": "0x83", + "EventName": "LLC_MISSES.PCIE_WRITE", + "FCMask": "0x07", + "Filter": "ch_mask=0x1f", + "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "MetricName": "LLC_MISSES.PCIE_WRITE", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "ScaleUnit": "4Bytes", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Clockticks of the IIO Traffic Controller", + "EventCode": "0x1", + "EventName": "UNC_IIO_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts clockticks of the 1GHz traffic controller clock in the IIO unit.", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x0f", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts; Port 0", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts; Port 1", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts; Port 2", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts; Port 3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0xf", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part2", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made to IIO Part0 by the CPU", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made to IIO Part1 by the CPU", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made to IIO Part2 by the CPU", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made to IIO Part3 by the CPU", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth reading at IIO, part 0", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth reading at IIO, part 1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth reading at IIO, part 2", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth reading at IIO, part 3", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card reading from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card reading from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO, part 0", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO, part 1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO, part 2", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO, part 3", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card writing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card writing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Num Link Correctable Errors", + "EventCode": "0xF", + "EventName": "UNC_IIO_LINK_NUM_CORR_ERR", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Num Link Retries", + "EventCode": "0xE", + "EventName": "UNC_IIO_LINK_NUM_RETRIES", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number packets that passed the Mask/Match Filter", + "EventCode": "0x21", + "EventName": "UNC_IIO_MASK_MATCH", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0", + "PerPkg": "1", + "PublicDescription": "Asserted if all bits specified by mask match", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and PCIE bus", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1", + "PerPkg": "1", + "PublicDescription": "Asserted if all bits specified by mask match", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and !(PCIE bus)", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1", + "PerPkg": "1", + "PublicDescription": "Asserted if all bits specified by mask match", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus; PCIE bus", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1", + "PerPkg": "1", + "PublicDescription": "Asserted if all bits specified by mask match", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1", + "PerPkg": "1", + "PublicDescription": "Asserted if all bits specified by mask match", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1", + "PerPkg": "1", + "PublicDescription": "Asserted if all bits specified by mask match", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0", + "PerPkg": "1", + "PublicDescription": "Asserted if any bits specified by mask match", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and PCIE bus", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1", + "PerPkg": "1", + "PublicDescription": "Asserted if any bits specified by mask match", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and !(PCIE bus)", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1", + "PerPkg": "1", + "PublicDescription": "Asserted if any bits specified by mask match", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus; PCIE bus", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1", + "PerPkg": "1", + "PublicDescription": "Asserted if any bits specified by mask match", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1", + "PerPkg": "1", + "PublicDescription": "Asserted if any bits specified by mask match", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) and !(PCIE bus)", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1", + "PerPkg": "1", + "PublicDescription": "Asserted if any bits specified by mask match", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Counting disabled", + "EventName": "UNC_IIO_NOTHING", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Symbol Times on Link", + "EventCode": "0x82", + "EventName": "UNC_IIO_SYMBOL_TIMES", + "PerPkg": "1", + "PublicDescription": "Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part2", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part0 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part1 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part1 to the MMIO space of an IIO target.In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; context cache miss", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.CTXT_MISS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; L1 miss", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.L1_MISS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; L2 miss", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.L2_MISS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; L3 miss", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.L3_MISS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; Vtd hit", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.L4_PAGE_HIT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; TLB miss", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.TLB1_MISS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; TLB is full", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.TLB_FULL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; TLB miss", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.TLB_MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Occupancy", + "EventCode": "0x40", + "EventName": "UNC_IIO_VTD_OCCUPANCY", + "PerPkg": "1", + "Unit": "IIO" + } +] diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json index aafd2c9b813b..f761856d738e 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json @@ -2735,7 +2735,7 @@ "EventCode": "0x81", "EventName": "UNC_M_WPQ_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller). They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. Is there a filter of sorts???", + "PublicDescription": "Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller). They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. Is there a filter of sorts?", "Unit": "iMC" }, { diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json deleted file mode 100644 index 5f3ed5e843b9..000000000000 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json +++ /dev/null @@ -1,26344 +0,0 @@ -[ - { - "BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.ia_miss", - "EventCode": "0x35", - "EventName": "LLC_MISSES.MMIO_READ", - "Filter": "config1=0x40040e33", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss", - "EventCode": "0x35", - "EventName": "LLC_MISSES.MMIO_WRITE", - "Filter": "config1=0x40041e33", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0", - "EventCode": "0x83", - "EventName": "LLC_MISSES.PCIE_READ", - "FCMask": "0x07", - "Filter": "ch_mask=0x1f", - "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "MetricName": "LLC_MISSES.PCIE_READ", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "ScaleUnit": "4Bytes", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0", - "EventCode": "0x83", - "EventName": "LLC_MISSES.PCIE_WRITE", - "FCMask": "0x07", - "Filter": "ch_mask=0x1f", - "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "MetricName": "LLC_MISSES.PCIE_WRITE", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "ScaleUnit": "4Bytes", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss", - "EventCode": "0x35", - "EventName": "LLC_MISSES.UNCACHEABLE", - "Filter": "config1=0x40e33", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.STREAMING_FULL", - "Filter": "config1=0x41833", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "ScaleUnit": "64Bytes", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.STREAMING_PARTIAL", - "Filter": "config1=0x41a33", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "ScaleUnit": "64Bytes", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA to iMC Bypass; Intermediate bypass Taken", - "EventCode": "0x57", - "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the intermediate bypass.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA to iMC Bypass; Not Taken", - "EventCode": "0x57", - "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA to iMC Bypass; Taken", - "EventCode": "0x57", - "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the full bypass.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Uncore cache clock ticks", - "EventName": "UNC_CHA_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Counts clockticks of the clock controlling the uncore caching and home agent (CHA).", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Clockticks", - "EventCode": "0xC0", - "EventName": "UNC_CHA_CMS_CLOCKTICKS", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "Core PMA Events; C1 State", - "EventCode": "0x17", - "EventName": "UNC_CHA_CORE_PMA.C1_STATE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Core PMA Events; C1 Transition", - "EventCode": "0x17", - "EventName": "UNC_CHA_CORE_PMA.C1_TRANSITION", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Core PMA Events; C6 State", - "EventCode": "0x17", - "EventName": "UNC_CHA_CORE_PMA.C6_STATE", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Core PMA Events; C6 Transition", - "EventCode": "0x17", - "EventName": "UNC_CHA_CORE_PMA.C6_TRANSITION", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Core PMA Events; GV", - "EventCode": "0x17", - "EventName": "UNC_CHA_CORE_PMA.GV", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Any Cycle with Multiple Snoops", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE", - "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0xe2", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Any Single Snoop", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.ANY_ONE", - "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0xe1", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Any Snoop to Remote Node", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.ANY_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0xe4", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Multiple Core Requests", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE", - "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x42", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Single Core Requests", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.CORE_ONE", - "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x41", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Core Request to Remote Node", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.CORE_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Multiple Eviction", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE", - "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x82", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Single Eviction", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE", - "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x81", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Eviction to Remote Node", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EVICT_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x84", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Multiple External Snoops", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE", - "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x22", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Single External Snoops", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EXT_ONE", - "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; External Snoop to Remote Node", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EXT_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "Counter 0 Occupancy", - "EventCode": "0x1F", - "EventName": "UNC_CHA_COUNTER0_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.", - "Unit": "CHA" - }, - { - "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed", - "EventCode": "0x53", - "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP", - "PerPkg": "1", - "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed", - "EventCode": "0x53", - "EventName": "UNC_CHA_DIR_LOOKUP.SNP", - "PerPkg": "1", - "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe", - "EventCode": "0x54", - "EventName": "UNC_CHA_DIR_UPDATE.HA", - "PerPkg": "1", - "PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe", - "EventCode": "0x54", - "EventName": "UNC_CHA_DIR_UPDATE.TOR", - "PerPkg": "1", - "PublicDescription": "Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements; Down", - "EventCode": "0xAE", - "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", - "PerPkg": "1", - "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements; Up", - "EventCode": "0xAE", - "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", - "PerPkg": "1", - "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "FaST wire asserted; Horizontal", - "EventCode": "0xA5", - "EventName": "UNC_CHA_FAST_ASSERTED.HORZ", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "FaST wire asserted; Vertical", - "EventCode": "0xA5", - "EventName": "UNC_CHA_FAST_ASSERTED.VERT", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state", - "EventCode": "0x5F", - "EventName": "UNC_CHA_HITME_HIT.EX_RDS", - "PerPkg": "1", - "PublicDescription": "Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state. This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*)", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of Hits in HitMe Cache; Shared hit and op is RdInvOwn, RdInv, Inv*", - "EventCode": "0x5F", - "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE", - "EventCode": "0x5F", - "EventName": "UNC_CHA_HITME_HIT.WBMTOE", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", - "EventCode": "0x5F", - "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*", - "EventCode": "0x5E", - "EventName": "UNC_CHA_HITME_LOOKUP.READ", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", - "EventCode": "0x5E", - "EventName": "UNC_CHA_HITME_LOOKUP.WRITE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of Misses in HitMe Cache; No SF/LLC HitS/F and op is RdInvOwn", - "EventCode": "0x60", - "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of Misses in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*", - "EventCode": "0x60", - "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of Misses in HitMe Cache; SF/LLC HitS/F and op is RdInvOwn", - "EventCode": "0x60", - "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Deallocate HitME$ on Reads without RspFwdI*", - "EventCode": "0x61", - "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a local request", - "EventCode": "0x61", - "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", - "PerPkg": "1", - "PublicDescription": "Received RspFwdI* for a local request, but converted HitME$ to SF entry", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache on RdInvOwn even if not RspFwdI*", - "EventCode": "0x61", - "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request", - "EventCode": "0x61", - "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM", - "PerPkg": "1", - "PublicDescription": "Updated HitME$ on RspFwdI* or local HitM/E received for a remote request", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache to SHARed", - "EventCode": "0x61", - "EventName": "UNC_CHA_HITME_UPDATE.SHARED", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AD Ring In Use; Left and Even", - "EventCode": "0xA7", - "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", - "EventCode": "0xA7", - "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AD Ring In Use; Right and Even", - "EventCode": "0xA7", - "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", - "EventCode": "0xA7", - "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AK Ring In Use; Left and Even", - "EventCode": "0xA9", - "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", - "EventCode": "0xA9", - "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AK Ring In Use; Right and Even", - "EventCode": "0xA9", - "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", - "EventCode": "0xA9", - "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal BL Ring in Use; Left and Even", - "EventCode": "0xAB", - "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", - "EventCode": "0xAB", - "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal BL Ring in Use; Right and Even", - "EventCode": "0xAB", - "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", - "EventCode": "0xAB", - "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal IV Ring in Use; Left", - "EventCode": "0xAD", - "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal IV Ring in Use; Right", - "EventCode": "0xAD", - "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Normal priority reads issued to the memory controller from the CHA", - "EventCode": "0x59", - "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", - "PerPkg": "1", - "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "HA to iMC Reads Issued; ISOCH", - "EventCode": "0x59", - "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY", - "PerPkg": "1", - "PublicDescription": "Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", - "PerPkg": "1", - "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Writes Issued to the iMC by the HA; Full Line MIG", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_MIG", - "PerPkg": "1", - "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Full Line", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", - "PerPkg": "1", - "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Writes Issued to the iMC by the HA; Partial Non-ISOCH", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", - "PerPkg": "1", - "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Writes Issued to the iMC by the HA; Partial MIG", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG", - "PerPkg": "1", - "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.; Filter for memory controller 5 only.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Partial", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", - "PerPkg": "1", - "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations", - "EventCode": "0x62", - "EventName": "UNC_CHA_IODC_ALLOC.INVITOM", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations dropped due to IODC Full", - "EventCode": "0x62", - "EventName": "UNC_CHA_IODC_ALLOC.IODCFULL", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IDOC allocation dropped due to OSB gate", - "EventCode": "0x62", - "EventName": "UNC_CHA_IODC_ALLOC.OSBGATED", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to any reason", - "EventCode": "0x63", - "EventName": "UNC_CHA_IODC_DEALLOC.ALL", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to conflicting transaction", - "EventCode": "0x63", - "EventName": "UNC_CHA_IODC_DEALLOC.SNPOUT", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoE", - "EventCode": "0x63", - "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoI", - "EventCode": "0x63", - "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOI", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbPushMtoI", - "EventCode": "0x63", - "EventName": "UNC_CHA_IODC_DEALLOC.WBPUSHMTOI", - "PerPkg": "1", - "PublicDescription": "Moved to Cbo section", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache and Snoop Filter Lookups; Any Request", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.ANY", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Read transactions", - "UMask": "0x3", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache and Snoop Filter Lookups; Local", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.", - "UMask": "0x31", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache and Snoop Filter Lookups; Remote", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.", - "UMask": "0x91", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache and Snoop Filter Lookups; External Snoop Request", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ.", - "UMask": "0x9", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache and Snoop Filter Lookups; Write Requests", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.WRITE", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.", - "UMask": "0x5", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.F_STATE", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Local - All Lines", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x2f", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Local - Lines in E State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x22", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Local - Lines in F State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_F", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x28", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Local - Lines in M State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Local - Lines in S State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Remote - All Lines", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x8f", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Remote - Lines in E State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x82", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Remote - Lines in F State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_F", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x88", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Remote - Lines in M State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x81", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Remote - Lines in S State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x84", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Lines in E state", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Lines in F State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_F", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Lines in M state", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Lines in S State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cbo Misc; CV0 Prefetch Miss", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.CV0_PREF_MISS", - "PerPkg": "1", - "PublicDescription": "Miscellaneous events in the Cbo.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Cbo Misc; CV0 Prefetch Victim", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.CV0_PREF_VIC", - "PerPkg": "1", - "PublicDescription": "Miscellaneous events in the Cbo.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Number of times that an RFO hit in S state.", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.RFO_HIT_S", - "PerPkg": "1", - "PublicDescription": "Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cbo Misc; Silent Snoop Eviction", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE", - "PerPkg": "1", - "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cbo Misc; Write Combining Aliasing", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.WC_ALIASING", - "PerPkg": "1", - "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "OSB Snoop Broadcast", - "EventCode": "0x55", - "EventName": "UNC_CHA_OSB", - "PerPkg": "1", - "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", - "Unit": "CHA" - }, - { - "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in IODC", - "EventCode": "0x64", - "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.IODC", - "PerPkg": "1", - "PublicDescription": "2LM related events; Counts the number of times CHA saw NM Set conflict in IODC", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in SF/LLC", - "EventCode": "0x64", - "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC", - "PerPkg": "1", - "PublicDescription": "NM evictions due to another read to the same near memory set in the LLC.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in SF/LLC", - "EventCode": "0x64", - "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF", - "PerPkg": "1", - "PublicDescription": "NM evictions due to another read to the same near memory set in the SF.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Memory Mode related events; Counts the number of times CHA saw NM Set conflict in TOR", - "EventCode": "0x64", - "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR", - "PerPkg": "1", - "PublicDescription": "No Reject in the CHA due to a pending read to the same near memory set in the TOR.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Memory mode related events; Counts the number of times CHA saw NM Set conflict in TOR and the transaction was rejected", - "EventCode": "0x64", - "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR_REJECT", - "PerPkg": "1", - "PublicDescription": "Rejects in the CHA due to a pending read to the same near memory set in the TOR.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC0_SMI2", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.EDC0_SMI2", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 2 only.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC1_SMI3", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.EDC1_SMI3", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 3 only.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC2_SMI4", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.EDC2_SMI4", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 4 only.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC3_SMI5", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.EDC3_SMI5", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 5 only.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC0_SMI0", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC0_SMI0", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 0 only.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC1_SMI1", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC1_SMI1", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 1 only.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", - "PerPkg": "1", - "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Read requests", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.READS", - "PerPkg": "1", - "PublicDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) .", - "UMask": "0x3", - "Unit": "CHA" - }, - { - "BriefDescription": "Read requests from a unit on this socket", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", - "PerPkg": "1", - "PublicDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Read requests from a remote socket", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Write requests", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.WRITES", - "PerPkg": "1", - "PublicDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", - "UMask": "0xc", - "Unit": "CHA" - }, - { - "BriefDescription": "Write Requests from a unit on this socket", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", - "PerPkg": "1", - "PublicDescription": "Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Read and Write Requests; Writes Remote", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD", - "EventCode": "0xA1", - "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK", - "EventCode": "0xA1", - "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL", - "EventCode": "0xA1", - "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV", - "EventCode": "0xA1", - "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.; AD", - "EventCode": "0xA0", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core", - "EventCode": "0xA0", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core", - "EventCode": "0xA0", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.", - "EventCode": "0xA0", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; AD", - "EventCode": "0xA3", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; AK", - "EventCode": "0xA3", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1", - "EventCode": "0xA3", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; BL", - "EventCode": "0xA3", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; IV", - "EventCode": "0xA3", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring; AD", - "EventCode": "0xA2", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core", - "EventCode": "0xA2", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core", - "EventCode": "0xA2", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.", - "EventCode": "0xA2", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Source Throttle", - "EventCode": "0xA4", - "EventName": "UNC_CHA_RING_SRC_THRTL", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations; IPQ", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.IPQ", - "PerPkg": "1", - "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations; IRQ", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.IRQ", - "PerPkg": "1", - "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations; IRQ Rejected", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ", - "PerPkg": "1", - "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations; PRQ", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.PRQ", - "PerPkg": "1", - "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations; PRQ", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ", - "PerPkg": "1", - "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations; RRQ", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.RRQ", - "PerPkg": "1", - "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations; WBQ", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.WBQ", - "PerPkg": "1", - "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; AD REQ on VN0", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; AD RSP on VN0", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; Non UPI AK Request", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; BL NCB on VN0", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; BL NCS on VN0", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; BL RSP on VN0", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; BL WB on VN0", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; Non UPI IV Request", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; Allow Snoop", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; ANY0", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; HA", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; Merging these two together to make room for ANY_REJECT_*0", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; LLC Victim", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; PhyAddr Match", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; SF Victim", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; Victim", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Merging these two together to make room for ANY_REJECT_*0", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects; AD REQ on VN0", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects; AD RSP on VN0", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects; Non UPI AK Request", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects; BL NCB on VN0", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects; BL NCS on VN0", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects; BL RSP on VN0", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects; BL WB on VN0", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects; Non UPI IV Request", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries; AD REQ on VN0", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries; AD RSP on VN0", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries; Non UPI AK Request", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries; BL NCB on VN0", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries; BL NCS on VN0", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries; BL RSP on VN0", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries; BL WB on VN0", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries; Non UPI IV Request", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects; ANY0", - "EventCode": "0x25", - "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects; HA", - "EventCode": "0x25", - "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries; ANY0", - "EventCode": "0x2D", - "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries; HA", - "EventCode": "0x2D", - "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Occupancy; IPQ", - "EventCode": "0x11", - "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ", - "PerPkg": "1", - "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Occupancy; IRQ", - "EventCode": "0x11", - "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ", - "PerPkg": "1", - "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Occupancy; RRQ", - "EventCode": "0x11", - "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ", - "PerPkg": "1", - "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Occupancy; WBQ", - "EventCode": "0x11", - "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ", - "PerPkg": "1", - "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; AD REQ on VN0", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; AD RSP on VN0", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; Non UPI AK Request", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; BL NCB on VN0", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; BL NCS on VN0", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; BL RSP on VN0", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; BL WB on VN0", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; Non UPI IV Request", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; Allow Snoop", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; ANY0", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; HA", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; Merging these two together to make room for ANY_REJECT_*0", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; LLC Victim", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; PhyAddr Match", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; SF Victim", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; Victim", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC OR SF Way", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; AD REQ on VN0", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; AD RSP on VN0", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; Non UPI AK Request", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; BL NCB on VN0", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; BL NCS on VN0", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; BL RSP on VN0", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; BL WB on VN0", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; Non UPI IV Request", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; Allow Snoop", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; ANY0", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; HA", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; Merging these two together to make room for ANY_REJECT_*0", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; LLC Victim", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; PhyAddr Match", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; SF Victim", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; Victim", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; AD REQ on VN0", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; AD RSP on VN0", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; Non UPI AK Request", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; BL NCB on VN0", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; BL NCS on VN0", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; BL RSP on VN0", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; BL WB on VN0", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; Non UPI IV Request", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; Allow Snoop", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; ANY0", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; HA", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; Merging these two together to make room for ANY_REJECT_*0", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; LLC Victim", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; PhyAddr Match", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; SF Victim", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; Victim", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; AD REQ on VN0", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; AD RSP on VN0", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; Non UPI AK Request", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; BL NCB on VN0", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; BL NCS on VN0", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; BL RSP on VN0", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; BL WB on VN0", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; Non UPI IV Request", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; Allow Snoop", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; ANY0", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; HA", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; Merging these two together to make room for ANY_REJECT_*0", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; LLC Victim", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; PhyAddr Match", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; SF Victim", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; Victim", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation; AD - Bounce", - "EventCode": "0xB4", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation; AD - Credit", - "EventCode": "0xB4", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation; BL - Bounce", - "EventCode": "0xB4", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation; BL - Credit", - "EventCode": "0xB4", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", - "EventCode": "0xB2", - "EventName": "UNC_CHA_RxR_BYPASS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass; AD - Credit", - "EventCode": "0xB2", - "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", - "EventCode": "0xB2", - "EventName": "UNC_CHA_RxR_BYPASS.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", - "EventCode": "0xB2", - "EventName": "UNC_CHA_RxR_BYPASS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass; BL - Credit", - "EventCode": "0xB2", - "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", - "EventCode": "0xB2", - "EventName": "UNC_CHA_RxR_BYPASS.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation; AD - Bounce", - "EventCode": "0xB3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation; AD - Credit", - "EventCode": "0xB3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation; AK - Bounce", - "EventCode": "0xB3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation; BL - Bounce", - "EventCode": "0xB3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation; BL - Credit", - "EventCode": "0xB3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation; IFV - Credit", - "EventCode": "0xB3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation; IV - Bounce", - "EventCode": "0xB3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", - "EventCode": "0xB1", - "EventName": "UNC_CHA_RxR_INSERTS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations; AD - Credit", - "EventCode": "0xB1", - "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", - "EventCode": "0xB1", - "EventName": "UNC_CHA_RxR_INSERTS.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", - "EventCode": "0xB1", - "EventName": "UNC_CHA_RxR_INSERTS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations; BL - Credit", - "EventCode": "0xB1", - "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", - "EventCode": "0xB1", - "EventName": "UNC_CHA_RxR_INSERTS.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", - "EventCode": "0xB0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", - "EventCode": "0xB0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", - "EventCode": "0xB0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", - "EventCode": "0xB0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", - "EventCode": "0xB0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", - "EventCode": "0xB0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop filter capacity evictions for E-state entries.", - "EventCode": "0x3D", - "EventName": "UNC_CHA_SF_EVICTION.E_STATE", - "PerPkg": "1", - "PublicDescription": "Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop filter capacity evictions for M-state entries.", - "EventCode": "0x3D", - "EventName": "UNC_CHA_SF_EVICTION.M_STATE", - "PerPkg": "1", - "PublicDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop filter capacity evictions for S-state entries.", - "EventCode": "0x3D", - "EventName": "UNC_CHA_SF_EVICTION.S_STATE", - "PerPkg": "1", - "PublicDescription": "Counts snoop filter capacity evictions for entries tracking shared lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent; All", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.ALL", - "PerPkg": "1", - "PublicDescription": "Counts the number of snoops issued by the HA.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent; Broadcast snoop for Local Requests", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL", - "PerPkg": "1", - "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast snoops issued by the HA. This filter includes only requests coming from local sockets.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent; Broadcast snoops for Remote Requests", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast snoops issued by the HA.This filter includes only requests coming from remote sockets.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent; Directed snoops for Local Requests", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", - "PerPkg": "1", - "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of directed snoops issued by the HA. This filter includes only requests coming from local sockets.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent; Directed snoops for Remote Requests", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of directed snoops issued by the HA. This filter includes only requests coming from remote sockets.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Local Requests", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL", - "PerPkg": "1", - "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the local socket.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Remote Requests", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the remote socket.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "RspCnflct* Snoop Responses Received", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCTS", - "PerPkg": "1", - "PublicDescription": "Counts when a a transaction with the opcode type RspCnflct* Snoop Response was received. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent. This triggers conflict resolution hardware. This covers both the opcode RspCnflct and RspCnflctWbI.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received; RspFwd", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD", - "PerPkg": "1", - "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspFwd to a CA request. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "RspI Snoop Responses Received", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPI", - "PerPkg": "1", - "PublicDescription": "Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data).", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "RspIFwd Snoop Responses Received", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD", - "PerPkg": "1", - "PublicDescription": "Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received : RspS", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPS", - "PerPkg": "1", - "PublicDescription": "Snoop Responses Received : RspS : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for snoop responses of RspS. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "RspSFwd Snoop Responses Received", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD", - "PerPkg": "1", - "PublicDescription": "Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Rsp*Fwd*WB Snoop Responses Received", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSP_FWD_WB", - "PerPkg": "1", - "PublicDescription": "Counts when a transaction with the opcode type Rsp*Fwd*WB Snoop Response was received which indicates the data was written back to its home socket, and the cacheline was forwarded to the requestor socket. This snoop response is only used in >= 4 socket systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to its home socket to be written back to memory.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Rsp*WB Snoop Responses Received", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB", - "PerPkg": "1", - "PublicDescription": "Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to its home. This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured. This response will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local; RspCnflct", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", - "PerPkg": "1", - "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoops responses of RspConflict to local CA requests. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local; RspFwd", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", - "PerPkg": "1", - "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspFwd to local CA requests. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local; RspI", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI", - "PerPkg": "1", - "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoops responses of RspI to local CA requests. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local; RspIFwd", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", - "PerPkg": "1", - "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoop responses of RspIFwd to local CA requests. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local; RspS", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS", - "PerPkg": "1", - "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoop responses of RspS to local CA requests. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local; RspSFwd", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", - "PerPkg": "1", - "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspSFwd to local CA requests. This is returned when a remote caching agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB", - "PerPkg": "1", - "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of Rsp*Fwd*WB to local CA requests. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local; Rsp*WB", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB", - "PerPkg": "1", - "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspIWB or RspSWB to local CA requests. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; All", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.ALL", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "UMask": "0xff", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; Hits from Local", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.ALL_HIT", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "UMask": "0x15", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; All from Local iA and IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.ALL_IO_IA", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests", - "UMask": "0x35", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; Misses from Local", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.ALL_MISS", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "UMask": "0x25", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; SF/LLC Evictions", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.EVICT", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; Hit (Not a Miss)", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.HIT", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; HITs (hit is defined to be not a miss [see below], as a result for any request allocated into the TOR, one of either HIT or MISS must be true)", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; All from Local iA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests from iA Cores", - "UMask": "0x31", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; Hits from Local iA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", - "Filter": "config1=0x40233", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", - "Filter": "config1=0x40433", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", - "Filter": "config1=0x4b233", - "PerPkg": "1", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", - "Filter": "config1=0x4b433", - "PerPkg": "1", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefRFO", - "Filter": "config1=0x4b033", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", - "Filter": "config1=0x40033", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", - "Filter": "config1=0x40233", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", - "Filter": "config1=0x40433", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", - "Filter": "config1=0x4b233", - "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", - "Filter": "config1=0x4b433", - "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefRFO", - "Filter": "config1=0x4b033", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", - "Filter": "config1=0x40033", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; All from Local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally generated IO traffic", - "UMask": "0x34", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; Hits from Local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "UMask": "0x14", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; Misses from Local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; ItoM misses from Local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", - "Filter": "config1=0x49033", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that are generated from local IO ItoM requests that miss the LLC. An ItoM request is used by IIO to request a data write without first reading the data for ownership.", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; RdCur misses from Local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RDCUR", - "Filter": "config1=0x43C33", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that are generated from local IO RdCur requests and miss the LLC. A RdCur request is used by IIO to read data without changing state.", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; RFO misses from Local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", - "Filter": "config1=0x40033", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that are generated from local IO RFO requests that miss the LLC. A read for ownership (RFO) requests a cache line to be cached in E state with the intent to modify.", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; IPQ", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IPQ", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IPQ_HIT", - "PerPkg": "1", - "UMask": "0x18", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IPQ_MISS", - "PerPkg": "1", - "UMask": "0x28", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; IRQ", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IRQ", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", - "PerPkg": "1", - "UMask": "0x37", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; Miss", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.MISS", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; Misses. (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to a local memory controller, in the event that the CHA is the home node)). Basically, if the LLC/SF/MLC complex were not able to service the request without involving another agent...it is a miss. If only IDI snoops were required, it is not a miss (that means the SF/MLC com", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; PRQ", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.PRQ", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL", - "PerPkg": "1", - "UMask": "0x30", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.RRQ_HIT", - "PerPkg": "1", - "UMask": "0x50", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS", - "PerPkg": "1", - "UMask": "0x60", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.WBQ_HIT", - "PerPkg": "1", - "UMask": "0x90", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.WBQ_MISS", - "PerPkg": "1", - "UMask": "0xa0", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xff", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; All from Local", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All remotely generated requests", - "UMask": "0x37", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; Hits from Local", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_HIT", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "UMask": "0x17", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; Misses from Local", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_MISS", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "UMask": "0x27", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; SF/LLC Evictions", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; Hit (Not a Miss)", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; HITs (hit is defined to be not a miss [see below], as a result for any request allocated into the TOR, one of either HIT or MISS must be true)", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; All from Local iA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; All locally initiated requests from iA Cores", - "UMask": "0x31", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; Hits from Local iA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", - "Filter": "config1=0x40233", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", - "Filter": "config1=0x40433", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", - "Filter": "config1=0x4b233", - "PerPkg": "1", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", - "Filter": "config1=0x4b433", - "PerPkg": "1", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", - "Filter": "config1=0x4b033", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", - "Filter": "config1=0x40033", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; Misses from Local iA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", - "Filter": "config1=0x40233", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", - "Filter": "config1=0x40433", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", - "Filter": "config1=0x4b233", - "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", - "Filter": "config1=0x4b433", - "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", - "Filter": "config1=0x4b033", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", - "Filter": "config1=0x40033", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; All from Local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; All locally generated IO traffic", - "UMask": "0x34", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; Hits from Local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "UMask": "0x14", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; Misses from Local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; ITOM Misses from Local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", - "Filter": "config1=0x49033", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO ItoM requests that miss the LLC. An ItoM is used by IIO to request a data write without first reading the data for ownership.", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; RDCUR misses from Local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RDCUR", - "Filter": "config1=0x43C33", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO RdCur requests that miss the LLC. A RdCur request is used by IIO to read data without changing state.", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; RFO misses from Local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", - "Filter": "config1=0x40033", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO RFO requests that miss the LLC. A read for ownership (RFO) requests data to be cached in E state with the intent to modify.", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; IPQ", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_HIT", - "PerPkg": "1", - "UMask": "0x18", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_MISS", - "PerPkg": "1", - "UMask": "0x28", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; IRQ", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", - "PerPkg": "1", - "UMask": "0x37", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; Miss", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; Misses. (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to a local memory controller, in the event that the CHA is the home node)). Basically, if the LLC/SF/MLC complex were not able to service the request without involving another agent...it is a miss. If only IDI snoops were required, it is not a miss (that means the SF/MLC com", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; PRQ", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", - "EventCode": "0x9F", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", - "EventCode": "0x9F", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", - "EventCode": "0x9F", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", - "EventCode": "0x9F", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", - "EventCode": "0x9F", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", - "EventCode": "0x9F", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce", - "EventCode": "0x97", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit", - "EventCode": "0x97", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce", - "EventCode": "0x97", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce", - "EventCode": "0x97", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit", - "EventCode": "0x97", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce", - "EventCode": "0x97", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", - "EventCode": "0x95", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", - "EventCode": "0x95", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", - "EventCode": "0x95", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", - "EventCode": "0x95", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", - "EventCode": "0x95", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", - "EventCode": "0x95", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", - "EventCode": "0x99", - "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", - "EventCode": "0x99", - "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", - "EventCode": "0x99", - "EventName": "UNC_CHA_TxR_HORZ_NACK.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", - "EventCode": "0x99", - "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", - "EventCode": "0x99", - "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", - "EventCode": "0x99", - "EventName": "UNC_CHA_TxR_HORZ_NACK.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce", - "EventCode": "0x9B", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce", - "EventCode": "0x9B", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce", - "EventCode": "0x9B", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce", - "EventCode": "0x9B", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; IV", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.IV", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.IV", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; IV", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_INSERTS.IV", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; IV", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK.IV", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; IV", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.IV", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED.IV", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credit Allocations; AD REQ Credits", - "EventCode": "0x38", - "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credit Allocations; AD RSP VN0 Credits", - "EventCode": "0x38", - "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credit Allocations; BL NCB Credits", - "EventCode": "0x38", - "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credit Allocations; BL NCS Credits", - "EventCode": "0x38", - "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credit Allocations; BL RSP Credits", - "EventCode": "0x38", - "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credit Allocations; BL DRS Credits", - "EventCode": "0x38", - "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_WB", - "PerPkg": "1", - "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credit Allocations; VN0 Credits", - "EventCode": "0x38", - "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VN0", - "PerPkg": "1", - "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credit Allocations; VNA Credits", - "EventCode": "0x38", - "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VNA", - "PerPkg": "1", - "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credits In Use Cycles; AD REQ VN0 Credits", - "EventCode": "0x3B", - "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_REQ", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credits In Use Cycles; AD RSP VN0 Credits", - "EventCode": "0x3B", - "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_RSP", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCB VN0 Credits", - "EventCode": "0x3B", - "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCB", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCS VN0 Credits", - "EventCode": "0x3B", - "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCS", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credits In Use Cycles; BL RSP VN0 Credits", - "EventCode": "0x3B", - "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_RSP", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credits In Use Cycles; BL DRS VN0 Credits", - "EventCode": "0x3B", - "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_WB", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credits In Use Cycles; AD VNA Credits", - "EventCode": "0x3B", - "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_AD", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credits In Use Cycles; BL VNA Credits", - "EventCode": "0x3B", - "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_BL", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AD Ring In Use; Down and Even", - "EventCode": "0xA6", - "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AD Ring In Use; Down and Odd", - "EventCode": "0xA6", - "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AD Ring In Use; Up and Even", - "EventCode": "0xA6", - "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AD Ring In Use; Up and Odd", - "EventCode": "0xA6", - "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AK Ring In Use; Down and Even", - "EventCode": "0xA8", - "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AK Ring In Use; Down and Odd", - "EventCode": "0xA8", - "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AK Ring In Use; Up and Even", - "EventCode": "0xA8", - "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AK Ring In Use; Up and Odd", - "EventCode": "0xA8", - "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical BL Ring in Use; Down and Even", - "EventCode": "0xAA", - "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical BL Ring in Use; Down and Odd", - "EventCode": "0xAA", - "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical BL Ring in Use; Up and Even", - "EventCode": "0xAA", - "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical BL Ring in Use; Up and Odd", - "EventCode": "0xAA", - "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical IV Ring in Use; Down", - "EventCode": "0xAC", - "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical IV Ring in Use; Up", - "EventCode": "0xAC", - "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "WbPushMtoI; Pushed to LLC", - "EventCode": "0x56", - "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when the CHA was received WbPushMtoI; Counts the number of times when the CHA was able to push WbPushMToI to LLC", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "WbPushMtoI; Pushed to Memory", - "EventCode": "0x56", - "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when the CHA was received WbPushMtoI; Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC0_SMI2", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 2 only.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC1_SMI3", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 3 only.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC2_SMI4", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 4 only.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC3_SMI5", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 5 only.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC0_SMI0", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 0 only.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC1_SMI1", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 1 only.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Any RspIFwdFE", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response I to Fwd F/E", - "UMask": "0xe4", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response I to Fwd M", - "UMask": "0xf0", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdFE", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response S to Fwd F/E", - "UMask": "0xe2", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdM", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response S to Fwd M", - "UMask": "0xe8", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Any RspHitFSE", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response any to Hit F/S/E", - "UMask": "0xe1", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdFE", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response I to Fwd F/E", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdM", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response I to Fwd M", - "UMask": "0x50", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdFE", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response S to Fwd F/E", - "UMask": "0x42", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdM", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response S to Fwd M", - "UMask": "0x48", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Core RspHitFSE", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response any to Hit F/S/E", - "UMask": "0x41", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdFE", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response I to Fwd F/E", - "UMask": "0x84", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdM", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response I to Fwd M", - "UMask": "0x90", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdFE", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response S to Fwd F/E", - "UMask": "0x82", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdM", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response S to Fwd M", - "UMask": "0x88", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Evict RspHitFSE", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response any to Hit F/S/E", - "UMask": "0x81", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; External RspIFwdFE", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response I to Fwd F/E", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; External RspIFwdM", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response I to Fwd M", - "UMask": "0x30", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; External RspSFwdFE", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response S to Fwd F/E", - "UMask": "0x22", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; External RspSFwdM", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response S to Fwd M", - "UMask": "0x28", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; External RspHitFSE", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response any to Hit F/S/E", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CLOCKTICKS", - "Deprecated": "1", - "EventName": "UNC_C_CLOCKTICKS", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_FAST_ASSERTED.HORZ", - "Deprecated": "1", - "EventCode": "0xA5", - "EventName": "UNC_C_FAST_ASSERTED", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.ANY", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_C_LLC_LOOKUP.ANY", - "PerPkg": "1", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_C_LLC_LOOKUP.DATA_READ", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOCAL", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_C_LLC_LOOKUP.LOCAL", - "PerPkg": "1", - "UMask": "0x31", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_C_LLC_LOOKUP.REMOTE", - "PerPkg": "1", - "UMask": "0x91", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP", - "PerPkg": "1", - "UMask": "0x9", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITE", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_C_LLC_LOOKUP.WRITE", - "PerPkg": "1", - "UMask": "0x5", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.E_STATE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.F_STATE", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.LOCAL_ALL", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.LOCAL", - "PerPkg": "1", - "UMask": "0x2f", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.M_STATE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.REMOTE", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.S_STATE", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SRC_THRTL", - "Deprecated": "1", - "EventCode": "0xA4", - "EventName": "UNC_C_RING_SRC_THRTL", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.EVICT", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.EVICT", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.HIT", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.HIT", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IPQ", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.IPQ", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.IPQ_HIT", - "PerPkg": "1", - "UMask": "0x18", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.IPQ_MISS", - "PerPkg": "1", - "UMask": "0x28", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.IRQ", - "PerPkg": "1", - "UMask": "0x31", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.IRQ_HIT", - "PerPkg": "1", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.IRQ_MISS", - "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.LOC_ALL", - "PerPkg": "1", - "UMask": "0x37", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.LOC_IA", - "PerPkg": "1", - "UMask": "0x31", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.LOC_IO", - "PerPkg": "1", - "UMask": "0x34", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.MISS", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.MISS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.PRQ", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.PRQ", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_HIT", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.PRQ_HIT", - "PerPkg": "1", - "UMask": "0x14", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_MISS", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.PRQ_MISS", - "PerPkg": "1", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.REM_ALL", - "PerPkg": "1", - "UMask": "0x30", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.RRQ_HIT", - "PerPkg": "1", - "UMask": "0x50", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.RRQ_MISS", - "PerPkg": "1", - "UMask": "0x60", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.WBQ_HIT", - "PerPkg": "1", - "UMask": "0x90", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.WBQ_MISS", - "PerPkg": "1", - "UMask": "0xa0", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.EVICT", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.EVICT", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.HIT", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.HIT", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IPQ", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.IPQ", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_HIT", - "PerPkg": "1", - "UMask": "0x18", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_MISS", - "PerPkg": "1", - "UMask": "0x28", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.IRQ", - "PerPkg": "1", - "UMask": "0x31", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_HIT", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_HIT", - "PerPkg": "1", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_MISS", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_MISS", - "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.LOC_ALL", - "PerPkg": "1", - "UMask": "0x37", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IA", - "PerPkg": "1", - "UMask": "0x31", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IO", - "PerPkg": "1", - "UMask": "0x34", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.MISS", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.MISS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.PRQ", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.PRQ", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_HIT", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_HIT", - "PerPkg": "1", - "UMask": "0x14", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_MISS", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_MISS", - "PerPkg": "1", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0", - "Deprecated": "1", - "EventCode": "0x80", - "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1", - "Deprecated": "1", - "EventCode": "0x80", - "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2", - "Deprecated": "1", - "EventCode": "0x80", - "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3", - "Deprecated": "1", - "EventCode": "0x80", - "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4", - "Deprecated": "1", - "EventCode": "0x80", - "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5", - "Deprecated": "1", - "EventCode": "0x80", - "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0", - "Deprecated": "1", - "EventCode": "0x82", - "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1", - "Deprecated": "1", - "EventCode": "0x82", - "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2", - "Deprecated": "1", - "EventCode": "0x82", - "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3", - "Deprecated": "1", - "EventCode": "0x82", - "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4", - "Deprecated": "1", - "EventCode": "0x82", - "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5", - "Deprecated": "1", - "EventCode": "0x82", - "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0", - "Deprecated": "1", - "EventCode": "0x88", - "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1", - "Deprecated": "1", - "EventCode": "0x88", - "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2", - "Deprecated": "1", - "EventCode": "0x88", - "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3", - "Deprecated": "1", - "EventCode": "0x88", - "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4", - "Deprecated": "1", - "EventCode": "0x88", - "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5", - "Deprecated": "1", - "EventCode": "0x88", - "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0", - "Deprecated": "1", - "EventCode": "0x8A", - "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1", - "Deprecated": "1", - "EventCode": "0x8A", - "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2", - "Deprecated": "1", - "EventCode": "0x8A", - "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3", - "Deprecated": "1", - "EventCode": "0x8A", - "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4", - "Deprecated": "1", - "EventCode": "0x8A", - "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5", - "Deprecated": "1", - "EventCode": "0x8A", - "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0", - "Deprecated": "1", - "EventCode": "0x86", - "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1", - "Deprecated": "1", - "EventCode": "0x86", - "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2", - "Deprecated": "1", - "EventCode": "0x86", - "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3", - "Deprecated": "1", - "EventCode": "0x86", - "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4", - "Deprecated": "1", - "EventCode": "0x86", - "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5", - "Deprecated": "1", - "EventCode": "0x86", - "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0", - "Deprecated": "1", - "EventCode": "0x8E", - "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1", - "Deprecated": "1", - "EventCode": "0x8E", - "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2", - "Deprecated": "1", - "EventCode": "0x8E", - "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3", - "Deprecated": "1", - "EventCode": "0x8E", - "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4", - "Deprecated": "1", - "EventCode": "0x8E", - "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5", - "Deprecated": "1", - "EventCode": "0x8E", - "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0", - "Deprecated": "1", - "EventCode": "0x8C", - "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1", - "Deprecated": "1", - "EventCode": "0x8C", - "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2", - "Deprecated": "1", - "EventCode": "0x8C", - "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3", - "Deprecated": "1", - "EventCode": "0x8C", - "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4", - "Deprecated": "1", - "EventCode": "0x8C", - "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5", - "Deprecated": "1", - "EventCode": "0x8C", - "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", - "Deprecated": "1", - "EventCode": "0x57", - "EventName": "UNC_H_BYPASS_CHA_IMC.INTERMEDIATE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", - "Deprecated": "1", - "EventCode": "0x57", - "EventName": "UNC_H_BYPASS_CHA_IMC.NOT_TAKEN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.TAKEN", - "Deprecated": "1", - "EventCode": "0x57", - "EventName": "UNC_H_BYPASS_CHA_IMC.TAKEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CMS_CLOCKTICKS", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_H_CLOCK", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C1_STATE", - "Deprecated": "1", - "EventCode": "0x17", - "EventName": "UNC_H_CORE_PMA.C1_STATE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C1_TRANSITION", - "Deprecated": "1", - "EventCode": "0x17", - "EventName": "UNC_H_CORE_PMA.C1_TRANSITION", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C6_STATE", - "Deprecated": "1", - "EventCode": "0x17", - "EventName": "UNC_H_CORE_PMA.C6_STATE", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C6_TRANSITION", - "Deprecated": "1", - "EventCode": "0x17", - "EventName": "UNC_H_CORE_PMA.C6_TRANSITION", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.GV", - "Deprecated": "1", - "EventCode": "0x17", - "EventName": "UNC_H_CORE_PMA.GV", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_GTONE", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.ANY_GTONE", - "PerPkg": "1", - "UMask": "0xe2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_ONE", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.ANY_ONE", - "PerPkg": "1", - "UMask": "0xe1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_REMOTE", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.ANY_REMOTE", - "PerPkg": "1", - "UMask": "0xe4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.CORE_GTONE", - "PerPkg": "1", - "UMask": "0x42", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_ONE", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.CORE_ONE", - "PerPkg": "1", - "UMask": "0x41", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_REMOTE", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.CORE_REMOTE", - "PerPkg": "1", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.EVICT_GTONE", - "PerPkg": "1", - "UMask": "0x82", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_ONE", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.EVICT_ONE", - "PerPkg": "1", - "UMask": "0x81", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_REMOTE", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.EVICT_REMOTE", - "PerPkg": "1", - "UMask": "0x84", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_GTONE", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.EXT_GTONE", - "PerPkg": "1", - "UMask": "0x22", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_ONE", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.EXT_ONE", - "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_REMOTE", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.EXT_REMOTE", - "PerPkg": "1", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_COUNTER0_OCCUPANCY", - "Deprecated": "1", - "EventCode": "0x1F", - "EventName": "UNC_H_COUNTER0_OCCUPANCY", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP", - "Deprecated": "1", - "EventCode": "0x53", - "EventName": "UNC_H_DIR_LOOKUP.NO_SNP", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP", - "Deprecated": "1", - "EventCode": "0x53", - "EventName": "UNC_H_DIR_LOOKUP.SNP", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA", - "Deprecated": "1", - "EventCode": "0x54", - "EventName": "UNC_H_DIR_UPDATE.HA", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR", - "Deprecated": "1", - "EventCode": "0x54", - "EventName": "UNC_H_DIR_UPDATE.TOR", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", - "Deprecated": "1", - "EventCode": "0xAE", - "EventName": "UNC_H_EGRESS_ORDERING.IV_SNOOPGO_DN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", - "Deprecated": "1", - "EventCode": "0xAE", - "EventName": "UNC_H_EGRESS_ORDERING.IV_SNOOPGO_UP", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS", - "Deprecated": "1", - "EventCode": "0x5F", - "EventName": "UNC_H_HITME_HIT.EX_RDS", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.SHARED_OWNREQ", - "Deprecated": "1", - "EventCode": "0x5F", - "EventName": "UNC_H_HITME_HIT.SHARED_OWNREQ", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.WBMTOE", - "Deprecated": "1", - "EventCode": "0x5F", - "EventName": "UNC_H_HITME_HIT.WBMTOE", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.WBMTOI_OR_S", - "Deprecated": "1", - "EventCode": "0x5F", - "EventName": "UNC_H_HITME_HIT.WBMTOI_OR_S", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_LOOKUP.READ", - "Deprecated": "1", - "EventCode": "0x5E", - "EventName": "UNC_H_HITME_LOOKUP.READ", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_LOOKUP.WRITE", - "Deprecated": "1", - "EventCode": "0x5E", - "EventName": "UNC_H_HITME_LOOKUP.WRITE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN", - "Deprecated": "1", - "EventCode": "0x60", - "EventName": "UNC_H_HITME_MISS.NOTSHARED_RDINVOWN", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.READ_OR_INV", - "Deprecated": "1", - "EventCode": "0x60", - "EventName": "UNC_H_HITME_MISS.READ_OR_INV", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.SHARED_RDINVOWN", - "Deprecated": "1", - "EventCode": "0x60", - "EventName": "UNC_H_HITME_MISS.SHARED_RDINVOWN", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.DEALLOCATE", - "Deprecated": "1", - "EventCode": "0x61", - "EventName": "UNC_H_HITME_UPDATE.DEALLOCATE", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", - "Deprecated": "1", - "EventCode": "0x61", - "EventName": "UNC_H_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.RDINVOWN", - "Deprecated": "1", - "EventCode": "0x61", - "EventName": "UNC_H_HITME_UPDATE.RDINVOWN", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.RSPFWDI_REM", - "Deprecated": "1", - "EventCode": "0x61", - "EventName": "UNC_H_HITME_UPDATE.RSPFWDI_REM", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.SHARED", - "Deprecated": "1", - "EventCode": "0x61", - "EventName": "UNC_H_HITME_UPDATE.SHARED", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", - "Deprecated": "1", - "EventCode": "0xA7", - "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", - "Deprecated": "1", - "EventCode": "0xA7", - "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_ODD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", - "Deprecated": "1", - "EventCode": "0xA7", - "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", - "Deprecated": "1", - "EventCode": "0xA7", - "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", - "Deprecated": "1", - "EventCode": "0xA9", - "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", - "Deprecated": "1", - "EventCode": "0xA9", - "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_ODD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", - "Deprecated": "1", - "EventCode": "0xA9", - "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", - "Deprecated": "1", - "EventCode": "0xA9", - "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", - "Deprecated": "1", - "EventCode": "0xAB", - "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", - "Deprecated": "1", - "EventCode": "0xAB", - "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_ODD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", - "Deprecated": "1", - "EventCode": "0xAB", - "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", - "Deprecated": "1", - "EventCode": "0xAB", - "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", - "Deprecated": "1", - "EventCode": "0xAD", - "EventName": "UNC_H_HORZ_RING_IV_IN_USE.LEFT", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", - "Deprecated": "1", - "EventCode": "0xAD", - "EventName": "UNC_H_HORZ_RING_IV_IN_USE.RIGHT", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_READS_COUNT.NORMAL", - "Deprecated": "1", - "EventCode": "0x59", - "EventName": "UNC_H_IMC_READS_COUNT.NORMAL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_READS_COUNT.PRIORITY", - "Deprecated": "1", - "EventCode": "0x59", - "EventName": "UNC_H_IMC_READS_COUNT.PRIORITY", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL", - "Deprecated": "1", - "EventCode": "0x5B", - "EventName": "UNC_H_IMC_WRITES_COUNT.FULL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL_MIG", - "Deprecated": "1", - "EventCode": "0x5B", - "EventName": "UNC_H_IMC_WRITES_COUNT.FULL_MIG", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", - "Deprecated": "1", - "EventCode": "0x5B", - "EventName": "UNC_H_IMC_WRITES_COUNT.FULL_PRIORITY", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL", - "Deprecated": "1", - "EventCode": "0x5B", - "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG", - "Deprecated": "1", - "EventCode": "0x5B", - "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL_MIG", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", - "Deprecated": "1", - "EventCode": "0x5B", - "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL_PRIORITY", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.INVITOM", - "Deprecated": "1", - "EventCode": "0x62", - "EventName": "UNC_H_IODC_ALLOC.INVITOM", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.IODCFULL", - "Deprecated": "1", - "EventCode": "0x62", - "EventName": "UNC_H_IODC_ALLOC.IODCFULL", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.OSBGATED", - "Deprecated": "1", - "EventCode": "0x62", - "EventName": "UNC_H_IODC_ALLOC.OSBGATED", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.ALL", - "Deprecated": "1", - "EventCode": "0x63", - "EventName": "UNC_H_IODC_DEALLOC.ALL", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.SNPOUT", - "Deprecated": "1", - "EventCode": "0x63", - "EventName": "UNC_H_IODC_DEALLOC.SNPOUT", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBMTOE", - "Deprecated": "1", - "EventCode": "0x63", - "EventName": "UNC_H_IODC_DEALLOC.WBMTOE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBMTOI", - "Deprecated": "1", - "EventCode": "0x63", - "EventName": "UNC_H_IODC_DEALLOC.WBMTOI", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBPUSHMTOI", - "Deprecated": "1", - "EventCode": "0x63", - "EventName": "UNC_H_IODC_DEALLOC.WBPUSHMTOI", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.CV0_PREF_MISS", - "Deprecated": "1", - "EventCode": "0x39", - "EventName": "UNC_H_MISC.CV0_PREF_MISS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.CV0_PREF_VIC", - "Deprecated": "1", - "EventCode": "0x39", - "EventName": "UNC_H_MISC.CV0_PREF_VIC", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S", - "Deprecated": "1", - "EventCode": "0x39", - "EventName": "UNC_H_MISC.RFO_HIT_S", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RSPI_WAS_FSE", - "Deprecated": "1", - "EventCode": "0x39", - "EventName": "UNC_H_MISC.RSPI_WAS_FSE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.WC_ALIASING", - "Deprecated": "1", - "EventCode": "0x39", - "EventName": "UNC_H_MISC.WC_ALIASING", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_OSB", - "Deprecated": "1", - "EventCode": "0x55", - "EventName": "UNC_H_OSB", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC0_SMI2", - "Deprecated": "1", - "EventCode": "0x58", - "EventName": "UNC_H_READ_NO_CREDITS.EDC0_SMI2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC1_SMI3", - "Deprecated": "1", - "EventCode": "0x58", - "EventName": "UNC_H_READ_NO_CREDITS.EDC1_SMI3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC2_SMI4", - "Deprecated": "1", - "EventCode": "0x58", - "EventName": "UNC_H_READ_NO_CREDITS.EDC2_SMI4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC3_SMI5", - "Deprecated": "1", - "EventCode": "0x58", - "EventName": "UNC_H_READ_NO_CREDITS.EDC3_SMI5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.MC0_SMI0", - "Deprecated": "1", - "EventCode": "0x58", - "EventName": "UNC_H_READ_NO_CREDITS.MC0_SMI0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.MC1_SMI1", - "Deprecated": "1", - "EventCode": "0x58", - "EventName": "UNC_H_READ_NO_CREDITS.MC1_SMI1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "read requests from home agent", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.READS", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "CHA" - }, - { - "BriefDescription": "read requests from local home agent", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.READS_LOCAL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "read requests from remote home agent", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.READS_REMOTE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "write requests from home agent", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.WRITES", - "PerPkg": "1", - "UMask": "0xc", - "Unit": "CHA" - }, - { - "BriefDescription": "write requests from local home agent", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.WRITES_LOCAL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "write requests from remote home agent", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.WRITES_REMOTE", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.AD", - "Deprecated": "1", - "EventCode": "0xA1", - "EventName": "UNC_H_RING_BOUNCES_HORZ.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.AK", - "Deprecated": "1", - "EventCode": "0xA1", - "EventName": "UNC_H_RING_BOUNCES_HORZ.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.BL", - "Deprecated": "1", - "EventCode": "0xA1", - "EventName": "UNC_H_RING_BOUNCES_HORZ.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.IV", - "Deprecated": "1", - "EventCode": "0xA1", - "EventName": "UNC_H_RING_BOUNCES_HORZ.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.AD", - "Deprecated": "1", - "EventCode": "0xA0", - "EventName": "UNC_H_RING_BOUNCES_VERT.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.AK", - "Deprecated": "1", - "EventCode": "0xA0", - "EventName": "UNC_H_RING_BOUNCES_VERT.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.BL", - "Deprecated": "1", - "EventCode": "0xA0", - "EventName": "UNC_H_RING_BOUNCES_VERT.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.IV", - "Deprecated": "1", - "EventCode": "0xA0", - "EventName": "UNC_H_RING_BOUNCES_VERT.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AD", - "Deprecated": "1", - "EventCode": "0xA3", - "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AK", - "Deprecated": "1", - "EventCode": "0xA3", - "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", - "Deprecated": "1", - "EventCode": "0xA3", - "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.BL", - "Deprecated": "1", - "EventCode": "0xA3", - "EventName": "UNC_H_RING_SINK_STARVED_HORZ.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.IV", - "Deprecated": "1", - "EventCode": "0xA3", - "EventName": "UNC_H_RING_SINK_STARVED_HORZ.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.AD", - "Deprecated": "1", - "EventCode": "0xA2", - "EventName": "UNC_H_RING_SINK_STARVED_VERT.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.AK", - "Deprecated": "1", - "EventCode": "0xA2", - "EventName": "UNC_H_RING_SINK_STARVED_VERT.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.BL", - "Deprecated": "1", - "EventCode": "0xA2", - "EventName": "UNC_H_RING_SINK_STARVED_VERT.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.IV", - "Deprecated": "1", - "EventCode": "0xA2", - "EventName": "UNC_H_RING_SINK_STARVED_VERT.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IPQ", - "Deprecated": "1", - "EventCode": "0x13", - "EventName": "UNC_H_RxC_INSERTS.IPQ", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ", - "Deprecated": "1", - "EventCode": "0x13", - "EventName": "UNC_H_RxC_INSERTS.IRQ", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ_REJ", - "Deprecated": "1", - "EventCode": "0x13", - "EventName": "UNC_H_RxC_INSERTS.IRQ_REJ", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.PRQ", - "Deprecated": "1", - "EventCode": "0x13", - "EventName": "UNC_H_RxC_INSERTS.PRQ", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.PRQ_REJ", - "Deprecated": "1", - "EventCode": "0x13", - "EventName": "UNC_H_RxC_INSERTS.PRQ_REJ", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.RRQ", - "Deprecated": "1", - "EventCode": "0x13", - "EventName": "UNC_H_RxC_INSERTS.RRQ", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.WBQ", - "Deprecated": "1", - "EventCode": "0x13", - "EventName": "UNC_H_RxC_INSERTS.WBQ", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0", - "Deprecated": "1", - "EventCode": "0x22", - "EventName": "UNC_H_RxC_IPQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x22", - "EventName": "UNC_H_RxC_IPQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0", - "Deprecated": "1", - "EventCode": "0x22", - "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0", - "Deprecated": "1", - "EventCode": "0x22", - "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x22", - "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0", - "Deprecated": "1", - "EventCode": "0x22", - "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP", - "Deprecated": "1", - "EventCode": "0x23", - "EventName": "UNC_H_RxC_IPQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ANY0", - "Deprecated": "1", - "EventCode": "0x23", - "EventName": "UNC_H_RxC_IPQ1_REJECT.ANY_IPQ0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.HA", - "Deprecated": "1", - "EventCode": "0x23", - "EventName": "UNC_H_RxC_IPQ1_REJECT.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", - "Deprecated": "1", - "EventCode": "0x23", - "EventName": "UNC_H_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM", - "Deprecated": "1", - "EventCode": "0x23", - "EventName": "UNC_H_RxC_IPQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH", - "Deprecated": "1", - "EventCode": "0x23", - "EventName": "UNC_H_RxC_IPQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM", - "Deprecated": "1", - "EventCode": "0x23", - "EventName": "UNC_H_RxC_IPQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.VICTIM", - "Deprecated": "1", - "EventCode": "0x23", - "EventName": "UNC_H_RxC_IPQ1_REJECT.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", - "Deprecated": "1", - "EventCode": "0x18", - "EventName": "UNC_H_RxC_IRQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x18", - "EventName": "UNC_H_RxC_IRQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", - "Deprecated": "1", - "EventCode": "0x18", - "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", - "Deprecated": "1", - "EventCode": "0x18", - "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x18", - "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", - "Deprecated": "1", - "EventCode": "0x18", - "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", - "Deprecated": "1", - "EventCode": "0x19", - "EventName": "UNC_H_RxC_IRQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ANY0", - "Deprecated": "1", - "EventCode": "0x19", - "EventName": "UNC_H_RxC_IRQ1_REJECT.ANY_REJECT_IRQ0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.HA", - "Deprecated": "1", - "EventCode": "0x19", - "EventName": "UNC_H_RxC_IRQ1_REJECT.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", - "Deprecated": "1", - "EventCode": "0x19", - "EventName": "UNC_H_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", - "Deprecated": "1", - "EventCode": "0x19", - "EventName": "UNC_H_RxC_IRQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", - "Deprecated": "1", - "EventCode": "0x19", - "EventName": "UNC_H_RxC_IRQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", - "Deprecated": "1", - "EventCode": "0x19", - "EventName": "UNC_H_RxC_IRQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.VICTIM", - "Deprecated": "1", - "EventCode": "0x19", - "EventName": "UNC_H_RxC_IRQ1_REJECT.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", - "Deprecated": "1", - "EventCode": "0x24", - "EventName": "UNC_H_RxC_ISMQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x24", - "EventName": "UNC_H_RxC_ISMQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", - "Deprecated": "1", - "EventCode": "0x24", - "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", - "Deprecated": "1", - "EventCode": "0x24", - "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x24", - "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", - "Deprecated": "1", - "EventCode": "0x24", - "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", - "Deprecated": "1", - "EventCode": "0x2C", - "EventName": "UNC_H_RxC_ISMQ0_RETRY.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x2C", - "EventName": "UNC_H_RxC_ISMQ0_RETRY.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", - "Deprecated": "1", - "EventCode": "0x2C", - "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", - "Deprecated": "1", - "EventCode": "0x2C", - "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x2C", - "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", - "Deprecated": "1", - "EventCode": "0x2C", - "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.ANY0", - "Deprecated": "1", - "EventCode": "0x25", - "EventName": "UNC_H_RxC_ISMQ1_REJECT.ANY_ISMQ0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.HA", - "Deprecated": "1", - "EventCode": "0x25", - "EventName": "UNC_H_RxC_ISMQ1_REJECT.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.ANY0", - "Deprecated": "1", - "EventCode": "0x2D", - "EventName": "UNC_H_RxC_ISMQ1_RETRY.ANY", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.HA", - "Deprecated": "1", - "EventCode": "0x2D", - "EventName": "UNC_H_RxC_ISMQ1_RETRY.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IPQ", - "Deprecated": "1", - "EventCode": "0x11", - "EventName": "UNC_H_RxC_OCCUPANCY.IPQ", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ", - "Deprecated": "1", - "EventCode": "0x11", - "EventName": "UNC_H_RxC_OCCUPANCY.IRQ", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.RRQ", - "Deprecated": "1", - "EventCode": "0x11", - "EventName": "UNC_H_RxC_OCCUPANCY.RRQ", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.WBQ", - "Deprecated": "1", - "EventCode": "0x11", - "EventName": "UNC_H_RxC_OCCUPANCY.WBQ", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", - "Deprecated": "1", - "EventCode": "0x2E", - "EventName": "UNC_H_RxC_OTHER0_RETRY.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x2E", - "EventName": "UNC_H_RxC_OTHER0_RETRY.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", - "Deprecated": "1", - "EventCode": "0x2E", - "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", - "Deprecated": "1", - "EventCode": "0x2E", - "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x2E", - "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", - "Deprecated": "1", - "EventCode": "0x2E", - "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", - "Deprecated": "1", - "EventCode": "0x2F", - "EventName": "UNC_H_RxC_OTHER1_RETRY.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ANY0", - "Deprecated": "1", - "EventCode": "0x2F", - "EventName": "UNC_H_RxC_OTHER1_RETRY.ANY", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.HA", - "Deprecated": "1", - "EventCode": "0x2F", - "EventName": "UNC_H_RxC_OTHER1_RETRY.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", - "Deprecated": "1", - "EventCode": "0x2F", - "EventName": "UNC_H_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", - "Deprecated": "1", - "EventCode": "0x2F", - "EventName": "UNC_H_RxC_OTHER1_RETRY.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", - "Deprecated": "1", - "EventCode": "0x2F", - "EventName": "UNC_H_RxC_OTHER1_RETRY.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", - "Deprecated": "1", - "EventCode": "0x2F", - "EventName": "UNC_H_RxC_OTHER1_RETRY.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.VICTIM", - "Deprecated": "1", - "EventCode": "0x2F", - "EventName": "UNC_H_RxC_OTHER1_RETRY.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", - "Deprecated": "1", - "EventCode": "0x20", - "EventName": "UNC_H_RxC_PRQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x20", - "EventName": "UNC_H_RxC_PRQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", - "Deprecated": "1", - "EventCode": "0x20", - "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", - "Deprecated": "1", - "EventCode": "0x20", - "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x20", - "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", - "Deprecated": "1", - "EventCode": "0x20", - "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", - "Deprecated": "1", - "EventCode": "0x21", - "EventName": "UNC_H_RxC_PRQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ANY0", - "Deprecated": "1", - "EventCode": "0x21", - "EventName": "UNC_H_RxC_PRQ1_REJECT.ANY_PRQ0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.HA", - "Deprecated": "1", - "EventCode": "0x21", - "EventName": "UNC_H_RxC_PRQ1_REJECT.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", - "Deprecated": "1", - "EventCode": "0x21", - "EventName": "UNC_H_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", - "Deprecated": "1", - "EventCode": "0x21", - "EventName": "UNC_H_RxC_PRQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", - "Deprecated": "1", - "EventCode": "0x21", - "EventName": "UNC_H_RxC_PRQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", - "Deprecated": "1", - "EventCode": "0x21", - "EventName": "UNC_H_RxC_PRQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.VICTIM", - "Deprecated": "1", - "EventCode": "0x21", - "EventName": "UNC_H_RxC_PRQ1_REJECT.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", - "Deprecated": "1", - "EventCode": "0x2A", - "EventName": "UNC_H_RxC_REQ_Q0_RETRY.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x2A", - "EventName": "UNC_H_RxC_REQ_Q0_RETRY.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", - "Deprecated": "1", - "EventCode": "0x2A", - "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", - "Deprecated": "1", - "EventCode": "0x2A", - "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x2A", - "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", - "Deprecated": "1", - "EventCode": "0x2A", - "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", - "Deprecated": "1", - "EventCode": "0x2B", - "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", - "Deprecated": "1", - "EventCode": "0x2B", - "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ANY", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.HA", - "Deprecated": "1", - "EventCode": "0x2B", - "EventName": "UNC_H_RxC_REQ_Q1_RETRY.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", - "Deprecated": "1", - "EventCode": "0x2B", - "EventName": "UNC_H_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", - "Deprecated": "1", - "EventCode": "0x2B", - "EventName": "UNC_H_RxC_REQ_Q1_RETRY.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", - "Deprecated": "1", - "EventCode": "0x2B", - "EventName": "UNC_H_RxC_REQ_Q1_RETRY.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", - "Deprecated": "1", - "EventCode": "0x2B", - "EventName": "UNC_H_RxC_REQ_Q1_RETRY.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", - "Deprecated": "1", - "EventCode": "0x2B", - "EventName": "UNC_H_RxC_REQ_Q1_RETRY.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0", - "Deprecated": "1", - "EventCode": "0x26", - "EventName": "UNC_H_RxC_RRQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x26", - "EventName": "UNC_H_RxC_RRQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0", - "Deprecated": "1", - "EventCode": "0x26", - "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0", - "Deprecated": "1", - "EventCode": "0x26", - "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x26", - "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0", - "Deprecated": "1", - "EventCode": "0x26", - "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP", - "Deprecated": "1", - "EventCode": "0x27", - "EventName": "UNC_H_RxC_RRQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ANY0", - "Deprecated": "1", - "EventCode": "0x27", - "EventName": "UNC_H_RxC_RRQ1_REJECT.ANY_RRQ0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.HA", - "Deprecated": "1", - "EventCode": "0x27", - "EventName": "UNC_H_RxC_RRQ1_REJECT.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", - "Deprecated": "1", - "EventCode": "0x27", - "EventName": "UNC_H_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM", - "Deprecated": "1", - "EventCode": "0x27", - "EventName": "UNC_H_RxC_RRQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH", - "Deprecated": "1", - "EventCode": "0x27", - "EventName": "UNC_H_RxC_RRQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM", - "Deprecated": "1", - "EventCode": "0x27", - "EventName": "UNC_H_RxC_RRQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.VICTIM", - "Deprecated": "1", - "EventCode": "0x27", - "EventName": "UNC_H_RxC_RRQ1_REJECT.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0", - "Deprecated": "1", - "EventCode": "0x28", - "EventName": "UNC_H_RxC_WBQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x28", - "EventName": "UNC_H_RxC_WBQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0", - "Deprecated": "1", - "EventCode": "0x28", - "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0", - "Deprecated": "1", - "EventCode": "0x28", - "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x28", - "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0", - "Deprecated": "1", - "EventCode": "0x28", - "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP", - "Deprecated": "1", - "EventCode": "0x29", - "EventName": "UNC_H_RxC_WBQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ANY0", - "Deprecated": "1", - "EventCode": "0x29", - "EventName": "UNC_H_RxC_WBQ1_REJECT.ANY_WBQ0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.HA", - "Deprecated": "1", - "EventCode": "0x29", - "EventName": "UNC_H_RxC_WBQ1_REJECT.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", - "Deprecated": "1", - "EventCode": "0x29", - "EventName": "UNC_H_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM", - "Deprecated": "1", - "EventCode": "0x29", - "EventName": "UNC_H_RxC_WBQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH", - "Deprecated": "1", - "EventCode": "0x29", - "EventName": "UNC_H_RxC_WBQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM", - "Deprecated": "1", - "EventCode": "0x29", - "EventName": "UNC_H_RxC_WBQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.VICTIM", - "Deprecated": "1", - "EventCode": "0x29", - "EventName": "UNC_H_RxC_WBQ1_REJECT.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.AD_BNC", - "Deprecated": "1", - "EventCode": "0xB4", - "EventName": "UNC_H_RxR_BUSY_STARVED.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.AD_CRD", - "Deprecated": "1", - "EventCode": "0xB4", - "EventName": "UNC_H_RxR_BUSY_STARVED.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.BL_BNC", - "Deprecated": "1", - "EventCode": "0xB4", - "EventName": "UNC_H_RxR_BUSY_STARVED.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.BL_CRD", - "Deprecated": "1", - "EventCode": "0xB4", - "EventName": "UNC_H_RxR_BUSY_STARVED.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AD_BNC", - "Deprecated": "1", - "EventCode": "0xB2", - "EventName": "UNC_H_RxR_BYPASS.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AD_CRD", - "Deprecated": "1", - "EventCode": "0xB2", - "EventName": "UNC_H_RxR_BYPASS.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AK_BNC", - "Deprecated": "1", - "EventCode": "0xB2", - "EventName": "UNC_H_RxR_BYPASS.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.BL_BNC", - "Deprecated": "1", - "EventCode": "0xB2", - "EventName": "UNC_H_RxR_BYPASS.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.BL_CRD", - "Deprecated": "1", - "EventCode": "0xB2", - "EventName": "UNC_H_RxR_BYPASS.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.IV_BNC", - "Deprecated": "1", - "EventCode": "0xB2", - "EventName": "UNC_H_RxR_BYPASS.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AD_BNC", - "Deprecated": "1", - "EventCode": "0xB3", - "EventName": "UNC_H_RxR_CRD_STARVED.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AD_CRD", - "Deprecated": "1", - "EventCode": "0xB3", - "EventName": "UNC_H_RxR_CRD_STARVED.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AK_BNC", - "Deprecated": "1", - "EventCode": "0xB3", - "EventName": "UNC_H_RxR_CRD_STARVED.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.BL_BNC", - "Deprecated": "1", - "EventCode": "0xB3", - "EventName": "UNC_H_RxR_CRD_STARVED.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.BL_CRD", - "Deprecated": "1", - "EventCode": "0xB3", - "EventName": "UNC_H_RxR_CRD_STARVED.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.IFV", - "Deprecated": "1", - "EventCode": "0xB3", - "EventName": "UNC_H_RxR_CRD_STARVED.IFV", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.IV_BNC", - "Deprecated": "1", - "EventCode": "0xB3", - "EventName": "UNC_H_RxR_CRD_STARVED.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AD_BNC", - "Deprecated": "1", - "EventCode": "0xB1", - "EventName": "UNC_H_RxR_INSERTS.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AD_CRD", - "Deprecated": "1", - "EventCode": "0xB1", - "EventName": "UNC_H_RxR_INSERTS.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AK_BNC", - "Deprecated": "1", - "EventCode": "0xB1", - "EventName": "UNC_H_RxR_INSERTS.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.BL_BNC", - "Deprecated": "1", - "EventCode": "0xB1", - "EventName": "UNC_H_RxR_INSERTS.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.BL_CRD", - "Deprecated": "1", - "EventCode": "0xB1", - "EventName": "UNC_H_RxR_INSERTS.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.IV_BNC", - "Deprecated": "1", - "EventCode": "0xB1", - "EventName": "UNC_H_RxR_INSERTS.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AD_BNC", - "Deprecated": "1", - "EventCode": "0xB0", - "EventName": "UNC_H_RxR_OCCUPANCY.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AD_CRD", - "Deprecated": "1", - "EventCode": "0xB0", - "EventName": "UNC_H_RxR_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AK_BNC", - "Deprecated": "1", - "EventCode": "0xB0", - "EventName": "UNC_H_RxR_OCCUPANCY.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.BL_BNC", - "Deprecated": "1", - "EventCode": "0xB0", - "EventName": "UNC_H_RxR_OCCUPANCY.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.BL_CRD", - "Deprecated": "1", - "EventCode": "0xB0", - "EventName": "UNC_H_RxR_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.IV_BNC", - "Deprecated": "1", - "EventCode": "0xB0", - "EventName": "UNC_H_RxR_OCCUPANCY.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.E_STATE", - "Deprecated": "1", - "EventCode": "0x3D", - "EventName": "UNC_H_SF_EVICTION.E_STATE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.M_STATE", - "Deprecated": "1", - "EventCode": "0x3D", - "EventName": "UNC_H_SF_EVICTION.M_STATE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.S_STATE", - "Deprecated": "1", - "EventCode": "0x3D", - "EventName": "UNC_H_SF_EVICTION.S_STATE", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.ALL", - "Deprecated": "1", - "EventCode": "0x51", - "EventName": "UNC_H_SNOOPS_SENT.", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_LOCAL", - "Deprecated": "1", - "EventCode": "0x51", - "EventName": "UNC_H_SNOOPS_SENT.BCST_LOC", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_REMOTE", - "Deprecated": "1", - "EventCode": "0x51", - "EventName": "UNC_H_SNOOPS_SENT.BCST_REM", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", - "Deprecated": "1", - "EventCode": "0x51", - "EventName": "UNC_H_SNOOPS_SENT.DIRECT_LOC", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", - "Deprecated": "1", - "EventCode": "0x51", - "EventName": "UNC_H_SNOOPS_SENT.DIRECT_REM", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.LOCAL", - "Deprecated": "1", - "EventCode": "0x51", - "EventName": "UNC_H_SNOOPS_SENT.LOCAL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.REMOTE", - "Deprecated": "1", - "EventCode": "0x51", - "EventName": "UNC_H_SNOOPS_SENT.REMOTE", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPCNFLCTS", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPFWD", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSPFWD", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPI", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSPI", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSPIFWD", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPS", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSPS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_WBWB", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSP_WB", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", - "Deprecated": "1", - "EventCode": "0x5D", - "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPCNFLCT", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", - "Deprecated": "1", - "EventCode": "0x5D", - "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPFWD", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPI", - "Deprecated": "1", - "EventCode": "0x5D", - "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPI", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", - "Deprecated": "1", - "EventCode": "0x5D", - "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPIFWD", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPS", - "Deprecated": "1", - "EventCode": "0x5D", - "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", - "Deprecated": "1", - "EventCode": "0x5D", - "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPSFWD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB", - "Deprecated": "1", - "EventCode": "0x5D", - "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_FWD_WB", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB", - "Deprecated": "1", - "EventCode": "0x5D", - "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_WB", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", - "Deprecated": "1", - "EventCode": "0xD0", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", - "Deprecated": "1", - "EventCode": "0xD0", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", - "Deprecated": "1", - "EventCode": "0xD0", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", - "Deprecated": "1", - "EventCode": "0xD0", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", - "Deprecated": "1", - "EventCode": "0xD0", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", - "Deprecated": "1", - "EventCode": "0xD0", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", - "Deprecated": "1", - "EventCode": "0xD2", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", - "Deprecated": "1", - "EventCode": "0xD2", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", - "Deprecated": "1", - "EventCode": "0xD2", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", - "Deprecated": "1", - "EventCode": "0xD2", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", - "Deprecated": "1", - "EventCode": "0xD2", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", - "Deprecated": "1", - "EventCode": "0xD2", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", - "Deprecated": "1", - "EventCode": "0xD4", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", - "Deprecated": "1", - "EventCode": "0xD4", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", - "Deprecated": "1", - "EventCode": "0xD4", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", - "Deprecated": "1", - "EventCode": "0xD4", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", - "Deprecated": "1", - "EventCode": "0xD4", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", - "Deprecated": "1", - "EventCode": "0xD4", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", - "Deprecated": "1", - "EventCode": "0xD6", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", - "Deprecated": "1", - "EventCode": "0xD6", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", - "Deprecated": "1", - "EventCode": "0xD6", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", - "Deprecated": "1", - "EventCode": "0xD6", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", - "Deprecated": "1", - "EventCode": "0xD6", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", - "Deprecated": "1", - "EventCode": "0xD6", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC", - "Deprecated": "1", - "EventCode": "0x9D", - "EventName": "UNC_H_TxR_HORZ_ADS_USED.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", - "Deprecated": "1", - "EventCode": "0x9D", - "EventName": "UNC_H_TxR_HORZ_ADS_USED.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC", - "Deprecated": "1", - "EventCode": "0x9D", - "EventName": "UNC_H_TxR_HORZ_ADS_USED.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC", - "Deprecated": "1", - "EventCode": "0x9D", - "EventName": "UNC_H_TxR_HORZ_ADS_USED.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", - "Deprecated": "1", - "EventCode": "0x9D", - "EventName": "UNC_H_TxR_HORZ_ADS_USED.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AD_BNC", - "Deprecated": "1", - "EventCode": "0x9F", - "EventName": "UNC_H_TxR_HORZ_BYPASS.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", - "Deprecated": "1", - "EventCode": "0x9F", - "EventName": "UNC_H_TxR_HORZ_BYPASS.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AK_BNC", - "Deprecated": "1", - "EventCode": "0x9F", - "EventName": "UNC_H_TxR_HORZ_BYPASS.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.BL_BNC", - "Deprecated": "1", - "EventCode": "0x9F", - "EventName": "UNC_H_TxR_HORZ_BYPASS.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", - "Deprecated": "1", - "EventCode": "0x9F", - "EventName": "UNC_H_TxR_HORZ_BYPASS.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.IV_BNC", - "Deprecated": "1", - "EventCode": "0x9F", - "EventName": "UNC_H_TxR_HORZ_BYPASS.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC", - "Deprecated": "1", - "EventCode": "0x96", - "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", - "Deprecated": "1", - "EventCode": "0x96", - "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC", - "Deprecated": "1", - "EventCode": "0x96", - "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC", - "Deprecated": "1", - "EventCode": "0x96", - "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", - "Deprecated": "1", - "EventCode": "0x96", - "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC", - "Deprecated": "1", - "EventCode": "0x96", - "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC", - "Deprecated": "1", - "EventCode": "0x97", - "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", - "Deprecated": "1", - "EventCode": "0x97", - "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC", - "Deprecated": "1", - "EventCode": "0x97", - "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC", - "Deprecated": "1", - "EventCode": "0x97", - "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", - "Deprecated": "1", - "EventCode": "0x97", - "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC", - "Deprecated": "1", - "EventCode": "0x97", - "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AD_BNC", - "Deprecated": "1", - "EventCode": "0x95", - "EventName": "UNC_H_TxR_HORZ_INSERTS.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", - "Deprecated": "1", - "EventCode": "0x95", - "EventName": "UNC_H_TxR_HORZ_INSERTS.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AK_BNC", - "Deprecated": "1", - "EventCode": "0x95", - "EventName": "UNC_H_TxR_HORZ_INSERTS.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.BL_BNC", - "Deprecated": "1", - "EventCode": "0x95", - "EventName": "UNC_H_TxR_HORZ_INSERTS.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", - "Deprecated": "1", - "EventCode": "0x95", - "EventName": "UNC_H_TxR_HORZ_INSERTS.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.IV_BNC", - "Deprecated": "1", - "EventCode": "0x95", - "EventName": "UNC_H_TxR_HORZ_INSERTS.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AD_BNC", - "Deprecated": "1", - "EventCode": "0x99", - "EventName": "UNC_H_TxR_HORZ_NACK.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AD_CRD", - "Deprecated": "1", - "EventCode": "0x99", - "EventName": "UNC_H_TxR_HORZ_NACK.AD_CRD", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AK_BNC", - "Deprecated": "1", - "EventCode": "0x99", - "EventName": "UNC_H_TxR_HORZ_NACK.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.BL_BNC", - "Deprecated": "1", - "EventCode": "0x99", - "EventName": "UNC_H_TxR_HORZ_NACK.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.BL_CRD", - "Deprecated": "1", - "EventCode": "0x99", - "EventName": "UNC_H_TxR_HORZ_NACK.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.IV_BNC", - "Deprecated": "1", - "EventCode": "0x99", - "EventName": "UNC_H_TxR_HORZ_NACK.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC", - "Deprecated": "1", - "EventCode": "0x94", - "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", - "Deprecated": "1", - "EventCode": "0x94", - "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC", - "Deprecated": "1", - "EventCode": "0x94", - "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC", - "Deprecated": "1", - "EventCode": "0x94", - "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", - "Deprecated": "1", - "EventCode": "0x94", - "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC", - "Deprecated": "1", - "EventCode": "0x94", - "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.AD_BNC", - "Deprecated": "1", - "EventCode": "0x9B", - "EventName": "UNC_H_TxR_HORZ_STARVED.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.AK_BNC", - "Deprecated": "1", - "EventCode": "0x9B", - "EventName": "UNC_H_TxR_HORZ_STARVED.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.BL_BNC", - "Deprecated": "1", - "EventCode": "0x9B", - "EventName": "UNC_H_TxR_HORZ_STARVED.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.IV_BNC", - "Deprecated": "1", - "EventCode": "0x9B", - "EventName": "UNC_H_TxR_HORZ_STARVED.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", - "Deprecated": "1", - "EventCode": "0x9C", - "EventName": "UNC_H_TxR_VERT_ADS_USED.AD_AG0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", - "Deprecated": "1", - "EventCode": "0x9C", - "EventName": "UNC_H_TxR_VERT_ADS_USED.AD_AG1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AK_AG0", - "Deprecated": "1", - "EventCode": "0x9C", - "EventName": "UNC_H_TxR_VERT_ADS_USED.AK_AG0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AK_AG1", - "Deprecated": "1", - "EventCode": "0x9C", - "EventName": "UNC_H_TxR_VERT_ADS_USED.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", - "Deprecated": "1", - "EventCode": "0x9C", - "EventName": "UNC_H_TxR_VERT_ADS_USED.BL_AG0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", - "Deprecated": "1", - "EventCode": "0x9C", - "EventName": "UNC_H_TxR_VERT_ADS_USED.BL_AG1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AD_AG0", - "Deprecated": "1", - "EventCode": "0x9E", - "EventName": "UNC_H_TxR_VERT_BYPASS.AD_AG0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AD_AG1", - "Deprecated": "1", - "EventCode": "0x9E", - "EventName": "UNC_H_TxR_VERT_BYPASS.AD_AG1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AK_AG0", - "Deprecated": "1", - "EventCode": "0x9E", - "EventName": "UNC_H_TxR_VERT_BYPASS.AK_AG0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AK_AG1", - "Deprecated": "1", - "EventCode": "0x9E", - "EventName": "UNC_H_TxR_VERT_BYPASS.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.BL_AG0", - "Deprecated": "1", - "EventCode": "0x9E", - "EventName": "UNC_H_TxR_VERT_BYPASS.BL_AG0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.BL_AG1", - "Deprecated": "1", - "EventCode": "0x9E", - "EventName": "UNC_H_TxR_VERT_BYPASS.BL_AG1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.IV", - "Deprecated": "1", - "EventCode": "0x9E", - "EventName": "UNC_H_TxR_VERT_BYPASS.IV_AG1", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0", - "Deprecated": "1", - "EventCode": "0x92", - "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AD_AG0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1", - "Deprecated": "1", - "EventCode": "0x92", - "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AD_AG1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0", - "Deprecated": "1", - "EventCode": "0x92", - "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AK_AG0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1", - "Deprecated": "1", - "EventCode": "0x92", - "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0", - "Deprecated": "1", - "EventCode": "0x92", - "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.BL_AG0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1", - "Deprecated": "1", - "EventCode": "0x92", - "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.BL_AG1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.IV", - "Deprecated": "1", - "EventCode": "0x92", - "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.IV_AG0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0", - "Deprecated": "1", - "EventCode": "0x93", - "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AD_AG0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1", - "Deprecated": "1", - "EventCode": "0x93", - "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AD_AG1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0", - "Deprecated": "1", - "EventCode": "0x93", - "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AK_AG0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1", - "Deprecated": "1", - "EventCode": "0x93", - "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0", - "Deprecated": "1", - "EventCode": "0x93", - "EventName": "UNC_H_TxR_VERT_CYCLES_NE.BL_AG0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1", - "Deprecated": "1", - "EventCode": "0x93", - "EventName": "UNC_H_TxR_VERT_CYCLES_NE.BL_AG1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.IV", - "Deprecated": "1", - "EventCode": "0x93", - "EventName": "UNC_H_TxR_VERT_CYCLES_NE.IV_AG0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AD_AG0", - "Deprecated": "1", - "EventCode": "0x91", - "EventName": "UNC_H_TxR_VERT_INSERTS.AD_AG0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AD_AG1", - "Deprecated": "1", - "EventCode": "0x91", - "EventName": "UNC_H_TxR_VERT_INSERTS.AD_AG1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AK_AG0", - "Deprecated": "1", - "EventCode": "0x91", - "EventName": "UNC_H_TxR_VERT_INSERTS.AK_AG0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AK_AG1", - "Deprecated": "1", - "EventCode": "0x91", - "EventName": "UNC_H_TxR_VERT_INSERTS.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.BL_AG0", - "Deprecated": "1", - "EventCode": "0x91", - "EventName": "UNC_H_TxR_VERT_INSERTS.BL_AG0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.BL_AG1", - "Deprecated": "1", - "EventCode": "0x91", - "EventName": "UNC_H_TxR_VERT_INSERTS.BL_AG1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.IV", - "Deprecated": "1", - "EventCode": "0x91", - "EventName": "UNC_H_TxR_VERT_INSERTS.IV_AG0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AD_AG0", - "Deprecated": "1", - "EventCode": "0x98", - "EventName": "UNC_H_TxR_VERT_NACK.AD_AG0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AD_AG1", - "Deprecated": "1", - "EventCode": "0x98", - "EventName": "UNC_H_TxR_VERT_NACK.AD_AG1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AK_AG0", - "Deprecated": "1", - "EventCode": "0x98", - "EventName": "UNC_H_TxR_VERT_NACK.AK_AG0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AK_AG1", - "Deprecated": "1", - "EventCode": "0x98", - "EventName": "UNC_H_TxR_VERT_NACK.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.BL_AG0", - "Deprecated": "1", - "EventCode": "0x98", - "EventName": "UNC_H_TxR_VERT_NACK.BL_AG0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.BL_AG1", - "Deprecated": "1", - "EventCode": "0x98", - "EventName": "UNC_H_TxR_VERT_NACK.BL_AG1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.IV", - "Deprecated": "1", - "EventCode": "0x98", - "EventName": "UNC_H_TxR_VERT_NACK.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0", - "Deprecated": "1", - "EventCode": "0x90", - "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AD_AG0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1", - "Deprecated": "1", - "EventCode": "0x90", - "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AD_AG1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0", - "Deprecated": "1", - "EventCode": "0x90", - "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AK_AG0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1", - "Deprecated": "1", - "EventCode": "0x90", - "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0", - "Deprecated": "1", - "EventCode": "0x90", - "EventName": "UNC_H_TxR_VERT_OCCUPANCY.BL_AG0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1", - "Deprecated": "1", - "EventCode": "0x90", - "EventName": "UNC_H_TxR_VERT_OCCUPANCY.BL_AG1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.IV", - "Deprecated": "1", - "EventCode": "0x90", - "EventName": "UNC_H_TxR_VERT_OCCUPANCY.IV_AG0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AD_AG0", - "Deprecated": "1", - "EventCode": "0x9A", - "EventName": "UNC_H_TxR_VERT_STARVED.AD_AG0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AD_AG1", - "Deprecated": "1", - "EventCode": "0x9A", - "EventName": "UNC_H_TxR_VERT_STARVED.AD_AG1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AK_AG0", - "Deprecated": "1", - "EventCode": "0x9A", - "EventName": "UNC_H_TxR_VERT_STARVED.AK_AG0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AK_AG1", - "Deprecated": "1", - "EventCode": "0x9A", - "EventName": "UNC_H_TxR_VERT_STARVED.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.BL_AG0", - "Deprecated": "1", - "EventCode": "0x9A", - "EventName": "UNC_H_TxR_VERT_STARVED.BL_AG0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.BL_AG1", - "Deprecated": "1", - "EventCode": "0x9A", - "EventName": "UNC_H_TxR_VERT_STARVED.BL_AG1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.IV", - "Deprecated": "1", - "EventCode": "0x9A", - "EventName": "UNC_H_TxR_VERT_STARVED.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", - "Deprecated": "1", - "EventCode": "0xA6", - "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_EVEN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", - "Deprecated": "1", - "EventCode": "0xA6", - "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_ODD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", - "Deprecated": "1", - "EventCode": "0xA6", - "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_EVEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", - "Deprecated": "1", - "EventCode": "0xA6", - "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_ODD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", - "Deprecated": "1", - "EventCode": "0xA8", - "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_EVEN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", - "Deprecated": "1", - "EventCode": "0xA8", - "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_ODD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", - "Deprecated": "1", - "EventCode": "0xA8", - "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_EVEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", - "Deprecated": "1", - "EventCode": "0xA8", - "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_ODD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", - "Deprecated": "1", - "EventCode": "0xAA", - "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_EVEN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", - "Deprecated": "1", - "EventCode": "0xAA", - "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_ODD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", - "Deprecated": "1", - "EventCode": "0xAA", - "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_EVEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", - "Deprecated": "1", - "EventCode": "0xAA", - "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_ODD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_IV_IN_USE.DN", - "Deprecated": "1", - "EventCode": "0xAC", - "EventName": "UNC_H_VERT_RING_IV_IN_USE.DN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_IV_IN_USE.UP", - "Deprecated": "1", - "EventCode": "0xAC", - "EventName": "UNC_H_VERT_RING_IV_IN_USE.UP", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WB_PUSH_MTOI.LLC", - "Deprecated": "1", - "EventCode": "0x56", - "EventName": "UNC_H_WB_PUSH_MTOI.LLC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WB_PUSH_MTOI.MEM", - "Deprecated": "1", - "EventCode": "0x56", - "EventName": "UNC_H_WB_PUSH_MTOI.MEM", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2", - "Deprecated": "1", - "EventCode": "0x5A", - "EventName": "UNC_H_WRITE_NO_CREDITS.EDC0_SMI2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3", - "Deprecated": "1", - "EventCode": "0x5A", - "EventName": "UNC_H_WRITE_NO_CREDITS.EDC1_SMI3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4", - "Deprecated": "1", - "EventCode": "0x5A", - "EventName": "UNC_H_WRITE_NO_CREDITS.EDC2_SMI4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5", - "Deprecated": "1", - "EventCode": "0x5A", - "EventName": "UNC_H_WRITE_NO_CREDITS.EDC3_SMI5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0", - "Deprecated": "1", - "EventCode": "0x5A", - "EventName": "UNC_H_WRITE_NO_CREDITS.MC0_SMI0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1", - "Deprecated": "1", - "EventCode": "0x5A", - "EventName": "UNC_H_WRITE_NO_CREDITS.MC1_SMI1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.ANY_RSPI_FWDFE", - "PerPkg": "1", - "UMask": "0xe4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.ANY_RSPI_FWDM", - "PerPkg": "1", - "UMask": "0xf0", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.ANY_RSPS_FWDFE", - "PerPkg": "1", - "UMask": "0xe2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.ANY_RSPS_FWDM", - "PerPkg": "1", - "UMask": "0xe8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.ANY_RSP_HITFSE", - "PerPkg": "1", - "UMask": "0xe1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.CORE_RSPI_FWDFE", - "PerPkg": "1", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.CORE_RSPI_FWDM", - "PerPkg": "1", - "UMask": "0x50", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.CORE_RSPS_FWDFE", - "PerPkg": "1", - "UMask": "0x42", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.CORE_RSPS_FWDM", - "PerPkg": "1", - "UMask": "0x48", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.CORE_RSP_HITFSE", - "PerPkg": "1", - "UMask": "0x41", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.EVICT_RSPI_FWDFE", - "PerPkg": "1", - "UMask": "0x84", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.EVICT_RSPI_FWDM", - "PerPkg": "1", - "UMask": "0x90", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.EVICT_RSPS_FWDFE", - "PerPkg": "1", - "UMask": "0x82", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.EVICT_RSPS_FWDM", - "PerPkg": "1", - "UMask": "0x88", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.EVICT_RSP_HITFSE", - "PerPkg": "1", - "UMask": "0x81", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.EXT_RSPI_FWDFE", - "PerPkg": "1", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.EXT_RSPI_FWDM", - "PerPkg": "1", - "UMask": "0x30", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.EXT_RSPS_FWDFE", - "PerPkg": "1", - "UMask": "0x22", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.EXT_RSPS_FWDM", - "PerPkg": "1", - "UMask": "0x28", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.EXT_RSP_HITFSE", - "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "Clockticks of the IIO Traffic Controller", - "EventCode": "0x1", - "EventName": "UNC_IIO_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Counts clockticks of the 1GHz traffic controller clock in the IIO unit.", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", - "FCMask": "0x4", - "PerPkg": "1", - "PortMask": "0x0f", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", - "FCMask": "0x4", - "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", - "FCMask": "0x4", - "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", - "FCMask": "0x4", - "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", - "FCMask": "0x4", - "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts; Port 0", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts; Port 1", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts; Port 2", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts; Port 3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", - "FCMask": "0x04", - "PerPkg": "1", - "UMask": "0xf", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", - "FCMask": "0x04", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", - "FCMask": "0x04", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", - "FCMask": "0x04", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", - "FCMask": "0x04", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part2", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of 4 bytes made to IIO Part0 by the CPU", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of 4 bytes made to IIO Part1 by the CPU", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of 4 bytes made to IIO Part2 by the CPU", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of 4 bytes made to IIO Part3 by the CPU", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 0", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 2", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 3", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Card reading from DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Card reading from DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 0", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 2", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 3", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Card writing to DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Card writing to DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Num Link Correctable Errors", - "EventCode": "0xF", - "EventName": "UNC_IIO_LINK_NUM_CORR_ERR", - "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "Num Link Retries", - "EventCode": "0xE", - "EventName": "UNC_IIO_LINK_NUM_RETRIES", - "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number packets that passed the Mask/Match Filter", - "EventCode": "0x21", - "EventName": "UNC_IIO_MASK_MATCH", - "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus", - "EventCode": "0x2", - "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0", - "PerPkg": "1", - "PublicDescription": "Asserted if all bits specified by mask match", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and PCIE bus", - "EventCode": "0x2", - "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1", - "PerPkg": "1", - "PublicDescription": "Asserted if all bits specified by mask match", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and !(PCIE bus)", - "EventCode": "0x2", - "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1", - "PerPkg": "1", - "PublicDescription": "Asserted if all bits specified by mask match", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "AND Mask/match for debug bus; PCIE bus", - "EventCode": "0x2", - "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1", - "PerPkg": "1", - "PublicDescription": "Asserted if all bits specified by mask match", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "AND Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus", - "EventCode": "0x2", - "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1", - "PerPkg": "1", - "PublicDescription": "Asserted if all bits specified by mask match", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "AND Mask/match for debug bus", - "EventCode": "0x2", - "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1", - "PerPkg": "1", - "PublicDescription": "Asserted if all bits specified by mask match", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus", - "EventCode": "0x3", - "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0", - "PerPkg": "1", - "PublicDescription": "Asserted if any bits specified by mask match", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and PCIE bus", - "EventCode": "0x3", - "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1", - "PerPkg": "1", - "PublicDescription": "Asserted if any bits specified by mask match", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and !(PCIE bus)", - "EventCode": "0x3", - "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1", - "PerPkg": "1", - "PublicDescription": "Asserted if any bits specified by mask match", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "OR Mask/match for debug bus; PCIE bus", - "EventCode": "0x3", - "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1", - "PerPkg": "1", - "PublicDescription": "Asserted if any bits specified by mask match", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus", - "EventCode": "0x3", - "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1", - "PerPkg": "1", - "PublicDescription": "Asserted if any bits specified by mask match", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) and !(PCIE bus)", - "EventCode": "0x3", - "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1", - "PerPkg": "1", - "PublicDescription": "Asserted if any bits specified by mask match", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Counting disabled", - "EventName": "UNC_IIO_NOTHING", - "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Symbol Times on Link", - "EventCode": "0x82", - "EventName": "UNC_IIO_SYMBOL_TIMES", - "PerPkg": "1", - "PublicDescription": "Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MSG.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MSG.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MSG.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MSG.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MSG.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MSG.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part0", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part2", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part0 to Memory", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part1 to Memory", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part1 to the MMIO space of an IIO target.In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Access; context cache miss", - "EventCode": "0x41", - "EventName": "UNC_IIO_VTD_ACCESS.CTXT_MISS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Access; L1 miss", - "EventCode": "0x41", - "EventName": "UNC_IIO_VTD_ACCESS.L1_MISS", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Access; L2 miss", - "EventCode": "0x41", - "EventName": "UNC_IIO_VTD_ACCESS.L2_MISS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Access; L3 miss", - "EventCode": "0x41", - "EventName": "UNC_IIO_VTD_ACCESS.L3_MISS", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Access; Vtd hit", - "EventCode": "0x41", - "EventName": "UNC_IIO_VTD_ACCESS.L4_PAGE_HIT", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Access; TLB miss", - "EventCode": "0x41", - "EventName": "UNC_IIO_VTD_ACCESS.TLB1_MISS", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Access; TLB is full", - "EventCode": "0x41", - "EventName": "UNC_IIO_VTD_ACCESS.TLB_FULL", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Access; TLB miss", - "EventCode": "0x41", - "EventName": "UNC_IIO_VTD_ACCESS.TLB_MISS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Occupancy", - "EventCode": "0x40", - "EventName": "UNC_IIO_VTD_OCCUPANCY", - "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "Total Write Cache Occupancy; Any Source", - "EventCode": "0xF", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Total Write Cache Occupancy; Snoops", - "EventCode": "0xF", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Total IRP occupancy of inbound read and write requests.", - "EventCode": "0xF", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", - "PerPkg": "1", - "PublicDescription": "Total IRP occupancy of inbound read and write requests. This is effectively the sum of read occupancy and write occupancy.", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "IRP Clocks", - "EventCode": "0x1", - "EventName": "UNC_I_CLOCKTICKS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; CLFlush", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x80", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; CRd", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.CRD", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; DRd", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.DRD", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; PCIDCAHin5t", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; PCIRdCur", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.PCITOM", - "PerPkg": "1", - "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.RFO", - "PerPkg": "1", - "PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; WbMtoI", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.WBMTOI", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "FAF RF full", - "EventCode": "0x17", - "EventName": "UNC_I_FAF_FULL", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.", - "EventCode": "0x18", - "EventName": "UNC_I_FAF_INSERTS", - "PerPkg": "1", - "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.", - "Unit": "IRP" - }, - { - "BriefDescription": "Occupancy of the IRP FAF queue.", - "EventCode": "0x19", - "EventName": "UNC_I_FAF_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.", - "Unit": "IRP" - }, - { - "BriefDescription": "FAF allocation -- sent to ADQ", - "EventCode": "0x16", - "EventName": "UNC_I_FAF_TRANSACTIONS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "All Inserts Inbound (p2p + faf + cset)", - "EventCode": "0x1E", - "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "All Inserts Outbound (BL, AK, Snoops)", - "EventCode": "0x1E", - "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary", - "EventCode": "0x1C", - "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary", - "EventCode": "0x1C", - "EventName": "UNC_I_MISC0.2ND_RD_INSERT", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary", - "EventCode": "0x1C", - "EventName": "UNC_I_MISC0.2ND_WR_INSERT", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Fastpath Rejects", - "EventCode": "0x1C", - "EventName": "UNC_I_MISC0.FAST_REJ", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Fastpath Requests", - "EventCode": "0x1C", - "EventName": "UNC_I_MISC0.FAST_REQ", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary", - "EventCode": "0x1C", - "EventName": "UNC_I_MISC0.FAST_XFER", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary", - "EventCode": "0x1C", - "EventName": "UNC_I_MISC0.PF_ACK_HINT", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0", - "EventCode": "0x1C", - "EventName": "UNC_I_MISC0.UNKNOWN", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Lost Forward", - "EventCode": "0x1D", - "EventName": "UNC_I_MISC1.LOST_FWD", - "PerPkg": "1", - "PublicDescription": "Snoop pulled away ownership before a write was committed", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Received Invalid", - "EventCode": "0x1D", - "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", - "PerPkg": "1", - "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Received Valid", - "EventCode": "0x1D", - "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", - "PerPkg": "1", - "PublicDescription": "Secondary received a transfer that did have sufficient MESI state", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line", - "EventCode": "0x1D", - "EventName": "UNC_I_MISC1.SLOW_E", - "PerPkg": "1", - "PublicDescription": "Secondary received a transfer that did have sufficient MESI state", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line", - "EventCode": "0x1D", - "EventName": "UNC_I_MISC1.SLOW_I", - "PerPkg": "1", - "PublicDescription": "Snoop took cacheline ownership before write from data was committed.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line", - "EventCode": "0x1D", - "EventName": "UNC_I_MISC1.SLOW_M", - "PerPkg": "1", - "PublicDescription": "Snoop took cacheline ownership before write from data was committed.", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line", - "EventCode": "0x1D", - "EventName": "UNC_I_MISC1.SLOW_S", - "PerPkg": "1", - "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Requests", - "EventCode": "0x14", - "EventName": "UNC_I_P2P_INSERTS", - "PerPkg": "1", - "PublicDescription": "P2P requests from the ITC", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Occupancy", - "EventCode": "0x15", - "EventName": "UNC_I_P2P_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "P2P B & S Queue Occupancy", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions; P2P completions", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions; match if local only", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.LOC", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions; match if local and target matches", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions; P2P Message", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.MSG", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions; P2P reads", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.RD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions; Match if remote only", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.REM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions; match if remote and target matches", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions; P2P Writes", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.WR", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT", - "PerPkg": "1", - "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO", - "UMask": "0x7e", - "Unit": "IRP" - }, - { - "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES", - "PerPkg": "1", - "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache", - "UMask": "0x74", - "Unit": "IRP" - }, - { - "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I", - "PerPkg": "1", - "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache", - "UMask": "0x72", - "Unit": "IRP" - }, - { - "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", - "PerPkg": "1", - "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache", - "UMask": "0x78", - "Unit": "IRP" - }, - { - "BriefDescription": "Responses to snoops of any type that miss the IIO cache", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_MISS", - "PerPkg": "1", - "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that miss the IIO cache", - "UMask": "0x71", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; Hit E or S", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.HIT_ES", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; Hit I", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.HIT_I", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; Hit M", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.HIT_M", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; Miss", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.MISS", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; SnpCode", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.SNPCODE", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; SnpData", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.SNPDATA", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; SnpInv", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.SNPINV", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Atomic", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.ATOMIC", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Other", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.OTHER", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions.", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Read Prefetches", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.RD_PREF", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Reads", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.READS", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Writes", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.WRITES", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound write (fast path) requests received by the IRP.", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.WR_PREF", - "PerPkg": "1", - "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "AK Egress Allocations", - "EventCode": "0xB", - "EventName": "UNC_I_TxC_AK_INSERTS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL DRS Egress Cycles Full", - "EventCode": "0x5", - "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL DRS Egress Inserts", - "EventCode": "0x2", - "EventName": "UNC_I_TxC_BL_DRS_INSERTS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL DRS Egress Occupancy", - "EventCode": "0x8", - "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL NCB Egress Cycles Full", - "EventCode": "0x6", - "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL NCB Egress Inserts", - "EventCode": "0x3", - "EventName": "UNC_I_TxC_BL_NCB_INSERTS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL NCB Egress Occupancy", - "EventCode": "0x9", - "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL NCS Egress Cycles Full", - "EventCode": "0x7", - "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL NCS Egress Inserts", - "EventCode": "0x4", - "EventName": "UNC_I_TxC_BL_NCS_INSERTS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL NCS Egress Occupancy", - "EventCode": "0xA", - "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "No AD Egress Credit Stalls", - "EventCode": "0x1A", - "EventName": "UNC_I_TxR2_AD_STALL_CREDIT_CYCLES", - "PerPkg": "1", - "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.", - "Unit": "IRP" - }, - { - "BriefDescription": "No BL Egress Credit Stalls", - "EventCode": "0x1B", - "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", - "PerPkg": "1", - "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Read Requests", - "EventCode": "0xD", - "EventName": "UNC_I_TxS_DATA_INSERTS_NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Read Requests", - "EventCode": "0xE", - "EventName": "UNC_I_TxS_DATA_INSERTS_NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Request Queue Occupancy", - "EventCode": "0xC", - "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.", - "Unit": "IRP" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Traffic in which the M2M to iMC Bypass was not taken", - "EventCode": "0x22", - "EventName": "UNC_M2M_BYPASS_M2M_Egress.NOT_TAKEN", - "PerPkg": "1", - "PublicDescription": "Counts traffic in which the M2M (Mesh to Memory) to iMC (Memory Controller) bypass was not taken", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC Bypass; Taken", - "EventCode": "0x22", - "EventName": "UNC_M2M_BYPASS_M2M_Egress.TAKEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC Bypass; Not Taken", - "EventCode": "0x21", - "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC Bypass; Taken", - "EventCode": "0x21", - "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles - at UCLK", - "EventName": "UNC_M2M_CLOCKTICKS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Clockticks", - "EventCode": "0xC0", - "EventName": "UNC_M2M_CMS_CLOCKTICKS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled", - "EventCode": "0x24", - "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", - "PerPkg": "1", - "PublicDescription": "Counts cycles when direct to core mode (which bypasses the CHA) was disabled", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages sent direct to core (bypassing the CHA)", - "EventCode": "0x23", - "EventName": "UNC_M2M_DIRECT2CORE_TAKEN", - "PerPkg": "1", - "PublicDescription": "Counts when messages were sent direct to core (bypassing the CHA)", - "Unit": "M2M" - }, - { - "BriefDescription": "Number of reads in which direct to core transaction were overridden", - "EventCode": "0x25", - "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", - "PerPkg": "1", - "PublicDescription": "Counts reads in which direct to core transactions (which would have bypassed the CHA) were overridden", - "Unit": "M2M" - }, - { - "BriefDescription": "Number of reads in which direct to Intel(R) UPI transactions were overridden", - "EventCode": "0x28", - "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS", - "PerPkg": "1", - "PublicDescription": "Counts reads in which direct to Intel(R) Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overridden", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles when direct to Intel(R) UPI was disabled", - "EventCode": "0x27", - "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE", - "PerPkg": "1", - "PublicDescription": "Counts cycles when the ability to send messages direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA) was disabled", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages sent direct to the Intel(R) UPI", - "EventCode": "0x26", - "EventName": "UNC_M2M_DIRECT2UPI_TAKEN", - "PerPkg": "1", - "PublicDescription": "Counts when messages were sent direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA)", - "Unit": "M2M" - }, - { - "BriefDescription": "Number of reads that a message sent direct2 Intel(R) UPI was overridden", - "EventCode": "0x29", - "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE", - "PerPkg": "1", - "PublicDescription": "Counts when a read message that was sent direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA) was overridden", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Hit; On NonDirty Line in A State", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Hit; On NonDirty Line in I State", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Hit; On NonDirty Line in L State", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Hit; On NonDirty Line in S State", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Hit; On Dirty Line in A State", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Hit; On Dirty Line in I State", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Hit; On Dirty Line in L State", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Hit; On Dirty Line in S State", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in Any State (A, I, S or unused)", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in the A (SnoopAll) state, indicating the cacheline is stored in another socket in any state, and we must snoop the other sockets to make sure we get the latest data. The data may be stored in any state in the local socket.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the I (Invalid) state indicating the cacheline is not stored in another socket, and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the S (Shared) state indicating the cacheline is either stored in another socket in the S(hared) state , and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Miss; On NonDirty Line in A State", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Miss; On NonDirty Line in I State", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Miss; On NonDirty Line in L State", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Miss; On NonDirty Line in S State", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Miss; On Dirty Line in A State", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Miss; On Dirty Line in I State", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Miss; On Dirty Line in L State", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Miss; On Dirty Line in S State", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory update from A to I", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from A (SnoopAll) to I (Invalid)", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory update from A to S", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from A (SnoopAll) to S (Shared)", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory update from/to Any state", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory to a new state", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory update from I to A", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from I (Invalid) to A (SnoopAll)", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory update from I to S", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from I (Invalid) to S (Shared)", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory update from S to A", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from S (Shared) to A (SnoopAll)", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory update from S to I", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from S (Shared) to I (Invalid)", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements; Down", - "EventCode": "0xAE", - "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN", - "PerPkg": "1", - "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements; Up", - "EventCode": "0xAE", - "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP", - "PerPkg": "1", - "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "FaST wire asserted; Horizontal", - "EventCode": "0xA5", - "EventName": "UNC_M2M_FAST_ASSERTED.HORZ", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "FaST wire asserted; Vertical", - "EventCode": "0xA5", - "EventName": "UNC_M2M_FAST_ASSERTED.VERT", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AD Ring In Use; Left and Even", - "EventCode": "0xA7", - "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", - "EventCode": "0xA7", - "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AD Ring In Use; Right and Even", - "EventCode": "0xA7", - "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", - "EventCode": "0xA7", - "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AK Ring In Use; Left and Even", - "EventCode": "0xA9", - "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", - "EventCode": "0xA9", - "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AK Ring In Use; Right and Even", - "EventCode": "0xA9", - "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", - "EventCode": "0xA9", - "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal BL Ring in Use; Left and Even", - "EventCode": "0xAB", - "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", - "EventCode": "0xAB", - "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal BL Ring in Use; Right and Even", - "EventCode": "0xAB", - "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", - "EventCode": "0xAB", - "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal IV Ring in Use; Left", - "EventCode": "0xAD", - "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal IV Ring in Use; Right", - "EventCode": "0xAD", - "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Reads to iMC issued", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.ALL", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller).", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC; All, regardless of priority.", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.FROM_TRANSGRESS", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC; Critical Priority", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.ISOCH", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Reads to iMC issued at Normal Priority (Non-Isochronous)", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.NORMAL", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller). It only counts normal priority non-isochronous reads.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Read requests to Intel(R) Optane(TM) DC persistent memory issued to the iMC from M2M", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.TO_PMM", - "PerPkg": "1", - "PublicDescription": "M2M Reads Issued to iMC; All, regardless of priority.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Writes to iMC issued", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.ALL", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) issues writes to the iMC (Memory Controller).", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority.", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.FROM_TRANSGRESS", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC; Full Line Non-ISOCH", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.FULL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC; ISOCH Full Line", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority.", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.NI", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Partial Non-Isochronous writes to the iMC", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) issues partial writes to the iMC (Memory Controller). It only counts normal priority non-isochronous writes.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC; ISOCH Partial", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Write requests to Intel(R) Optane(TM) DC persistent memory issued to the iMC from M2M", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.TO_PMM", - "PerPkg": "1", - "PublicDescription": "M2M Writes Issued to iMC; All, regardless of priority.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Number Packet Header Matches; MC Match", - "EventCode": "0x4C", - "EventName": "UNC_M2M_PKT_MATCH.MC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Number Packet Header Matches; Mesh Match", - "EventCode": "0x4C", - "EventName": "UNC_M2M_PKT_MATCH.MESH", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - Regular; Channel 0", - "EventCode": "0x4F", - "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - Regular; Channel 1", - "EventCode": "0x4F", - "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - Regular; Channel 2", - "EventCode": "0x4F", - "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0", - "EventCode": "0x51", - "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1", - "EventCode": "0x51", - "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2", - "EventCode": "0x51", - "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Cycles Full", - "EventCode": "0x53", - "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Cycles Not Empty", - "EventCode": "0x54", - "EventName": "UNC_M2M_PREFCAM_CYCLES_NE", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch requests that got turn into a demand request", - "EventCode": "0x56", - "EventName": "UNC_M2M_PREFCAM_DEMAND_PROMOTIONS", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) promotes a outstanding request in the prefetch queue due to a subsequent demand read request that entered the M2M with the same address. Explanatory Side Note: The Prefetch queue is made of CAM (Content Addressable Memory)", - "Unit": "M2M" - }, - { - "BriefDescription": "Inserts into the Memory Controller Prefetch Queue", - "EventCode": "0x57", - "EventName": "UNC_M2M_PREFCAM_INSERTS", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) receives a prefetch request and inserts it into its outstanding prefetch queue. Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Occupancy", - "EventCode": "0x55", - "EventName": "UNC_M2M_PREFCAM_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD", - "EventCode": "0xA1", - "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK", - "EventCode": "0xA1", - "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL", - "EventCode": "0xA1", - "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV", - "EventCode": "0xA1", - "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.; AD", - "EventCode": "0xA0", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core", - "EventCode": "0xA0", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core", - "EventCode": "0xA0", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.", - "EventCode": "0xA0", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; AD", - "EventCode": "0xA3", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; AK", - "EventCode": "0xA3", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1", - "EventCode": "0xA3", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; BL", - "EventCode": "0xA3", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; IV", - "EventCode": "0xA3", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring; AD", - "EventCode": "0xA2", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core", - "EventCode": "0xA2", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core", - "EventCode": "0xA2", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.", - "EventCode": "0xA2", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Source Throttle", - "EventCode": "0xA4", - "EventName": "UNC_M2M_RING_SRC_THRTL", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0", - "Deprecated": "1", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1", - "Deprecated": "1", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2", - "Deprecated": "1", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 0", - "EventCode": "0x43", - "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 1", - "EventCode": "0x43", - "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 2", - "EventCode": "0x43", - "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 0", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 1", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 2", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Ingress (from CMS) Full", - "EventCode": "0x4", - "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Ingress (from CMS) Not Empty", - "EventCode": "0x3", - "EventName": "UNC_M2M_RxC_AD_CYCLES_NE", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Ingress (from CMS) Queue Inserts", - "EventCode": "0x1", - "EventName": "UNC_M2M_RxC_AD_INSERTS", - "PerPkg": "1", - "PublicDescription": "Counts when the a new entry is Received(RxC) and then added to the AD (Address Ring) Ingress Queue from the CMS (Common Mesh Stop). This is generally used for reads, and", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Ingress (from CMS) Occupancy", - "EventCode": "0x2", - "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Ingress (from CMS) Full", - "EventCode": "0x8", - "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Ingress (from CMS) Not Empty", - "EventCode": "0x7", - "EventName": "UNC_M2M_RxC_BL_CYCLES_NE", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Ingress (from CMS) Allocations", - "EventCode": "0x5", - "EventName": "UNC_M2M_RxC_BL_INSERTS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Ingress (from CMS) Occupancy", - "EventCode": "0x6", - "EventName": "UNC_M2M_RxC_BL_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation; AD - Bounce", - "EventCode": "0xB4", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation; AD - Credit", - "EventCode": "0xB4", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation; BL - Bounce", - "EventCode": "0xB4", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation; BL - Credit", - "EventCode": "0xB4", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", - "EventCode": "0xB2", - "EventName": "UNC_M2M_RxR_BYPASS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass; AD - Credit", - "EventCode": "0xB2", - "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", - "EventCode": "0xB2", - "EventName": "UNC_M2M_RxR_BYPASS.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", - "EventCode": "0xB2", - "EventName": "UNC_M2M_RxR_BYPASS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass; BL - Credit", - "EventCode": "0xB2", - "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", - "EventCode": "0xB2", - "EventName": "UNC_M2M_RxR_BYPASS.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation; AD - Bounce", - "EventCode": "0xB3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation; AD - Credit", - "EventCode": "0xB3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation; AK - Bounce", - "EventCode": "0xB3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation; BL - Bounce", - "EventCode": "0xB3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation; BL - Credit", - "EventCode": "0xB3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation; IFV - Credit", - "EventCode": "0xB3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation; IV - Bounce", - "EventCode": "0xB3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", - "EventCode": "0xB1", - "EventName": "UNC_M2M_RxR_INSERTS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations; AD - Credit", - "EventCode": "0xB1", - "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", - "EventCode": "0xB1", - "EventName": "UNC_M2M_RxR_INSERTS.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", - "EventCode": "0xB1", - "EventName": "UNC_M2M_RxR_INSERTS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations; BL - Credit", - "EventCode": "0xB1", - "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", - "EventCode": "0xB1", - "EventName": "UNC_M2M_RxR_INSERTS.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", - "EventCode": "0xB0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", - "EventCode": "0xB0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", - "EventCode": "0xB0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", - "EventCode": "0xB0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", - "EventCode": "0xB0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", - "EventCode": "0xB0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Clean line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode and regular reads to DRAM in 1LM", - "EventCode": "0x2C", - "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN", - "PerPkg": "1", - "PublicDescription": "Tag Hit; Read Hit from NearMem, Clean Line", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Dirty line read hits(Regular and RFO) to Near Memory(DRAM cache) in Memory Mode", - "EventCode": "0x2C", - "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY", - "PerPkg": "1", - "PublicDescription": "Tag Hit; Read Hit from NearMem, Dirty Line", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Clean line underfill read hits to Near Memory(DRAM cache) in Memory Mode", - "EventCode": "0x2C", - "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN", - "PerPkg": "1", - "PublicDescription": "Tag Hit; Underfill Rd Hit from NearMem, Clean Line", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Dirty line underfill read hits to Near Memory(DRAM cache) in Memory Mode", - "EventCode": "0x2C", - "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY", - "PerPkg": "1", - "PublicDescription": "Tag Hit; Underfill Rd Hit from NearMem, Dirty Line", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Number AD Ingress Credits", - "EventCode": "0x41", - "EventName": "UNC_M2M_TGR_AD_CREDITS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Number BL Ingress Credits", - "EventCode": "0x42", - "EventName": "UNC_M2M_TGR_BL_CREDITS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Cycles Full; Channel 0", - "EventCode": "0x45", - "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Cycles Full; Channel 1", - "EventCode": "0x45", - "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Cycles Full; Channel 2", - "EventCode": "0x45", - "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Cycles Not Empty; Channel 0", - "EventCode": "0x46", - "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Cycles Not Empty; Channel 1", - "EventCode": "0x46", - "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Cycles Not Empty; Channel 2", - "EventCode": "0x46", - "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Inserts; Channel 0", - "EventCode": "0x49", - "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Inserts; Channel 1", - "EventCode": "0x49", - "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Inserts; Channel 2", - "EventCode": "0x49", - "EventName": "UNC_M2M_TRACKER_INSERTS.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Occupancy; Channel 0", - "EventCode": "0x47", - "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Occupancy; Channel 1", - "EventCode": "0x47", - "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Occupancy; Channel 2", - "EventCode": "0x47", - "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Pending Occupancy", - "EventCode": "0x48", - "EventName": "UNC_M2M_TRACKER_PENDING_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Egress (to CMS) Credit Acquired", - "EventCode": "0xD", - "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Egress (to CMS) Credits Occupancy", - "EventCode": "0xE", - "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Egress (to CMS) Full", - "EventCode": "0xC", - "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Egress (to CMS) Not Empty", - "EventCode": "0xB", - "EventName": "UNC_M2M_TxC_AD_CYCLES_NE", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Egress (to CMS) Allocations", - "EventCode": "0x9", - "EventName": "UNC_M2M_TxC_AD_INSERTS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles with No AD Egress (to CMS) Credits", - "EventCode": "0xF", - "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits", - "EventCode": "0x10", - "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Egress (to CMS) Occupancy", - "EventCode": "0xA", - "EventName": "UNC_M2M_TxC_AD_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Outbound Ring Transactions on AK; CRD Transactions to Cbo", - "EventCode": "0x39", - "EventName": "UNC_M2M_TxC_AK.CRD_CBO", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Outbound Ring Transactions on AK; NDR Transactions", - "EventCode": "0x39", - "EventName": "UNC_M2M_TxC_AK.NDR", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side", - "EventCode": "0x1D", - "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side", - "EventCode": "0x1D", - "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side", - "EventCode": "0x1E", - "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side", - "EventCode": "0x1E", - "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full; All", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Near Side", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Far Side", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1", - "PerPkg": "1", - "UMask": "0x88", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1", - "PerPkg": "1", - "UMask": "0xa0", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1", - "PerPkg": "1", - "UMask": "0x90", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Not Empty; All", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Near Side", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Far Side", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Not Empty; Read Credit Request", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Not Empty; Write Compare Request", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Not Empty; Write Credit Request", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations; All", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Near Side", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Far Side", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations; Prefetch Read Cam Hit", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations; Read Credit Request", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations; Write Compare Request", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations; Write Credit Request", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side", - "EventCode": "0x1F", - "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side", - "EventCode": "0x1F", - "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side", - "EventCode": "0x20", - "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side", - "EventCode": "0x20", - "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Occupancy; All", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Near Side", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Far Side", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Occupancy; Read Credit Request", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Occupancy; Write Compare Request", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Occupancy; Write Credit Request", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Sideband", - "EventCode": "0x6B", - "EventName": "UNC_M2M_TxC_AK_SIDEBAND.RD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Sideband", - "EventCode": "0x6B", - "EventName": "UNC_M2M_TxC_AK_SIDEBAND.WR", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache", - "EventCode": "0x40", - "EventName": "UNC_M2M_TxC_BL.DRS_CACHE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core", - "EventCode": "0x40", - "EventName": "UNC_M2M_TxC_BL.DRS_CORE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI", - "EventCode": "0x40", - "EventName": "UNC_M2M_TxC_BL.DRS_UPI", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side", - "EventCode": "0x19", - "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side", - "EventCode": "0x19", - "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side", - "EventCode": "0x1A", - "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side", - "EventCode": "0x1A", - "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Full; All", - "EventCode": "0x18", - "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Near Side", - "EventCode": "0x18", - "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Far Side", - "EventCode": "0x18", - "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Not Empty; All", - "EventCode": "0x17", - "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Near Side", - "EventCode": "0x17", - "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Far Side", - "EventCode": "0x17", - "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Allocations; All", - "EventCode": "0x15", - "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Near Side", - "EventCode": "0x15", - "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Far Side", - "EventCode": "0x15", - "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side", - "EventCode": "0x1B", - "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side", - "EventCode": "0x1B", - "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side", - "EventCode": "0x1C", - "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side", - "EventCode": "0x1C", - "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Occupancy; All", - "EventCode": "0x16", - "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Near Side", - "EventCode": "0x16", - "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Far Side", - "EventCode": "0x16", - "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", - "EventCode": "0x9F", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", - "EventCode": "0x9F", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", - "EventCode": "0x9F", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", - "EventCode": "0x9F", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", - "EventCode": "0x9F", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", - "EventCode": "0x9F", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce", - "EventCode": "0x97", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit", - "EventCode": "0x97", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce", - "EventCode": "0x97", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce", - "EventCode": "0x97", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit", - "EventCode": "0x97", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce", - "EventCode": "0x97", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", - "EventCode": "0x95", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", - "EventCode": "0x95", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", - "EventCode": "0x95", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", - "EventCode": "0x95", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", - "EventCode": "0x95", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", - "EventCode": "0x95", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", - "EventCode": "0x99", - "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", - "EventCode": "0x99", - "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", - "EventCode": "0x99", - "EventName": "UNC_M2M_TxR_HORZ_NACK.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", - "EventCode": "0x99", - "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", - "EventCode": "0x99", - "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", - "EventCode": "0x99", - "EventName": "UNC_M2M_TxR_HORZ_NACK.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce", - "EventCode": "0x9B", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce", - "EventCode": "0x9B", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce", - "EventCode": "0x9B", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce", - "EventCode": "0x9B", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; IV", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.IV", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.IV", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; IV", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_INSERTS.IV", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; IV", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK.IV", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; IV", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.IV", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED.IV", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AD Ring In Use; Down and Even", - "EventCode": "0xA6", - "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AD Ring In Use; Down and Odd", - "EventCode": "0xA6", - "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AD Ring In Use; Up and Even", - "EventCode": "0xA6", - "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AD Ring In Use; Up and Odd", - "EventCode": "0xA6", - "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AK Ring In Use; Down and Even", - "EventCode": "0xA8", - "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AK Ring In Use; Down and Odd", - "EventCode": "0xA8", - "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AK Ring In Use; Up and Even", - "EventCode": "0xA8", - "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AK Ring In Use; Up and Odd", - "EventCode": "0xA8", - "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical BL Ring in Use; Down and Even", - "EventCode": "0xAA", - "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical BL Ring in Use; Down and Odd", - "EventCode": "0xAA", - "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical BL Ring in Use; Up and Even", - "EventCode": "0xAA", - "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical BL Ring in Use; Up and Odd", - "EventCode": "0xAA", - "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical IV Ring in Use; Down", - "EventCode": "0xAC", - "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical IV Ring in Use; Up", - "EventCode": "0xAC", - "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0", - "Deprecated": "1", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1", - "Deprecated": "1", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2", - "Deprecated": "1", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 0", - "EventCode": "0x4E", - "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 1", - "EventCode": "0x4E", - "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 2", - "EventCode": "0x4E", - "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Full; Channel 0", - "EventCode": "0x4A", - "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Full; Channel 1", - "EventCode": "0x4A", - "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Full; Channel 2", - "EventCode": "0x4A", - "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Not Empty; Channel 0", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Not Empty; Channel 1", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Not Empty; Channel 2", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Inserts; Channel 0", - "EventCode": "0x61", - "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Inserts; Channel 1", - "EventCode": "0x61", - "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Inserts; Channel 2", - "EventCode": "0x61", - "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Occupancy; Channel 0", - "EventCode": "0x60", - "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Occupancy; Channel 1", - "EventCode": "0x60", - "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Occupancy; Channel 2", - "EventCode": "0x60", - "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CBox AD Credits Empty; Requests", - "EventCode": "0x22", - "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CBox AD Credits Empty; Snoops", - "EventCode": "0x22", - "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CBox AD Credits Empty; VNA Messages", - "EventCode": "0x22", - "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CBox AD Credits Empty; Writebacks", - "EventCode": "0x22", - "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Number of uclks in domain", - "EventCode": "0x1", - "EventName": "UNC_M3UPI_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Clockticks", - "EventCode": "0xC0", - "EventName": "UNC_M3UPI_CMS_CLOCKTICKS", - "PerPkg": "1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "D2C Sent", - "EventCode": "0x2B", - "EventName": "UNC_M3UPI_D2C_SENT", - "PerPkg": "1", - "PublicDescription": "Count cases BL sends direct to core", - "Unit": "M3UPI" - }, - { - "BriefDescription": "D2U Sent", - "EventCode": "0x2A", - "EventName": "UNC_M3UPI_D2U_SENT", - "PerPkg": "1", - "PublicDescription": "Cases where SMI3 sends D2U command", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements; Down", - "EventCode": "0xAE", - "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN", - "PerPkg": "1", - "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements; Up", - "EventCode": "0xAE", - "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP", - "PerPkg": "1", - "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "FaST wire asserted; Horizontal", - "EventCode": "0xA5", - "EventName": "UNC_M3UPI_FAST_ASSERTED.HORZ", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "FaST wire asserted; Vertical", - "EventCode": "0xA5", - "EventName": "UNC_M3UPI_FAST_ASSERTED.VERT", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AD Ring In Use; Left and Even", - "EventCode": "0xA7", - "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", - "EventCode": "0xA7", - "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AD Ring In Use; Right and Even", - "EventCode": "0xA7", - "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", - "EventCode": "0xA7", - "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AK Ring In Use; Left and Even", - "EventCode": "0xA9", - "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", - "EventCode": "0xA9", - "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AK Ring In Use; Right and Even", - "EventCode": "0xA9", - "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", - "EventCode": "0xA9", - "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal BL Ring in Use; Left and Even", - "EventCode": "0xAB", - "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", - "EventCode": "0xAB", - "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal BL Ring in Use; Right and Even", - "EventCode": "0xAB", - "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", - "EventCode": "0xAB", - "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal IV Ring in Use; Left", - "EventCode": "0xAD", - "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal IV Ring in Use; Right", - "EventCode": "0xAD", - "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "M2 BL Credits Empty; IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO0_IIO1_NCB", - "PerPkg": "1", - "PublicDescription": "No vn0 and vna credits available to send to M2", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "M2 BL Credits Empty; IIO2", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB", - "PerPkg": "1", - "PublicDescription": "No vn0 and vna credits available to send to M2", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "M2 BL Credits Empty; IIO3", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB", - "PerPkg": "1", - "PublicDescription": "No vn0 and vna credits available to send to M2", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "M2 BL Credits Empty; IIO4", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB", - "PerPkg": "1", - "PublicDescription": "No vn0 and vna credits available to send to M2", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "M2 BL Credits Empty; IIO5", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB", - "PerPkg": "1", - "PublicDescription": "No vn0 and vna credits available to send to M2", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "M2 BL Credits Empty; All IIO targets for NCS are in single mask. ORs them together", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS", - "PerPkg": "1", - "PublicDescription": "No vn0 and vna credits available to send to M2", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "M2 BL Credits Empty; Selected M2p BL NCS credits", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL", - "PerPkg": "1", - "PublicDescription": "No vn0 and vna credits available to send to M2", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Multi Slot Flit Received; AD - Slot 0", - "EventCode": "0x3E", - "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0", - "PerPkg": "1", - "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Multi Slot Flit Received; AD - Slot 1", - "EventCode": "0x3E", - "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1", - "PerPkg": "1", - "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Multi Slot Flit Received; AD - Slot 2", - "EventCode": "0x3E", - "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2", - "PerPkg": "1", - "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Multi Slot Flit Received; AK - Slot 0", - "EventCode": "0x3E", - "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0", - "PerPkg": "1", - "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Multi Slot Flit Received; AK - Slot 2", - "EventCode": "0x3E", - "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2", - "PerPkg": "1", - "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Multi Slot Flit Received; BL - Slot 0", - "EventCode": "0x3E", - "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0", - "PerPkg": "1", - "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD", - "EventCode": "0xA1", - "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK", - "EventCode": "0xA1", - "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL", - "EventCode": "0xA1", - "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV", - "EventCode": "0xA1", - "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.; AD", - "EventCode": "0xA0", - "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core", - "EventCode": "0xA0", - "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core", - "EventCode": "0xA0", - "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.", - "EventCode": "0xA0", - "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; AD", - "EventCode": "0xA3", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; AK", - "EventCode": "0xA3", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1", - "EventCode": "0xA3", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; BL", - "EventCode": "0xA3", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; IV", - "EventCode": "0xA3", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring; AD", - "EventCode": "0xA2", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core", - "EventCode": "0xA2", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core", - "EventCode": "0xA2", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.", - "EventCode": "0xA2", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Source Throttle", - "EventCode": "0xA4", - "EventName": "UNC_M3UPI_RING_SRC_THRTL", - "PerPkg": "1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN0; REQ on AD", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ", - "PerPkg": "1", - "PublicDescription": "VN0 message requested but lost arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN0; RSP on AD", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP", - "PerPkg": "1", - "PublicDescription": "VN0 message requested but lost arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN0; SNP on AD", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP", - "PerPkg": "1", - "PublicDescription": "VN0 message requested but lost arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN0; NCB on BL", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB", - "PerPkg": "1", - "PublicDescription": "VN0 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN0; NCS on BL", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS", - "PerPkg": "1", - "PublicDescription": "VN0 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN0; RSP on BL", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP", - "PerPkg": "1", - "PublicDescription": "VN0 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN0; WB on BL", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB", - "PerPkg": "1", - "PublicDescription": "VN0 message requested but lost arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN1; REQ on AD", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ", - "PerPkg": "1", - "PublicDescription": "VN1 message requested but lost arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN1; RSP on AD", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP", - "PerPkg": "1", - "PublicDescription": "VN1 message requested but lost arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN1; SNP on AD", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP", - "PerPkg": "1", - "PublicDescription": "VN1 message requested but lost arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN1; NCB on BL", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB", - "PerPkg": "1", - "PublicDescription": "VN1 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN1; NCS on BL", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS", - "PerPkg": "1", - "PublicDescription": "VN1 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN1; RSP on BL", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP", - "PerPkg": "1", - "PublicDescription": "VN1 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN1; WB on BL", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB", - "PerPkg": "1", - "PublicDescription": "VN1 message requested but lost arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Arb Miscellaneous; AD, BL Parallel Win", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN", - "PerPkg": "1", - "PublicDescription": "AD and BL messages won arbitration concurrently / in parallel", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN0", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0", - "PerPkg": "1", - "PublicDescription": "Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN1", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1", - "PerPkg": "1", - "PublicDescription": "Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN0", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0", - "PerPkg": "1", - "PublicDescription": "Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN1", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1", - "PerPkg": "1", - "PublicDescription": "Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN0", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN0", - "PerPkg": "1", - "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win to vn0, delaying vn1 win, because vn0 offered parallel ad/bl", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN1", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN1", - "PerPkg": "1", - "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win to vn1, delaying vn0 win, because vn1 offered parallel ad/bl", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN0; REQ on AD", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_REQ", - "PerPkg": "1", - "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN0; RSP on AD", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_RSP", - "PerPkg": "1", - "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN0; SNP on AD", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_SNP", - "PerPkg": "1", - "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN0; NCB on BL", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCB", - "PerPkg": "1", - "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN0; NCS on BL", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCS", - "PerPkg": "1", - "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN0; RSP on BL", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_RSP", - "PerPkg": "1", - "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN0; WB on BL", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_WB", - "PerPkg": "1", - "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN1; REQ on AD", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_REQ", - "PerPkg": "1", - "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN1; RSP on AD", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_RSP", - "PerPkg": "1", - "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN1; SNP on AD", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_SNP", - "PerPkg": "1", - "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN1; NCB on BL", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCB", - "PerPkg": "1", - "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN1; NCS on BL", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCS", - "PerPkg": "1", - "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN1; RSP on BL", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_RSP", - "PerPkg": "1", - "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN1; WB on BL", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_WB", - "PerPkg": "1", - "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN0; REQ on AD", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_REQ", - "PerPkg": "1", - "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN0; RSP on AD", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_RSP", - "PerPkg": "1", - "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN0; SNP on AD", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_SNP", - "PerPkg": "1", - "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN0; NCB on BL", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCB", - "PerPkg": "1", - "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN0; NCS on BL", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCS", - "PerPkg": "1", - "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN0; RSP on BL", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_RSP", - "PerPkg": "1", - "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN0; WB on BL", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_WB", - "PerPkg": "1", - "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN1; REQ on AD", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_REQ", - "PerPkg": "1", - "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN1; RSP on AD", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_RSP", - "PerPkg": "1", - "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN1; SNP on AD", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_SNP", - "PerPkg": "1", - "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN1; NCB on BL", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCB", - "PerPkg": "1", - "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN1; NCS on BL", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCS", - "PerPkg": "1", - "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN1; RSP on BL", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_RSP", - "PerPkg": "1", - "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN1; WB on BL", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_WB", - "PerPkg": "1", - "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on BL Arb", - "EventCode": "0x40", - "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB", - "PerPkg": "1", - "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while bl message is in arbitration", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on Idle", - "EventCode": "0x40", - "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE", - "PerPkg": "1", - "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while pipeline is idle", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 1", - "EventCode": "0x40", - "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT", - "PerPkg": "1", - "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 1 while merging with bl message in same flit", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 2", - "EventCode": "0x40", - "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT", - "PerPkg": "1", - "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 2 while merging with bl message in same flit", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message lost contest for flit; REQ on AD", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message lost contest for flit; RSP on AD", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message lost contest for flit; SNP on AD", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_SNP", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message lost contest for flit; NCB on BL", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message lost contest for flit; NCS on BL", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message lost contest for flit; RSP on BL", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message lost contest for flit; WB on BL", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_WB", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message lost contest for flit; REQ on AD", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message lost contest for flit; RSP on AD", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message lost contest for flit; SNP on AD", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_SNP", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message lost contest for flit; NCB on BL", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message lost contest for flit; NCS on BL", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message lost contest for flit; RSP on BL", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message lost contest for flit; WB on BL", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_WB", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Miscellaneous Credit Events; Any In BGF FIFO", - "EventCode": "0x60", - "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO", - "PerPkg": "1", - "PublicDescription": "Indication that at least one packet (flit) is in the bgf (fifo only)", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Miscellaneous Credit Events; Any in BGF Path", - "EventCode": "0x60", - "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH", - "PerPkg": "1", - "PublicDescription": "Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo)", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Miscellaneous Credit Events; No D2K For Arb", - "EventCode": "0x60", - "EventName": "UNC_M3UPI_RxC_CRD_MISC.NO_D2K_FOR_ARB", - "PerPkg": "1", - "PublicDescription": "VN0 or VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Credit Occupancy; D2K Credits", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD", - "PerPkg": "1", - "PublicDescription": "D2K completion fifo credit occupancy (credits in use), accumulated across all cycles", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Credit Occupancy; Packets in BGF FIFO", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO", - "PerPkg": "1", - "PublicDescription": "Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Credit Occupancy; Packets in BGF Path", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH", - "PerPkg": "1", - "PublicDescription": "Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo)", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Credit Occupancy", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO", - "PerPkg": "1", - "PublicDescription": "count of bl messages in pump-1-pending state, in completion fifo only", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Credit Occupancy", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL", - "PerPkg": "1", - "PublicDescription": "count of bl messages in pump-1-pending state, in marker table and in fifo", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Credit Occupancy; Transmit Credits", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD", - "PerPkg": "1", - "PublicDescription": "Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Credit Occupancy; VNA In Use", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE", - "PerPkg": "1", - "PublicDescription": "Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Data Flit Not Sent; All", - "EventCode": "0x57", - "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.ALL", - "PerPkg": "1", - "PublicDescription": "Data flit is ready for transmission but could not be sent", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Data Flit Not Sent; No BGF Credits", - "EventCode": "0x57", - "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_BGF", - "PerPkg": "1", - "PublicDescription": "Data flit is ready for transmission but could not be sent", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Data Flit Not Sent; No TxQ Credits", - "EventCode": "0x57", - "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_TXQ", - "PerPkg": "1", - "PublicDescription": "Data flit is ready for transmission but could not be sent", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 0", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT", - "PerPkg": "1", - "PublicDescription": "generating bl data flit sequence; waiting for data pump 0", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Generating BL Data Flit Sequence", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT", - "PerPkg": "1", - "PublicDescription": "pump-1-pending logic is at capacity (pending table plus completion fifo at limit)", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Generating BL Data Flit Sequence", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY", - "PerPkg": "1", - "PublicDescription": "pump-1-pending logic is tracking at least one message", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Generating BL Data Flit Sequence", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL", - "PerPkg": "1", - "PublicDescription": "pump-1-pending completion fifo is full", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Generating BL Data Flit Sequence", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0", - "PerPkg": "1", - "PublicDescription": "pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Generating BL Data Flit Sequence", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO", - "PerPkg": "1", - "PublicDescription": "a bl message finished but is in limbo and moved to pump-1-pending logic", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 1", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT", - "PerPkg": "1", - "PublicDescription": "generating bl data flit sequence; waiting for data pump 1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC", - "EventCode": "0x5A", - "EventName": "UNC_M3UPI_RxC_FLITS_MISC", - "PerPkg": "1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sent Header Flit; One Message", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG", - "PerPkg": "1", - "PublicDescription": "One message in flit; VNA or non-VNA flit", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sent Header Flit; One Message in non-VNA", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG_VNX", - "PerPkg": "1", - "PublicDescription": "One message in flit; non-VNA flit", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sent Header Flit; Two Messages", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SENT.2_MSGS", - "PerPkg": "1", - "PublicDescription": "Two messages in flit; VNA flit", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sent Header Flit; Three Messages", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SENT.3_MSGS", - "PerPkg": "1", - "PublicDescription": "Three messages in flit; VNA flit", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sent Header Flit", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sent Header Flit", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_2", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sent Header Flit", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_3", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Slotting BL Message Into Header Flit; All", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Slotting BL Message Into Header Flit; Needs Data Flit", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA", - "PerPkg": "1", - "PublicDescription": "BL message requires data flit sequence", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 0", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT", - "PerPkg": "1", - "PublicDescription": "Waiting for header pump 0", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ", - "PerPkg": "1", - "PublicDescription": "Header pump 1 is not required for flit", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Bubble", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE", - "PerPkg": "1", - "PublicDescription": "Header pump 1 is not required for flit but flit transmission delayed", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Not Avail", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL", - "PerPkg": "1", - "PublicDescription": "Header pump 1 is not required for flit and not available", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 1", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT", - "PerPkg": "1", - "PublicDescription": "Waiting for header pump 1", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 1; Accumulate", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM", - "PerPkg": "1", - "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 1; Accumulate Ready", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ", - "PerPkg": "1", - "PublicDescription": "Events related to Header Flit Generation - Set 1; header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 1; Accumulate Wasted", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED", - "PerPkg": "1", - "PublicDescription": "Events related to Header Flit Generation - Set 1; Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Blocked", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED", - "PerPkg": "1", - "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Message", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG", - "PerPkg": "1", - "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting is in run-ahead to start new flit, and message is actually slotted into new flit", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 1; Parallel Ok", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR", - "PerPkg": "1", - "PublicDescription": "Events related to Header Flit Generation - Set 1; New header flit construction may proceed in parallel with data flit sequence", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 1; Parallel Flit Finished", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_FLIT", - "PerPkg": "1", - "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit finished assembly in parallel with data flit sequence", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 1; Parallel Message", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_MSG", - "PerPkg": "1", - "PublicDescription": "Events related to Header Flit Generation - Set 1; Message is slotted into header flit in parallel with data flit sequence", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall", - "EventCode": "0x54", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL", - "PerPkg": "1", - "PublicDescription": "Events related to Header Flit Generation - Set 2; Rate-matching stall injected", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall - No Message", - "EventCode": "0x54", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG", - "PerPkg": "1", - "PublicDescription": "Events related to Header Flit Generation - Set 2; Rate matching stall injected, but no additional message slotted during stall cycle", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Header Not Sent; All", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ALL", - "PerPkg": "1", - "PublicDescription": "header flit is ready for transmission but could not be sent", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Header Not Sent; No BGF Credits", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_CRD", - "PerPkg": "1", - "PublicDescription": "header flit is ready for transmission but could not be sent; No BGF credits available", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Header Not Sent; No BGF Credits + No Extra Message Slotted", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_NO_MSG", - "PerPkg": "1", - "PublicDescription": "header flit is ready for transmission but could not be sent; No BGF credits available; no additional message slotted into flit", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Header Not Sent; No TxQ Credits", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_CRD", - "PerPkg": "1", - "PublicDescription": "header flit is ready for transmission but could not be sent; No TxQ credits available", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Header Not Sent; No TxQ Credits + No Extra Message Slotted", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_NO_MSG", - "PerPkg": "1", - "PublicDescription": "header flit is ready for transmission but could not be sent; No TxQ credits available; no additional message slotted into flit", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Header Not Sent; Sent - One Slot Taken", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ONE_TAKEN", - "PerPkg": "1", - "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with only one slot taken (two slots free)", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Header Not Sent; Sent - Three Slots Taken", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.THREE_TAKEN", - "PerPkg": "1", - "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with three slots taken (no slots free)", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Header Not Sent; Sent - Two Slots Taken", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.TWO_TAKEN", - "PerPkg": "1", - "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with only two slots taken (one slots free)", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Message Held; Can't Slot AD", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD", - "PerPkg": "1", - "PublicDescription": "some AD message could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1})", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Message Held; Can't Slot BL", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL", - "PerPkg": "1", - "PublicDescription": "some BL message could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1})", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Message Held; Parallel AD Lost", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_AD_LOST", - "PerPkg": "1", - "PublicDescription": "some AD message lost contest for slot 0 (logical OR of all AD events under INGR_SLOT_LOST_MC_VN{0,1})", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Message Held; Parallel Attempt", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT", - "PerPkg": "1", - "PublicDescription": "ad and bl messages attempted to slot into the same flit in parallel", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Message Held; Parallel BL Lost", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_BL_LOST", - "PerPkg": "1", - "PublicDescription": "some BL message lost contest for slot 0 (logical OR of all BL events under INGR_SLOT_LOST_MC_VN{0,1})", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Message Held; Parallel Success", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS", - "PerPkg": "1", - "PublicDescription": "ad and bl messages were actually slotted into the same flit in paralle", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Message Held; VN0", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_HELD.VN0", - "PerPkg": "1", - "PublicDescription": "vn0 message(s) that couldn't be slotted into last vn0 flit are held in slotting stage while processing vn1 flit", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Message Held; VN1", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_HELD.VN1", - "PerPkg": "1", - "PublicDescription": "vn1 message(s) that couldn't be slotted into last vn1 flit are held in slotting stage while processing vn0 flit", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; REQ on AD", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on AD", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; SNP on AD", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCB on BL", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCS on BL", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on BL", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; WB on BL", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; REQ on AD", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on AD", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; SNP on AD", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCB on BL", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCS on BL", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on BL", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; WB on BL", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; REQ on AD", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on AD", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; SNP on AD", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCB on BL", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCS on BL", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on BL", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; WB on BL", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; REQ on AD", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on AD", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; SNP on AD", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCB on BL", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCS on BL", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on BL", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; WB on BL", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message can't slot into flit; REQ on AD", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message can't slot into flit; RSP on AD", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message can't slot into flit; SNP on AD", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message can't slot into flit; NCB on BL", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message can't slot into flit; NCS on BL", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message can't slot into flit; RSP on BL", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message can't slot into flit; WB on BL", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message can't slot into flit; REQ on AD", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message can't slot into flit; RSP on AD", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message can't slot into flit; SNP on AD", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message can't slot into flit; NCB on BL", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message can't slot into flit; NCS on BL", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message can't slot into flit; RSP on BL", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message can't slot into flit; WB on BL", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "SMI3 Prefetch Messages; Lost Arbitration", - "EventCode": "0x62", - "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARB_LOST", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "SMI3 Prefetch Messages; Arrived", - "EventCode": "0x62", - "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARRIVED", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "SMI3 Prefetch Messages; Dropped - Old", - "EventCode": "0x62", - "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_OLD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "SMI3 Prefetch Messages; Dropped - Wrap", - "EventCode": "0x62", - "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_WRAP", - "PerPkg": "1", - "PublicDescription": "Dropped because it was overwritten by new message while prefetch queue was full", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "SMI3 Prefetch Messages; Slotted", - "EventCode": "0x62", - "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.SLOTTED", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Remote VNA Credits; Any In Use", - "EventCode": "0x5B", - "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE", - "PerPkg": "1", - "PublicDescription": "At least one remote vna credit is in use", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Remote VNA Credits; Corrected", - "EventCode": "0x5B", - "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED", - "PerPkg": "1", - "PublicDescription": "Number of remote vna credits corrected (local return) per cycle", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Remote VNA Credits; Level < 1", - "EventCode": "0x5B", - "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1", - "PerPkg": "1", - "PublicDescription": "Remote vna credit level is less than 1 (i.e. no vna credits available)", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Remote VNA Credits; Level < 4", - "EventCode": "0x5B", - "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4", - "PerPkg": "1", - "PublicDescription": "Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Remote VNA Credits; Level < 5", - "EventCode": "0x5B", - "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5", - "PerPkg": "1", - "PublicDescription": "Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Remote VNA Credits; Used", - "EventCode": "0x5B", - "EventName": "UNC_M3UPI_RxC_VNA_CRD.USED", - "PerPkg": "1", - "PublicDescription": "Number of remote vna credits consumed per cycle", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation; AD - Bounce", - "EventCode": "0xB4", - "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation; AD - Credit", - "EventCode": "0xB4", - "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation; BL - Bounce", - "EventCode": "0xB4", - "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation; BL - Credit", - "EventCode": "0xB4", - "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", - "EventCode": "0xB2", - "EventName": "UNC_M3UPI_RxR_BYPASS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Bypass; AD - Credit", - "EventCode": "0xB2", - "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", - "EventCode": "0xB2", - "EventName": "UNC_M3UPI_RxR_BYPASS.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", - "EventCode": "0xB2", - "EventName": "UNC_M3UPI_RxR_BYPASS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Bypass; BL - Credit", - "EventCode": "0xB2", - "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", - "EventCode": "0xB2", - "EventName": "UNC_M3UPI_RxR_BYPASS.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation; AD - Bounce", - "EventCode": "0xB3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation; AD - Credit", - "EventCode": "0xB3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation; AK - Bounce", - "EventCode": "0xB3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation; BL - Bounce", - "EventCode": "0xB3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation; BL - Credit", - "EventCode": "0xB3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation; IFV - Credit", - "EventCode": "0xB3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation; IV - Bounce", - "EventCode": "0xB3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", - "EventCode": "0xB1", - "EventName": "UNC_M3UPI_RxR_INSERTS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Allocations; AD - Credit", - "EventCode": "0xB1", - "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", - "EventCode": "0xB1", - "EventName": "UNC_M3UPI_RxR_INSERTS.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", - "EventCode": "0xB1", - "EventName": "UNC_M3UPI_RxR_INSERTS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Allocations; BL - Credit", - "EventCode": "0xB1", - "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", - "EventCode": "0xB1", - "EventName": "UNC_M3UPI_RxR_INSERTS.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", - "EventCode": "0xB0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", - "EventCode": "0xB0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", - "EventCode": "0xB0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", - "EventCode": "0xB0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", - "EventCode": "0xB0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", - "EventCode": "0xB0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for AD; VN0 REQ Messages", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ", - "PerPkg": "1", - "PublicDescription": "AD arb but no win; arb request asserted but not won", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for AD; VN0 RSP Messages", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "AD arb but no win; arb request asserted but not won", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for AD; VN0 SNP Messages", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "AD arb but no win; arb request asserted but not won", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for AD; VN0 WB Messages", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB", - "PerPkg": "1", - "PublicDescription": "AD arb but no win; arb request asserted but not won", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for AD; VN1 REQ Messages", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ", - "PerPkg": "1", - "PublicDescription": "AD arb but no win; arb request asserted but not won", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for AD; VN1 RSP Messages", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "AD arb but no win; arb request asserted but not won", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for AD; VN1 SNP Messages", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "AD arb but no win; arb request asserted but not won", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for AD; VN1 WB Messages", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB", - "PerPkg": "1", - "PublicDescription": "AD arb but no win; arb request asserted but not won", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD FlowQ Bypass", - "EventCode": "0x2C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0", - "PerPkg": "1", - "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD FlowQ Bypass", - "EventCode": "0x2C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1", - "PerPkg": "1", - "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD FlowQ Bypass", - "EventCode": "0x2C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2", - "PerPkg": "1", - "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD FlowQ Bypass", - "EventCode": "0x2C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP", - "PerPkg": "1", - "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Not Empty; VN0 REQ Messages", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Not Empty; VN0 RSP Messages", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Not Empty; VN0 SNP Messages", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Not Empty; VN0 WB Messages", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Not Empty; VN1 REQ Messages", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Not Empty; VN1 RSP Messages", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Not Empty; VN1 SNP Messages", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Not Empty; VN1 WB Messages", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Inserts; VN0 REQ Messages", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Inserts; VN0 RSP Messages", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Inserts; VN0 SNP Messages", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Inserts; VN0 WB Messages", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Inserts; VN1 REQ Messages", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Inserts; VN1 RSP Messages", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Inserts; VN1 SNP Messages", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Occupancy; VN0 REQ Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Occupancy; VN0 RSP Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Occupancy; VN0 SNP Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Occupancy; VN0 WB Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Occupancy; VN1 REQ Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Occupancy; VN1 RSP Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Occupancy; VN1 SNP Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Number of Snoop Targets; CHA on VN0", - "EventCode": "0x3C", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_CHA", - "PerPkg": "1", - "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to CHA", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN0", - "EventCode": "0x3C", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_NON_IDLE", - "PerPkg": "1", - "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of non-idle cycles in issuing Vn0 Snpf", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN0", - "EventCode": "0x3C", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI0", - "PerPkg": "1", - "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to peer UPI0", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN0", - "EventCode": "0x3C", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI1", - "PerPkg": "1", - "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to peer UPI1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Number of Snoop Targets; CHA on VN1", - "EventCode": "0x3C", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_CHA", - "PerPkg": "1", - "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to CHA", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN1", - "EventCode": "0x3C", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_NON_IDLE", - "PerPkg": "1", - "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of non-idle cycles in issuing Vn1 Snpf", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN1", - "EventCode": "0x3C", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI0", - "PerPkg": "1", - "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to peer UPI0", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN1", - "EventCode": "0x3C", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI1", - "PerPkg": "1", - "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to peer UPI1", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Snoop Arbitration; FlowQ Won", - "EventCode": "0x3D", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_NONSNP", - "PerPkg": "1", - "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn0", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won", - "EventCode": "0x3D", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_VN2SNP", - "PerPkg": "1", - "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ Vn0 SnpF issued when SnpF pending on Vn1", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Snoop Arbitration; FlowQ Won", - "EventCode": "0x3D", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_NONSNP", - "PerPkg": "1", - "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won", - "EventCode": "0x3D", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_VN0SNP", - "PerPkg": "1", - "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ Vn1 SnpF issued when SnpF pending on Vn0", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 REQ Messages", - "EventCode": "0x34", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_REQ", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 SNP Messages", - "EventCode": "0x34", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 WB Messages", - "EventCode": "0x34", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_WB", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 REQ Messages", - "EventCode": "0x34", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_REQ", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 SNP Messages", - "EventCode": "0x34", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 WB Messages", - "EventCode": "0x34", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_WB", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - New Message; VN0 REQ Messages", - "EventCode": "0x33", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_REQ", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - New Message; VN0 SNP Messages", - "EventCode": "0x33", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - New Message; VN0 WB Messages", - "EventCode": "0x33", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_WB", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - New Message; VN1 REQ Messages", - "EventCode": "0x33", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_REQ", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - New Message; VN1 SNP Messages", - "EventCode": "0x33", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - New Message; VN1 WB Messages", - "EventCode": "0x33", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_WB", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - No Credit; VN0 REQ Messages", - "EventCode": "0x32", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_REQ", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - No Credit; VN0 RSP Messages", - "EventCode": "0x32", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - No Credit; VN0 SNP Messages", - "EventCode": "0x32", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - No Credit; VN0 WB Messages", - "EventCode": "0x32", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_WB", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - No Credit; VN1 REQ Messages", - "EventCode": "0x32", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_REQ", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - No Credit; VN1 RSP Messages", - "EventCode": "0x32", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - No Credit; VN1 SNP Messages", - "EventCode": "0x32", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - No Credit; VN1 WB Messages", - "EventCode": "0x32", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_WB", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AK Flow Q Inserts", - "EventCode": "0x2F", - "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS", - "PerPkg": "1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AK Flow Q Occupancy", - "EventCode": "0x1E", - "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY", - "PerPkg": "1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL; VN0 NCB Messages", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB", - "PerPkg": "1", - "PublicDescription": "BL arb but no win; arb request asserted but not won", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL; VN0 NCS Messages", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS", - "PerPkg": "1", - "PublicDescription": "BL arb but no win; arb request asserted but not won", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL; VN0 RSP Messages", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "BL arb but no win; arb request asserted but not won", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL; VN0 WB Messages", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB", - "PerPkg": "1", - "PublicDescription": "BL arb but no win; arb request asserted but not won", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL; VN1 NCS Messages", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB", - "PerPkg": "1", - "PublicDescription": "BL arb but no win; arb request asserted but not won", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL; VN1 NCB Messages", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS", - "PerPkg": "1", - "PublicDescription": "BL arb but no win; arb request asserted but not won", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL; VN1 RSP Messages", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "BL arb but no win; arb request asserted but not won", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL; VN1 WB Messages", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB", - "PerPkg": "1", - "PublicDescription": "BL arb but no win; arb request asserted but not won", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Not Empty; VN0 REQ Messages", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Not Empty; VN0 RSP Messages", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Not Empty; VN0 SNP Messages", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Not Empty; VN0 WB Messages", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Not Empty; VN1 REQ Messages", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Not Empty; VN1 RSP Messages", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Not Empty; VN1 SNP Messages", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Not Empty; VN1 WB Messages", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Inserts; VN0 RSP Messages", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Inserts; VN0 WB Messages", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Inserts; VN0 NCS Messages", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Inserts; VN0 NCB Messages", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Inserts; VN1 RSP Messages", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Inserts; VN1 WB Messages", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Inserts; VN1_NCB Messages", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Inserts; VN1_NCS Messages", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy; VN0 NCB Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy; VN0 NCS Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy; VN0 RSP Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy; VN0 WB Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy; VN1_NCS Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy; VN1_NCB Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy; VN1 RSP Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy; VN1 WB Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB Messages", - "EventCode": "0x38", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCB", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for BL - New Message; VN0 NCS Messages", - "EventCode": "0x38", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCS", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB Messages", - "EventCode": "0x38", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_WB", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for BL - New Message; VN1 WB Messages", - "EventCode": "0x38", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCB", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for BL - New Message; VN1 NCB Messages", - "EventCode": "0x38", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCS", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for BL - New Message; VN1 RSP Messages", - "EventCode": "0x38", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_WB", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCB Messages", - "EventCode": "0x37", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCB", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCS Messages", - "EventCode": "0x37", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCS", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 RSP Messages", - "EventCode": "0x37", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 WB Messages", - "EventCode": "0x37", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_WB", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCS Messages", - "EventCode": "0x37", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCB", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCB Messages", - "EventCode": "0x37", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCS", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 RSP Messages", - "EventCode": "0x37", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 WB Messages", - "EventCode": "0x37", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_WB", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", - "EventCode": "0x9D", - "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", - "EventCode": "0x9D", - "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", - "EventCode": "0x9D", - "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", - "EventCode": "0x9D", - "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", - "EventCode": "0x9D", - "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", - "EventCode": "0x9F", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", - "EventCode": "0x9F", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", - "EventCode": "0x9F", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", - "EventCode": "0x9F", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", - "EventCode": "0x9F", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", - "EventCode": "0x9F", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce", - "EventCode": "0x97", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit", - "EventCode": "0x97", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce", - "EventCode": "0x97", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce", - "EventCode": "0x97", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit", - "EventCode": "0x97", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce", - "EventCode": "0x97", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", - "EventCode": "0x95", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", - "EventCode": "0x95", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", - "EventCode": "0x95", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", - "EventCode": "0x95", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", - "EventCode": "0x95", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", - "EventCode": "0x95", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", - "EventCode": "0x99", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", - "EventCode": "0x99", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", - "EventCode": "0x99", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", - "EventCode": "0x99", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", - "EventCode": "0x99", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", - "EventCode": "0x99", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce", - "EventCode": "0x9B", - "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce", - "EventCode": "0x9B", - "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce", - "EventCode": "0x9B", - "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce", - "EventCode": "0x9B", - "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", - "EventCode": "0x9E", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", - "EventCode": "0x9E", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", - "EventCode": "0x9E", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", - "EventCode": "0x9E", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", - "EventCode": "0x9E", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", - "EventCode": "0x9E", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; IV", - "EventCode": "0x9E", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.IV", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV", - "EventCode": "0x93", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.IV", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; IV", - "EventCode": "0x91", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.IV", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; IV", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK.IV", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; IV", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.IV", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED.IV", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 AD Credits Empty; VN0 REQ Messages", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 AD Credits Empty; VN0 RSP Messages", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 AD Credits Empty; VN0 SNP Messages", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 AD Credits Empty; VN1 REQ Messages", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 AD Credits Empty; VN1 RSP Messages", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 AD Credits Empty; VN1 SNP Messages", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 AD Credits Empty; VNA", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 BL Credits Empty; VN0 RSP Messages", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 BL Credits Empty; VN0 REQ Messages", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 BL Credits Empty; VN0 SNP Messages", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 BL Credits Empty; VN1 RSP Messages", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 BL Credits Empty; VN1 REQ Messages", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 BL Credits Empty; VN1 SNP Messages", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 BL Credits Empty; VNA", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Prefetches generated by the flow control queue of the M3UPI unit.", - "EventCode": "0x29", - "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN", - "PerPkg": "1", - "PublicDescription": "Count cases where flow control queue that sits between the Intel(R) Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller)", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AD Ring In Use; Down and Even", - "EventCode": "0xA6", - "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AD Ring In Use; Down and Odd", - "EventCode": "0xA6", - "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AD Ring In Use; Up and Even", - "EventCode": "0xA6", - "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AD Ring In Use; Up and Odd", - "EventCode": "0xA6", - "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AK Ring In Use; Down and Even", - "EventCode": "0xA8", - "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AK Ring In Use; Down and Odd", - "EventCode": "0xA8", - "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AK Ring In Use; Up and Even", - "EventCode": "0xA8", - "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AK Ring In Use; Up and Odd", - "EventCode": "0xA8", - "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical BL Ring in Use; Down and Even", - "EventCode": "0xAA", - "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical BL Ring in Use; Down and Odd", - "EventCode": "0xAA", - "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical BL Ring in Use; Up and Even", - "EventCode": "0xAA", - "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical BL Ring in Use; Up and Odd", - "EventCode": "0xAA", - "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical IV Ring in Use; Down", - "EventCode": "0xAC", - "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical IV Ring in Use; Up", - "EventCode": "0xAC", - "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Credit Used; WB on BL", - "EventCode": "0x5C", - "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Credit Used; NCB on BL", - "EventCode": "0x5C", - "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Credit Used; REQ on AD", - "EventCode": "0x5C", - "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Credit Used; RSP on AD", - "EventCode": "0x5C", - "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Credit Used; SNP on AD", - "EventCode": "0x5C", - "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Credit Used; RSP on BL", - "EventCode": "0x5C", - "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 No Credits; WB on BL", - "EventCode": "0x5E", - "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB", - "PerPkg": "1", - "PublicDescription": "Number of Cycles there were no VN0 Credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 No Credits; NCB on BL", - "EventCode": "0x5E", - "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS", - "PerPkg": "1", - "PublicDescription": "Number of Cycles there were no VN0 Credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 No Credits; REQ on AD", - "EventCode": "0x5E", - "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ", - "PerPkg": "1", - "PublicDescription": "Number of Cycles there were no VN0 Credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 No Credits; RSP on AD", - "EventCode": "0x5E", - "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP", - "PerPkg": "1", - "PublicDescription": "Number of Cycles there were no VN0 Credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 No Credits; SNP on AD", - "EventCode": "0x5E", - "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP", - "PerPkg": "1", - "PublicDescription": "Number of Cycles there were no VN0 Credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 No Credits; RSP on BL", - "EventCode": "0x5E", - "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB", - "PerPkg": "1", - "PublicDescription": "Number of Cycles there were no VN0 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Credit Used; WB on BL", - "EventCode": "0x5D", - "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Credit Used; NCB on BL", - "EventCode": "0x5D", - "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Credit Used; REQ on AD", - "EventCode": "0x5D", - "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Credit Used; RSP on AD", - "EventCode": "0x5D", - "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Credit Used; SNP on AD", - "EventCode": "0x5D", - "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Credit Used; RSP on BL", - "EventCode": "0x5D", - "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 No Credits; WB on BL", - "EventCode": "0x5F", - "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB", - "PerPkg": "1", - "PublicDescription": "Number of Cycles there were no VN1 Credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 No Credits; NCB on BL", - "EventCode": "0x5F", - "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS", - "PerPkg": "1", - "PublicDescription": "Number of Cycles there were no VN1 Credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 No Credits; REQ on AD", - "EventCode": "0x5F", - "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ", - "PerPkg": "1", - "PublicDescription": "Number of Cycles there were no VN1 Credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 No Credits; RSP on AD", - "EventCode": "0x5F", - "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP", - "PerPkg": "1", - "PublicDescription": "Number of Cycles there were no VN1 Credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 No Credits; SNP on AD", - "EventCode": "0x5F", - "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP", - "PerPkg": "1", - "PublicDescription": "Number of Cycles there were no VN1 Credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 No Credits; RSP on BL", - "EventCode": "0x5F", - "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB", - "PerPkg": "1", - "PublicDescription": "Number of Cycles there were no VN1 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_TxC_BL.DRS_UPI", - "Deprecated": "1", - "EventCode": "0x40", - "EventName": "UNC_NoUnit_TxC_BL.DRS_UPI", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Clocks of the Intel(R) Ultra Path Interconnect (UPI)", - "EventCode": "0x1", - "EventName": "UNC_UPI_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Counts clockticks of the fixed frequency clock controlling the Intel(R) Ultra Path Interconnect (UPI). This clock runs at1/8th the 'GT/s' speed of the UPI link. For example, a 9.6GT/s link will have a fixed Frequency of 1.2 Ghz.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Data Response packets that go direct to core", - "EventCode": "0x12", - "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C", - "PerPkg": "1", - "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to core bypassing the CHA.", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_DIRECT_ATTEMPTS.D2U", - "Deprecated": "1", - "EventCode": "0x12", - "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Data Response packets that go direct to Intel(R) UPI", - "EventCode": "0x12", - "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2U", - "PerPkg": "1", - "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to Intel(R) Ultra Path Interconnect (UPI) bypassing the CHA .", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Cycles Intel(R) UPI is in L1 power mode (shutdown)", - "EventCode": "0x21", - "EventName": "UNC_UPI_L1_POWER_CYCLES", - "PerPkg": "1", - "PublicDescription": "Counts cycles when the Intel(R) Ultra Path Interconnect (UPI) is in L1 power mode. L1 is a mode that totally shuts down the UPI link. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdown.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", - "EventCode": "0x14", - "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", - "EventCode": "0x14", - "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", - "EventCode": "0x14", - "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", - "EventCode": "0x14", - "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", - "EventCode": "0x14", - "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED", - "EventCode": "0x16", - "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1", - "EventCode": "0x20", - "EventName": "UNC_UPI_PHY_INIT_CYCLES", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "L1 Req Nack", - "EventCode": "0x23", - "EventName": "UNC_UPI_POWER_L1_NACK", - "PerPkg": "1", - "PublicDescription": "Counts the number of times a link sends/receives a LinkReqNAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx originally requested the power change). A Tx LinkReqNAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).", - "Unit": "UPI LL" - }, - { - "BriefDescription": "L1 Req (same as L1 Ack).", - "EventCode": "0x22", - "EventName": "UNC_UPI_POWER_L1_REQ", - "PerPkg": "1", - "PublicDescription": "Counts the number of times a link sends/receives a LinkReqAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqAck refers to receiving an Ack (meaning this agent's Tx originally requested the power change). A Tx LinkReqAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", - "EventCode": "0x46", - "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", - "EventCode": "0x46", - "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", - "EventCode": "0x46", - "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", - "EventCode": "0x46", - "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Cycles the Rx of the Intel(R) UPI is in L0p power mode", - "EventCode": "0x25", - "EventName": "UNC_UPI_RxL0P_POWER_CYCLES", - "PerPkg": "1", - "PublicDescription": "Counts cycles when the receive side (Rx) of the Intel(R) Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Cycles in L0. Receive side.", - "EventCode": "0x24", - "EventName": "UNC_UPI_RxL0_POWER_CYCLES", - "PerPkg": "1", - "PublicDescription": "Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", - "PerPkg": "1", - "PublicDescription": "Match Message Class - NCB", - "UMask": "0xe", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC", - "PerPkg": "1", - "PublicDescription": "Match Message Class - NCB", - "UMask": "0x10e", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", - "PerPkg": "1", - "PublicDescription": "Match Message Class - NCS", - "UMask": "0xf", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC", - "PerPkg": "1", - "PublicDescription": "Match Message Class - NCS", - "UMask": "0x10f", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Request", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", - "PerPkg": "1", - "PublicDescription": "REQ Message Class", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Request Opcode", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC", - "PerPkg": "1", - "PublicDescription": "Match REQ Opcodes - Specified in Umask[7:4]", - "UMask": "0x108", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Response - Conflict", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT", - "PerPkg": "1", - "UMask": "0x1aa", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Response - Invalid", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI", - "PerPkg": "1", - "UMask": "0x12a", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", - "PerPkg": "1", - "PublicDescription": "Match Message Class -WB", - "UMask": "0xc", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC", - "PerPkg": "1", - "PublicDescription": "Match Message Class -WB", - "UMask": "0x10c", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA", - "PerPkg": "1", - "PublicDescription": "Match Message Class - RSP", - "UMask": "0xa", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", - "PerPkg": "1", - "PublicDescription": "Match Message Class - RSP", - "UMask": "0x10a", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Snoop", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", - "PerPkg": "1", - "PublicDescription": "SNP Message Class", - "UMask": "0x9", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Snoop Opcode", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC", - "PerPkg": "1", - "PublicDescription": "Match SNP Opcodes - Specified in Umask[7:4]", - "UMask": "0x109", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Writeback", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB", - "PerPkg": "1", - "PublicDescription": "Match Message Class -WB", - "UMask": "0xd", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Writeback", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC", - "PerPkg": "1", - "PublicDescription": "Match Message Class -WB", - "UMask": "0x10d", - "Unit": "UPI LL" - }, - { - "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", - "EventCode": "0x31", - "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", - "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", - "EventCode": "0x31", - "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", - "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer (Receive Queue) and passed directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", - "EventCode": "0x31", - "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", - "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "VN0 Credit Consumed", - "EventCode": "0x39", - "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0", - "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "VN1 Credit Consumed", - "EventCode": "0x3A", - "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1", - "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "VNA Credit Consumed", - "EventCode": "0x38", - "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA", - "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid data FLITs received from any slot", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", - "PerPkg": "1", - "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel(R) Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.", - "UMask": "0xf", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Null FLITs received from any slot", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", - "PerPkg": "1", - "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel(R) Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.", - "UMask": "0x27", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received; Data", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.DATA", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received; Idle", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.IDLE", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).", - "UMask": "0x47", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received; LLCRD Not Empty", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.LLCRD", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2", - "UMask": "0x10", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received; LLCTRL", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.LLCTRL", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.", - "UMask": "0x40", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Protocol header and credit FLITs received from any slot", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", - "PerPkg": "1", - "PublicDescription": "Counts protocol header and credit FLITs (80 bit FLow control unITs) received from any of the 3 UPI slots on this UPI unit.", - "UMask": "0x97", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.ALL_NULL", - "Deprecated": "1", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.NULL", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received; Protocol Header", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.PROTHDR", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)", - "UMask": "0x80", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.PROTHDR", - "Deprecated": "1", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.PROT_HDR", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received; Slot 0", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.SLOT0", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 0 - Other mask bits determine types of headers to count.", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received; Slot 1", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.SLOT1", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 1 - Other mask bits determine types of headers to count.", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received; Slot 2", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.SLOT2", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 2 - Other mask bits determine types of headers to count.", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", - "Deprecated": "1", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_HDR_MATCH.NCB", - "PerPkg": "1", - "UMask": "0xc", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", - "Deprecated": "1", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_HDR_MATCH.NCS", - "PerPkg": "1", - "UMask": "0xd", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", - "Deprecated": "1", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_HDR_MATCH.REQ", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", - "Deprecated": "1", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_HDR_MATCH.RSP", - "PerPkg": "1", - "UMask": "0xa", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", - "Deprecated": "1", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_HDR_MATCH.SNP", - "PerPkg": "1", - "UMask": "0x9", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.WB", - "Deprecated": "1", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_HDR_MATCH.WB", - "PerPkg": "1", - "UMask": "0xb", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Flit Buffer Allocations; Slot 0", - "EventCode": "0x30", - "EventName": "UNC_UPI_RxL_INSERTS.SLOT0", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Flit Buffer Allocations; Slot 1", - "EventCode": "0x30", - "EventName": "UNC_UPI_RxL_INSERTS.SLOT1", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Flit Buffer Allocations; Slot 2", - "EventCode": "0x30", - "EventName": "UNC_UPI_RxL_INSERTS.SLOT2", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Occupancy - All Packets; Slot 0", - "EventCode": "0x32", - "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Occupancy - All Packets; Slot 1", - "EventCode": "0x32", - "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Occupancy - All Packets; Slot 2", - "EventCode": "0x32", - "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", - "EventCode": "0x33", - "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", - "EventCode": "0x33", - "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", - "EventCode": "0x33", - "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", - "EventCode": "0x33", - "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", - "EventCode": "0x33", - "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", - "EventCode": "0x33", - "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Cycles in which the Tx of the Intel(R) Ultra Path Interconnect (UPI) is in L0p power mode", - "EventCode": "0x27", - "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", - "PerPkg": "1", - "PublicDescription": "Counts cycles when the transmit side (Tx) of the Intel(R) Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", - "EventCode": "0x28", - "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", - "EventCode": "0x29", - "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Cycles in L0. Transmit side.", - "EventCode": "0x26", - "EventName": "UNC_UPI_TxL0_POWER_CYCLES", - "PerPkg": "1", - "PublicDescription": "Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", - "PerPkg": "1", - "PublicDescription": "Match Message Class - NCB", - "UMask": "0xe", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC", - "PerPkg": "1", - "PublicDescription": "Match Message Class - NCB", - "UMask": "0x10e", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", - "PerPkg": "1", - "PublicDescription": "Match Message Class - NCS", - "UMask": "0xf", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC", - "PerPkg": "1", - "PublicDescription": "Match Message Class - NCS", - "UMask": "0x10f", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Request", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", - "PerPkg": "1", - "PublicDescription": "REQ Message Class", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Request Opcode", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC", - "PerPkg": "1", - "PublicDescription": "Match REQ Opcodes - Specified in Umask[7:4]", - "UMask": "0x108", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Conflict", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT", - "PerPkg": "1", - "UMask": "0x1aa", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Invalid", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI", - "PerPkg": "1", - "UMask": "0x12a", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", - "PerPkg": "1", - "PublicDescription": "Match Message Class -WB", - "UMask": "0xc", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC", - "PerPkg": "1", - "PublicDescription": "Match Message Class -WB", - "UMask": "0x10c", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", - "PerPkg": "1", - "PublicDescription": "Match Message Class - RSP", - "UMask": "0xa", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", - "PerPkg": "1", - "PublicDescription": "Match Message Class - RSP", - "UMask": "0x10a", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", - "PerPkg": "1", - "PublicDescription": "SNP Message Class", - "UMask": "0x9", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop Opcode", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC", - "PerPkg": "1", - "PublicDescription": "Match SNP Opcodes - Specified in Umask[7:4]", - "UMask": "0x109", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB", - "PerPkg": "1", - "PublicDescription": "Match Message Class -WB", - "UMask": "0xd", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC", - "PerPkg": "1", - "PublicDescription": "Match Message Class -WB", - "UMask": "0x10d", - "Unit": "UPI LL" - }, - { - "BriefDescription": "FLITs that bypassed the TxL Buffer", - "EventCode": "0x41", - "EventName": "UNC_UPI_TxL_BYPASSED", - "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel(R) Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link. However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR mode, increasing latency to transfer out to the link.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid data FLITs transmitted via any slot", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", - "PerPkg": "1", - "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel(R) Ultra Path Interconnect (UPI) slots on this UPI unit.", - "UMask": "0xf", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Null FLITs transmitted from any slot", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", - "PerPkg": "1", - "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel(R) Ulra Path Interconnect (UPI) slots on this UPI unit.", - "UMask": "0x27", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent; Data", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.DATA", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Idle FLITs transmitted", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.IDLE", - "PerPkg": "1", - "PublicDescription": "Counts when the Intel Ultra Path Interconnect(UPI) transmits an idle FLIT(80 bit FLow control unITs). Every UPI cycle must be sending either data FLITs, protocol/credit FLITs or idle FLITs.", - "UMask": "0x47", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent; LLCRD Not Empty", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.LLCRD", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2", - "UMask": "0x10", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent; LLCTRL", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.LLCTRL", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.", - "UMask": "0x40", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Protocol header and credit FLITs transmitted across any slot", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", - "PerPkg": "1", - "PublicDescription": "Counts protocol header and credit FLITs (80 bit FLow control unITs) transmitted across any of the 3 UPI (Ultra Path Interconnect) slots on this UPI unit.", - "UMask": "0x97", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.ALL_NULL", - "Deprecated": "1", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.NULL", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent; Protocol Header", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.PROTHDR", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)", - "UMask": "0x80", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.PROTHDR", - "Deprecated": "1", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.PROT_HDR", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent; Slot 0", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.SLOT0", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 0 - Other mask bits determine types of headers to count.", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent; Slot 1", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.SLOT1", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 1 - Other mask bits determine types of headers to count.", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent; Slot 2", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.SLOT2", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 2 - Other mask bits determine types of headers to count.", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.DATA_HDR", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.DUAL_SLOT_HDR", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.LOC", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.NCB", - "PerPkg": "1", - "UMask": "0xe", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.NCS", - "PerPkg": "1", - "UMask": "0xf", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.NON_DATA_HDR", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.REM", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.REQ", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_DATA", - "PerPkg": "1", - "UMask": "0xc", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_NODATA", - "PerPkg": "1", - "UMask": "0xa", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.SGL_SLOT_HDR", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.SNP", - "PerPkg": "1", - "UMask": "0x9", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.WB", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.WB", - "PerPkg": "1", - "UMask": "0xc", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Tx Flit Buffer Allocations", - "EventCode": "0x40", - "EventName": "UNC_UPI_TxL_INSERTS", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the UPI Tx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Tx Flit Buffer Occupancy", - "EventCode": "0x42", - "EventName": "UNC_UPI_TxL_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of flits in the TxQ. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", - "EventCode": "0x45", - "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "VNA Credits Pending Return - Occupancy", - "EventCode": "0x44", - "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", - "EventCode": "0xff", - "EventName": "UNC_U_CLOCKTICKS", - "PerPkg": "1", - "Unit": "UBOX" - }, - { - "BriefDescription": "Message Received", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", - "PerPkg": "1", - "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.", - "UMask": "0x8", - "Unit": "UBOX" - }, - { - "BriefDescription": "Message Received", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.INT_PRIO", - "PerPkg": "1", - "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.", - "UMask": "0x10", - "Unit": "UBOX" - }, - { - "BriefDescription": "Message Received; IPI", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", - "PerPkg": "1", - "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.; Inter Processor Interrupts", - "UMask": "0x4", - "Unit": "UBOX" - }, - { - "BriefDescription": "Message Received; MSI", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", - "PerPkg": "1", - "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.; Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "Message Received; VLW", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", - "PerPkg": "1", - "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "IDI Lock/SplitLock Cycles", - "EventCode": "0x44", - "EventName": "UNC_U_LOCK_CYCLES", - "PerPkg": "1", - "PublicDescription": "Number of times an IDI Lock/SplitLock sequence was started", - "Unit": "UBOX" - }, - { - "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", - "EventCode": "0x45", - "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", - "PerPkg": "1", - "PublicDescription": "PHOLD cycles.", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", - "EventCode": "0x4C", - "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_RACU_DRNG.RDRAND", - "EventCode": "0x4C", - "EventName": "UNC_U_RACU_DRNG.RDRAND", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_RACU_DRNG.RDSEED", - "EventCode": "0x4C", - "EventName": "UNC_U_RACU_DRNG.RDSEED", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "RACU Request", - "EventCode": "0x46", - "EventName": "UNC_U_RACU_REQUESTS", - "PerPkg": "1", - "PublicDescription": "Number outstanding register requests within message channel tracker", - "Unit": "UBOX" - }, - { - "BriefDescription": "UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data", - "EventCode": "0x2", - "EventName": "UPI_DATA_BANDWIDTH_TX", - "PerPkg": "1", - "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel(R) Ultra Path Interconnect (UPI) slots on this UPI unit.", - "ScaleUnit": "7.11E-06Bytes", - "UMask": "0xf", - "Unit": "UPI LL" - } -] -- cgit v1.2.3-58-ga151 From 6910f7bac205b28110f896b0b9881ecd35772426 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 13 Apr 2023 06:29:37 -0700 Subject: perf vendor events intel: Fix uncore topics for haswell Move events from 'uncore-other' topic classification to cache and interconnect. Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230413132949.3487664-10-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/haswell/uncore-cache.json | 50 ++++++++++----------- .../arch/x86/haswell/uncore-interconnect.json | 52 ++++++++++++++++++++++ .../pmu-events/arch/x86/haswell/uncore-other.json | 50 --------------------- 3 files changed, 77 insertions(+), 75 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/haswell/uncore-interconnect.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json b/tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json index c538557ba4c0..be9a3ed1a940 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json @@ -5,7 +5,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES", "PerPkg": "1", "UMask": "0x86", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.", @@ -13,7 +13,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I", "PerPkg": "1", "UMask": "0x88", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.", @@ -21,7 +21,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M", "PerPkg": "1", "UMask": "0x81", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.", @@ -29,7 +29,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI", "PerPkg": "1", "UMask": "0x8f", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.", @@ -37,7 +37,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES", "PerPkg": "1", "UMask": "0x46", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.", @@ -45,7 +45,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I", "PerPkg": "1", "UMask": "0x48", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.", @@ -53,7 +53,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M", "PerPkg": "1", "UMask": "0x41", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.", @@ -61,7 +61,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI", "PerPkg": "1", "UMask": "0x4f", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.", @@ -69,7 +69,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES", "PerPkg": "1", "UMask": "0x16", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup read request that access cache and found line in I-state.", @@ -77,7 +77,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I", "PerPkg": "1", "UMask": "0x18", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup read request that access cache and found line in M-state.", @@ -85,7 +85,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M", "PerPkg": "1", "UMask": "0x11", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state.", @@ -93,7 +93,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI", "PerPkg": "1", "UMask": "0x1f", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state.", @@ -101,7 +101,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES", "PerPkg": "1", "UMask": "0x26", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup write request that access cache and found line in I-state.", @@ -109,7 +109,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I", "PerPkg": "1", "UMask": "0x28", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup write request that access cache and found line in M-state.", @@ -117,7 +117,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M", "PerPkg": "1", "UMask": "0x21", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state.", @@ -125,7 +125,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI", "PerPkg": "1", "UMask": "0x2f", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.", @@ -133,7 +133,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION", "PerPkg": "1", "UMask": "0x88", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "An external snoop hits a modified line in some processor core.", @@ -141,7 +141,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL", "PerPkg": "1", "UMask": "0x28", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.", @@ -149,7 +149,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", "PerPkg": "1", "UMask": "0x48", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.", @@ -157,7 +157,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION", "PerPkg": "1", "UMask": "0x84", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "An external snoop hits a non-modified line in some processor core.", @@ -165,7 +165,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL", "PerPkg": "1", "UMask": "0x24", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.", @@ -173,7 +173,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", "PerPkg": "1", "UMask": "0x44", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.", @@ -181,7 +181,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", "PerPkg": "1", "UMask": "0x81", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "An external snoop misses in some processor core.", @@ -189,7 +189,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL", "PerPkg": "1", "UMask": "0x21", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.", @@ -197,6 +197,6 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", "PerPkg": "1", "UMask": "0x41", - "Unit": "CBO" + "Unit": "CBOX" } ] diff --git a/tools/perf/pmu-events/arch/x86/haswell/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/haswell/uncore-interconnect.json new file mode 100644 index 000000000000..8da28239ebf9 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/haswell/uncore-interconnect.json @@ -0,0 +1,52 @@ +[ + { + "BriefDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory)", + "EventCode": "0x83", + "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.All", + "PerPkg": "1", + "PublicDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory).", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.", + "EventCode": "0x84", + "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle counts number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", + "CounterMask": "1", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "ARB" + } +] diff --git a/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json b/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json index 84cc2536de69..2af92e43b28a 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json @@ -1,54 +1,4 @@ [ - { - "BriefDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory)", - "EventCode": "0x83", - "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.All", - "PerPkg": "1", - "PublicDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory).", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.", - "EventCode": "0x84", - "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Each cycle counts number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.", - "EventCode": "0x80", - "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", - "CounterMask": "1", - "EventCode": "0x80", - "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "ARB" - }, { "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.", "EventCode": "0xff", -- cgit v1.2.3-58-ga151 From 579c04721539f690c63a9fe095d76af235a95864 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 13 Apr 2023 06:29:38 -0700 Subject: perf vendor events intel: Fix uncore topics for haswellx Remove 'uncore-other' topic classification, move to cache, interconnect and io. Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Edward Baker Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: http://lore.kernel.org/lkml/20230413132949.3487664-11-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/haswellx/uncore-cache.json | 360 +- .../arch/x86/haswellx/uncore-interconnect.json | 4242 ++++++++++++++++---- .../pmu-events/arch/x86/haswellx/uncore-io.json | 528 +++ .../pmu-events/arch/x86/haswellx/uncore-other.json | 3160 --------------- 4 files changed, 4145 insertions(+), 4145 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/haswellx/uncore-io.json delete mode 100644 tools/perf/pmu-events/arch/x86/haswellx/uncore-other.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json b/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json index e969dc71bea1..9227cc226002 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json @@ -8,7 +8,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LLC prefetch misses for data reads. Derived from unc_c_tor_inserts.miss_opcode", @@ -19,7 +19,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LLC misses - demand and prefetch data reads - excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode", @@ -30,7 +30,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "MMIO reads. Derived from unc_c_tor_inserts.miss_opcode", @@ -41,7 +41,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "MMIO writes. Derived from unc_c_tor_inserts.miss_opcode", @@ -52,7 +52,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "PCIe write misses (full cache line). Derived from unc_c_tor_inserts.miss_opcode", @@ -63,7 +63,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LLC misses for PCIe read current. Derived from unc_c_tor_inserts.miss_opcode", @@ -74,7 +74,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ItoM write misses (as part of fast string memcpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_opcode", @@ -85,7 +85,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LLC prefetch misses for RFO. Derived from unc_c_tor_inserts.miss_opcode", @@ -96,7 +96,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_c_tor_inserts.miss_opcode", @@ -107,7 +107,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "ScaleUnit": "64Bytes", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L2 demand and L2 prefetch code references to LLC. Derived from unc_c_tor_inserts.opcode", @@ -118,7 +118,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "PCIe writes (partial cache line). Derived from unc_c_tor_inserts.opcode", @@ -128,7 +128,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "PCIe read current. Derived from unc_c_tor_inserts.opcode", @@ -139,7 +139,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "PCIe write references (full cache line). Derived from unc_c_tor_inserts.opcode", @@ -150,7 +150,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Streaming stores (full cache line). Derived from unc_c_tor_inserts.opcode", @@ -161,7 +161,7 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Streaming stores (partial cache line). Derived from unc_c_tor_inserts.opcode", @@ -172,20 +172,20 @@ "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "ScaleUnit": "64Bytes", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Bounce Control", "EventCode": "0xA", "EventName": "UNC_C_BOUNCE_CONTROL", "PerPkg": "1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Uncore Clocks", "EventName": "UNC_C_CLOCKTICKS", "PerPkg": "1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Counter 0 Occupancy", @@ -193,7 +193,7 @@ "EventName": "UNC_C_COUNTER0_OCCUPANCY", "PerPkg": "1", "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "FaST wire asserted", @@ -201,7 +201,7 @@ "EventName": "UNC_C_FAST_ASSERTED", "PerPkg": "1", "PublicDescription": "Counts the number of cycles either the local distress or incoming distress signals are asserted. Incoming distress includes both up and dn.", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "All LLC Misses (code+ data rd + data wr - including demand and prefetch)", @@ -212,7 +212,7 @@ "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.", "ScaleUnit": "64Bytes", "UMask": "0x11", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; Data Read Request", @@ -221,7 +221,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; Lookups that Match NID", @@ -230,7 +230,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x41", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; Any Read Request", @@ -239,7 +239,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Read transactions", "UMask": "0x21", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; External Snoop Request", @@ -248,7 +248,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ.", "UMask": "0x9", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; Write Requests", @@ -257,7 +257,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.", "UMask": "0x5", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized; Lines in E state", @@ -266,7 +266,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized", @@ -275,7 +275,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized; Lines in S State", @@ -284,7 +284,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized", @@ -293,7 +293,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "M line evictions from LLC (writebacks to memory)", @@ -303,7 +303,7 @@ "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "ScaleUnit": "64Bytes", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized; Victimized Lines that Match NID", @@ -312,7 +312,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines in S State", @@ -321,7 +321,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=0", @@ -330,7 +330,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc; Clean Victim with raw CV=0", @@ -339,7 +339,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc; RFO HitS", @@ -348,7 +348,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.; Number of times that an RFO hit in S state. This is useful for determining if it might be good for a workload to use RspIWB instead of RspSWB.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc; Silent Snoop Eviction", @@ -357,7 +357,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc", @@ -366,7 +366,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc; Write Combining Aliasing", @@ -375,7 +375,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LRU Queue; LRU Age 0", @@ -384,7 +384,7 @@ "PerPkg": "1", "PublicDescription": "How often age was set to 0", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LRU Queue; LRU Age 1", @@ -393,7 +393,7 @@ "PerPkg": "1", "PublicDescription": "How often age was set to 1", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LRU Queue; LRU Age 2", @@ -402,7 +402,7 @@ "PerPkg": "1", "PublicDescription": "How often age was set to 2", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LRU Queue; LRU Age 3", @@ -411,7 +411,7 @@ "PerPkg": "1", "PublicDescription": "How often age was set to 3", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LRU Queue; LRU Bits Decremented", @@ -420,7 +420,7 @@ "PerPkg": "1", "PublicDescription": "How often all LRU bits were decremented by 1", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LRU Queue; Non-0 Aged Victim", @@ -429,7 +429,7 @@ "PerPkg": "1", "PublicDescription": "How often we picked a victim that had a non-zero age", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; All", @@ -438,7 +438,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0xf", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Down", @@ -447,7 +447,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0xc", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Down and Even", @@ -456,7 +456,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Down and Odd", @@ -465,7 +465,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Up", @@ -474,7 +474,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Up and Even", @@ -483,7 +483,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Up and Odd", @@ -492,7 +492,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; All", @@ -501,7 +501,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0xf", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Down", @@ -510,7 +510,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0xc", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Down and Even", @@ -519,7 +519,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Down and Odd", @@ -528,7 +528,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Up", @@ -537,7 +537,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Up and Even", @@ -546,7 +546,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Up and Odd", @@ -555,7 +555,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Down", @@ -564,7 +564,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0xf", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Down", @@ -573,7 +573,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0xc", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Down and Even", @@ -582,7 +582,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Down and Odd", @@ -591,7 +591,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Up", @@ -600,7 +600,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Up and Even", @@ -609,7 +609,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Up and Odd", @@ -618,7 +618,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of LLC responses that bounced on the Ring.; AD", @@ -626,7 +626,7 @@ "EventName": "UNC_C_RING_BOUNCES.AD", "PerPkg": "1", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of LLC responses that bounced on the Ring.; AK", @@ -634,7 +634,7 @@ "EventName": "UNC_C_RING_BOUNCES.AK", "PerPkg": "1", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of LLC responses that bounced on the Ring.; BL", @@ -642,7 +642,7 @@ "EventName": "UNC_C_RING_BOUNCES.BL", "PerPkg": "1", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.", @@ -650,7 +650,7 @@ "EventName": "UNC_C_RING_BOUNCES.IV", "PerPkg": "1", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Any", @@ -659,7 +659,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in HSX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity", "UMask": "0xf", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Any", @@ -668,7 +668,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in HSX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity", "UMask": "0xc", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Down", @@ -677,7 +677,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in HSX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters for Down polarity", "UMask": "0xcc", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Any", @@ -686,7 +686,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in HSX Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "UNC_C_RING_SINK_STARVED.AD", @@ -694,7 +694,7 @@ "EventName": "UNC_C_RING_SINK_STARVED.AD", "PerPkg": "1", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "UNC_C_RING_SINK_STARVED.AK", @@ -702,7 +702,7 @@ "EventName": "UNC_C_RING_SINK_STARVED.AK", "PerPkg": "1", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "UNC_C_RING_SINK_STARVED.BL", @@ -710,7 +710,7 @@ "EventName": "UNC_C_RING_SINK_STARVED.BL", "PerPkg": "1", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "UNC_C_RING_SINK_STARVED.IV", @@ -718,14 +718,14 @@ "EventName": "UNC_C_RING_SINK_STARVED.IV", "PerPkg": "1", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of cycles the Cbo is actively throttling traffic onto the Ring in order to limit bounce traffic.", "EventCode": "0x7", "EventName": "UNC_C_RING_SRC_THRTL", "PerPkg": "1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ", @@ -734,7 +734,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally startved and therefore we are blocking the IRQ.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ", @@ -743,7 +743,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IRQ is externally starved and therefore we are blocking the IPQ.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID", @@ -752,7 +752,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; Number of times that the ISMQ Bid.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; PRQ", @@ -761,7 +761,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Allocations; IPQ", @@ -770,7 +770,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Allocations; IRQ", @@ -779,7 +779,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Allocations; IRQ Rejected", @@ -788,7 +788,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Allocations; PRQ", @@ -797,7 +797,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Allocations; PRQ", @@ -806,7 +806,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Internal Starvation Cycles; IPQ", @@ -815,7 +815,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IPQ in Internal Starvation.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Internal Starvation Cycles; IRQ", @@ -824,7 +824,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IRQ in Internal Starvation.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ", @@ -833,7 +833,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the ISMQ in Internal Starvation.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Internal Starvation Cycles; PRQ", @@ -842,7 +842,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; Address Conflict", @@ -851,7 +851,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from an address conflicts. Address conflicts out of the IPQ should be rare. They will generally only occur if two different sockets are sending requests to the same address at the same time. This is a true conflict case, unlike the IPQ Address Conflict which is commonly caused by prefetching characteristics.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; Any Reject", @@ -860,7 +860,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject. TOR rejects from the IPQ can be caused by the Egress being full or Address Conflicts.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; No Egress Credits", @@ -869,7 +869,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from the Egress being full. IPQ requests make use of the AD Egress for regular responses, the BL egress to forward data, and the AK egress to return credits.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; No QPI Credits", @@ -878,7 +878,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; No AD Sbo Credits", @@ -887,7 +887,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; Target Node Filter", @@ -896,7 +896,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; Address Conflict", @@ -905,7 +905,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the IRQ was retried because of an address match in the TOR. In order to maintain coherency, requests to the same address are not allowed to pass each other up in the Cbo. Therefore, if there is an outstanding request to a given address, one cannot issue another request to that address until it is complete. This comes up most commonly with prefetches. Outstanding prefetches occasionally will not complete their memory fetch and a demand request to the same address will then sit in the IRQ and get retried until the prefetch fills the data into the LLC. Therefore, it will not be uncommon to see this case in high bandwidth streaming workloads when the LLC Prefetcher in the core is enabled.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; Any Reject", @@ -914,7 +914,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of IRQ retries that occur. Requests from the IRQ are retried if they are rejected from the TOR pipeline for a variety of reasons. Some of the most common reasons include if the Egress is full, there are no RTIDs, or there is a Physical Address match to another outstanding request.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No Egress Credits", @@ -923,7 +923,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the IRQ was retried because it failed to acquire an entry in the Egress. The egress is the buffer that queues up for allocating onto the ring. IRQ requests can make use of all four rings and all four Egresses. If any of the queues that a given request needs to make use of are full, the request will be retried.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits", @@ -932,7 +932,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO. There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects", @@ -941,7 +941,7 @@ "PerPkg": "1", "PublicDescription": "Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No QPI Credits", @@ -950,7 +950,7 @@ "PerPkg": "1", "PublicDescription": "Number of requests rejects because of lack of QPI Ingress credits. These credits are required in order to send transactions to the QPI agent. Please see the QPI_IGR_CREDITS events for more information.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No RTIDs", @@ -959,7 +959,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that requests from the IRQ were retried because there were no RTIDs available. RTIDs are required after a request misses the LLC and needs to send snoops and/or requests to memory. If there are no RTIDs available, requests will queue up in the IRQ and retry until one becomes available. Note that there are multiple RTID pools for the different sockets. There may be cases where the local RTIDs are all used, but requests destined for remote memory can still acquire an RTID because there are remote RTIDs available. This event does not provide any filtering for this case.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No AD Sbo Credits", @@ -968,7 +968,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an AD packet to the Sbo.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No BL Sbo Credits", @@ -977,7 +977,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the IPQ was retried because of it lacked credits to send an BL packet to the Sbo.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; Target Node Filter", @@ -986,7 +986,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the IPQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; Any Reject", @@ -995,7 +995,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the total number of times that a request from the ISMQ retried because of a TOR reject. ISMQ requests generally will not need to retry (or at least ISMQ retries are less common than IRQ retries). ISMQ requests will retry if they are not able to acquire a needed Egress credit to get onto the ring, or for cache evictions that need to acquire an RTID. Most ISMQ requests already have an RTID, so eviction retries will be less common here.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; No Egress Credits", @@ -1004,7 +1004,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by a lack of Egress credits. The egress is the buffer that queues up for allocating onto the ring. If any of the Egress queues that a given request needs to make use of are full, the request will be retried.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; No IIO Credits", @@ -1013,7 +1013,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO. There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries", @@ -1022,7 +1022,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; No QPI Credits", @@ -1031,7 +1031,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; No RTIDs", @@ -1040,7 +1040,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by no RTIDs. M-state cache evictions are serviced through the ISMQ, and must acquire an RTID in order to write back to memory. If no RTIDs are available, they will be retried.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries", @@ -1049,7 +1049,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Qualify one of the other subevents by a given RTID destination NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER1.nid.", "UMask": "0x80", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Request Queue Rejects; No AD Sbo Credits", @@ -1058,7 +1058,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an AD packet to the Sbo.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Request Queue Rejects; No BL Sbo Credits", @@ -1067,7 +1067,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the ISMQ was retried because of it lacked credits to send an BL packet to the Sbo.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Request Queue Rejects; Target Node Filter", @@ -1076,7 +1076,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the ISMQ was retried filtered by the Target NodeID as specified in the Cbox's Filter register.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Occupancy; IPQ", @@ -1085,7 +1085,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Occupancy; IRQ", @@ -1094,7 +1094,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Occupancy; IRQ Rejected", @@ -1103,7 +1103,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Occupancy; PRQ Rejects", @@ -1112,7 +1112,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "SBo Credits Acquired; For AD Ring", @@ -1121,7 +1121,7 @@ "PerPkg": "1", "PublicDescription": "Number of Sbo credits acquired in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "SBo Credits Acquired; For BL Ring", @@ -1130,7 +1130,7 @@ "PerPkg": "1", "PublicDescription": "Number of Sbo credits acquired in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "SBo Credits Occupancy; For AD Ring", @@ -1139,7 +1139,7 @@ "PerPkg": "1", "PublicDescription": "Number of Sbo credits in use in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "SBo Credits Occupancy; For BL Ring", @@ -1148,7 +1148,7 @@ "PerPkg": "1", "PublicDescription": "Number of Sbo credits in use in a given cycle, per ring. Each Cbo is assigned an Sbo it can communicate with.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; All", @@ -1157,7 +1157,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Evictions", @@ -1166,7 +1166,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Eviction transactions inserted into the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Local Memory", @@ -1175,7 +1175,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x28", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched", @@ -1184,7 +1184,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisfied by an opcode, inserted into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x21", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Misses to Local Memory", @@ -1193,7 +1193,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x2a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode Matched", @@ -1202,7 +1202,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisfied by an opcode, inserted into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x23", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Miss Opcode Match", @@ -1211,7 +1211,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Misses to Remote Memory", @@ -1220,7 +1220,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x8a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode Matched", @@ -1229,7 +1229,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisfied by an opcode, inserted into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x83", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID Matched", @@ -1238,7 +1238,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x48", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID Matched Evictions", @@ -1247,7 +1247,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction transactions inserted into the TOR.", "UMask": "0x44", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID Matched Miss All", @@ -1256,7 +1256,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.", "UMask": "0x4a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss", @@ -1265,7 +1265,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode.", "UMask": "0x43", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID and Opcode Matched", @@ -1274,7 +1274,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode.", "UMask": "0x41", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID Matched Writebacks", @@ -1283,7 +1283,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transactions inserted into the TOR.", "UMask": "0x50", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Opcode Match", @@ -1292,7 +1292,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Remote Memory", @@ -1301,7 +1301,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x88", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched", @@ -1310,7 +1310,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisfied by an opcode, inserted into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x81", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Writebacks", @@ -1319,7 +1319,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Write transactions inserted into the TOR. This does not include RFO, but actual operations that contain data being sent from the core.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Any", @@ -1328,7 +1328,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All valid TOR entries. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Evictions", @@ -1337,7 +1337,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding eviction transactions in the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Occupancy counter for LLC data reads (demand and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode", @@ -1347,7 +1347,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO.", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy", @@ -1356,7 +1356,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x28", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched", @@ -1365,7 +1365,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisfied by an opcode, in the TOR that are satisfied by locally HOMed memory.", "UMask": "0x21", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Miss All", @@ -1374,7 +1374,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding miss requests in the TOR. 'Miss' means the allocation requires an RTID. This generally means that the request was sent to memory or MMIO.", "UMask": "0xa", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy", @@ -1383,7 +1383,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x2a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcode Matched", @@ -1392,7 +1392,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisfied by an opcode, in the TOR that are satisfied by locally HOMed memory.", "UMask": "0x23", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Miss Opcode Match", @@ -1401,7 +1401,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO.", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy", @@ -1410,7 +1410,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x8a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opcode Matched", @@ -1419,7 +1419,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisfied by an opcode, in the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x83", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID Matched", @@ -1428,7 +1428,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of NID matched outstanding requests in the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x48", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID Matched Evictions", @@ -1437,7 +1437,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding NID matched eviction transactions in the TOR .", "UMask": "0x44", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID Matched", @@ -1446,7 +1446,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID.", "UMask": "0x4a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss", @@ -1455,7 +1455,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID and an opcode.", "UMask": "0x43", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID and Opcode Matched", @@ -1464,7 +1464,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match a NID and an opcode.", "UMask": "0x41", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID Matched Writebacks", @@ -1473,7 +1473,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); NID matched write transactions int the TOR.", "UMask": "0x50", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Opcode Match", @@ -1482,7 +1482,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc).", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy", @@ -1491,7 +1491,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x88", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Remote Memory - Opcode Matched", @@ -1500,7 +1500,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisfied by an opcode, in the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x81", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Writebacks", @@ -1509,7 +1509,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Write transactions in the TOR. This does not include RFO, but actual operations that contain data being sent from the core.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Onto AD Ring", @@ -1517,7 +1517,7 @@ "EventName": "UNC_C_TxR_ADS_USED.AD", "PerPkg": "1", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Onto AK Ring", @@ -1525,7 +1525,7 @@ "EventName": "UNC_C_TxR_ADS_USED.AK", "PerPkg": "1", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Onto BL Ring", @@ -1533,7 +1533,7 @@ "EventName": "UNC_C_TxR_ADS_USED.BL", "PerPkg": "1", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; AD - Cachebo", @@ -1542,7 +1542,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; AD - Corebo", @@ -1551,7 +1551,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AD ring. This is commonly used for outbound requests.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; AK - Cachebo", @@ -1560,7 +1560,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AK ring. This is commonly used for credit returns and GO responses.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; AK - Corebo", @@ -1569,7 +1569,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AK ring. This is commonly used for snoop responses coming from the core and destined for a Cachebo.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; BL - Cacheno", @@ -1578,7 +1578,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the BL ring. This is commonly used to send data from the cache to various destinations.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; BL - Corebo", @@ -1587,7 +1587,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring. This is commonly used for transferring writeback data to the cache.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; IV - Cachebo", @@ -1596,7 +1596,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the IV ring. This is commonly used for snoops to the cores.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Injection Starvation; Onto AD Ring (to core)", @@ -1605,7 +1605,7 @@ "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the core AD egress spent in starvation", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Injection Starvation; Onto AK Ring", @@ -1614,7 +1614,7 @@ "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both AK egresses spent in starvation", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Injection Starvation; Onto BL Ring", @@ -1623,7 +1623,7 @@ "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both BL egresses spent in starvation", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Injection Starvation; Onto IV Ring", @@ -1632,7 +1632,7 @@ "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the cachebo IV egress spent in starvation", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BT Cycles Not Empty", diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/haswellx/uncore-interconnect.json index 15059b17cd19..954e8198c7a5 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/uncore-interconnect.json @@ -6,7 +6,7 @@ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets.", "ScaleUnit": "8Bytes", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Number of data flits transmitted . Derived from unc_q_txl_flits_g0.data", @@ -15,1318 +15,3950 @@ "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets.", "ScaleUnit": "8Bytes", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { - "BriefDescription": "Number of qfclks", - "EventCode": "0x14", - "EventName": "UNC_Q_CLOCKTICKS", + "BriefDescription": "Total Write Cache Occupancy; Any Source", + "EventCode": "0x12", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", "PerPkg": "1", - "PublicDescription": "Counts the number of clocks in the QPI LL. This clock runs at 1/4th the GT/s speed of the QPI link. For example, a 4GT/s link will have qfclk or 1GHz. HSX does not support dynamic link speeds, so this frequency is fixed.", - "Unit": "QPI LL" + "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.", + "UMask": "0x1", + "Unit": "IRP" }, { - "BriefDescription": "Count of CTO Events", - "EventCode": "0x38", - "EventName": "UNC_Q_CTO_COUNT", + "BriefDescription": "Total Write Cache Occupancy; Select Source", + "EventCode": "0x12", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE", "PerPkg": "1", - "PublicDescription": "Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots. If both slots trigger in a given cycle, the event will increment by 2. You can use edge detect to count the number of cases when both events triggered.", - "Unit": "QPI LL" + "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time.", + "UMask": "0x2", + "Unit": "IRP" }, { - "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress Credits", + "BriefDescription": "Clocks in the IRP", + "EventName": "UNC_I_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Number of clocks in the IRP.", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; CLFlush", "EventCode": "0x13", - "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS", + "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits. Had there been enough credits, the spawn would have worked as the RBT bit was set and the RBT tag matched.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x80", + "Unit": "IRP" }, { - "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss", + "BriefDescription": "Coherent Ops; CRd", "EventCode": "0x13", - "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS", + "EventName": "UNC_I_COHERENT_OPS.CRD", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and there weren't enough Egress credits. The valid bit was set.", - "UMask": "0x20", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x2", + "Unit": "IRP" }, { - "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Invalid", + "BriefDescription": "Coherent Ops; DRd", "EventCode": "0x13", - "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT", + "EventName": "UNC_I_COHERENT_OPS.DRD", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits AND the RBT bit was not set, but the RBT tag matched.", - "UMask": "0x8", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x4", + "Unit": "IRP" }, { - "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid", + "BriefDescription": "Coherent Ops; PCIDCAHin5t", "EventCode": "0x13", - "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS", + "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match, the valid bit was not set and there weren't enough Egress credits.", - "UMask": "0x80", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x20", + "Unit": "IRP" }, { - "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss", + "BriefDescription": "Coherent Ops; PCIRdCur", "EventCode": "0x13", - "EventName": "UNC_Q_DIRECT2CORE.FAILURE_MISS", + "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match although the valid bit was set and there were enough Egress credits.", - "UMask": "0x10", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x1", + "Unit": "IRP" }, { - "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Invalid", + "BriefDescription": "Coherent Ops; PCIItoM", "EventCode": "0x13", - "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT", + "EventName": "UNC_I_COHERENT_OPS.PCITOM", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the route-back table (RBT) specified that the transaction should not trigger a direct2core transaction. This is common for IO transactions. There were enough Egress credits and the RBT tag matched but the valid bit was not set.", - "UMask": "0x4", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x10", + "Unit": "IRP" }, { - "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss and Invalid", + "BriefDescription": "Coherent Ops; RFO", "EventCode": "0x13", - "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS", + "EventName": "UNC_I_COHERENT_OPS.RFO", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and the valid bit was not set although there were enough Egress credits.", - "UMask": "0x40", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x8", + "Unit": "IRP" }, { - "BriefDescription": "Direct 2 Core Spawning; Spawn Success", + "BriefDescription": "Coherent Ops; WbMtoI", "EventCode": "0x13", - "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT", + "EventName": "UNC_I_COHERENT_OPS.WBMTOI", "PerPkg": "1", - "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn was successful. There were sufficient credits, the RBT valid bit was set and there was an RBT tag match. The message was marked to spawn direct2core.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x40", + "Unit": "IRP" }, { - "BriefDescription": "Cycles in L1", - "EventCode": "0x12", - "EventName": "UNC_Q_L1_POWER_CYCLES", + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", "PerPkg": "1", - "PublicDescription": "Number of QPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a QPI link. Use edge detect to count the number of instances when the QPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.", - "Unit": "QPI LL" + "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary", + "UMask": "0x10", + "Unit": "IRP" }, { - "BriefDescription": "Cycles in L0p", - "EventCode": "0x10", - "EventName": "UNC_Q_RxL0P_POWER_CYCLES", + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.2ND_RD_INSERT", "PerPkg": "1", - "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.", - "Unit": "QPI LL" + "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary", + "UMask": "0x4", + "Unit": "IRP" }, { - "BriefDescription": "Cycles in L0", - "EventCode": "0xF", - "EventName": "UNC_Q_RxL0_POWER_CYCLES", + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.2ND_WR_INSERT", "PerPkg": "1", - "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", - "Unit": "QPI LL" + "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary", + "UMask": "0x8", + "Unit": "IRP" }, { - "BriefDescription": "Rx Flit Buffer Bypassed", - "EventCode": "0x9", - "EventName": "UNC_Q_RxL_BYPASSED", + "BriefDescription": "Misc Events - Set 0; Fastpath Rejects", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.FAST_REJ", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", - "Unit": "QPI LL" + "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", + "UMask": "0x2", + "Unit": "IRP" }, { - "BriefDescription": "CRC Errors Detected; LinkInit", - "EventCode": "0x3", - "EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT", + "BriefDescription": "Misc Events - Set 0; Fastpath Requests", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.FAST_REQ", "PerPkg": "1", - "PublicDescription": "Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during link initialization.", + "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Requests", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "IRP" }, { - "BriefDescription": "CRC Errors Detected; Normal Operations", - "EventCode": "0x3", - "EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP", + "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.FAST_XFER", "PerPkg": "1", - "PublicDescription": "Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during normal operation.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary", + "UMask": "0x20", + "Unit": "IRP" }, { - "BriefDescription": "VN0 Credit Consumed; DRS", - "EventCode": "0x1E", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS", + "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.PF_ACK_HINT", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the DRS message class.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary", + "UMask": "0x40", + "Unit": "IRP" }, { - "BriefDescription": "VN0 Credit Consumed; HOM", - "EventCode": "0x1E", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM", + "BriefDescription": "Misc Events - Set 0; Prefetch TimeOut", + "EventCode": "0x14", + "EventName": "UNC_I_MISC0.PF_TIMEOUT", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the HOM message class.", - "UMask": "0x8", - "Unit": "QPI LL" + "PublicDescription": "Indicates the fetch for a previous prefetch wasn't accepted by the prefetch. This happens in the case of a prefetch TimeOut", + "UMask": "0x80", + "Unit": "IRP" }, { - "BriefDescription": "VN0 Credit Consumed; NCB", - "EventCode": "0x1E", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB", + "BriefDescription": "Misc Events - Set 1; Data Throttled", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.DATA_THROTTLE", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCB message class.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "IRP throttled switch data", + "UMask": "0x80", + "Unit": "IRP" }, { - "BriefDescription": "VN0 Credit Consumed; NCS", - "EventCode": "0x1E", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS", + "BriefDescription": "Misc Events - Set 1", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.LOST_FWD", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCS message class.", - "UMask": "0x4", - "Unit": "QPI LL" + "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed", + "UMask": "0x10", + "Unit": "IRP" }, { - "BriefDescription": "VN0 Credit Consumed; NDR", - "EventCode": "0x1E", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR", + "BriefDescription": "Misc Events - Set 1; Received Invalid", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NDR message class.", + "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state", "UMask": "0x20", - "Unit": "QPI LL" + "Unit": "IRP" }, { - "BriefDescription": "VN0 Credit Consumed; SNP", - "EventCode": "0x1E", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP", + "BriefDescription": "Misc Events - Set 1; Received Valid", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the SNP message class.", - "UMask": "0x10", - "Unit": "QPI LL" + "PublicDescription": "Secondary received a transfer that did have sufficient MESI state", + "UMask": "0x40", + "Unit": "IRP" }, { - "BriefDescription": "VN1 Credit Consumed; DRS", - "EventCode": "0x39", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS", + "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SLOW_E", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the DRS message class.", + "PublicDescription": "Secondary received a transfer that did have sufficient MESI state", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SLOW_I", + "PerPkg": "1", + "PublicDescription": "Snoop took cacheline ownership before write from data was committed.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "IRP" }, { - "BriefDescription": "VN1 Credit Consumed; HOM", - "EventCode": "0x39", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM", + "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SLOW_M", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the HOM message class.", + "PublicDescription": "Snoop took cacheline ownership before write from data was committed.", "UMask": "0x8", - "Unit": "QPI LL" + "Unit": "IRP" }, { - "BriefDescription": "VN1 Credit Consumed; NCB", - "EventCode": "0x39", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB", + "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line", + "EventCode": "0x15", + "EventName": "UNC_I_MISC1.SLOW_S", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCB message class.", + "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "IRP" }, { - "BriefDescription": "VN1 Credit Consumed; NCS", - "EventCode": "0x39", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS", + "BriefDescription": "AK Ingress Occupancy", + "EventCode": "0xA", + "EventName": "UNC_I_RxR_AK_INSERTS", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCS message class.", - "UMask": "0x4", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of allocations into the AK Ingress. This queue is where the IRP receives responses from R2PCIe (the ring).", + "Unit": "IRP" }, { - "BriefDescription": "VN1 Credit Consumed; NDR", - "EventCode": "0x39", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR", + "BriefDescription": "UNC_I_RxR_BL_DRS_CYCLES_FULL", + "EventCode": "0x4", + "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NDR message class.", - "UMask": "0x20", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" }, { - "BriefDescription": "VN1 Credit Consumed; SNP", - "EventCode": "0x39", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP", + "BriefDescription": "BL Ingress Occupancy - DRS", + "EventCode": "0x1", + "EventName": "UNC_I_RxR_BL_DRS_INSERTS", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the SNP message class.", - "UMask": "0x10", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" }, { - "BriefDescription": "VNA Credit Consumed", - "EventCode": "0x1D", - "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA", + "BriefDescription": "UNC_I_RxR_BL_DRS_OCCUPANCY", + "EventCode": "0x7", + "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", - "Unit": "QPI LL" + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty", - "EventCode": "0xA", - "EventName": "UNC_Q_RxL_CYCLES_NE", + "BriefDescription": "UNC_I_RxR_BL_NCB_CYCLES_FULL", + "EventCode": "0x5", + "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN0", - "EventCode": "0xF", - "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN0", + "BriefDescription": "BL Ingress Occupancy - NCB", + "EventCode": "0x2", + "EventName": "UNC_I_RxR_BL_NCB_INSERTS", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN1", - "EventCode": "0xF", - "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN1", + "BriefDescription": "UNC_I_RxR_BL_NCB_OCCUPANCY", + "EventCode": "0x8", + "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN0", - "EventCode": "0x12", - "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN0", + "BriefDescription": "UNC_I_RxR_BL_NCS_CYCLES_FULL", + "EventCode": "0x6", + "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN1", - "EventCode": "0x12", - "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN1", + "BriefDescription": "BL Ingress Occupancy - NCS", + "EventCode": "0x3", + "EventName": "UNC_I_RxR_BL_NCS_INSERTS", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN0", - "EventCode": "0x10", - "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN0", + "BriefDescription": "UNC_I_RxR_BL_NCS_OCCUPANCY", + "EventCode": "0x9", + "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN1", - "EventCode": "0x10", - "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN1", + "BriefDescription": "Snoop Responses; Hit E or S", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.HIT_ES", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Snoop Responses : Hit E or S", + "UMask": "0x4", + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN0", - "EventCode": "0x11", - "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN0", + "BriefDescription": "Snoop Responses; Hit I", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.HIT_I", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Snoop Responses : Hit I", + "UMask": "0x2", + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN1", - "EventCode": "0x11", - "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN1", + "BriefDescription": "Snoop Responses; Hit M", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.HIT_M", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Snoop Responses : Hit M", + "UMask": "0x8", + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN0", - "EventCode": "0x14", - "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN0", + "BriefDescription": "Snoop Responses; Miss", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.MISS", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only.", + "PublicDescription": "Snoop Responses : Miss", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN1", - "EventCode": "0x14", - "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN1", + "BriefDescription": "Snoop Responses; SnpCode", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.SNPCODE", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Snoop Responses : SnpCode", + "UMask": "0x10", + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN0", - "EventCode": "0x13", - "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN0", + "BriefDescription": "Snoop Responses; SnpData", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.SNPDATA", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Snoop Responses : SnpData", + "UMask": "0x20", + "Unit": "IRP" }, { - "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN1", - "EventCode": "0x13", - "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN1", + "BriefDescription": "Snoop Responses; SnpInv", + "EventCode": "0x17", + "EventName": "UNC_I_SNOOP_RESP.SNPINV", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Snoop Responses : SnpInv", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Atomic", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.ATOMIC", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Other", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.OTHER", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions.", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Read Prefetches", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.RD_PREF", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Reads", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.READS", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Writes", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.WRITES", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Write Prefetches", + "EventCode": "0x16", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of write prefetches.", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "No AD Egress Credit Stalls", + "EventCode": "0x18", + "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.", + "Unit": "IRP" + }, + { + "BriefDescription": "No BL Egress Credit Stalls", + "EventCode": "0x19", + "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "EventCode": "0xE", + "EventName": "UNC_I_TxR_DATA_INSERTS_NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "EventCode": "0xF", + "EventName": "UNC_I_TxR_DATA_INSERTS_NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Request Queue Occupancy", + "EventCode": "0xD", + "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.", + "Unit": "IRP" + }, + { + "BriefDescription": "Number of qfclks", + "EventCode": "0x14", + "EventName": "UNC_Q_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts the number of clocks in the QPI LL. This clock runs at 1/4th the GT/s speed of the QPI link. For example, a 4GT/s link will have qfclk or 1GHz. HSX does not support dynamic link speeds, so this frequency is fixed.", + "Unit": "QPI" + }, + { + "BriefDescription": "Count of CTO Events", + "EventCode": "0x38", + "EventName": "UNC_Q_CTO_COUNT", + "PerPkg": "1", + "PublicDescription": "Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots. If both slots trigger in a given cycle, the event will increment by 2. You can use edge detect to count the number of cases when both events triggered.", + "Unit": "QPI" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress Credits", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits. Had there been enough credits, the spawn would have worked as the RBT bit was set and the RBT tag matched.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and there weren't enough Egress credits. The valid bit was set.", + "UMask": "0x20", + "Unit": "QPI" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Invalid", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits AND the RBT bit was not set, but the RBT tag matched.", + "UMask": "0x8", + "Unit": "QPI" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match, the valid bit was not set and there weren't enough Egress credits.", + "UMask": "0x80", + "Unit": "QPI" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_MISS", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match although the valid bit was set and there were enough Egress credits.", + "UMask": "0x10", + "Unit": "QPI" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Invalid", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the route-back table (RBT) specified that the transaction should not trigger a direct2core transaction. This is common for IO transactions. There were enough Egress credits and the RBT tag matched but the valid bit was not set.", + "UMask": "0x4", + "Unit": "QPI" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss and Invalid", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and the valid bit was not set although there were enough Egress credits.", + "UMask": "0x40", + "Unit": "QPI" + }, + { + "BriefDescription": "Direct 2 Core Spawning; Spawn Success", + "EventCode": "0x13", + "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT", + "PerPkg": "1", + "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn was successful. There were sufficient credits, the RBT valid bit was set and there was an RBT tag match. The message was marked to spawn direct2core.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Cycles in L1", + "EventCode": "0x12", + "EventName": "UNC_Q_L1_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of QPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a QPI link. Use edge detect to count the number of instances when the QPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.", + "Unit": "QPI" + }, + { + "BriefDescription": "Cycles in L0p", + "EventCode": "0x10", + "EventName": "UNC_Q_RxL0P_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.", + "Unit": "QPI" + }, + { + "BriefDescription": "Cycles in L0", + "EventCode": "0xF", + "EventName": "UNC_Q_RxL0_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Bypassed", + "EventCode": "0x9", + "EventName": "UNC_Q_RxL_BYPASSED", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "Unit": "QPI" + }, + { + "BriefDescription": "CRC Errors Detected; LinkInit", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT", + "PerPkg": "1", + "PublicDescription": "Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during link initialization.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "CRC Errors Detected; Normal Operations", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP", + "PerPkg": "1", + "PublicDescription": "Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during normal operation.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "VN0 Credit Consumed; DRS", + "EventCode": "0x1E", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the DRS message class.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "VN0 Credit Consumed; HOM", + "EventCode": "0x1E", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the HOM message class.", + "UMask": "0x8", + "Unit": "QPI" + }, + { + "BriefDescription": "VN0 Credit Consumed; NCB", + "EventCode": "0x1E", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCB message class.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "VN0 Credit Consumed; NCS", + "EventCode": "0x1E", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCS message class.", + "UMask": "0x4", + "Unit": "QPI" + }, + { + "BriefDescription": "VN0 Credit Consumed; NDR", + "EventCode": "0x1E", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NDR message class.", + "UMask": "0x20", + "Unit": "QPI" + }, + { + "BriefDescription": "VN0 Credit Consumed; SNP", + "EventCode": "0x1E", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the SNP message class.", + "UMask": "0x10", + "Unit": "QPI" + }, + { + "BriefDescription": "VN1 Credit Consumed; DRS", + "EventCode": "0x39", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the DRS message class.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "VN1 Credit Consumed; HOM", + "EventCode": "0x39", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the HOM message class.", + "UMask": "0x8", + "Unit": "QPI" + }, + { + "BriefDescription": "VN1 Credit Consumed; NCB", + "EventCode": "0x39", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCB message class.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "VN1 Credit Consumed; NCS", + "EventCode": "0x39", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCS message class.", + "UMask": "0x4", + "Unit": "QPI" + }, + { + "BriefDescription": "VN1 Credit Consumed; NDR", + "EventCode": "0x39", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NDR message class.", + "UMask": "0x20", + "Unit": "QPI" + }, + { + "BriefDescription": "VN1 Credit Consumed; SNP", + "EventCode": "0x39", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the SNP message class.", + "UMask": "0x10", + "Unit": "QPI" + }, + { + "BriefDescription": "VNA Credit Consumed", + "EventCode": "0x1D", + "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty", + "EventCode": "0xA", + "EventName": "UNC_Q_RxL_CYCLES_NE", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN0", + "EventCode": "0xF", + "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN1", + "EventCode": "0xF", + "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN0", + "EventCode": "0x12", + "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN1", + "EventCode": "0x12", + "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN0", + "EventCode": "0x10", + "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN1", + "EventCode": "0x10", + "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN0", + "EventCode": "0x11", + "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN1", + "EventCode": "0x11", + "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN0", + "EventCode": "0x14", + "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN1", + "EventCode": "0x14", + "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN0", + "EventCode": "0x13", + "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN1", + "EventCode": "0x13", + "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only.", + "UMask": "0x2", + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 0; Idle and Null Flits", "EventCode": "0x1", - "EventName": "UNC_Q_RxL_FLITS_G0.IDLE", + "EventName": "UNC_Q_RxL_FLITS_G0.IDLE", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits received over QPI that do not hold protocol payload. When QPI is not in a power saving state, it continuously transmits flits across the link. When there are no protocol flits to send, it will send IDLE and NULL flits across. These flits sometimes do carry a payload, such as credit returns, but are generally not considered part of the QPI bandwidth.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data.", + "UMask": "0x18", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 1; DRS Data Flits", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).", + "UMask": "0x8", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 1; DRS Header Flits", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.", + "UMask": "0x10", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 1; HOM Flits", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits received over QPI on the home channel.", + "UMask": "0x6", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits received over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.", + "UMask": "0x4", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 1; HOM Request Flits", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request received over QPI on the home channel. This basically counts the number of remote memory requests received over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 1; SNP Flits", + "EventCode": "0x2", + "EventName": "UNC_Q_RxL_FLITS_G1.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits received over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are received on the home channel.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.", + "UMask": "0xc", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Coherent data Rx Flits", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers.", + "UMask": "0x4", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Coherent non-data Rx Flits", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.", + "UMask": "0x8", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits received over QPI. This includes extended headers.", + "UMask": "0x10", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK", + "EventCode": "0x3", + "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations", + "EventCode": "0x8", + "EventName": "UNC_Q_RxL_INSERTS", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN0", + "EventCode": "0x9", + "EventName": "UNC_Q_RxL_INSERTS_DRS.VN0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN1", + "EventCode": "0x9", + "EventName": "UNC_Q_RxL_INSERTS_DRS.VN1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN0", + "EventCode": "0xC", + "EventName": "UNC_Q_RxL_INSERTS_HOM.VN0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN1", + "EventCode": "0xC", + "EventName": "UNC_Q_RxL_INSERTS_HOM.VN1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN0", + "EventCode": "0xA", + "EventName": "UNC_Q_RxL_INSERTS_NCB.VN0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN1", + "EventCode": "0xA", + "EventName": "UNC_Q_RxL_INSERTS_NCB.VN1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN0", + "EventCode": "0xB", + "EventName": "UNC_Q_RxL_INSERTS_NCS.VN0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN1", + "EventCode": "0xB", + "EventName": "UNC_Q_RxL_INSERTS_NCS.VN1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN0", + "EventCode": "0xE", + "EventName": "UNC_Q_RxL_INSERTS_NDR.VN0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN1", + "EventCode": "0xE", + "EventName": "UNC_Q_RxL_INSERTS_NDR.VN1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN0", + "EventCode": "0xD", + "EventName": "UNC_Q_RxL_INSERTS_SNP.VN0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN1", + "EventCode": "0xD", + "EventName": "UNC_Q_RxL_INSERTS_SNP.VN1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets", + "EventCode": "0xB", + "EventName": "UNC_Q_RxL_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - DRS; for VN0", + "EventCode": "0x15", + "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN0", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - DRS; for VN1", + "EventCode": "0x15", + "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - HOM; for VN0", + "EventCode": "0x18", + "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN0", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - HOM; for VN1", + "EventCode": "0x18", + "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - NCB; for VN0", + "EventCode": "0x16", + "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN0", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - NCB; for VN1", + "EventCode": "0x16", + "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - NCS; for VN0", + "EventCode": "0x17", + "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN0", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - NCS; for VN1", + "EventCode": "0x17", + "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - NDR; for VN0", + "EventCode": "0x1A", + "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN0", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - NDR; for VN1", + "EventCode": "0x1A", + "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - SNP; for VN0", + "EventCode": "0x19", + "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN0", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "RxQ Occupancy - SNP; for VN1", + "EventCode": "0x19", + "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - HOM", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_DRS", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - DRS", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_HOM", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x8", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - SNP", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCB", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NDR", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCS", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x4", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCS", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NDR", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x20", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCB", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_SNP", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x10", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; Egress Credits", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet because there were insufficient BGF credits. For details on a message class granularity, use the Egress Credit Occupancy events.", + "UMask": "0x40", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN0; GV", + "EventCode": "0x35", + "EventName": "UNC_Q_RxL_STALLS_VN0.GV", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled because a GV transition (frequency transition) was taking place.", + "UMask": "0x80", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - HOM", + "EventCode": "0x3A", + "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_DRS", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - DRS", + "EventCode": "0x3A", + "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_HOM", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x8", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - SNP", + "EventCode": "0x3A", + "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCB", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NDR", + "EventCode": "0x3A", + "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCS", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x4", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCS", + "EventCode": "0x3A", + "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NDR", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x20", + "Unit": "QPI" + }, + { + "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCB", + "EventCode": "0x3A", + "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_SNP", + "PerPkg": "1", + "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "UMask": "0x10", + "Unit": "QPI" + }, + { + "BriefDescription": "Cycles in L0p", + "EventCode": "0xD", + "EventName": "UNC_Q_TxL0P_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.", + "Unit": "QPI" + }, + { + "BriefDescription": "Cycles in L0", + "EventCode": "0xC", + "EventName": "UNC_Q_TxL0_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", + "Unit": "QPI" + }, + { + "BriefDescription": "Tx Flit Buffer Bypassed", + "EventCode": "0x5", + "EventName": "UNC_Q_TxL_BYPASSED", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.", + "Unit": "QPI" + }, + { + "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full", + "EventCode": "0x2", + "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL", + "PerPkg": "1", + "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is almost full, we block some but not all packets.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full", + "EventCode": "0x2", + "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL", + "PerPkg": "1", + "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is totally full, we are not allowed to send any packets.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Tx Flit Buffer Cycles not Empty", + "EventCode": "0x6", + "EventName": "UNC_Q_TxL_CYCLES_NE", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits", + "EventName": "UNC_Q_TxL_FLITS_G0.DATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits", + "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets.", + "UMask": "0x4", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)", + "EventName": "UNC_Q_TxL_FLITS_G1.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency.", + "UMask": "0x18", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits", + "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).", + "UMask": "0x8", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits", + "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.", + "UMask": "0x10", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 1; HOM Flits", + "EventName": "UNC_Q_TxL_FLITS_G1.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits transmitted over QPI on the home channel.", + "UMask": "0x6", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits", + "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits transmitted over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.", + "UMask": "0x4", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits", + "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request transmitted over QPI on the home channel. This basically counts the number of remote memory requests transmitted over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 1; SNP Flits", + "EventName": "UNC_Q_TxL_FLITS_G1.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits transmitted over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are transmitted on the home channel.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.", + "UMask": "0xc", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Coherent data Tx Flits", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers.", + "UMask": "0x4", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Coherent non-data Tx Flits", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.", + "UMask": "0x8", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits transmitted over QPI. This includes extended headers.", + "UMask": "0x10", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK", + "EventCode": "0x1", + "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK", + "PerPkg": "1", + "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "Tx Flit Buffer Allocations", + "EventCode": "0x4", + "EventName": "UNC_Q_TxL_INSERTS", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the QPI Tx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", + "Unit": "QPI" + }, + { + "BriefDescription": "Tx Flit Buffer Occupancy", + "EventCode": "0x7", + "EventName": "UNC_Q_TxL_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of flits in the TxQ. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN0", + "EventCode": "0x26", + "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0", + "PerPkg": "1", + "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN1", + "EventCode": "0x26", + "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1", + "PerPkg": "1", + "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN0", + "EventCode": "0x22", + "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN1", + "EventCode": "0x22", + "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0", + "EventCode": "0x28", + "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0", + "PerPkg": "1", + "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1", + "EventCode": "0x28", + "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1", + "PerPkg": "1", + "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0", + "EventCode": "0x24", + "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1", + "EventCode": "0x24", + "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN0", + "EventCode": "0x27", + "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0", + "PerPkg": "1", + "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN1", + "EventCode": "0x27", + "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1", + "PerPkg": "1", + "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN0", + "EventCode": "0x23", + "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for Snoop messages on AD.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN1", + "EventCode": "0x23", + "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for Snoop messages on AD.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR", + "EventCode": "0x29", + "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR", + "EventCode": "0x25", + "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. Local NDR message class to AK Egress.", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN0", + "EventCode": "0x2A", + "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN1", + "EventCode": "0x2A", + "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for Shared VN", + "EventCode": "0x2A", + "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.", + "UMask": "0x4", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN0", + "EventCode": "0x1F", + "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN1", + "EventCode": "0x1F", + "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for Shared VN", + "EventCode": "0x1F", + "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.", + "UMask": "0x4", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN0", + "EventCode": "0x2B", + "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN1", + "EventCode": "0x2B", + "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN0", + "EventCode": "0x20", + "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN1", + "EventCode": "0x20", + "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN0", + "EventCode": "0x2C", + "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN1", + "EventCode": "0x2C", + "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1", + "PerPkg": "1", + "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN0", + "EventCode": "0x21", + "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress.", + "UMask": "0x1", + "Unit": "QPI" + }, + { + "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN1", + "EventCode": "0x21", + "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1", + "PerPkg": "1", + "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress.", + "UMask": "0x2", + "Unit": "QPI" + }, + { + "BriefDescription": "VNA Credits Returned", + "EventCode": "0x1C", + "EventName": "UNC_Q_VNA_CREDIT_RETURNS", + "PerPkg": "1", + "PublicDescription": "Number of VNA credits returned.", + "Unit": "QPI" + }, + { + "BriefDescription": "VNA Credits Pending Return - Occupancy", + "EventCode": "0x1B", + "EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.", + "Unit": "QPI" + }, + { + "BriefDescription": "Number of uclks in domain", + "EventCode": "0x1", + "EventName": "UNC_R3_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts the number of uclks in the QPI uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles.", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x1F", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 10", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x1F", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 11", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x1F", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 12", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x1F", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 13", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x1F", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14_16", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 14&16", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x1F", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 8", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x1F", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 9", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x1F", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO_15_17", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 15&17", + "UMask": "0x80", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x22", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 0", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x22", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x22", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 2", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x22", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 3", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x22", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 4", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x22", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 5", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x22", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 6", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x22", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 7", + "UMask": "0x80", + "Unit": "R3QPI" + }, + { + "BriefDescription": "HA/R2 AD Credits Empty", + "EventCode": "0x2D", + "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0", + "PerPkg": "1", + "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA0", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "HA/R2 AD Credits Empty", + "EventCode": "0x2D", + "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1", + "PerPkg": "1", + "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "HA/R2 AD Credits Empty", + "EventCode": "0x2D", + "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB", + "PerPkg": "1", + "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCB Messages", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "HA/R2 AD Credits Empty", + "EventCode": "0x2D", + "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS", + "PerPkg": "1", + "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCS Messages", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "IOT Backpressure", + "EventCode": "0xB", + "EventName": "UNC_R3_IOT_BACKPRESSURE.HUB", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "IOT Backpressure", + "EventCode": "0xB", + "EventName": "UNC_R3_IOT_BACKPRESSURE.SAT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "IOT Common Trigger Sequencer - Hi", + "EventCode": "0xD", + "EventName": "UNC_R3_IOT_CTS_HI.CTS2", + "PerPkg": "1", + "PublicDescription": "Debug Mask/Match Tie-Ins", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "IOT Common Trigger Sequencer - Hi", + "EventCode": "0xD", + "EventName": "UNC_R3_IOT_CTS_HI.CTS3", + "PerPkg": "1", + "PublicDescription": "Debug Mask/Match Tie-Ins", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "EventCode": "0xC", + "EventName": "UNC_R3_IOT_CTS_LO.CTS0", + "PerPkg": "1", + "PublicDescription": "Debug Mask/Match Tie-Ins", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "EventCode": "0xC", + "EventName": "UNC_R3_IOT_CTS_LO.CTS1", + "PerPkg": "1", + "PublicDescription": "Debug Mask/Match Tie-Ins", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "EventCode": "0x20", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 HOM Messages", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "EventCode": "0x20", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 NDR Messages", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "EventCode": "0x20", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 SNP Messages", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "EventCode": "0x20", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 HOM Messages", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "EventCode": "0x20", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 NDR Messages", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "EventCode": "0x20", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 SNP Messages", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "EventCode": "0x20", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VNA", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "EventCode": "0x21", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 HOM Messages", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "EventCode": "0x21", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 NDR Messages", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "EventCode": "0x21", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 SNP Messages", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "EventCode": "0x21", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VNA", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "EventCode": "0x2E", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 HOM Messages", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "EventCode": "0x2E", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 NDR Messages", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "EventCode": "0x2E", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 SNP Messages", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "EventCode": "0x2E", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VNA", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "EventCode": "0x2F", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 HOM Messages", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "EventCode": "0x2F", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 NDR Messages", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "EventCode": "0x2F", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 SNP Messages", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "EventCode": "0x2F", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 HOM Messages", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "EventCode": "0x2F", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 NDR Messages", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "EventCode": "0x2F", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 SNP Messages", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "EventCode": "0x2F", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VNA", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Counterclockwise", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xc", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Clockwise", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x3", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Clockwise and Even", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Counterclockwise", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xc", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Clockwise", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x3", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Clockwise and Even", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Counterclockwise", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xc", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Clockwise", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x3", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Clockwise and Even", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 IV Ring in Use; Any", + "EventCode": "0xA", + "EventName": "UNC_R3_RING_IV_USED.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", + "UMask": "0xf", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 IV Ring in Use; Clockwise", + "EventCode": "0xA", + "EventName": "UNC_R3_RING_IV_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", + "UMask": "0x3", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ring Stop Starved; AK", + "EventCode": "0xE", + "EventName": "UNC_R3_RING_SINK_STARVED.AK", + "PerPkg": "1", + "PublicDescription": "Number of cycles the ringstop is in starvation (per ring)", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; HOM", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NDR", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.NDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; SNP", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Cycles Not Empty; DRS", + "EventCode": "0x14", + "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Cycles Not Empty; HOM", + "EventCode": "0x14", + "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Cycles Not Empty; NCB", + "EventCode": "0x14", + "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Cycles Not Empty; NCS", + "EventCode": "0x14", + "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Cycles Not Empty; NDR", + "EventCode": "0x14", + "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Cycles Not Empty; SNP", + "EventCode": "0x14", + "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; DRS", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; HOM", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; NCB", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; NCS", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; NDR", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.NDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; SNP", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Allocations; DRS", + "EventCode": "0x15", + "EventName": "UNC_R3_RxR_INSERTS_VN1.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Allocations; HOM", + "EventCode": "0x15", + "EventName": "UNC_R3_RxR_INSERTS_VN1.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Allocations; NCB", + "EventCode": "0x15", + "EventName": "UNC_R3_RxR_INSERTS_VN1.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Allocations; NCS", + "EventCode": "0x15", + "EventName": "UNC_R3_RxR_INSERTS_VN1.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Allocations; NDR", + "EventCode": "0x15", + "EventName": "UNC_R3_RxR_INSERTS_VN1.NDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Allocations; SNP", + "EventCode": "0x15", + "EventName": "UNC_R3_RxR_INSERTS_VN1.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Occupancy Accumulator; DRS", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.DRS", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Occupancy Accumulator; HOM", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.HOM", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; HOM Ingress Queue", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Occupancy Accumulator; NCB", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCB", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NCB Ingress Queue", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Occupancy Accumulator; NCS", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCS", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NCS Ingress Queue", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Occupancy Accumulator; NDR", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NDR", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NDR Ingress Queue", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Ingress Occupancy Accumulator; SNP", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.SNP", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; SNP Ingress Queue", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "SBo0 Credits Acquired; For AD Ring", + "EventCode": "0x28", + "EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.AD", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "SBo0 Credits Acquired; For BL Ring", + "EventCode": "0x28", + "EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.BL", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "SBo0 Credits Occupancy; For AD Ring", + "EventCode": "0x2A", + "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.AD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits received over QPI that do not hold protocol payload. When QPI is not in a power saving state, it continuously transmits flits across the link. When there are no protocol flits to send, it will send IDLE and NULL flits across. These flits sometimes do carry a payload, such as credit returns, but are generally not considered part of the QPI bandwidth.", + "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)", - "EventCode": "0x2", - "EventName": "UNC_Q_RxL_FLITS_G1.DRS", + "BriefDescription": "SBo0 Credits Occupancy; For BL Ring", + "EventCode": "0x2A", + "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.BL", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data.", - "UMask": "0x18", - "Unit": "QPI LL" + "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.", + "UMask": "0x2", + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 1; DRS Data Flits", - "EventCode": "0x2", - "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA", + "BriefDescription": "SBo1 Credits Acquired; For AD Ring", + "EventCode": "0x29", + "EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.AD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).", - "UMask": "0x8", - "Unit": "QPI LL" + "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.", + "UMask": "0x1", + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 1; DRS Header Flits", - "EventCode": "0x2", - "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA", + "BriefDescription": "SBo1 Credits Acquired; For BL Ring", + "EventCode": "0x29", + "EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.BL", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.", - "UMask": "0x10", - "Unit": "QPI LL" + "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.", + "UMask": "0x2", + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 1; HOM Flits", - "EventCode": "0x2", - "EventName": "UNC_Q_RxL_FLITS_G1.HOM", + "BriefDescription": "SBo1 Credits Occupancy; For AD Ring", + "EventCode": "0x2B", + "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.AD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits received over QPI on the home channel.", - "UMask": "0x6", - "Unit": "QPI LL" + "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.", + "UMask": "0x1", + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits", - "EventCode": "0x2", - "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ", + "BriefDescription": "SBo1 Credits Occupancy; For BL Ring", + "EventCode": "0x2B", + "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.BL", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits received over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.", + "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring", + "EventCode": "0x2C", + "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_AD", + "PerPkg": "1", + "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring", + "EventCode": "0x2C", + "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_BL", + "PerPkg": "1", + "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 1; HOM Request Flits", - "EventCode": "0x2", - "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ", + "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring", + "EventCode": "0x2C", + "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_AD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request received over QPI on the home channel. This basically counts the number of remote memory requests received over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.", + "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 1; SNP Flits", - "EventCode": "0x2", - "EventName": "UNC_Q_RxL_FLITS_G1.SNP", + "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring", + "EventCode": "0x2C", + "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_BL", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits received over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are received on the home channel.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", + "UMask": "0x8", + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits", - "EventCode": "0x3", - "EventName": "UNC_Q_RxL_FLITS_G2.NCB", + "BriefDescription": "Egress CCW NACK; AD CCW", + "EventCode": "0x26", + "EventName": "UNC_R3_TxR_NACK.DN_AD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.", - "UMask": "0xc", - "Unit": "QPI LL" + "PublicDescription": "AD CounterClockwise Egress Queue", + "UMask": "0x1", + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 2; Non-Coherent data Rx Flits", - "EventCode": "0x3", - "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA", + "BriefDescription": "Egress CCW NACK; AK CCW", + "EventCode": "0x26", + "EventName": "UNC_R3_TxR_NACK.DN_AK", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers.", + "PublicDescription": "AK CounterClockwise Egress Queue", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 2; Non-Coherent non-data Rx Flits", - "EventCode": "0x3", - "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA", + "BriefDescription": "Egress CCW NACK; BL CCW", + "EventCode": "0x26", + "EventName": "UNC_R3_TxR_NACK.DN_BL", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.", + "PublicDescription": "BL CounterClockwise Egress Queue", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Egress CCW NACK; AK CCW", + "EventCode": "0x26", + "EventName": "UNC_R3_TxR_NACK.UP_AD", + "PerPkg": "1", + "PublicDescription": "BL CounterClockwise Egress Queue", "UMask": "0x8", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits", - "EventCode": "0x3", - "EventName": "UNC_Q_RxL_FLITS_G2.NCS", + "BriefDescription": "Egress CCW NACK; BL CW", + "EventCode": "0x26", + "EventName": "UNC_R3_TxR_NACK.UP_AK", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits received over QPI. This includes extended headers.", + "PublicDescription": "AD Clockwise Egress Queue", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Egress CCW NACK; BL CCW", + "EventCode": "0x26", + "EventName": "UNC_R3_TxR_NACK.UP_BL", + "PerPkg": "1", + "PublicDescription": "AD CounterClockwise Egress Queue", "UMask": "0x10", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD", - "EventCode": "0x3", - "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD", + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.", + "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK", - "EventCode": "0x3", - "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK", + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Message Class", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB", "PerPkg": "1", - "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.", + "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Message Class", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Rx Flit Buffer Allocations", - "EventCode": "0x8", - "EventName": "UNC_Q_RxL_INSERTS", + "BriefDescription": "VN0 Credit Used; DRS Message Class", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.DRS", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", - "Unit": "QPI LL" + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", + "UMask": "0x8", + "Unit": "R3QPI" }, { - "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN0", - "EventCode": "0x9", - "EventName": "UNC_Q_RxL_INSERTS_DRS.VN0", + "BriefDescription": "VN0 Credit Used; HOM Message Class", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.HOM", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits.", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN1", - "EventCode": "0x9", - "EventName": "UNC_Q_RxL_INSERTS_DRS.VN1", + "BriefDescription": "VN0 Credit Used; NCB Message Class", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.NCB", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits.", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; NCS Message Class", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; NDR Message Class", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.NDR", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; SNP Message Class", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN0", - "EventCode": "0xC", - "EventName": "UNC_Q_RxL_INSERTS_HOM.VN0", + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Message Class", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits.", + "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Message Class", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN1", - "EventCode": "0xC", - "EventName": "UNC_Q_RxL_INSERTS_HOM.VN1", + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCB Message Class", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCB", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits.", + "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCS Message Class", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCS", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Message Class", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Message Class", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN0", - "EventCode": "0xA", - "EventName": "UNC_Q_RxL_INSERTS_NCB.VN0", + "BriefDescription": "VN1 Credit Used; DRS Message Class", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.DRS", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits.", + "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; HOM Message Class", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.HOM", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN1", - "EventCode": "0xA", - "EventName": "UNC_Q_RxL_INSERTS_NCB.VN1", + "BriefDescription": "VN1 Credit Used; NCB Message Class", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.NCB", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits.", + "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; NCS Message Class", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; NDR Message Class", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.NDR", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; SNP Message Class", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN0", - "EventCode": "0xB", - "EventName": "UNC_Q_RxL_INSERTS_NCS.VN0", + "BriefDescription": "VNA credit Acquisitions; HOM Message Class", + "EventCode": "0x33", + "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits.", + "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN1", - "EventCode": "0xB", - "EventName": "UNC_Q_RxL_INSERTS_NCS.VN1", + "BriefDescription": "VNA credit Acquisitions; HOM Message Class", + "EventCode": "0x33", + "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits.", + "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; DRS Message Class", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; HOM Message Class", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; NCB Message Class", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; NCS Message Class", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Standard (NCS).", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; NDR Message Class", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; SNP Message Class", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "R3QPI" }, { - "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN0", - "EventCode": "0xE", - "EventName": "UNC_Q_RxL_INSERTS_NDR.VN0", + "BriefDescription": "Bounce Control", + "EventCode": "0xA", + "EventName": "UNC_S_BOUNCE_CONTROL", + "PerPkg": "1", + "Unit": "SBOX" + }, + { + "BriefDescription": "Uncore Clocks", + "EventName": "UNC_S_CLOCKTICKS", + "PerPkg": "1", + "Unit": "SBOX" + }, + { + "BriefDescription": "FaST wire asserted", + "EventCode": "0x9", + "EventName": "UNC_S_FAST_ASSERTED", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", + "Unit": "SBOX" + }, + { + "BriefDescription": "AD Ring In Use; Down", + "EventCode": "0x1B", + "EventName": "UNC_S_RING_AD_USED.DOWN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0xc", + "Unit": "SBOX" + }, + { + "BriefDescription": "AD Ring In Use; Down and Event", + "EventCode": "0x1B", + "EventName": "UNC_S_RING_AD_USED.DOWN_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.", + "UMask": "0x4", + "Unit": "SBOX" + }, + { + "BriefDescription": "AD Ring In Use; Down and Odd", + "EventCode": "0x1B", + "EventName": "UNC_S_RING_AD_USED.DOWN_ODD", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.", + "UMask": "0x8", + "Unit": "SBOX" }, { - "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN1", - "EventCode": "0xE", - "EventName": "UNC_Q_RxL_INSERTS_NDR.VN1", + "BriefDescription": "AD Ring In Use; Up", + "EventCode": "0x1B", + "EventName": "UNC_S_RING_AD_USED.UP", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x3", + "Unit": "SBOX" }, { - "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN0", - "EventCode": "0xD", - "EventName": "UNC_Q_RxL_INSERTS_SNP.VN0", + "BriefDescription": "AD Ring In Use; Up and Even", + "EventCode": "0x1B", + "EventName": "UNC_S_RING_AD_USED.UP_EVEN", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits.", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN1", - "EventCode": "0xD", - "EventName": "UNC_Q_RxL_INSERTS_SNP.VN1", + "BriefDescription": "AD Ring In Use; Up and Odd", + "EventCode": "0x1B", + "EventName": "UNC_S_RING_AD_USED.UP_ODD", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits.", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - All Packets", - "EventCode": "0xB", - "EventName": "UNC_Q_RxL_OCCUPANCY", + "BriefDescription": "AK Ring In Use; Down", + "EventCode": "0x1C", + "EventName": "UNC_S_RING_AK_USED.DOWN", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0xc", + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - DRS; for VN0", - "EventCode": "0x15", - "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN0", + "BriefDescription": "AK Ring In Use; Down and Event", + "EventCode": "0x1C", + "EventName": "UNC_S_RING_AK_USED.DOWN_EVEN", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.", + "UMask": "0x4", + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - DRS; for VN1", - "EventCode": "0x15", - "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN1", + "BriefDescription": "AK Ring In Use; Down and Odd", + "EventCode": "0x1C", + "EventName": "UNC_S_RING_AK_USED.DOWN_ODD", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.", + "UMask": "0x8", + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - HOM; for VN0", - "EventCode": "0x18", - "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN0", + "BriefDescription": "AK Ring In Use; Up", + "EventCode": "0x1C", + "EventName": "UNC_S_RING_AK_USED.UP", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only.", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x3", + "Unit": "SBOX" + }, + { + "BriefDescription": "AK Ring In Use; Up and Even", + "EventCode": "0x1C", + "EventName": "UNC_S_RING_AK_USED.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - HOM; for VN1", - "EventCode": "0x18", - "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN1", + "BriefDescription": "AK Ring In Use; Up and Odd", + "EventCode": "0x1C", + "EventName": "UNC_S_RING_AK_USED.UP_ODD", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only.", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - NCB; for VN0", - "EventCode": "0x16", - "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN0", + "BriefDescription": "BL Ring in Use; Down", + "EventCode": "0x1D", + "EventName": "UNC_S_RING_BL_USED.DOWN", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0xc", + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - NCB; for VN1", - "EventCode": "0x16", - "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN1", + "BriefDescription": "BL Ring in Use; Down and Event", + "EventCode": "0x1D", + "EventName": "UNC_S_RING_BL_USED.DOWN_EVEN", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.", + "UMask": "0x4", + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - NCS; for VN0", - "EventCode": "0x17", - "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN0", + "BriefDescription": "BL Ring in Use; Down and Odd", + "EventCode": "0x1D", + "EventName": "UNC_S_RING_BL_USED.DOWN_ODD", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.", + "UMask": "0x8", + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - NCS; for VN1", - "EventCode": "0x17", - "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN1", + "BriefDescription": "BL Ring in Use; Up", + "EventCode": "0x1D", + "EventName": "UNC_S_RING_BL_USED.UP", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x3", + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - NDR; for VN0", - "EventCode": "0x1A", - "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN0", + "BriefDescription": "BL Ring in Use; Up and Even", + "EventCode": "0x1D", + "EventName": "UNC_S_RING_BL_USED.UP_EVEN", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only.", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - NDR; for VN1", - "EventCode": "0x1A", - "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN1", + "BriefDescription": "BL Ring in Use; Up and Odd", + "EventCode": "0x1D", + "EventName": "UNC_S_RING_BL_USED.UP_ODD", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only.", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - SNP; for VN0", - "EventCode": "0x19", - "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN0", + "BriefDescription": "Number of LLC responses that bounced on the Ring.", + "EventCode": "0x5", + "EventName": "UNC_S_RING_BOUNCES.AD_CACHE", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "RxQ Occupancy - SNP; for VN1", - "EventCode": "0x19", - "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN1", + "BriefDescription": "Number of LLC responses that bounced on the Ring.; Acknowledgements to core", + "EventCode": "0x5", + "EventName": "UNC_S_RING_BOUNCES.AK_CORE", "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - HOM", - "EventCode": "0x35", - "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_DRS", + "BriefDescription": "Number of LLC responses that bounced on the Ring.; Data Responses to core", + "EventCode": "0x5", + "EventName": "UNC_S_RING_BOUNCES.BL_CORE", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", - "UMask": "0x1", - "Unit": "QPI LL" + "UMask": "0x4", + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - DRS", - "EventCode": "0x35", - "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_HOM", + "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.", + "EventCode": "0x5", + "EventName": "UNC_S_RING_BOUNCES.IV_CORE", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", "UMask": "0x8", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - SNP", - "EventCode": "0x35", - "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCB", + "BriefDescription": "BL Ring in Use; Any", + "EventCode": "0x1E", + "EventName": "UNC_S_RING_IV_USED.DN", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. There is only 1 IV ring in HSX. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity", + "UMask": "0xc", + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NDR", - "EventCode": "0x35", - "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCS", + "BriefDescription": "BL Ring in Use; Any", + "EventCode": "0x1E", + "EventName": "UNC_S_RING_IV_USED.UP", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", - "UMask": "0x4", - "Unit": "QPI LL" + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. There is only 1 IV ring in HSX. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity", + "UMask": "0x3", + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCS", - "EventCode": "0x35", - "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NDR", + "BriefDescription": "UNC_S_RING_SINK_STARVED.AD_CACHE", + "EventCode": "0x6", + "EventName": "UNC_S_RING_SINK_STARVED.AD_CACHE", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", - "UMask": "0x20", - "Unit": "QPI LL" + "UMask": "0x1", + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCB", - "EventCode": "0x35", - "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_SNP", + "BriefDescription": "UNC_S_RING_SINK_STARVED.AK_CORE", + "EventCode": "0x6", + "EventName": "UNC_S_RING_SINK_STARVED.AK_CORE", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", - "UMask": "0x10", - "Unit": "QPI LL" + "UMask": "0x2", + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN0; Egress Credits", - "EventCode": "0x35", - "EventName": "UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS", + "BriefDescription": "UNC_S_RING_SINK_STARVED.BL_CORE", + "EventCode": "0x6", + "EventName": "UNC_S_RING_SINK_STARVED.BL_CORE", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet because there were insufficient BGF credits. For details on a message class granularity, use the Egress Credit Occupancy events.", - "UMask": "0x40", - "Unit": "QPI LL" + "UMask": "0x4", + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN0; GV", - "EventCode": "0x35", - "EventName": "UNC_Q_RxL_STALLS_VN0.GV", + "BriefDescription": "UNC_S_RING_SINK_STARVED.IV_CORE", + "EventCode": "0x6", + "EventName": "UNC_S_RING_SINK_STARVED.IV_CORE", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled because a GV transition (frequency transition) was taking place.", - "UMask": "0x80", - "Unit": "QPI LL" + "UMask": "0x8", + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - HOM", - "EventCode": "0x3A", - "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_DRS", + "BriefDescription": "Injection Starvation; AD - Bounces", + "EventCode": "0x15", + "EventName": "UNC_S_RxR_BUSY_STARVED.AD_BNC", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.", + "UMask": "0x2", + "Unit": "SBOX" + }, + { + "BriefDescription": "Injection Starvation; AD - Credits", + "EventCode": "0x15", + "EventName": "UNC_S_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - DRS", - "EventCode": "0x3A", - "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_HOM", + "BriefDescription": "Injection Starvation; BL - Bounces", + "EventCode": "0x15", + "EventName": "UNC_S_RxR_BUSY_STARVED.BL_BNC", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.", "UMask": "0x8", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - SNP", - "EventCode": "0x3A", - "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCB", + "BriefDescription": "Injection Starvation; BL - Credits", + "EventCode": "0x15", + "EventName": "UNC_S_RxR_BUSY_STARVED.BL_CRD", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.", + "UMask": "0x4", + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NDR", - "EventCode": "0x3A", - "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCS", + "BriefDescription": "Bypass; AD - Bounces", + "EventCode": "0x12", + "EventName": "UNC_S_RxR_BYPASS.AD_BNC", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", - "UMask": "0x4", - "Unit": "QPI LL" + "PublicDescription": "Bypass the Sbo Ingress.", + "UMask": "0x2", + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCS", - "EventCode": "0x3A", - "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NDR", + "BriefDescription": "Bypass; AD - Credits", + "EventCode": "0x12", + "EventName": "UNC_S_RxR_BYPASS.AD_CRD", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", - "UMask": "0x20", - "Unit": "QPI LL" + "PublicDescription": "Bypass the Sbo Ingress.", + "UMask": "0x1", + "Unit": "SBOX" }, { - "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCB", - "EventCode": "0x3A", - "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_SNP", + "BriefDescription": "Bypass; AK", + "EventCode": "0x12", + "EventName": "UNC_S_RxR_BYPASS.AK", "PerPkg": "1", - "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", + "PublicDescription": "Bypass the Sbo Ingress.", "UMask": "0x10", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Cycles in L0p", - "EventCode": "0xD", - "EventName": "UNC_Q_TxL0P_POWER_CYCLES", + "BriefDescription": "Bypass; BL - Bounces", + "EventCode": "0x12", + "EventName": "UNC_S_RxR_BYPASS.BL_BNC", "PerPkg": "1", - "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.", - "Unit": "QPI LL" + "PublicDescription": "Bypass the Sbo Ingress.", + "UMask": "0x8", + "Unit": "SBOX" }, { - "BriefDescription": "Cycles in L0", - "EventCode": "0xC", - "EventName": "UNC_Q_TxL0_POWER_CYCLES", + "BriefDescription": "Bypass; BL - Credits", + "EventCode": "0x12", + "EventName": "UNC_S_RxR_BYPASS.BL_CRD", "PerPkg": "1", - "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", - "Unit": "QPI LL" + "PublicDescription": "Bypass the Sbo Ingress.", + "UMask": "0x4", + "Unit": "SBOX" }, { - "BriefDescription": "Tx Flit Buffer Bypassed", - "EventCode": "0x5", - "EventName": "UNC_Q_TxL_BYPASSED", + "BriefDescription": "Bypass; IV", + "EventCode": "0x12", + "EventName": "UNC_S_RxR_BYPASS.IV", "PerPkg": "1", - "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.", - "Unit": "QPI LL" + "PublicDescription": "Bypass the Sbo Ingress.", + "UMask": "0x20", + "Unit": "SBOX" }, { - "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full", - "EventCode": "0x2", - "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL", + "BriefDescription": "Injection Starvation; AD - Bounces", + "EventCode": "0x14", + "EventName": "UNC_S_RxR_CRD_STARVED.AD_BNC", "PerPkg": "1", - "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is almost full, we block some but not all packets.", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full", - "EventCode": "0x2", - "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL", + "BriefDescription": "Injection Starvation; AD - Credits", + "EventCode": "0x14", + "EventName": "UNC_S_RxR_CRD_STARVED.AD_CRD", "PerPkg": "1", - "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is totally full, we are not allowed to send any packets.", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Tx Flit Buffer Cycles not Empty", - "EventCode": "0x6", - "EventName": "UNC_Q_TxL_CYCLES_NE", + "BriefDescription": "Injection Starvation; AK", + "EventCode": "0x14", + "EventName": "UNC_S_RxR_CRD_STARVED.AK", "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.", - "Unit": "QPI LL" + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", + "UMask": "0x10", + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits", - "EventName": "UNC_Q_TxL_FLITS_G0.DATA", + "BriefDescription": "Injection Starvation; BL - Bounces", + "EventCode": "0x14", + "EventName": "UNC_S_RxR_CRD_STARVED.BL_BNC", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", + "UMask": "0x8", + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits", - "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA", + "BriefDescription": "Injection Starvation; BL - Credits", + "EventCode": "0x14", + "EventName": "UNC_S_RxR_CRD_STARVED.BL_CRD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets.", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)", - "EventName": "UNC_Q_TxL_FLITS_G1.DRS", + "BriefDescription": "Injection Starvation; IVF Credit", + "EventCode": "0x14", + "EventName": "UNC_S_RxR_CRD_STARVED.IFV", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency.", - "UMask": "0x18", - "Unit": "QPI LL" + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", + "UMask": "0x40", + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits", - "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA", + "BriefDescription": "Injection Starvation; IV", + "EventCode": "0x14", + "EventName": "UNC_S_RxR_CRD_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", + "UMask": "0x20", + "Unit": "SBOX" + }, + { + "BriefDescription": "Ingress Allocations; AD - Bounces", + "EventCode": "0x13", + "EventName": "UNC_S_RxR_INSERTS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", + "UMask": "0x2", + "Unit": "SBOX" + }, + { + "BriefDescription": "Ingress Allocations; AD - Credits", + "EventCode": "0x13", + "EventName": "UNC_S_RxR_INSERTS.AD_CRD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).", - "UMask": "0x8", - "Unit": "QPI LL" + "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", + "UMask": "0x1", + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits", - "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA", + "BriefDescription": "Ingress Allocations; AK", + "EventCode": "0x13", + "EventName": "UNC_S_RxR_INSERTS.AK", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.", + "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", "UMask": "0x10", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 1; HOM Flits", - "EventName": "UNC_Q_TxL_FLITS_G1.HOM", + "BriefDescription": "Ingress Allocations; BL - Bounces", + "EventCode": "0x13", + "EventName": "UNC_S_RxR_INSERTS.BL_BNC", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits transmitted over QPI on the home channel.", - "UMask": "0x6", - "Unit": "QPI LL" + "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", + "UMask": "0x8", + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits", - "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ", + "BriefDescription": "Ingress Allocations; BL - Credits", + "EventCode": "0x13", + "EventName": "UNC_S_RxR_INSERTS.BL_CRD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits transmitted over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.", + "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits", - "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ", + "BriefDescription": "Ingress Allocations; IV", + "EventCode": "0x13", + "EventName": "UNC_S_RxR_INSERTS.IV", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request transmitted over QPI on the home channel. This basically counts the number of remote memory requests transmitted over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.", + "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", + "UMask": "0x20", + "Unit": "SBOX" + }, + { + "BriefDescription": "Ingress Occupancy; AD - Bounces", + "EventCode": "0x11", + "EventName": "UNC_S_RxR_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 1; SNP Flits", - "EventName": "UNC_Q_TxL_FLITS_G1.SNP", + "BriefDescription": "Ingress Occupancy; AD - Credits", + "EventCode": "0x11", + "EventName": "UNC_S_RxR_OCCUPANCY.AD_CRD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits transmitted over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are transmitted on the home channel.", + "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits", - "EventCode": "0x1", - "EventName": "UNC_Q_TxL_FLITS_G2.NCB", + "BriefDescription": "Ingress Occupancy; AK", + "EventCode": "0x11", + "EventName": "UNC_S_RxR_OCCUPANCY.AK", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.", - "UMask": "0xc", - "Unit": "QPI LL" + "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", + "UMask": "0x10", + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 2; Non-Coherent data Tx Flits", - "EventCode": "0x1", - "EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA", + "BriefDescription": "Ingress Occupancy; BL - Bounces", + "EventCode": "0x11", + "EventName": "UNC_S_RxR_OCCUPANCY.BL_BNC", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers.", - "UMask": "0x4", - "Unit": "QPI LL" + "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", + "UMask": "0x8", + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 2; Non-Coherent non-data Tx Flits", - "EventCode": "0x1", - "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA", + "BriefDescription": "Ingress Occupancy; BL - Credits", + "EventCode": "0x11", + "EventName": "UNC_S_RxR_OCCUPANCY.BL_CRD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.", - "UMask": "0x8", - "Unit": "QPI LL" + "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", + "UMask": "0x4", + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits", - "EventCode": "0x1", - "EventName": "UNC_Q_TxL_FLITS_G2.NCS", + "BriefDescription": "Ingress Occupancy; IV", + "EventCode": "0x11", + "EventName": "UNC_S_RxR_OCCUPANCY.IV", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits transmitted over QPI. This includes extended headers.", - "UMask": "0x10", - "Unit": "QPI LL" + "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", + "UMask": "0x20", + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD", - "EventCode": "0x1", - "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD", + "BriefDescription": "UNC_S_TxR_ADS_USED.AD", + "EventCode": "0x4", + "EventName": "UNC_S_TxR_ADS_USED.AD", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK", - "EventCode": "0x1", - "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK", + "BriefDescription": "UNC_S_TxR_ADS_USED.AK", + "EventCode": "0x4", + "EventName": "UNC_S_TxR_ADS_USED.AK", "PerPkg": "1", - "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "Tx Flit Buffer Allocations", + "BriefDescription": "UNC_S_TxR_ADS_USED.BL", "EventCode": "0x4", - "EventName": "UNC_Q_TxL_INSERTS", + "EventName": "UNC_S_TxR_ADS_USED.BL", "PerPkg": "1", - "PublicDescription": "Number of allocations into the QPI Tx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", - "Unit": "QPI LL" + "UMask": "0x4", + "Unit": "SBOX" }, { - "BriefDescription": "Tx Flit Buffer Occupancy", - "EventCode": "0x7", - "EventName": "UNC_Q_TxL_OCCUPANCY", + "BriefDescription": "Egress Allocations; AD - Bounces", + "EventCode": "0x2", + "EventName": "UNC_S_TxR_INSERTS.AD_BNC", "PerPkg": "1", - "PublicDescription": "Accumulates the number of flits in the TxQ. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.", - "Unit": "QPI LL" + "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", + "UMask": "0x2", + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN0", - "EventCode": "0x26", - "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0", + "BriefDescription": "Egress Allocations; AD - Credits", + "EventCode": "0x2", + "EventName": "UNC_S_TxR_INSERTS.AD_CRD", "PerPkg": "1", - "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.", + "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN1", - "EventCode": "0x26", - "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1", + "BriefDescription": "Egress Allocations; AK", + "EventCode": "0x2", + "EventName": "UNC_S_TxR_INSERTS.AK", "PerPkg": "1", - "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", + "UMask": "0x10", + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN0", - "EventCode": "0x22", - "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0", + "BriefDescription": "Egress Allocations; BL - Bounces", + "EventCode": "0x2", + "EventName": "UNC_S_TxR_INSERTS.BL_BNC", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", + "UMask": "0x8", + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN1", - "EventCode": "0x22", - "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1", + "BriefDescription": "Egress Allocations; BL - Credits", + "EventCode": "0x2", + "EventName": "UNC_S_TxR_INSERTS.BL_CRD", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", + "UMask": "0x4", + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0", - "EventCode": "0x28", - "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0", + "BriefDescription": "Egress Allocations; IV", + "EventCode": "0x2", + "EventName": "UNC_S_TxR_INSERTS.IV", "PerPkg": "1", - "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", + "UMask": "0x20", + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1", - "EventCode": "0x28", - "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1", + "BriefDescription": "Egress Occupancy; AD - Bounces", + "EventCode": "0x1", + "EventName": "UNC_S_TxR_OCCUPANCY.AD_BNC", "PerPkg": "1", - "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD.", + "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0", - "EventCode": "0x24", - "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0", + "BriefDescription": "Egress Occupancy; AD - Credits", + "EventCode": "0x1", + "EventName": "UNC_S_TxR_OCCUPANCY.AD_CRD", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD.", + "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1", - "EventCode": "0x24", - "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1", + "BriefDescription": "Egress Occupancy; AK", + "EventCode": "0x1", + "EventName": "UNC_S_TxR_OCCUPANCY.AK", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", + "UMask": "0x10", + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN0", - "EventCode": "0x27", - "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0", + "BriefDescription": "Egress Occupancy; BL - Bounces", + "EventCode": "0x1", + "EventName": "UNC_S_TxR_OCCUPANCY.BL_BNC", "PerPkg": "1", - "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", + "UMask": "0x8", + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN1", - "EventCode": "0x27", - "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1", + "BriefDescription": "Egress Occupancy; BL - Credits", + "EventCode": "0x1", + "EventName": "UNC_S_TxR_OCCUPANCY.BL_CRD", "PerPkg": "1", - "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", + "UMask": "0x4", + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN0", - "EventCode": "0x23", - "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0", + "BriefDescription": "Egress Occupancy; IV", + "EventCode": "0x1", + "EventName": "UNC_S_TxR_OCCUPANCY.IV", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for Snoop messages on AD.", + "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", + "UMask": "0x20", + "Unit": "SBOX" + }, + { + "BriefDescription": "Injection Starvation; Onto AD Ring", + "EventCode": "0x3", + "EventName": "UNC_S_TxR_STARVED.AD", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN1", - "EventCode": "0x23", - "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1", + "BriefDescription": "Injection Starvation; Onto AK Ring", + "EventCode": "0x3", + "EventName": "UNC_S_TxR_STARVED.AK", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for Snoop messages on AD.", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR", - "EventCode": "0x29", - "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED", + "BriefDescription": "Injection Starvation; Onto BL Ring", + "EventCode": "0x3", + "EventName": "UNC_S_TxR_STARVED.BL", "PerPkg": "1", - "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.", - "Unit": "QPI LL" + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.", + "UMask": "0x4", + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR", - "EventCode": "0x25", - "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY", + "BriefDescription": "Injection Starvation; Onto IV Ring", + "EventCode": "0x3", + "EventName": "UNC_S_TxR_STARVED.IV", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. Local NDR message class to AK Egress.", - "Unit": "QPI LL" + "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.", + "UMask": "0x8", + "Unit": "SBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN0", - "EventCode": "0x2A", - "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0", + "BriefDescription": "UNC_U_CLOCKTICKS", + "EventName": "UNC_U_CLOCKTICKS", "PerPkg": "1", - "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.", - "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN1", - "EventCode": "0x2A", - "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1", + "BriefDescription": "VLW Received", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", "PerPkg": "1", - "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x8", + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for Shared VN", - "EventCode": "0x2A", - "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR", + "BriefDescription": "Filter Match", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.DISABLE", "PerPkg": "1", - "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.", - "UMask": "0x4", - "Unit": "QPI LL" + "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x2", + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN0", - "EventCode": "0x1F", - "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0", + "BriefDescription": "Filter Match", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.ENABLE", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.", + "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN1", - "EventCode": "0x1F", - "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1", + "BriefDescription": "Filter Match", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x8", + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for Shared VN", - "EventCode": "0x1F", - "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR", + "BriefDescription": "Filter Match", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.", + "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN0", - "EventCode": "0x2B", - "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0", + "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", + "EventCode": "0x45", + "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", "PerPkg": "1", - "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.", + "PublicDescription": "PHOLD cycles. Filter from source CoreID.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN1", - "EventCode": "0x2B", - "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1", + "BriefDescription": "RACU Request", + "EventCode": "0x46", + "EventName": "UNC_U_RACU_REQUESTS", "PerPkg": "1", - "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Number outstanding register requests within message channel tracker", + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN0", - "EventCode": "0x20", - "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0", + "BriefDescription": "Monitor Sent to T0; Correctable Machine Check", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.CMC", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Events coming from Uncore can be sent to one or all cores", + "UMask": "0x10", + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN1", - "EventCode": "0x20", - "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1", + "BriefDescription": "Monitor Sent to T0; Livelock", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.LIVELOCK", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", + "UMask": "0x4", + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN0", - "EventCode": "0x2C", - "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0", + "BriefDescription": "Monitor Sent to T0; LTError", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.LTERROR", "PerPkg": "1", - "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", + "UMask": "0x8", + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN1", - "EventCode": "0x2C", - "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1", + "BriefDescription": "Monitor Sent to T0; Monitor T0", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0", "PerPkg": "1", - "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", + "UMask": "0x1", + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN0", - "EventCode": "0x21", - "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0", + "BriefDescription": "Monitor Sent to T0; Monitor T1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress.", - "UMask": "0x1", - "Unit": "QPI LL" + "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", + "UMask": "0x2", + "Unit": "UBOX" }, { - "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN1", - "EventCode": "0x21", - "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1", + "BriefDescription": "Monitor Sent to T0; Other", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.OTHER", "PerPkg": "1", - "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress.", - "UMask": "0x2", - "Unit": "QPI LL" + "PublicDescription": "Events coming from Uncore can be sent to one or all cores; PREQ, PSMI, P2U, Thermal, PCUSMI, PMI", + "UMask": "0x80", + "Unit": "UBOX" }, { - "BriefDescription": "VNA Credits Returned", - "EventCode": "0x1C", - "EventName": "UNC_Q_VNA_CREDIT_RETURNS", + "BriefDescription": "Monitor Sent to T0; Trap", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.TRAP", "PerPkg": "1", - "PublicDescription": "Number of VNA credits returned.", - "Unit": "QPI LL" + "PublicDescription": "Events coming from Uncore can be sent to one or all cores", + "UMask": "0x40", + "Unit": "UBOX" }, { - "BriefDescription": "VNA Credits Pending Return - Occupancy", - "EventCode": "0x1B", - "EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY", + "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.UMC", "PerPkg": "1", - "PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.", - "Unit": "QPI LL" + "PublicDescription": "Events coming from Uncore can be sent to one or all cores", + "UMask": "0x20", + "Unit": "UBOX" } ] diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-io.json b/tools/perf/pmu-events/arch/x86/haswellx/uncore-io.json new file mode 100644 index 000000000000..bd64a8a1625f --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/haswellx/uncore-io.json @@ -0,0 +1,528 @@ +[ + { + "BriefDescription": "Number of uclks in domain", + "EventCode": "0x1", + "EventName": "UNC_R2_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts the number of uclks in the R2PCIe uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI0", + "EventCode": "0x2D", + "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI1", + "EventCode": "0x2D", + "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI0", + "EventCode": "0x2D", + "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI1", + "EventCode": "0x2D", + "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; DRS", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; NCB", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; NCS", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; DRS", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; NCB", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; NCS", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xc", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x3", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise and Even", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "AK Ingress Bounced; Dn", + "EventCode": "0x12", + "EventName": "UNC_R2_RING_AK_BOUNCES.DN", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "AK Ingress Bounced; Up", + "EventCode": "0x12", + "EventName": "UNC_R2_RING_AK_BOUNCES.UP", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xc", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x3", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise and Even", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xc", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x3", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise and Even", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 IV Ring in Use; Any", + "EventCode": "0xA", + "EventName": "UNC_R2_RING_IV_USED.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", + "UMask": "0xf", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 IV Ring in Use; Counterclockwise", + "EventCode": "0xA", + "EventName": "UNC_R2_RING_IV_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", + "UMask": "0xc", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 IV Ring in Use; Clockwise", + "EventCode": "0xA", + "EventName": "UNC_R2_RING_IV_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", + "UMask": "0x3", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NCB", + "EventCode": "0x10", + "EventName": "UNC_R2_RxR_CYCLES_NE.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NCS", + "EventCode": "0x10", + "EventName": "UNC_R2_RxR_CYCLES_NE.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Allocations; NCB", + "EventCode": "0x11", + "EventName": "UNC_R2_RxR_INSERTS.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Allocations; NCS", + "EventCode": "0x11", + "EventName": "UNC_R2_RxR_INSERTS.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; DRS", + "EventCode": "0x13", + "EventName": "UNC_R2_RxR_OCCUPANCY.DRS", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "SBo0 Credits Acquired; For AD Ring", + "EventCode": "0x28", + "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.AD", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "SBo0 Credits Acquired; For BL Ring", + "EventCode": "0x28", + "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.BL", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "SBo0 Credits Occupancy; For AD Ring", + "EventCode": "0x2A", + "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.AD", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "SBo0 Credits Occupancy; For BL Ring", + "EventCode": "0x2A", + "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.BL", + "PerPkg": "1", + "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring", + "EventCode": "0x2C", + "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD", + "PerPkg": "1", + "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring", + "EventCode": "0x2C", + "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL", + "PerPkg": "1", + "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring", + "EventCode": "0x2C", + "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD", + "PerPkg": "1", + "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring", + "EventCode": "0x2C", + "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL", + "PerPkg": "1", + "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; AD", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AD Egress Queue", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; AK", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.AK", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AK Egress Queue", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; BL", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.BL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; BL Egress Queue", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; AD", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AD Egress Queue", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; AK", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.AK", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AK Egress Queue", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; BL", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.BL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; BL Egress Queue", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; AD CCW", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.DN_AD", + "PerPkg": "1", + "PublicDescription": "AD CounterClockwise Egress Queue", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; AK CCW", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.DN_AK", + "PerPkg": "1", + "PublicDescription": "AK CounterClockwise Egress Queue", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; BL CCW", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.DN_BL", + "PerPkg": "1", + "PublicDescription": "BL CounterClockwise Egress Queue", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; AK CCW", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.UP_AD", + "PerPkg": "1", + "PublicDescription": "BL CounterClockwise Egress Queue", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; BL CW", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.UP_AK", + "PerPkg": "1", + "PublicDescription": "AD Clockwise Egress Queue", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; BL CCW", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.UP_BL", + "PerPkg": "1", + "PublicDescription": "AD CounterClockwise Egress Queue", + "UMask": "0x10", + "Unit": "R2PCIe" + } +] diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-other.json b/tools/perf/pmu-events/arch/x86/haswellx/uncore-other.json deleted file mode 100644 index d30e3b16c1af..000000000000 --- a/tools/perf/pmu-events/arch/x86/haswellx/uncore-other.json +++ /dev/null @@ -1,3160 +0,0 @@ -[ - { - "BriefDescription": "Total Write Cache Occupancy; Any Source", - "EventCode": "0x12", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Total Write Cache Occupancy; Select Source", - "EventCode": "0x12", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Clocks in the IRP", - "EventName": "UNC_I_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Number of clocks in the IRP.", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; CLFlush", - "EventCode": "0x13", - "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x80", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; CRd", - "EventCode": "0x13", - "EventName": "UNC_I_COHERENT_OPS.CRD", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; DRd", - "EventCode": "0x13", - "EventName": "UNC_I_COHERENT_OPS.DRD", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; PCIDCAHin5t", - "EventCode": "0x13", - "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; PCIRdCur", - "EventCode": "0x13", - "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; PCIItoM", - "EventCode": "0x13", - "EventName": "UNC_I_COHERENT_OPS.PCITOM", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; RFO", - "EventCode": "0x13", - "EventName": "UNC_I_COHERENT_OPS.RFO", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; WbMtoI", - "EventCode": "0x13", - "EventName": "UNC_I_COHERENT_OPS.WBMTOI", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary", - "EventCode": "0x14", - "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", - "PerPkg": "1", - "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary", - "EventCode": "0x14", - "EventName": "UNC_I_MISC0.2ND_RD_INSERT", - "PerPkg": "1", - "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary", - "EventCode": "0x14", - "EventName": "UNC_I_MISC0.2ND_WR_INSERT", - "PerPkg": "1", - "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Fastpath Rejects", - "EventCode": "0x14", - "EventName": "UNC_I_MISC0.FAST_REJ", - "PerPkg": "1", - "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Fastpath Requests", - "EventCode": "0x14", - "EventName": "UNC_I_MISC0.FAST_REQ", - "PerPkg": "1", - "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Requests", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary", - "EventCode": "0x14", - "EventName": "UNC_I_MISC0.FAST_XFER", - "PerPkg": "1", - "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary", - "EventCode": "0x14", - "EventName": "UNC_I_MISC0.PF_ACK_HINT", - "PerPkg": "1", - "PublicDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Prefetch TimeOut", - "EventCode": "0x14", - "EventName": "UNC_I_MISC0.PF_TIMEOUT", - "PerPkg": "1", - "PublicDescription": "Indicates the fetch for a previous prefetch wasn't accepted by the prefetch. This happens in the case of a prefetch TimeOut", - "UMask": "0x80", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Data Throttled", - "EventCode": "0x15", - "EventName": "UNC_I_MISC1.DATA_THROTTLE", - "PerPkg": "1", - "PublicDescription": "IRP throttled switch data", - "UMask": "0x80", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1", - "EventCode": "0x15", - "EventName": "UNC_I_MISC1.LOST_FWD", - "PerPkg": "1", - "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Received Invalid", - "EventCode": "0x15", - "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", - "PerPkg": "1", - "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Received Valid", - "EventCode": "0x15", - "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", - "PerPkg": "1", - "PublicDescription": "Secondary received a transfer that did have sufficient MESI state", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line", - "EventCode": "0x15", - "EventName": "UNC_I_MISC1.SLOW_E", - "PerPkg": "1", - "PublicDescription": "Secondary received a transfer that did have sufficient MESI state", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line", - "EventCode": "0x15", - "EventName": "UNC_I_MISC1.SLOW_I", - "PerPkg": "1", - "PublicDescription": "Snoop took cacheline ownership before write from data was committed.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line", - "EventCode": "0x15", - "EventName": "UNC_I_MISC1.SLOW_M", - "PerPkg": "1", - "PublicDescription": "Snoop took cacheline ownership before write from data was committed.", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line", - "EventCode": "0x15", - "EventName": "UNC_I_MISC1.SLOW_S", - "PerPkg": "1", - "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "AK Ingress Occupancy", - "EventCode": "0xA", - "EventName": "UNC_I_RxR_AK_INSERTS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the AK Ingress. This queue is where the IRP receives responses from R2PCIe (the ring).", - "Unit": "IRP" - }, - { - "BriefDescription": "UNC_I_RxR_BL_DRS_CYCLES_FULL", - "EventCode": "0x4", - "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "BL Ingress Occupancy - DRS", - "EventCode": "0x1", - "EventName": "UNC_I_RxR_BL_DRS_INSERTS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "UNC_I_RxR_BL_DRS_OCCUPANCY", - "EventCode": "0x7", - "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "UNC_I_RxR_BL_NCB_CYCLES_FULL", - "EventCode": "0x5", - "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "BL Ingress Occupancy - NCB", - "EventCode": "0x2", - "EventName": "UNC_I_RxR_BL_NCB_INSERTS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "UNC_I_RxR_BL_NCB_OCCUPANCY", - "EventCode": "0x8", - "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "UNC_I_RxR_BL_NCS_CYCLES_FULL", - "EventCode": "0x6", - "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "BL Ingress Occupancy - NCS", - "EventCode": "0x3", - "EventName": "UNC_I_RxR_BL_NCS_INSERTS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "UNC_I_RxR_BL_NCS_OCCUPANCY", - "EventCode": "0x9", - "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; Hit E or S", - "EventCode": "0x17", - "EventName": "UNC_I_SNOOP_RESP.HIT_ES", - "PerPkg": "1", - "PublicDescription": "Snoop Responses : Hit E or S", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; Hit I", - "EventCode": "0x17", - "EventName": "UNC_I_SNOOP_RESP.HIT_I", - "PerPkg": "1", - "PublicDescription": "Snoop Responses : Hit I", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; Hit M", - "EventCode": "0x17", - "EventName": "UNC_I_SNOOP_RESP.HIT_M", - "PerPkg": "1", - "PublicDescription": "Snoop Responses : Hit M", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; Miss", - "EventCode": "0x17", - "EventName": "UNC_I_SNOOP_RESP.MISS", - "PerPkg": "1", - "PublicDescription": "Snoop Responses : Miss", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; SnpCode", - "EventCode": "0x17", - "EventName": "UNC_I_SNOOP_RESP.SNPCODE", - "PerPkg": "1", - "PublicDescription": "Snoop Responses : SnpCode", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; SnpData", - "EventCode": "0x17", - "EventName": "UNC_I_SNOOP_RESP.SNPDATA", - "PerPkg": "1", - "PublicDescription": "Snoop Responses : SnpData", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; SnpInv", - "EventCode": "0x17", - "EventName": "UNC_I_SNOOP_RESP.SNPINV", - "PerPkg": "1", - "PublicDescription": "Snoop Responses : SnpInv", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Atomic", - "EventCode": "0x16", - "EventName": "UNC_I_TRANSACTIONS.ATOMIC", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Other", - "EventCode": "0x16", - "EventName": "UNC_I_TRANSACTIONS.OTHER", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions.", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Read Prefetches", - "EventCode": "0x16", - "EventName": "UNC_I_TRANSACTIONS.RD_PREF", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Reads", - "EventCode": "0x16", - "EventName": "UNC_I_TRANSACTIONS.READS", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Writes", - "EventCode": "0x16", - "EventName": "UNC_I_TRANSACTIONS.WRITES", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Write Prefetches", - "EventCode": "0x16", - "EventName": "UNC_I_TRANSACTIONS.WR_PREF", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of write prefetches.", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "No AD Egress Credit Stalls", - "EventCode": "0x18", - "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES", - "PerPkg": "1", - "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.", - "Unit": "IRP" - }, - { - "BriefDescription": "No BL Egress Credit Stalls", - "EventCode": "0x19", - "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES", - "PerPkg": "1", - "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Read Requests", - "EventCode": "0xE", - "EventName": "UNC_I_TxR_DATA_INSERTS_NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Read Requests", - "EventCode": "0xF", - "EventName": "UNC_I_TxR_DATA_INSERTS_NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Request Queue Occupancy", - "EventCode": "0xD", - "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.", - "Unit": "IRP" - }, - { - "BriefDescription": "Number of uclks in domain", - "EventCode": "0x1", - "EventName": "UNC_R2_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Counts the number of uclks in the R2PCIe uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI0", - "EventCode": "0x2D", - "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI1", - "EventCode": "0x2D", - "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI0", - "EventCode": "0x2D", - "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI1", - "EventCode": "0x2D", - "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credit Acquired; DRS", - "EventCode": "0x33", - "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credit Acquired; NCB", - "EventCode": "0x33", - "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credit Acquired; NCS", - "EventCode": "0x33", - "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credits in Use; DRS", - "EventCode": "0x32", - "EventName": "UNC_R2_IIO_CREDITS_USED.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credits in Use; NCB", - "EventCode": "0x32", - "EventName": "UNC_R2_IIO_CREDITS_USED.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credits in Use; NCS", - "EventCode": "0x32", - "EventName": "UNC_R2_IIO_CREDITS_USED.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Counterclockwise", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xc", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CCW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CCW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Clockwise", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x3", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Clockwise and Even", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "AK Ingress Bounced; Dn", - "EventCode": "0x12", - "EventName": "UNC_R2_RING_AK_BOUNCES.DN", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "AK Ingress Bounced; Up", - "EventCode": "0x12", - "EventName": "UNC_R2_RING_AK_BOUNCES.UP", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Counterclockwise", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xc", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CCW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CCW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Clockwise", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x3", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Clockwise and Even", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Counterclockwise", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xc", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CCW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CCW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Clockwise", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x3", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Clockwise and Even", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 IV Ring in Use; Any", - "EventCode": "0xA", - "EventName": "UNC_R2_RING_IV_USED.ANY", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", - "UMask": "0xf", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 IV Ring in Use; Counterclockwise", - "EventCode": "0xA", - "EventName": "UNC_R2_RING_IV_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", - "UMask": "0xc", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 IV Ring in Use; Clockwise", - "EventCode": "0xA", - "EventName": "UNC_R2_RING_IV_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", - "UMask": "0x3", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; NCB", - "EventCode": "0x10", - "EventName": "UNC_R2_RxR_CYCLES_NE.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; NCS", - "EventCode": "0x10", - "EventName": "UNC_R2_RxR_CYCLES_NE.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Ingress Allocations; NCB", - "EventCode": "0x11", - "EventName": "UNC_R2_RxR_INSERTS.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Ingress Allocations; NCS", - "EventCode": "0x11", - "EventName": "UNC_R2_RxR_INSERTS.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Ingress Occupancy Accumulator; DRS", - "EventCode": "0x13", - "EventName": "UNC_R2_RxR_OCCUPANCY.DRS", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "SBo0 Credits Acquired; For AD Ring", - "EventCode": "0x28", - "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.AD", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "SBo0 Credits Acquired; For BL Ring", - "EventCode": "0x28", - "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.BL", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "SBo0 Credits Occupancy; For AD Ring", - "EventCode": "0x2A", - "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.AD", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "SBo0 Credits Occupancy; For BL Ring", - "EventCode": "0x2A", - "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.BL", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring", - "EventCode": "0x2C", - "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD", - "PerPkg": "1", - "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring", - "EventCode": "0x2C", - "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL", - "PerPkg": "1", - "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring", - "EventCode": "0x2C", - "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD", - "PerPkg": "1", - "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring", - "EventCode": "0x2C", - "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL", - "PerPkg": "1", - "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Full; AD", - "EventCode": "0x25", - "EventName": "UNC_R2_TxR_CYCLES_FULL.AD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AD Egress Queue", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Full; AK", - "EventCode": "0x25", - "EventName": "UNC_R2_TxR_CYCLES_FULL.AK", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AK Egress Queue", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Full; BL", - "EventCode": "0x25", - "EventName": "UNC_R2_TxR_CYCLES_FULL.BL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; BL Egress Queue", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Not Empty; AD", - "EventCode": "0x23", - "EventName": "UNC_R2_TxR_CYCLES_NE.AD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AD Egress Queue", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Not Empty; AK", - "EventCode": "0x23", - "EventName": "UNC_R2_TxR_CYCLES_NE.AK", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AK Egress Queue", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Not Empty; BL", - "EventCode": "0x23", - "EventName": "UNC_R2_TxR_CYCLES_NE.BL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; BL Egress Queue", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress CCW NACK; AD CCW", - "EventCode": "0x26", - "EventName": "UNC_R2_TxR_NACK_CW.DN_AD", - "PerPkg": "1", - "PublicDescription": "AD CounterClockwise Egress Queue", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress CCW NACK; AK CCW", - "EventCode": "0x26", - "EventName": "UNC_R2_TxR_NACK_CW.DN_AK", - "PerPkg": "1", - "PublicDescription": "AK CounterClockwise Egress Queue", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress CCW NACK; BL CCW", - "EventCode": "0x26", - "EventName": "UNC_R2_TxR_NACK_CW.DN_BL", - "PerPkg": "1", - "PublicDescription": "BL CounterClockwise Egress Queue", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress CCW NACK; AK CCW", - "EventCode": "0x26", - "EventName": "UNC_R2_TxR_NACK_CW.UP_AD", - "PerPkg": "1", - "PublicDescription": "BL CounterClockwise Egress Queue", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress CCW NACK; BL CW", - "EventCode": "0x26", - "EventName": "UNC_R2_TxR_NACK_CW.UP_AK", - "PerPkg": "1", - "PublicDescription": "AD Clockwise Egress Queue", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress CCW NACK; BL CCW", - "EventCode": "0x26", - "EventName": "UNC_R2_TxR_NACK_CW.UP_BL", - "PerPkg": "1", - "PublicDescription": "AD CounterClockwise Egress Queue", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Number of uclks in domain", - "EventCode": "0x1", - "EventName": "UNC_R3_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Counts the number of uclks in the QPI uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles.", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x1F", - "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 10", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x1F", - "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 11", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x1F", - "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 12", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x1F", - "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 13", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x1F", - "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14_16", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 14&16", - "UMask": "0x40", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x1F", - "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 8", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x1F", - "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 9", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x1F", - "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO_15_17", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 15&17", - "UMask": "0x80", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x22", - "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 0", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x22", - "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 1", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x22", - "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 2", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x22", - "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 3", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x22", - "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 4", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x22", - "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 5", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x22", - "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 6", - "UMask": "0x40", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x22", - "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 7", - "UMask": "0x80", - "Unit": "R3QPI" - }, - { - "BriefDescription": "HA/R2 AD Credits Empty", - "EventCode": "0x2D", - "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0", - "PerPkg": "1", - "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA0", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "HA/R2 AD Credits Empty", - "EventCode": "0x2D", - "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1", - "PerPkg": "1", - "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA1", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "HA/R2 AD Credits Empty", - "EventCode": "0x2D", - "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB", - "PerPkg": "1", - "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCB Messages", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "HA/R2 AD Credits Empty", - "EventCode": "0x2D", - "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS", - "PerPkg": "1", - "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCS Messages", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "IOT Backpressure", - "EventCode": "0xB", - "EventName": "UNC_R3_IOT_BACKPRESSURE.HUB", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "IOT Backpressure", - "EventCode": "0xB", - "EventName": "UNC_R3_IOT_BACKPRESSURE.SAT", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "IOT Common Trigger Sequencer - Hi", - "EventCode": "0xD", - "EventName": "UNC_R3_IOT_CTS_HI.CTS2", - "PerPkg": "1", - "PublicDescription": "Debug Mask/Match Tie-Ins", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "IOT Common Trigger Sequencer - Hi", - "EventCode": "0xD", - "EventName": "UNC_R3_IOT_CTS_HI.CTS3", - "PerPkg": "1", - "PublicDescription": "Debug Mask/Match Tie-Ins", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "IOT Common Trigger Sequencer - Lo", - "EventCode": "0xC", - "EventName": "UNC_R3_IOT_CTS_LO.CTS0", - "PerPkg": "1", - "PublicDescription": "Debug Mask/Match Tie-Ins", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "IOT Common Trigger Sequencer - Lo", - "EventCode": "0xC", - "EventName": "UNC_R3_IOT_CTS_LO.CTS1", - "PerPkg": "1", - "PublicDescription": "Debug Mask/Match Tie-Ins", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 AD Credits Empty", - "EventCode": "0x20", - "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 HOM Messages", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 AD Credits Empty", - "EventCode": "0x20", - "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 NDR Messages", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 AD Credits Empty", - "EventCode": "0x20", - "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 SNP Messages", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 AD Credits Empty", - "EventCode": "0x20", - "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 HOM Messages", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 AD Credits Empty", - "EventCode": "0x20", - "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 NDR Messages", - "UMask": "0x40", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 AD Credits Empty", - "EventCode": "0x20", - "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 SNP Messages", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 AD Credits Empty", - "EventCode": "0x20", - "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VNA", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 BL Credits Empty", - "EventCode": "0x21", - "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 HOM Messages", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 BL Credits Empty", - "EventCode": "0x21", - "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 NDR Messages", - "UMask": "0x40", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 BL Credits Empty", - "EventCode": "0x21", - "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 SNP Messages", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 BL Credits Empty", - "EventCode": "0x21", - "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VNA", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 AD Credits Empty", - "EventCode": "0x2E", - "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 HOM Messages", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 AD Credits Empty", - "EventCode": "0x2E", - "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 NDR Messages", - "UMask": "0x40", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 AD Credits Empty", - "EventCode": "0x2E", - "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 SNP Messages", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 AD Credits Empty", - "EventCode": "0x2E", - "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VNA", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 BL Credits Empty", - "EventCode": "0x2F", - "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 HOM Messages", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 BL Credits Empty", - "EventCode": "0x2F", - "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 NDR Messages", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 BL Credits Empty", - "EventCode": "0x2F", - "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 SNP Messages", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 BL Credits Empty", - "EventCode": "0x2F", - "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 HOM Messages", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 BL Credits Empty", - "EventCode": "0x2F", - "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 NDR Messages", - "UMask": "0x40", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 BL Credits Empty", - "EventCode": "0x2F", - "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 SNP Messages", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 BL Credits Empty", - "EventCode": "0x2F", - "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VNA", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AD Ring in Use; Counterclockwise", - "EventCode": "0x7", - "EventName": "UNC_R3_RING_AD_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xc", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even", - "EventCode": "0x7", - "EventName": "UNC_R3_RING_AD_USED.CCW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd", - "EventCode": "0x7", - "EventName": "UNC_R3_RING_AD_USED.CCW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AD Ring in Use; Clockwise", - "EventCode": "0x7", - "EventName": "UNC_R3_RING_AD_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x3", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AD Ring in Use; Clockwise and Even", - "EventCode": "0x7", - "EventName": "UNC_R3_RING_AD_USED.CW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd", - "EventCode": "0x7", - "EventName": "UNC_R3_RING_AD_USED.CW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AK Ring in Use; Counterclockwise", - "EventCode": "0x8", - "EventName": "UNC_R3_RING_AK_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xc", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even", - "EventCode": "0x8", - "EventName": "UNC_R3_RING_AK_USED.CCW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd", - "EventCode": "0x8", - "EventName": "UNC_R3_RING_AK_USED.CCW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AK Ring in Use; Clockwise", - "EventCode": "0x8", - "EventName": "UNC_R3_RING_AK_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x3", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AK Ring in Use; Clockwise and Even", - "EventCode": "0x8", - "EventName": "UNC_R3_RING_AK_USED.CW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd", - "EventCode": "0x8", - "EventName": "UNC_R3_RING_AK_USED.CW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 BL Ring in Use; Counterclockwise", - "EventCode": "0x9", - "EventName": "UNC_R3_RING_BL_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xc", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even", - "EventCode": "0x9", - "EventName": "UNC_R3_RING_BL_USED.CCW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity.", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd", - "EventCode": "0x9", - "EventName": "UNC_R3_RING_BL_USED.CCW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 BL Ring in Use; Clockwise", - "EventCode": "0x9", - "EventName": "UNC_R3_RING_BL_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x3", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 BL Ring in Use; Clockwise and Even", - "EventCode": "0x9", - "EventName": "UNC_R3_RING_BL_USED.CW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd", - "EventCode": "0x9", - "EventName": "UNC_R3_RING_BL_USED.CW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 IV Ring in Use; Any", - "EventCode": "0xA", - "EventName": "UNC_R3_RING_IV_USED.ANY", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", - "UMask": "0xf", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 IV Ring in Use; Clockwise", - "EventCode": "0xA", - "EventName": "UNC_R3_RING_IV_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", - "UMask": "0x3", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ring Stop Starved; AK", - "EventCode": "0xE", - "EventName": "UNC_R3_RING_SINK_STARVED.AK", - "PerPkg": "1", - "PublicDescription": "Number of cycles the ringstop is in starvation (per ring)", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; HOM", - "EventCode": "0x10", - "EventName": "UNC_R3_RxR_CYCLES_NE.HOM", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; NDR", - "EventCode": "0x10", - "EventName": "UNC_R3_RxR_CYCLES_NE.NDR", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; SNP", - "EventCode": "0x10", - "EventName": "UNC_R3_RxR_CYCLES_NE.SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Cycles Not Empty; DRS", - "EventCode": "0x14", - "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Cycles Not Empty; HOM", - "EventCode": "0x14", - "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.HOM", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Cycles Not Empty; NCB", - "EventCode": "0x14", - "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Cycles Not Empty; NCS", - "EventCode": "0x14", - "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Cycles Not Empty; NDR", - "EventCode": "0x14", - "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NDR", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Cycles Not Empty; SNP", - "EventCode": "0x14", - "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI VN1 Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Allocations; DRS", - "EventCode": "0x11", - "EventName": "UNC_R3_RxR_INSERTS.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Allocations; HOM", - "EventCode": "0x11", - "EventName": "UNC_R3_RxR_INSERTS.HOM", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Allocations; NCB", - "EventCode": "0x11", - "EventName": "UNC_R3_RxR_INSERTS.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Allocations; NCS", - "EventCode": "0x11", - "EventName": "UNC_R3_RxR_INSERTS.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Allocations; NDR", - "EventCode": "0x11", - "EventName": "UNC_R3_RxR_INSERTS.NDR", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Allocations; SNP", - "EventCode": "0x11", - "EventName": "UNC_R3_RxR_INSERTS.SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Allocations; DRS", - "EventCode": "0x15", - "EventName": "UNC_R3_RxR_INSERTS_VN1.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Allocations; HOM", - "EventCode": "0x15", - "EventName": "UNC_R3_RxR_INSERTS_VN1.HOM", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Allocations; NCB", - "EventCode": "0x15", - "EventName": "UNC_R3_RxR_INSERTS_VN1.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Allocations; NCS", - "EventCode": "0x15", - "EventName": "UNC_R3_RxR_INSERTS_VN1.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Allocations; NDR", - "EventCode": "0x15", - "EventName": "UNC_R3_RxR_INSERTS_VN1.NDR", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Allocations; SNP", - "EventCode": "0x15", - "EventName": "UNC_R3_RxR_INSERTS_VN1.SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI VN1 Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Occupancy Accumulator; DRS", - "EventCode": "0x13", - "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.DRS", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Occupancy Accumulator; HOM", - "EventCode": "0x13", - "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.HOM", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; HOM Ingress Queue", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Occupancy Accumulator; NCB", - "EventCode": "0x13", - "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCB", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NCB Ingress Queue", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Occupancy Accumulator; NCS", - "EventCode": "0x13", - "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCS", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NCS Ingress Queue", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Occupancy Accumulator; NDR", - "EventCode": "0x13", - "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NDR", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; NDR Ingress Queue", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Ingress Occupancy Accumulator; SNP", - "EventCode": "0x13", - "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.SNP", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given QPI VN1 Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI VN1 Ingress Not Empty event to calculate average occupancy or the QPI VN1 Ingress Allocations event in order to calculate average queuing latency.; SNP Ingress Queue", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "SBo0 Credits Acquired; For AD Ring", - "EventCode": "0x28", - "EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.AD", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "SBo0 Credits Acquired; For BL Ring", - "EventCode": "0x28", - "EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.BL", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 0 credits acquired in a given cycle, per ring.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "SBo0 Credits Occupancy; For AD Ring", - "EventCode": "0x2A", - "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.AD", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "SBo0 Credits Occupancy; For BL Ring", - "EventCode": "0x2A", - "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.BL", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 0 credits in use in a given cycle, per ring.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "SBo1 Credits Acquired; For AD Ring", - "EventCode": "0x29", - "EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.AD", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "SBo1 Credits Acquired; For BL Ring", - "EventCode": "0x29", - "EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.BL", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 1 credits acquired in a given cycle, per ring.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "SBo1 Credits Occupancy; For AD Ring", - "EventCode": "0x2B", - "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.AD", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "SBo1 Credits Occupancy; For BL Ring", - "EventCode": "0x2B", - "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.BL", - "PerPkg": "1", - "PublicDescription": "Number of Sbo 1 credits in use in a given cycle, per ring.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring", - "EventCode": "0x2C", - "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_AD", - "PerPkg": "1", - "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring", - "EventCode": "0x2C", - "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_BL", - "PerPkg": "1", - "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring", - "EventCode": "0x2C", - "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_AD", - "PerPkg": "1", - "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring", - "EventCode": "0x2C", - "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_BL", - "PerPkg": "1", - "PublicDescription": "Number of cycles Egress is stalled waiting for an Sbo credit to become available. Per Sbo, per Ring.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Egress CCW NACK; AD CCW", - "EventCode": "0x26", - "EventName": "UNC_R3_TxR_NACK.DN_AD", - "PerPkg": "1", - "PublicDescription": "AD CounterClockwise Egress Queue", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Egress CCW NACK; AK CCW", - "EventCode": "0x26", - "EventName": "UNC_R3_TxR_NACK.DN_AK", - "PerPkg": "1", - "PublicDescription": "AK CounterClockwise Egress Queue", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Egress CCW NACK; BL CCW", - "EventCode": "0x26", - "EventName": "UNC_R3_TxR_NACK.DN_BL", - "PerPkg": "1", - "PublicDescription": "BL CounterClockwise Egress Queue", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Egress CCW NACK; AK CCW", - "EventCode": "0x26", - "EventName": "UNC_R3_TxR_NACK.UP_AD", - "PerPkg": "1", - "PublicDescription": "BL CounterClockwise Egress Queue", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Egress CCW NACK; BL CW", - "EventCode": "0x26", - "EventName": "UNC_R3_TxR_NACK.UP_AK", - "PerPkg": "1", - "PublicDescription": "AD Clockwise Egress Queue", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Egress CCW NACK; BL CCW", - "EventCode": "0x26", - "EventName": "UNC_R3_TxR_NACK.UP_BL", - "PerPkg": "1", - "PublicDescription": "AD CounterClockwise Egress Queue", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class", - "EventCode": "0x37", - "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class", - "EventCode": "0x37", - "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Message Class", - "EventCode": "0x37", - "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Message Class", - "EventCode": "0x37", - "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class", - "EventCode": "0x37", - "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class", - "EventCode": "0x37", - "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Used; DRS Message Class", - "EventCode": "0x36", - "EventName": "UNC_R3_VN0_CREDITS_USED.DRS", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Used; HOM Message Class", - "EventCode": "0x36", - "EventName": "UNC_R3_VN0_CREDITS_USED.HOM", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Used; NCB Message Class", - "EventCode": "0x36", - "EventName": "UNC_R3_VN0_CREDITS_USED.NCB", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Used; NCS Message Class", - "EventCode": "0x36", - "EventName": "UNC_R3_VN0_CREDITS_USED.NCS", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Used; NDR Message Class", - "EventCode": "0x36", - "EventName": "UNC_R3_VN0_CREDITS_USED.NDR", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Used; SNP Message Class", - "EventCode": "0x36", - "EventName": "UNC_R3_VN0_CREDITS_USED.SNP", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Message Class", - "EventCode": "0x39", - "EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Message Class", - "EventCode": "0x39", - "EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCB Message Class", - "EventCode": "0x39", - "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCB", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCS Message Class", - "EventCode": "0x39", - "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCS", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Message Class", - "EventCode": "0x39", - "EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Message Class", - "EventCode": "0x39", - "EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Used; DRS Message Class", - "EventCode": "0x38", - "EventName": "UNC_R3_VN1_CREDITS_USED.DRS", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Used; HOM Message Class", - "EventCode": "0x38", - "EventName": "UNC_R3_VN1_CREDITS_USED.HOM", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Used; NCB Message Class", - "EventCode": "0x38", - "EventName": "UNC_R3_VN1_CREDITS_USED.NCB", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Used; NCS Message Class", - "EventCode": "0x38", - "EventName": "UNC_R3_VN1_CREDITS_USED.NCS", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Used; NDR Message Class", - "EventCode": "0x38", - "EventName": "UNC_R3_VN1_CREDITS_USED.NDR", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Used; SNP Message Class", - "EventCode": "0x38", - "EventName": "UNC_R3_VN1_CREDITS_USED.SNP", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA credit Acquisitions; HOM Message Class", - "EventCode": "0x33", - "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD", - "PerPkg": "1", - "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA credit Acquisitions; HOM Message Class", - "EventCode": "0x33", - "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL", - "PerPkg": "1", - "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA Credit Reject; DRS Message Class", - "EventCode": "0x34", - "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS", - "PerPkg": "1", - "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA Credit Reject; HOM Message Class", - "EventCode": "0x34", - "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM", - "PerPkg": "1", - "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA Credit Reject; NCB Message Class", - "EventCode": "0x34", - "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB", - "PerPkg": "1", - "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA Credit Reject; NCS Message Class", - "EventCode": "0x34", - "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS", - "PerPkg": "1", - "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Standard (NCS).", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA Credit Reject; NDR Message Class", - "EventCode": "0x34", - "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR", - "PerPkg": "1", - "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA Credit Reject; SNP Message Class", - "EventCode": "0x34", - "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP", - "PerPkg": "1", - "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Bounce Control", - "EventCode": "0xA", - "EventName": "UNC_S_BOUNCE_CONTROL", - "PerPkg": "1", - "Unit": "SBO" - }, - { - "BriefDescription": "Uncore Clocks", - "EventName": "UNC_S_CLOCKTICKS", - "PerPkg": "1", - "Unit": "SBO" - }, - { - "BriefDescription": "FaST wire asserted", - "EventCode": "0x9", - "EventName": "UNC_S_FAST_ASSERTED", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", - "Unit": "SBO" - }, - { - "BriefDescription": "AD Ring In Use; Down", - "EventCode": "0x1B", - "EventName": "UNC_S_RING_AD_USED.DOWN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0xc", - "Unit": "SBO" - }, - { - "BriefDescription": "AD Ring In Use; Down and Event", - "EventCode": "0x1B", - "EventName": "UNC_S_RING_AD_USED.DOWN_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "AD Ring In Use; Down and Odd", - "EventCode": "0x1B", - "EventName": "UNC_S_RING_AD_USED.DOWN_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "AD Ring In Use; Up", - "EventCode": "0x1B", - "EventName": "UNC_S_RING_AD_USED.UP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x3", - "Unit": "SBO" - }, - { - "BriefDescription": "AD Ring In Use; Up and Even", - "EventCode": "0x1B", - "EventName": "UNC_S_RING_AD_USED.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "AD Ring In Use; Up and Odd", - "EventCode": "0x1B", - "EventName": "UNC_S_RING_AD_USED.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "AK Ring In Use; Down", - "EventCode": "0x1C", - "EventName": "UNC_S_RING_AK_USED.DOWN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0xc", - "Unit": "SBO" - }, - { - "BriefDescription": "AK Ring In Use; Down and Event", - "EventCode": "0x1C", - "EventName": "UNC_S_RING_AK_USED.DOWN_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "AK Ring In Use; Down and Odd", - "EventCode": "0x1C", - "EventName": "UNC_S_RING_AK_USED.DOWN_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "AK Ring In Use; Up", - "EventCode": "0x1C", - "EventName": "UNC_S_RING_AK_USED.UP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x3", - "Unit": "SBO" - }, - { - "BriefDescription": "AK Ring In Use; Up and Even", - "EventCode": "0x1C", - "EventName": "UNC_S_RING_AK_USED.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "AK Ring In Use; Up and Odd", - "EventCode": "0x1C", - "EventName": "UNC_S_RING_AK_USED.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "BL Ring in Use; Down", - "EventCode": "0x1D", - "EventName": "UNC_S_RING_BL_USED.DOWN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0xc", - "Unit": "SBO" - }, - { - "BriefDescription": "BL Ring in Use; Down and Event", - "EventCode": "0x1D", - "EventName": "UNC_S_RING_BL_USED.DOWN_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Event ring polarity.", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "BL Ring in Use; Down and Odd", - "EventCode": "0x1D", - "EventName": "UNC_S_RING_BL_USED.DOWN_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity.", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "BL Ring in Use; Up", - "EventCode": "0x1D", - "EventName": "UNC_S_RING_BL_USED.UP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x3", - "Unit": "SBO" - }, - { - "BriefDescription": "BL Ring in Use; Up and Even", - "EventCode": "0x1D", - "EventName": "UNC_S_RING_BL_USED.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity.", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "BL Ring in Use; Up and Odd", - "EventCode": "0x1D", - "EventName": "UNC_S_RING_BL_USED.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. We really have two rings in HSX -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity.", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "Number of LLC responses that bounced on the Ring.", - "EventCode": "0x5", - "EventName": "UNC_S_RING_BOUNCES.AD_CACHE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "Number of LLC responses that bounced on the Ring.; Acknowledgements to core", - "EventCode": "0x5", - "EventName": "UNC_S_RING_BOUNCES.AK_CORE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "Number of LLC responses that bounced on the Ring.; Data Responses to core", - "EventCode": "0x5", - "EventName": "UNC_S_RING_BOUNCES.BL_CORE", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.", - "EventCode": "0x5", - "EventName": "UNC_S_RING_BOUNCES.IV_CORE", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "BL Ring in Use; Any", - "EventCode": "0x1E", - "EventName": "UNC_S_RING_IV_USED.DN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. There is only 1 IV ring in HSX. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity", - "UMask": "0xc", - "Unit": "SBO" - }, - { - "BriefDescription": "BL Ring in Use; Any", - "EventCode": "0x1E", - "EventName": "UNC_S_RING_IV_USED.UP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. There is only 1 IV ring in HSX. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.; Filters any polarity", - "UMask": "0x3", - "Unit": "SBO" - }, - { - "BriefDescription": "UNC_S_RING_SINK_STARVED.AD_CACHE", - "EventCode": "0x6", - "EventName": "UNC_S_RING_SINK_STARVED.AD_CACHE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "UNC_S_RING_SINK_STARVED.AK_CORE", - "EventCode": "0x6", - "EventName": "UNC_S_RING_SINK_STARVED.AK_CORE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "UNC_S_RING_SINK_STARVED.BL_CORE", - "EventCode": "0x6", - "EventName": "UNC_S_RING_SINK_STARVED.BL_CORE", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "UNC_S_RING_SINK_STARVED.IV_CORE", - "EventCode": "0x6", - "EventName": "UNC_S_RING_SINK_STARVED.IV_CORE", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; AD - Bounces", - "EventCode": "0x15", - "EventName": "UNC_S_RxR_BUSY_STARVED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; AD - Credits", - "EventCode": "0x15", - "EventName": "UNC_S_RxR_BUSY_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; BL - Bounces", - "EventCode": "0x15", - "EventName": "UNC_S_RxR_BUSY_STARVED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; BL - Credits", - "EventCode": "0x15", - "EventName": "UNC_S_RxR_BUSY_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress because a message (credited/bounceable) is being sent.", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "Bypass; AD - Bounces", - "EventCode": "0x12", - "EventName": "UNC_S_RxR_BYPASS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Bypass the Sbo Ingress.", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "Bypass; AD - Credits", - "EventCode": "0x12", - "EventName": "UNC_S_RxR_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Bypass the Sbo Ingress.", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "Bypass; AK", - "EventCode": "0x12", - "EventName": "UNC_S_RxR_BYPASS.AK", - "PerPkg": "1", - "PublicDescription": "Bypass the Sbo Ingress.", - "UMask": "0x10", - "Unit": "SBO" - }, - { - "BriefDescription": "Bypass; BL - Bounces", - "EventCode": "0x12", - "EventName": "UNC_S_RxR_BYPASS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Bypass the Sbo Ingress.", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "Bypass; BL - Credits", - "EventCode": "0x12", - "EventName": "UNC_S_RxR_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Bypass the Sbo Ingress.", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "Bypass; IV", - "EventCode": "0x12", - "EventName": "UNC_S_RxR_BYPASS.IV", - "PerPkg": "1", - "PublicDescription": "Bypass the Sbo Ingress.", - "UMask": "0x20", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; AD - Bounces", - "EventCode": "0x14", - "EventName": "UNC_S_RxR_CRD_STARVED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; AD - Credits", - "EventCode": "0x14", - "EventName": "UNC_S_RxR_CRD_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; AK", - "EventCode": "0x14", - "EventName": "UNC_S_RxR_CRD_STARVED.AK", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", - "UMask": "0x10", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; BL - Bounces", - "EventCode": "0x14", - "EventName": "UNC_S_RxR_CRD_STARVED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; BL - Credits", - "EventCode": "0x14", - "EventName": "UNC_S_RxR_CRD_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; IVF Credit", - "EventCode": "0x14", - "EventName": "UNC_S_RxR_CRD_STARVED.IFV", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", - "UMask": "0x40", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; IV", - "EventCode": "0x14", - "EventName": "UNC_S_RxR_CRD_STARVED.IV", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Ingress cannot send a transaction onto the ring for a long period of time. In this case, the Ingress but unable to forward to Egress due to lack of credit.", - "UMask": "0x20", - "Unit": "SBO" - }, - { - "BriefDescription": "Ingress Allocations; AD - Bounces", - "EventCode": "0x13", - "EventName": "UNC_S_RxR_INSERTS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "Ingress Allocations; AD - Credits", - "EventCode": "0x13", - "EventName": "UNC_S_RxR_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "Ingress Allocations; AK", - "EventCode": "0x13", - "EventName": "UNC_S_RxR_INSERTS.AK", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", - "UMask": "0x10", - "Unit": "SBO" - }, - { - "BriefDescription": "Ingress Allocations; BL - Bounces", - "EventCode": "0x13", - "EventName": "UNC_S_RxR_INSERTS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "Ingress Allocations; BL - Credits", - "EventCode": "0x13", - "EventName": "UNC_S_RxR_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "Ingress Allocations; IV", - "EventCode": "0x13", - "EventName": "UNC_S_RxR_INSERTS.IV", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Sbo Ingress The Ingress is used to queue up requests received from the ring.", - "UMask": "0x20", - "Unit": "SBO" - }, - { - "BriefDescription": "Ingress Occupancy; AD - Bounces", - "EventCode": "0x11", - "EventName": "UNC_S_RxR_OCCUPANCY.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "Ingress Occupancy; AD - Credits", - "EventCode": "0x11", - "EventName": "UNC_S_RxR_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "Ingress Occupancy; AK", - "EventCode": "0x11", - "EventName": "UNC_S_RxR_OCCUPANCY.AK", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", - "UMask": "0x10", - "Unit": "SBO" - }, - { - "BriefDescription": "Ingress Occupancy; BL - Bounces", - "EventCode": "0x11", - "EventName": "UNC_S_RxR_OCCUPANCY.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "Ingress Occupancy; BL - Credits", - "EventCode": "0x11", - "EventName": "UNC_S_RxR_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "Ingress Occupancy; IV", - "EventCode": "0x11", - "EventName": "UNC_S_RxR_OCCUPANCY.IV", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the Sbo. The Ingress is used to queue up requests received from the ring.", - "UMask": "0x20", - "Unit": "SBO" - }, - { - "BriefDescription": "UNC_S_TxR_ADS_USED.AD", - "EventCode": "0x4", - "EventName": "UNC_S_TxR_ADS_USED.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "UNC_S_TxR_ADS_USED.AK", - "EventCode": "0x4", - "EventName": "UNC_S_TxR_ADS_USED.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "UNC_S_TxR_ADS_USED.BL", - "EventCode": "0x4", - "EventName": "UNC_S_TxR_ADS_USED.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "Egress Allocations; AD - Bounces", - "EventCode": "0x2", - "EventName": "UNC_S_TxR_INSERTS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "Egress Allocations; AD - Credits", - "EventCode": "0x2", - "EventName": "UNC_S_TxR_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "Egress Allocations; AK", - "EventCode": "0x2", - "EventName": "UNC_S_TxR_INSERTS.AK", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", - "UMask": "0x10", - "Unit": "SBO" - }, - { - "BriefDescription": "Egress Allocations; BL - Bounces", - "EventCode": "0x2", - "EventName": "UNC_S_TxR_INSERTS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "Egress Allocations; BL - Credits", - "EventCode": "0x2", - "EventName": "UNC_S_TxR_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "Egress Allocations; IV", - "EventCode": "0x2", - "EventName": "UNC_S_TxR_INSERTS.IV", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Sbo Egress. The Egress is used to queue up requests destined for the ring.", - "UMask": "0x20", - "Unit": "SBO" - }, - { - "BriefDescription": "Egress Occupancy; AD - Bounces", - "EventCode": "0x1", - "EventName": "UNC_S_TxR_OCCUPANCY.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "Egress Occupancy; AD - Credits", - "EventCode": "0x1", - "EventName": "UNC_S_TxR_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "Egress Occupancy; AK", - "EventCode": "0x1", - "EventName": "UNC_S_TxR_OCCUPANCY.AK", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", - "UMask": "0x10", - "Unit": "SBO" - }, - { - "BriefDescription": "Egress Occupancy; BL - Bounces", - "EventCode": "0x1", - "EventName": "UNC_S_TxR_OCCUPANCY.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "Egress Occupancy; BL - Credits", - "EventCode": "0x1", - "EventName": "UNC_S_TxR_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "Egress Occupancy; IV", - "EventCode": "0x1", - "EventName": "UNC_S_TxR_OCCUPANCY.IV", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Sbo. The egress is used to queue up requests destined for the ring.", - "UMask": "0x20", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; Onto AD Ring", - "EventCode": "0x3", - "EventName": "UNC_S_TxR_STARVED.AD", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.", - "UMask": "0x1", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; Onto AK Ring", - "EventCode": "0x3", - "EventName": "UNC_S_TxR_STARVED.AK", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.", - "UMask": "0x2", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; Onto BL Ring", - "EventCode": "0x3", - "EventName": "UNC_S_TxR_STARVED.BL", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.", - "UMask": "0x4", - "Unit": "SBO" - }, - { - "BriefDescription": "Injection Starvation; Onto IV Ring", - "EventCode": "0x3", - "EventName": "UNC_S_TxR_STARVED.IV", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.", - "UMask": "0x8", - "Unit": "SBO" - }, - { - "BriefDescription": "UNC_U_CLOCKTICKS", - "EventName": "UNC_U_CLOCKTICKS", - "PerPkg": "1", - "Unit": "UBOX" - }, - { - "BriefDescription": "VLW Received", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", - "PerPkg": "1", - "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x8", - "Unit": "UBOX" - }, - { - "BriefDescription": "Filter Match", - "EventCode": "0x41", - "EventName": "UNC_U_FILTER_MATCH.DISABLE", - "PerPkg": "1", - "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "Filter Match", - "EventCode": "0x41", - "EventName": "UNC_U_FILTER_MATCH.ENABLE", - "PerPkg": "1", - "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "Filter Match", - "EventCode": "0x41", - "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE", - "PerPkg": "1", - "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x8", - "Unit": "UBOX" - }, - { - "BriefDescription": "Filter Match", - "EventCode": "0x41", - "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE", - "PerPkg": "1", - "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x4", - "Unit": "UBOX" - }, - { - "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", - "EventCode": "0x45", - "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", - "PerPkg": "1", - "PublicDescription": "PHOLD cycles. Filter from source CoreID.", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "RACU Request", - "EventCode": "0x46", - "EventName": "UNC_U_RACU_REQUESTS", - "PerPkg": "1", - "PublicDescription": "Number outstanding register requests within message channel tracker", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Correctable Machine Check", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.CMC", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores", - "UMask": "0x10", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Livelock", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.LIVELOCK", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", - "UMask": "0x4", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; LTError", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.LTERROR", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", - "UMask": "0x8", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Monitor T0", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Monitor T1", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Other", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.OTHER", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores; PREQ, PSMI, P2U, Thermal, PCUSMI, PMI", - "UMask": "0x80", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Trap", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.TRAP", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores", - "UMask": "0x40", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.UMC", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores", - "UMask": "0x20", - "Unit": "UBOX" - } -] -- cgit v1.2.3-58-ga151 From bc4a245a80eef3ac1f0ee33f1ee3217218e38f3e Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 13 Apr 2023 06:29:39 -0700 Subject: perf vendor events intel: Fix uncore topics for icelake Move events from 'uncore-other' topic classification to interconnect. Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230413132949.3487664-12-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/x86/icelake/uncore-interconnect.json | 74 ++++++++++++++++++++++ .../pmu-events/arch/x86/icelake/uncore-other.json | 72 --------------------- 2 files changed, 74 insertions(+), 72 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/icelake/uncore-interconnect.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/icelake/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/icelake/uncore-interconnect.json new file mode 100644 index 000000000000..8027590f1776 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/icelake/uncore-interconnect.json @@ -0,0 +1,74 @@ +[ + { + "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, etc.", + "EventCode": "0x84", + "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core. This event is not supported on ICL products but is supported on RKL products.", + "EventCode": "0x85", + "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core. This event is not supported on ICL products but is supported on RKL products.", + "EventCode": "0x85", + "EventName": "UNC_ARB_DAT_OCCUPANCY.RD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches. This event is not supported on ICL products but is supported on RKL products.", + "EventCode": "0x80", + "EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches", + "EventCode": "0x81", + "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic. This event is not supported on ICL products but is supported on RKL products.", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches. This event is not supported on ICL products but is supported on RKL products.", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.RD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches. This event is not supported on ICL products but is supported on RKL products.", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.RD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + } +] diff --git a/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json b/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json index b27d95b2c857..c6596ba09195 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json @@ -1,76 +1,4 @@ [ - { - "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, etc.", - "EventCode": "0x84", - "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core. This event is not supported on ICL products but is supported on RKL products.", - "EventCode": "0x85", - "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core. This event is not supported on ICL products but is supported on RKL products.", - "EventCode": "0x85", - "EventName": "UNC_ARB_DAT_OCCUPANCY.RD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "ARB" - }, - { - "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches. This event is not supported on ICL products but is supported on RKL products.", - "EventCode": "0x80", - "EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "ARB" - }, - { - "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches", - "EventCode": "0x81", - "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "ARB" - }, - { - "BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic. This event is not supported on ICL products but is supported on RKL products.", - "EventCode": "0x80", - "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches. This event is not supported on ICL products but is supported on RKL products.", - "EventCode": "0x80", - "EventName": "UNC_ARB_TRK_OCCUPANCY.RD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "ARB" - }, - { - "BriefDescription": "Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic.", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches. This event is not supported on ICL products but is supported on RKL products.", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.RD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "ARB" - }, { "BriefDescription": "UNC_CLOCK.SOCKET", "EventCode": "0xff", -- cgit v1.2.3-58-ga151 From f42a7d02b7a3ce2531fef0ae89e474f0e0bbf0f9 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 13 Apr 2023 06:29:40 -0700 Subject: perf vendor events intel: Fix uncore topics for icelakex Remove 'uncore-other' topic classification, move to cache, interconnect and io. Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Edward Baker Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: http://lore.kernel.org/lkml/20230413132949.3487664-13-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/icelakex/uncore-cache.json | 9860 ++++++ .../arch/x86/icelakex/uncore-interconnect.json | 14571 ++++++++ .../pmu-events/arch/x86/icelakex/uncore-io.json | 9270 +++++ .../pmu-events/arch/x86/icelakex/uncore-other.json | 33697 ------------------- 4 files changed, 33701 insertions(+), 33697 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/icelakex/uncore-cache.json create mode 100644 tools/perf/pmu-events/arch/x86/icelakex/uncore-interconnect.json create mode 100644 tools/perf/pmu-events/arch/x86/icelakex/uncore-io.json delete mode 100644 tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-cache.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-cache.json new file mode 100644 index 000000000000..b6ce14ebf844 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-cache.json @@ -0,0 +1,9860 @@ +[ + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL", + "Deprecated": "1", + "EventCode": "0x65", + "EventName": "UNC_CHA_2LM_NM_INVITOX.LOCAL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE", + "Deprecated": "1", + "EventCode": "0x65", + "EventName": "UNC_CHA_2LM_NM_INVITOX.REMOTE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT", + "Deprecated": "1", + "EventCode": "0x65", + "EventName": "UNC_CHA_2LM_NM_INVITOX.SETCONFLICT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC", + "Deprecated": "1", + "EventCode": "0x64", + "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.LLC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF", + "Deprecated": "1", + "EventCode": "0x64", + "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.SF", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR", + "Deprecated": "1", + "EventCode": "0x64", + "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.TOR", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR", + "Deprecated": "1", + "EventCode": "0x70", + "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS2.MEMWR", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI", + "Deprecated": "1", + "EventCode": "0x70", + "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS2.MEMWRNI", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10", + "EventCode": "0x81", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8", + "EventCode": "0x81", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9", + "EventCode": "0x81", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10", + "EventCode": "0x83", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8", + "EventCode": "0x83", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9", + "EventCode": "0x83", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10", + "EventCode": "0x89", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8", + "EventCode": "0x89", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9", + "EventCode": "0x89", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10", + "EventCode": "0x8B", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8", + "EventCode": "0x8B", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9", + "EventCode": "0x8B", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10", + "EventCode": "0x85", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8", + "EventCode": "0x85", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9", + "EventCode": "0x85", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10", + "EventCode": "0x87", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8", + "EventCode": "0x87", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9", + "EventCode": "0x87", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10", + "EventCode": "0x8D", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8", + "EventCode": "0x8D", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9", + "EventCode": "0x8D", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10", + "EventCode": "0x8F", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8", + "EventCode": "0x8F", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9", + "EventCode": "0x8F", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", + "PerPkg": "1", + "PublicDescription": "CHA to iMC Bypass : Intermediate bypass Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the intermediate bypass.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Bypass : Not Taken", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", + "PerPkg": "1", + "PublicDescription": "CHA to iMC Bypass : Not Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Bypass : Taken", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN", + "PerPkg": "1", + "PublicDescription": "CHA to iMC Bypass : Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the full bypass.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Clockticks of the uncore caching and home agent (CHA)", + "EventName": "UNC_CHA_CLOCKTICKS", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Clockticks", + "EventCode": "0xc0", + "EventName": "UNC_CHA_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0xf2", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Any Single Snoop", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_ONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Any Single Snoop : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0xf1", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Multiple Core Requests", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Multiple Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x42", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Single Core Requests", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.CORE_ONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Single Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x41", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Multiple Eviction", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Multiple Eviction : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x82", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Single Eviction", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Single Eviction : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x81", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Multiple External Snoops", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Multiple External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x22", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Single External Snoops", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_ONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Single External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Multiple Snoop Targets from Remote", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.REMOTE_GTONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Multiple Snoop Targets from Remote : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x12", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Single Snoop Target from Remote", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.REMOTE_ONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Single Snoop Target from Remote : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Counter 0 Occupancy", + "EventCode": "0x1F", + "EventName": "UNC_CHA_COUNTER0_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Counter 0 Occupancy : Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6E", + "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6E", + "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6E", + "EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.GO", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.NOP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.PULL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Multi-socket cacheline directory state lookups : Snoop Not Needed", + "EventCode": "0x53", + "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP", + "PerPkg": "1", + "PublicDescription": "Multi-socket cacheline directory state lookups : Snoop Not Needed : Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to. : Filters for transactions that did not have to send any snoops because the directory was clean.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Multi-socket cacheline directory state lookups : Snoop Needed", + "EventCode": "0x53", + "EventName": "UNC_CHA_DIR_LOOKUP.SNP", + "PerPkg": "1", + "PublicDescription": "Multi-socket cacheline directory state lookups : Snoop Needed : Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to. : Filters for transactions that had to send one or more snoops because the directory was not clean.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Multi-socket cacheline directory state updates; memory write due to directory update from the home agent (HA) pipe", + "EventCode": "0x54", + "EventName": "UNC_CHA_DIR_UPDATE.HA", + "PerPkg": "1", + "PublicDescription": "Counts only multi-socket cacheline directory state updates memory writes issued from the home agent (HA) pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Multi-socket cacheline directory state updates; memory write due to directory update from (table of requests) TOR pipe", + "EventCode": "0x54", + "EventName": "UNC_CHA_DIR_UPDATE.TOR", + "PerPkg": "1", + "PublicDescription": "Counts only multi-socket cacheline directory state updates due to memory writes issued from the table of requests (TOR) pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Distress signal asserted : DPT Local", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_LOCAL", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Distress signal asserted : DPT Remote", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_NONLOCAL", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Distress signal asserted : DPT Stalled - IV", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_IV", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_NOCRD", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Distress signal asserted : Horizontal", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.HORZ", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Distress signal asserted : PMM Local", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.PMM_LOCAL", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Distress signal asserted : PMM Remote", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.PMM_NONLOCAL", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Distress signal asserted : Vertical", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.VERT", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Down", + "EventCode": "0xBA", + "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Up", + "EventCode": "0xBA", + "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.EX_RDS", + "PerPkg": "1", + "PublicDescription": "Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state. This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*).", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket ownership read requests that hit in S state.", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ", + "PerPkg": "1", + "PublicDescription": "Counts Number of Hits in HitMe Cache : Remote socket ownership read requests that hit in S state. : Shared hit and op is RdInvOwn, RdInv, Inv*", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket WBMtoE requests", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.WBMTOE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket writeback to I or S requests", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S", + "PerPkg": "1", + "PublicDescription": "Counts Number of Hits in HitMe Cache : Remote socket writeback to I or S requests : op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed : Remote socket read requests", + "EventCode": "0x5E", + "EventName": "UNC_CHA_HITME_LOOKUP.READ", + "PerPkg": "1", + "PublicDescription": "Counts Number of times HitMe Cache is accessed : Remote socket read requests : op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed : Remote socket write (i.e. writeback) requests", + "EventCode": "0x5E", + "EventName": "UNC_CHA_HITME_LOOKUP.WRITE", + "PerPkg": "1", + "PublicDescription": "Counts Number of times HitMe Cache is accessed : Remote socket write (i.e. writeback) requests : op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests that are not to shared line", + "EventCode": "0x60", + "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN", + "PerPkg": "1", + "PublicDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests that are not to shared line : No SF/LLC HitS/F and op is RdInvOwn", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket read or invalidate requests", + "EventCode": "0x60", + "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV", + "PerPkg": "1", + "PublicDescription": "Counts Number of Misses in HitMe Cache : Remote socket read or invalidate requests : op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests to shared line", + "EventCode": "0x60", + "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN", + "PerPkg": "1", + "PublicDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests to shared line : SF/LLC HitS/F and op is RdInvOwn", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Deallocate HitME$ on Reads without RspFwdI*", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", + "PerPkg": "1", + "PublicDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request : Received RspFwdI* for a local request, but converted HitME$ to SF entry", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache on RdInvOwn even if not RspFwdI*", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM", + "PerPkg": "1", + "PublicDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request : Updated HitME$ on RspFwdI* or local HitM/E received for a remote request", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache to SHARed", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.SHARED", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Left and Even", + "EventCode": "0xB6", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", + "EventCode": "0xB6", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Right and Even", + "EventCode": "0xB6", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", + "EventCode": "0xB6", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "EventCode": "0xBB", + "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "EventCode": "0xBB", + "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "EventCode": "0xBB", + "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "EventCode": "0xBB", + "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "EventCode": "0xB7", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "EventCode": "0xB7", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "EventCode": "0xB7", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "EventCode": "0xB7", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Left and Even", + "EventCode": "0xB8", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", + "EventCode": "0xB8", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Right and Even", + "EventCode": "0xB8", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", + "EventCode": "0xB8", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal IV Ring in Use : Left", + "EventCode": "0xB9", + "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal IV Ring in Use : Right", + "EventCode": "0xB9", + "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Normal priority reads issued to the memory controller from the CHA", + "EventCode": "0x59", + "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", + "PerPkg": "1", + "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "HA to iMC Reads Issued : ISOCH", + "EventCode": "0x59", + "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY", + "PerPkg": "1", + "PublicDescription": "HA to iMC Reads Issued : ISOCH : Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", + "PerPkg": "1", + "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to any of the memory controller channels.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "PerPkg": "1", + "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line : Counts the total number of full line writes issued from the HA into the memory controller.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "PerPkg": "1", + "PublicDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH : Counts the total number of full line writes issued from the HA into the memory controller.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "PerPkg": "1", + "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial : Counts the total number of full line writes issued from the HA into the memory controller.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Any Request", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.", + "UMask": "0x1fffff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : All transactions from Remote Agents", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.ALL_REMOTE", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : All transactions from Remote Agents : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x1e20ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : All Request Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.ANY_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : All Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local or remote transaction to the LLC, including prefetch.", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE", + "PerPkg": "1", + "UMask": "0x1bd0ff", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE_LOCAL", + "PerPkg": "1", + "UMask": "0x19d0ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Code Reads", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Code Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x1bd0ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : CRd Request Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : CRd Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : CRd Requests that come from the local socket (usually the core)", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.", + "UMask": "0x19d0ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Code Read Misses", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_MISS", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Code Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x1bd001", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : CRd Requests that come from a Remote socket.", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.", + "UMask": "0x1a10ff", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE_REMOTE", + "PerPkg": "1", + "UMask": "0x1a10ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Local request Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Local request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local transaction to the LLC, including prefetches from the Core", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD", + "PerPkg": "1", + "UMask": "0x1bc1ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions", + "UMask": "0x1bc1ff", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL", + "PerPkg": "1", + "UMask": "0x1fc1ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Data Read Request Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Data Read Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Read transactions.", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request that come from the local socket (usually the core)", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions", + "UMask": "0x19c1ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Data Read Misses", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Data Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x1bc101", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Requests that come from a Remote socket", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions", + "UMask": "0x1a01ff", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DMND_READ_LOCAL", + "PerPkg": "1", + "UMask": "0x841ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : E State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.E", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Exclusive State", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : F State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : F State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Forward State", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Flush or Invalidate Requests", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.", + "UMask": "0x1a44ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Flush or Invalidate Requests that come from the local socket (usually the core)", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV_LOCAL", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.", + "UMask": "0x1844ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Flush or Invalidate requests that come from a Remote socket.", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV_REMOTE", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.", + "UMask": "0x1a04ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Flush or Invalidate Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Flush or Invalidate Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : I State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.I", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : I State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Miss", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Prefetch requests to the LLC that come from the local socket (usually the core)", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions", + "UMask": "0x189dff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Local LLC prefetch requests (from LLC) Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Local LLC prefetch requests (from LLC) Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local LLC prefetch to the LLC", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LLC_PF_LOCAL", + "PerPkg": "1", + "UMask": "0x189dff", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOC_HOM", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCALLY_HOMED_ADDRESS", + "PerPkg": "1", + "UMask": "0xbdfff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Transactions homed locally Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Transactions homed locally Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC.", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Transactions homed locally", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOC_HOM", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Transactions homed locally : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC.", + "UMask": "0xbdfff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : M State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.M", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : M State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Modified State", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : All Misses", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : All Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x1fe001", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Write Request Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Write Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Writeback transactions to the LLC This includes all write transactions -- both Cacheable and UC.", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Remote non-snoop request Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.PREF_OR_DMND_REMOTE_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Remote non-snoop request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Non-snoop transactions to the LLC from remote agent", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Reads", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x1bd9ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_LOC_HOM", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x9d9ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_REM_HOM", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x11d9ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Read Misses", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x1bd901", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Locally HOMed Read Misses", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_LOC_HOM", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Locally HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0xbd901", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Remotely HOMed Read Misses", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_REM_HOM", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Remotely HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x13d901", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_OR_SNOOP_REMOTE_MISS_REM_HOM", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x161901", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_REMOTE_LOC_HOM", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0xa19ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Reads that Hit the Snoop Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_SF_HIT", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Reads that Hit the Snoop Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x1bd90e", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REM_HOM", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTELY_HOMED_ADDRESS", + "PerPkg": "1", + "UMask": "0x15dfff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Transactions homed remotely Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Transactions homed remotely Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Remote snoop request Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Remote snoop request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Snoop transactions to the LLC from remote agent", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Snoop Requests from a Remote Socket", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.", + "UMask": "0x1c19ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Transactions homed remotely", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REM_HOM", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Transactions homed remotely : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC", + "UMask": "0x15dfff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : RFO Requests", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.", + "UMask": "0x1bc8ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : RFO Request Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : RFO Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : RFO Requests that come from the local socket (usually the core)", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO_LOCAL", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.", + "UMask": "0x19c8ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : RFO Misses", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO_MISS", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : RFO Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x1bc801", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.RFO_LOCAL", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO_PREF_LOCAL", + "PerPkg": "1", + "UMask": "0x888ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : RFO Requests that come from a Remote socket.", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO_REMOTE", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.", + "UMask": "0x1a08ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : S State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.S", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Shared State", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : SnoopFilter - E State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.SF_E", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : SnoopFilter - E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit Exclusive State", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : SnoopFilter - H State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.SF_H", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : SnoopFilter - H State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit HitMe State", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : SnoopFilter - S State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.SF_S", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : SnoopFilter - S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit Shared State", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Filters Requests for those that write info into the cache", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Write Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.", + "UMask": "0x1a42ff", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL", + "PerPkg": "1", + "UMask": "0x842ff", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_REMOTE", + "PerPkg": "1", + "UMask": "0x17c2ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : All Lines Victimized", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.ALL", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : All Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0xf", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Lines in E state", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Lines in E state : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Local - All Lines", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Local - All Lines : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x200f", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Local - Lines in E State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Local - Lines in E State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x2002", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Local - Lines in M State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Local - Lines in M State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x2001", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Local Only", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Local Only : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Local - Lines in S State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Local - Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x2004", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Lines in M state", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Lines in M state : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Remote - All Lines", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Remote - All Lines : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x800f", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Remote - Lines in E State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Remote - Lines in E State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x8002", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Remote - Lines in M State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Remote - Lines in M State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x8001", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Remote Only", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ONLY", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Remote Only : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Remote - Lines in S State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Remote - Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x8004", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Lines in S State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc : CV0 Prefetch Miss", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.CV0_PREF_MISS", + "PerPkg": "1", + "PublicDescription": "Cbo Misc : CV0 Prefetch Miss : Miscellaneous events in the Cbo.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc : CV0 Prefetch Victim", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.CV0_PREF_VIC", + "PerPkg": "1", + "PublicDescription": "Cbo Misc : CV0 Prefetch Victim : Miscellaneous events in the Cbo.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Number of times that an RFO hit in S state.", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.RFO_HIT_S", + "PerPkg": "1", + "PublicDescription": "Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc : Silent Snoop Eviction", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE", + "PerPkg": "1", + "PublicDescription": "Cbo Misc : Silent Snoop Eviction : Miscellaneous events in the Cbo. : Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc : Write Combining Aliasing", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.WC_ALIASING", + "PerPkg": "1", + "PublicDescription": "Cbo Misc : Write Combining Aliasing : Miscellaneous events in the Cbo. : Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0", + "EventCode": "0xE6", + "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1", + "EventCode": "0xE6", + "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast : Local InvItoE", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB.LOCAL_INVITOE", + "PerPkg": "1", + "PublicDescription": "OSB Snoop Broadcast : Local InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast : Local Rd", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB.LOCAL_READ", + "PerPkg": "1", + "PublicDescription": "OSB Snoop Broadcast : Local Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast : Off", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB.OFF_PWRHEURISTIC", + "PerPkg": "1", + "PublicDescription": "OSB Snoop Broadcast : Off : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast : Remote Rd", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB.REMOTE_READ", + "PerPkg": "1", + "PublicDescription": "OSB Snoop Broadcast : Remote Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast : Remote Rd InvItoE", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB.REMOTE_READINVITOE", + "PerPkg": "1", + "PublicDescription": "OSB Snoop Broadcast : Remote Rd InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB.RFO_HITS_SNP_BCAST", + "PerPkg": "1", + "PublicDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.ADEGRCREDIT", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.AKEGRCREDIT", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.ALLRSFWAYS_RES", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.BLEGRCREDIT", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.FSF_VICP", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLOWSNP", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLWAYRSV", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_PAMATCH", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_WAYMATCH", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.HACREDIT", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.IDX_INPIPE", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.IPQ_SETMATCH_VICP", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.IRQ_PMM", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.IRQ_SETMATCH_VICP", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.ISMQ_SETMATCH_VICP", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.IVEGRCREDIT", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.LLC_WAYS_RES", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.NOTALLOWSNOOP", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.ONE_FSF_VIC", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.ONE_RSP_CON", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.PMM_MEMMODE_TORMATCH_MULTI", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.PMM_MEMMODE_TOR_MATCH", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.PRQ_PMM", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.PTL_INPIPE", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.RMW_SETMATCH", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.RRQ_SETMATCH_VICP", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.SETMATCHENTRYWSCT", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.SF_WAYS_RES", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.TOPA_MATCH", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.TORID_MATCH_GO_P", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_REQ", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_RSP", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCB", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCS", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_RSP", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_WB", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.WAY_MATCH", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL", + "EventCode": "0x65", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE", + "EventCode": "0x65", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT", + "EventCode": "0x65", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC", + "EventCode": "0x64", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC", + "PerPkg": "1", + "PublicDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC : NM evictions due to another read to the same near memory set in the LLC.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC", + "EventCode": "0x64", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF", + "PerPkg": "1", + "PublicDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC : NM evictions due to another read to the same near memory set in the SF.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in TOR", + "EventCode": "0x64", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR", + "PerPkg": "1", + "PublicDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in TOR : No Reject in the CHA due to a pending read to the same near memory set in the TOR.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC", + "EventCode": "0x70", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR", + "EventCode": "0x70", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI", + "EventCode": "0x70", + "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT", + "EventCode": "0x66", + "EventName": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_QOS.REJ_IRQ", + "EventCode": "0x66", + "EventName": "UNC_CHA_PMM_QOS.REJ_IRQ", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP", + "EventCode": "0x66", + "EventName": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_QOS.SLOW_INSERT", + "EventCode": "0x66", + "EventName": "UNC_CHA_PMM_QOS.SLOW_INSERT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE", + "EventCode": "0x66", + "EventName": "UNC_CHA_PMM_QOS.THROTTLE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_IRQ", + "EventCode": "0x66", + "EventName": "UNC_CHA_PMM_QOS.THROTTLE_IRQ", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_PRQ", + "EventCode": "0x66", + "EventName": "UNC_CHA_PMM_QOS.THROTTLE_PRQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO", + "EventCode": "0x67", + "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO", + "PerPkg": "1", + "PublicDescription": ": count # of FAST TOR Request inserted to ha_tor_req_fifo", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO", + "EventCode": "0x67", + "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO", + "PerPkg": "1", + "PublicDescription": ": count # of SLOW TOR Request inserted to ha_pmm_tor_req_fifo", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC0", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC0 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 0 only.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC1", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC1 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 1 only.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC10", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC10", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC10 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 10 only.", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC11", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC11", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC11 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 11 only.", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC12", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC12", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC12 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 12 only.", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC13", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC13", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC13 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 13 only.", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC2", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC2 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 2 only.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC3", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC3 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 3 only.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC4", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC4 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 4 only.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC5", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC5 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 5 only.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC6", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC6", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC6 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 6 only.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC7", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC7", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC7 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 7 only.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC8", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC8", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC8 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 8 only.", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC9", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC9", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC9 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 9 only.", + "Unit": "CHA" + }, + { + "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and remote INVITOE requests sent to the CHA's home agent", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.INVITOE", + "PerPkg": "1", + "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "UMask": "0x30", + "Unit": "CHA" + }, + { + "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and are sent to the CHA's home agent", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Remote INVITOE requests (exclusive ownership of a cache line without receiving data) sent to the CHA's home agent", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Local read requests that miss the SF/LLC and remote read requests sent to the CHA's home agent", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS", + "PerPkg": "1", + "PublicDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) .", + "UMask": "0x3", + "Unit": "CHA" + }, + { + "BriefDescription": "Local read requests that miss the SF/LLC and are sent to the CHA's home agent", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Remote read requests sent to the CHA's home agent", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Local write requests that miss the SF/LLC and remote write requests sent to the CHA's home agent", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES", + "PerPkg": "1", + "PublicDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", + "UMask": "0xc", + "Unit": "CHA" + }, + { + "BriefDescription": "Local write requests that miss the SF/LLC and are sent to the CHA's home agent", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Remote write requests sent to the CHA's home agent", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD", + "EventCode": "0xAC", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK", + "EventCode": "0xAC", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL", + "EventCode": "0xAC", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV", + "EventCode": "0xAC", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : AD", + "EventCode": "0xAA", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core", + "EventCode": "0xAA", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.", + "EventCode": "0xAA", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.AKC", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core", + "EventCode": "0xAA", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.", + "EventCode": "0xAA", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : AD", + "EventCode": "0xAD", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : AK", + "EventCode": "0xAD", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1", + "EventCode": "0xAD", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : BL", + "EventCode": "0xAD", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : IV", + "EventCode": "0xAD", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : AD", + "EventCode": "0xAB", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core", + "EventCode": "0xAB", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring", + "EventCode": "0xAB", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AKC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core", + "EventCode": "0xAB", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.", + "EventCode": "0xAB", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Source Throttle", + "EventCode": "0xae", + "EventName": "UNC_CHA_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : IPQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IPQ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Allocations : IPQ : Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : IRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IRQ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Allocations : IRQ : Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Allocations : IRQ Rejected : Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : PRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.PRQ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : PRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : RRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.RRQ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Allocations : RRQ : Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : WBQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.WBQ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Allocations : WBQ : Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Allow Snoop", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : ANY0", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0", + "PerPkg": "1", + "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IPQ0 Reject counter was true", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : HA", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC Victim", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : SF Victim", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Victim", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IRQ0 Reject counter was true", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way : Way conflict with another request that caused the reject", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC Victim", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Victim", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 1 : ANY0", + "EventCode": "0x25", + "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 1 : HA", + "EventCode": "0x25", + "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 1 : ANY0", + "EventCode": "0x2D", + "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 1 : HA", + "EventCode": "0x2D", + "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy : IPQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Occupancy : IPQ : Counts number of entries in the specified Ingress queue in each cycle.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy : IRQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Occupancy : IRQ : Counts number of entries in the specified Ingress queue in each cycle.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy : RRQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Occupancy : RRQ : Counts number of entries in the specified Ingress queue in each cycle.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy : WBQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Occupancy : WBQ : Counts number of entries in the specified Ingress queue in each cycle.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : AD REQ on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : AD REQ on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a request", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : AD RSP on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : AD RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a response", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : Non UPI AK Request", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : Non UPI AK Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject AK ring message", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : BL NCB on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : BL NCB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCB", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : BL NCS on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : BL NCS on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCS", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : BL RSP on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : BL RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a response", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : BL WB on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : BL WB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : Non UPI IV Request", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : Non UPI IV Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject IV ring message", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : Allow Snoop", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 1 : Allow Snoop : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : ANY0", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 1 : ANY0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Any condition listed in the Other0 Reject counter was true", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : HA", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 1 : HA : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : LLC OR SF Way", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 1 : LLC OR SF Way : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Way conflict with another request that caused the reject", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : LLC Victim", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 1 : LLC Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : PhyAddr Match", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 1 : PhyAddr Match : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Address match with an outstanding request that was rejected.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : SF Victim", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 1 : SF Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Requests did not generate Snoop filter victim", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : Victim", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 1 : Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the PRQ0 Reject counter was true", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC Victim", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Victim", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : AD REQ on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a request", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : AD RSP on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a response", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Request", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : Non UPI AK Request : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject AK ring message", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : BL NCB on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCB", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : BL NCS on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCS", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : BL RSP on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a response", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : BL WB on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Request", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : Non UPI IV Request : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject IV ring message", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : Allow Snoop : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : ANY0", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : ANY0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Any condition listed in the WBQ0 Reject counter was true", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : HA", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : HA : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : LLC OR SF Way : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Way conflict with another request that caused the reject", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : LLC Victim", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : LLC Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : PhyAddr Match : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Address match with an outstanding request that was rejected.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : SF Victim", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : SF Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Requests did not generate Snoop filter victim", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : Victim", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 0 : AD REQ on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No AD VN0 credit for generating a request", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 0 : AD RSP on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No AD VN0 credit for generating a response", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 0 : Non UPI AK Request", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Can't inject AK ring message", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 0 : BL NCB on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for NCB", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 0 : BL NCS on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for NCS", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 0 : BL RSP on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for generating a response", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 0 : BL WB on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 0 : Non UPI IV Request", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Can't inject IV ring message", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 1 : Allow Snoop", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 1 : Allow Snoop : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 1 : ANY0", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Any condition listed in the RRQ0 Reject counter was true", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 1 : HA", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 1 : HA : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 1 : LLC OR SF Way", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 1 : LLC OR SF Way : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Way conflict with another request that caused the reject", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 1 : LLC Victim", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 1 : LLC Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 1 : PhyAddr Match", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 1 : PhyAddr Match : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Address match with an outstanding request that was rejected.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 1 : SF Victim", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 1 : SF Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Requests did not generate Snoop filter victim", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects - Set 1 : Victim", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM", + "PerPkg": "1", + "PublicDescription": "RRQ Rejects - Set 1 : Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 0 : AD REQ on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No AD VN0 credit for generating a request", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 0 : AD RSP on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No AD VN0 credit for generating a response", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 0 : Non UPI AK Request", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Can't inject AK ring message", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 0 : BL NCB on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for NCB", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 0 : BL NCS on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for NCS", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 0 : BL RSP on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for generating a response", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 0 : BL WB on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 0 : Non UPI IV Request", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Can't inject IV ring message", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 1 : Allow Snoop", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 1 : Allow Snoop : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 1 : ANY0", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Any condition listed in the WBQ0 Reject counter was true", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 1 : HA", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 1 : HA : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 1 : LLC OR SF Way", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 1 : LLC OR SF Way : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Way conflict with another request that caused the reject", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 1 : LLC Victim", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 1 : LLC Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 1 : PhyAddr Match", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 1 : PhyAddr Match : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Address match with an outstanding request that was rejected.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 1 : SF Victim", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 1 : SF Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Requests did not generate Snoop filter victim", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects - Set 1 : Victim", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM", + "PerPkg": "1", + "PublicDescription": "WBQ Rejects - Set 1 : Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - All", + "EventCode": "0xE5", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Credited", + "EventCode": "0xE5", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", + "EventCode": "0xE5", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - All", + "EventCode": "0xE5", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Credited", + "EventCode": "0xE5", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", + "EventCode": "0xE5", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - All", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - Credited", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AK", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - All", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - Credited", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : IV", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - All", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Credited", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : AK", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - All", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Credited", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : IFV - Credited", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : IV", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation", + "EventCode": "0xe4", + "EventName": "UNC_CHA_RxR_CRD_STARVED_1", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - All", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - Credited", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AK", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - All", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - Credited", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : IV", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - All", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AK", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - All", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : IV", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop filter capacity evictions for E-state entries.", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.E_STATE", + "PerPkg": "1", + "PublicDescription": "Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop filter capacity evictions for M-state entries.", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.M_STATE", + "PerPkg": "1", + "PublicDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop filter capacity evictions for S-state entries.", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.S_STATE", + "PerPkg": "1", + "PublicDescription": "Counts snoop filter capacity evictions for entries tracking shared lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : All", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.ALL", + "PerPkg": "1", + "PublicDescription": "Snoops Sent : All : Counts the number of snoops issued by the HA.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : Broadcast snoops for Local Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL", + "PerPkg": "1", + "PublicDescription": "Snoops Sent : Broadcast snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA responding to local requests", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : Broadcast snoops for Remote Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE", + "PerPkg": "1", + "PublicDescription": "Snoops Sent : Broadcast snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA responding to remote requests", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : Directed snoops for Local Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", + "PerPkg": "1", + "PublicDescription": "Snoops Sent : Directed snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA responding to local requests", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : Directed snoops for Remote Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", + "PerPkg": "1", + "PublicDescription": "Snoops Sent : Directed snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA responding to remote requests", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : Snoops sent for Local Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL", + "PerPkg": "1", + "PublicDescription": "Snoops Sent : Snoops sent for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA responding to local requests", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : Snoops sent for Remote Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE", + "PerPkg": "1", + "PublicDescription": "Snoops Sent : Snoops sent for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA responding to remote requests", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received : RSPCNFLCT*", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCT", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received : RSPCNFLCT* : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for snoops responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received : RspFwd", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received : RspFwd : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of RspFwd to a CA request. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received : Rsp*Fwd*WB", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPFWDWB", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received : Rsp*Fwd*WB : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received : RspI", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPI", + "PerPkg": "1", + "PublicDescription": "Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data).", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received : RspIFwd", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD", + "PerPkg": "1", + "PublicDescription": "Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received : RspS", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPS", + "PerPkg": "1", + "PublicDescription": "Counts when a transaction with the opcode type RspS Snoop Response was received which indicates when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received : RspSFwd", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD", + "PerPkg": "1", + "PublicDescription": "Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received : Rsp*WB", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPWB", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received : Rsp*WB : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of RspIWB or RspSWB. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : RspCnflct", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received Local : RspCnflct : Number of snoop responses received for a Local request : Filters for snoops responses of RspConflict to local CA requests. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : RspFwd", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received Local : RspFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspFwd to local CA requests. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received Local : Rsp*FWD*WB : Number of snoop responses received for a Local request : Filters for a snoop response of Rsp*Fwd*WB to local CA requests. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : RspI", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received Local : RspI : Number of snoop responses received for a Local request : Filters for snoops responses of RspI to local CA requests. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : RspIFwd", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received Local : RspIFwd : Number of snoop responses received for a Local request : Filters for snoop responses of RspIFwd to local CA requests. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : RspS", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received Local : RspS : Number of snoop responses received for a Local request : Filters for snoop responses of RspS to local CA requests. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : RspSFwd", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received Local : RspSFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspSFwd to local CA requests. This is returned when a remote caching agent forwards data but holds on to its currently copy. This is common for data and code reads that hit in a remote socket in E or F state.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : Rsp*WB", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received Local : Rsp*WB : Number of snoop responses received for a Local request : Filters for a snoop response of RspIWB or RspSWB to local CA requests. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Misc Snoop Responses Received : MtoI RspIDataM", + "EventCode": "0x6B", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM", + "EventCode": "0x6B", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit LLC", + "EventCode": "0x6B", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit SF", + "EventCode": "0x6B", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit LLC", + "EventCode": "0x6B", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit SF", + "EventCode": "0x6B", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10", + "EventCode": "0xD1", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8", + "EventCode": "0xD1", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9", + "EventCode": "0xD1", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10", + "EventCode": "0xD3", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8", + "EventCode": "0xD3", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9", + "EventCode": "0xD3", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10", + "EventCode": "0xD5", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8", + "EventCode": "0xD5", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9", + "EventCode": "0xD5", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10", + "EventCode": "0xD7", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8", + "EventCode": "0xD7", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9", + "EventCode": "0xD7", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ALL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001ffff", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DDR4 Access", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DDR4 Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.DDR", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.DDR4", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : SF/LLC Evictions", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.EVICT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : SF/LLC Evictions : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just Hits", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.HIT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Just Hits : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All requests from iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CLFlushes issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8c7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CLFlushOpts issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CLFlushOpts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8d7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRDs issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRDs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc80fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; CRd Pref from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter", + "UMask": "0xc88fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc817ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc837ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc827ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8a7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc897ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc80ffd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc88ffd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc817fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to page walks that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc837fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc827fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8a7fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc897fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc47fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcccffd01", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCRD", + "PerPkg": "1", + "UMask": "0xcccffd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xccd7fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDRD", + "PerPkg": "1", + "UMask": "0xccd7fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xccc7fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc807fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc887fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores that hit in the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_SPECITOM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc57fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc47ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcd47ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcccfff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xccd7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xccc7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc80ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc80efe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc88ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc88efe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc88f7e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc80f7e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc817fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc837fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8178601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc816fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8168601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8168a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc827fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8a7fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8178a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc897fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8978601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; DRd Pref misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read prefetch from local IA that misses in the snoop filter", + "UMask": "0xc896fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8968601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8968a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8978a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; DRd Pref misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read prefetch from remote IA that misses in the snoop filter", + "UMask": "0xc8977e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8970601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8970a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8177e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8170601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8170a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", + "UMask": "0xc867fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", + "UMask": "0xc8678601", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_DRAM", + "PerPkg": "1", + "UMask": "0xc8678601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", + "UMask": "0xc8668601", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_DRAM", + "PerPkg": "1", + "UMask": "0xc8668601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", + "UMask": "0xc8668a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", + "UMask": "0xc8678a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", + "UMask": "0xc8670601", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_DRAM", + "PerPkg": "1", + "UMask": "0xc8670601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", + "UMask": "0xc8670a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc47fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcccffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xccd7fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xccc7fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8668601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8668a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86e8601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86e8a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", + "UMask": "0xc86ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", + "UMask": "0xc86f8601", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_DRAM", + "PerPkg": "1", + "UMask": "0xc86f8601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", + "UMask": "0xc86e8601", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DRAM", + "PerPkg": "1", + "UMask": "0xc86e8601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", + "UMask": "0xc86e8a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", + "UMask": "0xc86f8a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", + "UMask": "0xc86f0601", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DRAM", + "PerPkg": "1", + "UMask": "0xc86f0601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", + "UMask": "0xc86f0a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8670601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remote memory", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8670a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86f0601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86f0a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc807fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc806fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc887fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc886fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8877e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8077e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_SPECITOM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc57fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc877de01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc867fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8678601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8678a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86f8601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86f8a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc87fde01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc807ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc887ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc57ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE", + "PerPkg": "1", + "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc3fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WBEFtoIs issued by an IA Core. Non Modified Write Backs", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI", + "PerPkg": "1", + "PublicDescription": "WbEFtoIs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc37ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WBMtoEs issued by an IA Core. Non Modified Write Backs", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE", + "PerPkg": "1", + "PublicDescription": "WbMtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc2fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI", + "PerPkg": "1", + "PublicDescription": "WbMtoIs issued by iA Cores . (Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc27ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WBStoIs issued by an IA Core. Non Modified Write Backs", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI", + "PerPkg": "1", + "PublicDescription": "WbStoIs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc67ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc867ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All requests from IO Devices", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CLFlushes issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8c3ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All requests from IO Devices that hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc43fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcd43fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8f3fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc803fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc43ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcd43ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to locally HOMed memory", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcd42ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to remotely HOMed memory", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcd437f04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to locally HOMed memory", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc42ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to remotely HOMed memory", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc437f04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All requests from IO Devices that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc43fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcd43fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8f3fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc803fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8f3ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by IO Devices", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc803ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WbMtoIs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc23ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : IPQ", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IPQ", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : IPQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : IRQ - iA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : IRQ - iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From an iA Core", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : IRQ - Non iA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : IRQ - Non iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just ISOC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ISOC", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Just ISOC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just Local Targets", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Just Local Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All from Local iA and IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All from Local iA and IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests", + "UMask": "0xc000ff05", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All from Local iA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All from Local iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores", + "UMask": "0xc000ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All from Local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All from Local IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic", + "UMask": "0xc000ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just Misses", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.MISS", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Just Misses : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : MMCFG Access", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.MMCFG", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : MMCFG Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just NearMem", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.NEARMEM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Just NearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just NonCoherent", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.NONCOH", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Just NonCoherent : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just NotNearMem", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Just NotNearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : PMM Access", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.PMM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PMM Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : PRQ - IOSF", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PRQ - IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From a PCIe Device", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : PRQ - Non IOSF", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PRQ - Non IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just Remote Targets", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.REMOTE_TGT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Just Remote Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RRQ", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.RRQ", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RRQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WBQ", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.WBQ", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WBQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DDR4 Access", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DDR4 Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : SF/LLC Evictions", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : SF/LLC Evictions : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just Hits", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Just Hits : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All requests from iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8c7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8d7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRDs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc80fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; CRd Pref from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter", + "UMask": "0xc88fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc817ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc837ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc827ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8a7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc897ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc80ffd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc88ffd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc817fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc837fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc827fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8a7fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc897fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc47fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcccffd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xccd7fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xccc7fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc807fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc887fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc47ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcd47ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcccfff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xccd7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xccc7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc80ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc80efe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc88ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc88efe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc88f7e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc80f7e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc817fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc837fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8178601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc816fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8168601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8168a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc827fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8a7fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8178a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc897fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8978601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter", + "UMask": "0xc896fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8968601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8968a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8978a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter", + "UMask": "0xc8977e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8970601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8970a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8177e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8170601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8170a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", + "UMask": "0xc867fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", + "UMask": "0xc8678601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_LOCAL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", + "UMask": "0xc8668601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_LOCAL_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", + "UMask": "0xc8668a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", + "UMask": "0xc8678a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_REMOTE_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", + "UMask": "0xc8670601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_REMOTE_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", + "UMask": "0xc8670a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc47fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcccffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xccd7fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xccc7fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8668601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8668a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86e8601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86e8a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; WCiL misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", + "UMask": "0xc86ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; WCiL misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", + "UMask": "0xc86f8601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; WCiL misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", + "UMask": "0xc86e8601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; WCiL misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", + "UMask": "0xc86e8a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; WCiL misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", + "UMask": "0xc86f8a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; WCiL misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", + "UMask": "0xc86f0601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; WCiL misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", + "UMask": "0xc86f0a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8670601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8670a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86f0601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86f0a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc807fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc806fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc887fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc886fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8877e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8077e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_SPECITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores that missed the LLC: For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc57fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc877de01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc867fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8678601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8678a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86f8601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86f8a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc87fde01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc807ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc887ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc57ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc27ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc867ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All requests from IO Devices", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Devices", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8c3ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc43fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcd43fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8f3fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc803fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc43ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcd43ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc43fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcd43fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8f3fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc803fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8f3ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc803ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc23ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : IPQ", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : IPQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : IRQ - iA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : IRQ - iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From an iA Core", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : IRQ - Non iA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : IRQ - Non iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just ISOC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Just ISOC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just Local Targets", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Just Local Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All from Local iA and IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All from Local iA and IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests", + "UMask": "0xc000ff05", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All from Local iA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All from Local iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores", + "UMask": "0xc000ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All from Local IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic", + "UMask": "0xc000ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just Misses", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Just Misses : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : MMCFG Access", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : MMCFG Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just NearMem", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Just NearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just NonCoherent", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Just NonCoherent : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just NotNearMem", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Just NotNearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : PMM Access", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.PMM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PMM Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : PRQ - IOSF", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PRQ - IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From a PCIe Device", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : PRQ - Non IOSF", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PRQ - Non IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just Remote Targets", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.REMOTE_TGT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Just Remote Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - All", + "EventCode": "0xA6", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", + "EventCode": "0xA6", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", + "EventCode": "0xA6", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - All", + "EventCode": "0xA6", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", + "EventCode": "0xA6", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", + "EventCode": "0xA6", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - All", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AK", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - All", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : IV", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AK", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : IV", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AK", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : IV", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AK", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : IV", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All", + "EventCode": "0xA5", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited", + "EventCode": "0xA5", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK", + "EventCode": "0xA5", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited", + "EventCode": "0xA5", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All", + "EventCode": "0xA5", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited", + "EventCode": "0xA5", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV", + "EventCode": "0xA5", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : IV", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : IV", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_VERT_STARVED1.TGC", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Down and Even", + "EventCode": "0xB0", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Down and Odd", + "EventCode": "0xB0", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Up and Even", + "EventCode": "0xB0", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Up and Odd", + "EventCode": "0xB0", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Down and Even", + "EventCode": "0xB4", + "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", + "EventCode": "0xB4", + "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Up and Even", + "EventCode": "0xB4", + "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", + "EventCode": "0xB4", + "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Down and Even", + "EventCode": "0xB1", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Down and Odd", + "EventCode": "0xB1", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Up and Even", + "EventCode": "0xB1", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Up and Odd", + "EventCode": "0xB1", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Down and Even", + "EventCode": "0xB2", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Down and Odd", + "EventCode": "0xB2", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Up and Even", + "EventCode": "0xB2", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Up and Odd", + "EventCode": "0xB2", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical IV Ring in Use : Down", + "EventCode": "0xB3", + "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical IV Ring in Use : Up", + "EventCode": "0xB3", + "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Down and Even", + "EventCode": "0xB5", + "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", + "EventCode": "0xB5", + "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Up and Even", + "EventCode": "0xB5", + "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", + "EventCode": "0xB5", + "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "WbPushMtoI : Pushed to LLC", + "EventCode": "0x56", + "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC", + "PerPkg": "1", + "PublicDescription": "WbPushMtoI : Pushed to LLC : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was able to push WbPushMToI to LLC", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "WbPushMtoI : Pushed to Memory", + "EventCode": "0x56", + "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM", + "PerPkg": "1", + "PublicDescription": "WbPushMtoI : Pushed to Memory : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC0 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 0 only.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC1 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 1 only.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC10", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC10", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC10 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 10 only.", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC11", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC11", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC11 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 11 only.", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC12", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC12", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC12 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 12 only.", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC13", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC13", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC13 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 13 only.", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC2 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 2 only.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC3 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 3 only.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC4 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 4 only.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC5 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 5 only.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC6", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC6", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC6 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 6 only.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC7", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC7", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC7 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 7 only.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC8", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC8", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC8 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 8 only.", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC9", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC9", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC9 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 9 only.", + "Unit": "CHA" + }, + { + "BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT", + "PerPkg": "1", + "PublicDescription": "XPT Prefetches : Dropped (on 0?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD", + "PerPkg": "1", + "PublicDescription": "XPT Prefetches : Dropped (on 0?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT", + "PerPkg": "1", + "PublicDescription": "XPT Prefetches : Dropped (on 1?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD", + "PerPkg": "1", + "PublicDescription": "XPT Prefetches : Dropped (on 1?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "XPT Prefetches : Sent (on 0?)", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.SENT0", + "PerPkg": "1", + "PublicDescription": "XPT Prefetches : Sent (on 0?) : Number of XPT prefetches sent", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "XPT Prefetches : Sent (on 1?)", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.SENT1", + "PerPkg": "1", + "PublicDescription": "XPT Prefetches : Sent (on 1?) : Number of XPT prefetches sent", + "UMask": "0x10", + "Unit": "CHA" + } +] diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-interconnect.json new file mode 100644 index 000000000000..8ac5907762e1 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-interconnect.json @@ -0,0 +1,14571 @@ +[ + { + "BriefDescription": "Total Write Cache Occupancy : Any Source", + "EventCode": "0x0F", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Total Write Cache Occupancy : Any Source : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events. : Tracks all requests from any source port.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Total Write Cache Occupancy : Snoops", + "EventCode": "0x0F", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q", + "PerPkg": "1", + "PublicDescription": "Total Write Cache Occupancy : Snoops : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory.", + "EventCode": "0x0f", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", + "PerPkg": "1", + "PublicDescription": "Total IRP occupancy of inbound read and write requests to coherent memory. This is effectively the sum of read occupancy and write occupancy.", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Clockticks of the IO coherency tracker (IRP)", + "EventCode": "0x01", + "EventName": "UNC_I_CLOCKTICKS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops : CLFlush", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", + "PerPkg": "1", + "PublicDescription": "Coherent Ops : CLFlush : Counts the number of coherency related operations servied by the IRP", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.PCITOM", + "PerPkg": "1", + "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.RFO", + "PerPkg": "1", + "PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops : WbMtoI", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.WBMTOI", + "PerPkg": "1", + "PublicDescription": "Coherent Ops : WbMtoI : Counts the number of coherency related operations servied by the IRP", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "FAF RF full", + "EventCode": "0x17", + "EventName": "UNC_I_FAF_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.", + "EventCode": "0x18", + "EventName": "UNC_I_FAF_INSERTS", + "PerPkg": "1", + "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.", + "Unit": "IRP" + }, + { + "BriefDescription": "Occupancy of the IRP FAF queue.", + "EventCode": "0x19", + "EventName": "UNC_I_FAF_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.", + "Unit": "IRP" + }, + { + "BriefDescription": "FAF allocation -- sent to ADQ", + "EventCode": "0x16", + "EventName": "UNC_I_FAF_TRANSACTIONS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", + "EventCode": "0x20", + "EventName": "UNC_I_IRP_ALL.EVICTS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)", + "EventCode": "0x20", + "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", + "EventCode": "0x20", + "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary", + "EventCode": "0x1E", + "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary", + "EventCode": "0x1e", + "EventName": "UNC_I_MISC0.2ND_RD_INSERT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary", + "EventCode": "0x1e", + "EventName": "UNC_I_MISC0.2ND_WR_INSERT", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", + "EventCode": "0x1E", + "EventName": "UNC_I_MISC0.FAST_REJ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests", + "EventCode": "0x1e", + "EventName": "UNC_I_MISC0.FAST_REQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary", + "EventCode": "0x1E", + "EventName": "UNC_I_MISC0.FAST_XFER", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary", + "EventCode": "0x1E", + "EventName": "UNC_I_MISC0.PF_ACK_HINT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch", + "EventCode": "0x1E", + "EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Lost Forward", + "EventCode": "0x1F", + "EventName": "UNC_I_MISC1.LOST_FWD", + "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Received Invalid", + "EventCode": "0x1F", + "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", + "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Received Invalid : Secondary received a transfer that did not have sufficient MESI state", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Received Valid", + "EventCode": "0x1F", + "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", + "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Received Valid : Secondary received a transfer that did have sufficient MESI state", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line", + "EventCode": "0x1f", + "EventName": "UNC_I_MISC1.SLOW_E", + "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Slow Transfer of E Line : Secondary received a transfer that did have sufficient MESI state", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line", + "EventCode": "0x1f", + "EventName": "UNC_I_MISC1.SLOW_I", + "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Slow Transfer of I Line : Snoop took cacheline ownership before write from data was committed.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line", + "EventCode": "0x1f", + "EventName": "UNC_I_MISC1.SLOW_M", + "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Slow Transfer of M Line : Snoop took cacheline ownership before write from data was committed.", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line", + "EventCode": "0x1f", + "EventName": "UNC_I_MISC1.SLOW_S", + "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Slow Transfer of S Line : Secondary received a transfer that did not have sufficient MESI state", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Requests", + "EventCode": "0x14", + "EventName": "UNC_I_P2P_INSERTS", + "PerPkg": "1", + "PublicDescription": "P2P Requests : P2P requests from the ITC", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Occupancy", + "EventCode": "0x15", + "EventName": "UNC_I_P2P_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "P2P Occupancy : P2P B & S Queue Occupancy", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions : P2P completions", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions : match if local only", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.LOC", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions : match if local and target matches", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions : P2P Message", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.MSG", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions : P2P reads", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.RD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions : Match if remote only", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.REM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions : match if remote and target matches", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions : P2P Writes", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.WR", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO", + "UMask": "0x7e", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache", + "UMask": "0x74", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache", + "UMask": "0x72", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache", + "UMask": "0x78", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that miss the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_MISS", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that miss the IIO cache", + "UMask": "0x71", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : Hit E or S", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_ES", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : Hit I", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_I", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : Hit M", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_M", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : Miss", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.MISS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : SnpCode", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPCODE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : SnpData", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPDATA", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : SnpInv", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPINV", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count : Atomic", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.ATOMIC", + "PerPkg": "1", + "PublicDescription": "Inbound Transaction Count : Atomic : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of atomic transactions", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count : Other", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.OTHER", + "PerPkg": "1", + "PublicDescription": "Inbound Transaction Count : Other : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of 'other' kinds of transactions.", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count : Writes", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.WRITES", + "PerPkg": "1", + "PublicDescription": "Inbound Transaction Count : Writes : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound write (fast path) requests received by the IRP.", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "PerPkg": "1", + "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "AK Egress Allocations", + "EventCode": "0x0B", + "EventName": "UNC_I_TxC_AK_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL DRS Egress Cycles Full", + "EventCode": "0x05", + "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL DRS Egress Inserts", + "EventCode": "0x02", + "EventName": "UNC_I_TxC_BL_DRS_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL DRS Egress Occupancy", + "EventCode": "0x08", + "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCB Egress Cycles Full", + "EventCode": "0x06", + "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCB Egress Inserts", + "EventCode": "0x03", + "EventName": "UNC_I_TxC_BL_NCB_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCB Egress Occupancy", + "EventCode": "0x09", + "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCS Egress Cycles Full", + "EventCode": "0x07", + "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCS Egress Inserts", + "EventCode": "0x04", + "EventName": "UNC_I_TxC_BL_NCS_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCS Egress Occupancy", + "EventCode": "0x0A", + "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", + "EventCode": "0x1C", + "EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": ": Counts the number times when it is not possible to issue a request to the M2PCIe because there are no Egress Credits available on AD0, A1 or AD0&AD1 both. Stalls on both AD0 and AD1 will count as 2", + "Unit": "IRP" + }, + { + "BriefDescription": "No AD0 Egress Credits Stalls", + "EventCode": "0x1A", + "EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "No AD0 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD0 Egress Credits available.", + "Unit": "IRP" + }, + { + "BriefDescription": "No AD1 Egress Credits Stalls", + "EventCode": "0x1B", + "EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "No AD1 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD1 Egress Credits available.", + "Unit": "IRP" + }, + { + "BriefDescription": "No BL Egress Credit Stalls", + "EventCode": "0x1D", + "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "No BL Egress Credit Stalls : Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "EventCode": "0x0D", + "EventName": "UNC_I_TxS_DATA_INSERTS_NCB", + "PerPkg": "1", + "PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "EventCode": "0x0E", + "EventName": "UNC_I_TxS_DATA_INSERTS_NCS", + "PerPkg": "1", + "PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Request Queue Occupancy", + "EventCode": "0x0C", + "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Outbound Request Queue Occupancy : Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.", + "Unit": "IRP" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10", + "EventCode": "0x81", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8", + "EventCode": "0x81", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9", + "EventCode": "0x81", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10", + "EventCode": "0x83", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8", + "EventCode": "0x83", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9", + "EventCode": "0x83", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10", + "EventCode": "0x89", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8", + "EventCode": "0x89", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9", + "EventCode": "0x89", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10", + "EventCode": "0x8B", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8", + "EventCode": "0x8B", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9", + "EventCode": "0x8B", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10", + "EventCode": "0x85", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8", + "EventCode": "0x85", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9", + "EventCode": "0x85", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10", + "EventCode": "0x87", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8", + "EventCode": "0x87", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9", + "EventCode": "0x87", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10", + "EventCode": "0x8D", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8", + "EventCode": "0x8D", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9", + "EventCode": "0x8D", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10", + "EventCode": "0x8F", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8", + "EventCode": "0x8F", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9", + "EventCode": "0x8F", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC Bypass : Not Taken", + "EventCode": "0x22", + "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.NOT_TAKEN", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC Bypass : Taken", + "EventCode": "0x22", + "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.TAKEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC Bypass : Not Taken", + "EventCode": "0x21", + "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC Bypass : Taken", + "EventCode": "0x21", + "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Clockticks of the mesh to memory (M2M)", + "EventName": "UNC_M2M_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Clockticks", + "EventCode": "0xc0", + "EventName": "UNC_M2M_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles when direct to core mode, which bypasses the CHA, was disabled", + "EventCode": "0x24", + "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", + "EventCode": "0x60", + "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number of reads in which direct to core transaction was overridden", + "EventCode": "0x25", + "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden", + "EventCode": "0x28", + "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles when Direct2UPI was Disabled", + "EventCode": "0x27", + "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden", + "EventCode": "0x29", + "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE", + "PerPkg": "1", + "PublicDescription": "Clockticks of the mesh to PCI (M2P)", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit : On NonDirty Line in A State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit : On NonDirty Line in I State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit : On NonDirty Line in L State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit : On NonDirty Line in S State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit : On Dirty Line in A State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit : On Dirty Line in I State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit : On Dirty Line in L State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit : On Dirty Line in S State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in any state", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in A state", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in I state", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in S state", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss : On NonDirty Line in A State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss : On NonDirty Line in I State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss : On NonDirty Line in L State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss : On NonDirty Line in S State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss : On Dirty Line in A State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss : On Dirty Line in I State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss : On Dirty Line in L State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss : On Dirty Line in S State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode.", + "EventCode": "0x2e", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Distress signal asserted : DPT Local", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_LOCAL", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Distress signal asserted : DPT Remote", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_NONLOCAL", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Distress signal asserted : DPT Stalled - IV", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_IV", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_NOCRD", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Distress signal asserted : Horizontal", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.HORZ", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Distress signal asserted : PMM Local", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.PMM_LOCAL", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Distress signal asserted : PMM Remote", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.PMM_NONLOCAL", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Distress signal asserted : Vertical", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.VERT", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_DISTRESS_PMM", + "EventCode": "0xF2", + "EventName": "UNC_M2M_DISTRESS_PMM", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_DISTRESS_PMM_MEMMODE", + "EventCode": "0xF1", + "EventName": "UNC_M2M_DISTRESS_PMM_MEMMODE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Down", + "EventCode": "0xBA", + "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Up", + "EventCode": "0xBA", + "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Left and Even", + "EventCode": "0xB6", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", + "EventCode": "0xB6", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Right and Even", + "EventCode": "0xB6", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", + "EventCode": "0xB6", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "EventCode": "0xBB", + "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "EventCode": "0xBB", + "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "EventCode": "0xBB", + "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "EventCode": "0xBB", + "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "EventCode": "0xB7", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "EventCode": "0xB7", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "EventCode": "0xB7", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "EventCode": "0xB7", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Left and Even", + "EventCode": "0xB8", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", + "EventCode": "0xB8", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Right and Even", + "EventCode": "0xB8", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", + "EventCode": "0xB8", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal IV Ring in Use : Left", + "EventCode": "0xB9", + "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal IV Ring in Use : Right", + "EventCode": "0xB9", + "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - All Channels", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.ALL", + "PerPkg": "1", + "UMask": "0x704", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch0", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH0_ALL", + "PerPkg": "1", + "UMask": "0x104", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch0", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR", + "PerPkg": "1", + "UMask": "0x140", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch0", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH0_ISOCH", + "PerPkg": "1", + "UMask": "0x102", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch0", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH0_NORMAL", + "PerPkg": "1", + "UMask": "0x101", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - Ch0", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE", + "PerPkg": "1", + "UMask": "0x110", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : DDR - Ch0", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM", + "PerPkg": "1", + "UMask": "0x108", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : PMM - Ch0", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH0_TO_PMM", + "PerPkg": "1", + "PublicDescription": "M2M Reads Issued to iMC : PMM - Ch0 : Counts all PMM dimm read requests(full line) sent from M2M to iMC", + "UMask": "0x120", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch1", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH1_ALL", + "PerPkg": "1", + "UMask": "0x204", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch1", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR", + "PerPkg": "1", + "UMask": "0x240", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch1", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH1_ISOCH", + "PerPkg": "1", + "UMask": "0x202", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch1", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH1_NORMAL", + "PerPkg": "1", + "UMask": "0x201", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - Ch1", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE", + "PerPkg": "1", + "UMask": "0x210", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : DDR - Ch1", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM", + "PerPkg": "1", + "UMask": "0x208", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : PMM - Ch1", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH1_TO_PMM", + "PerPkg": "1", + "PublicDescription": "M2M Reads Issued to iMC : PMM - Ch1 : Counts all PMM dimm read requests(full line) sent from M2M to iMC", + "UMask": "0x220", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch2", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH2_FROM_TGR", + "PerPkg": "1", + "UMask": "0x440", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : From TGR - All Channels", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.FROM_TGR", + "PerPkg": "1", + "UMask": "0x740", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - All Channels", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.ISOCH", + "PerPkg": "1", + "UMask": "0x702", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - All Channels", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.NORMAL", + "PerPkg": "1", + "UMask": "0x701", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - All Channels", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_CACHE", + "PerPkg": "1", + "UMask": "0x710", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : DDR - All Channels", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_MEM", + "PerPkg": "1", + "UMask": "0x708", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : PMM - All Channels", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.TO_PMM", + "PerPkg": "1", + "UMask": "0x720", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : All Writes - All Channels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.ALL", + "PerPkg": "1", + "UMask": "0x1c10", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_ALL", + "PerPkg": "1", + "UMask": "0x410", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL", + "PerPkg": "1", + "UMask": "0x401", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH", + "PerPkg": "1", + "UMask": "0x404", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Ch0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_NI", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL", + "PerPkg": "1", + "UMask": "0x402", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH", + "PerPkg": "1", + "UMask": "0x408", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - Ch0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_CACHE", + "PerPkg": "1", + "UMask": "0x440", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : DDR - Ch0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM", + "PerPkg": "1", + "UMask": "0x420", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : PMM - Ch0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_PMM", + "PerPkg": "1", + "PublicDescription": "M2M Writes Issued to iMC : PMM - Ch0 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC", + "UMask": "0x480", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_ALL", + "PerPkg": "1", + "UMask": "0x810", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL", + "PerPkg": "1", + "UMask": "0x801", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH", + "PerPkg": "1", + "UMask": "0x804", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Ch1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_NI", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL", + "PerPkg": "1", + "UMask": "0x802", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH", + "PerPkg": "1", + "UMask": "0x808", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - Ch1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_CACHE", + "PerPkg": "1", + "UMask": "0x840", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : DDR - Ch1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_MEM", + "PerPkg": "1", + "UMask": "0x820", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : PMM - Ch1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_PMM", + "PerPkg": "1", + "PublicDescription": "M2M Writes Issued to iMC : PMM - Ch1 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC", + "UMask": "0x880", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : From TGR - All Channels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FROM_TGR", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - All Channels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FULL", + "PerPkg": "1", + "UMask": "0x1c01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - All Channels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH", + "PerPkg": "1", + "UMask": "0x1c04", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - All Channels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.NI", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - All Channels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.NI_MISS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - All Channels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", + "PerPkg": "1", + "UMask": "0x1c02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - All Channels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH", + "PerPkg": "1", + "UMask": "0x1c08", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - All Channels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_CACHE", + "PerPkg": "1", + "UMask": "0x1c40", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : DDR - All Channels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_MEM", + "PerPkg": "1", + "UMask": "0x1c20", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : PMM - All Channels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.TO_PMM", + "PerPkg": "1", + "UMask": "0x1c80", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts", + "EventCode": "0x64", + "EventName": "UNC_M2M_MIRR_WRQ_INSERTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy", + "EventCode": "0x65", + "EventName": "UNC_M2M_MIRR_WRQ_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0", + "EventCode": "0xE6", + "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1", + "EventCode": "0xE6", + "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Number Packet Header Matches : MC Match", + "EventCode": "0x4C", + "EventName": "UNC_M2M_PKT_MATCH.MC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Number Packet Header Matches : Mesh Match", + "EventCode": "0x4C", + "EventName": "UNC_M2M_PKT_MATCH.MESH", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS", + "EventCode": "0x73", + "EventName": "UNC_M2M_PREFCAM_CIS_DROPS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Full : All Channels", + "EventCode": "0x6B", + "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.ALLCH", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Full : Channel 0", + "EventCode": "0x6B", + "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Full : Channel 1", + "EventCode": "0x6B", + "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Full : Channel 2", + "EventCode": "0x6B", + "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Not Empty : All Channels", + "EventCode": "0x6C", + "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.ALLCH", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 0", + "EventCode": "0x6C", + "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 1", + "EventCode": "0x6C", + "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 2", + "EventCode": "0x6C", + "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA0_INVAL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA1_INVAL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_MISS_INVAL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_RSP_PDRESET", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA0_INVAL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA1_INVAL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_MISS_INVAL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_RSP_PDRESET", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_HITA0_INVAL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_HITA1_INVAL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_MISS_INVAL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_RSP_PDRESET", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped : UPI - Ch 0", + "EventCode": "0x6F", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_UPI", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped : XPT - Ch 0", + "EventCode": "0x6F", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped : UPI - Ch 1", + "EventCode": "0x6F", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_UPI", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped : XPT - Ch 1", + "EventCode": "0x6F", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped : UPI - Ch 2", + "EventCode": "0x6F", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH2_UPI", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped : XPT - Ch 2", + "EventCode": "0x6F", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH2_XPT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped : UPI - All Channels", + "EventCode": "0x6f", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.UPI_ALLCH", + "PerPkg": "1", + "UMask": "0x2a", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped : XPT - All Channels", + "EventCode": "0x6f", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH", + "PerPkg": "1", + "UMask": "0x15", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 0", + "EventCode": "0x74", + "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPTUPI", + "PerPkg": "1", + "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 0", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 1", + "EventCode": "0x74", + "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPTUPI", + "PerPkg": "1", + "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 2", + "EventCode": "0x74", + "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH2_XPTUPI", + "PerPkg": "1", + "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 2", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- All Channels", + "EventCode": "0x74", + "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPTUPI_ALLCH", + "PerPkg": "1", + "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - All Channels", + "UMask": "0x15", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 0", + "EventCode": "0x75", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPTUPI", + "PerPkg": "1", + "PublicDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 0", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 1", + "EventCode": "0x75", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPTUPI", + "PerPkg": "1", + "PublicDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 2", + "EventCode": "0x75", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH2_XPTUPI", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - All Channels", + "EventCode": "0x75", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPTUPI_ALLCH", + "PerPkg": "1", + "UMask": "0x15", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.ERRORBLK_RxC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.NOT_PF_SAD_REGION", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_AD_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_FULL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_HIT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_SECURE_DROP", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.RPQ_PROXY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.STOP_B2B", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.UPI_THRESH", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.WPQ_PROXY", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.XPT_THRESH", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.ERRORBLK_RxC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.NOT_PF_SAD_REGION", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_AD_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_FULL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_HIT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_SECURE_DROP", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.RPQ_PROXY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.STOP_B2B", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.UPI_THRESH", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.WPQ_PROXY", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.XPT_THRESH", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "EventCode": "0x72", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.ERRORBLK_RxC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "EventCode": "0x72", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.NOT_PF_SAD_REGION", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "EventCode": "0x72", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_AD_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "EventCode": "0x72", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_CAM_FULL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "EventCode": "0x72", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_CAM_HIT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "EventCode": "0x72", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_SECURE_DROP", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "EventCode": "0x72", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.RPQ_PROXY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "EventCode": "0x72", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.STOP_B2B", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "EventCode": "0x72", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.UPI_THRESH", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "EventCode": "0x72", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.WPQ_PROXY", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "EventCode": "0x72", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.XPT_THRESH", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0", + "EventCode": "0x6D", + "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_UPI", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0", + "EventCode": "0x6D", + "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 1", + "EventCode": "0x6D", + "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_UPI", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1", + "EventCode": "0x6D", + "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 2", + "EventCode": "0x6D", + "EventName": "UNC_M2M_PREFCAM_INSERTS.CH2_UPI", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 2", + "EventCode": "0x6D", + "EventName": "UNC_M2M_PREFCAM_INSERTS.CH2_XPT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels", + "EventCode": "0x6d", + "EventName": "UNC_M2M_PREFCAM_INSERTS.UPI_ALLCH", + "PerPkg": "1", + "UMask": "0x2a", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels", + "EventCode": "0x6D", + "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH", + "PerPkg": "1", + "UMask": "0x15", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Occupancy : All Channels", + "EventCode": "0x6A", + "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Occupancy : Channel 0", + "EventCode": "0x6A", + "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Occupancy : Channel 1", + "EventCode": "0x6A", + "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Occupancy : Channel 2", + "EventCode": "0x6A", + "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": ": All Channels", + "EventCode": "0x76", + "EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "M2M" + }, + { + "BriefDescription": ": Channel 0", + "EventCode": "0x76", + "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": ": Channel 1", + "EventCode": "0x76", + "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": ": Channel 2", + "EventCode": "0x76", + "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_RxC_CYCLES_NE", + "EventCode": "0x79", + "EventName": "UNC_M2M_PREFCAM_RxC_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "EventCode": "0x7A", + "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", + "EventCode": "0x7A", + "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT", + "EventCode": "0x7A", + "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", + "EventCode": "0x7A", + "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_RxC_INSERTS", + "EventCode": "0x78", + "EventName": "UNC_M2M_PREFCAM_RxC_INSERTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", + "EventCode": "0x77", + "EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD", + "EventCode": "0xAC", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK", + "EventCode": "0xAC", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL", + "EventCode": "0xAC", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV", + "EventCode": "0xAC", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : AD", + "EventCode": "0xAA", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core", + "EventCode": "0xAA", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.", + "EventCode": "0xAA", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.AKC", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core", + "EventCode": "0xAA", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.", + "EventCode": "0xAA", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : AD", + "EventCode": "0xAD", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : AK", + "EventCode": "0xAD", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1", + "EventCode": "0xAD", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : BL", + "EventCode": "0xAD", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : IV", + "EventCode": "0xAD", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : AD", + "EventCode": "0xAB", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core", + "EventCode": "0xAB", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring", + "EventCode": "0xAB", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AKC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core", + "EventCode": "0xAB", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.", + "EventCode": "0xAB", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Source Throttle", + "EventCode": "0xae", + "EventName": "UNC_M2M_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 0", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 1", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 2", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 0", + "EventCode": "0x4F", + "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 1", + "EventCode": "0x4F", + "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 2", + "EventCode": "0x4F", + "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 0", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 1", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 2", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Full", + "EventCode": "0x04", + "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Not Empty", + "EventCode": "0x03", + "EventName": "UNC_M2M_RxC_AD_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Allocations", + "EventCode": "0x01", + "EventName": "UNC_M2M_RxC_AD_INSERTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Occupancy", + "EventCode": "0x02", + "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches", + "EventCode": "0x77", + "EventName": "UNC_M2M_RxC_AD_PREF_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations", + "EventCode": "0x5C", + "EventName": "UNC_M2M_RxC_AK_WR_CMP", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Full", + "EventCode": "0x08", + "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Not Empty", + "EventCode": "0x07", + "EventName": "UNC_M2M_RxC_BL_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Allocations", + "EventCode": "0x05", + "EventName": "UNC_M2M_RxC_BL_INSERTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Occupancy", + "EventCode": "0x06", + "EventName": "UNC_M2M_RxC_BL_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - All", + "EventCode": "0xE5", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Credited", + "EventCode": "0xE5", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", + "EventCode": "0xE5", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - All", + "EventCode": "0xE5", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Credited", + "EventCode": "0xE5", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", + "EventCode": "0xE5", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - All", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - Credited", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AK", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - All", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - Credited", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : IV", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - All", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Credited", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : AK", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - All", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Credited", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : IFV - Credited", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : IV", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation", + "EventCode": "0xe4", + "EventName": "UNC_M2M_RxR_CRD_STARVED_1", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - All", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - Credited", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AK", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - All", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - Credited", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : IV", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - All", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AK", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - All", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : IV", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS", + "EventCode": "0x33", + "EventName": "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS", + "EventCode": "0x34", + "EventName": "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Retry - Mem Mirroring Mode", + "EventCode": "0x35", + "EventName": "UNC_M2M_SCOREBOARD_BL_RETRY_ACCEPTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Retry - Mem Mirroring Mode", + "EventCode": "0x36", + "EventName": "UNC_M2M_SCOREBOARD_BL_RETRY_REJECTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Scoreboard Accepts", + "EventCode": "0x2F", + "EventName": "UNC_M2M_SCOREBOARD_RD_ACCEPTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Scoreboard Rejects", + "EventCode": "0x30", + "EventName": "UNC_M2M_SCOREBOARD_RD_REJECTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Scoreboard Accepts", + "EventCode": "0x31", + "EventName": "UNC_M2M_SCOREBOARD_WR_ACCEPTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Scoreboard Rejects", + "EventCode": "0x32", + "EventName": "UNC_M2M_SCOREBOARD_WR_REJECTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10", + "EventCode": "0xD1", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8", + "EventCode": "0xD1", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9", + "EventCode": "0xD1", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10", + "EventCode": "0xD3", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8", + "EventCode": "0xD3", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9", + "EventCode": "0xD3", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10", + "EventCode": "0xD5", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8", + "EventCode": "0xD5", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9", + "EventCode": "0xD5", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10", + "EventCode": "0xD7", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8", + "EventCode": "0xD7", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9", + "EventCode": "0xD7", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tag Hit : Clean NearMem Read Hit", + "EventCode": "0x2C", + "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN", + "PerPkg": "1", + "PublicDescription": "Tag Hit : Clean NearMem Read Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean full line read hits (reads and RFOs).", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tag Hit : Dirty NearMem Read Hit", + "EventCode": "0x2C", + "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY", + "PerPkg": "1", + "PublicDescription": "Tag Hit : Dirty NearMem Read Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty full line read hits (reads and RFOs).", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tag Hit : Clean NearMem Underfill Hit", + "EventCode": "0x2C", + "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN", + "PerPkg": "1", + "PublicDescription": "Tag Hit : Clean NearMem Underfill Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean underfill hits due to a partial write", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Tag Hit : Dirty NearMem Underfill Hit", + "EventCode": "0x2C", + "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY", + "PerPkg": "1", + "PublicDescription": "Tag Hit : Dirty NearMem Underfill Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty underfill read hits due to a partial write", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Tag Miss", + "EventCode": "0x61", + "EventName": "UNC_M2M_TAG_MISS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number AD Ingress Credits", + "EventCode": "0x41", + "EventName": "UNC_M2M_TGR_AD_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number BL Ingress Credits", + "EventCode": "0x42", + "EventName": "UNC_M2M_TGR_BL_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Full : Channel 0", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_FULL.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Full : Channel 1", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_FULL.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Full : Channel 2", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_FULL.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Inserts : Channel 0", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Inserts : Channel 1", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Inserts : Channel 2", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Not Empty : Channel 0", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_NE.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Not Empty : Channel 1", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_NE.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Not Empty : Channel 2", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_NE.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Occupancy : Channel 0", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Occupancy : Channel 1", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Occupancy : Channel 2", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Credit Acquired", + "EventCode": "0x0d", + "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Credits Occupancy", + "EventCode": "0x0e", + "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Full", + "EventCode": "0x0c", + "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Not Empty", + "EventCode": "0x0b", + "EventName": "UNC_M2M_TxC_AD_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Allocations", + "EventCode": "0x09", + "EventName": "UNC_M2M_TxC_AD_INSERTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No AD Egress (to CMS) Credits", + "EventCode": "0x0f", + "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits", + "EventCode": "0x10", + "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Occupancy", + "EventCode": "0x0A", + "EventName": "UNC_M2M_TxC_AD_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound Ring Transactions on AK : CRD Transactions to Cbo", + "EventCode": "0x39", + "EventName": "UNC_M2M_TxC_AK.CRD_CBO", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound Ring Transactions on AK : NDR Transactions", + "EventCode": "0x39", + "EventName": "UNC_M2M_TxC_AK.NDR", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AKC Credits", + "EventCode": "0x5F", + "EventName": "UNC_M2M_TxC_AKC_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side", + "EventCode": "0x1D", + "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side", + "EventCode": "0x1D", + "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full : All", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Near Side", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Far Side", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1", + "PerPkg": "1", + "UMask": "0x88", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1", + "PerPkg": "1", + "UMask": "0xa0", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1", + "PerPkg": "1", + "UMask": "0x90", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty : All", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Near Side", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Far Side", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations : All", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Near Side", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Far Side", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side", + "EventCode": "0x1F", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side", + "EventCode": "0x1F", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side", + "EventCode": "0x20", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side", + "EventCode": "0x20", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy : All", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Near Side", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Far Side", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Cache", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_CACHE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Core", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_CORE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to QPI", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_UPI", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side", + "EventCode": "0x19", + "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side", + "EventCode": "0x19", + "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Full : All", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Near Side", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Far Side", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Not Empty : All", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Near Side", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Far Side", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Allocations : All", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Near Side", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Far Side", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side", + "EventCode": "0x1B", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side", + "EventCode": "0x1B", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side", + "EventCode": "0x1C", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side", + "EventCode": "0x1C", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - All", + "EventCode": "0xA6", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", + "EventCode": "0xA6", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", + "EventCode": "0xA6", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - All", + "EventCode": "0xA6", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", + "EventCode": "0xA6", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", + "EventCode": "0xA6", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - All", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AK", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - All", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : IV", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AK", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : IV", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AK", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : IV", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AK", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : IV", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : IV", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : IV", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_VERT_STARVED1.TGC", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Down and Even", + "EventCode": "0xB0", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Down and Odd", + "EventCode": "0xB0", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Up and Even", + "EventCode": "0xB0", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Up and Odd", + "EventCode": "0xB0", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Down and Even", + "EventCode": "0xB4", + "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", + "EventCode": "0xB4", + "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Up and Even", + "EventCode": "0xB4", + "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", + "EventCode": "0xB4", + "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Down and Even", + "EventCode": "0xB1", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Down and Odd", + "EventCode": "0xB1", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Up and Even", + "EventCode": "0xB1", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Up and Odd", + "EventCode": "0xB1", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Down and Even", + "EventCode": "0xB2", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Down and Odd", + "EventCode": "0xB2", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Up and Even", + "EventCode": "0xB2", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Up and Odd", + "EventCode": "0xB2", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical IV Ring in Use : Down", + "EventCode": "0xB3", + "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical IV Ring in Use : Up", + "EventCode": "0xB3", + "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Down and Even", + "EventCode": "0xB5", + "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", + "EventCode": "0xB5", + "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Up and Even", + "EventCode": "0xB5", + "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", + "EventCode": "0xB5", + "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "WPQ Flush : Channel 0", + "EventCode": "0x58", + "EventName": "UNC_M2M_WPQ_FLUSH.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "WPQ Flush : Channel 1", + "EventCode": "0x58", + "EventName": "UNC_M2M_WPQ_FLUSH.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "WPQ Flush : Channel 2", + "EventCode": "0x58", + "EventName": "UNC_M2M_WPQ_FLUSH.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 2", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 0", + "EventCode": "0x51", + "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 1", + "EventCode": "0x51", + "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 2", + "EventCode": "0x51", + "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 0", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 1", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 2", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Full : Channel 0", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WR_TRACKER_FULL.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Full : Channel 1", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WR_TRACKER_FULL.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Full : Channel 2", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WR_TRACKER_FULL.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Full : Mirror", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WR_TRACKER_FULL.MIRR", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts : Channel 0", + "EventCode": "0x56", + "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts : Channel 1", + "EventCode": "0x56", + "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts : Channel 2", + "EventCode": "0x56", + "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty : Channel 0", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WR_TRACKER_NE.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty : Channel 1", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WR_TRACKER_NE.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty : Channel 2", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WR_TRACKER_NE.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty : Mirror", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0", + "EventCode": "0x63", + "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1", + "EventCode": "0x63", + "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 2", + "EventCode": "0x63", + "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 0", + "EventCode": "0x62", + "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 1", + "EventCode": "0x62", + "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 2", + "EventCode": "0x62", + "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy : Channel 0", + "EventCode": "0x55", + "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy : Channel 1", + "EventCode": "0x55", + "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy : Channel 2", + "EventCode": "0x55", + "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy : Mirror", + "EventCode": "0x55", + "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy", + "EventCode": "0x55", + "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_NONTGR", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy", + "EventCode": "0x55", + "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_PWR", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Posted Inserts : Channel 0", + "EventCode": "0x5E", + "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Posted Inserts : Channel 1", + "EventCode": "0x5E", + "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Posted Inserts : Channel 2", + "EventCode": "0x5E", + "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Posted Occupancy : Channel 0", + "EventCode": "0x5D", + "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Posted Occupancy : Channel 1", + "EventCode": "0x5D", + "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Posted Occupancy : Channel 2", + "EventCode": "0x5D", + "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10", + "EventCode": "0x81", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8", + "EventCode": "0x81", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9", + "EventCode": "0x81", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10", + "EventCode": "0x83", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8", + "EventCode": "0x83", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9", + "EventCode": "0x83", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10", + "EventCode": "0x89", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8", + "EventCode": "0x89", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9", + "EventCode": "0x89", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10", + "EventCode": "0x8B", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8", + "EventCode": "0x8B", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9", + "EventCode": "0x8B", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10", + "EventCode": "0x85", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8", + "EventCode": "0x85", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9", + "EventCode": "0x85", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10", + "EventCode": "0x87", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8", + "EventCode": "0x87", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9", + "EventCode": "0x87", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10", + "EventCode": "0x8D", + "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8", + "EventCode": "0x8D", + "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9", + "EventCode": "0x8D", + "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10", + "EventCode": "0x8F", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8", + "EventCode": "0x8F", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9", + "EventCode": "0x8F", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty : Requests", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ", + "PerPkg": "1", + "PublicDescription": "CBox AD Credits Empty : Requests : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty : Snoops", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP", + "PerPkg": "1", + "PublicDescription": "CBox AD Credits Empty : Snoops : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty : VNA Messages", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "CBox AD Credits Empty : VNA Messages : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty : Writebacks", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB", + "PerPkg": "1", + "PublicDescription": "CBox AD Credits Empty : Writebacks : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Clockticks of the mesh to UPI (M3UPI)", + "EventCode": "0x01", + "EventName": "UNC_M3UPI_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Clockticks of the mesh to UPI (M3UPI) : Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Clockticks", + "EventCode": "0xc0", + "EventName": "UNC_M3UPI_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "D2C Sent", + "EventCode": "0x2B", + "EventName": "UNC_M3UPI_D2C_SENT", + "PerPkg": "1", + "PublicDescription": "D2C Sent : Count cases BL sends direct to core", + "Unit": "M3UPI" + }, + { + "BriefDescription": "D2U Sent", + "EventCode": "0x2A", + "EventName": "UNC_M3UPI_D2U_SENT", + "PerPkg": "1", + "PublicDescription": "D2U Sent : Cases where SMI3 sends D2U command", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Distress signal asserted : DPT Local", + "EventCode": "0xAF", + "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_LOCAL", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Distress signal asserted : DPT Remote", + "EventCode": "0xAF", + "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_NONLOCAL", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Distress signal asserted : DPT Stalled - IV", + "EventCode": "0xAF", + "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_STALL_IV", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit", + "EventCode": "0xAF", + "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_STALL_NOCRD", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Distress signal asserted : Horizontal", + "EventCode": "0xAF", + "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.HORZ", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Distress signal asserted : PMM Local", + "EventCode": "0xAF", + "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.PMM_LOCAL", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Distress signal asserted : PMM Remote", + "EventCode": "0xAF", + "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.PMM_NONLOCAL", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Distress signal asserted : Vertical", + "EventCode": "0xAF", + "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.VERT", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Down", + "EventCode": "0xBA", + "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Up", + "EventCode": "0xBA", + "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Left and Even", + "EventCode": "0xB6", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", + "EventCode": "0xB6", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Right and Even", + "EventCode": "0xB6", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", + "EventCode": "0xB6", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "EventCode": "0xBB", + "EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "EventCode": "0xBB", + "EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "EventCode": "0xBB", + "EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "EventCode": "0xBB", + "EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "EventCode": "0xB7", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "EventCode": "0xB7", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "EventCode": "0xB7", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "EventCode": "0xB7", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Left and Even", + "EventCode": "0xB8", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", + "EventCode": "0xB8", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Right and Even", + "EventCode": "0xB8", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", + "EventCode": "0xB8", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal IV Ring in Use : Left", + "EventCode": "0xB9", + "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal IV Ring in Use : Right", + "EventCode": "0xB9", + "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO1_NCB", + "PerPkg": "1", + "PublicDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only) : No vn0 and vna credits available to send to M2", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty : IIO2", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB", + "PerPkg": "1", + "PublicDescription": "M2 BL Credits Empty : IIO2 : No vn0 and vna credits available to send to M2", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty : IIO3", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB", + "PerPkg": "1", + "PublicDescription": "M2 BL Credits Empty : IIO3 : No vn0 and vna credits available to send to M2", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty : IIO4", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB", + "PerPkg": "1", + "PublicDescription": "M2 BL Credits Empty : IIO4 : No vn0 and vna credits available to send to M2", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty : IIO5", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB", + "PerPkg": "1", + "PublicDescription": "M2 BL Credits Empty : IIO5 : No vn0 and vna credits available to send to M2", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS", + "PerPkg": "1", + "PublicDescription": "M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together : No vn0 and vna credits available to send to M2", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty : Selected M2p BL NCS credits", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL", + "PerPkg": "1", + "PublicDescription": "M2 BL Credits Empty : Selected M2p BL NCS credits : No vn0 and vna credits available to send to M2", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty : IIO5", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.UBOX_NCB", + "PerPkg": "1", + "PublicDescription": "M2 BL Credits Empty : IIO5 : No vn0 and vna credits available to send to M2", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0", + "EventCode": "0xE6", + "EventName": "UNC_M3UPI_MISC_EXTERNAL.MBE_INST0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1", + "EventCode": "0xE6", + "EventName": "UNC_M3UPI_MISC_EXTERNAL.MBE_INST1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received : AD - Slot 0", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0", + "PerPkg": "1", + "PublicDescription": "Multi Slot Flit Received : AD - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received : AD - Slot 1", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1", + "PerPkg": "1", + "PublicDescription": "Multi Slot Flit Received : AD - Slot 1 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received : AD - Slot 2", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2", + "PerPkg": "1", + "PublicDescription": "Multi Slot Flit Received : AD - Slot 2 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received : AK - Slot 0", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0", + "PerPkg": "1", + "PublicDescription": "Multi Slot Flit Received : AK - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received : AK - Slot 2", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2", + "PerPkg": "1", + "PublicDescription": "Multi Slot Flit Received : AK - Slot 2 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received : BL - Slot 0", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0", + "PerPkg": "1", + "PublicDescription": "Multi Slot Flit Received : BL - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD", + "EventCode": "0xAC", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK", + "EventCode": "0xAC", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL", + "EventCode": "0xAC", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV", + "EventCode": "0xAC", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : AD", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AKC", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : AD", + "EventCode": "0xAD", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : AK", + "EventCode": "0xAD", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1", + "EventCode": "0xAD", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : BL", + "EventCode": "0xAD", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : IV", + "EventCode": "0xAD", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : AD", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AKC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Source Throttle", + "EventCode": "0xae", + "EventName": "UNC_M3UPI_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0 : REQ on AD", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN0 : REQ on AD : VN0 message requested but lost arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0 : RSP on AD", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN0 : RSP on AD : VN0 message requested but lost arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0 : SNP on AD", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN0 : SNP on AD : VN0 message requested but lost arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0 : NCB on BL", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN0 : NCB on BL : VN0 message requested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0 : NCS on BL", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN0 : NCS on BL : VN0 message requested but lost arbitration : Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0 : RSP on BL", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN0 : RSP on BL : VN0 message requested but lost arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0 : WB on BL", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN0 : WB on BL : VN0 message requested but lost arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1 : REQ on AD", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN1 : REQ on AD : VN1 message requested but lost arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1 : RSP on AD", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN1 : RSP on AD : VN1 message requested but lost arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1 : SNP on AD", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN1 : SNP on AD : VN1 message requested but lost arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1 : NCB on BL", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN1 : NCB on BL : VN1 message requested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1 : NCS on BL", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN1 : NCS on BL : VN1 message requested but lost arbitration : Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1 : RSP on BL", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN1 : RSP on BL : VN1 message requested but lost arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1 : WB on BL", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "Lost Arb for VN1 : WB on BL : VN1 message requested but lost arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN0", + "PerPkg": "1", + "PublicDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0 : AD and BL messages won arbitration concurrently / in parallel", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN1", + "PerPkg": "1", + "PublicDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1 : AD and BL messages won arbitration concurrently / in parallel", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous : Max Parallel Win", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.ALL_PARALLEL_WIN", + "PerPkg": "1", + "PublicDescription": "Arb Miscellaneous : Max Parallel Win : VN0 and VN1 arbitration sub-pipelines both produced AD and BL winners (maximum possible parallel winners)", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN0", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0", + "PerPkg": "1", + "PublicDescription": "Arb Miscellaneous : No Progress on Pending AD VN0 : Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN1", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1", + "PerPkg": "1", + "PublicDescription": "Arb Miscellaneous : No Progress on Pending AD VN1 : Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN0", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0", + "PerPkg": "1", + "PublicDescription": "Arb Miscellaneous : No Progress on Pending BL VN0 : Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN1", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1", + "PerPkg": "1", + "PublicDescription": "Arb Miscellaneous : No Progress on Pending BL VN1 : Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.VN01_PARALLEL_WIN", + "PerPkg": "1", + "PublicDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win : VN0 and VN1 arbitration sub-pipelines had parallel winners (at least one AD or BL on each side)", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0 : REQ on AD", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN0 : REQ on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0 : RSP on AD", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN0 : RSP on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0 : SNP on AD", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN0 : SNP on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0 : NCB on BL", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN0 : NCB on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0 : NCS on BL", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN0 : NCS on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0 : RSP on BL", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN0 : RSP on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0 : WB on BL", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN0 : WB on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1 : REQ on AD", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN1 : REQ on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1 : RSP on AD", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN1 : RSP on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1 : SNP on AD", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN1 : SNP on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1 : NCB on BL", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN1 : NCB on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1 : NCS on BL", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN1 : NCS on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1 : RSP on BL", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN1 : RSP on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1 : WB on BL", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "No Credits to Arb for VN1 : WB on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0 : REQ on AD", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN0 : REQ on AD : VN0 message was not able to request arbitration while some other message won arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0 : RSP on AD", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN0 : RSP on AD : VN0 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0 : SNP on AD", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN0 : SNP on AD : VN0 message was not able to request arbitration while some other message won arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0 : NCB on BL", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN0 : NCB on BL : VN0 message was not able to request arbitration while some other message won arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0 : NCS on BL", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN0 : NCS on BL : VN0 message was not able to request arbitration while some other message won arbitration : Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0 : RSP on BL", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN0 : RSP on BL : VN0 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0 : WB on BL", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN0 : WB on BL : VN0 message was not able to request arbitration while some other message won arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1 : REQ on AD", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN1 : REQ on AD : VN1 message was not able to request arbitration while some other message won arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1 : RSP on AD", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN1 : RSP on AD : VN1 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1 : SNP on AD", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN1 : SNP on AD : VN1 message was not able to request arbitration while some other message won arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1 : NCB on BL", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN1 : NCB on BL : VN1 message was not able to request arbitration while some other message won arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1 : NCS on BL", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN1 : NCS on BL : VN1 message was not able to request arbitration while some other message won arbitration : Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1 : RSP on BL", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN1 : RSP on BL : VN1 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1 : WB on BL", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "Can't Arb for VN1 : WB on BL : VN1 message was not able to request arbitration while some other message won arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL Arb", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB", + "PerPkg": "1", + "PublicDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL Arb : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to slot 0 of independent flit while bl message is in arbitration", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE", + "PerPkg": "1", + "PublicDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to slot 0 of independent flit while pipeline is idle", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 1", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT", + "PerPkg": "1", + "PublicDescription": "Ingress Queue Bypasses : AD + BL to Slot 1 : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to flit slot 1 while merging with bl message in same flit", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 2", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT", + "PerPkg": "1", + "PublicDescription": "Ingress Queue Bypasses : AD + BL to Slot 2 : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to flit slot 2 while merging with bl message in same flit", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events : Any In BGF FIFO", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO", + "PerPkg": "1", + "PublicDescription": "Miscellaneous Credit Events : Any In BGF FIFO : Indication that at least one packet (flit) is in the bgf (fifo only)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events : Any in BGF Path", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH", + "PerPkg": "1", + "PublicDescription": "Miscellaneous Credit Events : Any in BGF Path : Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT1_FOR_D2K", + "PerPkg": "1", + "PublicDescription": "Miscellaneous Credit Events : d2k credit count is less than 1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT2_FOR_D2K", + "PerPkg": "1", + "PublicDescription": "Miscellaneous Credit Events : d2k credit count is less than 2", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events : No D2K For Arb", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN0_NO_D2K_FOR_ARB", + "PerPkg": "1", + "PublicDescription": "Miscellaneous Credit Events : No D2K For Arb : VN0 BL RSP message was blocked from arbitration request due to lack of D2K CMP credit", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN1_NO_D2K_FOR_ARB", + "PerPkg": "1", + "PublicDescription": "Miscellaneous Credit Events : VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy : Credits Consumed", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.CONSUMED", + "PerPkg": "1", + "PublicDescription": "Credit Occupancy : Credits Consumed : number of remote vna credits consumed per cycle", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy : D2K Credits", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD", + "PerPkg": "1", + "PublicDescription": "Credit Occupancy : D2K Credits : D2K completion fifo credit occupancy (credits in use), accumulated across all cycles", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy : Packets in BGF FIFO", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO", + "PerPkg": "1", + "PublicDescription": "Credit Occupancy : Packets in BGF FIFO : Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy : Packets in BGF Path", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH", + "PerPkg": "1", + "PublicDescription": "Credit Occupancy : Packets in BGF Path : Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO", + "PerPkg": "1", + "PublicDescription": "Credit Occupancy : count of bl messages in pump-1-pending state, in completion fifo only", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL", + "PerPkg": "1", + "PublicDescription": "Credit Occupancy : count of bl messages in pump-1-pending state, in marker table and in fifo", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy : Transmit Credits", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD", + "PerPkg": "1", + "PublicDescription": "Credit Occupancy : Transmit Credits : Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy : VNA In Use", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE", + "PerPkg": "1", + "PublicDescription": "Credit Occupancy : VNA In Use : Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent : All", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.ALL", + "PerPkg": "1", + "PublicDescription": "Data Flit Not Sent : All : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but could not be sent for any reason, e.g. low credits, low tsv, stall injection", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent : No BGF Credits", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_BGF", + "PerPkg": "1", + "PublicDescription": "Data Flit Not Sent : No BGF Credits : Data flit is ready for transmission but could not be sent", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent : No TxQ Credits", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_TXQ", + "PerPkg": "1", + "PublicDescription": "Data Flit Not Sent : No TxQ Credits : Data flit is ready for transmission but could not be sent", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent : TSV High", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.TSV_HI", + "PerPkg": "1", + "PublicDescription": "Data Flit Not Sent : TSV High : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but was not sent while tsv high", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent : Cycle valid for Flit", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.VALID_FOR_FLIT", + "PerPkg": "1", + "PublicDescription": "Data Flit Not Sent : Cycle valid for Flit : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but was not sent while cycle is valid for flit transmission", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 0", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT", + "PerPkg": "1", + "PublicDescription": "Generating BL Data Flit Sequence : Wait on Pump 0 : generating bl data flit sequence; waiting for data pump 0", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT", + "PerPkg": "1", + "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is at capacity (pending table plus completion fifo at limit)", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY", + "PerPkg": "1", + "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is tracking at least one message", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL", + "PerPkg": "1", + "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending completion fifo is full", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0", + "PerPkg": "1", + "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO", + "PerPkg": "1", + "PublicDescription": "Generating BL Data Flit Sequence : a bl message finished but is in limbo and moved to pump-1-pending logic", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 1", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT", + "PerPkg": "1", + "PublicDescription": "Generating BL Data Flit Sequence : Wait on Pump 1 : generating bl data flit sequence; waiting for data pump 1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF", + "PerPkg": "1", + "PublicDescription": ": slot 2 request naturally serviced during hold-off period", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE", + "PerPkg": "1", + "PublicDescription": ": slot 2 request forcibly serviced during service window", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED", + "PerPkg": "1", + "PublicDescription": ": slot 2 request received from link layer while idle (with no slot 2 request active immediately prior)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN", + "PerPkg": "1", + "PublicDescription": ": slot 2 request withdrawn during hold-off period or service window", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit : All", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit : Needs Data Flit", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA", + "PerPkg": "1", + "PublicDescription": "Slotting BL Message Into Header Flit : Needs Data Flit : BL message requires data flit sequence", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 0", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT", + "PerPkg": "1", + "PublicDescription": "Slotting BL Message Into Header Flit : Wait on Pump 0 : Waiting for header pump 0", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ", + "PerPkg": "1", + "PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 : Header pump 1 is not required for flit", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE", + "PerPkg": "1", + "PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble : Header pump 1 is not required for flit but flit transmission delayed", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL", + "PerPkg": "1", + "PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail : Header pump 1 is not required for flit and not available", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 1", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT", + "PerPkg": "1", + "PublicDescription": "Slotting BL Message Into Header Flit : Wait on Pump 1 : Waiting for header pump 1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1 : Accumulate", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 1 : Accumulate : Events related to Header Flit Generation - Set 1 : Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1 : Accumulate Ready", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 1 : Accumulate Ready : Events related to Header Flit Generation - Set 1 : header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1 : Accumulate Wasted", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 1 : Accumulate Wasted : Events related to Header Flit Generation - Set 1 : Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked : Events related to Header Flit Generation - Set 1 : Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_AFTER", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: message was slotted only after run-ahead was over; run-ahead mode definitely wasted", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Message", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_DURING", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 1 : Run-Ahead - Message : Events related to Header Flit Generation - Set 1 : run-ahead mode: one message slotted during run-ahead", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_AFTER", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: second message slotted immediately after run-ahead; potential run-ahead success", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_SENT", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: two (or three) message flit sent immediately after run-ahead; complete run-ahead success", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 2 : Parallel Ok", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 2 : Parallel Ok : Events related to Header Flit Generation - Set 2 : new header flit construction may proceed in parallel with data flit sequence", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 2 : Parallel Flit Finished", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_FLIT", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 2 : Parallel Flit Finished : Events related to Header Flit Generation - Set 2 : header flit finished assembly in parallel with data flit sequence", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 2 : Parallel Message", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_MSG", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 2 : Parallel Message : Events related to Header Flit Generation - Set 2 : message is slotted into header flit in parallel with data flit sequence", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 2 : Rate-matching Stall : Events related to Header Flit Generation - Set 2 : Rate-matching stall injected", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall - No Message", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG", + "PerPkg": "1", + "PublicDescription": "Flit Gen - Header 2 : Rate-matching Stall - No Message : Events related to Header Flit Generation - Set 2 : Rate matching stall injected, but no additional message slotted during stall cycle", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit : One Message", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG", + "PerPkg": "1", + "PublicDescription": "Sent Header Flit : One Message : One message in flit; VNA or non-VNA flit", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit : One Message in non-VNA", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG_VNX", + "PerPkg": "1", + "PublicDescription": "Sent Header Flit : One Message in non-VNA : One message in flit; non-VNA flit", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit : Two Messages", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.2_MSGS", + "PerPkg": "1", + "PublicDescription": "Sent Header Flit : Two Messages : Two messages in flit; VNA flit", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit : Three Messages", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.3_MSGS", + "PerPkg": "1", + "PublicDescription": "Sent Header Flit : Three Messages : Three messages in flit; VNA flit", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit : One Slot Taken", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit : Two Slots Taken", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_2", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit : All Slots Taken", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_3", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent : All", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.ALL", + "PerPkg": "1", + "PublicDescription": "Header Not Sent : All : header flit is ready for transmission but could not be sent : header flit is ready for transmission but could not be sent for any reason, e.g. no credits, low tsv, stall injection", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent : No BGF Credits", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_CRD", + "PerPkg": "1", + "PublicDescription": "Header Not Sent : No BGF Credits : header flit is ready for transmission but could not be sent : No BGF credits available", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent : No BGF Credits + No Extra Message Slotted", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_NO_MSG", + "PerPkg": "1", + "PublicDescription": "Header Not Sent : No BGF Credits + No Extra Message Slotted : header flit is ready for transmission but could not be sent : No BGF credits available; no additional message slotted into flit", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent : No TxQ Credits", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_CRD", + "PerPkg": "1", + "PublicDescription": "Header Not Sent : No TxQ Credits : header flit is ready for transmission but could not be sent : No TxQ credits available", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent : No TxQ Credits + No Extra Message Slotted", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_NO_MSG", + "PerPkg": "1", + "PublicDescription": "Header Not Sent : No TxQ Credits + No Extra Message Slotted : header flit is ready for transmission but could not be sent : No TxQ credits available; no additional message slotted into flit", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent : TSV High", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.TSV_HI", + "PerPkg": "1", + "PublicDescription": "Header Not Sent : TSV High : header flit is ready for transmission but could not be sent : header flit is ready for transmission but was not sent while tsv high", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent : Cycle valid for Flit", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.VALID_FOR_FLIT", + "PerPkg": "1", + "PublicDescription": "Header Not Sent : Cycle valid for Flit : header flit is ready for transmission but could not be sent : header flit is ready for transmission but was not sent while cycle is valid for flit transmission", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held : Can't Slot AD", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD", + "PerPkg": "1", + "PublicDescription": "Message Held : Can't Slot AD : some AD message could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1})", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held : Can't Slot BL", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL", + "PerPkg": "1", + "PublicDescription": "Message Held : Can't Slot BL : some BL message could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1})", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held : Parallel Attempt", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT", + "PerPkg": "1", + "PublicDescription": "Message Held : Parallel Attempt : ad and bl messages attempted to slot into the same flit in parallel", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held : Parallel Success", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS", + "PerPkg": "1", + "PublicDescription": "Message Held : Parallel Success : ad and bl messages were actually slotted into the same flit in paralle", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held : VN0", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_HELD.VN0", + "PerPkg": "1", + "PublicDescription": "Message Held : VN0 : vn0 message(s) that couldn't be slotted into last vn0 flit are held in slotting stage while processing vn1 flit", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held : VN1", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_HELD.VN1", + "PerPkg": "1", + "PublicDescription": "Message Held : VN1 : vn1 message(s) that couldn't be slotted into last vn1 flit are held in slotting stage while processing vn0 flit", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : REQ on AD", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : REQ on AD : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on AD", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on AD : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : SNP on AD", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : SNP on AD : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCB on BL", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCB on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCS on BL", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCS on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on BL", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : WB on BL", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : WB on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : REQ on AD", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : REQ on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on AD", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : SNP on AD", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : SNP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCB on BL", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCS on BL", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCS on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on BL", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : WB on BL", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : WB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : REQ on AD", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : REQ on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on AD", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : SNP on AD", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : SNP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCB on BL", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCS on BL", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCS on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on BL", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : WB on BL", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : WB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : REQ on AD", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : REQ on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on AD", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : SNP on AD", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : SNP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCB on BL", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCS on BL", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCS on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on BL", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : WB on BL", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : WB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit : REQ on AD", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "VN0 message can't slot into flit : REQ on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit : RSP on AD", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "VN0 message can't slot into flit : RSP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit : SNP on AD", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "VN0 message can't slot into flit : SNP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit : NCB on BL", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "VN0 message can't slot into flit : NCB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit : NCS on BL", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "VN0 message can't slot into flit : NCS on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit : RSP on BL", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "VN0 message can't slot into flit : RSP on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit : WB on BL", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "VN0 message can't slot into flit : WB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit : REQ on AD", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "VN1 message can't slot into flit : REQ on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit : RSP on AD", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "VN1 message can't slot into flit : RSP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit : SNP on AD", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "VN1 message can't slot into flit : SNP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit : NCB on BL", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "VN1 message can't slot into flit : NCB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit : NCS on BL", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "VN1 message can't slot into flit : NCS on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit : RSP on BL", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "VN1 message can't slot into flit : RSP on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit : WB on BL", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "VN1 message can't slot into flit : WB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits : Any In Use", + "EventCode": "0x5A", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE", + "PerPkg": "1", + "PublicDescription": "Remote VNA Credits : Any In Use : At least one remote vna credit is in use", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits : Corrected", + "EventCode": "0x5A", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED", + "PerPkg": "1", + "PublicDescription": "Remote VNA Credits : Corrected : Number of remote vna credits corrected (local return) per cycle", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits : Level < 1", + "EventCode": "0x5A", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1", + "PerPkg": "1", + "PublicDescription": "Remote VNA Credits : Level < 1 : Remote vna credit level is less than 1 (i.e. no vna credits available)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits : Level < 10", + "EventCode": "0x5A", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT10", + "PerPkg": "1", + "PublicDescription": "Remote VNA Credits : Level < 10 : remote vna credit level is less than 10; parallel vn0/vn1 arb not possible", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits : Level < 4", + "EventCode": "0x5A", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4", + "PerPkg": "1", + "PublicDescription": "Remote VNA Credits : Level < 4 : Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits : Level < 5", + "EventCode": "0x5A", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5", + "PerPkg": "1", + "PublicDescription": "Remote VNA Credits : Level < 5 : Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5", + "PerPkg": "1", + "PublicDescription": ": remote vna credit count was less than 5 and allocation to ad or bl messages was required", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10", + "PerPkg": "1", + "PublicDescription": ": remote vna credit count was less than 10 and allocation to vn0 or vn1 was required", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD", + "PerPkg": "1", + "PublicDescription": ": on vn0, remote vna credits were allocated only to ad messages, not to bl", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL", + "PerPkg": "1", + "PublicDescription": ": on vn0, remote vna credits were allocated only to bl messages, not to ad", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY", + "PerPkg": "1", + "PublicDescription": ": remote vna credits were allocated only to vn0, not to vn1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD", + "PerPkg": "1", + "PublicDescription": ": on vn1, remote vna credits were allocated only to ad messages, not to bl", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL", + "PerPkg": "1", + "PublicDescription": ": on vn1, remote vna credits were allocated only to bl messages, not to ad", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY", + "PerPkg": "1", + "PublicDescription": ": remote vna credits were allocated only to vn1, not to vn0", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - All", + "EventCode": "0xE5", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Credited", + "EventCode": "0xE5", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", + "EventCode": "0xE5", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - All", + "EventCode": "0xE5", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Credited", + "EventCode": "0xE5", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", + "EventCode": "0xE5", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - All", + "EventCode": "0xE2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - Credited", + "EventCode": "0xE2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", + "EventCode": "0xE2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AK", + "EventCode": "0xE2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", + "EventCode": "0xE2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - All", + "EventCode": "0xE2", + "EventName": "UNC_M3UPI_RxR_BYPASS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - Credited", + "EventCode": "0xE2", + "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", + "EventCode": "0xE2", + "EventName": "UNC_M3UPI_RxR_BYPASS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass : IV", + "EventCode": "0xE2", + "EventName": "UNC_M3UPI_RxR_BYPASS.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - All", + "EventCode": "0xE3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Credited", + "EventCode": "0xE3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", + "EventCode": "0xE3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : AK", + "EventCode": "0xE3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - All", + "EventCode": "0xE3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Credited", + "EventCode": "0xE3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", + "EventCode": "0xE3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : IFV - Credited", + "EventCode": "0xE3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation : IV", + "EventCode": "0xE3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation", + "EventCode": "0xe4", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED_1", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - All", + "EventCode": "0xE1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - Credited", + "EventCode": "0xE1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited", + "EventCode": "0xE1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AK", + "EventCode": "0xE1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited", + "EventCode": "0xE1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - All", + "EventCode": "0xE1", + "EventName": "UNC_M3UPI_RxR_INSERTS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - Credited", + "EventCode": "0xE1", + "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited", + "EventCode": "0xE1", + "EventName": "UNC_M3UPI_RxR_INSERTS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations : IV", + "EventCode": "0xE1", + "EventName": "UNC_M3UPI_RxR_INSERTS.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - All", + "EventCode": "0xE0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", + "EventCode": "0xE0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited", + "EventCode": "0xE0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AK", + "EventCode": "0xE0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited", + "EventCode": "0xE0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - All", + "EventCode": "0xE0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", + "EventCode": "0xE0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited", + "EventCode": "0xE0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : IV", + "EventCode": "0xE0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10", + "EventCode": "0xD1", + "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8", + "EventCode": "0xD1", + "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9", + "EventCode": "0xD1", + "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10", + "EventCode": "0xD3", + "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8", + "EventCode": "0xD3", + "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9", + "EventCode": "0xD3", + "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10", + "EventCode": "0xD5", + "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8", + "EventCode": "0xD5", + "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9", + "EventCode": "0xD5", + "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10", + "EventCode": "0xD7", + "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8", + "EventCode": "0xD7", + "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9", + "EventCode": "0xD7", + "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD : VN0 REQ Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "Failed ARB for AD : VN0 REQ Messages : AD arb but no win; arb request asserted but not won", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD : VN0 RSP Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "Failed ARB for AD : VN0 RSP Messages : AD arb but no win; arb request asserted but not won", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD : VN0 SNP Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "Failed ARB for AD : VN0 SNP Messages : AD arb but no win; arb request asserted but not won", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD : VN0 WB Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB", + "PerPkg": "1", + "PublicDescription": "Failed ARB for AD : VN0 WB Messages : AD arb but no win; arb request asserted but not won", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD : VN1 REQ Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "Failed ARB for AD : VN1 REQ Messages : AD arb but no win; arb request asserted but not won", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD : VN1 RSP Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "Failed ARB for AD : VN1 RSP Messages : AD arb but no win; arb request asserted but not won", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD : VN1 SNP Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "Failed ARB for AD : VN1 SNP Messages : AD arb but no win; arb request asserted but not won", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD : VN1 WB Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB", + "PerPkg": "1", + "PublicDescription": "Failed ARB for AD : VN1 WB Messages : AD arb but no win; arb request asserted but not won", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0", + "PerPkg": "1", + "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1", + "PerPkg": "1", + "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2", + "PerPkg": "1", + "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP", + "PerPkg": "1", + "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty : VN0 REQ Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Not Empty : VN0 REQ Messages : Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty : VN0 RSP Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Not Empty : VN0 RSP Messages : Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty : VN0 SNP Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Not Empty : VN0 SNP Messages : Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty : VN0 WB Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Not Empty : VN0 WB Messages : Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty : VN1 REQ Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Not Empty : VN1 REQ Messages : Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty : VN1 RSP Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Not Empty : VN1 RSP Messages : Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty : VN1 SNP Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Not Empty : VN1 SNP Messages : Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty : VN1 WB Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Not Empty : VN1 WB Messages : Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts : VN0 REQ Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Inserts : VN0 REQ Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts : VN0 RSP Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Inserts : VN0 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts : VN0 SNP Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Inserts : VN0 SNP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts : VN0 WB Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Inserts : VN0 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts : VN1 REQ Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Inserts : VN1 REQ Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts : VN1 RSP Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Inserts : VN1 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts : VN1 SNP Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "AD Flow Q Inserts : VN1 SNP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy : VN0 REQ Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy : VN0 RSP Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy : VN0 SNP Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy : VN0 WB Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy : VN1 REQ Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy : VN1 RSP Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy : VN1 SNP Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AK Flow Q Inserts", + "EventCode": "0x2F", + "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AK Flow Q Occupancy", + "EventCode": "0x1E", + "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL : VN0 NCB Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB", + "PerPkg": "1", + "PublicDescription": "Failed ARB for BL : VN0 NCB Messages : BL arb but no win; arb request asserted but not won", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL : VN0 NCS Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS", + "PerPkg": "1", + "PublicDescription": "Failed ARB for BL : VN0 NCS Messages : BL arb but no win; arb request asserted but not won", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL : VN0 RSP Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "Failed ARB for BL : VN0 RSP Messages : BL arb but no win; arb request asserted but not won", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL : VN0 WB Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB", + "PerPkg": "1", + "PublicDescription": "Failed ARB for BL : VN0 WB Messages : BL arb but no win; arb request asserted but not won", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL : VN1 NCS Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB", + "PerPkg": "1", + "PublicDescription": "Failed ARB for BL : VN1 NCS Messages : BL arb but no win; arb request asserted but not won", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL : VN1 NCB Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS", + "PerPkg": "1", + "PublicDescription": "Failed ARB for BL : VN1 NCB Messages : BL arb but no win; arb request asserted but not won", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL : VN1 RSP Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "Failed ARB for BL : VN1 RSP Messages : BL arb but no win; arb request asserted but not won", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL : VN1 WB Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB", + "PerPkg": "1", + "PublicDescription": "Failed ARB for BL : VN1 WB Messages : BL arb but no win; arb request asserted but not won", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty : VN0 REQ Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Not Empty : VN0 REQ Messages : Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty : VN0 RSP Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Not Empty : VN0 RSP Messages : Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty : VN0 SNP Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Not Empty : VN0 SNP Messages : Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty : VN0 WB Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Not Empty : VN0 WB Messages : Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty : VN1 REQ Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Not Empty : VN1 REQ Messages : Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty : VN1 RSP Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Not Empty : VN1 RSP Messages : Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty : VN1 SNP Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Not Empty : VN1 SNP Messages : Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty : VN1 WB Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Not Empty : VN1 WB Messages : Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts : VN0 RSP Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Inserts : VN0 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts : VN0 WB Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Inserts : VN0 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts : VN0 NCS Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Inserts : VN0 NCS Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts : VN0 NCB Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Inserts : VN0 NCB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts : VN1 RSP Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Inserts : VN1 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts : VN1 WB Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Inserts : VN1 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts : VN1_NCB Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Inserts : VN1_NCB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts : VN1_NCS Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB", + "PerPkg": "1", + "PublicDescription": "BL Flow Q Inserts : VN1_NCS Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN0 NCS Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN1_NCB Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages", + "EventCode": "0x1F", + "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_LOCAL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages", + "EventCode": "0x1F", + "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_THROUGH", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages", + "EventCode": "0x1F", + "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_WRPULL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages", + "EventCode": "0x1F", + "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_LOCAL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages", + "EventCode": "0x1F", + "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_THROUGH", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages", + "EventCode": "0x1F", + "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_WRPULL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - All", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - All", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - All", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AK", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - All", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : IV", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AK", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : IV", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", + "EventCode": "0xA4", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", + "EventCode": "0xA4", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited", + "EventCode": "0xA4", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AK", + "EventCode": "0xA4", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited", + "EventCode": "0xA4", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", + "EventCode": "0xA4", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", + "EventCode": "0xA4", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited", + "EventCode": "0xA4", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : IV", + "EventCode": "0xA4", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AK", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : IV", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All", + "EventCode": "0xA5", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited", + "EventCode": "0xA5", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK", + "EventCode": "0xA5", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited", + "EventCode": "0xA5", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All", + "EventCode": "0xA5", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited", + "EventCode": "0xA5", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV", + "EventCode": "0xA5", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS_1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS_1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : IV", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_VERT_NACK1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_VERT_NACK1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : IV", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.TGC", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty : VN0 REQ Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "UPI0 AD Credits Empty : VN0 REQ Messages : No credits available to send to UPIs on the AD Ring", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty : VN0 RSP Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "UPI0 AD Credits Empty : VN0 RSP Messages : No credits available to send to UPIs on the AD Ring", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty : VN0 SNP Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "UPI0 AD Credits Empty : VN0 SNP Messages : No credits available to send to UPIs on the AD Ring", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty : VN1 REQ Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "UPI0 AD Credits Empty : VN1 REQ Messages : No credits available to send to UPIs on the AD Ring", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty : VN1 RSP Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "UPI0 AD Credits Empty : VN1 RSP Messages : No credits available to send to UPIs on the AD Ring", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty : VN1 SNP Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "UPI0 AD Credits Empty : VN1 SNP Messages : No credits available to send to UPIs on the AD Ring", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty : VNA", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "UPI0 AD Credits Empty : VNA : No credits available to send to UPIs on the AD Ring", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty : VN0 RSP Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB", + "PerPkg": "1", + "PublicDescription": "UPI0 BL Credits Empty : VN0 RSP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty : VN0 REQ Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "UPI0 BL Credits Empty : VN0 REQ Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty : VN0 SNP Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB", + "PerPkg": "1", + "PublicDescription": "UPI0 BL Credits Empty : VN0 SNP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty : VN1 RSP Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB", + "PerPkg": "1", + "PublicDescription": "UPI0 BL Credits Empty : VN1 RSP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty : VN1 REQ Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "UPI0 BL Credits Empty : VN1 REQ Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty : VN1 SNP Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB", + "PerPkg": "1", + "PublicDescription": "UPI0 BL Credits Empty : VN1 SNP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty : VNA", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "UPI0 BL Credits Empty : VNA : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "FlowQ Generated Prefetch", + "EventCode": "0x29", + "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN", + "PerPkg": "1", + "PublicDescription": "FlowQ Generated Prefetch : Count cases where FlowQ causes spawn of Prefetch to iMC/SMI3 target", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Down and Even", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Down and Odd", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Up and Even", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Up and Odd", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Down and Even", + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Up and Even", + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Down and Even", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Down and Odd", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Up and Even", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Up and Odd", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Down and Even", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Down and Odd", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Up and Even", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Up and Odd", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical IV Ring in Use : Down", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical IV Ring in Use : Up", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Down and Even", + "EventCode": "0xB5", + "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", + "EventCode": "0xB5", + "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Up and Even", + "EventCode": "0xB5", + "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", + "EventCode": "0xB5", + "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used : WB on BL", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB", + "PerPkg": "1", + "PublicDescription": "VN0 Credit Used : WB on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used : NCB on BL", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "VN0 Credit Used : NCB on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used : REQ on AD", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ", + "PerPkg": "1", + "PublicDescription": "VN0 Credit Used : REQ on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used : RSP on AD", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP", + "PerPkg": "1", + "PublicDescription": "VN0 Credit Used : RSP on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used : SNP on AD", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP", + "PerPkg": "1", + "PublicDescription": "VN0 Credit Used : SNP on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used : RSP on BL", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB", + "PerPkg": "1", + "PublicDescription": "VN0 Credit Used : RSP on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits : WB on BL", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB", + "PerPkg": "1", + "PublicDescription": "VN0 No Credits : WB on BL : Number of Cycles there were no VN0 Credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits : NCB on BL", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS", + "PerPkg": "1", + "PublicDescription": "VN0 No Credits : NCB on BL : Number of Cycles there were no VN0 Credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits : REQ on AD", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ", + "PerPkg": "1", + "PublicDescription": "VN0 No Credits : REQ on AD : Number of Cycles there were no VN0 Credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits : RSP on AD", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP", + "PerPkg": "1", + "PublicDescription": "VN0 No Credits : RSP on AD : Number of Cycles there were no VN0 Credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits : SNP on AD", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP", + "PerPkg": "1", + "PublicDescription": "VN0 No Credits : SNP on AD : Number of Cycles there were no VN0 Credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits : RSP on BL", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB", + "PerPkg": "1", + "PublicDescription": "VN0 No Credits : RSP on BL : Number of Cycles there were no VN0 Credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used : WB on BL", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB", + "PerPkg": "1", + "PublicDescription": "VN1 Credit Used : WB on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used : NCB on BL", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "VN1 Credit Used : NCB on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used : REQ on AD", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ", + "PerPkg": "1", + "PublicDescription": "VN1 Credit Used : REQ on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used : RSP on AD", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP", + "PerPkg": "1", + "PublicDescription": "VN1 Credit Used : RSP on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used : SNP on AD", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP", + "PerPkg": "1", + "PublicDescription": "VN1 Credit Used : SNP on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used : RSP on BL", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB", + "PerPkg": "1", + "PublicDescription": "VN1 Credit Used : RSP on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits : WB on BL", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB", + "PerPkg": "1", + "PublicDescription": "VN1 No Credits : WB on BL : Number of Cycles there were no VN1 Credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits : NCB on BL", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS", + "PerPkg": "1", + "PublicDescription": "VN1 No Credits : NCB on BL : Number of Cycles there were no VN1 Credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits : REQ on AD", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ", + "PerPkg": "1", + "PublicDescription": "VN1 No Credits : REQ on AD : Number of Cycles there were no VN1 Credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits : RSP on AD", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP", + "PerPkg": "1", + "PublicDescription": "VN1 No Credits : RSP on AD : Number of Cycles there were no VN1 Credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits : SNP on AD", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP", + "PerPkg": "1", + "PublicDescription": "VN1 No Credits : SNP on AD : Number of Cycles there were no VN1 Credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits : RSP on BL", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB", + "PerPkg": "1", + "PublicDescription": "VN1 No Credits : RSP on BL : Number of Cycles there were no VN1 Credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0", + "EventCode": "0x7E", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0", + "PerPkg": "1", + "UMask": "0x82", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1", + "EventCode": "0x7E", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1", + "PerPkg": "1", + "UMask": "0xa0", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0", + "EventCode": "0x7E", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0", + "PerPkg": "1", + "UMask": "0x81", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1", + "EventCode": "0x7E", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1", + "PerPkg": "1", + "UMask": "0x90", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0", + "EventCode": "0x7E", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0", + "PerPkg": "1", + "UMask": "0x84", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1", + "EventCode": "0x7E", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1", + "PerPkg": "1", + "UMask": "0xc0", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0", + "EventCode": "0x7E", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1", + "EventCode": "0x7E", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0", + "EventCode": "0x7E", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1", + "EventCode": "0x7E", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0", + "EventCode": "0x7E", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1", + "EventCode": "0x7E", + "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0", + "EventCode": "0x7D", + "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1", + "EventCode": "0x7D", + "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0", + "EventCode": "0x7D", + "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1", + "EventCode": "0x7D", + "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0", + "EventCode": "0x7D", + "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1", + "EventCode": "0x7D", + "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0", + "EventCode": "0x7D", + "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1", + "EventCode": "0x7D", + "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARB", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_XPT_PFTCH.ARB", + "PerPkg": "1", + "PublicDescription": ": xpt prefetch message is making arbitration request", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARRIVED", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_XPT_PFTCH.ARRIVED", + "PerPkg": "1", + "PublicDescription": ": xpt prefetch message arrived in ingress pipeline", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_XPT_PFTCH.BYPASS", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_XPT_PFTCH.BYPASS", + "PerPkg": "1", + "PublicDescription": ": xpt prefetch message took bypass path", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_XPT_PFTCH.FLITTED", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_XPT_PFTCH.FLITTED", + "PerPkg": "1", + "PublicDescription": ": xpt prefetch message was slotted into flit (non bypass)", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_ARB", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_ARB", + "PerPkg": "1", + "PublicDescription": ": xpt prefetch message lost arbitration", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_OLD", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_OLD", + "PerPkg": "1", + "PublicDescription": ": xpt prefetch message was dropped because it became too old", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL", + "PerPkg": "1", + "PublicDescription": ": xpt prefetch message was dropped because it was overwritten by new message while prefetch queue was full", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of kfclks", + "EventCode": "0x01", + "EventName": "UNC_UPI_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Number of kfclks : Counts the number of clocks in the UPI LL. This clock runs at 1/8th the GT/s speed of the UPI link. For example, a 8GT/s link will have qfclk or 1GHz. Current products do not support dynamic link speeds, so this frequency is fixed.", + "Unit": "UPI" + }, + { + "BriefDescription": "Direct packet attempts : D2C", + "EventCode": "0x12", + "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C", + "PerPkg": "1", + "PublicDescription": "Direct packet attempts : D2C : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "Direct packet attempts : D2K", + "EventCode": "0x12", + "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K", + "PerPkg": "1", + "PublicDescription": "Direct packet attempts : D2K : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles in L1", + "EventCode": "0x21", + "EventName": "UNC_UPI_L1_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Cycles in L1 : Number of UPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a UPI link. Use edge detect to count the number of instances when the UPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "EventCode": "0x16", + "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1", + "EventCode": "0x20", + "EventName": "UNC_UPI_PHY_INIT_CYCLES", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "L1 Req Nack", + "EventCode": "0x23", + "EventName": "UNC_UPI_POWER_L1_NACK", + "PerPkg": "1", + "PublicDescription": "L1 Req Nack : Counts the number of times a link sends/receives a LinkReqNAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx originally requested the power change). A Tx LinkReqNAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).", + "Unit": "UPI" + }, + { + "BriefDescription": "L1 Req (same as L1 Ack).", + "EventCode": "0x22", + "EventName": "UNC_UPI_POWER_L1_REQ", + "PerPkg": "1", + "PublicDescription": "L1 Req (same as L1 Ack). : Counts the number of times a link sends/receives a LinkReqAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqAck refers to receiving an Ack (meaning this agent's Tx originally requested the power change). A Tx LinkReqAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles in L0p", + "EventCode": "0x25", + "EventName": "UNC_UPI_RxL0P_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles in L0", + "EventCode": "0x24", + "EventName": "UNC_UPI_RxL0_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Cycles in L0 : Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", + "PerPkg": "1", + "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0xe", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC", + "PerPkg": "1", + "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x10e", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", + "PerPkg": "1", + "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0xf", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC", + "PerPkg": "1", + "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x10f", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Request", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", + "PerPkg": "1", + "PublicDescription": "Matches on Receive path of a UPI Port : Request : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Request, Match Opcode", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC", + "PerPkg": "1", + "PublicDescription": "Matches on Receive path of a UPI Port : Request, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x108", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Response - Conflict", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT", + "PerPkg": "1", + "PublicDescription": "Matches on Receive path of a UPI Port : Response - Conflict : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x1aa", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Response - Invalid", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI", + "PerPkg": "1", + "PublicDescription": "Matches on Receive path of a UPI Port : Response - Invalid : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x12a", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Response - Data", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", + "PerPkg": "1", + "PublicDescription": "Matches on Receive path of a UPI Port : Response - Data : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0xc", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Response - Data, Match Opcode", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC", + "PerPkg": "1", + "PublicDescription": "Matches on Receive path of a UPI Port : Response - Data, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x10c", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA", + "PerPkg": "1", + "PublicDescription": "Matches on Receive path of a UPI Port : Response - No Data : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0xa", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data, Match Opcode", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", + "PerPkg": "1", + "PublicDescription": "Matches on Receive path of a UPI Port : Response - No Data, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x10a", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Snoop", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", + "PerPkg": "1", + "PublicDescription": "Matches on Receive path of a UPI Port : Snoop : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x9", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Snoop, Match Opcode", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC", + "PerPkg": "1", + "PublicDescription": "Matches on Receive path of a UPI Port : Snoop, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x109", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Writeback", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB", + "PerPkg": "1", + "PublicDescription": "Matches on Receive path of a UPI Port : Writeback : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0xd", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Writeback, Match Opcode", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC", + "PerPkg": "1", + "PublicDescription": "Matches on Receive path of a UPI Port : Writeback, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x10d", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 0", + "EventCode": "0x31", + "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", + "PerPkg": "1", + "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 0 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 1", + "EventCode": "0x31", + "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", + "PerPkg": "1", + "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 1 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 2", + "EventCode": "0x31", + "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", + "PerPkg": "1", + "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 2 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "CRC Errors Detected", + "EventCode": "0x0B", + "EventName": "UNC_UPI_RxL_CRC_ERRORS", + "PerPkg": "1", + "PublicDescription": "CRC Errors Detected : Number of CRC errors detected in the UPI Agent. Each UPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the UPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).", + "Unit": "UPI" + }, + { + "BriefDescription": "LLR Requests Sent", + "EventCode": "0x08", + "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT", + "PerPkg": "1", + "PublicDescription": "LLR Requests Sent : Number of LLR Requests were transmitted. This should generally be <= the number of CRC errors detected. If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs.", + "Unit": "UPI" + }, + { + "BriefDescription": "VN0 Credit Consumed", + "EventCode": "0x39", + "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0", + "PerPkg": "1", + "PublicDescription": "VN0 Credit Consumed : Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", + "Unit": "UPI" + }, + { + "BriefDescription": "VN1 Credit Consumed", + "EventCode": "0x3A", + "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1", + "PerPkg": "1", + "PublicDescription": "VN1 Credit Consumed : Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", + "Unit": "UPI" + }, + { + "BriefDescription": "VNA Credit Consumed", + "EventCode": "0x38", + "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA", + "PerPkg": "1", + "PublicDescription": "VNA Credit Consumed : Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : All Data", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", + "PerPkg": "1", + "PublicDescription": "Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c).", + "UMask": "0xf", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : Null FLITs received from any slot", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", + "PerPkg": "1", + "PublicDescription": "Valid Flits Received : Null FLITs received from any slot : Shows legal flit time (hides impact of L0p and L0c).", + "UMask": "0x27", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : Data", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.DATA", + "PerPkg": "1", + "PublicDescription": "Valid Flits Received : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : Null FLITs received from any slot", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.IDLE", + "PerPkg": "1", + "PublicDescription": "Valid Flits Received : Null FLITs received from any slot : Shows legal flit time (hides impact of L0p and L0c).", + "UMask": "0x47", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : LLCRD Not Empty", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.LLCRD", + "PerPkg": "1", + "PublicDescription": "Valid Flits Received : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : LLCTRL", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.LLCTRL", + "PerPkg": "1", + "PublicDescription": "Valid Flits Received : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.", + "UMask": "0x40", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : All Non Data", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", + "PerPkg": "1", + "PublicDescription": "Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c).", + "UMask": "0x97", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Empty", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.NULL", + "PerPkg": "1", + "PublicDescription": "Valid Flits Received : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : Protocol Header", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.PROTHDR", + "PerPkg": "1", + "PublicDescription": "Valid Flits Received : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)", + "UMask": "0x80", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : Slot 0", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.SLOT0", + "PerPkg": "1", + "PublicDescription": "Valid Flits Received : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : Slot 1", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.SLOT1", + "PerPkg": "1", + "PublicDescription": "Valid Flits Received : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : Slot 2", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.SLOT2", + "PerPkg": "1", + "PublicDescription": "Valid Flits Received : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Flit Buffer Allocations : Slot 0", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT0", + "PerPkg": "1", + "PublicDescription": "RxQ Flit Buffer Allocations : Slot 0 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Flit Buffer Allocations : Slot 1", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT1", + "PerPkg": "1", + "PublicDescription": "RxQ Flit Buffer Allocations : Slot 1 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Flit Buffer Allocations : Slot 2", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT2", + "PerPkg": "1", + "PublicDescription": "RxQ Flit Buffer Allocations : Slot 2 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets : Slot 0", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0", + "PerPkg": "1", + "PublicDescription": "RxQ Occupancy - All Packets : Slot 0 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets : Slot 1", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1", + "PerPkg": "1", + "PublicDescription": "RxQ Occupancy - All Packets : Slot 1 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets : Slot 2", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2", + "PerPkg": "1", + "PublicDescription": "RxQ Occupancy - All Packets : Slot 2 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles in L0p", + "EventCode": "0x27", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "EventCode": "0x28", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "EventCode": "0x29", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles in L0", + "EventCode": "0x26", + "EventName": "UNC_UPI_TxL0_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Cycles in L0 : Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", + "PerPkg": "1", + "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0xe", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC", + "PerPkg": "1", + "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x10e", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", + "PerPkg": "1", + "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0xf", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC", + "PerPkg": "1", + "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x10f", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Request", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", + "PerPkg": "1", + "PublicDescription": "Matches on Transmit path of a UPI Port : Request : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Request, Match Opcode", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC", + "PerPkg": "1", + "PublicDescription": "Matches on Transmit path of a UPI Port : Request, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x108", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Conflict", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT", + "PerPkg": "1", + "PublicDescription": "Matches on Transmit path of a UPI Port : Response - Conflict : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x1aa", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Invalid", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI", + "PerPkg": "1", + "PublicDescription": "Matches on Transmit path of a UPI Port : Response - Invalid : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x12a", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", + "PerPkg": "1", + "PublicDescription": "Matches on Transmit path of a UPI Port : Response - Data : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0xc", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data, Match Opcode", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC", + "PerPkg": "1", + "PublicDescription": "Matches on Transmit path of a UPI Port : Response - Data, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x10c", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", + "PerPkg": "1", + "PublicDescription": "Matches on Transmit path of a UPI Port : Response - No Data : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0xa", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", + "PerPkg": "1", + "PublicDescription": "Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x10a", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Snoop", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", + "PerPkg": "1", + "PublicDescription": "Matches on Transmit path of a UPI Port : Snoop : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x9", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Snoop, Match Opcode", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC", + "PerPkg": "1", + "PublicDescription": "Matches on Transmit path of a UPI Port : Snoop, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x109", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Writeback", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB", + "PerPkg": "1", + "PublicDescription": "Matches on Transmit path of a UPI Port : Writeback : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0xd", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Writeback, Match Opcode", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC", + "PerPkg": "1", + "PublicDescription": "Matches on Transmit path of a UPI Port : Writeback, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", + "UMask": "0x10d", + "Unit": "UPI" + }, + { + "BriefDescription": "Tx Flit Buffer Bypassed", + "EventCode": "0x41", + "EventName": "UNC_UPI_TxL_BYPASSED", + "PerPkg": "1", + "PublicDescription": "Tx Flit Buffer Bypassed : Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the UPI Link. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : All Data", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : All Data : Shows legal flit time (hides impact of L0p and L0c).", + "UMask": "0xf", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : Null FLITs transmitted to any slot", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : Null FLITs transmitted to any slot : Shows legal flit time (hides impact of L0p and L0c).", + "UMask": "0x27", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : Data", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.DATA", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : Idle", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.IDLE", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : Idle : Shows legal flit time (hides impact of L0p and L0c).", + "UMask": "0x47", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : LLCRD Not Empty", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.LLCRD", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : LLCTRL", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.LLCTRL", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.", + "UMask": "0x40", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : All Non Data", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c).", + "UMask": "0x97", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.NULL", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : Protocol Header", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.PROTHDR", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)", + "UMask": "0x80", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : Slot 0", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.SLOT0", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : Slot 1", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.SLOT1", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : Slot 2", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.SLOT2", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "Tx Flit Buffer Allocations", + "EventCode": "0x40", + "EventName": "UNC_UPI_TxL_INSERTS", + "PerPkg": "1", + "PublicDescription": "Tx Flit Buffer Allocations : Number of allocations into the UPI Tx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", + "Unit": "UPI" + }, + { + "BriefDescription": "Tx Flit Buffer Occupancy", + "EventCode": "0x42", + "EventName": "UNC_UPI_TxL_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Tx Flit Buffer Occupancy : Accumulates the number of flits in the TxQ. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "EventCode": "0x45", + "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "VNA Credits Pending Return - Occupancy", + "EventCode": "0x44", + "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "VNA Credits Pending Return - Occupancy : Number of VNA credits in the Rx side that are waitng to be returned back across the link.", + "Unit": "UPI" + }, + { + "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", + "EventCode": "0xff", + "EventName": "UNC_U_CLOCKTICKS", + "PerPkg": "1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received : Doorbell", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received : Interrupt", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.INT_PRIO", + "PerPkg": "1", + "PublicDescription": "Message Received : Interrupt : Interrupts", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received : IPI", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", + "PerPkg": "1", + "PublicDescription": "Message Received : IPI : Inter Processor Interrupts", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received : MSI", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", + "PerPkg": "1", + "PublicDescription": "Message Received : MSI : Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received : VLW", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", + "PerPkg": "1", + "PublicDescription": "Message Received : VLW : Virtual Logical Wire (legacy) message were received from Uncore.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "IDI Lock/SplitLock Cycles", + "EventCode": "0x44", + "EventName": "UNC_U_LOCK_CYCLES", + "PerPkg": "1", + "PublicDescription": "IDI Lock/SplitLock Cycles : Number of times an IDI Lock/SplitLock sequence was started", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", + "EventCode": "0x4D", + "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", + "EventCode": "0x4D", + "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB", + "EventCode": "0x4D", + "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS", + "EventCode": "0x4D", + "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", + "EventCode": "0x4D", + "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", + "EventCode": "0x4D", + "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB", + "EventCode": "0x4D", + "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS", + "EventCode": "0x4D", + "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", + "EventCode": "0x4F", + "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", + "EventCode": "0x4F", + "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK", + "EventCode": "0x45", + "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", + "PerPkg": "1", + "PublicDescription": "Cycles PHOLD Assert to Ack : Assert to ACK : PHOLD cycles.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_RACU_DRNG.RDRAND", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.RDRAND", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_RACU_DRNG.RDSEED", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.RDSEED", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "RACU Request", + "EventCode": "0x46", + "EventName": "UNC_U_RACU_REQUESTS", + "PerPkg": "1", + "PublicDescription": "RACU Request : Number outstanding register requests within message channel tracker", + "Unit": "UBOX" + } +] diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-io.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-io.json new file mode 100644 index 000000000000..9cef8862c428 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-io.json @@ -0,0 +1,9270 @@ +[ + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN", + "PerPkg": "1", + "UMask": "0x22", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN", + "PerPkg": "1", + "UMask": "0x23", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN", + "PerPkg": "1", + "UMask": "0x25", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN", + "PerPkg": "1", + "UMask": "0x26", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN", + "PerPkg": "1", + "UMask": "0x27", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller", + "EventCode": "0x01", + "EventName": "UNC_IIO_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Clockticks of the integrated IO (IIO) traffic controller : Increments counter once every Traffic Controller clock, the LSCLK (500MHz)", + "Unit": "IIO" + }, + { + "BriefDescription": "Free running counter that increments for IIO clocktick", + "EventCode": "0xff", + "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", + "PerPkg": "1", + "PublicDescription": "Free running counter that increments for integrated IO (IIO) traffic controller clockticks", + "UMask": "0x10", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts : All Ports", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0xff", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7", + "UMask": "0xff", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7", + "UMask": "0xff", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 1", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 2", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 3", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 3 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 4", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 4 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 5", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 5 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 6", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 6 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 7", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 7 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests : Passing data to be written", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests : Passing data to be written : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests : Issuing final read or write of line", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests : Issuing final read or write of line : How often different queues (e.g. channel / fc) ask to send request into pipeline", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests : Processing response from IOMMU", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests : Processing response from IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests : Issuing to IOMMU", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests : Issuing to IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests : Request Ownership", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests : Request Ownership : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests : Writing line", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests : Writing line : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests granted : Passing data to be written", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.DATA", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests granted : Passing data to be written : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests granted : Issuing final read or write of line", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests granted : Issuing final read or write of line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests granted : Processing response from IOMMU", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests granted : Processing response from IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests granted : Issuing to IOMMU", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests granted : Issuing to IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests granted : Request Ownership", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests granted : Request Ownership : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests granted : Writing line", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests granted : Writing line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOTLB Hits to a 1G Page", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.1G_HITS", + "PerPkg": "1", + "PublicDescription": ": IOTLB Hits to a 1G Page : Counts if a transaction to a 1G page, on its first lookup, hits the IOTLB.", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOTLB Hits to a 2M Page", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.2M_HITS", + "PerPkg": "1", + "PublicDescription": ": IOTLB Hits to a 2M Page : Counts if a transaction to a 2M page, on its first lookup, hits the IOTLB.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOTLB Hits to a 4K Page", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.4K_HITS", + "PerPkg": "1", + "PublicDescription": ": IOTLB Hits to a 4K Page : Counts if a transaction to a 4K page, on its first lookup, hits the IOTLB.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOTLB lookups all", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS", + "PerPkg": "1", + "PublicDescription": ": IOTLB lookups all : Some transactions have to look up IOTLB multiple times. Counts every time a request looks up IOTLB.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": ": Context cache hits", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS", + "PerPkg": "1", + "PublicDescription": ": Context cache hits : Counts each time a first look up of the transaction hits the RCC.", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": ": Context cache lookups", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS", + "PerPkg": "1", + "PublicDescription": ": Context cache lookups : Counts each time a transaction looks up root context cache.", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOTLB lookups first", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS", + "PerPkg": "1", + "PublicDescription": ": IOTLB lookups first : Some transactions have to look up IOTLB multiple times. Counts the first time a request looks up IOTLB.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOTLB Fills (same as IOTLB miss)", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.MISSES", + "PerPkg": "1", + "PublicDescription": ": IOTLB Fills (same as IOTLB miss) : When a transaction misses IOTLB, it does a page walk to look up memory and bring in the relevant page translation. Counts when this page translation is written to IOTLB.", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": ": Cycles PWT full", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.CYC_PWT_FULL", + "PerPkg": "1", + "PublicDescription": ": Cycles PWT full : Counts cycles the IOMMU has reached its maximum limit for outstanding page walks.", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOMMU memory access", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES", + "PerPkg": "1", + "PublicDescription": ": IOMMU memory access : IOMMU sends out memory fetches when it misses the cache look up which is indicated by this signal. M2IOSF only uses low priority channel", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": ": PWC Hit to a 1G page", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS", + "PerPkg": "1", + "PublicDescription": ": PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": ": PWC Hit to a 2M page", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS", + "PerPkg": "1", + "PublicDescription": ": PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": ": PWC Hit to a 4K page", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_4K_HITS", + "PerPkg": "1", + "PublicDescription": ": PWC Hit to a 4K page : Counts each time a transaction's first look up hits the SLPWC at the 4K level", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": ": PWT Hit to a 256T page", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS", + "PerPkg": "1", + "PublicDescription": ": PWT Hit to a 256T page : Counts each time a transaction's first look up hits the SLPWC at the 512G level", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": ": PageWalk cache fill", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS", + "PerPkg": "1", + "PublicDescription": ": PageWalk cache fill : When a transaction misses SLPWC, it does a page walk to look up memory and bring in the relevant page translation. When this page translation is written to SLPWC, ObsPwcFillValid_nnnH is asserted.", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": ": PageWalk cache lookup", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS", + "PerPkg": "1", + "PublicDescription": ": PageWalk cache lookup : Counts each time a transaction looks up second level page walk cache.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": ": Interrupt Entry cache hit", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS", + "PerPkg": "1", + "PublicDescription": ": Interrupt Entry cache hit : Counts each time a transaction's first look up hits the IEC.", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": ": Interrupt Entry cache lookup", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS", + "PerPkg": "1", + "PublicDescription": ": Interrupt Entry cache lookup : Counts the number of transaction looks up that interrupt remapping cache.", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": ": Device-selective Context cache invalidation cycles", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DEVICE", + "PerPkg": "1", + "PublicDescription": ": Device-selective Context cache invalidation cycles : Counts number of Device selective context cache invalidation events", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": ": Domain-selective Context cache invalidation cycles", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DOMAIN", + "PerPkg": "1", + "PublicDescription": ": Domain-selective Context cache invalidation cycles : Counts number of Domain selective context cache invalidation events", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": ": Context cache global invalidation cycles", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_GBL", + "PerPkg": "1", + "PublicDescription": ": Context cache global invalidation cycles : Counts number of Context Cache global invalidation events", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": ": Domain-selective IOTLB invalidation cycles", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_DOMAIN", + "PerPkg": "1", + "PublicDescription": ": Domain-selective IOTLB invalidation cycles : Counts number of Domain selective invalidation events", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": ": Global IOTLB invalidation cycles", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_GBL", + "PerPkg": "1", + "PublicDescription": ": Global IOTLB invalidation cycles : Indicates that IOMMU is doing global invalidation.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": ": Page-selective IOTLB invalidation cycles", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PAGE", + "PerPkg": "1", + "PublicDescription": ": Page-selective IOTLB invalidation cycles : Counts number of Page-selective within Domain Invalidation events", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0", + "PerPkg": "1", + "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus : Asserted if all bits specified by mask match", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1", + "PerPkg": "1", + "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if all bits specified by mask match", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1", + "PerPkg": "1", + "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if all bits specified by mask match", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus : PCIE bus", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1", + "PerPkg": "1", + "PublicDescription": "AND Mask/match for debug bus : PCIE bus : Asserted if all bits specified by mask match", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1", + "PerPkg": "1", + "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if all bits specified by mask match", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1", + "PerPkg": "1", + "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if all bits specified by mask match", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0", + "PerPkg": "1", + "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus : Asserted if any bits specified by mask match", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1", + "PerPkg": "1", + "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if any bits specified by mask match", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1", + "PerPkg": "1", + "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if any bits specified by mask match", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus : PCIE bus", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1", + "PerPkg": "1", + "PublicDescription": "OR Mask/match for debug bus : PCIE bus : Asserted if any bits specified by mask match", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1", + "PerPkg": "1", + "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if any bits specified by mask match", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1", + "PerPkg": "1", + "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if any bits specified by mask match", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Counting disabled", + "EventCode": "0x80", + "EventName": "UNC_IIO_NOTHING", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Occupancy of outbound request queue : To device", + "EventCode": "0xC5", + "EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Occupancy of outbound request queue : To device : Counts number of outbound requests/completions IIO is currently processing", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": ": Passing data to be written", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": ": Passing data to be written : Only for posted requests", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": ": Issuing final read or write of line", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": ": Processing response from IOMMU", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": ": Issuing to IOMMU", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": ": Request Ownership", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": ": Request Ownership : Only for posted requests", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": ": Writing line", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": ": Writing line : Only for posted requests", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number requests sent to PCIe from main die : From IRP", + "EventCode": "0xC2", + "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.IRP", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Number requests sent to PCIe from main die : From IRP : Captures Posted/Non-posted allocations from IRP. i.e. either non-confined P2P traffic or from the CPU", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number requests sent to PCIe from main die : From ITC", + "EventCode": "0xC2", + "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.ITC", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Number requests sent to PCIe from main die : From ITC : Confined P2P", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number requests sent to PCIe from main die : Completion allocations", + "EventCode": "0xc2", + "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.PREALLOC", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number requests PCIe makes of the main die : Drop request", + "EventCode": "0x85", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU.ALL.DROP", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Number requests PCIe makes of the main die : Drop request : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU. : Packet error detected, must be dropped", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number requests PCIe makes of the main die : All", + "EventCode": "0x85", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Abort", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Confined P2P", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Local P2P", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Multi-cast", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Memory", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : MsgB", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Remote P2P", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Ubox", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "ITC address map 1", + "EventCode": "0x8F", + "EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Outbound cacheline requests issued : 64B requests issued to device", + "EventCode": "0xD0", + "EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Outbound cacheline requests issued : 64B requests issued to device : Each outbound cacheline granular request may need to make multiple passes through the pipeline. Each time a cacheline completes all its passes it advances line", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Outbound TLP (transaction layer packet) requests issued : To device", + "EventCode": "0xD1", + "EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Outbound TLP (transaction layer packet) requests issued : To device : Each time an outbound completes all its passes it advances the pointer", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "PWT occupancy", + "EventCode": "0x42", + "EventName": "UNC_IIO_PWT_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "PWT occupancy : Indicates how many page walks are outstanding at any point in time.", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request - cacheline complete : Passing data to be written", + "EventCode": "0x91", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request - cacheline complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request - cacheline complete : Issuing final read or write of line", + "EventCode": "0x91", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request - cacheline complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request - cacheline complete : Request Ownership", + "EventCode": "0x91", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request - cacheline complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request - cacheline complete : Writing line", + "EventCode": "0x91", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request - cacheline complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request complete : Passing data to be written", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.DATA", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request complete : Issuing final read or write of line", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request complete : Processing response from IOMMU", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request complete : Processing response from IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request complete : Issuing to IOMMU", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request complete : Issuing to IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request complete : Request Ownership", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request complete : Writing line", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request - pass complete : Passing data to be written", + "EventCode": "0x90", + "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request - pass complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request - pass complete : Issuing final read or write of line", + "EventCode": "0x90", + "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request - pass complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request - pass complete : Request Ownership", + "EventCode": "0x90", + "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request - pass complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request - pass complete : Writing line", + "EventCode": "0x90", + "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request - pass complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Symbol Times on Link", + "EventCode": "0x82", + "EventName": "UNC_IIO_SYMBOL_TIMES", + "PerPkg": "1", + "PublicDescription": "Symbol Times on Link : Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10", + "EventCode": "0x81", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8", + "EventCode": "0x81", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9", + "EventCode": "0x81", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10", + "EventCode": "0x83", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8", + "EventCode": "0x83", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9", + "EventCode": "0x83", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10", + "EventCode": "0x89", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8", + "EventCode": "0x89", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9", + "EventCode": "0x89", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10", + "EventCode": "0x8b", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8", + "EventCode": "0x8b", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9", + "EventCode": "0x8b", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10", + "EventCode": "0x85", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8", + "EventCode": "0x85", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9", + "EventCode": "0x85", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10", + "EventCode": "0x87", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8", + "EventCode": "0x87", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9", + "EventCode": "0x87", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10", + "EventCode": "0x8d", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8", + "EventCode": "0x8d", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9", + "EventCode": "0x8d", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10", + "EventCode": "0x8f", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8", + "EventCode": "0x8f", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9", + "EventCode": "0x8f", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Clockticks of the mesh to PCI (M2P)", + "EventCode": "0x01", + "EventName": "UNC_M2P_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Clockticks of the mesh to PCI (M2P) : Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Clockticks", + "EventCode": "0xc0", + "EventName": "UNC_M2P_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Distress signal asserted : DPT Local", + "EventCode": "0xaf", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_LOCAL", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Distress signal asserted : DPT Remote", + "EventCode": "0xaf", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_NONLOCAL", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Distress signal asserted : DPT Stalled - IV", + "EventCode": "0xaf", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_IV", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit", + "EventCode": "0xaf", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_NOCRD", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Distress signal asserted : Horizontal", + "EventCode": "0xaf", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.HORZ", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Distress signal asserted : PMM Local", + "EventCode": "0xAF", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.PMM_LOCAL", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Distress signal asserted : PMM Remote", + "EventCode": "0xAF", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.PMM_NONLOCAL", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Distress signal asserted : Vertical", + "EventCode": "0xaf", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.VERT", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Down", + "EventCode": "0xba", + "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Up", + "EventCode": "0xba", + "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Left and Even", + "EventCode": "0xb6", + "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", + "EventCode": "0xb6", + "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Right and Even", + "EventCode": "0xb6", + "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", + "EventCode": "0xb6", + "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "EventCode": "0xbb", + "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "EventCode": "0xbb", + "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "EventCode": "0xbb", + "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "EventCode": "0xbb", + "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "EventCode": "0xb7", + "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "EventCode": "0xb7", + "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "EventCode": "0xb7", + "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "EventCode": "0xb7", + "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Left and Even", + "EventCode": "0xb8", + "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", + "EventCode": "0xb8", + "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Right and Even", + "EventCode": "0xb8", + "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", + "EventCode": "0xb8", + "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal IV Ring in Use : Left", + "EventCode": "0xb9", + "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal IV Ring in Use : Right", + "EventCode": "0xb9", + "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS", + "EventCode": "0x34", + "EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the DRS message class.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB", + "EventCode": "0x34", + "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCB message class.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS", + "EventCode": "0x34", + "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCS message class.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCB", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCS", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCB", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCS", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCB", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCS", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCB", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCS", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCB", + "EventCode": "0x47", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCS", + "EventCode": "0x47", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCB", + "EventCode": "0x47", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCS", + "EventCode": "0x47", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCB", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCS", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCB", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCS", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCB", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCS", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCB", + "EventCode": "0x1a", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCS", + "EventCode": "0x1a", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCB", + "EventCode": "0x1a", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCS", + "EventCode": "0x1a", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Shared Credits Returned : Agent0", + "EventCode": "0x17", + "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Shared Credits Returned : Agent1", + "EventCode": "0x17", + "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Shared Credits Returned : Agent2", + "EventCode": "0x17", + "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent0", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent1", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent2", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent3", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent4", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent5", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCB", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCS", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCB", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCS", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCB", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCS", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCB", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCS", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCB", + "EventCode": "0x41", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCS", + "EventCode": "0x41", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCB", + "EventCode": "0x41", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCS", + "EventCode": "0x41", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCB", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCS", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCB", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCS", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCB", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCS", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCB", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCS", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCB", + "EventCode": "0x4b", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCS", + "EventCode": "0x4b", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCB", + "EventCode": "0x4b", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCS", + "EventCode": "0x4b", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0", + "EventCode": "0xe6", + "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1", + "EventCode": "0xe6", + "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "P2P Credit Occupancy : All", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "P2P Credit Occupancy : Local NCB", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "P2P Credit Occupancy : Local NCS", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "P2P Credit Occupancy : Remote NCB", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "P2P Credit Occupancy : Remote NCS", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Dedicated Credits Received : All", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Dedicated Credits Received : Local NCB", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Dedicated Credits Received : Local NCS", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Dedicated Credits Received : Remote NCB", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Dedicated Credits Received : Remote NCS", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Shared Credits Received : All", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Shared Credits Received : Local NCB", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Shared Credits Received : Local NCS", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Shared Credits Received : Remote NCB", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Shared Credits Received : Remote NCS", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - DRS", + "EventCode": "0x48", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_DRS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCB", + "EventCode": "0x48", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCB", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCS", + "EventCode": "0x48", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - DRS", + "EventCode": "0x48", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_DRS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCB", + "EventCode": "0x48", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCS", + "EventCode": "0x48", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - DRS", + "EventCode": "0x49", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_DRS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCB", + "EventCode": "0x49", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCB", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCS", + "EventCode": "0x49", + "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 - NCB", + "EventCode": "0x1b", + "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 - NCS", + "EventCode": "0x1b", + "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 - NCB", + "EventCode": "0x1b", + "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 - NCS", + "EventCode": "0x1b", + "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 - NCB", + "EventCode": "0x1b", + "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 - NCS", + "EventCode": "0x1b", + "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Shared Credits Returned : Agent0", + "EventCode": "0x18", + "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Shared Credits Returned : Agent1", + "EventCode": "0x18", + "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Shared Credits Returned : Agent2", + "EventCode": "0x18", + "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent0", + "EventCode": "0x45", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent1", + "EventCode": "0x45", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent2", + "EventCode": "0x45", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - DRS", + "EventCode": "0x42", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_DRS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - NCB", + "EventCode": "0x42", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCB", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - NCS", + "EventCode": "0x42", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - DRS", + "EventCode": "0x42", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_DRS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - NCB", + "EventCode": "0x42", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - NCS", + "EventCode": "0x42", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - DRS", + "EventCode": "0x43", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_DRS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - NCB", + "EventCode": "0x43", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCB", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - NCS", + "EventCode": "0x43", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - DRS", + "EventCode": "0x4c", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_DRS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCB", + "EventCode": "0x4c", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCB", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCS", + "EventCode": "0x4c", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - DRS", + "EventCode": "0x4c", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_DRS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCB", + "EventCode": "0x4c", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCS", + "EventCode": "0x4c", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - DRS", + "EventCode": "0x4d", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_DRS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCB", + "EventCode": "0x4d", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCB", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCS", + "EventCode": "0x4d", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD", + "EventCode": "0xac", + "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK", + "EventCode": "0xac", + "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL", + "EventCode": "0xac", + "EventName": "UNC_M2P_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV", + "EventCode": "0xac", + "EventName": "UNC_M2P_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : AD", + "EventCode": "0xaa", + "EventName": "UNC_M2P_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core", + "EventCode": "0xaa", + "EventName": "UNC_M2P_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.", + "EventCode": "0xaa", + "EventName": "UNC_M2P_RING_BOUNCES_VERT.AKC", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core", + "EventCode": "0xaa", + "EventName": "UNC_M2P_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.", + "EventCode": "0xaa", + "EventName": "UNC_M2P_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : AD", + "EventCode": "0xad", + "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : AK", + "EventCode": "0xad", + "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1", + "EventCode": "0xad", + "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : BL", + "EventCode": "0xad", + "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : IV", + "EventCode": "0xad", + "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : AD", + "EventCode": "0xab", + "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core", + "EventCode": "0xab", + "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring", + "EventCode": "0xab", + "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AKC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core", + "EventCode": "0xab", + "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.", + "EventCode": "0xab", + "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Source Throttle", + "EventCode": "0xae", + "EventName": "UNC_M2P_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.ALL", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCB", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCS", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.ALL", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCB", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCS", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - All", + "EventCode": "0xe5", + "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Credited", + "EventCode": "0xe5", + "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", + "EventCode": "0xe5", + "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - All", + "EventCode": "0xe5", + "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Credited", + "EventCode": "0xe5", + "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", + "EventCode": "0xe5", + "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - All", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - Credited", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AK", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - All", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - Credited", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : IV", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - All", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Credited", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : AK", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - All", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Credited", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : IFV - Credited", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : IV", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation", + "EventCode": "0xe4", + "EventName": "UNC_M2P_RxR_CRD_STARVED_1", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - All", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - Credited", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AK", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - All", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - Credited", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : IV", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - All", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AK", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - All", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : IV", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0", + "EventCode": "0xd0", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1", + "EventCode": "0xd0", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2", + "EventCode": "0xd0", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3", + "EventCode": "0xd0", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4", + "EventCode": "0xd0", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5", + "EventCode": "0xd0", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6", + "EventCode": "0xd0", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7", + "EventCode": "0xd0", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0", + "EventCode": "0xd2", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1", + "EventCode": "0xd2", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2", + "EventCode": "0xd2", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3", + "EventCode": "0xd2", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4", + "EventCode": "0xd2", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5", + "EventCode": "0xd2", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6", + "EventCode": "0xd2", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7", + "EventCode": "0xd2", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0", + "EventCode": "0xd4", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1", + "EventCode": "0xd4", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2", + "EventCode": "0xd4", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3", + "EventCode": "0xd4", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4", + "EventCode": "0xd4", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5", + "EventCode": "0xd4", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6", + "EventCode": "0xd4", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7", + "EventCode": "0xd4", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0", + "EventCode": "0xd6", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1", + "EventCode": "0xd6", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2", + "EventCode": "0xd6", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3", + "EventCode": "0xd6", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4", + "EventCode": "0xd6", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5", + "EventCode": "0xd6", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6", + "EventCode": "0xd6", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7", + "EventCode": "0xd6", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10", + "EventCode": "0xd1", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8", + "EventCode": "0xd1", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9", + "EventCode": "0xd1", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10", + "EventCode": "0xd3", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8", + "EventCode": "0xd3", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9", + "EventCode": "0xd3", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10", + "EventCode": "0xd5", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8", + "EventCode": "0xd5", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9", + "EventCode": "0xd5", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10", + "EventCode": "0xd7", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8", + "EventCode": "0xd7", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9", + "EventCode": "0xd7", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "UNC_M2P_TxC_CREDITS.PMM", + "EventCode": "0x2D", + "EventName": "UNC_M2P_TxC_CREDITS.PMM", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ", + "EventCode": "0x2d", + "EventName": "UNC_M2P_TxC_CREDITS.PRQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress", + "EventCode": "0x24", + "EventName": "UNC_M2P_TxC_INSERTS.AD_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress", + "EventCode": "0x24", + "EventName": "UNC_M2P_TxC_INSERTS.AD_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress", + "EventCode": "0x24", + "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress", + "EventCode": "0x24", + "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress", + "EventCode": "0x24", + "EventName": "UNC_M2P_TxC_INSERTS.BL_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress", + "EventCode": "0x24", + "EventName": "UNC_M2P_TxC_INSERTS.BL_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - All", + "EventCode": "0xa6", + "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", + "EventCode": "0xa6", + "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", + "EventCode": "0xa6", + "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - All", + "EventCode": "0xa6", + "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", + "EventCode": "0xa6", + "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", + "EventCode": "0xa6", + "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - All", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AK", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - All", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : IV", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AK", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.IV", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AK", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.IV", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AK", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : IV", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AK", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : IV", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AK", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : IV", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All", + "EventCode": "0xa5", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited", + "EventCode": "0xa5", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK", + "EventCode": "0xa5", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited", + "EventCode": "0xa5", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All", + "EventCode": "0xa5", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited", + "EventCode": "0xa5", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV", + "EventCode": "0xa5", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "EventCode": "0x9c", + "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "EventCode": "0x9c", + "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "EventCode": "0x9c", + "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "EventCode": "0x9c", + "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "EventCode": "0x9d", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "EventCode": "0x9d", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", + "EventCode": "0x9d", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", + "EventCode": "0x9d", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "EventCode": "0x9d", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "EventCode": "0x9d", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", + "EventCode": "0x9d", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.IV_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", + "EventCode": "0x9e", + "EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", + "EventCode": "0x9e", + "EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1", + "EventCode": "0x94", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1", + "EventCode": "0x94", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1", + "EventCode": "0x94", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0", + "EventCode": "0x95", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1", + "EventCode": "0x95", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1", + "EventCode": "0x96", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1", + "EventCode": "0x96", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1", + "EventCode": "0x96", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0", + "EventCode": "0x97", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1", + "EventCode": "0x97", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : IV", + "EventCode": "0x98", + "EventName": "UNC_M2P_TxR_VERT_NACK0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", + "EventCode": "0x99", + "EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", + "EventCode": "0x99", + "EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0", + "EventCode": "0x9a", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1", + "EventCode": "0x9a", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0", + "EventCode": "0x9a", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1", + "EventCode": "0x9a", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0", + "EventCode": "0x9a", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1", + "EventCode": "0x9a", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : IV", + "EventCode": "0x9a", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", + "EventCode": "0x9b", + "EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1", + "EventCode": "0x9b", + "EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", + "EventCode": "0x9b", + "EventName": "UNC_M2P_TxR_VERT_STARVED1.TGC", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Down and Even", + "EventCode": "0xb0", + "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Down and Odd", + "EventCode": "0xb0", + "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Up and Even", + "EventCode": "0xb0", + "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Up and Odd", + "EventCode": "0xb0", + "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Down and Even", + "EventCode": "0xb4", + "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", + "EventCode": "0xb4", + "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Up and Even", + "EventCode": "0xb4", + "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", + "EventCode": "0xb4", + "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Down and Even", + "EventCode": "0xb1", + "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Down and Odd", + "EventCode": "0xb1", + "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Up and Even", + "EventCode": "0xb1", + "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Up and Odd", + "EventCode": "0xb1", + "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Down and Even", + "EventCode": "0xb2", + "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Down and Odd", + "EventCode": "0xb2", + "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Up and Even", + "EventCode": "0xb2", + "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Up and Odd", + "EventCode": "0xb2", + "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical IV Ring in Use : Down", + "EventCode": "0xb3", + "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical IV Ring in Use : Up", + "EventCode": "0xb3", + "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Down and Even", + "EventCode": "0xb5", + "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", + "EventCode": "0xb5", + "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Up and Even", + "EventCode": "0xb5", + "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", + "EventCode": "0xb5", + "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2PCIe" + } +] diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json deleted file mode 100644 index 134b54da0869..000000000000 --- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json +++ /dev/null @@ -1,33697 +0,0 @@ -[ - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL", - "Deprecated": "1", - "EventCode": "0x65", - "EventName": "UNC_CHA_2LM_NM_INVITOX.LOCAL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE", - "Deprecated": "1", - "EventCode": "0x65", - "EventName": "UNC_CHA_2LM_NM_INVITOX.REMOTE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT", - "Deprecated": "1", - "EventCode": "0x65", - "EventName": "UNC_CHA_2LM_NM_INVITOX.SETCONFLICT", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC", - "Deprecated": "1", - "EventCode": "0x64", - "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.LLC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF", - "Deprecated": "1", - "EventCode": "0x64", - "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.SF", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR", - "Deprecated": "1", - "EventCode": "0x64", - "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.TOR", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR", - "Deprecated": "1", - "EventCode": "0x70", - "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS2.MEMWR", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI", - "Deprecated": "1", - "EventCode": "0x70", - "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS2.MEMWRNI", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10", - "EventCode": "0x81", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8", - "EventCode": "0x81", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9", - "EventCode": "0x81", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10", - "EventCode": "0x83", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8", - "EventCode": "0x83", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9", - "EventCode": "0x83", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10", - "EventCode": "0x89", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8", - "EventCode": "0x89", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9", - "EventCode": "0x89", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10", - "EventCode": "0x8B", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8", - "EventCode": "0x8B", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9", - "EventCode": "0x8B", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10", - "EventCode": "0x85", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8", - "EventCode": "0x85", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9", - "EventCode": "0x85", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10", - "EventCode": "0x87", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8", - "EventCode": "0x87", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9", - "EventCode": "0x87", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10", - "EventCode": "0x8D", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8", - "EventCode": "0x8D", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9", - "EventCode": "0x8D", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10", - "EventCode": "0x8F", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8", - "EventCode": "0x8F", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9", - "EventCode": "0x8F", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken", - "EventCode": "0x57", - "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", - "PerPkg": "1", - "PublicDescription": "CHA to iMC Bypass : Intermediate bypass Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the intermediate bypass.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA to iMC Bypass : Not Taken", - "EventCode": "0x57", - "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", - "PerPkg": "1", - "PublicDescription": "CHA to iMC Bypass : Not Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA to iMC Bypass : Taken", - "EventCode": "0x57", - "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN", - "PerPkg": "1", - "PublicDescription": "CHA to iMC Bypass : Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the full bypass.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Clockticks of the uncore caching and home agent (CHA)", - "EventName": "UNC_CHA_CLOCKTICKS", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Clockticks", - "EventCode": "0xc0", - "EventName": "UNC_CHA_CMS_CLOCKTICKS", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE", - "PerPkg": "1", - "PublicDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0xf2", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued : Any Single Snoop", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.ANY_ONE", - "PerPkg": "1", - "PublicDescription": "Core Cross Snoops Issued : Any Single Snoop : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0xf1", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued : Multiple Core Requests", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE", - "PerPkg": "1", - "PublicDescription": "Core Cross Snoops Issued : Multiple Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x42", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued : Single Core Requests", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.CORE_ONE", - "PerPkg": "1", - "PublicDescription": "Core Cross Snoops Issued : Single Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x41", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued : Multiple Eviction", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE", - "PerPkg": "1", - "PublicDescription": "Core Cross Snoops Issued : Multiple Eviction : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x82", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued : Single Eviction", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE", - "PerPkg": "1", - "PublicDescription": "Core Cross Snoops Issued : Single Eviction : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x81", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued : Multiple External Snoops", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE", - "PerPkg": "1", - "PublicDescription": "Core Cross Snoops Issued : Multiple External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x22", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued : Single External Snoops", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EXT_ONE", - "PerPkg": "1", - "PublicDescription": "Core Cross Snoops Issued : Single External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued : Multiple Snoop Targets from Remote", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.REMOTE_GTONE", - "PerPkg": "1", - "PublicDescription": "Core Cross Snoops Issued : Multiple Snoop Targets from Remote : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x12", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued : Single Snoop Target from Remote", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.REMOTE_ONE", - "PerPkg": "1", - "PublicDescription": "Core Cross Snoops Issued : Single Snoop Target from Remote : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "Counter 0 Occupancy", - "EventCode": "0x1F", - "EventName": "UNC_CHA_COUNTER0_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Counter 0 Occupancy : Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.", - "Unit": "CHA" - }, - { - "BriefDescription": "Direct GO", - "EventCode": "0x6E", - "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Direct GO", - "EventCode": "0x6E", - "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Direct GO", - "EventCode": "0x6E", - "EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Direct GO", - "EventCode": "0x6D", - "EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Direct GO", - "EventCode": "0x6D", - "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Direct GO", - "EventCode": "0x6D", - "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Direct GO", - "EventCode": "0x6D", - "EventName": "UNC_CHA_DIRECT_GO_OPC.GO", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Direct GO", - "EventCode": "0x6D", - "EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Direct GO", - "EventCode": "0x6D", - "EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Direct GO", - "EventCode": "0x6D", - "EventName": "UNC_CHA_DIRECT_GO_OPC.NOP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Direct GO", - "EventCode": "0x6D", - "EventName": "UNC_CHA_DIRECT_GO_OPC.PULL", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Multi-socket cacheline directory state lookups : Snoop Not Needed", - "EventCode": "0x53", - "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP", - "PerPkg": "1", - "PublicDescription": "Multi-socket cacheline directory state lookups : Snoop Not Needed : Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to. : Filters for transactions that did not have to send any snoops because the directory was clean.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Multi-socket cacheline directory state lookups : Snoop Needed", - "EventCode": "0x53", - "EventName": "UNC_CHA_DIR_LOOKUP.SNP", - "PerPkg": "1", - "PublicDescription": "Multi-socket cacheline directory state lookups : Snoop Needed : Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to. : Filters for transactions that had to send one or more snoops because the directory was not clean.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Multi-socket cacheline directory state updates; memory write due to directory update from the home agent (HA) pipe", - "EventCode": "0x54", - "EventName": "UNC_CHA_DIR_UPDATE.HA", - "PerPkg": "1", - "PublicDescription": "Counts only multi-socket cacheline directory state updates memory writes issued from the home agent (HA) pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Multi-socket cacheline directory state updates; memory write due to directory update from (table of requests) TOR pipe", - "EventCode": "0x54", - "EventName": "UNC_CHA_DIR_UPDATE.TOR", - "PerPkg": "1", - "PublicDescription": "Counts only multi-socket cacheline directory state updates due to memory writes issued from the table of requests (TOR) pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Distress signal asserted : DPT Local", - "EventCode": "0xAF", - "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_LOCAL", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Distress signal asserted : DPT Remote", - "EventCode": "0xAF", - "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_NONLOCAL", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Distress signal asserted : DPT Stalled - IV", - "EventCode": "0xAF", - "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_IV", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit", - "EventCode": "0xAF", - "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_NOCRD", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Distress signal asserted : Horizontal", - "EventCode": "0xAF", - "EventName": "UNC_CHA_DISTRESS_ASSERTED.HORZ", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Distress signal asserted : PMM Local", - "EventCode": "0xAF", - "EventName": "UNC_CHA_DISTRESS_ASSERTED.PMM_LOCAL", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Distress signal asserted : PMM Remote", - "EventCode": "0xAF", - "EventName": "UNC_CHA_DISTRESS_ASSERTED.PMM_NONLOCAL", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Distress signal asserted : Vertical", - "EventCode": "0xAF", - "EventName": "UNC_CHA_DISTRESS_ASSERTED.VERT", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements : Down", - "EventCode": "0xBA", - "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", - "PerPkg": "1", - "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements : Up", - "EventCode": "0xBA", - "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", - "PerPkg": "1", - "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state", - "EventCode": "0x5F", - "EventName": "UNC_CHA_HITME_HIT.EX_RDS", - "PerPkg": "1", - "PublicDescription": "Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state. This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*).", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket ownership read requests that hit in S state.", - "EventCode": "0x5F", - "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ", - "PerPkg": "1", - "PublicDescription": "Counts Number of Hits in HitMe Cache : Remote socket ownership read requests that hit in S state. : Shared hit and op is RdInvOwn, RdInv, Inv*", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket WBMtoE requests", - "EventCode": "0x5F", - "EventName": "UNC_CHA_HITME_HIT.WBMTOE", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote socket writeback to I or S requests", - "EventCode": "0x5F", - "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S", - "PerPkg": "1", - "PublicDescription": "Counts Number of Hits in HitMe Cache : Remote socket writeback to I or S requests : op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of times HitMe Cache is accessed : Remote socket read requests", - "EventCode": "0x5E", - "EventName": "UNC_CHA_HITME_LOOKUP.READ", - "PerPkg": "1", - "PublicDescription": "Counts Number of times HitMe Cache is accessed : Remote socket read requests : op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of times HitMe Cache is accessed : Remote socket write (i.e. writeback) requests", - "EventCode": "0x5E", - "EventName": "UNC_CHA_HITME_LOOKUP.WRITE", - "PerPkg": "1", - "PublicDescription": "Counts Number of times HitMe Cache is accessed : Remote socket write (i.e. writeback) requests : op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests that are not to shared line", - "EventCode": "0x60", - "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN", - "PerPkg": "1", - "PublicDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests that are not to shared line : No SF/LLC HitS/F and op is RdInvOwn", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket read or invalidate requests", - "EventCode": "0x60", - "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV", - "PerPkg": "1", - "PublicDescription": "Counts Number of Misses in HitMe Cache : Remote socket read or invalidate requests : op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests to shared line", - "EventCode": "0x60", - "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN", - "PerPkg": "1", - "PublicDescription": "Counts Number of Misses in HitMe Cache : Remote socket RdInvOwn requests to shared line : SF/LLC HitS/F and op is RdInvOwn", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Deallocate HitME$ on Reads without RspFwdI*", - "EventCode": "0x61", - "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request", - "EventCode": "0x61", - "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", - "PerPkg": "1", - "PublicDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a local request : Received RspFwdI* for a local request, but converted HitME$ to SF entry", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache on RdInvOwn even if not RspFwdI*", - "EventCode": "0x61", - "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request", - "EventCode": "0x61", - "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM", - "PerPkg": "1", - "PublicDescription": "Counts the number of Allocate/Update to HitMe Cache : op is RspIFwd or RspIFwdWb for a remote request : Updated HitME$ on RspFwdI* or local HitM/E received for a remote request", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache : Update HitMe Cache to SHARed", - "EventCode": "0x61", - "EventName": "UNC_CHA_HITME_UPDATE.SHARED", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Left and Even", - "EventCode": "0xB6", - "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", - "EventCode": "0xB6", - "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Right and Even", - "EventCode": "0xB6", - "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", - "EventCode": "0xB6", - "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Even", - "EventCode": "0xBB", - "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", - "EventCode": "0xBB", - "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Even", - "EventCode": "0xBB", - "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", - "EventCode": "0xBB", - "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Even", - "EventCode": "0xB7", - "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", - "EventCode": "0xB7", - "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Even", - "EventCode": "0xB7", - "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", - "EventCode": "0xB7", - "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Left and Even", - "EventCode": "0xB8", - "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", - "EventCode": "0xB8", - "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Right and Even", - "EventCode": "0xB8", - "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", - "EventCode": "0xB8", - "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal IV Ring in Use : Left", - "EventCode": "0xB9", - "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", - "PerPkg": "1", - "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal IV Ring in Use : Right", - "EventCode": "0xB9", - "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", - "PerPkg": "1", - "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Normal priority reads issued to the memory controller from the CHA", - "EventCode": "0x59", - "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", - "PerPkg": "1", - "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "HA to iMC Reads Issued : ISOCH", - "EventCode": "0x59", - "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY", - "PerPkg": "1", - "PublicDescription": "HA to iMC Reads Issued : ISOCH : Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", - "PerPkg": "1", - "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to any of the memory controller channels.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", - "PerPkg": "1", - "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line : Counts the total number of full line writes issued from the HA into the memory controller.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", - "PerPkg": "1", - "PublicDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH : Counts the total number of full line writes issued from the HA into the memory controller.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", - "PerPkg": "1", - "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial : Counts the total number of full line writes issued from the HA into the memory controller.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache and Snoop Filter Lookups; Any Request", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.ALL", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.", - "UMask": "0x1fffff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : All transactions from Remote Agents", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.ALL_REMOTE", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : All transactions from Remote Agents : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x1e20ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : All Request Filter", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.ANY_F", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : All Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local or remote transaction to the LLC, including prefetch.", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.CODE", - "PerPkg": "1", - "UMask": "0x1bd0ff", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.CODE_LOCAL", - "PerPkg": "1", - "UMask": "0x19d0ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Code Reads", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Code Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x1bd0ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : CRd Request Filter", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : CRd Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : CRd Requests that come from the local socket (usually the core)", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.", - "UMask": "0x19d0ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Code Read Misses", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_MISS", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Code Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x1bd001", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : CRd Requests that come from a Remote socket.", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : CRd Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.", - "UMask": "0x1a10ff", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.CODE_REMOTE", - "PerPkg": "1", - "UMask": "0x1a10ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Local request Filter", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Local request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local transaction to the LLC, including prefetches from the Core", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD", - "PerPkg": "1", - "UMask": "0x1bc1ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions", - "UMask": "0x1bc1ff", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL", - "PerPkg": "1", - "UMask": "0x1fc1ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Data Read Request Filter", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Data Read Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Read transactions.", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request that come from the local socket (usually the core)", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions", - "UMask": "0x19c1ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Data Read Misses", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Data Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x1bc101", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Requests that come from a Remote socket", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions", - "UMask": "0x1a01ff", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DMND_READ_LOCAL", - "PerPkg": "1", - "UMask": "0x841ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : E State", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.E", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Exclusive State", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : F State", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.F", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : F State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Forward State", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Flush or Invalidate Requests", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.", - "UMask": "0x1a44ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Flush or Invalidate Requests that come from the local socket (usually the core)", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV_LOCAL", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.", - "UMask": "0x1844ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Flush or Invalidate requests that come from a Remote socket.", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV_REMOTE", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.", - "UMask": "0x1a04ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Flush or Invalidate Filter", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Flush or Invalidate Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : I State", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.I", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : I State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Miss", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache and Snoop Filter Lookups; Prefetch requests to the LLC that come from the local socket (usually the core)", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions", - "UMask": "0x189dff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Local LLC prefetch requests (from LLC) Filter", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL_F", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Local LLC prefetch requests (from LLC) Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local LLC prefetch to the LLC", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.LLC_PF_LOCAL", - "PerPkg": "1", - "UMask": "0x189dff", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOC_HOM", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.LOCALLY_HOMED_ADDRESS", - "PerPkg": "1", - "UMask": "0xbdfff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Transactions homed locally Filter", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Transactions homed locally Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC.", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Transactions homed locally", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.LOC_HOM", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Transactions homed locally : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC.", - "UMask": "0xbdfff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : M State", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.M", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : M State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Modified State", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : All Misses", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : All Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x1fe001", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Write Request Filter", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Write Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Writeback transactions to the LLC This includes all write transactions -- both Cacheable and UC.", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Remote non-snoop request Filter", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.PREF_OR_DMND_REMOTE_F", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Remote non-snoop request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Non-snoop transactions to the LLC from remote agent", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Reads", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x1bd9ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_LOC_HOM", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x9d9ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_REM_HOM", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x11d9ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Read Misses", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x1bd901", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Locally HOMed Read Misses", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_LOC_HOM", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Locally HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0xbd901", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Remotely HOMed Read Misses", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_REM_HOM", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Remotely HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x13d901", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ_OR_SNOOP_REMOTE_MISS_REM_HOM", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x161901", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ_REMOTE_LOC_HOM", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0xa19ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Reads that Hit the Snoop Filter", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ_SF_HIT", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Reads that Hit the Snoop Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x1bd90e", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REM_HOM", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.REMOTELY_HOMED_ADDRESS", - "PerPkg": "1", - "UMask": "0x15dfff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Transactions homed remotely Filter", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_F", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Transactions homed remotely Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Remote snoop request Filter", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP_F", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Remote snoop request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Snoop transactions to the LLC from remote agent", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache and Snoop Filter Lookups; Snoop Requests from a Remote Socket", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.", - "UMask": "0x1c19ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Transactions homed remotely", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.REM_HOM", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Transactions homed remotely : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Transaction whose address resides in a remote MC", - "UMask": "0x15dfff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : RFO Requests", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.RFO", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.", - "UMask": "0x1bc8ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : RFO Request Filter", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.RFO_F", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : RFO Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : RFO Requests that come from the local socket (usually the core)", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.RFO_LOCAL", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.", - "UMask": "0x19c8ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : RFO Misses", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.RFO_MISS", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : RFO Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x1bc801", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.RFO_LOCAL", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.RFO_PREF_LOCAL", - "PerPkg": "1", - "UMask": "0x888ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : RFO Requests that come from a Remote socket.", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.RFO_REMOTE", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.", - "UMask": "0x1a08ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : S State", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.S", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Shared State", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : SnoopFilter - E State", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.SF_E", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : SnoopFilter - E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit Exclusive State", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : SnoopFilter - H State", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.SF_H", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : SnoopFilter - H State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit HitMe State", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : SnoopFilter - S State", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.SF_S", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : SnoopFilter - S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit Shared State", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Filters Requests for those that write info into the cache", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Write Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.", - "UMask": "0x1a42ff", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL", - "PerPkg": "1", - "UMask": "0x842ff", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_REMOTE", - "PerPkg": "1", - "UMask": "0x17c2ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized : All Lines Victimized", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.ALL", - "PerPkg": "1", - "PublicDescription": "Lines Victimized : All Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0xf", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized : Lines in E state", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE", - "PerPkg": "1", - "PublicDescription": "Lines Victimized : Lines in E state : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized : Local - All Lines", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", - "PerPkg": "1", - "PublicDescription": "Lines Victimized : Local - All Lines : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x200f", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized : Local - Lines in E State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", - "PerPkg": "1", - "PublicDescription": "Lines Victimized : Local - Lines in E State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x2002", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized : Local - Lines in M State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", - "PerPkg": "1", - "PublicDescription": "Lines Victimized : Local - Lines in M State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x2001", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized : Local Only", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY", - "PerPkg": "1", - "PublicDescription": "Lines Victimized : Local Only : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized : Local - Lines in S State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", - "PerPkg": "1", - "PublicDescription": "Lines Victimized : Local - Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x2004", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized : Lines in M state", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE", - "PerPkg": "1", - "PublicDescription": "Lines Victimized : Lines in M state : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized : Remote - All Lines", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL", - "PerPkg": "1", - "PublicDescription": "Lines Victimized : Remote - All Lines : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x800f", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized : Remote - Lines in E State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E", - "PerPkg": "1", - "PublicDescription": "Lines Victimized : Remote - Lines in E State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x8002", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized : Remote - Lines in M State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M", - "PerPkg": "1", - "PublicDescription": "Lines Victimized : Remote - Lines in M State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x8001", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized : Remote Only", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ONLY", - "PerPkg": "1", - "PublicDescription": "Lines Victimized : Remote Only : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized : Remote - Lines in S State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S", - "PerPkg": "1", - "PublicDescription": "Lines Victimized : Remote - Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x8004", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized : Lines in S State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE", - "PerPkg": "1", - "PublicDescription": "Lines Victimized : Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cbo Misc : CV0 Prefetch Miss", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.CV0_PREF_MISS", - "PerPkg": "1", - "PublicDescription": "Cbo Misc : CV0 Prefetch Miss : Miscellaneous events in the Cbo.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Cbo Misc : CV0 Prefetch Victim", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.CV0_PREF_VIC", - "PerPkg": "1", - "PublicDescription": "Cbo Misc : CV0 Prefetch Victim : Miscellaneous events in the Cbo.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Number of times that an RFO hit in S state.", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.RFO_HIT_S", - "PerPkg": "1", - "PublicDescription": "Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cbo Misc : Silent Snoop Eviction", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE", - "PerPkg": "1", - "PublicDescription": "Cbo Misc : Silent Snoop Eviction : Miscellaneous events in the Cbo. : Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cbo Misc : Write Combining Aliasing", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.WC_ALIASING", - "PerPkg": "1", - "PublicDescription": "Cbo Misc : Write Combining Aliasing : Miscellaneous events in the Cbo. : Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0", - "EventCode": "0xE6", - "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1", - "EventCode": "0xE6", - "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "OSB Snoop Broadcast : Local InvItoE", - "EventCode": "0x55", - "EventName": "UNC_CHA_OSB.LOCAL_INVITOE", - "PerPkg": "1", - "PublicDescription": "OSB Snoop Broadcast : Local InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "OSB Snoop Broadcast : Local Rd", - "EventCode": "0x55", - "EventName": "UNC_CHA_OSB.LOCAL_READ", - "PerPkg": "1", - "PublicDescription": "OSB Snoop Broadcast : Local Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "OSB Snoop Broadcast : Off", - "EventCode": "0x55", - "EventName": "UNC_CHA_OSB.OFF_PWRHEURISTIC", - "PerPkg": "1", - "PublicDescription": "OSB Snoop Broadcast : Off : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "OSB Snoop Broadcast : Remote Rd", - "EventCode": "0x55", - "EventName": "UNC_CHA_OSB.REMOTE_READ", - "PerPkg": "1", - "PublicDescription": "OSB Snoop Broadcast : Remote Rd : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "OSB Snoop Broadcast : Remote Rd InvItoE", - "EventCode": "0x55", - "EventName": "UNC_CHA_OSB.REMOTE_READINVITOE", - "PerPkg": "1", - "PublicDescription": "OSB Snoop Broadcast : Remote Rd InvItoE : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast", - "EventCode": "0x55", - "EventName": "UNC_CHA_OSB.RFO_HITS_SNP_BCAST", - "PerPkg": "1", - "PublicDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcast : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.ADEGRCREDIT", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.AKEGRCREDIT", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.ALLRSFWAYS_RES", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.BLEGRCREDIT", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.FSF_VICP", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLOWSNP", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLWAYRSV", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_PAMATCH", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_WAYMATCH", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.HACREDIT", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.IDX_INPIPE", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.IPQ_SETMATCH_VICP", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.IRQ_PMM", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.IRQ_SETMATCH_VICP", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.ISMQ_SETMATCH_VICP", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.IVEGRCREDIT", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.LLC_WAYS_RES", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.NOTALLOWSNOOP", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.ONE_FSF_VIC", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.ONE_RSP_CON", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.PMM_MEMMODE_TORMATCH_MULTI", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.PMM_MEMMODE_TOR_MATCH", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.PRQ_PMM", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.PTL_INPIPE", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.RMW_SETMATCH", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.RRQ_SETMATCH_VICP", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.SETMATCHENTRYWSCT", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.SF_WAYS_RES", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.TOPA_MATCH", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.TORID_MATCH_GO_P", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_REQ", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_RSP", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCB", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCS", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_RSP", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_WB", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.WAY_MATCH", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL", - "EventCode": "0x65", - "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE", - "EventCode": "0x65", - "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT", - "EventCode": "0x65", - "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC", - "EventCode": "0x64", - "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC", - "PerPkg": "1", - "PublicDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC : NM evictions due to another read to the same near memory set in the LLC.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC", - "EventCode": "0x64", - "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF", - "PerPkg": "1", - "PublicDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in SF/LLC : NM evictions due to another read to the same near memory set in the SF.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in TOR", - "EventCode": "0x64", - "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR", - "PerPkg": "1", - "PublicDescription": "PMM Memory Mode related events : Counts the number of times CHA saw NM Set conflict in TOR : No Reject in the CHA due to a pending read to the same near memory set in the TOR.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC", - "EventCode": "0x70", - "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR", - "EventCode": "0x70", - "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI", - "EventCode": "0x70", - "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT", - "EventCode": "0x66", - "EventName": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_PMM_QOS.REJ_IRQ", - "EventCode": "0x66", - "EventName": "UNC_CHA_PMM_QOS.REJ_IRQ", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP", - "EventCode": "0x66", - "EventName": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_PMM_QOS.SLOW_INSERT", - "EventCode": "0x66", - "EventName": "UNC_CHA_PMM_QOS.SLOW_INSERT", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE", - "EventCode": "0x66", - "EventName": "UNC_CHA_PMM_QOS.THROTTLE", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_IRQ", - "EventCode": "0x66", - "EventName": "UNC_CHA_PMM_QOS.THROTTLE_IRQ", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_PRQ", - "EventCode": "0x66", - "EventName": "UNC_CHA_PMM_QOS.THROTTLE_PRQ", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO", - "EventCode": "0x67", - "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO", - "PerPkg": "1", - "PublicDescription": ": count # of FAST TOR Request inserted to ha_tor_req_fifo", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO", - "EventCode": "0x67", - "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO", - "PerPkg": "1", - "PublicDescription": ": count # of SLOW TOR Request inserted to ha_pmm_tor_req_fifo", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC0", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC0 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 0 only.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC1", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC1 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 1 only.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC10", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC10", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC10 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 10 only.", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC11", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC11", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC11 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 11 only.", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC12", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC12", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC12 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 12 only.", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC13", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC13", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC13 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 13 only.", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC2", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC2 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 2 only.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC3", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC3 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 3 only.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC4", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC4 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 4 only.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC5", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC5 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 5 only.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC6", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC6", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC6 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 6 only.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC7", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC7", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC7 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 7 only.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC8", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC8", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC8 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 8 only.", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC9", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC9", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC9 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 9 only.", - "Unit": "CHA" - }, - { - "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and remote INVITOE requests sent to the CHA's home agent", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.INVITOE", - "PerPkg": "1", - "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", - "UMask": "0x30", - "Unit": "CHA" - }, - { - "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and are sent to the CHA's home agent", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", - "PerPkg": "1", - "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Remote INVITOE requests (exclusive ownership of a cache line without receiving data) sent to the CHA's home agent", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Local read requests that miss the SF/LLC and remote read requests sent to the CHA's home agent", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.READS", - "PerPkg": "1", - "PublicDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) .", - "UMask": "0x3", - "Unit": "CHA" - }, - { - "BriefDescription": "Local read requests that miss the SF/LLC and are sent to the CHA's home agent", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", - "PerPkg": "1", - "PublicDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Remote read requests sent to the CHA's home agent", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Local write requests that miss the SF/LLC and remote write requests sent to the CHA's home agent", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.WRITES", - "PerPkg": "1", - "PublicDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", - "UMask": "0xc", - "Unit": "CHA" - }, - { - "BriefDescription": "Local write requests that miss the SF/LLC and are sent to the CHA's home agent", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", - "PerPkg": "1", - "PublicDescription": "Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Remote write requests sent to the CHA's home agent", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD", - "EventCode": "0xAC", - "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK", - "EventCode": "0xAC", - "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL", - "EventCode": "0xAC", - "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV", - "EventCode": "0xAC", - "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : AD", - "EventCode": "0xAA", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core", - "EventCode": "0xAA", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.", - "EventCode": "0xAA", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.AKC", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core", - "EventCode": "0xAA", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.", - "EventCode": "0xAA", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : AD", - "EventCode": "0xAD", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : AK", - "EventCode": "0xAD", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1", - "EventCode": "0xAD", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : BL", - "EventCode": "0xAD", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : IV", - "EventCode": "0xAD", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : AD", - "EventCode": "0xAB", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core", - "EventCode": "0xAB", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring", - "EventCode": "0xAB", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AKC", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core", - "EventCode": "0xAB", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.", - "EventCode": "0xAB", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Source Throttle", - "EventCode": "0xae", - "EventName": "UNC_CHA_RING_SRC_THRTL", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations : IPQ", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.IPQ", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Allocations : IPQ : Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations : IRQ", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.IRQ", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Allocations : IRQ : Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Allocations : IRQ Rejected : Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations : PRQ", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.PRQ", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations : PRQ", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations : RRQ", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.RRQ", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Allocations : RRQ : Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations : WBQ", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.WBQ", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Allocations : WBQ : Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Allow Snoop", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : ANY0", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0", - "PerPkg": "1", - "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IPQ0 Reject counter was true", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : HA", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LLC Victim", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : SF Victim", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Victim", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0", - "PerPkg": "1", - "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IRQ0 Reject counter was true", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way : Way conflict with another request that caused the reject", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC Victim", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Victim", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "ISMQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "ISMQ Retries - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "ISMQ Retries - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "ISMQ Retries - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "ISMQ Retries - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "ISMQ Retries - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "ISMQ Retries - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "ISMQ Retries - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "ISMQ Retries - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects - Set 1 : ANY0", - "EventCode": "0x25", - "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0", - "PerPkg": "1", - "PublicDescription": "ISMQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects - Set 1 : HA", - "EventCode": "0x25", - "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA", - "PerPkg": "1", - "PublicDescription": "ISMQ Rejects - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries - Set 1 : ANY0", - "EventCode": "0x2D", - "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0", - "PerPkg": "1", - "PublicDescription": "ISMQ Retries - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries - Set 1 : HA", - "EventCode": "0x2D", - "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA", - "PerPkg": "1", - "PublicDescription": "ISMQ Retries - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Occupancy : IPQ", - "EventCode": "0x11", - "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Occupancy : IPQ : Counts number of entries in the specified Ingress queue in each cycle.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Occupancy : IRQ", - "EventCode": "0x11", - "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Occupancy : IRQ : Counts number of entries in the specified Ingress queue in each cycle.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Occupancy : RRQ", - "EventCode": "0x11", - "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Occupancy : RRQ : Counts number of entries in the specified Ingress queue in each cycle.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Occupancy : WBQ", - "EventCode": "0x11", - "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Occupancy : WBQ : Counts number of entries in the specified Ingress queue in each cycle.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 0 : AD REQ on VN0", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 0 : AD REQ on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a request", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 0 : AD RSP on VN0", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 0 : AD RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a response", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 0 : Non UPI AK Request", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 0 : Non UPI AK Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject AK ring message", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 0 : BL NCB on VN0", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 0 : BL NCB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCB", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 0 : BL NCS on VN0", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 0 : BL NCS on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCS", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 0 : BL RSP on VN0", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 0 : BL RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a response", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 0 : BL WB on VN0", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 0 : BL WB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a writeback", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 0 : Non UPI IV Request", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 0 : Non UPI IV Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject IV ring message", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 1 : Allow Snoop", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 1 : Allow Snoop : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 1 : ANY0", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 1 : ANY0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Any condition listed in the Other0 Reject counter was true", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 1 : HA", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 1 : HA : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 1 : LLC OR SF Way", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 1 : LLC OR SF Way : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Way conflict with another request that caused the reject", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 1 : LLC Victim", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 1 : LLC Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 1 : PhyAddr Match", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 1 : PhyAddr Match : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Address match with an outstanding request that was rejected.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 1 : SF Victim", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 1 : SF Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Requests did not generate Snoop filter victim", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 1 : Victim", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 1 : Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0", - "PerPkg": "1", - "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the PRQ0 Reject counter was true", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC Victim", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Victim", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 0 : AD REQ on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a request", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 0 : AD RSP on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a response", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Request", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 0 : Non UPI AK Request : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject AK ring message", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 0 : BL NCB on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCB", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 0 : BL NCS on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCS", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 0 : BL RSP on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a response", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 0 : BL WB on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a writeback", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Request", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 0 : Non UPI IV Request : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject IV ring message", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 1 : Allow Snoop : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 1 : ANY0", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 1 : ANY0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Any condition listed in the WBQ0 Reject counter was true", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 1 : HA", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 1 : HA : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 1 : LLC OR SF Way : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Way conflict with another request that caused the reject", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 1 : LLC Victim", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 1 : LLC Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 1 : PhyAddr Match : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Address match with an outstanding request that was rejected.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 1 : SF Victim", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 1 : SF Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Requests did not generate Snoop filter victim", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 1 : Victim", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 1 : Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects - Set 0 : AD REQ on VN0", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "RRQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No AD VN0 credit for generating a request", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects - Set 0 : AD RSP on VN0", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "RRQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No AD VN0 credit for generating a response", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects - Set 0 : Non UPI AK Request", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "RRQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Can't inject AK ring message", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects - Set 0 : BL NCB on VN0", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "RRQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for NCB", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects - Set 0 : BL NCS on VN0", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "RRQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for NCS", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects - Set 0 : BL RSP on VN0", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "RRQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for generating a response", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects - Set 0 : BL WB on VN0", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "RRQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : No BL VN0 credit for generating a writeback", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects - Set 0 : Non UPI IV Request", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "RRQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Can't inject IV ring message", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects - Set 1 : Allow Snoop", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "PublicDescription": "RRQ Rejects - Set 1 : Allow Snoop : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects - Set 1 : ANY0", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0", - "PerPkg": "1", - "PublicDescription": "RRQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Any condition listed in the RRQ0 Reject counter was true", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects - Set 1 : HA", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA", - "PerPkg": "1", - "PublicDescription": "RRQ Rejects - Set 1 : HA : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects - Set 1 : LLC OR SF Way", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "PublicDescription": "RRQ Rejects - Set 1 : LLC OR SF Way : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Way conflict with another request that caused the reject", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects - Set 1 : LLC Victim", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "PublicDescription": "RRQ Rejects - Set 1 : LLC Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects - Set 1 : PhyAddr Match", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "PublicDescription": "RRQ Rejects - Set 1 : PhyAddr Match : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Address match with an outstanding request that was rejected.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects - Set 1 : SF Victim", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "PublicDescription": "RRQ Rejects - Set 1 : SF Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry. : Requests did not generate Snoop filter victim", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects - Set 1 : Victim", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM", - "PerPkg": "1", - "PublicDescription": "RRQ Rejects - Set 1 : Victim : Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects - Set 0 : AD REQ on VN0", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "WBQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No AD VN0 credit for generating a request", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects - Set 0 : AD RSP on VN0", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "WBQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No AD VN0 credit for generating a response", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects - Set 0 : Non UPI AK Request", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "WBQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Can't inject AK ring message", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects - Set 0 : BL NCB on VN0", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "WBQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for NCB", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects - Set 0 : BL NCS on VN0", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "WBQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for NCS", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects - Set 0 : BL RSP on VN0", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "WBQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for generating a response", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects - Set 0 : BL WB on VN0", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "WBQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : No BL VN0 credit for generating a writeback", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects - Set 0 : Non UPI IV Request", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "WBQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Can't inject IV ring message", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects - Set 1 : Allow Snoop", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "PublicDescription": "WBQ Rejects - Set 1 : Allow Snoop : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects - Set 1 : ANY0", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0", - "PerPkg": "1", - "PublicDescription": "WBQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Any condition listed in the WBQ0 Reject counter was true", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects - Set 1 : HA", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA", - "PerPkg": "1", - "PublicDescription": "WBQ Rejects - Set 1 : HA : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects - Set 1 : LLC OR SF Way", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "PublicDescription": "WBQ Rejects - Set 1 : LLC OR SF Way : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Way conflict with another request that caused the reject", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects - Set 1 : LLC Victim", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "PublicDescription": "WBQ Rejects - Set 1 : LLC Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects - Set 1 : PhyAddr Match", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "PublicDescription": "WBQ Rejects - Set 1 : PhyAddr Match : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Address match with an outstanding request that was rejected.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects - Set 1 : SF Victim", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "PublicDescription": "WBQ Rejects - Set 1 : SF Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry. : Requests did not generate Snoop filter victim", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects - Set 1 : Victim", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM", - "PerPkg": "1", - "PublicDescription": "WBQ Rejects - Set 1 : Victim : Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - All", - "EventCode": "0xE5", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Credited", - "EventCode": "0xE5", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", - "EventCode": "0xE5", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - All", - "EventCode": "0xE5", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Credited", - "EventCode": "0xE5", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", - "EventCode": "0xE5", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AD - All", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AD - Credited", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AK", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass : BL - All", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass : BL - Credited", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass : IV", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - All", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Credited", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : AK", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - All", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Credited", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : IFV - Credited", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : IV", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation", - "EventCode": "0xe4", - "EventName": "UNC_CHA_RxR_CRD_STARVED_1", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AD - All", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AD - Credited", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AK", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations : BL - All", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations : BL - Credited", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations : IV", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AD - All", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AK", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : BL - All", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : IV", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop filter capacity evictions for E-state entries.", - "EventCode": "0x3D", - "EventName": "UNC_CHA_SF_EVICTION.E_STATE", - "PerPkg": "1", - "PublicDescription": "Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop filter capacity evictions for M-state entries.", - "EventCode": "0x3D", - "EventName": "UNC_CHA_SF_EVICTION.M_STATE", - "PerPkg": "1", - "PublicDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop filter capacity evictions for S-state entries.", - "EventCode": "0x3D", - "EventName": "UNC_CHA_SF_EVICTION.S_STATE", - "PerPkg": "1", - "PublicDescription": "Counts snoop filter capacity evictions for entries tracking shared lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent : All", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.ALL", - "PerPkg": "1", - "PublicDescription": "Snoops Sent : All : Counts the number of snoops issued by the HA.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent : Broadcast snoops for Local Requests", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL", - "PerPkg": "1", - "PublicDescription": "Snoops Sent : Broadcast snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA responding to local requests", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent : Broadcast snoops for Remote Requests", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE", - "PerPkg": "1", - "PublicDescription": "Snoops Sent : Broadcast snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA responding to remote requests", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent : Directed snoops for Local Requests", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", - "PerPkg": "1", - "PublicDescription": "Snoops Sent : Directed snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA responding to local requests", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent : Directed snoops for Remote Requests", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", - "PerPkg": "1", - "PublicDescription": "Snoops Sent : Directed snoops for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA responding to remote requests", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent : Snoops sent for Local Requests", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL", - "PerPkg": "1", - "PublicDescription": "Snoops Sent : Snoops sent for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA responding to local requests", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent : Snoops sent for Remote Requests", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE", - "PerPkg": "1", - "PublicDescription": "Snoops Sent : Snoops sent for Remote Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA responding to remote requests", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received : RSPCNFLCT*", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCT", - "PerPkg": "1", - "PublicDescription": "Snoop Responses Received : RSPCNFLCT* : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for snoops responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received : RspFwd", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD", - "PerPkg": "1", - "PublicDescription": "Snoop Responses Received : RspFwd : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of RspFwd to a CA request. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received : Rsp*Fwd*WB", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPFWDWB", - "PerPkg": "1", - "PublicDescription": "Snoop Responses Received : Rsp*Fwd*WB : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received : RspI", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPI", - "PerPkg": "1", - "PublicDescription": "Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data).", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received : RspIFwd", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD", - "PerPkg": "1", - "PublicDescription": "Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received : RspS", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPS", - "PerPkg": "1", - "PublicDescription": "Counts when a transaction with the opcode type RspS Snoop Response was received which indicates when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received : RspSFwd", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD", - "PerPkg": "1", - "PublicDescription": "Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received : Rsp*WB", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPWB", - "PerPkg": "1", - "PublicDescription": "Snoop Responses Received : Rsp*WB : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for a snoop response of RspIWB or RspSWB. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local : RspCnflct", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", - "PerPkg": "1", - "PublicDescription": "Snoop Responses Received Local : RspCnflct : Number of snoop responses received for a Local request : Filters for snoops responses of RspConflict to local CA requests. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local : RspFwd", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", - "PerPkg": "1", - "PublicDescription": "Snoop Responses Received Local : RspFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspFwd to local CA requests. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB", - "PerPkg": "1", - "PublicDescription": "Snoop Responses Received Local : Rsp*FWD*WB : Number of snoop responses received for a Local request : Filters for a snoop response of Rsp*Fwd*WB to local CA requests. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local : RspI", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI", - "PerPkg": "1", - "PublicDescription": "Snoop Responses Received Local : RspI : Number of snoop responses received for a Local request : Filters for snoops responses of RspI to local CA requests. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local : RspIFwd", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", - "PerPkg": "1", - "PublicDescription": "Snoop Responses Received Local : RspIFwd : Number of snoop responses received for a Local request : Filters for snoop responses of RspIFwd to local CA requests. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local : RspS", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS", - "PerPkg": "1", - "PublicDescription": "Snoop Responses Received Local : RspS : Number of snoop responses received for a Local request : Filters for snoop responses of RspS to local CA requests. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local : RspSFwd", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", - "PerPkg": "1", - "PublicDescription": "Snoop Responses Received Local : RspSFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspSFwd to local CA requests. This is returned when a remote caching agent forwards data but holds on to its currently copy. This is common for data and code reads that hit in a remote socket in E or F state.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local : Rsp*WB", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB", - "PerPkg": "1", - "PublicDescription": "Snoop Responses Received Local : Rsp*WB : Number of snoop responses received for a Local request : Filters for a snoop response of RspIWB or RspSWB to local CA requests. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Misc Snoop Responses Received : MtoI RspIDataM", - "EventCode": "0x6B", - "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM", - "EventCode": "0x6B", - "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit LLC", - "EventCode": "0x6B", - "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit SF", - "EventCode": "0x6B", - "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit LLC", - "EventCode": "0x6B", - "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit SF", - "EventCode": "0x6B", - "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10", - "EventCode": "0xD1", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8", - "EventCode": "0xD1", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9", - "EventCode": "0xD1", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10", - "EventCode": "0xD3", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8", - "EventCode": "0xD3", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9", - "EventCode": "0xD3", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10", - "EventCode": "0xD5", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8", - "EventCode": "0xD5", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9", - "EventCode": "0xD5", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10", - "EventCode": "0xD7", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8", - "EventCode": "0xD7", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9", - "EventCode": "0xD7", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.ALL", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001ffff", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DDR4 Access", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.DDR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DDR4 Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.DDR", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.DDR4", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : SF/LLC Evictions", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.EVICT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : SF/LLC Evictions : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Just Hits", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.HIT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Just Hits : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All requests from iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : CLFlushes issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8c7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CLFlushOpts issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : CLFlushOpts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8d7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CRDs issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : CRDs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc80fff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; CRd Pref from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter", - "UMask": "0xc88fff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRds issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc817ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc837ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc827ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8a7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc897ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc80ffd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc88ffd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc817fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to page walks that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc837fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc827fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8a7fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc897fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores that Hit LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc47fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcccffd01", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCRD", - "PerPkg": "1", - "UMask": "0xcccffd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xccd7fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDRD", - "PerPkg": "1", - "UMask": "0xccd7fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xccc7fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc807fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc887fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores that hit in the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_SPECITOM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc57fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc47ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMCacheNears issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcd47ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcccfff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xccd7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xccc7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc80ffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc80efe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc88ffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc88efe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc88f7e01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc80f7e01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc817fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc837fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8178601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc816fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8168601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8168a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc827fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8a7fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8178a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc897fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8978601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; DRd Pref misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read prefetch from local IA that misses in the snoop filter", - "UMask": "0xc896fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8968601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8968a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8978a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; DRd Pref misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read prefetch from remote IA that misses in the snoop filter", - "UMask": "0xc8977e01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8970601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8970a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8177e01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8170601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8170a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; WCiLF misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", - "UMask": "0xc867fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; WCiLF misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", - "UMask": "0xc8678601", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_DRAM", - "PerPkg": "1", - "UMask": "0xc8678601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; WCiLF misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", - "UMask": "0xc8668601", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_DRAM", - "PerPkg": "1", - "UMask": "0xc8668601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; WCiLF misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", - "UMask": "0xc8668a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; WCiLF misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", - "UMask": "0xc8678a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; WCiLF misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", - "UMask": "0xc8670601", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_DRAM", - "PerPkg": "1", - "UMask": "0xc8670601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; WCiLF misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", - "UMask": "0xc8670a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc47fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcccffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xccd7fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xccc7fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8668601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8668a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86e8601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86e8a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; WCiL misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", - "UMask": "0xc86ffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; WCiL misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", - "UMask": "0xc86f8601", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_DRAM", - "PerPkg": "1", - "UMask": "0xc86f8601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; WCiL misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", - "UMask": "0xc86e8601", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DRAM", - "PerPkg": "1", - "UMask": "0xc86e8601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; WCiL misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", - "UMask": "0xc86e8a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; WCiL misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", - "UMask": "0xc86f8a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; WCiL misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", - "UMask": "0xc86f0601", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DRAM", - "PerPkg": "1", - "UMask": "0xc86f0601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; WCiL misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", - "UMask": "0xc86f0a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8670601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remote memory", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8670a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86f0601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86f0a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc807fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc806fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc887fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc886fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8877e01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8077e01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_SPECITOM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc57fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc877de01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86ffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc867fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8678601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targeting PMM that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8678a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86f8601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targeting PMM that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86f8a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc87fde01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFOs issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFOs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc807ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc887ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc57ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE", - "PerPkg": "1", - "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc3fff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WBEFtoIs issued by an IA Core. Non Modified Write Backs", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI", - "PerPkg": "1", - "PublicDescription": "WbEFtoIs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc37ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WBMtoEs issued by an IA Core. Non Modified Write Backs", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE", - "PerPkg": "1", - "PublicDescription": "WbMtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc2fff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI", - "PerPkg": "1", - "PublicDescription": "WbMtoIs issued by iA Cores . (Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc27ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WBStoIs issued by an IA Core. Non Modified Write Backs", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI", - "PerPkg": "1", - "PublicDescription": "WbStoIs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc67ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86fff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc867ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All requests from IO Devices", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : CLFlushes issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8c3ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All requests from IO Devices that hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc43fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcd43fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8f3fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc803fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc43ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcd43ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to locally HOMed memory", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcd42ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to remotely HOMed memory", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcd437f04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to locally HOMed memory", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc42ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to remotely HOMed memory", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc437f04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All requests from IO Devices that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc43fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcd43fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8f3fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc803fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8f3ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFOs issued by IO Devices", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc803ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WbMtoIs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc23ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : IPQ", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IPQ", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : IPQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : IRQ - iA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : IRQ - iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From an iA Core", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : IRQ - Non iA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : IRQ - Non iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Just ISOC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.ISOC", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Just ISOC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Just Local Targets", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Just Local Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All from Local iA and IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All from Local iA and IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests", - "UMask": "0xc000ff05", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All from Local iA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All from Local iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores", - "UMask": "0xc000ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All from Local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All from Local IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic", - "UMask": "0xc000ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Just Misses", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.MISS", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Just Misses : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : MMCFG Access", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.MMCFG", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : MMCFG Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Just NearMem", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.NEARMEM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Just NearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Just NonCoherent", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.NONCOH", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Just NonCoherent : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Just NotNearMem", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Just NotNearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : PMM Access", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.PMM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : PMM Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : PRQ - IOSF", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : PRQ - IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From a PCIe Device", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : PRQ - Non IOSF", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : PRQ - Non IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Just Remote Targets", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.REMOTE_TGT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Just Remote Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RRQ", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.RRQ", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RRQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WBQ", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.WBQ", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WBQ : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DDR4 Access", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DDR4 Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : SF/LLC Evictions", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : SF/LLC Evictions : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Just Hits", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Just Hits : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All requests from iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8c7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8d7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CRDs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc80fff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; CRd Pref from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter", - "UMask": "0xc88fff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRds issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc817ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc837ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc827ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8a7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc897ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc80ffd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc88ffd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc817fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc837fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc827fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8a7fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc897fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Hit LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc47fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcccffd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xccd7fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xccc7fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc807fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc887fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc47ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMCacheNears issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcd47ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcccfff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xccd7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xccc7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc80ffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc80efe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc88ffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc88efe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc88f7e01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc80f7e01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc817fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc837fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8178601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc816fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8168601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8168a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc827fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8a7fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8178a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc897fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8978601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter", - "UMask": "0xc896fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8968601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8968a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8978a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter", - "UMask": "0xc8977e01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8970601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8970a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8177e01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8170601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8170a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", - "UMask": "0xc867fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", - "UMask": "0xc8678601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_LOCAL_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", - "UMask": "0xc8668601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_LOCAL_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", - "UMask": "0xc8668a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", - "UMask": "0xc8678a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_REMOTE_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", - "UMask": "0xc8670601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_REMOTE_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", - "UMask": "0xc8670a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc47fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcccffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xccd7fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xccc7fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8668601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8668a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86e8601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86e8a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; WCiL misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", - "UMask": "0xc86ffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; WCiL misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", - "UMask": "0xc86f8601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; WCiL misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", - "UMask": "0xc86e8601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; WCiL misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_LOCAL_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", - "UMask": "0xc86e8a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; WCiL misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", - "UMask": "0xc86f8a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; WCiL misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", - "UMask": "0xc86f0601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; WCiL misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_REMOTE_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", - "UMask": "0xc86f0a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8670601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8670a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86f0601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86f0a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc807fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc806fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc887fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc886fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8877e01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8077e01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_SPECITOM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores that missed the LLC: For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc57fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc877de01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86ffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc867fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8678601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8678a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86f8601", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores targeting PMM that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86f8a01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc87fde01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc807ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc887ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc57ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc27ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86fff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc867ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All requests from IO Devices", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Devices", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8c3ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc43fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcd43fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8f3fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc803fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc43ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcd43ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc43fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcd43fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8f3fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc803fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8f3ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc803ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc23ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : IPQ", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : IPQ : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : IRQ - iA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : IRQ - iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From an iA Core", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : IRQ - Non iA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : IRQ - Non iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Just ISOC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Just ISOC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Just Local Targets", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Just Local Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All from Local iA and IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All from Local iA and IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests", - "UMask": "0xc000ff05", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All from Local iA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All from Local iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores", - "UMask": "0xc000ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All from Local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All from Local IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic", - "UMask": "0xc000ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Just Misses", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Just Misses : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : MMCFG Access", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : MMCFG Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Just NearMem", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Just NearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Just NonCoherent", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Just NonCoherent : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Just NotNearMem", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Just NotNearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : PMM Access", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.PMM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : PMM Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : PRQ - IOSF", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : PRQ - IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From a PCIe Device", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : PRQ - Non IOSF", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : PRQ - Non IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Just Remote Targets", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.REMOTE_TGT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Just Remote Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : AD - All", - "EventCode": "0xA6", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", - "EventCode": "0xA6", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", - "EventCode": "0xA6", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : BL - All", - "EventCode": "0xA6", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", - "EventCode": "0xA6", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", - "EventCode": "0xA6", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AD - All", - "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", - "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", - "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AK", - "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited", - "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : BL - All", - "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", - "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", - "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : IV", - "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All", - "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited", - "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited", - "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK", - "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited", - "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All", - "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited", - "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited", - "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV", - "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All", - "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited", - "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited", - "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK", - "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited", - "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All", - "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited", - "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited", - "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV", - "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", - "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited", - "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited", - "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AK", - "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited", - "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", - "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited", - "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited", - "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : IV", - "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", - "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", - "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited", - "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AK", - "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited", - "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", - "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", - "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited", - "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : IV", - "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", - "EventCode": "0xA0", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited", - "EventCode": "0xA0", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited", - "EventCode": "0xA0", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AK", - "EventCode": "0xA0", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited", - "EventCode": "0xA0", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", - "EventCode": "0xA0", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited", - "EventCode": "0xA0", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited", - "EventCode": "0xA0", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : IV", - "EventCode": "0xA0", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All", - "EventCode": "0xA5", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited", - "EventCode": "0xA5", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK", - "EventCode": "0xA5", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited", - "EventCode": "0xA5", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All", - "EventCode": "0xA5", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited", - "EventCode": "0xA5", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV", - "EventCode": "0xA5", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0", - "EventCode": "0x95", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1", - "EventCode": "0x95", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0", - "EventCode": "0x97", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1", - "EventCode": "0x97", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_INSERTS0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : IV", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", - "EventCode": "0x99", - "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", - "EventCode": "0x99", - "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : IV", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", - "EventCode": "0x9B", - "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1", - "EventCode": "0x9B", - "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", - "EventCode": "0x9B", - "EventName": "UNC_CHA_TxR_VERT_STARVED1.TGC", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Down and Even", - "EventCode": "0xB0", - "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Down and Odd", - "EventCode": "0xB0", - "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Up and Even", - "EventCode": "0xB0", - "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Up and Odd", - "EventCode": "0xB0", - "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Down and Even", - "EventCode": "0xB4", - "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", - "EventCode": "0xB4", - "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Up and Even", - "EventCode": "0xB4", - "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", - "EventCode": "0xB4", - "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Down and Even", - "EventCode": "0xB1", - "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Down and Odd", - "EventCode": "0xB1", - "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Up and Even", - "EventCode": "0xB1", - "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Up and Odd", - "EventCode": "0xB1", - "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Down and Even", - "EventCode": "0xB2", - "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Down and Odd", - "EventCode": "0xB2", - "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Up and Even", - "EventCode": "0xB2", - "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Up and Odd", - "EventCode": "0xB2", - "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical IV Ring in Use : Down", - "EventCode": "0xB3", - "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN", - "PerPkg": "1", - "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical IV Ring in Use : Up", - "EventCode": "0xB3", - "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP", - "PerPkg": "1", - "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Down and Even", - "EventCode": "0xB5", - "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", - "EventCode": "0xB5", - "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Up and Even", - "EventCode": "0xB5", - "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", - "EventCode": "0xB5", - "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "WbPushMtoI : Pushed to LLC", - "EventCode": "0x56", - "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC", - "PerPkg": "1", - "PublicDescription": "WbPushMtoI : Pushed to LLC : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was able to push WbPushMToI to LLC", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "WbPushMtoI : Pushed to Memory", - "EventCode": "0x56", - "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM", - "PerPkg": "1", - "PublicDescription": "WbPushMtoI : Pushed to Memory : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC0 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 0 only.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC1 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 1 only.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC10", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC10", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC10 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 10 only.", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC11", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC11", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC11 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 11 only.", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC12", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC12", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC12 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 12 only.", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC13", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC13", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC13 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 13 only.", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC2 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 2 only.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC3 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 3 only.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC4 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 4 only.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC5 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 5 only.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC6", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC6", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC6 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 6 only.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC7", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC7", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC7 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 7 only.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC8", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC8", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC8 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 8 only.", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC9", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC9", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC9 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 9 only.", - "Unit": "CHA" - }, - { - "BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict", - "EventCode": "0x6f", - "EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT", - "PerPkg": "1", - "PublicDescription": "XPT Prefetches : Dropped (on 0?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits", - "EventCode": "0x6f", - "EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD", - "PerPkg": "1", - "PublicDescription": "XPT Prefetches : Dropped (on 0?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict", - "EventCode": "0x6f", - "EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT", - "PerPkg": "1", - "PublicDescription": "XPT Prefetches : Dropped (on 1?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits", - "EventCode": "0x6f", - "EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD", - "PerPkg": "1", - "PublicDescription": "XPT Prefetches : Dropped (on 1?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "XPT Prefetches : Sent (on 0?)", - "EventCode": "0x6f", - "EventName": "UNC_CHA_XPT_PREF.SENT0", - "PerPkg": "1", - "PublicDescription": "XPT Prefetches : Sent (on 0?) : Number of XPT prefetches sent", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "XPT Prefetches : Sent (on 1?)", - "EventCode": "0x6f", - "EventName": "UNC_CHA_XPT_PREF.SENT1", - "PerPkg": "1", - "PublicDescription": "XPT Prefetches : Sent (on 1?) : Number of XPT prefetches sent", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventCode": "0xff", - "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "iio_free_running" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventCode": "0xff", - "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN", - "PerPkg": "1", - "UMask": "0x21", - "Unit": "iio_free_running" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventCode": "0xff", - "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN", - "PerPkg": "1", - "UMask": "0x22", - "Unit": "iio_free_running" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventCode": "0xff", - "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN", - "PerPkg": "1", - "UMask": "0x23", - "Unit": "iio_free_running" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventCode": "0xff", - "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN", - "PerPkg": "1", - "UMask": "0x24", - "Unit": "iio_free_running" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventCode": "0xff", - "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN", - "PerPkg": "1", - "UMask": "0x25", - "Unit": "iio_free_running" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventCode": "0xff", - "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN", - "PerPkg": "1", - "UMask": "0x26", - "Unit": "iio_free_running" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventCode": "0xff", - "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN", - "PerPkg": "1", - "UMask": "0x27", - "Unit": "iio_free_running" - }, - { - "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller", - "EventCode": "0x01", - "EventName": "UNC_IIO_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Clockticks of the integrated IO (IIO) traffic controller : Increments counter once every Traffic Controller clock, the LSCLK (500MHz)", - "Unit": "IIO" - }, - { - "BriefDescription": "Free running counter that increments for IIO clocktick", - "EventCode": "0xff", - "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", - "PerPkg": "1", - "PublicDescription": "Free running counter that increments for integrated IO (IIO) traffic controller clockticks", - "UMask": "0x10", - "Unit": "iio_free_running" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts : All Ports", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL", - "FCMask": "0x04", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", - "FCMask": "0x04", - "PerPkg": "1", - "PortMask": "0xff", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", - "FCMask": "0x04", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", - "FCMask": "0x04", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", - "FCMask": "0x04", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", - "FCMask": "0x04", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4", - "FCMask": "0x04", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5", - "FCMask": "0x04", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6", - "FCMask": "0x04", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7", - "FCMask": "0x04", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL", - "FCMask": "0x04", - "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7", - "UMask": "0xff", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", - "FCMask": "0x04", - "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7", - "UMask": "0xff", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", - "FCMask": "0x04", - "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 1", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", - "FCMask": "0x04", - "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer Occupancy : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 2", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", - "FCMask": "0x04", - "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer Occupancy : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 3", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", - "FCMask": "0x04", - "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer Occupancy : Part 3 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 4", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", - "FCMask": "0x04", - "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer Occupancy : Part 4 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 5", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", - "FCMask": "0x04", - "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer Occupancy : Part 5 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 6", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", - "FCMask": "0x04", - "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer Occupancy : Part 6 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 7", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", - "FCMask": "0x04", - "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer Occupancy : Part 7 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Incoming arbitration requests : Passing data to be written", - "EventCode": "0x86", - "EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Incoming arbitration requests : Passing data to be written : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Incoming arbitration requests : Issuing final read or write of line", - "EventCode": "0x86", - "EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Incoming arbitration requests : Issuing final read or write of line : How often different queues (e.g. channel / fc) ask to send request into pipeline", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Incoming arbitration requests : Processing response from IOMMU", - "EventCode": "0x86", - "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Incoming arbitration requests : Processing response from IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Incoming arbitration requests : Issuing to IOMMU", - "EventCode": "0x86", - "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Incoming arbitration requests : Issuing to IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Incoming arbitration requests : Request Ownership", - "EventCode": "0x86", - "EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Incoming arbitration requests : Request Ownership : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Incoming arbitration requests : Writing line", - "EventCode": "0x86", - "EventName": "UNC_IIO_INBOUND_ARB_REQ.WR", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Incoming arbitration requests : Writing line : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Incoming arbitration requests granted : Passing data to be written", - "EventCode": "0x87", - "EventName": "UNC_IIO_INBOUND_ARB_WON.DATA", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Incoming arbitration requests granted : Passing data to be written : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Incoming arbitration requests granted : Issuing final read or write of line", - "EventCode": "0x87", - "EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Incoming arbitration requests granted : Issuing final read or write of line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Incoming arbitration requests granted : Processing response from IOMMU", - "EventCode": "0x87", - "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Incoming arbitration requests granted : Processing response from IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Incoming arbitration requests granted : Issuing to IOMMU", - "EventCode": "0x87", - "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Incoming arbitration requests granted : Issuing to IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Incoming arbitration requests granted : Request Ownership", - "EventCode": "0x87", - "EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Incoming arbitration requests granted : Request Ownership : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Incoming arbitration requests granted : Writing line", - "EventCode": "0x87", - "EventName": "UNC_IIO_INBOUND_ARB_WON.WR", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Incoming arbitration requests granted : Writing line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": ": IOTLB Hits to a 1G Page", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.1G_HITS", - "PerPkg": "1", - "PublicDescription": ": IOTLB Hits to a 1G Page : Counts if a transaction to a 1G page, on its first lookup, hits the IOTLB.", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": ": IOTLB Hits to a 2M Page", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.2M_HITS", - "PerPkg": "1", - "PublicDescription": ": IOTLB Hits to a 2M Page : Counts if a transaction to a 2M page, on its first lookup, hits the IOTLB.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": ": IOTLB Hits to a 4K Page", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.4K_HITS", - "PerPkg": "1", - "PublicDescription": ": IOTLB Hits to a 4K Page : Counts if a transaction to a 4K page, on its first lookup, hits the IOTLB.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": ": IOTLB lookups all", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS", - "PerPkg": "1", - "PublicDescription": ": IOTLB lookups all : Some transactions have to look up IOTLB multiple times. Counts every time a request looks up IOTLB.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": ": Context cache hits", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS", - "PerPkg": "1", - "PublicDescription": ": Context cache hits : Counts each time a first look up of the transaction hits the RCC.", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": ": Context cache lookups", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS", - "PerPkg": "1", - "PublicDescription": ": Context cache lookups : Counts each time a transaction looks up root context cache.", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": ": IOTLB lookups first", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS", - "PerPkg": "1", - "PublicDescription": ": IOTLB lookups first : Some transactions have to look up IOTLB multiple times. Counts the first time a request looks up IOTLB.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": ": IOTLB Fills (same as IOTLB miss)", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.MISSES", - "PerPkg": "1", - "PublicDescription": ": IOTLB Fills (same as IOTLB miss) : When a transaction misses IOTLB, it does a page walk to look up memory and bring in the relevant page translation. Counts when this page translation is written to IOTLB.", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": ": Cycles PWT full", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.CYC_PWT_FULL", - "PerPkg": "1", - "PublicDescription": ": Cycles PWT full : Counts cycles the IOMMU has reached its maximum limit for outstanding page walks.", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": ": IOMMU memory access", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES", - "PerPkg": "1", - "PublicDescription": ": IOMMU memory access : IOMMU sends out memory fetches when it misses the cache look up which is indicated by this signal. M2IOSF only uses low priority channel", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": ": PWC Hit to a 1G page", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS", - "PerPkg": "1", - "PublicDescription": ": PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": ": PWC Hit to a 2M page", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS", - "PerPkg": "1", - "PublicDescription": ": PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": ": PWC Hit to a 4K page", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.PWC_4K_HITS", - "PerPkg": "1", - "PublicDescription": ": PWC Hit to a 4K page : Counts each time a transaction's first look up hits the SLPWC at the 4K level", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": ": PWT Hit to a 256T page", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS", - "PerPkg": "1", - "PublicDescription": ": PWT Hit to a 256T page : Counts each time a transaction's first look up hits the SLPWC at the 512G level", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": ": PageWalk cache fill", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS", - "PerPkg": "1", - "PublicDescription": ": PageWalk cache fill : When a transaction misses SLPWC, it does a page walk to look up memory and bring in the relevant page translation. When this page translation is written to SLPWC, ObsPwcFillValid_nnnH is asserted.", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": ": PageWalk cache lookup", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS", - "PerPkg": "1", - "PublicDescription": ": PageWalk cache lookup : Counts each time a transaction looks up second level page walk cache.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": ": Interrupt Entry cache hit", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS", - "PerPkg": "1", - "PublicDescription": ": Interrupt Entry cache hit : Counts each time a transaction's first look up hits the IEC.", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": ": Interrupt Entry cache lookup", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS", - "PerPkg": "1", - "PublicDescription": ": Interrupt Entry cache lookup : Counts the number of transaction looks up that interrupt remapping cache.", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": ": Device-selective Context cache invalidation cycles", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DEVICE", - "PerPkg": "1", - "PublicDescription": ": Device-selective Context cache invalidation cycles : Counts number of Device selective context cache invalidation events", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": ": Domain-selective Context cache invalidation cycles", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DOMAIN", - "PerPkg": "1", - "PublicDescription": ": Domain-selective Context cache invalidation cycles : Counts number of Domain selective context cache invalidation events", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": ": Context cache global invalidation cycles", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_GBL", - "PerPkg": "1", - "PublicDescription": ": Context cache global invalidation cycles : Counts number of Context Cache global invalidation events", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": ": Domain-selective IOTLB invalidation cycles", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_DOMAIN", - "PerPkg": "1", - "PublicDescription": ": Domain-selective IOTLB invalidation cycles : Counts number of Domain selective invalidation events", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": ": Global IOTLB invalidation cycles", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_GBL", - "PerPkg": "1", - "PublicDescription": ": Global IOTLB invalidation cycles : Indicates that IOMMU is doing global invalidation.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": ": Page-selective IOTLB invalidation cycles", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PAGE", - "PerPkg": "1", - "PublicDescription": ": Page-selective IOTLB invalidation cycles : Counts number of Page-selective within Domain Invalidation events", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus", - "EventCode": "0x02", - "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0", - "PerPkg": "1", - "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus : Asserted if all bits specified by mask match", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus", - "EventCode": "0x02", - "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1", - "PerPkg": "1", - "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if all bits specified by mask match", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)", - "EventCode": "0x02", - "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1", - "PerPkg": "1", - "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if all bits specified by mask match", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "AND Mask/match for debug bus : PCIE bus", - "EventCode": "0x02", - "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1", - "PerPkg": "1", - "PublicDescription": "AND Mask/match for debug bus : PCIE bus : Asserted if all bits specified by mask match", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus", - "EventCode": "0x02", - "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1", - "PerPkg": "1", - "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if all bits specified by mask match", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)", - "EventCode": "0x02", - "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1", - "PerPkg": "1", - "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if all bits specified by mask match", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus", - "EventCode": "0x03", - "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0", - "PerPkg": "1", - "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus : Asserted if any bits specified by mask match", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus", - "EventCode": "0x03", - "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1", - "PerPkg": "1", - "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if any bits specified by mask match", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)", - "EventCode": "0x03", - "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1", - "PerPkg": "1", - "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if any bits specified by mask match", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "OR Mask/match for debug bus : PCIE bus", - "EventCode": "0x03", - "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1", - "PerPkg": "1", - "PublicDescription": "OR Mask/match for debug bus : PCIE bus : Asserted if any bits specified by mask match", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus", - "EventCode": "0x03", - "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1", - "PerPkg": "1", - "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if any bits specified by mask match", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)", - "EventCode": "0x03", - "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1", - "PerPkg": "1", - "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if any bits specified by mask match", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Counting disabled", - "EventCode": "0x80", - "EventName": "UNC_IIO_NOTHING", - "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "Occupancy of outbound request queue : To device", - "EventCode": "0xC5", - "EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Occupancy of outbound request queue : To device : Counts number of outbound requests/completions IIO is currently processing", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": ": Passing data to be written", - "EventCode": "0x88", - "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": ": Passing data to be written : Only for posted requests", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": ": Issuing final read or write of line", - "EventCode": "0x88", - "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": ": Processing response from IOMMU", - "EventCode": "0x88", - "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": ": Issuing to IOMMU", - "EventCode": "0x88", - "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": ": Request Ownership", - "EventCode": "0x88", - "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": ": Request Ownership : Only for posted requests", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": ": Writing line", - "EventCode": "0x88", - "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": ": Writing line : Only for posted requests", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number requests sent to PCIe from main die : From IRP", - "EventCode": "0xC2", - "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.IRP", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Number requests sent to PCIe from main die : From IRP : Captures Posted/Non-posted allocations from IRP. i.e. either non-confined P2P traffic or from the CPU", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number requests sent to PCIe from main die : From ITC", - "EventCode": "0xC2", - "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.ITC", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Number requests sent to PCIe from main die : From ITC : Confined P2P", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number requests sent to PCIe from main die : Completion allocations", - "EventCode": "0xc2", - "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.PREALLOC", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number requests PCIe makes of the main die : Drop request", - "EventCode": "0x85", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU.ALL.DROP", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Number requests PCIe makes of the main die : Drop request : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU. : Packet error detected, must be dropped", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number requests PCIe makes of the main die : All", - "EventCode": "0x85", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Num requests sent by PCIe - by target : Abort", - "EventCode": "0x8E", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Num requests sent by PCIe - by target : Confined P2P", - "EventCode": "0x8E", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Num requests sent by PCIe - by target : Local P2P", - "EventCode": "0x8E", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Num requests sent by PCIe - by target : Multi-cast", - "EventCode": "0x8E", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Num requests sent by PCIe - by target : Memory", - "EventCode": "0x8E", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Num requests sent by PCIe - by target : MsgB", - "EventCode": "0x8E", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Num requests sent by PCIe - by target : Remote P2P", - "EventCode": "0x8E", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Num requests sent by PCIe - by target : Ubox", - "EventCode": "0x8E", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "ITC address map 1", - "EventCode": "0x8F", - "EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU", - "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "Outbound cacheline requests issued : 64B requests issued to device", - "EventCode": "0xD0", - "EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Outbound cacheline requests issued : 64B requests issued to device : Each outbound cacheline granular request may need to make multiple passes through the pipeline. Each time a cacheline completes all its passes it advances line", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Outbound TLP (transaction layer packet) requests issued : To device", - "EventCode": "0xD1", - "EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Outbound TLP (transaction layer packet) requests issued : To device : Each time an outbound completes all its passes it advances the pointer", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "PWT occupancy", - "EventCode": "0x42", - "EventName": "UNC_IIO_PWT_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "PWT occupancy : Indicates how many page walks are outstanding at any point in time.", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request - cacheline complete : Passing data to be written", - "EventCode": "0x91", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request - cacheline complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request - cacheline complete : Issuing final read or write of line", - "EventCode": "0x91", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request - cacheline complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request - cacheline complete : Request Ownership", - "EventCode": "0x91", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request - cacheline complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request - cacheline complete : Writing line", - "EventCode": "0x91", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request - cacheline complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request complete : Passing data to be written", - "EventCode": "0x92", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.DATA", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request complete : Issuing final read or write of line", - "EventCode": "0x92", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request complete : Processing response from IOMMU", - "EventCode": "0x92", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request complete : Processing response from IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request complete : Issuing to IOMMU", - "EventCode": "0x92", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request complete : Issuing to IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request complete : Request Ownership", - "EventCode": "0x92", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request complete : Writing line", - "EventCode": "0x92", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.WR", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request - pass complete : Passing data to be written", - "EventCode": "0x90", - "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request - pass complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request - pass complete : Issuing final read or write of line", - "EventCode": "0x90", - "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request - pass complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request - pass complete : Request Ownership", - "EventCode": "0x90", - "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request - pass complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request - pass complete : Writing line", - "EventCode": "0x90", - "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request - pass complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Symbol Times on Link", - "EventCode": "0x82", - "EventName": "UNC_IIO_SYMBOL_TIMES", - "PerPkg": "1", - "PublicDescription": "Symbol Times on Link : Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Total Write Cache Occupancy : Any Source", - "EventCode": "0x0F", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", - "PerPkg": "1", - "PublicDescription": "Total Write Cache Occupancy : Any Source : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events. : Tracks all requests from any source port.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Total Write Cache Occupancy : Snoops", - "EventCode": "0x0F", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q", - "PerPkg": "1", - "PublicDescription": "Total Write Cache Occupancy : Snoops : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory.", - "EventCode": "0x0f", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", - "PerPkg": "1", - "PublicDescription": "Total IRP occupancy of inbound read and write requests to coherent memory. This is effectively the sum of read occupancy and write occupancy.", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Clockticks of the IO coherency tracker (IRP)", - "EventCode": "0x01", - "EventName": "UNC_I_CLOCKTICKS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops : CLFlush", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", - "PerPkg": "1", - "PublicDescription": "Coherent Ops : CLFlush : Counts the number of coherency related operations servied by the IRP", - "UMask": "0x80", - "Unit": "IRP" - }, - { - "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.PCITOM", - "PerPkg": "1", - "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.RFO", - "PerPkg": "1", - "PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops : WbMtoI", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.WBMTOI", - "PerPkg": "1", - "PublicDescription": "Coherent Ops : WbMtoI : Counts the number of coherency related operations servied by the IRP", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "FAF RF full", - "EventCode": "0x17", - "EventName": "UNC_I_FAF_FULL", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.", - "EventCode": "0x18", - "EventName": "UNC_I_FAF_INSERTS", - "PerPkg": "1", - "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.", - "Unit": "IRP" - }, - { - "BriefDescription": "Occupancy of the IRP FAF queue.", - "EventCode": "0x19", - "EventName": "UNC_I_FAF_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.", - "Unit": "IRP" - }, - { - "BriefDescription": "FAF allocation -- sent to ADQ", - "EventCode": "0x16", - "EventName": "UNC_I_FAF_TRANSACTIONS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", - "EventCode": "0x20", - "EventName": "UNC_I_IRP_ALL.EVICTS", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)", - "EventCode": "0x20", - "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", - "EventCode": "0x20", - "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary", - "EventCode": "0x1E", - "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary", - "EventCode": "0x1e", - "EventName": "UNC_I_MISC0.2ND_RD_INSERT", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary", - "EventCode": "0x1e", - "EventName": "UNC_I_MISC0.2ND_WR_INSERT", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", - "EventCode": "0x1E", - "EventName": "UNC_I_MISC0.FAST_REJ", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests", - "EventCode": "0x1e", - "EventName": "UNC_I_MISC0.FAST_REQ", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary", - "EventCode": "0x1E", - "EventName": "UNC_I_MISC0.FAST_XFER", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary", - "EventCode": "0x1E", - "EventName": "UNC_I_MISC0.PF_ACK_HINT", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch", - "EventCode": "0x1E", - "EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1 : Lost Forward", - "EventCode": "0x1F", - "EventName": "UNC_I_MISC1.LOST_FWD", - "PerPkg": "1", - "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1 : Received Invalid", - "EventCode": "0x1F", - "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", - "PerPkg": "1", - "PublicDescription": "Misc Events - Set 1 : Received Invalid : Secondary received a transfer that did not have sufficient MESI state", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1 : Received Valid", - "EventCode": "0x1F", - "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", - "PerPkg": "1", - "PublicDescription": "Misc Events - Set 1 : Received Valid : Secondary received a transfer that did have sufficient MESI state", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line", - "EventCode": "0x1f", - "EventName": "UNC_I_MISC1.SLOW_E", - "PerPkg": "1", - "PublicDescription": "Misc Events - Set 1 : Slow Transfer of E Line : Secondary received a transfer that did have sufficient MESI state", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line", - "EventCode": "0x1f", - "EventName": "UNC_I_MISC1.SLOW_I", - "PerPkg": "1", - "PublicDescription": "Misc Events - Set 1 : Slow Transfer of I Line : Snoop took cacheline ownership before write from data was committed.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line", - "EventCode": "0x1f", - "EventName": "UNC_I_MISC1.SLOW_M", - "PerPkg": "1", - "PublicDescription": "Misc Events - Set 1 : Slow Transfer of M Line : Snoop took cacheline ownership before write from data was committed.", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line", - "EventCode": "0x1f", - "EventName": "UNC_I_MISC1.SLOW_S", - "PerPkg": "1", - "PublicDescription": "Misc Events - Set 1 : Slow Transfer of S Line : Secondary received a transfer that did not have sufficient MESI state", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Requests", - "EventCode": "0x14", - "EventName": "UNC_I_P2P_INSERTS", - "PerPkg": "1", - "PublicDescription": "P2P Requests : P2P requests from the ITC", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Occupancy", - "EventCode": "0x15", - "EventName": "UNC_I_P2P_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "P2P Occupancy : P2P B & S Queue Occupancy", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions : P2P completions", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions : match if local only", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.LOC", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions : match if local and target matches", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions : P2P Message", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.MSG", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions : P2P reads", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.RD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions : Match if remote only", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.REM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions : match if remote and target matches", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions : P2P Writes", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.WR", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT", - "PerPkg": "1", - "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO", - "UMask": "0x7e", - "Unit": "IRP" - }, - { - "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES", - "PerPkg": "1", - "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache", - "UMask": "0x74", - "Unit": "IRP" - }, - { - "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I", - "PerPkg": "1", - "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache", - "UMask": "0x72", - "Unit": "IRP" - }, - { - "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", - "PerPkg": "1", - "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache", - "UMask": "0x78", - "Unit": "IRP" - }, - { - "BriefDescription": "Responses to snoops of any type that miss the IIO cache", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_MISS", - "PerPkg": "1", - "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that miss the IIO cache", - "UMask": "0x71", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses : Hit E or S", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.HIT_ES", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses : Hit I", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.HIT_I", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses : Hit M", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.HIT_M", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses : Miss", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.MISS", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses : SnpCode", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.SNPCODE", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses : SnpData", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.SNPDATA", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses : SnpInv", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.SNPINV", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count : Atomic", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.ATOMIC", - "PerPkg": "1", - "PublicDescription": "Inbound Transaction Count : Atomic : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of atomic transactions", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count : Other", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.OTHER", - "PerPkg": "1", - "PublicDescription": "Inbound Transaction Count : Other : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of 'other' kinds of transactions.", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count : Writes", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.WRITES", - "PerPkg": "1", - "PublicDescription": "Inbound Transaction Count : Writes : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound write (fast path) requests received by the IRP.", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.WR_PREF", - "PerPkg": "1", - "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "AK Egress Allocations", - "EventCode": "0x0B", - "EventName": "UNC_I_TxC_AK_INSERTS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL DRS Egress Cycles Full", - "EventCode": "0x05", - "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL DRS Egress Inserts", - "EventCode": "0x02", - "EventName": "UNC_I_TxC_BL_DRS_INSERTS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL DRS Egress Occupancy", - "EventCode": "0x08", - "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL NCB Egress Cycles Full", - "EventCode": "0x06", - "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL NCB Egress Inserts", - "EventCode": "0x03", - "EventName": "UNC_I_TxC_BL_NCB_INSERTS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL NCB Egress Occupancy", - "EventCode": "0x09", - "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL NCS Egress Cycles Full", - "EventCode": "0x07", - "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL NCS Egress Inserts", - "EventCode": "0x04", - "EventName": "UNC_I_TxC_BL_NCS_INSERTS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL NCS Egress Occupancy", - "EventCode": "0x0A", - "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", - "EventCode": "0x1C", - "EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", - "PerPkg": "1", - "PublicDescription": ": Counts the number times when it is not possible to issue a request to the M2PCIe because there are no Egress Credits available on AD0, A1 or AD0&AD1 both. Stalls on both AD0 and AD1 will count as 2", - "Unit": "IRP" - }, - { - "BriefDescription": "No AD0 Egress Credits Stalls", - "EventCode": "0x1A", - "EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES", - "PerPkg": "1", - "PublicDescription": "No AD0 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD0 Egress Credits available.", - "Unit": "IRP" - }, - { - "BriefDescription": "No AD1 Egress Credits Stalls", - "EventCode": "0x1B", - "EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES", - "PerPkg": "1", - "PublicDescription": "No AD1 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD1 Egress Credits available.", - "Unit": "IRP" - }, - { - "BriefDescription": "No BL Egress Credit Stalls", - "EventCode": "0x1D", - "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", - "PerPkg": "1", - "PublicDescription": "No BL Egress Credit Stalls : Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Read Requests", - "EventCode": "0x0D", - "EventName": "UNC_I_TxS_DATA_INSERTS_NCB", - "PerPkg": "1", - "PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Read Requests", - "EventCode": "0x0E", - "EventName": "UNC_I_TxS_DATA_INSERTS_NCS", - "PerPkg": "1", - "PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Request Queue Occupancy", - "EventCode": "0x0C", - "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Outbound Request Queue Occupancy : Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.", - "Unit": "IRP" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10", - "EventCode": "0x81", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8", - "EventCode": "0x81", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9", - "EventCode": "0x81", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10", - "EventCode": "0x83", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8", - "EventCode": "0x83", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9", - "EventCode": "0x83", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10", - "EventCode": "0x89", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8", - "EventCode": "0x89", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9", - "EventCode": "0x89", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10", - "EventCode": "0x8B", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8", - "EventCode": "0x8B", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9", - "EventCode": "0x8B", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10", - "EventCode": "0x85", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8", - "EventCode": "0x85", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9", - "EventCode": "0x85", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10", - "EventCode": "0x87", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8", - "EventCode": "0x87", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9", - "EventCode": "0x87", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10", - "EventCode": "0x8D", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8", - "EventCode": "0x8D", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9", - "EventCode": "0x8D", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10", - "EventCode": "0x8F", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8", - "EventCode": "0x8F", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9", - "EventCode": "0x8F", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC Bypass : Not Taken", - "EventCode": "0x22", - "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.NOT_TAKEN", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC Bypass : Taken", - "EventCode": "0x22", - "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.TAKEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC Bypass : Not Taken", - "EventCode": "0x21", - "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC Bypass : Taken", - "EventCode": "0x21", - "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Clockticks of the mesh to memory (M2M)", - "EventName": "UNC_M2M_CLOCKTICKS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Clockticks", - "EventCode": "0xc0", - "EventName": "UNC_M2M_CMS_CLOCKTICKS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles when direct to core mode, which bypasses the CHA, was disabled", - "EventCode": "0x24", - "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", - "EventCode": "0x60", - "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Number of reads in which direct to core transaction was overridden", - "EventCode": "0x25", - "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Number of reads in which direct to Intel UPI transactions were overridden", - "EventCode": "0x28", - "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles when Direct2UPI was Disabled", - "EventCode": "0x27", - "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Number of reads that a message sent direct2 Intel UPI was overridden", - "EventCode": "0x29", - "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE", - "PerPkg": "1", - "PublicDescription": "Clockticks of the mesh to PCI (M2P)", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Hit : On NonDirty Line in A State", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Hit : On NonDirty Line in I State", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Hit : On NonDirty Line in L State", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Hit : On NonDirty Line in S State", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Hit : On Dirty Line in A State", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Hit : On Dirty Line in I State", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Hit : On Dirty Line in L State", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Hit : On Dirty Line in S State", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in any state", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in A state", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in I state", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory Lookups : Found in S state", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Miss : On NonDirty Line in A State", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Miss : On NonDirty Line in I State", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Miss : On NonDirty Line in L State", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Miss : On NonDirty Line in S State", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Miss : On Dirty Line in A State", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Miss : On Dirty Line in I State", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Miss : On Dirty Line in L State", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Miss : On Dirty Line in S State", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode.", - "EventCode": "0x2e", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Distress signal asserted : DPT Local", - "EventCode": "0xAF", - "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_LOCAL", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Distress signal asserted : DPT Remote", - "EventCode": "0xAF", - "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_NONLOCAL", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Distress signal asserted : DPT Stalled - IV", - "EventCode": "0xAF", - "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_IV", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit", - "EventCode": "0xAF", - "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_NOCRD", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Distress signal asserted : Horizontal", - "EventCode": "0xAF", - "EventName": "UNC_M2M_DISTRESS_ASSERTED.HORZ", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Distress signal asserted : PMM Local", - "EventCode": "0xAF", - "EventName": "UNC_M2M_DISTRESS_ASSERTED.PMM_LOCAL", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Distress signal asserted : PMM Remote", - "EventCode": "0xAF", - "EventName": "UNC_M2M_DISTRESS_ASSERTED.PMM_NONLOCAL", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Distress signal asserted : Vertical", - "EventCode": "0xAF", - "EventName": "UNC_M2M_DISTRESS_ASSERTED.VERT", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "UNC_M2M_DISTRESS_PMM", - "EventCode": "0xF2", - "EventName": "UNC_M2M_DISTRESS_PMM", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "UNC_M2M_DISTRESS_PMM_MEMMODE", - "EventCode": "0xF1", - "EventName": "UNC_M2M_DISTRESS_PMM_MEMMODE", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements : Down", - "EventCode": "0xBA", - "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN", - "PerPkg": "1", - "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements : Up", - "EventCode": "0xBA", - "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP", - "PerPkg": "1", - "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Left and Even", - "EventCode": "0xB6", - "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", - "EventCode": "0xB6", - "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Right and Even", - "EventCode": "0xB6", - "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", - "EventCode": "0xB6", - "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Even", - "EventCode": "0xBB", - "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", - "EventCode": "0xBB", - "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Even", - "EventCode": "0xBB", - "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", - "EventCode": "0xBB", - "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Even", - "EventCode": "0xB7", - "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", - "EventCode": "0xB7", - "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Even", - "EventCode": "0xB7", - "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", - "EventCode": "0xB7", - "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Left and Even", - "EventCode": "0xB8", - "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", - "EventCode": "0xB8", - "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Right and Even", - "EventCode": "0xB8", - "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", - "EventCode": "0xB8", - "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal IV Ring in Use : Left", - "EventCode": "0xB9", - "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT", - "PerPkg": "1", - "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal IV Ring in Use : Right", - "EventCode": "0xB9", - "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT", - "PerPkg": "1", - "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - All Channels", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.ALL", - "PerPkg": "1", - "UMask": "0x704", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch0", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH0_ALL", - "PerPkg": "1", - "UMask": "0x104", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch0", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR", - "PerPkg": "1", - "UMask": "0x140", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch0", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH0_ISOCH", - "PerPkg": "1", - "UMask": "0x102", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch0", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH0_NORMAL", - "PerPkg": "1", - "UMask": "0x101", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - Ch0", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE", - "PerPkg": "1", - "UMask": "0x110", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : DDR - Ch0", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM", - "PerPkg": "1", - "UMask": "0x108", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : PMM - Ch0", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH0_TO_PMM", - "PerPkg": "1", - "PublicDescription": "M2M Reads Issued to iMC : PMM - Ch0 : Counts all PMM dimm read requests(full line) sent from M2M to iMC", - "UMask": "0x120", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch1", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH1_ALL", - "PerPkg": "1", - "UMask": "0x204", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch1", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR", - "PerPkg": "1", - "UMask": "0x240", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch1", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH1_ISOCH", - "PerPkg": "1", - "UMask": "0x202", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch1", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH1_NORMAL", - "PerPkg": "1", - "UMask": "0x201", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - Ch1", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE", - "PerPkg": "1", - "UMask": "0x210", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : DDR - Ch1", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM", - "PerPkg": "1", - "UMask": "0x208", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : PMM - Ch1", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH1_TO_PMM", - "PerPkg": "1", - "PublicDescription": "M2M Reads Issued to iMC : PMM - Ch1 : Counts all PMM dimm read requests(full line) sent from M2M to iMC", - "UMask": "0x220", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch2", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH2_FROM_TGR", - "PerPkg": "1", - "UMask": "0x440", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : From TGR - All Channels", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.FROM_TGR", - "PerPkg": "1", - "UMask": "0x740", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - All Channels", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.ISOCH", - "PerPkg": "1", - "UMask": "0x702", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - All Channels", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.NORMAL", - "PerPkg": "1", - "UMask": "0x701", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cache - All Channels", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_CACHE", - "PerPkg": "1", - "UMask": "0x710", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : DDR - All Channels", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_MEM", - "PerPkg": "1", - "UMask": "0x708", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : PMM - All Channels", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.TO_PMM", - "PerPkg": "1", - "UMask": "0x720", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : All Writes - All Channels", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.ALL", - "PerPkg": "1", - "UMask": "0x1c10", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch0", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_ALL", - "PerPkg": "1", - "UMask": "0x410", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch0", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch0", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL", - "PerPkg": "1", - "UMask": "0x401", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch0", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH", - "PerPkg": "1", - "UMask": "0x404", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Ch0", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_NI", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch0", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch0", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL", - "PerPkg": "1", - "UMask": "0x402", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch0", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH", - "PerPkg": "1", - "UMask": "0x408", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - Ch0", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_CACHE", - "PerPkg": "1", - "UMask": "0x440", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : DDR - Ch0", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM", - "PerPkg": "1", - "UMask": "0x420", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : PMM - Ch0", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_PMM", - "PerPkg": "1", - "PublicDescription": "M2M Writes Issued to iMC : PMM - Ch0 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC", - "UMask": "0x480", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch1", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_ALL", - "PerPkg": "1", - "UMask": "0x810", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch1", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch1", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL", - "PerPkg": "1", - "UMask": "0x801", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch1", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH", - "PerPkg": "1", - "UMask": "0x804", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Ch1", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_NI", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch1", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch1", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL", - "PerPkg": "1", - "UMask": "0x802", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch1", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH", - "PerPkg": "1", - "UMask": "0x808", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - Ch1", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_CACHE", - "PerPkg": "1", - "UMask": "0x840", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : DDR - Ch1", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_MEM", - "PerPkg": "1", - "UMask": "0x820", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : PMM - Ch1", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_PMM", - "PerPkg": "1", - "PublicDescription": "M2M Writes Issued to iMC : PMM - Ch1 : Counts all PMM dimm writes requests(full line and partial) sent from M2M to iMC", - "UMask": "0x880", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : From TGR - All Channels", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.FROM_TGR", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - All Channels", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.FULL", - "PerPkg": "1", - "UMask": "0x1c01", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - All Channels", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH", - "PerPkg": "1", - "UMask": "0x1c04", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - All Channels", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.NI", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - All Channels", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.NI_MISS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - All Channels", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", - "PerPkg": "1", - "UMask": "0x1c02", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - All Channels", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH", - "PerPkg": "1", - "UMask": "0x1c08", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cache - All Channels", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_CACHE", - "PerPkg": "1", - "UMask": "0x1c40", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : DDR - All Channels", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_MEM", - "PerPkg": "1", - "UMask": "0x1c20", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : PMM - All Channels", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.TO_PMM", - "PerPkg": "1", - "UMask": "0x1c80", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Inserts", - "EventCode": "0x64", - "EventName": "UNC_M2M_MIRR_WRQ_INSERTS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Occupancy", - "EventCode": "0x65", - "EventName": "UNC_M2M_MIRR_WRQ_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0", - "EventCode": "0xE6", - "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1", - "EventCode": "0xE6", - "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Number Packet Header Matches : MC Match", - "EventCode": "0x4C", - "EventName": "UNC_M2M_PKT_MATCH.MC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Number Packet Header Matches : Mesh Match", - "EventCode": "0x4C", - "EventName": "UNC_M2M_PKT_MATCH.MESH", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS", - "EventCode": "0x73", - "EventName": "UNC_M2M_PREFCAM_CIS_DROPS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Cycles Full : All Channels", - "EventCode": "0x6B", - "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.ALLCH", - "PerPkg": "1", - "UMask": "0x7", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Cycles Full : Channel 0", - "EventCode": "0x6B", - "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Cycles Full : Channel 1", - "EventCode": "0x6B", - "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Cycles Full : Channel 2", - "EventCode": "0x6B", - "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Cycles Not Empty : All Channels", - "EventCode": "0x6C", - "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.ALLCH", - "PerPkg": "1", - "UMask": "0x7", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 0", - "EventCode": "0x6C", - "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 1", - "EventCode": "0x6C", - "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 2", - "EventCode": "0x6C", - "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Deallocs", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA0_INVAL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Deallocs", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA1_INVAL", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Deallocs", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_MISS_INVAL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Deallocs", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_RSP_PDRESET", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Deallocs", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA0_INVAL", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Deallocs", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA1_INVAL", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Deallocs", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_MISS_INVAL", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Deallocs", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_RSP_PDRESET", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Deallocs", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_HITA0_INVAL", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Deallocs", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_HITA1_INVAL", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Deallocs", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_MISS_INVAL", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Deallocs", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_RSP_PDRESET", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped : UPI - Ch 0", - "EventCode": "0x6F", - "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_UPI", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped : XPT - Ch 0", - "EventCode": "0x6F", - "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped : UPI - Ch 1", - "EventCode": "0x6F", - "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_UPI", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped : XPT - Ch 1", - "EventCode": "0x6F", - "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped : UPI - Ch 2", - "EventCode": "0x6F", - "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH2_UPI", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped : XPT - Ch 2", - "EventCode": "0x6F", - "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH2_XPT", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped : UPI - All Channels", - "EventCode": "0x6f", - "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.UPI_ALLCH", - "PerPkg": "1", - "UMask": "0x2a", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped : XPT - All Channels", - "EventCode": "0x6f", - "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH", - "PerPkg": "1", - "UMask": "0x15", - "Unit": "M2M" - }, - { - "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 0", - "EventCode": "0x74", - "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPTUPI", - "PerPkg": "1", - "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 0", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 1", - "EventCode": "0x74", - "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPTUPI", - "PerPkg": "1", - "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 2", - "EventCode": "0x74", - "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH2_XPTUPI", - "PerPkg": "1", - "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 2", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- All Channels", - "EventCode": "0x74", - "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPTUPI_ALLCH", - "PerPkg": "1", - "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - All Channels", - "UMask": "0x15", - "Unit": "M2M" - }, - { - "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 0", - "EventCode": "0x75", - "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPTUPI", - "PerPkg": "1", - "PublicDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 0", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 1", - "EventCode": "0x75", - "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPTUPI", - "PerPkg": "1", - "PublicDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 2", - "EventCode": "0x75", - "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH2_XPTUPI", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - All Channels", - "EventCode": "0x75", - "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPTUPI_ALLCH", - "PerPkg": "1", - "UMask": "0x15", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.ERRORBLK_RxC", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.NOT_PF_SAD_REGION", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_AD_CRD", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_FULL", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_HIT", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_SECURE_DROP", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.RPQ_PROXY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.STOP_B2B", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.UPI_THRESH", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.WPQ_PROXY", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.XPT_THRESH", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.ERRORBLK_RxC", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.NOT_PF_SAD_REGION", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_AD_CRD", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_FULL", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_HIT", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_SECURE_DROP", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.RPQ_PROXY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.STOP_B2B", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.UPI_THRESH", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.WPQ_PROXY", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.XPT_THRESH", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", - "EventCode": "0x72", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.ERRORBLK_RxC", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", - "EventCode": "0x72", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.NOT_PF_SAD_REGION", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", - "EventCode": "0x72", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_AD_CRD", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", - "EventCode": "0x72", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_CAM_FULL", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", - "EventCode": "0x72", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_CAM_HIT", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", - "EventCode": "0x72", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_SECURE_DROP", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", - "EventCode": "0x72", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.RPQ_PROXY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", - "EventCode": "0x72", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.STOP_B2B", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", - "EventCode": "0x72", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.UPI_THRESH", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", - "EventCode": "0x72", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.WPQ_PROXY", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", - "EventCode": "0x72", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.XPT_THRESH", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0", - "EventCode": "0x6D", - "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_UPI", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0", - "EventCode": "0x6D", - "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 1", - "EventCode": "0x6D", - "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_UPI", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1", - "EventCode": "0x6D", - "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 2", - "EventCode": "0x6D", - "EventName": "UNC_M2M_PREFCAM_INSERTS.CH2_UPI", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 2", - "EventCode": "0x6D", - "EventName": "UNC_M2M_PREFCAM_INSERTS.CH2_XPT", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels", - "EventCode": "0x6d", - "EventName": "UNC_M2M_PREFCAM_INSERTS.UPI_ALLCH", - "PerPkg": "1", - "UMask": "0x2a", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels", - "EventCode": "0x6D", - "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH", - "PerPkg": "1", - "UMask": "0x15", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Occupancy : All Channels", - "EventCode": "0x6A", - "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH", - "PerPkg": "1", - "UMask": "0x7", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Occupancy : Channel 0", - "EventCode": "0x6A", - "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Occupancy : Channel 1", - "EventCode": "0x6A", - "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Occupancy : Channel 2", - "EventCode": "0x6A", - "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": ": All Channels", - "EventCode": "0x76", - "EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH", - "PerPkg": "1", - "UMask": "0x7", - "Unit": "M2M" - }, - { - "BriefDescription": ": Channel 0", - "EventCode": "0x76", - "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": ": Channel 1", - "EventCode": "0x76", - "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": ": Channel 2", - "EventCode": "0x76", - "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "UNC_M2M_PREFCAM_RxC_CYCLES_NE", - "EventCode": "0x79", - "EventName": "UNC_M2M_PREFCAM_RxC_CYCLES_NE", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", - "EventCode": "0x7A", - "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", - "EventCode": "0x7A", - "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT", - "EventCode": "0x7A", - "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", - "EventCode": "0x7A", - "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "UNC_M2M_PREFCAM_RxC_INSERTS", - "EventCode": "0x78", - "EventName": "UNC_M2M_PREFCAM_RxC_INSERTS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", - "EventCode": "0x77", - "EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD", - "EventCode": "0xAC", - "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK", - "EventCode": "0xAC", - "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL", - "EventCode": "0xAC", - "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV", - "EventCode": "0xAC", - "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : AD", - "EventCode": "0xAA", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core", - "EventCode": "0xAA", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.", - "EventCode": "0xAA", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.AKC", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core", - "EventCode": "0xAA", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.", - "EventCode": "0xAA", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : AD", - "EventCode": "0xAD", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : AK", - "EventCode": "0xAD", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1", - "EventCode": "0xAD", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : BL", - "EventCode": "0xAD", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : IV", - "EventCode": "0xAD", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : AD", - "EventCode": "0xAB", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core", - "EventCode": "0xAB", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring", - "EventCode": "0xAB", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AKC", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core", - "EventCode": "0xAB", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.", - "EventCode": "0xAB", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Source Throttle", - "EventCode": "0xae", - "EventName": "UNC_M2M_RING_SRC_THRTL", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 0", - "EventCode": "0x43", - "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 1", - "EventCode": "0x43", - "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 2", - "EventCode": "0x43", - "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 0", - "EventCode": "0x4F", - "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 1", - "EventCode": "0x4F", - "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel 2", - "EventCode": "0x4F", - "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 0", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 1", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 2", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Ingress (from CMS) Full", - "EventCode": "0x04", - "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Ingress (from CMS) Not Empty", - "EventCode": "0x03", - "EventName": "UNC_M2M_RxC_AD_CYCLES_NE", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Ingress (from CMS) Allocations", - "EventCode": "0x01", - "EventName": "UNC_M2M_RxC_AD_INSERTS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Ingress (from CMS) Occupancy", - "EventCode": "0x02", - "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches", - "EventCode": "0x77", - "EventName": "UNC_M2M_RxC_AD_PREF_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations", - "EventCode": "0x5C", - "EventName": "UNC_M2M_RxC_AK_WR_CMP", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Ingress (from CMS) Full", - "EventCode": "0x08", - "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Ingress (from CMS) Not Empty", - "EventCode": "0x07", - "EventName": "UNC_M2M_RxC_BL_CYCLES_NE", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Ingress (from CMS) Allocations", - "EventCode": "0x05", - "EventName": "UNC_M2M_RxC_BL_INSERTS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Ingress (from CMS) Occupancy", - "EventCode": "0x06", - "EventName": "UNC_M2M_RxC_BL_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - All", - "EventCode": "0xE5", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Credited", - "EventCode": "0xE5", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", - "EventCode": "0xE5", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - All", - "EventCode": "0xE5", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Credited", - "EventCode": "0xE5", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", - "EventCode": "0xE5", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AD - All", - "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AD - Credited", - "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", - "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AK", - "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", - "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass : BL - All", - "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass : BL - Credited", - "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", - "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass : IV", - "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - All", - "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Credited", - "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", - "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : AK", - "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - All", - "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Credited", - "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", - "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : IFV - Credited", - "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : IV", - "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation", - "EventCode": "0xe4", - "EventName": "UNC_M2M_RxR_CRD_STARVED_1", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AD - All", - "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AD - Credited", - "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited", - "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AK", - "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited", - "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations : BL - All", - "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations : BL - Credited", - "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited", - "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations : IV", - "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AD - All", - "EventCode": "0xE0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", - "EventCode": "0xE0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited", - "EventCode": "0xE0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AK", - "EventCode": "0xE0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited", - "EventCode": "0xE0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : BL - All", - "EventCode": "0xE0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", - "EventCode": "0xE0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited", - "EventCode": "0xE0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : IV", - "EventCode": "0xE0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS", - "EventCode": "0x33", - "EventName": "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS", - "EventCode": "0x34", - "EventName": "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Retry - Mem Mirroring Mode", - "EventCode": "0x35", - "EventName": "UNC_M2M_SCOREBOARD_BL_RETRY_ACCEPTS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Retry - Mem Mirroring Mode", - "EventCode": "0x36", - "EventName": "UNC_M2M_SCOREBOARD_BL_RETRY_REJECTS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Scoreboard Accepts", - "EventCode": "0x2F", - "EventName": "UNC_M2M_SCOREBOARD_RD_ACCEPTS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Scoreboard Rejects", - "EventCode": "0x30", - "EventName": "UNC_M2M_SCOREBOARD_RD_REJECTS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Scoreboard Accepts", - "EventCode": "0x31", - "EventName": "UNC_M2M_SCOREBOARD_WR_ACCEPTS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Scoreboard Rejects", - "EventCode": "0x32", - "EventName": "UNC_M2M_SCOREBOARD_WR_REJECTS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10", - "EventCode": "0xD1", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8", - "EventCode": "0xD1", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9", - "EventCode": "0xD1", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10", - "EventCode": "0xD3", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8", - "EventCode": "0xD3", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9", - "EventCode": "0xD3", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10", - "EventCode": "0xD5", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8", - "EventCode": "0xD5", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9", - "EventCode": "0xD5", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10", - "EventCode": "0xD7", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8", - "EventCode": "0xD7", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9", - "EventCode": "0xD7", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Tag Hit : Clean NearMem Read Hit", - "EventCode": "0x2C", - "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN", - "PerPkg": "1", - "PublicDescription": "Tag Hit : Clean NearMem Read Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean full line read hits (reads and RFOs).", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Tag Hit : Dirty NearMem Read Hit", - "EventCode": "0x2C", - "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY", - "PerPkg": "1", - "PublicDescription": "Tag Hit : Dirty NearMem Read Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty full line read hits (reads and RFOs).", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Tag Hit : Clean NearMem Underfill Hit", - "EventCode": "0x2C", - "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN", - "PerPkg": "1", - "PublicDescription": "Tag Hit : Clean NearMem Underfill Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean underfill hits due to a partial write", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Tag Hit : Dirty NearMem Underfill Hit", - "EventCode": "0x2C", - "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY", - "PerPkg": "1", - "PublicDescription": "Tag Hit : Dirty NearMem Underfill Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty underfill read hits due to a partial write", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Tag Miss", - "EventCode": "0x61", - "EventName": "UNC_M2M_TAG_MISS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Number AD Ingress Credits", - "EventCode": "0x41", - "EventName": "UNC_M2M_TGR_AD_CREDITS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Number BL Ingress Credits", - "EventCode": "0x42", - "EventName": "UNC_M2M_TGR_BL_CREDITS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Cycles Full : Channel 0", - "EventCode": "0x45", - "EventName": "UNC_M2M_TRACKER_FULL.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Cycles Full : Channel 1", - "EventCode": "0x45", - "EventName": "UNC_M2M_TRACKER_FULL.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Cycles Full : Channel 2", - "EventCode": "0x45", - "EventName": "UNC_M2M_TRACKER_FULL.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Inserts : Channel 0", - "EventCode": "0x49", - "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Inserts : Channel 1", - "EventCode": "0x49", - "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Inserts : Channel 2", - "EventCode": "0x49", - "EventName": "UNC_M2M_TRACKER_INSERTS.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Cycles Not Empty : Channel 0", - "EventCode": "0x46", - "EventName": "UNC_M2M_TRACKER_NE.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Cycles Not Empty : Channel 1", - "EventCode": "0x46", - "EventName": "UNC_M2M_TRACKER_NE.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Cycles Not Empty : Channel 2", - "EventCode": "0x46", - "EventName": "UNC_M2M_TRACKER_NE.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Occupancy : Channel 0", - "EventCode": "0x47", - "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Occupancy : Channel 1", - "EventCode": "0x47", - "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Occupancy : Channel 2", - "EventCode": "0x47", - "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Egress (to CMS) Credit Acquired", - "EventCode": "0x0d", - "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Egress (to CMS) Credits Occupancy", - "EventCode": "0x0e", - "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Egress (to CMS) Full", - "EventCode": "0x0c", - "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Egress (to CMS) Not Empty", - "EventCode": "0x0b", - "EventName": "UNC_M2M_TxC_AD_CYCLES_NE", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Egress (to CMS) Allocations", - "EventCode": "0x09", - "EventName": "UNC_M2M_TxC_AD_INSERTS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles with No AD Egress (to CMS) Credits", - "EventCode": "0x0f", - "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits", - "EventCode": "0x10", - "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Egress (to CMS) Occupancy", - "EventCode": "0x0A", - "EventName": "UNC_M2M_TxC_AD_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Outbound Ring Transactions on AK : CRD Transactions to Cbo", - "EventCode": "0x39", - "EventName": "UNC_M2M_TxC_AK.CRD_CBO", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Outbound Ring Transactions on AK : NDR Transactions", - "EventCode": "0x39", - "EventName": "UNC_M2M_TxC_AK.NDR", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AKC Credits", - "EventCode": "0x5F", - "EventName": "UNC_M2M_TxC_AKC_CREDITS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side", - "EventCode": "0x1D", - "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side", - "EventCode": "0x1D", - "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full : All", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Near Side", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Far Side", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1", - "PerPkg": "1", - "UMask": "0x88", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1", - "PerPkg": "1", - "UMask": "0xa0", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1", - "PerPkg": "1", - "UMask": "0x90", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Not Empty : All", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Near Side", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Far Side", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Not Empty", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Not Empty", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Not Empty", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations : All", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Near Side", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Far Side", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side", - "EventCode": "0x1F", - "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side", - "EventCode": "0x1F", - "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side", - "EventCode": "0x20", - "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side", - "EventCode": "0x20", - "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Occupancy : All", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Near Side", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Far Side", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Occupancy", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Occupancy", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Occupancy", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Cache", - "EventCode": "0x40", - "EventName": "UNC_M2M_TxC_BL.DRS_CACHE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Core", - "EventCode": "0x40", - "EventName": "UNC_M2M_TxC_BL.DRS_CORE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to QPI", - "EventCode": "0x40", - "EventName": "UNC_M2M_TxC_BL.DRS_UPI", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side", - "EventCode": "0x19", - "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side", - "EventCode": "0x19", - "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Full : All", - "EventCode": "0x18", - "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Near Side", - "EventCode": "0x18", - "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Far Side", - "EventCode": "0x18", - "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Not Empty : All", - "EventCode": "0x17", - "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Near Side", - "EventCode": "0x17", - "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Far Side", - "EventCode": "0x17", - "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Allocations : All", - "EventCode": "0x15", - "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Near Side", - "EventCode": "0x15", - "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Far Side", - "EventCode": "0x15", - "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side", - "EventCode": "0x1B", - "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side", - "EventCode": "0x1B", - "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side", - "EventCode": "0x1C", - "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side", - "EventCode": "0x1C", - "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : AD - All", - "EventCode": "0xA6", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", - "EventCode": "0xA6", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", - "EventCode": "0xA6", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : BL - All", - "EventCode": "0xA6", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", - "EventCode": "0xA6", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", - "EventCode": "0xA6", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AD - All", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AK", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : BL - All", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : IV", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AK", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : IV", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AK", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : IV", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AK", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : IV", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All", - "EventCode": "0xA5", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited", - "EventCode": "0xA5", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK", - "EventCode": "0xA5", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited", - "EventCode": "0xA5", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All", - "EventCode": "0xA5", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited", - "EventCode": "0xA5", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV", - "EventCode": "0xA5", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0", - "EventCode": "0x95", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1", - "EventCode": "0x95", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0", - "EventCode": "0x97", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1", - "EventCode": "0x97", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_INSERTS0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : IV", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", - "EventCode": "0x99", - "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", - "EventCode": "0x99", - "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : IV", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", - "EventCode": "0x9B", - "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1", - "EventCode": "0x9B", - "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", - "EventCode": "0x9B", - "EventName": "UNC_M2M_TxR_VERT_STARVED1.TGC", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Down and Even", - "EventCode": "0xB0", - "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Down and Odd", - "EventCode": "0xB0", - "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Up and Even", - "EventCode": "0xB0", - "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Up and Odd", - "EventCode": "0xB0", - "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Down and Even", - "EventCode": "0xB4", - "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", - "EventCode": "0xB4", - "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Up and Even", - "EventCode": "0xB4", - "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", - "EventCode": "0xB4", - "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Down and Even", - "EventCode": "0xB1", - "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Down and Odd", - "EventCode": "0xB1", - "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Up and Even", - "EventCode": "0xB1", - "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Up and Odd", - "EventCode": "0xB1", - "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Down and Even", - "EventCode": "0xB2", - "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Down and Odd", - "EventCode": "0xB2", - "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Up and Even", - "EventCode": "0xB2", - "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Up and Odd", - "EventCode": "0xB2", - "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical IV Ring in Use : Down", - "EventCode": "0xB3", - "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN", - "PerPkg": "1", - "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical IV Ring in Use : Up", - "EventCode": "0xB3", - "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP", - "PerPkg": "1", - "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Down and Even", - "EventCode": "0xB5", - "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", - "EventCode": "0xB5", - "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Up and Even", - "EventCode": "0xB5", - "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", - "EventCode": "0xB5", - "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "WPQ Flush : Channel 0", - "EventCode": "0x58", - "EventName": "UNC_M2M_WPQ_FLUSH.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "WPQ Flush : Channel 1", - "EventCode": "0x58", - "EventName": "UNC_M2M_WPQ_FLUSH.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "WPQ Flush : Channel 2", - "EventCode": "0x58", - "EventName": "UNC_M2M_WPQ_FLUSH.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 2", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 0", - "EventCode": "0x51", - "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 1", - "EventCode": "0x51", - "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel 2", - "EventCode": "0x51", - "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 0", - "EventCode": "0x4E", - "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 1", - "EventCode": "0x4E", - "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 2", - "EventCode": "0x4E", - "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Full : Channel 0", - "EventCode": "0x4A", - "EventName": "UNC_M2M_WR_TRACKER_FULL.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Full : Channel 1", - "EventCode": "0x4A", - "EventName": "UNC_M2M_WR_TRACKER_FULL.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Full : Channel 2", - "EventCode": "0x4A", - "EventName": "UNC_M2M_WR_TRACKER_FULL.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Full : Mirror", - "EventCode": "0x4A", - "EventName": "UNC_M2M_WR_TRACKER_FULL.MIRR", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Inserts : Channel 0", - "EventCode": "0x56", - "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Inserts : Channel 1", - "EventCode": "0x56", - "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Inserts : Channel 2", - "EventCode": "0x56", - "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Not Empty : Channel 0", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WR_TRACKER_NE.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Not Empty : Channel 1", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WR_TRACKER_NE.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Not Empty : Channel 2", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WR_TRACKER_NE.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Not Empty : Mirror", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Not Empty", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Not Empty", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0", - "EventCode": "0x63", - "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1", - "EventCode": "0x63", - "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 2", - "EventCode": "0x63", - "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 0", - "EventCode": "0x62", - "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 1", - "EventCode": "0x62", - "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 2", - "EventCode": "0x62", - "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Occupancy : Channel 0", - "EventCode": "0x55", - "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Occupancy : Channel 1", - "EventCode": "0x55", - "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Occupancy : Channel 2", - "EventCode": "0x55", - "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Occupancy : Mirror", - "EventCode": "0x55", - "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Occupancy", - "EventCode": "0x55", - "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_NONTGR", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Occupancy", - "EventCode": "0x55", - "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_PWR", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Posted Inserts : Channel 0", - "EventCode": "0x5E", - "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Posted Inserts : Channel 1", - "EventCode": "0x5E", - "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Posted Inserts : Channel 2", - "EventCode": "0x5E", - "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Posted Occupancy : Channel 0", - "EventCode": "0x5D", - "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Posted Occupancy : Channel 1", - "EventCode": "0x5D", - "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Posted Occupancy : Channel 2", - "EventCode": "0x5D", - "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0", - "EventCode": "0x80", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1", - "EventCode": "0x80", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2", - "EventCode": "0x80", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3", - "EventCode": "0x80", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4", - "EventCode": "0x80", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5", - "EventCode": "0x80", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6", - "EventCode": "0x80", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7", - "EventCode": "0x80", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10", - "EventCode": "0x81", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8", - "EventCode": "0x81", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9", - "EventCode": "0x81", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0", - "EventCode": "0x82", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1", - "EventCode": "0x82", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2", - "EventCode": "0x82", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3", - "EventCode": "0x82", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4", - "EventCode": "0x82", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5", - "EventCode": "0x82", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6", - "EventCode": "0x82", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7", - "EventCode": "0x82", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10", - "EventCode": "0x83", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8", - "EventCode": "0x83", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9", - "EventCode": "0x83", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0", - "EventCode": "0x88", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1", - "EventCode": "0x88", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2", - "EventCode": "0x88", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3", - "EventCode": "0x88", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4", - "EventCode": "0x88", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5", - "EventCode": "0x88", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6", - "EventCode": "0x88", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7", - "EventCode": "0x88", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10", - "EventCode": "0x89", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8", - "EventCode": "0x89", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9", - "EventCode": "0x89", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0", - "EventCode": "0x8a", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1", - "EventCode": "0x8a", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2", - "EventCode": "0x8a", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3", - "EventCode": "0x8a", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4", - "EventCode": "0x8a", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5", - "EventCode": "0x8a", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6", - "EventCode": "0x8a", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7", - "EventCode": "0x8a", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10", - "EventCode": "0x8b", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8", - "EventCode": "0x8b", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9", - "EventCode": "0x8b", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0", - "EventCode": "0x84", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1", - "EventCode": "0x84", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2", - "EventCode": "0x84", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3", - "EventCode": "0x84", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4", - "EventCode": "0x84", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5", - "EventCode": "0x84", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6", - "EventCode": "0x84", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7", - "EventCode": "0x84", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10", - "EventCode": "0x85", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8", - "EventCode": "0x85", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9", - "EventCode": "0x85", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0", - "EventCode": "0x86", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1", - "EventCode": "0x86", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2", - "EventCode": "0x86", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3", - "EventCode": "0x86", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4", - "EventCode": "0x86", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5", - "EventCode": "0x86", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6", - "EventCode": "0x86", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7", - "EventCode": "0x86", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10", - "EventCode": "0x87", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8", - "EventCode": "0x87", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9", - "EventCode": "0x87", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0", - "EventCode": "0x8c", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1", - "EventCode": "0x8c", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2", - "EventCode": "0x8c", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3", - "EventCode": "0x8c", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", - "EventCode": "0x8c", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", - "EventCode": "0x8c", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", - "EventCode": "0x8c", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", - "EventCode": "0x8c", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10", - "EventCode": "0x8d", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8", - "EventCode": "0x8d", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9", - "EventCode": "0x8d", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0", - "EventCode": "0x8e", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1", - "EventCode": "0x8e", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2", - "EventCode": "0x8e", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3", - "EventCode": "0x8e", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4", - "EventCode": "0x8e", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5", - "EventCode": "0x8e", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6", - "EventCode": "0x8e", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7", - "EventCode": "0x8e", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10", - "EventCode": "0x8f", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8", - "EventCode": "0x8f", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9", - "EventCode": "0x8f", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Clockticks of the mesh to PCI (M2P)", - "EventCode": "0x01", - "EventName": "UNC_M2P_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Clockticks of the mesh to PCI (M2P) : Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Clockticks", - "EventCode": "0xc0", - "EventName": "UNC_M2P_CMS_CLOCKTICKS", - "PerPkg": "1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Distress signal asserted : DPT Local", - "EventCode": "0xaf", - "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_LOCAL", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Distress signal asserted : DPT Remote", - "EventCode": "0xaf", - "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_NONLOCAL", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Distress signal asserted : DPT Stalled - IV", - "EventCode": "0xaf", - "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_IV", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit", - "EventCode": "0xaf", - "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_NOCRD", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Distress signal asserted : Horizontal", - "EventCode": "0xaf", - "EventName": "UNC_M2P_DISTRESS_ASSERTED.HORZ", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Distress signal asserted : PMM Local", - "EventCode": "0xAF", - "EventName": "UNC_M2P_DISTRESS_ASSERTED.PMM_LOCAL", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Distress signal asserted : PMM Remote", - "EventCode": "0xAF", - "EventName": "UNC_M2P_DISTRESS_ASSERTED.PMM_NONLOCAL", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Distress signal asserted : Vertical", - "EventCode": "0xaf", - "EventName": "UNC_M2P_DISTRESS_ASSERTED.VERT", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements : Down", - "EventCode": "0xba", - "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN", - "PerPkg": "1", - "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements : Up", - "EventCode": "0xba", - "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP", - "PerPkg": "1", - "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Left and Even", - "EventCode": "0xb6", - "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", - "EventCode": "0xb6", - "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Right and Even", - "EventCode": "0xb6", - "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", - "EventCode": "0xb6", - "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Even", - "EventCode": "0xbb", - "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", - "EventCode": "0xbb", - "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Even", - "EventCode": "0xbb", - "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", - "EventCode": "0xbb", - "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Even", - "EventCode": "0xb7", - "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", - "EventCode": "0xb7", - "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Even", - "EventCode": "0xb7", - "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", - "EventCode": "0xb7", - "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Left and Even", - "EventCode": "0xb8", - "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", - "EventCode": "0xb8", - "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Right and Even", - "EventCode": "0xb8", - "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", - "EventCode": "0xb8", - "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal IV Ring in Use : Left", - "EventCode": "0xb9", - "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.LEFT", - "PerPkg": "1", - "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal IV Ring in Use : Right", - "EventCode": "0xb9", - "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.RIGHT", - "PerPkg": "1", - "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", - "EventCode": "0x33", - "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", - "EventCode": "0x33", - "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", - "EventCode": "0x33", - "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", - "EventCode": "0x33", - "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", - "EventCode": "0x33", - "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", - "EventCode": "0x33", - "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS", - "EventCode": "0x34", - "EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the DRS message class.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB", - "EventCode": "0x34", - "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCB message class.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS", - "EventCode": "0x34", - "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCS message class.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0", - "EventCode": "0x32", - "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1", - "EventCode": "0x32", - "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0", - "EventCode": "0x32", - "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1", - "EventCode": "0x32", - "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0", - "EventCode": "0x32", - "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1", - "EventCode": "0x32", - "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCB", - "EventCode": "0x46", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCS", - "EventCode": "0x46", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCB", - "EventCode": "0x46", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCS", - "EventCode": "0x46", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCB", - "EventCode": "0x46", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCS", - "EventCode": "0x46", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCB", - "EventCode": "0x46", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCS", - "EventCode": "0x46", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCB", - "EventCode": "0x47", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCS", - "EventCode": "0x47", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCB", - "EventCode": "0x47", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCS", - "EventCode": "0x47", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCB", - "EventCode": "0x19", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCS", - "EventCode": "0x19", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCB", - "EventCode": "0x19", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCS", - "EventCode": "0x19", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCB", - "EventCode": "0x19", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCS", - "EventCode": "0x19", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB", - "EventCode": "0x19", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS", - "EventCode": "0x19", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCB", - "EventCode": "0x1a", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCS", - "EventCode": "0x1a", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCB", - "EventCode": "0x1a", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCS", - "EventCode": "0x1a", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Shared Credits Returned : Agent0", - "EventCode": "0x17", - "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Shared Credits Returned : Agent1", - "EventCode": "0x17", - "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Shared Credits Returned : Agent2", - "EventCode": "0x17", - "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent0", - "EventCode": "0x44", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent1", - "EventCode": "0x44", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent2", - "EventCode": "0x44", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent3", - "EventCode": "0x44", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent4", - "EventCode": "0x44", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent5", - "EventCode": "0x44", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCB", - "EventCode": "0x40", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCS", - "EventCode": "0x40", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCB", - "EventCode": "0x40", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCS", - "EventCode": "0x40", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCB", - "EventCode": "0x40", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCS", - "EventCode": "0x40", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCB", - "EventCode": "0x40", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCS", - "EventCode": "0x40", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCB", - "EventCode": "0x41", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCS", - "EventCode": "0x41", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCB", - "EventCode": "0x41", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCS", - "EventCode": "0x41", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCB", - "EventCode": "0x4a", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCS", - "EventCode": "0x4a", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCB", - "EventCode": "0x4a", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCS", - "EventCode": "0x4a", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCB", - "EventCode": "0x4a", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCS", - "EventCode": "0x4a", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCB", - "EventCode": "0x4a", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCS", - "EventCode": "0x4a", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCB", - "EventCode": "0x4b", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCS", - "EventCode": "0x4b", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCB", - "EventCode": "0x4b", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCS", - "EventCode": "0x4b", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0", - "EventCode": "0xe6", - "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1", - "EventCode": "0xe6", - "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "P2P Credit Occupancy : All", - "EventCode": "0x14", - "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "P2P Credit Occupancy : Local NCB", - "EventCode": "0x14", - "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "P2P Credit Occupancy : Local NCS", - "EventCode": "0x14", - "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "P2P Credit Occupancy : Remote NCB", - "EventCode": "0x14", - "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "P2P Credit Occupancy : Remote NCS", - "EventCode": "0x14", - "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Dedicated Credits Received : All", - "EventCode": "0x16", - "EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Dedicated Credits Received : Local NCB", - "EventCode": "0x16", - "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Dedicated Credits Received : Local NCS", - "EventCode": "0x16", - "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Dedicated Credits Received : Remote NCB", - "EventCode": "0x16", - "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Dedicated Credits Received : Remote NCS", - "EventCode": "0x16", - "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Shared Credits Received : All", - "EventCode": "0x15", - "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Shared Credits Received : Local NCB", - "EventCode": "0x15", - "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Shared Credits Received : Local NCS", - "EventCode": "0x15", - "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Shared Credits Received : Remote NCB", - "EventCode": "0x15", - "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Shared Credits Received : Remote NCS", - "EventCode": "0x15", - "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - DRS", - "EventCode": "0x48", - "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_DRS", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCB", - "EventCode": "0x48", - "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCB", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 - NCS", - "EventCode": "0x48", - "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCS", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - DRS", - "EventCode": "0x48", - "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_DRS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCB", - "EventCode": "0x48", - "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCB", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 - NCS", - "EventCode": "0x48", - "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - DRS", - "EventCode": "0x49", - "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_DRS", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCB", - "EventCode": "0x49", - "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCB", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 - NCS", - "EventCode": "0x49", - "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCS", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 - NCB", - "EventCode": "0x1b", - "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 - NCS", - "EventCode": "0x1b", - "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 - NCB", - "EventCode": "0x1b", - "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 - NCS", - "EventCode": "0x1b", - "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 - NCB", - "EventCode": "0x1b", - "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCB", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 - NCS", - "EventCode": "0x1b", - "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote P2P Shared Credits Returned : Agent0", - "EventCode": "0x18", - "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote P2P Shared Credits Returned : Agent1", - "EventCode": "0x18", - "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote P2P Shared Credits Returned : Agent2", - "EventCode": "0x18", - "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent0", - "EventCode": "0x45", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent1", - "EventCode": "0x45", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent2", - "EventCode": "0x45", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - DRS", - "EventCode": "0x42", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_DRS", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - NCB", - "EventCode": "0x42", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCB", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - NCS", - "EventCode": "0x42", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCS", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - DRS", - "EventCode": "0x42", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_DRS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - NCB", - "EventCode": "0x42", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCB", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - NCS", - "EventCode": "0x42", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - DRS", - "EventCode": "0x43", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_DRS", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - NCB", - "EventCode": "0x43", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCB", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - NCS", - "EventCode": "0x43", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCS", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - DRS", - "EventCode": "0x4c", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_DRS", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCB", - "EventCode": "0x4c", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCB", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI0 - NCS", - "EventCode": "0x4c", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCS", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - DRS", - "EventCode": "0x4c", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_DRS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCB", - "EventCode": "0x4c", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCB", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI1 - NCS", - "EventCode": "0x4c", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - DRS", - "EventCode": "0x4d", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_DRS", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCB", - "EventCode": "0x4d", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCB", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI2 - NCS", - "EventCode": "0x4d", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCS", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD", - "EventCode": "0xac", - "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AD", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK", - "EventCode": "0xac", - "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AK", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL", - "EventCode": "0xac", - "EventName": "UNC_M2P_RING_BOUNCES_HORZ.BL", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV", - "EventCode": "0xac", - "EventName": "UNC_M2P_RING_BOUNCES_HORZ.IV", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : AD", - "EventCode": "0xaa", - "EventName": "UNC_M2P_RING_BOUNCES_VERT.AD", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core", - "EventCode": "0xaa", - "EventName": "UNC_M2P_RING_BOUNCES_VERT.AK", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.", - "EventCode": "0xaa", - "EventName": "UNC_M2P_RING_BOUNCES_VERT.AKC", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core", - "EventCode": "0xaa", - "EventName": "UNC_M2P_RING_BOUNCES_VERT.BL", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.", - "EventCode": "0xaa", - "EventName": "UNC_M2P_RING_BOUNCES_VERT.IV", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : AD", - "EventCode": "0xad", - "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : AK", - "EventCode": "0xad", - "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1", - "EventCode": "0xad", - "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : BL", - "EventCode": "0xad", - "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : IV", - "EventCode": "0xad", - "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : AD", - "EventCode": "0xab", - "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core", - "EventCode": "0xab", - "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring", - "EventCode": "0xab", - "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AKC", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core", - "EventCode": "0xab", - "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.", - "EventCode": "0xab", - "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Source Throttle", - "EventCode": "0xae", - "EventName": "UNC_M2P_RING_SRC_THRTL", - "PerPkg": "1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", - "EventCode": "0x10", - "EventName": "UNC_M2P_RxC_CYCLES_NE.ALL", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", - "EventCode": "0x10", - "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", - "EventCode": "0x10", - "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", - "EventCode": "0x10", - "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", - "EventCode": "0x10", - "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", - "EventCode": "0x10", - "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", - "EventCode": "0x10", - "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCB", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", - "EventCode": "0x10", - "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCS", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Inserts", - "EventCode": "0x11", - "EventName": "UNC_M2P_RxC_INSERTS.ALL", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Inserts", - "EventCode": "0x11", - "EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Inserts", - "EventCode": "0x11", - "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Inserts", - "EventCode": "0x11", - "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Inserts", - "EventCode": "0x11", - "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Inserts", - "EventCode": "0x11", - "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Inserts", - "EventCode": "0x11", - "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCB", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Inserts", - "EventCode": "0x11", - "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCS", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - All", - "EventCode": "0xe5", - "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Credited", - "EventCode": "0xe5", - "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", - "EventCode": "0xe5", - "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - All", - "EventCode": "0xe5", - "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Credited", - "EventCode": "0xe5", - "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", - "EventCode": "0xe5", - "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AD - All", - "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AD - Credited", - "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", - "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AK", - "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", - "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Bypass : BL - All", - "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Bypass : BL - Credited", - "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", - "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Bypass : IV", - "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - All", - "EventCode": "0xe3", - "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Credited", - "EventCode": "0xe3", - "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", - "EventCode": "0xe3", - "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : AK", - "EventCode": "0xe3", - "EventName": "UNC_M2P_RxR_CRD_STARVED.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - All", - "EventCode": "0xe3", - "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Credited", - "EventCode": "0xe3", - "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", - "EventCode": "0xe3", - "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : IFV - Credited", - "EventCode": "0xe3", - "EventName": "UNC_M2P_RxR_CRD_STARVED.IFV", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : IV", - "EventCode": "0xe3", - "EventName": "UNC_M2P_RxR_CRD_STARVED.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation", - "EventCode": "0xe4", - "EventName": "UNC_M2P_RxR_CRD_STARVED_1", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AD - All", - "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AD - Credited", - "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited", - "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AK", - "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited", - "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Allocations : BL - All", - "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Allocations : BL - Credited", - "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited", - "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Allocations : IV", - "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AD - All", - "EventCode": "0xe0", - "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", - "EventCode": "0xe0", - "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited", - "EventCode": "0xe0", - "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AK", - "EventCode": "0xe0", - "EventName": "UNC_M2P_RxR_OCCUPANCY.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited", - "EventCode": "0xe0", - "EventName": "UNC_M2P_RxR_OCCUPANCY.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : BL - All", - "EventCode": "0xe0", - "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", - "EventCode": "0xe0", - "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited", - "EventCode": "0xe0", - "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : IV", - "EventCode": "0xe0", - "EventName": "UNC_M2P_RxR_OCCUPANCY.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0", - "EventCode": "0xd0", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1", - "EventCode": "0xd0", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2", - "EventCode": "0xd0", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3", - "EventCode": "0xd0", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4", - "EventCode": "0xd0", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5", - "EventCode": "0xd0", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6", - "EventCode": "0xd0", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7", - "EventCode": "0xd0", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0", - "EventCode": "0xd2", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1", - "EventCode": "0xd2", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2", - "EventCode": "0xd2", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3", - "EventCode": "0xd2", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4", - "EventCode": "0xd2", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5", - "EventCode": "0xd2", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6", - "EventCode": "0xd2", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7", - "EventCode": "0xd2", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0", - "EventCode": "0xd4", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1", - "EventCode": "0xd4", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2", - "EventCode": "0xd4", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3", - "EventCode": "0xd4", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4", - "EventCode": "0xd4", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5", - "EventCode": "0xd4", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6", - "EventCode": "0xd4", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7", - "EventCode": "0xd4", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0", - "EventCode": "0xd6", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1", - "EventCode": "0xd6", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2", - "EventCode": "0xd6", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3", - "EventCode": "0xd6", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4", - "EventCode": "0xd6", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5", - "EventCode": "0xd6", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6", - "EventCode": "0xd6", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7", - "EventCode": "0xd6", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10", - "EventCode": "0xd1", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8", - "EventCode": "0xd1", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9", - "EventCode": "0xd1", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10", - "EventCode": "0xd3", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8", - "EventCode": "0xd3", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9", - "EventCode": "0xd3", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10", - "EventCode": "0xd5", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8", - "EventCode": "0xd5", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9", - "EventCode": "0xd5", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10", - "EventCode": "0xd7", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8", - "EventCode": "0xd7", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9", - "EventCode": "0xd7", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "UNC_M2P_TxC_CREDITS.PMM", - "EventCode": "0x2D", - "EventName": "UNC_M2P_TxC_CREDITS.PMM", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ", - "EventCode": "0x2d", - "EventName": "UNC_M2P_TxC_CREDITS.PRQ", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Full", - "EventCode": "0x25", - "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_0", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Full", - "EventCode": "0x25", - "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_1", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Full", - "EventCode": "0x25", - "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_0", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Full", - "EventCode": "0x25", - "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_1", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Full", - "EventCode": "0x25", - "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_0", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Full", - "EventCode": "0x25", - "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_1", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Full", - "EventCode": "0x25", - "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_0", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Full", - "EventCode": "0x25", - "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_1", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Not Empty", - "EventCode": "0x23", - "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_0", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Not Empty", - "EventCode": "0x23", - "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_1", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Not Empty", - "EventCode": "0x23", - "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_0", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Not Empty", - "EventCode": "0x23", - "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_1", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Not Empty", - "EventCode": "0x23", - "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_0", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Not Empty", - "EventCode": "0x23", - "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_1", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Not Empty", - "EventCode": "0x23", - "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_0", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Not Empty", - "EventCode": "0x23", - "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_1", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Ingress", - "EventCode": "0x24", - "EventName": "UNC_M2P_TxC_INSERTS.AD_0", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Ingress", - "EventCode": "0x24", - "EventName": "UNC_M2P_TxC_INSERTS.AD_1", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Ingress", - "EventCode": "0x24", - "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_0", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Ingress", - "EventCode": "0x24", - "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_1", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Ingress", - "EventCode": "0x24", - "EventName": "UNC_M2P_TxC_INSERTS.BL_0", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Ingress", - "EventCode": "0x24", - "EventName": "UNC_M2P_TxC_INSERTS.BL_1", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : AD - All", - "EventCode": "0xa6", - "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", - "EventCode": "0xa6", - "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", - "EventCode": "0xa6", - "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : BL - All", - "EventCode": "0xa6", - "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", - "EventCode": "0xa6", - "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", - "EventCode": "0xa6", - "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AD - All", - "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", - "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", - "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AK", - "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited", - "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : BL - All", - "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", - "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", - "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : IV", - "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All", - "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited", - "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited", - "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK", - "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AK", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited", - "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All", - "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited", - "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited", - "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV", - "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.IV", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All", - "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited", - "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited", - "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK", - "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AK", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited", - "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All", - "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited", - "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited", - "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV", - "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.IV", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", - "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited", - "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited", - "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AK", - "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited", - "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", - "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited", - "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited", - "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : IV", - "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", - "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", - "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited", - "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AK", - "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited", - "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", - "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", - "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited", - "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : IV", - "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", - "EventCode": "0xa0", - "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited", - "EventCode": "0xa0", - "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited", - "EventCode": "0xa0", - "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AK", - "EventCode": "0xa0", - "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited", - "EventCode": "0xa0", - "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", - "EventCode": "0xa0", - "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited", - "EventCode": "0xa0", - "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited", - "EventCode": "0xa0", - "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : IV", - "EventCode": "0xa0", - "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All", - "EventCode": "0xa5", - "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited", - "EventCode": "0xa5", - "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK", - "EventCode": "0xa5", - "EventName": "UNC_M2P_TxR_HORZ_STARVED.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited", - "EventCode": "0xa5", - "EventName": "UNC_M2P_TxR_HORZ_STARVED.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All", - "EventCode": "0xa5", - "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited", - "EventCode": "0xa5", - "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV", - "EventCode": "0xa5", - "EventName": "UNC_M2P_TxR_HORZ_STARVED.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", - "EventCode": "0x9c", - "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", - "EventCode": "0x9c", - "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", - "EventCode": "0x9c", - "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", - "EventCode": "0x9c", - "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", - "EventCode": "0x9d", - "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", - "EventCode": "0x9d", - "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", - "EventCode": "0x9d", - "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", - "EventCode": "0x9d", - "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", - "EventCode": "0x9d", - "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", - "EventCode": "0x9d", - "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", - "EventCode": "0x9d", - "EventName": "UNC_M2P_TxR_VERT_BYPASS.IV_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", - "EventCode": "0x9e", - "EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", - "EventCode": "0x9e", - "EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1", - "EventCode": "0x94", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1", - "EventCode": "0x94", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1", - "EventCode": "0x94", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0", - "EventCode": "0x95", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1", - "EventCode": "0x95", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1", - "EventCode": "0x96", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1", - "EventCode": "0x96", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1", - "EventCode": "0x96", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0", - "EventCode": "0x97", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1", - "EventCode": "0x97", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M2P_TxR_VERT_INSERTS0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : IV", - "EventCode": "0x98", - "EventName": "UNC_M2P_TxR_VERT_NACK0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", - "EventCode": "0x99", - "EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", - "EventCode": "0x99", - "EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0", - "EventCode": "0x9a", - "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1", - "EventCode": "0x9a", - "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0", - "EventCode": "0x9a", - "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1", - "EventCode": "0x9a", - "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0", - "EventCode": "0x9a", - "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1", - "EventCode": "0x9a", - "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : IV", - "EventCode": "0x9a", - "EventName": "UNC_M2P_TxR_VERT_STARVED0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", - "EventCode": "0x9b", - "EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1", - "EventCode": "0x9b", - "EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", - "EventCode": "0x9b", - "EventName": "UNC_M2P_TxR_VERT_STARVED1.TGC", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Down and Even", - "EventCode": "0xb0", - "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Down and Odd", - "EventCode": "0xb0", - "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Up and Even", - "EventCode": "0xb0", - "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Up and Odd", - "EventCode": "0xb0", - "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Down and Even", - "EventCode": "0xb4", - "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", - "EventCode": "0xb4", - "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Up and Even", - "EventCode": "0xb4", - "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", - "EventCode": "0xb4", - "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Down and Even", - "EventCode": "0xb1", - "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Down and Odd", - "EventCode": "0xb1", - "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Up and Even", - "EventCode": "0xb1", - "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Up and Odd", - "EventCode": "0xb1", - "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Down and Even", - "EventCode": "0xb2", - "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Down and Odd", - "EventCode": "0xb2", - "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Up and Even", - "EventCode": "0xb2", - "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Up and Odd", - "EventCode": "0xb2", - "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical IV Ring in Use : Down", - "EventCode": "0xb3", - "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.DN", - "PerPkg": "1", - "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical IV Ring in Use : Up", - "EventCode": "0xb3", - "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.UP", - "PerPkg": "1", - "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Down and Even", - "EventCode": "0xb5", - "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", - "EventCode": "0xb5", - "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Up and Even", - "EventCode": "0xb5", - "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", - "EventCode": "0xb5", - "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10", - "EventCode": "0x81", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8", - "EventCode": "0x81", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9", - "EventCode": "0x81", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10", - "EventCode": "0x83", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8", - "EventCode": "0x83", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9", - "EventCode": "0x83", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10", - "EventCode": "0x89", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8", - "EventCode": "0x89", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9", - "EventCode": "0x89", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10", - "EventCode": "0x8B", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8", - "EventCode": "0x8B", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9", - "EventCode": "0x8B", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10", - "EventCode": "0x85", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8", - "EventCode": "0x85", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9", - "EventCode": "0x85", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10", - "EventCode": "0x87", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8", - "EventCode": "0x87", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9", - "EventCode": "0x87", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10", - "EventCode": "0x8D", - "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8", - "EventCode": "0x8D", - "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9", - "EventCode": "0x8D", - "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10", - "EventCode": "0x8F", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8", - "EventCode": "0x8F", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9", - "EventCode": "0x8F", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CBox AD Credits Empty : Requests", - "EventCode": "0x22", - "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ", - "PerPkg": "1", - "PublicDescription": "CBox AD Credits Empty : Requests : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CBox AD Credits Empty : Snoops", - "EventCode": "0x22", - "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP", - "PerPkg": "1", - "PublicDescription": "CBox AD Credits Empty : Snoops : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CBox AD Credits Empty : VNA Messages", - "EventCode": "0x22", - "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA", - "PerPkg": "1", - "PublicDescription": "CBox AD Credits Empty : VNA Messages : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CBox AD Credits Empty : Writebacks", - "EventCode": "0x22", - "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB", - "PerPkg": "1", - "PublicDescription": "CBox AD Credits Empty : Writebacks : No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Clockticks of the mesh to UPI (M3UPI)", - "EventCode": "0x01", - "EventName": "UNC_M3UPI_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Clockticks of the mesh to UPI (M3UPI) : Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Clockticks", - "EventCode": "0xc0", - "EventName": "UNC_M3UPI_CMS_CLOCKTICKS", - "PerPkg": "1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "D2C Sent", - "EventCode": "0x2B", - "EventName": "UNC_M3UPI_D2C_SENT", - "PerPkg": "1", - "PublicDescription": "D2C Sent : Count cases BL sends direct to core", - "Unit": "M3UPI" - }, - { - "BriefDescription": "D2U Sent", - "EventCode": "0x2A", - "EventName": "UNC_M3UPI_D2U_SENT", - "PerPkg": "1", - "PublicDescription": "D2U Sent : Cases where SMI3 sends D2U command", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Distress signal asserted : DPT Local", - "EventCode": "0xAF", - "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_LOCAL", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Distress signal asserted : DPT Remote", - "EventCode": "0xAF", - "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_NONLOCAL", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Distress signal asserted : DPT Stalled - IV", - "EventCode": "0xAF", - "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_STALL_IV", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit", - "EventCode": "0xAF", - "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_STALL_NOCRD", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Distress signal asserted : Horizontal", - "EventCode": "0xAF", - "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.HORZ", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Distress signal asserted : PMM Local", - "EventCode": "0xAF", - "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.PMM_LOCAL", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : PMM Local : Counts the number of cycles either the local or incoming distress signals are asserted. : If the CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Distress signal asserted : PMM Remote", - "EventCode": "0xAF", - "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.PMM_NONLOCAL", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : PMM Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : If another CHA TOR has too many PMM transactions, this signal will throttle outgoing MS2IDI traffic", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Distress signal asserted : Vertical", - "EventCode": "0xAF", - "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.VERT", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements : Down", - "EventCode": "0xBA", - "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN", - "PerPkg": "1", - "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements : Up", - "EventCode": "0xBA", - "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP", - "PerPkg": "1", - "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Left and Even", - "EventCode": "0xB6", - "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", - "EventCode": "0xB6", - "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Right and Even", - "EventCode": "0xB6", - "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", - "EventCode": "0xB6", - "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Even", - "EventCode": "0xBB", - "EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", - "EventCode": "0xBB", - "EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Even", - "EventCode": "0xBB", - "EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", - "EventCode": "0xBB", - "EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Even", - "EventCode": "0xB7", - "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", - "EventCode": "0xB7", - "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Even", - "EventCode": "0xB7", - "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", - "EventCode": "0xB7", - "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Left and Even", - "EventCode": "0xB8", - "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", - "EventCode": "0xB8", - "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Right and Even", - "EventCode": "0xB8", - "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", - "EventCode": "0xB8", - "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal IV Ring in Use : Left", - "EventCode": "0xB9", - "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT", - "PerPkg": "1", - "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal IV Ring in Use : Right", - "EventCode": "0xB9", - "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT", - "PerPkg": "1", - "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO1_NCB", - "PerPkg": "1", - "PublicDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the same ring destination. (1 VN0 credit only) : No vn0 and vna credits available to send to M2", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "M2 BL Credits Empty : IIO2", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB", - "PerPkg": "1", - "PublicDescription": "M2 BL Credits Empty : IIO2 : No vn0 and vna credits available to send to M2", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "M2 BL Credits Empty : IIO3", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB", - "PerPkg": "1", - "PublicDescription": "M2 BL Credits Empty : IIO3 : No vn0 and vna credits available to send to M2", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "M2 BL Credits Empty : IIO4", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB", - "PerPkg": "1", - "PublicDescription": "M2 BL Credits Empty : IIO4 : No vn0 and vna credits available to send to M2", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "M2 BL Credits Empty : IIO5", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB", - "PerPkg": "1", - "PublicDescription": "M2 BL Credits Empty : IIO5 : No vn0 and vna credits available to send to M2", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS", - "PerPkg": "1", - "PublicDescription": "M2 BL Credits Empty : All IIO targets for NCS are in single mask. ORs them together : No vn0 and vna credits available to send to M2", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "M2 BL Credits Empty : Selected M2p BL NCS credits", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL", - "PerPkg": "1", - "PublicDescription": "M2 BL Credits Empty : Selected M2p BL NCS credits : No vn0 and vna credits available to send to M2", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "M2 BL Credits Empty : IIO5", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.UBOX_NCB", - "PerPkg": "1", - "PublicDescription": "M2 BL Credits Empty : IIO5 : No vn0 and vna credits available to send to M2", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0", - "EventCode": "0xE6", - "EventName": "UNC_M3UPI_MISC_EXTERNAL.MBE_INST0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1", - "EventCode": "0xE6", - "EventName": "UNC_M3UPI_MISC_EXTERNAL.MBE_INST1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Multi Slot Flit Received : AD - Slot 0", - "EventCode": "0x3E", - "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0", - "PerPkg": "1", - "PublicDescription": "Multi Slot Flit Received : AD - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Multi Slot Flit Received : AD - Slot 1", - "EventCode": "0x3E", - "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1", - "PerPkg": "1", - "PublicDescription": "Multi Slot Flit Received : AD - Slot 1 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Multi Slot Flit Received : AD - Slot 2", - "EventCode": "0x3E", - "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2", - "PerPkg": "1", - "PublicDescription": "Multi Slot Flit Received : AD - Slot 2 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Multi Slot Flit Received : AK - Slot 0", - "EventCode": "0x3E", - "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0", - "PerPkg": "1", - "PublicDescription": "Multi Slot Flit Received : AK - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Multi Slot Flit Received : AK - Slot 2", - "EventCode": "0x3E", - "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2", - "PerPkg": "1", - "PublicDescription": "Multi Slot Flit Received : AK - Slot 2 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Multi Slot Flit Received : BL - Slot 0", - "EventCode": "0x3E", - "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0", - "PerPkg": "1", - "PublicDescription": "Multi Slot Flit Received : BL - Slot 0 : Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD", - "EventCode": "0xAC", - "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK", - "EventCode": "0xAC", - "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL", - "EventCode": "0xAC", - "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV", - "EventCode": "0xAC", - "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : AD", - "EventCode": "0xAA", - "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core", - "EventCode": "0xAA", - "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.", - "EventCode": "0xAA", - "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AKC", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core", - "EventCode": "0xAA", - "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.", - "EventCode": "0xAA", - "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : AD", - "EventCode": "0xAD", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : AK", - "EventCode": "0xAD", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1", - "EventCode": "0xAD", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : BL", - "EventCode": "0xAD", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : IV", - "EventCode": "0xAD", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : AD", - "EventCode": "0xAB", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core", - "EventCode": "0xAB", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring", - "EventCode": "0xAB", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AKC", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core", - "EventCode": "0xAB", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.", - "EventCode": "0xAB", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Source Throttle", - "EventCode": "0xae", - "EventName": "UNC_M3UPI_RING_SRC_THRTL", - "PerPkg": "1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN0 : REQ on AD", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Lost Arb for VN0 : REQ on AD : VN0 message requested but lost arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN0 : RSP on AD", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Lost Arb for VN0 : RSP on AD : VN0 message requested but lost arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN0 : SNP on AD", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP", - "PerPkg": "1", - "PublicDescription": "Lost Arb for VN0 : SNP on AD : VN0 message requested but lost arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN0 : NCB on BL", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Lost Arb for VN0 : NCB on BL : VN0 message requested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN0 : NCS on BL", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Lost Arb for VN0 : NCS on BL : VN0 message requested but lost arbitration : Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN0 : RSP on BL", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Lost Arb for VN0 : RSP on BL : VN0 message requested but lost arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN0 : WB on BL", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB", - "PerPkg": "1", - "PublicDescription": "Lost Arb for VN0 : WB on BL : VN0 message requested but lost arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN1 : REQ on AD", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Lost Arb for VN1 : REQ on AD : VN1 message requested but lost arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN1 : RSP on AD", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Lost Arb for VN1 : RSP on AD : VN1 message requested but lost arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN1 : SNP on AD", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP", - "PerPkg": "1", - "PublicDescription": "Lost Arb for VN1 : SNP on AD : VN1 message requested but lost arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN1 : NCB on BL", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Lost Arb for VN1 : NCB on BL : VN1 message requested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN1 : NCS on BL", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Lost Arb for VN1 : NCS on BL : VN1 message requested but lost arbitration : Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN1 : RSP on BL", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Lost Arb for VN1 : RSP on BL : VN1 message requested but lost arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN1 : WB on BL", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB", - "PerPkg": "1", - "PublicDescription": "Lost Arb for VN1 : WB on BL : VN1 message requested but lost arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN0", - "PerPkg": "1", - "PublicDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0 : AD and BL messages won arbitration concurrently / in parallel", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN1", - "PerPkg": "1", - "PublicDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1 : AD and BL messages won arbitration concurrently / in parallel", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Arb Miscellaneous : Max Parallel Win", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.ALL_PARALLEL_WIN", - "PerPkg": "1", - "PublicDescription": "Arb Miscellaneous : Max Parallel Win : VN0 and VN1 arbitration sub-pipelines both produced AD and BL winners (maximum possible parallel winners)", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN0", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0", - "PerPkg": "1", - "PublicDescription": "Arb Miscellaneous : No Progress on Pending AD VN0 : Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD VN1", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1", - "PerPkg": "1", - "PublicDescription": "Arb Miscellaneous : No Progress on Pending AD VN1 : Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN0", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0", - "PerPkg": "1", - "PublicDescription": "Arb Miscellaneous : No Progress on Pending BL VN0 : Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL VN1", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1", - "PerPkg": "1", - "PublicDescription": "Arb Miscellaneous : No Progress on Pending BL VN1 : Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.VN01_PARALLEL_WIN", - "PerPkg": "1", - "PublicDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win : VN0 and VN1 arbitration sub-pipelines had parallel winners (at least one AD or BL on each side)", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN0 : REQ on AD", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_REQ", - "PerPkg": "1", - "PublicDescription": "No Credits to Arb for VN0 : REQ on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN0 : RSP on AD", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_RSP", - "PerPkg": "1", - "PublicDescription": "No Credits to Arb for VN0 : RSP on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN0 : SNP on AD", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_SNP", - "PerPkg": "1", - "PublicDescription": "No Credits to Arb for VN0 : SNP on AD : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN0 : NCB on BL", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCB", - "PerPkg": "1", - "PublicDescription": "No Credits to Arb for VN0 : NCB on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN0 : NCS on BL", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCS", - "PerPkg": "1", - "PublicDescription": "No Credits to Arb for VN0 : NCS on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN0 : RSP on BL", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_RSP", - "PerPkg": "1", - "PublicDescription": "No Credits to Arb for VN0 : RSP on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN0 : WB on BL", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_WB", - "PerPkg": "1", - "PublicDescription": "No Credits to Arb for VN0 : WB on BL : VN0 message is blocked from requesting arbitration due to lack of remote UPI credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN1 : REQ on AD", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_REQ", - "PerPkg": "1", - "PublicDescription": "No Credits to Arb for VN1 : REQ on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN1 : RSP on AD", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_RSP", - "PerPkg": "1", - "PublicDescription": "No Credits to Arb for VN1 : RSP on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN1 : SNP on AD", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_SNP", - "PerPkg": "1", - "PublicDescription": "No Credits to Arb for VN1 : SNP on AD : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN1 : NCB on BL", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCB", - "PerPkg": "1", - "PublicDescription": "No Credits to Arb for VN1 : NCB on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN1 : NCS on BL", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCS", - "PerPkg": "1", - "PublicDescription": "No Credits to Arb for VN1 : NCS on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN1 : RSP on BL", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_RSP", - "PerPkg": "1", - "PublicDescription": "No Credits to Arb for VN1 : RSP on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN1 : WB on BL", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_WB", - "PerPkg": "1", - "PublicDescription": "No Credits to Arb for VN1 : WB on BL : VN1 message is blocked from requesting arbitration due to lack of remote UPI credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN0 : REQ on AD", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Can't Arb for VN0 : REQ on AD : VN0 message was not able to request arbitration while some other message won arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN0 : RSP on AD", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Can't Arb for VN0 : RSP on AD : VN0 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN0 : SNP on AD", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_SNP", - "PerPkg": "1", - "PublicDescription": "Can't Arb for VN0 : SNP on AD : VN0 message was not able to request arbitration while some other message won arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN0 : NCB on BL", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Can't Arb for VN0 : NCB on BL : VN0 message was not able to request arbitration while some other message won arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN0 : NCS on BL", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Can't Arb for VN0 : NCS on BL : VN0 message was not able to request arbitration while some other message won arbitration : Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN0 : RSP on BL", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Can't Arb for VN0 : RSP on BL : VN0 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN0 : WB on BL", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_WB", - "PerPkg": "1", - "PublicDescription": "Can't Arb for VN0 : WB on BL : VN0 message was not able to request arbitration while some other message won arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN1 : REQ on AD", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Can't Arb for VN1 : REQ on AD : VN1 message was not able to request arbitration while some other message won arbitration : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN1 : RSP on AD", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Can't Arb for VN1 : RSP on AD : VN1 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN1 : SNP on AD", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_SNP", - "PerPkg": "1", - "PublicDescription": "Can't Arb for VN1 : SNP on AD : VN1 message was not able to request arbitration while some other message won arbitration : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN1 : NCB on BL", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Can't Arb for VN1 : NCB on BL : VN1 message was not able to request arbitration while some other message won arbitration : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN1 : NCS on BL", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Can't Arb for VN1 : NCS on BL : VN1 message was not able to request arbitration while some other message won arbitration : Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN1 : RSP on BL", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Can't Arb for VN1 : RSP on BL : VN1 message was not able to request arbitration while some other message won arbitration : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN1 : WB on BL", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_WB", - "PerPkg": "1", - "PublicDescription": "Can't Arb for VN1 : WB on BL : VN1 message was not able to request arbitration while some other message won arbitration : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL Arb", - "EventCode": "0x40", - "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB", - "PerPkg": "1", - "PublicDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL Arb : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to slot 0 of independent flit while bl message is in arbitration", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle", - "EventCode": "0x40", - "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE", - "PerPkg": "1", - "PublicDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to slot 0 of independent flit while pipeline is idle", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 1", - "EventCode": "0x40", - "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT", - "PerPkg": "1", - "PublicDescription": "Ingress Queue Bypasses : AD + BL to Slot 1 : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to flit slot 1 while merging with bl message in same flit", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 2", - "EventCode": "0x40", - "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT", - "PerPkg": "1", - "PublicDescription": "Ingress Queue Bypasses : AD + BL to Slot 2 : Number of times message is bypassed around the Ingress Queue : AD is taking bypass to flit slot 2 while merging with bl message in same flit", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Miscellaneous Credit Events : Any In BGF FIFO", - "EventCode": "0x5F", - "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO", - "PerPkg": "1", - "PublicDescription": "Miscellaneous Credit Events : Any In BGF FIFO : Indication that at least one packet (flit) is in the bgf (fifo only)", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Miscellaneous Credit Events : Any in BGF Path", - "EventCode": "0x5F", - "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH", - "PerPkg": "1", - "PublicDescription": "Miscellaneous Credit Events : Any in BGF Path : Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo)", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Miscellaneous Credit Events", - "EventCode": "0x5F", - "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT1_FOR_D2K", - "PerPkg": "1", - "PublicDescription": "Miscellaneous Credit Events : d2k credit count is less than 1", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Miscellaneous Credit Events", - "EventCode": "0x5F", - "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT2_FOR_D2K", - "PerPkg": "1", - "PublicDescription": "Miscellaneous Credit Events : d2k credit count is less than 2", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Miscellaneous Credit Events : No D2K For Arb", - "EventCode": "0x5F", - "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN0_NO_D2K_FOR_ARB", - "PerPkg": "1", - "PublicDescription": "Miscellaneous Credit Events : No D2K For Arb : VN0 BL RSP message was blocked from arbitration request due to lack of D2K CMP credit", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Miscellaneous Credit Events", - "EventCode": "0x5F", - "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN1_NO_D2K_FOR_ARB", - "PerPkg": "1", - "PublicDescription": "Miscellaneous Credit Events : VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Credit Occupancy : Credits Consumed", - "EventCode": "0x60", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.CONSUMED", - "PerPkg": "1", - "PublicDescription": "Credit Occupancy : Credits Consumed : number of remote vna credits consumed per cycle", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Credit Occupancy : D2K Credits", - "EventCode": "0x60", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD", - "PerPkg": "1", - "PublicDescription": "Credit Occupancy : D2K Credits : D2K completion fifo credit occupancy (credits in use), accumulated across all cycles", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Credit Occupancy : Packets in BGF FIFO", - "EventCode": "0x60", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO", - "PerPkg": "1", - "PublicDescription": "Credit Occupancy : Packets in BGF FIFO : Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Credit Occupancy : Packets in BGF Path", - "EventCode": "0x60", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH", - "PerPkg": "1", - "PublicDescription": "Credit Occupancy : Packets in BGF Path : Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo)", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Credit Occupancy", - "EventCode": "0x60", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO", - "PerPkg": "1", - "PublicDescription": "Credit Occupancy : count of bl messages in pump-1-pending state, in completion fifo only", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Credit Occupancy", - "EventCode": "0x60", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL", - "PerPkg": "1", - "PublicDescription": "Credit Occupancy : count of bl messages in pump-1-pending state, in marker table and in fifo", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Credit Occupancy : Transmit Credits", - "EventCode": "0x60", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD", - "PerPkg": "1", - "PublicDescription": "Credit Occupancy : Transmit Credits : Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Credit Occupancy : VNA In Use", - "EventCode": "0x60", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE", - "PerPkg": "1", - "PublicDescription": "Credit Occupancy : VNA In Use : Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ", - "PerPkg": "1", - "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP", - "PerPkg": "1", - "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP", - "PerPkg": "1", - "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB", - "PerPkg": "1", - "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS", - "PerPkg": "1", - "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP", - "PerPkg": "1", - "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB", - "PerPkg": "1", - "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL : Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ", - "PerPkg": "1", - "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : REQ on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP", - "PerPkg": "1", - "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP", - "PerPkg": "1", - "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : SNP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB", - "PerPkg": "1", - "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS", - "PerPkg": "1", - "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : NCS on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP", - "PerPkg": "1", - "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : RSP on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB", - "PerPkg": "1", - "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty : WB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Data Flit Not Sent : All", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.ALL", - "PerPkg": "1", - "PublicDescription": "Data Flit Not Sent : All : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but could not be sent for any reason, e.g. low credits, low tsv, stall injection", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Data Flit Not Sent : No BGF Credits", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_BGF", - "PerPkg": "1", - "PublicDescription": "Data Flit Not Sent : No BGF Credits : Data flit is ready for transmission but could not be sent", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Data Flit Not Sent : No TxQ Credits", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_TXQ", - "PerPkg": "1", - "PublicDescription": "Data Flit Not Sent : No TxQ Credits : Data flit is ready for transmission but could not be sent", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Data Flit Not Sent : TSV High", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.TSV_HI", - "PerPkg": "1", - "PublicDescription": "Data Flit Not Sent : TSV High : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but was not sent while tsv high", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Data Flit Not Sent : Cycle valid for Flit", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.VALID_FOR_FLIT", - "PerPkg": "1", - "PublicDescription": "Data Flit Not Sent : Cycle valid for Flit : Data flit is ready for transmission but could not be sent : data flit is ready for transmission but was not sent while cycle is valid for flit transmission", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 0", - "EventCode": "0x57", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT", - "PerPkg": "1", - "PublicDescription": "Generating BL Data Flit Sequence : Wait on Pump 0 : generating bl data flit sequence; waiting for data pump 0", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Generating BL Data Flit Sequence", - "EventCode": "0x57", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT", - "PerPkg": "1", - "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is at capacity (pending table plus completion fifo at limit)", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Generating BL Data Flit Sequence", - "EventCode": "0x57", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY", - "PerPkg": "1", - "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is tracking at least one message", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Generating BL Data Flit Sequence", - "EventCode": "0x57", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL", - "PerPkg": "1", - "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending completion fifo is full", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Generating BL Data Flit Sequence", - "EventCode": "0x57", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0", - "PerPkg": "1", - "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Generating BL Data Flit Sequence", - "EventCode": "0x57", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO", - "PerPkg": "1", - "PublicDescription": "Generating BL Data Flit Sequence : a bl message finished but is in limbo and moved to pump-1-pending logic", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pump 1", - "EventCode": "0x57", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT", - "PerPkg": "1", - "PublicDescription": "Generating BL Data Flit Sequence : Wait on Pump 1 : generating bl data flit sequence; waiting for data pump 1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF", - "PerPkg": "1", - "PublicDescription": ": slot 2 request naturally serviced during hold-off period", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE", - "PerPkg": "1", - "PublicDescription": ": slot 2 request forcibly serviced during service window", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED", - "PerPkg": "1", - "PublicDescription": ": slot 2 request received from link layer while idle (with no slot 2 request active immediately prior)", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN", - "PerPkg": "1", - "PublicDescription": ": slot 2 request withdrawn during hold-off period or service window", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Slotting BL Message Into Header Flit : All", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Slotting BL Message Into Header Flit : Needs Data Flit", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA", - "PerPkg": "1", - "PublicDescription": "Slotting BL Message Into Header Flit : Needs Data Flit : BL message requires data flit sequence", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 0", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT", - "PerPkg": "1", - "PublicDescription": "Slotting BL Message Into Header Flit : Wait on Pump 0 : Waiting for header pump 0", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ", - "PerPkg": "1", - "PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 : Header pump 1 is not required for flit", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE", - "PerPkg": "1", - "PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Bubble : Header pump 1 is not required for flit but flit transmission delayed", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL", - "PerPkg": "1", - "PublicDescription": "Slotting BL Message Into Header Flit : Don't Need Pump 1 - Not Avail : Header pump 1 is not required for flit and not available", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Slotting BL Message Into Header Flit : Wait on Pump 1", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT", - "PerPkg": "1", - "PublicDescription": "Slotting BL Message Into Header Flit : Wait on Pump 1 : Waiting for header pump 1", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 1 : Accumulate", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM", - "PerPkg": "1", - "PublicDescription": "Flit Gen - Header 1 : Accumulate : Events related to Header Flit Generation - Set 1 : Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 1 : Accumulate Ready", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ", - "PerPkg": "1", - "PublicDescription": "Flit Gen - Header 1 : Accumulate Ready : Events related to Header Flit Generation - Set 1 : header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 1 : Accumulate Wasted", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED", - "PerPkg": "1", - "PublicDescription": "Flit Gen - Header 1 : Accumulate Wasted : Events related to Header Flit Generation - Set 1 : Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED", - "PerPkg": "1", - "PublicDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked : Events related to Header Flit Generation - Set 1 : Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 1", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_AFTER", - "PerPkg": "1", - "PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: message was slotted only after run-ahead was over; run-ahead mode definitely wasted", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Message", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_DURING", - "PerPkg": "1", - "PublicDescription": "Flit Gen - Header 1 : Run-Ahead - Message : Events related to Header Flit Generation - Set 1 : run-ahead mode: one message slotted during run-ahead", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 1", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_AFTER", - "PerPkg": "1", - "PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: second message slotted immediately after run-ahead; potential run-ahead success", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 1", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_SENT", - "PerPkg": "1", - "PublicDescription": "Flit Gen - Header 1 : Events related to Header Flit Generation - Set 1 : run-ahead mode: two (or three) message flit sent immediately after run-ahead; complete run-ahead success", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 2 : Parallel Ok", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR", - "PerPkg": "1", - "PublicDescription": "Flit Gen - Header 2 : Parallel Ok : Events related to Header Flit Generation - Set 2 : new header flit construction may proceed in parallel with data flit sequence", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 2 : Parallel Flit Finished", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_FLIT", - "PerPkg": "1", - "PublicDescription": "Flit Gen - Header 2 : Parallel Flit Finished : Events related to Header Flit Generation - Set 2 : header flit finished assembly in parallel with data flit sequence", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 2 : Parallel Message", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_MSG", - "PerPkg": "1", - "PublicDescription": "Flit Gen - Header 2 : Parallel Message : Events related to Header Flit Generation - Set 2 : message is slotted into header flit in parallel with data flit sequence", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL", - "PerPkg": "1", - "PublicDescription": "Flit Gen - Header 2 : Rate-matching Stall : Events related to Header Flit Generation - Set 2 : Rate-matching stall injected", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall - No Message", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG", - "PerPkg": "1", - "PublicDescription": "Flit Gen - Header 2 : Rate-matching Stall - No Message : Events related to Header Flit Generation - Set 2 : Rate matching stall injected, but no additional message slotted during stall cycle", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sent Header Flit : One Message", - "EventCode": "0x54", - "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG", - "PerPkg": "1", - "PublicDescription": "Sent Header Flit : One Message : One message in flit; VNA or non-VNA flit", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sent Header Flit : One Message in non-VNA", - "EventCode": "0x54", - "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG_VNX", - "PerPkg": "1", - "PublicDescription": "Sent Header Flit : One Message in non-VNA : One message in flit; non-VNA flit", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sent Header Flit : Two Messages", - "EventCode": "0x54", - "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.2_MSGS", - "PerPkg": "1", - "PublicDescription": "Sent Header Flit : Two Messages : Two messages in flit; VNA flit", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sent Header Flit : Three Messages", - "EventCode": "0x54", - "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.3_MSGS", - "PerPkg": "1", - "PublicDescription": "Sent Header Flit : Three Messages : Three messages in flit; VNA flit", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sent Header Flit : One Slot Taken", - "EventCode": "0x54", - "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sent Header Flit : Two Slots Taken", - "EventCode": "0x54", - "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_2", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sent Header Flit : All Slots Taken", - "EventCode": "0x54", - "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_3", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Header Not Sent : All", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.ALL", - "PerPkg": "1", - "PublicDescription": "Header Not Sent : All : header flit is ready for transmission but could not be sent : header flit is ready for transmission but could not be sent for any reason, e.g. no credits, low tsv, stall injection", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Header Not Sent : No BGF Credits", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_CRD", - "PerPkg": "1", - "PublicDescription": "Header Not Sent : No BGF Credits : header flit is ready for transmission but could not be sent : No BGF credits available", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Header Not Sent : No BGF Credits + No Extra Message Slotted", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_NO_MSG", - "PerPkg": "1", - "PublicDescription": "Header Not Sent : No BGF Credits + No Extra Message Slotted : header flit is ready for transmission but could not be sent : No BGF credits available; no additional message slotted into flit", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Header Not Sent : No TxQ Credits", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_CRD", - "PerPkg": "1", - "PublicDescription": "Header Not Sent : No TxQ Credits : header flit is ready for transmission but could not be sent : No TxQ credits available", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Header Not Sent : No TxQ Credits + No Extra Message Slotted", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_NO_MSG", - "PerPkg": "1", - "PublicDescription": "Header Not Sent : No TxQ Credits + No Extra Message Slotted : header flit is ready for transmission but could not be sent : No TxQ credits available; no additional message slotted into flit", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Header Not Sent : TSV High", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.TSV_HI", - "PerPkg": "1", - "PublicDescription": "Header Not Sent : TSV High : header flit is ready for transmission but could not be sent : header flit is ready for transmission but was not sent while tsv high", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Header Not Sent : Cycle valid for Flit", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.VALID_FOR_FLIT", - "PerPkg": "1", - "PublicDescription": "Header Not Sent : Cycle valid for Flit : header flit is ready for transmission but could not be sent : header flit is ready for transmission but was not sent while cycle is valid for flit transmission", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Message Held : Can't Slot AD", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD", - "PerPkg": "1", - "PublicDescription": "Message Held : Can't Slot AD : some AD message could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1})", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Message Held : Can't Slot BL", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL", - "PerPkg": "1", - "PublicDescription": "Message Held : Can't Slot BL : some BL message could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1})", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Message Held : Parallel Attempt", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT", - "PerPkg": "1", - "PublicDescription": "Message Held : Parallel Attempt : ad and bl messages attempted to slot into the same flit in parallel", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Message Held : Parallel Success", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS", - "PerPkg": "1", - "PublicDescription": "Message Held : Parallel Success : ad and bl messages were actually slotted into the same flit in paralle", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Message Held : VN0", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_HELD.VN0", - "PerPkg": "1", - "PublicDescription": "Message Held : VN0 : vn0 message(s) that couldn't be slotted into last vn0 flit are held in slotting stage while processing vn1 flit", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Message Held : VN1", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_HELD.VN1", - "PerPkg": "1", - "PublicDescription": "Message Held : VN1 : vn1 message(s) that couldn't be slotted into last vn1 flit are held in slotting stage while processing vn0 flit", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : REQ on AD", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ", - "PerPkg": "1", - "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : REQ on AD : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on AD", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP", - "PerPkg": "1", - "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on AD : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : SNP on AD", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP", - "PerPkg": "1", - "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : SNP on AD : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCB on BL", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB", - "PerPkg": "1", - "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCB on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCS on BL", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS", - "PerPkg": "1", - "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCS on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on BL", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP", - "PerPkg": "1", - "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : WB on BL", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB", - "PerPkg": "1", - "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : WB on BL : Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : REQ on AD", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ", - "PerPkg": "1", - "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : REQ on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on AD", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP", - "PerPkg": "1", - "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : SNP on AD", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP", - "PerPkg": "1", - "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : SNP on AD : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCB on BL", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB", - "PerPkg": "1", - "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCS on BL", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS", - "PerPkg": "1", - "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCS on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on BL", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP", - "PerPkg": "1", - "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : WB on BL", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB", - "PerPkg": "1", - "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : WB on BL : Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : REQ on AD", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ", - "PerPkg": "1", - "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : REQ on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on AD", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP", - "PerPkg": "1", - "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : SNP on AD", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP", - "PerPkg": "1", - "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : SNP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCB on BL", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB", - "PerPkg": "1", - "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCS on BL", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS", - "PerPkg": "1", - "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NCS on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on BL", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP", - "PerPkg": "1", - "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RSP on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : WB on BL", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB", - "PerPkg": "1", - "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : WB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : REQ on AD", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ", - "PerPkg": "1", - "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : REQ on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on AD", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP", - "PerPkg": "1", - "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : SNP on AD", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP", - "PerPkg": "1", - "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : SNP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCB on BL", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB", - "PerPkg": "1", - "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCS on BL", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS", - "PerPkg": "1", - "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NCS on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on BL", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP", - "PerPkg": "1", - "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RSP on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : WB on BL", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB", - "PerPkg": "1", - "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : WB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message can't slot into flit : REQ on AD", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ", - "PerPkg": "1", - "PublicDescription": "VN0 message can't slot into flit : REQ on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message can't slot into flit : RSP on AD", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP", - "PerPkg": "1", - "PublicDescription": "VN0 message can't slot into flit : RSP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message can't slot into flit : SNP on AD", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP", - "PerPkg": "1", - "PublicDescription": "VN0 message can't slot into flit : SNP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message can't slot into flit : NCB on BL", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB", - "PerPkg": "1", - "PublicDescription": "VN0 message can't slot into flit : NCB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message can't slot into flit : NCS on BL", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS", - "PerPkg": "1", - "PublicDescription": "VN0 message can't slot into flit : NCS on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message can't slot into flit : RSP on BL", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP", - "PerPkg": "1", - "PublicDescription": "VN0 message can't slot into flit : RSP on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message can't slot into flit : WB on BL", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB", - "PerPkg": "1", - "PublicDescription": "VN0 message can't slot into flit : WB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message can't slot into flit : REQ on AD", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ", - "PerPkg": "1", - "PublicDescription": "VN1 message can't slot into flit : REQ on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message can't slot into flit : RSP on AD", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP", - "PerPkg": "1", - "PublicDescription": "VN1 message can't slot into flit : RSP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message can't slot into flit : SNP on AD", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP", - "PerPkg": "1", - "PublicDescription": "VN1 message can't slot into flit : SNP on AD : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message can't slot into flit : NCB on BL", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB", - "PerPkg": "1", - "PublicDescription": "VN1 message can't slot into flit : NCB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message can't slot into flit : NCS on BL", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS", - "PerPkg": "1", - "PublicDescription": "VN1 message can't slot into flit : NCS on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message can't slot into flit : RSP on BL", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP", - "PerPkg": "1", - "PublicDescription": "VN1 message can't slot into flit : RSP on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message can't slot into flit : WB on BL", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB", - "PerPkg": "1", - "PublicDescription": "VN1 message can't slot into flit : WB on BL : Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Remote VNA Credits : Any In Use", - "EventCode": "0x5A", - "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE", - "PerPkg": "1", - "PublicDescription": "Remote VNA Credits : Any In Use : At least one remote vna credit is in use", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Remote VNA Credits : Corrected", - "EventCode": "0x5A", - "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED", - "PerPkg": "1", - "PublicDescription": "Remote VNA Credits : Corrected : Number of remote vna credits corrected (local return) per cycle", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Remote VNA Credits : Level < 1", - "EventCode": "0x5A", - "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1", - "PerPkg": "1", - "PublicDescription": "Remote VNA Credits : Level < 1 : Remote vna credit level is less than 1 (i.e. no vna credits available)", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Remote VNA Credits : Level < 10", - "EventCode": "0x5A", - "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT10", - "PerPkg": "1", - "PublicDescription": "Remote VNA Credits : Level < 10 : remote vna credit level is less than 10; parallel vn0/vn1 arb not possible", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Remote VNA Credits : Level < 4", - "EventCode": "0x5A", - "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4", - "PerPkg": "1", - "PublicDescription": "Remote VNA Credits : Level < 4 : Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Remote VNA Credits : Level < 5", - "EventCode": "0x5A", - "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5", - "PerPkg": "1", - "PublicDescription": "Remote VNA Credits : Level < 5 : Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5", - "PerPkg": "1", - "PublicDescription": ": remote vna credit count was less than 5 and allocation to ad or bl messages was required", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10", - "PerPkg": "1", - "PublicDescription": ": remote vna credit count was less than 10 and allocation to vn0 or vn1 was required", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD", - "PerPkg": "1", - "PublicDescription": ": on vn0, remote vna credits were allocated only to ad messages, not to bl", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL", - "PerPkg": "1", - "PublicDescription": ": on vn0, remote vna credits were allocated only to bl messages, not to ad", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY", - "PerPkg": "1", - "PublicDescription": ": remote vna credits were allocated only to vn0, not to vn1", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD", - "PerPkg": "1", - "PublicDescription": ": on vn1, remote vna credits were allocated only to ad messages, not to bl", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL", - "PerPkg": "1", - "PublicDescription": ": on vn1, remote vna credits were allocated only to bl messages, not to ad", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY", - "PerPkg": "1", - "PublicDescription": ": remote vna credits were allocated only to vn1, not to vn0", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - All", - "EventCode": "0xE5", - "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Credited", - "EventCode": "0xE5", - "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", - "EventCode": "0xE5", - "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - All", - "EventCode": "0xE5", - "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Credited", - "EventCode": "0xE5", - "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", - "EventCode": "0xE5", - "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AD - All", - "EventCode": "0xE2", - "EventName": "UNC_M3UPI_RxR_BYPASS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AD - Credited", - "EventCode": "0xE2", - "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", - "EventCode": "0xE2", - "EventName": "UNC_M3UPI_RxR_BYPASS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AK", - "EventCode": "0xE2", - "EventName": "UNC_M3UPI_RxR_BYPASS.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", - "EventCode": "0xE2", - "EventName": "UNC_M3UPI_RxR_BYPASS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Bypass : BL - All", - "EventCode": "0xE2", - "EventName": "UNC_M3UPI_RxR_BYPASS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Bypass : BL - Credited", - "EventCode": "0xE2", - "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", - "EventCode": "0xE2", - "EventName": "UNC_M3UPI_RxR_BYPASS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Bypass : IV", - "EventCode": "0xE2", - "EventName": "UNC_M3UPI_RxR_BYPASS.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - All", - "EventCode": "0xE3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Credited", - "EventCode": "0xE3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", - "EventCode": "0xE3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation : AK", - "EventCode": "0xE3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - All", - "EventCode": "0xE3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Credited", - "EventCode": "0xE3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", - "EventCode": "0xE3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation : IFV - Credited", - "EventCode": "0xE3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation : IV", - "EventCode": "0xE3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation", - "EventCode": "0xe4", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED_1", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AD - All", - "EventCode": "0xE1", - "EventName": "UNC_M3UPI_RxR_INSERTS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AD - Credited", - "EventCode": "0xE1", - "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited", - "EventCode": "0xE1", - "EventName": "UNC_M3UPI_RxR_INSERTS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AK", - "EventCode": "0xE1", - "EventName": "UNC_M3UPI_RxR_INSERTS.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited", - "EventCode": "0xE1", - "EventName": "UNC_M3UPI_RxR_INSERTS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Allocations : BL - All", - "EventCode": "0xE1", - "EventName": "UNC_M3UPI_RxR_INSERTS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Allocations : BL - Credited", - "EventCode": "0xE1", - "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited", - "EventCode": "0xE1", - "EventName": "UNC_M3UPI_RxR_INSERTS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Allocations : IV", - "EventCode": "0xE1", - "EventName": "UNC_M3UPI_RxR_INSERTS.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AD - All", - "EventCode": "0xE0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", - "EventCode": "0xE0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited", - "EventCode": "0xE0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AK", - "EventCode": "0xE0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited", - "EventCode": "0xE0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : BL - All", - "EventCode": "0xE0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", - "EventCode": "0xE0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited", - "EventCode": "0xE0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : IV", - "EventCode": "0xE0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10", - "EventCode": "0xD1", - "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8", - "EventCode": "0xD1", - "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9", - "EventCode": "0xD1", - "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10", - "EventCode": "0xD3", - "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8", - "EventCode": "0xD3", - "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9", - "EventCode": "0xD3", - "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10", - "EventCode": "0xD5", - "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8", - "EventCode": "0xD5", - "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9", - "EventCode": "0xD5", - "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10", - "EventCode": "0xD7", - "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8", - "EventCode": "0xD7", - "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9", - "EventCode": "0xD7", - "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for AD : VN0 REQ Messages", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ", - "PerPkg": "1", - "PublicDescription": "Failed ARB for AD : VN0 REQ Messages : AD arb but no win; arb request asserted but not won", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for AD : VN0 RSP Messages", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "Failed ARB for AD : VN0 RSP Messages : AD arb but no win; arb request asserted but not won", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for AD : VN0 SNP Messages", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "Failed ARB for AD : VN0 SNP Messages : AD arb but no win; arb request asserted but not won", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for AD : VN0 WB Messages", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB", - "PerPkg": "1", - "PublicDescription": "Failed ARB for AD : VN0 WB Messages : AD arb but no win; arb request asserted but not won", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for AD : VN1 REQ Messages", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ", - "PerPkg": "1", - "PublicDescription": "Failed ARB for AD : VN1 REQ Messages : AD arb but no win; arb request asserted but not won", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for AD : VN1 RSP Messages", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "Failed ARB for AD : VN1 RSP Messages : AD arb but no win; arb request asserted but not won", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for AD : VN1 SNP Messages", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "Failed ARB for AD : VN1 SNP Messages : AD arb but no win; arb request asserted but not won", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for AD : VN1 WB Messages", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB", - "PerPkg": "1", - "PublicDescription": "Failed ARB for AD : VN1 WB Messages : AD arb but no win; arb request asserted but not won", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD FlowQ Bypass", - "EventCode": "0x2C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0", - "PerPkg": "1", - "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD FlowQ Bypass", - "EventCode": "0x2C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1", - "PerPkg": "1", - "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD FlowQ Bypass", - "EventCode": "0x2C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2", - "PerPkg": "1", - "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD FlowQ Bypass", - "EventCode": "0x2C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP", - "PerPkg": "1", - "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Not Empty : VN0 REQ Messages", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ", - "PerPkg": "1", - "PublicDescription": "AD Flow Q Not Empty : VN0 REQ Messages : Number of cycles the AD Egress queue is Not Empty", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Not Empty : VN0 RSP Messages", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "AD Flow Q Not Empty : VN0 RSP Messages : Number of cycles the AD Egress queue is Not Empty", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Not Empty : VN0 SNP Messages", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "AD Flow Q Not Empty : VN0 SNP Messages : Number of cycles the AD Egress queue is Not Empty", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Not Empty : VN0 WB Messages", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB", - "PerPkg": "1", - "PublicDescription": "AD Flow Q Not Empty : VN0 WB Messages : Number of cycles the AD Egress queue is Not Empty", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Not Empty : VN1 REQ Messages", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ", - "PerPkg": "1", - "PublicDescription": "AD Flow Q Not Empty : VN1 REQ Messages : Number of cycles the AD Egress queue is Not Empty", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Not Empty : VN1 RSP Messages", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "AD Flow Q Not Empty : VN1 RSP Messages : Number of cycles the AD Egress queue is Not Empty", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Not Empty : VN1 SNP Messages", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "AD Flow Q Not Empty : VN1 SNP Messages : Number of cycles the AD Egress queue is Not Empty", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Not Empty : VN1 WB Messages", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB", - "PerPkg": "1", - "PublicDescription": "AD Flow Q Not Empty : VN1 WB Messages : Number of cycles the AD Egress queue is Not Empty", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Inserts : VN0 REQ Messages", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ", - "PerPkg": "1", - "PublicDescription": "AD Flow Q Inserts : VN0 REQ Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Inserts : VN0 RSP Messages", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "AD Flow Q Inserts : VN0 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Inserts : VN0 SNP Messages", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "AD Flow Q Inserts : VN0 SNP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Inserts : VN0 WB Messages", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB", - "PerPkg": "1", - "PublicDescription": "AD Flow Q Inserts : VN0 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Inserts : VN1 REQ Messages", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ", - "PerPkg": "1", - "PublicDescription": "AD Flow Q Inserts : VN1 REQ Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Inserts : VN1 RSP Messages", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "AD Flow Q Inserts : VN1 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Inserts : VN1 SNP Messages", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "AD Flow Q Inserts : VN1 SNP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Occupancy : VN0 REQ Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Occupancy : VN0 RSP Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Occupancy : VN0 SNP Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Occupancy : VN0 WB Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Occupancy : VN1 REQ Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Occupancy : VN1 RSP Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Occupancy : VN1 SNP Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AK Flow Q Inserts", - "EventCode": "0x2F", - "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS", - "PerPkg": "1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AK Flow Q Occupancy", - "EventCode": "0x1E", - "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY", - "PerPkg": "1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL : VN0 NCB Messages", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB", - "PerPkg": "1", - "PublicDescription": "Failed ARB for BL : VN0 NCB Messages : BL arb but no win; arb request asserted but not won", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL : VN0 NCS Messages", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS", - "PerPkg": "1", - "PublicDescription": "Failed ARB for BL : VN0 NCS Messages : BL arb but no win; arb request asserted but not won", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL : VN0 RSP Messages", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "Failed ARB for BL : VN0 RSP Messages : BL arb but no win; arb request asserted but not won", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL : VN0 WB Messages", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB", - "PerPkg": "1", - "PublicDescription": "Failed ARB for BL : VN0 WB Messages : BL arb but no win; arb request asserted but not won", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL : VN1 NCS Messages", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB", - "PerPkg": "1", - "PublicDescription": "Failed ARB for BL : VN1 NCS Messages : BL arb but no win; arb request asserted but not won", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL : VN1 NCB Messages", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS", - "PerPkg": "1", - "PublicDescription": "Failed ARB for BL : VN1 NCB Messages : BL arb but no win; arb request asserted but not won", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL : VN1 RSP Messages", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "Failed ARB for BL : VN1 RSP Messages : BL arb but no win; arb request asserted but not won", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL : VN1 WB Messages", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB", - "PerPkg": "1", - "PublicDescription": "Failed ARB for BL : VN1 WB Messages : BL arb but no win; arb request asserted but not won", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Not Empty : VN0 REQ Messages", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ", - "PerPkg": "1", - "PublicDescription": "BL Flow Q Not Empty : VN0 REQ Messages : Number of cycles the BL Egress queue is Not Empty", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Not Empty : VN0 RSP Messages", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "BL Flow Q Not Empty : VN0 RSP Messages : Number of cycles the BL Egress queue is Not Empty", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Not Empty : VN0 SNP Messages", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "BL Flow Q Not Empty : VN0 SNP Messages : Number of cycles the BL Egress queue is Not Empty", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Not Empty : VN0 WB Messages", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB", - "PerPkg": "1", - "PublicDescription": "BL Flow Q Not Empty : VN0 WB Messages : Number of cycles the BL Egress queue is Not Empty", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Not Empty : VN1 REQ Messages", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ", - "PerPkg": "1", - "PublicDescription": "BL Flow Q Not Empty : VN1 REQ Messages : Number of cycles the BL Egress queue is Not Empty", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Not Empty : VN1 RSP Messages", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "BL Flow Q Not Empty : VN1 RSP Messages : Number of cycles the BL Egress queue is Not Empty", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Not Empty : VN1 SNP Messages", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "BL Flow Q Not Empty : VN1 SNP Messages : Number of cycles the BL Egress queue is Not Empty", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Not Empty : VN1 WB Messages", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB", - "PerPkg": "1", - "PublicDescription": "BL Flow Q Not Empty : VN1 WB Messages : Number of cycles the BL Egress queue is Not Empty", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Inserts : VN0 RSP Messages", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB", - "PerPkg": "1", - "PublicDescription": "BL Flow Q Inserts : VN0 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Inserts : VN0 WB Messages", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS", - "PerPkg": "1", - "PublicDescription": "BL Flow Q Inserts : VN0 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Inserts : VN0 NCS Messages", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "BL Flow Q Inserts : VN0 NCS Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Inserts : VN0 NCB Messages", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB", - "PerPkg": "1", - "PublicDescription": "BL Flow Q Inserts : VN0 NCB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Inserts : VN1 RSP Messages", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB", - "PerPkg": "1", - "PublicDescription": "BL Flow Q Inserts : VN1 RSP Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Inserts : VN1 WB Messages", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS", - "PerPkg": "1", - "PublicDescription": "BL Flow Q Inserts : VN1 WB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Inserts : VN1_NCB Messages", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "BL Flow Q Inserts : VN1_NCB Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Inserts : VN1_NCS Messages", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB", - "PerPkg": "1", - "PublicDescription": "BL Flow Q Inserts : VN1_NCS Messages : Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy : VN0 NCS Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy : VN1_NCB Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages", - "EventCode": "0x1F", - "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_LOCAL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages", - "EventCode": "0x1F", - "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_THROUGH", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages", - "EventCode": "0x1F", - "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_WRPULL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages", - "EventCode": "0x1F", - "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_LOCAL", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages", - "EventCode": "0x1F", - "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_THROUGH", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages", - "EventCode": "0x1F", - "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_WRPULL", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : AD - All", - "EventCode": "0xA6", - "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", - "EventCode": "0xA6", - "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", - "EventCode": "0xA6", - "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : BL - All", - "EventCode": "0xA6", - "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", - "EventCode": "0xA6", - "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", - "EventCode": "0xA6", - "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AD - All", - "EventCode": "0xA7", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", - "EventCode": "0xA7", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", - "EventCode": "0xA7", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AK", - "EventCode": "0xA7", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited", - "EventCode": "0xA7", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : BL - All", - "EventCode": "0xA7", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", - "EventCode": "0xA7", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", - "EventCode": "0xA7", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : IV", - "EventCode": "0xA7", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All", - "EventCode": "0xA2", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited", - "EventCode": "0xA2", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited", - "EventCode": "0xA2", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK", - "EventCode": "0xA2", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited", - "EventCode": "0xA2", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All", - "EventCode": "0xA2", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited", - "EventCode": "0xA2", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited", - "EventCode": "0xA2", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV", - "EventCode": "0xA2", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All", - "EventCode": "0xA3", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited", - "EventCode": "0xA3", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited", - "EventCode": "0xA3", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK", - "EventCode": "0xA3", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited", - "EventCode": "0xA3", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All", - "EventCode": "0xA3", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited", - "EventCode": "0xA3", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited", - "EventCode": "0xA3", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV", - "EventCode": "0xA3", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", - "EventCode": "0xA1", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited", - "EventCode": "0xA1", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited", - "EventCode": "0xA1", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AK", - "EventCode": "0xA1", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited", - "EventCode": "0xA1", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", - "EventCode": "0xA1", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited", - "EventCode": "0xA1", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited", - "EventCode": "0xA1", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : IV", - "EventCode": "0xA1", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", - "EventCode": "0xA4", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", - "EventCode": "0xA4", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited", - "EventCode": "0xA4", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AK", - "EventCode": "0xA4", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited", - "EventCode": "0xA4", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", - "EventCode": "0xA4", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", - "EventCode": "0xA4", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited", - "EventCode": "0xA4", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : IV", - "EventCode": "0xA4", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", - "EventCode": "0xA0", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited", - "EventCode": "0xA0", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited", - "EventCode": "0xA0", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AK", - "EventCode": "0xA0", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited", - "EventCode": "0xA0", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", - "EventCode": "0xA0", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited", - "EventCode": "0xA0", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited", - "EventCode": "0xA0", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : IV", - "EventCode": "0xA0", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All", - "EventCode": "0xA5", - "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited", - "EventCode": "0xA5", - "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK", - "EventCode": "0xA5", - "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited", - "EventCode": "0xA5", - "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All", - "EventCode": "0xA5", - "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited", - "EventCode": "0xA5", - "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV", - "EventCode": "0xA5", - "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", - "EventCode": "0x9D", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", - "EventCode": "0x9D", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", - "EventCode": "0x9D", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", - "EventCode": "0x9D", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", - "EventCode": "0x9D", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", - "EventCode": "0x9D", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", - "EventCode": "0x9D", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", - "EventCode": "0x9E", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS_1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", - "EventCode": "0x9E", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS_1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0", - "EventCode": "0x95", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1", - "EventCode": "0x95", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0", - "EventCode": "0x97", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1", - "EventCode": "0x97", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : IV", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", - "EventCode": "0x99", - "EventName": "UNC_M3UPI_TxR_VERT_NACK1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", - "EventCode": "0x99", - "EventName": "UNC_M3UPI_TxR_VERT_NACK1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : IV", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", - "EventCode": "0x9B", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1", - "EventCode": "0x9B", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", - "EventCode": "0x9B", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.TGC", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 AD Credits Empty : VN0 REQ Messages", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ", - "PerPkg": "1", - "PublicDescription": "UPI0 AD Credits Empty : VN0 REQ Messages : No credits available to send to UPIs on the AD Ring", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 AD Credits Empty : VN0 RSP Messages", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "UPI0 AD Credits Empty : VN0 RSP Messages : No credits available to send to UPIs on the AD Ring", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 AD Credits Empty : VN0 SNP Messages", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "UPI0 AD Credits Empty : VN0 SNP Messages : No credits available to send to UPIs on the AD Ring", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 AD Credits Empty : VN1 REQ Messages", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ", - "PerPkg": "1", - "PublicDescription": "UPI0 AD Credits Empty : VN1 REQ Messages : No credits available to send to UPIs on the AD Ring", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 AD Credits Empty : VN1 RSP Messages", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "UPI0 AD Credits Empty : VN1 RSP Messages : No credits available to send to UPIs on the AD Ring", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 AD Credits Empty : VN1 SNP Messages", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "UPI0 AD Credits Empty : VN1 SNP Messages : No credits available to send to UPIs on the AD Ring", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 AD Credits Empty : VNA", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA", - "PerPkg": "1", - "PublicDescription": "UPI0 AD Credits Empty : VNA : No credits available to send to UPIs on the AD Ring", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 BL Credits Empty : VN0 RSP Messages", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB", - "PerPkg": "1", - "PublicDescription": "UPI0 BL Credits Empty : VN0 RSP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 BL Credits Empty : VN0 REQ Messages", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "UPI0 BL Credits Empty : VN0 REQ Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 BL Credits Empty : VN0 SNP Messages", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB", - "PerPkg": "1", - "PublicDescription": "UPI0 BL Credits Empty : VN0 SNP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 BL Credits Empty : VN1 RSP Messages", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB", - "PerPkg": "1", - "PublicDescription": "UPI0 BL Credits Empty : VN1 RSP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 BL Credits Empty : VN1 REQ Messages", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "UPI0 BL Credits Empty : VN1 REQ Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 BL Credits Empty : VN1 SNP Messages", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB", - "PerPkg": "1", - "PublicDescription": "UPI0 BL Credits Empty : VN1 SNP Messages : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 BL Credits Empty : VNA", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA", - "PerPkg": "1", - "PublicDescription": "UPI0 BL Credits Empty : VNA : No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "FlowQ Generated Prefetch", - "EventCode": "0x29", - "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN", - "PerPkg": "1", - "PublicDescription": "FlowQ Generated Prefetch : Count cases where FlowQ causes spawn of Prefetch to iMC/SMI3 target", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Down and Even", - "EventCode": "0xB0", - "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Down and Odd", - "EventCode": "0xB0", - "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Up and Even", - "EventCode": "0xB0", - "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Up and Odd", - "EventCode": "0xB0", - "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Down and Even", - "EventCode": "0xB4", - "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", - "EventCode": "0xB4", - "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Up and Even", - "EventCode": "0xB4", - "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", - "EventCode": "0xB4", - "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Down and Even", - "EventCode": "0xB1", - "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Down and Odd", - "EventCode": "0xB1", - "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Up and Even", - "EventCode": "0xB1", - "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Up and Odd", - "EventCode": "0xB1", - "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Down and Even", - "EventCode": "0xB2", - "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Down and Odd", - "EventCode": "0xB2", - "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Up and Even", - "EventCode": "0xB2", - "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Up and Odd", - "EventCode": "0xB2", - "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical IV Ring in Use : Down", - "EventCode": "0xB3", - "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN", - "PerPkg": "1", - "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical IV Ring in Use : Up", - "EventCode": "0xB3", - "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP", - "PerPkg": "1", - "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Down and Even", - "EventCode": "0xB5", - "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", - "EventCode": "0xB5", - "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Up and Even", - "EventCode": "0xB5", - "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", - "EventCode": "0xB5", - "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Credit Used : WB on BL", - "EventCode": "0x5B", - "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB", - "PerPkg": "1", - "PublicDescription": "VN0 Credit Used : WB on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Credit Used : NCB on BL", - "EventCode": "0x5B", - "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS", - "PerPkg": "1", - "PublicDescription": "VN0 Credit Used : NCB on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Credit Used : REQ on AD", - "EventCode": "0x5B", - "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ", - "PerPkg": "1", - "PublicDescription": "VN0 Credit Used : REQ on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Credit Used : RSP on AD", - "EventCode": "0x5B", - "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP", - "PerPkg": "1", - "PublicDescription": "VN0 Credit Used : RSP on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Credit Used : SNP on AD", - "EventCode": "0x5B", - "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP", - "PerPkg": "1", - "PublicDescription": "VN0 Credit Used : SNP on AD : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Credit Used : RSP on BL", - "EventCode": "0x5B", - "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB", - "PerPkg": "1", - "PublicDescription": "VN0 Credit Used : RSP on BL : Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 No Credits : WB on BL", - "EventCode": "0x5D", - "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB", - "PerPkg": "1", - "PublicDescription": "VN0 No Credits : WB on BL : Number of Cycles there were no VN0 Credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 No Credits : NCB on BL", - "EventCode": "0x5D", - "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS", - "PerPkg": "1", - "PublicDescription": "VN0 No Credits : NCB on BL : Number of Cycles there were no VN0 Credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 No Credits : REQ on AD", - "EventCode": "0x5D", - "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ", - "PerPkg": "1", - "PublicDescription": "VN0 No Credits : REQ on AD : Number of Cycles there were no VN0 Credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 No Credits : RSP on AD", - "EventCode": "0x5D", - "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP", - "PerPkg": "1", - "PublicDescription": "VN0 No Credits : RSP on AD : Number of Cycles there were no VN0 Credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 No Credits : SNP on AD", - "EventCode": "0x5D", - "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP", - "PerPkg": "1", - "PublicDescription": "VN0 No Credits : SNP on AD : Number of Cycles there were no VN0 Credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 No Credits : RSP on BL", - "EventCode": "0x5D", - "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB", - "PerPkg": "1", - "PublicDescription": "VN0 No Credits : RSP on BL : Number of Cycles there were no VN0 Credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Credit Used : WB on BL", - "EventCode": "0x5C", - "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB", - "PerPkg": "1", - "PublicDescription": "VN1 Credit Used : WB on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Credit Used : NCB on BL", - "EventCode": "0x5C", - "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS", - "PerPkg": "1", - "PublicDescription": "VN1 Credit Used : NCB on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Credit Used : REQ on AD", - "EventCode": "0x5C", - "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ", - "PerPkg": "1", - "PublicDescription": "VN1 Credit Used : REQ on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Credit Used : RSP on AD", - "EventCode": "0x5C", - "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP", - "PerPkg": "1", - "PublicDescription": "VN1 Credit Used : RSP on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Credit Used : SNP on AD", - "EventCode": "0x5C", - "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP", - "PerPkg": "1", - "PublicDescription": "VN1 Credit Used : SNP on AD : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Credit Used : RSP on BL", - "EventCode": "0x5C", - "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB", - "PerPkg": "1", - "PublicDescription": "VN1 Credit Used : RSP on BL : Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers. : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 No Credits : WB on BL", - "EventCode": "0x5E", - "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB", - "PerPkg": "1", - "PublicDescription": "VN1 No Credits : WB on BL : Number of Cycles there were no VN1 Credits : Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 No Credits : NCB on BL", - "EventCode": "0x5E", - "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS", - "PerPkg": "1", - "PublicDescription": "VN1 No Credits : NCB on BL : Number of Cycles there were no VN1 Credits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 No Credits : REQ on AD", - "EventCode": "0x5E", - "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ", - "PerPkg": "1", - "PublicDescription": "VN1 No Credits : REQ on AD : Number of Cycles there were no VN1 Credits : Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 No Credits : RSP on AD", - "EventCode": "0x5E", - "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP", - "PerPkg": "1", - "PublicDescription": "VN1 No Credits : RSP on AD : Number of Cycles there were no VN1 Credits : Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 No Credits : SNP on AD", - "EventCode": "0x5E", - "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP", - "PerPkg": "1", - "PublicDescription": "VN1 No Credits : SNP on AD : Number of Cycles there were no VN1 Credits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 No Credits : RSP on BL", - "EventCode": "0x5E", - "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB", - "PerPkg": "1", - "PublicDescription": "VN1 No Credits : RSP on BL : Number of Cycles there were no VN1 Credits : Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0", - "EventCode": "0x7E", - "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN0", - "PerPkg": "1", - "UMask": "0x82", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1", - "EventCode": "0x7E", - "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST_VN1", - "PerPkg": "1", - "UMask": "0xa0", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0", - "EventCode": "0x7E", - "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN0", - "PerPkg": "1", - "UMask": "0x81", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1", - "EventCode": "0x7E", - "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST_VN1", - "PerPkg": "1", - "UMask": "0x90", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0", - "EventCode": "0x7E", - "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN0", - "PerPkg": "1", - "UMask": "0x84", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1", - "EventCode": "0x7E", - "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST_VN1", - "PerPkg": "1", - "UMask": "0xc0", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0", - "EventCode": "0x7E", - "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1", - "EventCode": "0x7E", - "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0", - "EventCode": "0x7E", - "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1", - "EventCode": "0x7E", - "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0", - "EventCode": "0x7E", - "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1", - "EventCode": "0x7E", - "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0", - "EventCode": "0x7D", - "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1", - "EventCode": "0x7D", - "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0", - "EventCode": "0x7D", - "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1", - "EventCode": "0x7D", - "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0", - "EventCode": "0x7D", - "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1", - "EventCode": "0x7D", - "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0", - "EventCode": "0x7D", - "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1", - "EventCode": "0x7D", - "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARB", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_XPT_PFTCH.ARB", - "PerPkg": "1", - "PublicDescription": ": xpt prefetch message is making arbitration request", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARRIVED", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_XPT_PFTCH.ARRIVED", - "PerPkg": "1", - "PublicDescription": ": xpt prefetch message arrived in ingress pipeline", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_XPT_PFTCH.BYPASS", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_XPT_PFTCH.BYPASS", - "PerPkg": "1", - "PublicDescription": ": xpt prefetch message took bypass path", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_XPT_PFTCH.FLITTED", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_XPT_PFTCH.FLITTED", - "PerPkg": "1", - "PublicDescription": ": xpt prefetch message was slotted into flit (non bypass)", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_ARB", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_ARB", - "PerPkg": "1", - "PublicDescription": ": xpt prefetch message lost arbitration", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_OLD", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_OLD", - "PerPkg": "1", - "PublicDescription": ": xpt prefetch message was dropped because it became too old", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL", - "PerPkg": "1", - "PublicDescription": ": xpt prefetch message was dropped because it was overwritten by new message while prefetch queue was full", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Number of kfclks", - "EventCode": "0x01", - "EventName": "UNC_UPI_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Number of kfclks : Counts the number of clocks in the UPI LL. This clock runs at 1/8th the GT/s speed of the UPI link. For example, a 8GT/s link will have qfclk or 1GHz. Current products do not support dynamic link speeds, so this frequency is fixed.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Direct packet attempts : D2C", - "EventCode": "0x12", - "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C", - "PerPkg": "1", - "PublicDescription": "Direct packet attempts : D2C : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Direct packet attempts : D2K", - "EventCode": "0x12", - "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K", - "PerPkg": "1", - "PublicDescription": "Direct packet attempts : D2K : Counts the number of DRS packets that we attempted to do direct2core/direct2UPI on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Cycles in L1", - "EventCode": "0x21", - "EventName": "UNC_UPI_L1_POWER_CYCLES", - "PerPkg": "1", - "PublicDescription": "Cycles in L1 : Number of UPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a UPI link. Use edge detect to count the number of instances when the UPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", - "EventCode": "0x14", - "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", - "EventCode": "0x14", - "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", - "EventCode": "0x14", - "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", - "EventCode": "0x14", - "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", - "EventCode": "0x14", - "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED", - "EventCode": "0x16", - "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1", - "EventCode": "0x20", - "EventName": "UNC_UPI_PHY_INIT_CYCLES", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "L1 Req Nack", - "EventCode": "0x23", - "EventName": "UNC_UPI_POWER_L1_NACK", - "PerPkg": "1", - "PublicDescription": "L1 Req Nack : Counts the number of times a link sends/receives a LinkReqNAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx originally requested the power change). A Tx LinkReqNAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).", - "Unit": "UPI LL" - }, - { - "BriefDescription": "L1 Req (same as L1 Ack).", - "EventCode": "0x22", - "EventName": "UNC_UPI_POWER_L1_REQ", - "PerPkg": "1", - "PublicDescription": "L1 Req (same as L1 Ack). : Counts the number of times a link sends/receives a LinkReqAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqAck refers to receiving an Ack (meaning this agent's Tx originally requested the power change). A Tx LinkReqAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", - "EventCode": "0x46", - "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", - "EventCode": "0x46", - "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", - "EventCode": "0x46", - "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", - "EventCode": "0x46", - "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Cycles in L0p", - "EventCode": "0x25", - "EventName": "UNC_UPI_RxL0P_POWER_CYCLES", - "PerPkg": "1", - "PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Cycles in L0", - "EventCode": "0x24", - "EventName": "UNC_UPI_RxL0_POWER_CYCLES", - "PerPkg": "1", - "PublicDescription": "Cycles in L0 : Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass", - "EventCode": "0x05", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", - "PerPkg": "1", - "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0xe", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode", - "EventCode": "0x05", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC", - "PerPkg": "1", - "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x10e", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard", - "EventCode": "0x05", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", - "PerPkg": "1", - "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0xf", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode", - "EventCode": "0x05", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC", - "PerPkg": "1", - "PublicDescription": "Matches on Receive path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x10f", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port : Request", - "EventCode": "0x05", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", - "PerPkg": "1", - "PublicDescription": "Matches on Receive path of a UPI Port : Request : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port : Request, Match Opcode", - "EventCode": "0x05", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC", - "PerPkg": "1", - "PublicDescription": "Matches on Receive path of a UPI Port : Request, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x108", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port : Response - Conflict", - "EventCode": "0x05", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT", - "PerPkg": "1", - "PublicDescription": "Matches on Receive path of a UPI Port : Response - Conflict : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x1aa", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port : Response - Invalid", - "EventCode": "0x05", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI", - "PerPkg": "1", - "PublicDescription": "Matches on Receive path of a UPI Port : Response - Invalid : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x12a", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port : Response - Data", - "EventCode": "0x05", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", - "PerPkg": "1", - "PublicDescription": "Matches on Receive path of a UPI Port : Response - Data : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0xc", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port : Response - Data, Match Opcode", - "EventCode": "0x05", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC", - "PerPkg": "1", - "PublicDescription": "Matches on Receive path of a UPI Port : Response - Data, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x10c", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data", - "EventCode": "0x05", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA", - "PerPkg": "1", - "PublicDescription": "Matches on Receive path of a UPI Port : Response - No Data : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0xa", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port : Response - No Data, Match Opcode", - "EventCode": "0x05", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", - "PerPkg": "1", - "PublicDescription": "Matches on Receive path of a UPI Port : Response - No Data, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x10a", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port : Snoop", - "EventCode": "0x05", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", - "PerPkg": "1", - "PublicDescription": "Matches on Receive path of a UPI Port : Snoop : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x9", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port : Snoop, Match Opcode", - "EventCode": "0x05", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC", - "PerPkg": "1", - "PublicDescription": "Matches on Receive path of a UPI Port : Snoop, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x109", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port : Writeback", - "EventCode": "0x05", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB", - "PerPkg": "1", - "PublicDescription": "Matches on Receive path of a UPI Port : Writeback : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0xd", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port : Writeback, Match Opcode", - "EventCode": "0x05", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC", - "PerPkg": "1", - "PublicDescription": "Matches on Receive path of a UPI Port : Writeback, Match Opcode : Matches on Receive path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x10d", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 0", - "EventCode": "0x31", - "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", - "PerPkg": "1", - "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 0 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 1", - "EventCode": "0x31", - "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", - "PerPkg": "1", - "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 1 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 2", - "EventCode": "0x31", - "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", - "PerPkg": "1", - "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 2 : Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "CRC Errors Detected", - "EventCode": "0x0B", - "EventName": "UNC_UPI_RxL_CRC_ERRORS", - "PerPkg": "1", - "PublicDescription": "CRC Errors Detected : Number of CRC errors detected in the UPI Agent. Each UPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the UPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).", - "Unit": "UPI LL" - }, - { - "BriefDescription": "LLR Requests Sent", - "EventCode": "0x08", - "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT", - "PerPkg": "1", - "PublicDescription": "LLR Requests Sent : Number of LLR Requests were transmitted. This should generally be <= the number of CRC errors detected. If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "VN0 Credit Consumed", - "EventCode": "0x39", - "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0", - "PerPkg": "1", - "PublicDescription": "VN0 Credit Consumed : Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "VN1 Credit Consumed", - "EventCode": "0x3A", - "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1", - "PerPkg": "1", - "PublicDescription": "VN1 Credit Consumed : Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "VNA Credit Consumed", - "EventCode": "0x38", - "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA", - "PerPkg": "1", - "PublicDescription": "VNA Credit Consumed : Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received : All Data", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", - "PerPkg": "1", - "PublicDescription": "Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c).", - "UMask": "0xf", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received : Null FLITs received from any slot", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", - "PerPkg": "1", - "PublicDescription": "Valid Flits Received : Null FLITs received from any slot : Shows legal flit time (hides impact of L0p and L0c).", - "UMask": "0x27", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received : Data", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.DATA", - "PerPkg": "1", - "PublicDescription": "Valid Flits Received : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received : Null FLITs received from any slot", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.IDLE", - "PerPkg": "1", - "PublicDescription": "Valid Flits Received : Null FLITs received from any slot : Shows legal flit time (hides impact of L0p and L0c).", - "UMask": "0x47", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received : LLCRD Not Empty", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.LLCRD", - "PerPkg": "1", - "PublicDescription": "Valid Flits Received : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2", - "UMask": "0x10", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received : LLCTRL", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.LLCTRL", - "PerPkg": "1", - "PublicDescription": "Valid Flits Received : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.", - "UMask": "0x40", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received : All Non Data", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", - "PerPkg": "1", - "PublicDescription": "Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c).", - "UMask": "0x97", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Empty", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.NULL", - "PerPkg": "1", - "PublicDescription": "Valid Flits Received : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.", - "UMask": "0x20", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received : Protocol Header", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.PROTHDR", - "PerPkg": "1", - "PublicDescription": "Valid Flits Received : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)", - "UMask": "0x80", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received : Slot 0", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.SLOT0", - "PerPkg": "1", - "PublicDescription": "Valid Flits Received : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received : Slot 1", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.SLOT1", - "PerPkg": "1", - "PublicDescription": "Valid Flits Received : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received : Slot 2", - "EventCode": "0x03", - "EventName": "UNC_UPI_RxL_FLITS.SLOT2", - "PerPkg": "1", - "PublicDescription": "Valid Flits Received : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Flit Buffer Allocations : Slot 0", - "EventCode": "0x30", - "EventName": "UNC_UPI_RxL_INSERTS.SLOT0", - "PerPkg": "1", - "PublicDescription": "RxQ Flit Buffer Allocations : Slot 0 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Flit Buffer Allocations : Slot 1", - "EventCode": "0x30", - "EventName": "UNC_UPI_RxL_INSERTS.SLOT1", - "PerPkg": "1", - "PublicDescription": "RxQ Flit Buffer Allocations : Slot 1 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Flit Buffer Allocations : Slot 2", - "EventCode": "0x30", - "EventName": "UNC_UPI_RxL_INSERTS.SLOT2", - "PerPkg": "1", - "PublicDescription": "RxQ Flit Buffer Allocations : Slot 2 : Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Occupancy - All Packets : Slot 0", - "EventCode": "0x32", - "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0", - "PerPkg": "1", - "PublicDescription": "RxQ Occupancy - All Packets : Slot 0 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Occupancy - All Packets : Slot 1", - "EventCode": "0x32", - "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1", - "PerPkg": "1", - "PublicDescription": "RxQ Occupancy - All Packets : Slot 1 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Occupancy - All Packets : Slot 2", - "EventCode": "0x32", - "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2", - "PerPkg": "1", - "PublicDescription": "RxQ Occupancy - All Packets : Slot 2 : Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", - "EventCode": "0x33", - "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", - "EventCode": "0x33", - "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", - "EventCode": "0x33", - "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", - "EventCode": "0x33", - "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", - "EventCode": "0x33", - "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", - "EventCode": "0x33", - "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Cycles in L0p", - "EventCode": "0x27", - "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", - "PerPkg": "1", - "PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", - "EventCode": "0x28", - "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", - "EventCode": "0x29", - "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Cycles in L0", - "EventCode": "0x26", - "EventName": "UNC_UPI_TxL0_POWER_CYCLES", - "PerPkg": "1", - "PublicDescription": "Cycles in L0 : Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass", - "EventCode": "0x04", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", - "PerPkg": "1", - "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0xe", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode", - "EventCode": "0x04", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC", - "PerPkg": "1", - "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Bypass, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x10e", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard", - "EventCode": "0x04", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", - "PerPkg": "1", - "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0xf", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode", - "EventCode": "0x04", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC", - "PerPkg": "1", - "PublicDescription": "Matches on Transmit path of a UPI Port : Non-Coherent Standard, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x10f", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port : Request", - "EventCode": "0x04", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", - "PerPkg": "1", - "PublicDescription": "Matches on Transmit path of a UPI Port : Request : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port : Request, Match Opcode", - "EventCode": "0x04", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC", - "PerPkg": "1", - "PublicDescription": "Matches on Transmit path of a UPI Port : Request, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x108", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Conflict", - "EventCode": "0x04", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT", - "PerPkg": "1", - "PublicDescription": "Matches on Transmit path of a UPI Port : Response - Conflict : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x1aa", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Invalid", - "EventCode": "0x04", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI", - "PerPkg": "1", - "PublicDescription": "Matches on Transmit path of a UPI Port : Response - Invalid : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x12a", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data", - "EventCode": "0x04", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", - "PerPkg": "1", - "PublicDescription": "Matches on Transmit path of a UPI Port : Response - Data : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0xc", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port : Response - Data, Match Opcode", - "EventCode": "0x04", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC", - "PerPkg": "1", - "PublicDescription": "Matches on Transmit path of a UPI Port : Response - Data, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x10c", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data", - "EventCode": "0x04", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", - "PerPkg": "1", - "PublicDescription": "Matches on Transmit path of a UPI Port : Response - No Data : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0xa", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode", - "EventCode": "0x04", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", - "PerPkg": "1", - "PublicDescription": "Matches on Transmit path of a UPI Port : Response - No Data, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x10a", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port : Snoop", - "EventCode": "0x04", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", - "PerPkg": "1", - "PublicDescription": "Matches on Transmit path of a UPI Port : Snoop : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x9", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port : Snoop, Match Opcode", - "EventCode": "0x04", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC", - "PerPkg": "1", - "PublicDescription": "Matches on Transmit path of a UPI Port : Snoop, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x109", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port : Writeback", - "EventCode": "0x04", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB", - "PerPkg": "1", - "PublicDescription": "Matches on Transmit path of a UPI Port : Writeback : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0xd", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port : Writeback, Match Opcode", - "EventCode": "0x04", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC", - "PerPkg": "1", - "PublicDescription": "Matches on Transmit path of a UPI Port : Writeback, Match Opcode : Matches on Transmit path of a UPI port.\r\nMatch based on UMask specific bits:\r\nZ: Message Class (3-bit)\r\nY: Message Class Enable\r\nW: Opcode (4-bit)\r\nV: Opcode Enable\r\nU: Local Enable\r\nT: Remote Enable\r\nS: Data Hdr Enable\r\nR: Non-Data Hdr Enable\r\nQ: Dual Slot Hdr Enable\r\nP: Single Slot Hdr Enable\r\nLink Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific opcode match_en cases.\r\nNote: If Message Class is disabled, we expect opcode to also be disabled.", - "UMask": "0x10d", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Tx Flit Buffer Bypassed", - "EventCode": "0x41", - "EventName": "UNC_UPI_TxL_BYPASSED", - "PerPkg": "1", - "PublicDescription": "Tx Flit Buffer Bypassed : Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the UPI Link. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent : All Data", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", - "PerPkg": "1", - "PublicDescription": "Valid Flits Sent : All Data : Shows legal flit time (hides impact of L0p and L0c).", - "UMask": "0xf", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent : Null FLITs transmitted to any slot", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", - "PerPkg": "1", - "PublicDescription": "Valid Flits Sent : Null FLITs transmitted to any slot : Shows legal flit time (hides impact of L0p and L0c).", - "UMask": "0x27", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent : Data", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.DATA", - "PerPkg": "1", - "PublicDescription": "Valid Flits Sent : Data : Shows legal flit time (hides impact of L0p and L0c). : Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent : Idle", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.IDLE", - "PerPkg": "1", - "PublicDescription": "Valid Flits Sent : Idle : Shows legal flit time (hides impact of L0p and L0c).", - "UMask": "0x47", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent : LLCRD Not Empty", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.LLCRD", - "PerPkg": "1", - "PublicDescription": "Valid Flits Sent : LLCRD Not Empty : Shows legal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2", - "UMask": "0x10", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent : LLCTRL", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.LLCTRL", - "PerPkg": "1", - "PublicDescription": "Valid Flits Sent : LLCTRL : Shows legal flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.", - "UMask": "0x40", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent : All Non Data", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", - "PerPkg": "1", - "PublicDescription": "Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c).", - "UMask": "0x97", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.NULL", - "PerPkg": "1", - "PublicDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slot. This can apply to slot 0,1, or 2.", - "UMask": "0x20", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent : Protocol Header", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.PROTHDR", - "PerPkg": "1", - "PublicDescription": "Valid Flits Sent : Protocol Header : Shows legal flit time (hides impact of L0p and L0c). : Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)", - "UMask": "0x80", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent : Slot 0", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.SLOT0", - "PerPkg": "1", - "PublicDescription": "Valid Flits Sent : Slot 0 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determine types of headers to count.", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent : Slot 1", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.SLOT1", - "PerPkg": "1", - "PublicDescription": "Valid Flits Sent : Slot 1 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determine types of headers to count.", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent : Slot 2", - "EventCode": "0x02", - "EventName": "UNC_UPI_TxL_FLITS.SLOT2", - "PerPkg": "1", - "PublicDescription": "Valid Flits Sent : Slot 2 : Shows legal flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determine types of headers to count.", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Tx Flit Buffer Allocations", - "EventCode": "0x40", - "EventName": "UNC_UPI_TxL_INSERTS", - "PerPkg": "1", - "PublicDescription": "Tx Flit Buffer Allocations : Number of allocations into the UPI Tx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Tx Flit Buffer Occupancy", - "EventCode": "0x42", - "EventName": "UNC_UPI_TxL_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Tx Flit Buffer Occupancy : Accumulates the number of flits in the TxQ. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", - "EventCode": "0x45", - "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "VNA Credits Pending Return - Occupancy", - "EventCode": "0x44", - "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "VNA Credits Pending Return - Occupancy : Number of VNA credits in the Rx side that are waitng to be returned back across the link.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", - "EventCode": "0xff", - "EventName": "UNC_U_CLOCKTICKS", - "PerPkg": "1", - "Unit": "UBOX" - }, - { - "BriefDescription": "Message Received : Doorbell", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UBOX" - }, - { - "BriefDescription": "Message Received : Interrupt", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.INT_PRIO", - "PerPkg": "1", - "PublicDescription": "Message Received : Interrupt : Interrupts", - "UMask": "0x10", - "Unit": "UBOX" - }, - { - "BriefDescription": "Message Received : IPI", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", - "PerPkg": "1", - "PublicDescription": "Message Received : IPI : Inter Processor Interrupts", - "UMask": "0x4", - "Unit": "UBOX" - }, - { - "BriefDescription": "Message Received : MSI", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", - "PerPkg": "1", - "PublicDescription": "Message Received : MSI : Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "Message Received : VLW", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", - "PerPkg": "1", - "PublicDescription": "Message Received : VLW : Virtual Logical Wire (legacy) message were received from Uncore.", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "IDI Lock/SplitLock Cycles", - "EventCode": "0x44", - "EventName": "UNC_U_LOCK_CYCLES", - "PerPkg": "1", - "PublicDescription": "IDI Lock/SplitLock Cycles : Number of times an IDI Lock/SplitLock sequence was started", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", - "EventCode": "0x4D", - "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", - "EventCode": "0x4D", - "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB", - "EventCode": "0x4D", - "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS", - "EventCode": "0x4D", - "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", - "EventCode": "0x4D", - "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", - "EventCode": "0x4D", - "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB", - "EventCode": "0x4D", - "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS", - "EventCode": "0x4D", - "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", - "EventCode": "0x4E", - "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", - "EventCode": "0x4E", - "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", - "EventCode": "0x4E", - "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", - "EventCode": "0x4E", - "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", - "EventCode": "0x4E", - "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", - "EventCode": "0x4E", - "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", - "EventCode": "0x4E", - "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", - "EventCode": "0x4E", - "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", - "EventCode": "0x4F", - "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", - "EventCode": "0x4F", - "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK", - "EventCode": "0x45", - "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", - "PerPkg": "1", - "PublicDescription": "Cycles PHOLD Assert to Ack : Assert to ACK : PHOLD cycles.", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", - "EventCode": "0x4C", - "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_RACU_DRNG.RDRAND", - "EventCode": "0x4C", - "EventName": "UNC_U_RACU_DRNG.RDRAND", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_RACU_DRNG.RDSEED", - "EventCode": "0x4C", - "EventName": "UNC_U_RACU_DRNG.RDSEED", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "RACU Request", - "EventCode": "0x46", - "EventName": "UNC_U_RACU_REQUESTS", - "PerPkg": "1", - "PublicDescription": "RACU Request : Number outstanding register requests within message channel tracker", - "Unit": "UBOX" - } -] -- cgit v1.2.3-58-ga151 From c2f38d3b95e600d3a9a7195a2db57f7d47fb0664 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 13 Apr 2023 06:29:41 -0700 Subject: perf vendor events intel: Fix uncore topics for ivybridge Remove 'uncore-other' topic classification, move to cache and interconnect. Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230413132949.3487664-14-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/x86/ivybridge/uncore-cache.json | 50 +++++++-------- .../arch/x86/ivybridge/uncore-interconnect.json | 75 ++++++++++++++++++++++ .../arch/x86/ivybridge/uncore-other.json | 75 ---------------------- 3 files changed, 100 insertions(+), 100 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/ivybridge/uncore-interconnect.json delete mode 100644 tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json index c538557ba4c0..be9a3ed1a940 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json @@ -5,7 +5,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES", "PerPkg": "1", "UMask": "0x86", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.", @@ -13,7 +13,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I", "PerPkg": "1", "UMask": "0x88", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.", @@ -21,7 +21,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M", "PerPkg": "1", "UMask": "0x81", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.", @@ -29,7 +29,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI", "PerPkg": "1", "UMask": "0x8f", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.", @@ -37,7 +37,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES", "PerPkg": "1", "UMask": "0x46", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.", @@ -45,7 +45,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I", "PerPkg": "1", "UMask": "0x48", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.", @@ -53,7 +53,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M", "PerPkg": "1", "UMask": "0x41", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.", @@ -61,7 +61,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI", "PerPkg": "1", "UMask": "0x4f", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.", @@ -69,7 +69,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES", "PerPkg": "1", "UMask": "0x16", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup read request that access cache and found line in I-state.", @@ -77,7 +77,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I", "PerPkg": "1", "UMask": "0x18", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup read request that access cache and found line in M-state.", @@ -85,7 +85,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M", "PerPkg": "1", "UMask": "0x11", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state.", @@ -93,7 +93,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI", "PerPkg": "1", "UMask": "0x1f", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state.", @@ -101,7 +101,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES", "PerPkg": "1", "UMask": "0x26", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup write request that access cache and found line in I-state.", @@ -109,7 +109,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I", "PerPkg": "1", "UMask": "0x28", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup write request that access cache and found line in M-state.", @@ -117,7 +117,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M", "PerPkg": "1", "UMask": "0x21", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state.", @@ -125,7 +125,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI", "PerPkg": "1", "UMask": "0x2f", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.", @@ -133,7 +133,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION", "PerPkg": "1", "UMask": "0x88", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "An external snoop hits a modified line in some processor core.", @@ -141,7 +141,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL", "PerPkg": "1", "UMask": "0x28", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.", @@ -149,7 +149,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", "PerPkg": "1", "UMask": "0x48", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.", @@ -157,7 +157,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION", "PerPkg": "1", "UMask": "0x84", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "An external snoop hits a non-modified line in some processor core.", @@ -165,7 +165,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL", "PerPkg": "1", "UMask": "0x24", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.", @@ -173,7 +173,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", "PerPkg": "1", "UMask": "0x44", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.", @@ -181,7 +181,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", "PerPkg": "1", "UMask": "0x81", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "An external snoop misses in some processor core.", @@ -189,7 +189,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL", "PerPkg": "1", "UMask": "0x21", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.", @@ -197,6 +197,6 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", "PerPkg": "1", "UMask": "0x41", - "Unit": "CBO" + "Unit": "CBOX" } ] diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-interconnect.json new file mode 100644 index 000000000000..c3252c094a9c --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-interconnect.json @@ -0,0 +1,75 @@ +[ + { + "BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.", + "EventCode": "0x83", + "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of requests allocated in Coherency Tracker.", + "EventCode": "0x84", + "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", + "CounterMask": "10", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", + "CounterMask": "1", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts the number of LLC evictions allocated.", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "ARB" + }, + { + "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.", + "EventCode": "0xff", + "EventName": "UNC_CLOCK.SOCKET", + "PerPkg": "1", + "Unit": "ARB" + } +] diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json deleted file mode 100644 index c3252c094a9c..000000000000 --- a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json +++ /dev/null @@ -1,75 +0,0 @@ -[ - { - "BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.", - "EventCode": "0x83", - "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Number of requests allocated in Coherency Tracker.", - "EventCode": "0x84", - "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.", - "EventCode": "0x80", - "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", - "CounterMask": "10", - "EventCode": "0x80", - "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", - "CounterMask": "1", - "EventCode": "0x80", - "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Counts the number of LLC evictions allocated.", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "ARB" - }, - { - "BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "ARB" - }, - { - "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.", - "EventCode": "0xff", - "EventName": "UNC_CLOCK.SOCKET", - "PerPkg": "1", - "Unit": "ARB" - } -] -- cgit v1.2.3-58-ga151 From 14b4c54485bbab73e54c9170b8c9eae3f642edc2 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 13 Apr 2023 06:29:42 -0700 Subject: perf vendor events intel: Fix uncore topics for ivytown Remove 'uncore-other' topic classification, move to cache, interconnect and io. Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Edward Baker Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: http://lore.kernel.org/lkml/20230413132949.3487664-15-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/ivytown/uncore-cache.json | 314 +-- .../arch/x86/ivytown/uncore-interconnect.json | 2025 ++++++++++++++++-- .../pmu-events/arch/x86/ivytown/uncore-io.json | 549 +++++ .../pmu-events/arch/x86/ivytown/uncore-other.json | 2174 -------------------- 4 files changed, 2531 insertions(+), 2531 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/ivytown/uncore-io.json delete mode 100644 tools/perf/pmu-events/arch/x86/ivytown/uncore-other.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-cache.json b/tools/perf/pmu-events/arch/x86/ivytown/uncore-cache.json index 521175881173..8bf2706eb6d5 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-cache.json @@ -3,7 +3,7 @@ "BriefDescription": "Uncore Clocks", "EventName": "UNC_C_CLOCKTICKS", "PerPkg": "1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Counter 0 Occupancy", @@ -11,7 +11,7 @@ "EventName": "UNC_C_COUNTER0_OCCUPANCY", "PerPkg": "1", "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; Any Request", @@ -20,7 +20,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.", "UMask": "0x11", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; Data Read Request", @@ -29,7 +29,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Read transactions", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; Lookups that Match NID", @@ -38,7 +38,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x41", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; External Snoop Request", @@ -47,7 +47,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ.", "UMask": "0x9", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; Write Requests", @@ -56,7 +56,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.", "UMask": "0x5", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized; Lines in E state", @@ -65,7 +65,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized", @@ -74,7 +74,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized; Lines in M state", @@ -83,7 +83,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized; Victimized Lines that Match NID", @@ -92,7 +92,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized; Lines in S State", @@ -101,7 +101,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc; RFO HitS", @@ -110,7 +110,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.; Number of times that an RFO hit in S state. This is useful for determining if it might be good for a workload to use RspIWB instead of RspSWB.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc; Silent Snoop Eviction", @@ -119,7 +119,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc", @@ -128,7 +128,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc; Write Combining Aliasing", @@ -137,7 +137,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LRU Queue; LRU Age 0", @@ -146,7 +146,7 @@ "PerPkg": "1", "PublicDescription": "How often age was set to 0", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LRU Queue; LRU Age 1", @@ -155,7 +155,7 @@ "PerPkg": "1", "PublicDescription": "How often age was set to 1", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LRU Queue; LRU Age 2", @@ -164,7 +164,7 @@ "PerPkg": "1", "PublicDescription": "How often age was set to 2", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LRU Queue; LRU Age 3", @@ -173,7 +173,7 @@ "PerPkg": "1", "PublicDescription": "How often age was set to 3", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LRU Queue; LRU Bits Decremented", @@ -182,7 +182,7 @@ "PerPkg": "1", "PublicDescription": "How often all LRU bits were decremented by 1", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "LRU Queue; Non-0 Aged Victim", @@ -191,7 +191,7 @@ "PerPkg": "1", "PublicDescription": "How often we picked a victim that had a non-zero age", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Counterclockwise", @@ -200,7 +200,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0xc", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Clockwise", @@ -209,7 +209,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Down", @@ -218,7 +218,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0xcc", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Down and Even on Vring 0", @@ -227,7 +227,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 0.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Down and Odd on Vring 0", @@ -236,7 +236,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 0.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Down and Even on VRing 1", @@ -245,7 +245,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 1.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Down and Odd on VRing 1", @@ -254,7 +254,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 1.", "UMask": "0x80", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Up", @@ -263,7 +263,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x33", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Up and Even on Vring 0", @@ -272,7 +272,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 0.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Up and Odd on Vring 0", @@ -281,7 +281,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 0.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Up and Even on VRing 1", @@ -290,7 +290,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 1.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Up and Odd on VRing 1", @@ -299,7 +299,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 1.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Counterclockwise", @@ -308,7 +308,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0xc", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Clockwise", @@ -317,7 +317,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Down", @@ -326,7 +326,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0xcc", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Down and Even on Vring 0", @@ -335,7 +335,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 0.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Down and Odd on Vring 0", @@ -344,7 +344,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 0.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Down and Even on VRing 1", @@ -353,7 +353,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 1.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Down and Odd on VRing 1", @@ -362,7 +362,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 1.", "UMask": "0x80", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Up", @@ -371,7 +371,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x33", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Up and Even on Vring 0", @@ -380,7 +380,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 0.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Up and Odd on Vring 0", @@ -389,7 +389,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 0.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Up and Even on VRing 1", @@ -398,7 +398,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 1.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Up and Odd on VRing 1", @@ -407,7 +407,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 1.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Counterclockwise", @@ -416,7 +416,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0xc", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Clockwise", @@ -425,7 +425,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Down", @@ -434,7 +434,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0xcc", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Down and Even on Vring 0", @@ -443,7 +443,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 0.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Down and Odd on Vring 0", @@ -452,7 +452,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 0.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Down and Even on VRing 1", @@ -461,7 +461,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 1.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Down and Odd on VRing 1", @@ -470,7 +470,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 1.", "UMask": "0x80", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Up", @@ -479,7 +479,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x33", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Up and Even on Vring 0", @@ -488,7 +488,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 0.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Up and Odd on Vring 0", @@ -497,7 +497,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 0.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Up and Even on VRing 1", @@ -506,7 +506,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 1.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Up and Odd on VRing 1", @@ -515,7 +515,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 1.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of LLC responses that bounced on the Ring.", @@ -523,7 +523,7 @@ "EventName": "UNC_C_RING_BOUNCES.AD_IRQ", "PerPkg": "1", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of LLC responses that bounced on the Ring.; Acknowledgements to core", @@ -531,7 +531,7 @@ "EventName": "UNC_C_RING_BOUNCES.AK", "PerPkg": "1", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of LLC responses that bounced on the Ring.: Acknowledgements to core", @@ -539,7 +539,7 @@ "EventName": "UNC_C_RING_BOUNCES.AK_CORE", "PerPkg": "1", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of LLC responses that bounced on the Ring.; Data Responses to core", @@ -547,7 +547,7 @@ "EventName": "UNC_C_RING_BOUNCES.BL", "PerPkg": "1", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of LLC responses that bounced on the Ring.: Data Responses to core", @@ -555,7 +555,7 @@ "EventName": "UNC_C_RING_BOUNCES.BL_CORE", "PerPkg": "1", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.", @@ -563,7 +563,7 @@ "EventName": "UNC_C_RING_BOUNCES.IV", "PerPkg": "1", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of LLC responses that bounced on the Ring.: Snoops of processor's cache.", @@ -571,7 +571,7 @@ "EventName": "UNC_C_RING_BOUNCES.IV_CORE", "PerPkg": "1", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "IV Ring in Use; Any", @@ -580,7 +580,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters any polarity", "UMask": "0xf", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "IV Ring in Use; Down", @@ -589,7 +589,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for Down polarity", "UMask": "0xcc", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "IV Ring in Use; Up", @@ -598,34 +598,34 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for Up polarity", "UMask": "0x33", - "Unit": "CBO" + "Unit": "CBOX" }, { "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.AD_IPQ", "PerPkg": "1", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.AD_IRQ", "PerPkg": "1", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.IV", "PerPkg": "1", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "EventCode": "0x7", "EventName": "UNC_C_RING_SRC_THRTL", "PerPkg": "1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ", @@ -634,7 +634,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally startved and therefore we are blocking the IRQ.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ", @@ -643,7 +643,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IRQ is externally starved and therefore we are blocking the IPQ.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID", @@ -652,7 +652,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; Number of times that the ISMQ Bid.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Arbiter Blocking Cycles", @@ -661,7 +661,7 @@ "PerPkg": "1", "PublicDescription": "IRQ is blocking the ingress queue and causing the starvation.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Allocations; IPQ", @@ -670,7 +670,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Allocations; IRQ", @@ -679,7 +679,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Allocations; IRQ Rejected", @@ -688,7 +688,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Allocations: IRQ Rejected", @@ -697,7 +697,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Allocations; VFIFO", @@ -706,7 +706,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.; Counts the number of allocations into the IRQ Ordering FIFO. In JKT, it is necessary to keep IO requests in order. Therefore, they are allocated into an ordering FIFO that sits next to the IRQ, and must be satisfied from the FIFO in order (with respect to each other). This event, in conjunction with the Occupancy Accumulator event, can be used to calculate average lifetime in the FIFO. Transactions are allocated into the FIFO as soon as they enter the Cachebo (and the IRQ) and are deallocated from the FIFO as soon as they are deallocated from the IRQ.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Internal Starvation Cycles; IPQ", @@ -715,7 +715,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IPQ in Internal Starvation.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Internal Starvation Cycles; IRQ", @@ -724,7 +724,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IRQ in Internal Starvation.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ", @@ -733,7 +733,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the ISMQ in Internal Starvation.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; Address Conflict", @@ -742,7 +742,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from an address conflicts. Address conflicts out of the IPQ should be rare. They will generally only occur if two different sockets are sending requests to the same address at the same time. This is a true conflict case, unlike the IPQ Address Conflict which is commonly caused by prefetching characteristics.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; Any Reject", @@ -751,7 +751,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject. TOR rejects from the IPQ can be caused by the Egress being full or Address Conflicts.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; No Egress Credits", @@ -760,7 +760,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from the Egress being full. IPQ requests make use of the AD Egress for regular responses, the BL egress to forward data, and the AK egress to return credits.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; No QPI Credits", @@ -769,7 +769,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; Address Conflict", @@ -778,7 +778,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the IRQ was retried because of an address match in the TOR. In order to maintain coherency, requests to the same address are not allowed to pass each other up in the Cbo. Therefore, if there is an outstanding request to a given address, one cannot issue another request to that address until it is complete. This comes up most commonly with prefetches. Outstanding prefetches occasionally will not complete their memory fetch and a demand request to the same address will then sit in the IRQ and get retried until the prefetch fills the data into the LLC. Therefore, it will not be uncommon to see this case in high bandwidth streaming workloads when the LLC Prefetcher in the core is enabled.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; Any Reject", @@ -787,7 +787,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of IRQ retries that occur. Requests from the IRQ are retried if they are rejected from the TOR pipeline for a variety of reasons. Some of the most common reasons include if the Egress is full, there are no RTIDs, or there is a Physical Address match to another outstanding request.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No Egress Credits", @@ -796,7 +796,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that a request from the IRQ was retried because it failed to acquire an entry in the Egress. The egress is the buffer that queues up for allocating onto the ring. IRQ requests can make use of all four rings and all four Egresses. If any of the queues that a given request needs to make use of are full, the request will be retried.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits", @@ -805,7 +805,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO. There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No QPI Credits", @@ -814,7 +814,7 @@ "PerPkg": "1", "PublicDescription": "Number of requests rejects because of lack of QPI Ingress credits. These credits are required in order to send transactions to the QPI agent. Please see the QPI_IGR_CREDITS events for more information.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No RTIDs", @@ -823,7 +823,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that requests from the IRQ were retried because there were no RTIDs available. RTIDs are required after a request misses the LLC and needs to send snoops and/or requests to memory. If there are no RTIDs available, requests will queue up in the IRQ and retry until one becomes available. Note that there are multiple RTID pools for the different sockets. There may be cases where the local RTIDs are all used, but requests destined for remote memory can still acquire an RTID because there are remote RTIDs available. This event does not provide any filtering for this case.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; Any Reject", @@ -832,7 +832,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the total number of times that a request from the ISMQ retried because of a TOR reject. ISMQ requests generally will not need to retry (or at least ISMQ retries are less common than IRQ retries). ISMQ requests will retry if they are not able to acquire a needed Egress credit to get onto the ring, or for cache evictions that need to acquire an RTID. Most ISMQ requests already have an RTID, so eviction retries will be less common here.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; No Egress Credits", @@ -841,7 +841,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by a lack of Egress credits. The egress is the buffer that queues up for allocating onto the ring. If any of the Egress queues that a given request needs to make use of are full, the request will be retried.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; No IIO Credits", @@ -850,7 +850,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO. There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; No QPI Credits", @@ -859,7 +859,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; No RTIDs", @@ -868,7 +868,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by no RTIDs. M-state cache evictions are serviced through the ISMQ, and must acquire an RTID in order to write back to memory. If no RTIDs are available, they will be retried.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; No WB Credits", @@ -877,7 +877,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Retries of writes to local memory due to lack of HT WB credits", "UMask": "0x80", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Occupancy; IPQ", @@ -886,7 +886,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Occupancy; IRQ", @@ -895,7 +895,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Occupancy; IRQ Rejected", @@ -904,7 +904,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "IRQ Rejected", @@ -913,7 +913,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Occupancy; VFIFO", @@ -922,7 +922,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.; Accumulates the number of used entries in the IRQ Ordering FIFO in each cycle. In JKT, it is necessary to keep IO requests in order. Therefore, they are allocated into an ordering FIFO that sits next to the IRQ, and must be satisfied from the FIFO in order (with respect to each other). This event, in conjunction with the Allocations event, can be used to calculate average lifetime in the FIFO. This event can be used in conjunction with the Not Empty event to calculate average queue occupancy. Transactions are allocated into the FIFO as soon as they enter the Cachebo (and the IRQ) and are deallocated from the FIFO as soon as they are deallocated from the IRQ.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; All", @@ -931,7 +931,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Evictions", @@ -940,7 +940,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Eviction transactions inserted into the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Local Memory", @@ -949,7 +949,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x28", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched", @@ -958,7 +958,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisfied by an opcode, inserted into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x21", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Misses to Local Memory", @@ -967,7 +967,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x2a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode Matched", @@ -976,7 +976,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisfied by an opcode, inserted into the TOR that are satisfied by locally HOMed memory.", "UMask": "0x23", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Miss Opcode Match", @@ -985,7 +985,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode.", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Misses to Remote Memory", @@ -994,7 +994,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x8a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode Matched", @@ -1003,7 +1003,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisfied by an opcode, inserted into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x83", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID Matched", @@ -1012,7 +1012,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x48", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID Matched Evictions", @@ -1021,7 +1021,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction transactions inserted into the TOR.", "UMask": "0x44", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID Matched Miss All", @@ -1030,7 +1030,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requests that were inserted into the TOR.", "UMask": "0x4a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss", @@ -1039,7 +1039,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode.", "UMask": "0x43", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID and Opcode Matched", @@ -1048,7 +1048,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode.", "UMask": "0x41", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID Matched Writebacks", @@ -1057,7 +1057,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transactions inserted into the TOR.", "UMask": "0x50", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Opcode Match", @@ -1066,7 +1066,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc)", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Remote Memory", @@ -1075,7 +1075,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x88", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched", @@ -1084,7 +1084,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisfied by an opcode, inserted into the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x81", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Writebacks", @@ -1093,7 +1093,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Write transactions inserted into the TOR. This does not include RFO, but actual operations that contain data being sent from the core.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Any", @@ -1102,7 +1102,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All valid TOR entries. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Evictions", @@ -1111,7 +1111,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding eviction transactions in the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory).", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy", @@ -1120,7 +1120,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x28", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched", @@ -1129,7 +1129,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisfied by an opcode, in the TOR that are satisfied by locally HOMed memory.", "UMask": "0x21", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Miss All", @@ -1138,7 +1138,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding miss requests in the TOR. 'Miss' means the allocation requires an RTID. This generally means that the request was sent to memory or MMIO.", "UMask": "0xa", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy", @@ -1147,7 +1147,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x2a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcode Matched", @@ -1156,7 +1156,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisfied by an opcode, in the TOR that are satisfied by locally HOMed memory.", "UMask": "0x23", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Miss Opcode Match", @@ -1165,7 +1165,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO.", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy", @@ -1174,7 +1174,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x8a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opcode Matched", @@ -1183,7 +1183,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisfied by an opcode, in the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x83", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID Matched", @@ -1192,7 +1192,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of NID matched outstanding requests in the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system.", "UMask": "0x48", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID Matched Evictions", @@ -1201,7 +1201,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding NID matched eviction transactions in the TOR .", "UMask": "0x44", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID Matched", @@ -1210,7 +1210,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID.", "UMask": "0x4a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss", @@ -1219,7 +1219,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID and an opcode.", "UMask": "0x43", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID and Opcode Matched", @@ -1228,7 +1228,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match a NID and an opcode.", "UMask": "0x41", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID Matched Writebacks", @@ -1237,7 +1237,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); NID matched write transactions int the TOR.", "UMask": "0x50", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Opcode Match", @@ -1246,7 +1246,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc).", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy", @@ -1255,7 +1255,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x88", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Remote Memory - Opcode Matched", @@ -1264,7 +1264,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisfied by an opcode, in the TOR that are satisfied by remote caches or remote memory.", "UMask": "0x81", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Writebacks", @@ -1273,7 +1273,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Write transactions in the TOR. This does not include RFO, but actual operations that contain data being sent from the core.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Onto AD Ring", @@ -1281,7 +1281,7 @@ "EventName": "UNC_C_TxR_ADS_USED.AD", "PerPkg": "1", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Onto AK Ring", @@ -1289,7 +1289,7 @@ "EventName": "UNC_C_TxR_ADS_USED.AK", "PerPkg": "1", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Onto BL Ring", @@ -1297,7 +1297,7 @@ "EventName": "UNC_C_TxR_ADS_USED.BL", "PerPkg": "1", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; AD - Cachebo", @@ -1306,7 +1306,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; AD - Corebo", @@ -1315,7 +1315,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AD ring. This is commonly used for outbound requests.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; AK - Cachebo", @@ -1324,7 +1324,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AK ring. This is commonly used for credit returns and GO responses.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; AK - Corebo", @@ -1333,7 +1333,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AK ring. This is commonly used for snoop responses coming from the core and destined for a Cachebo.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; BL - Cacheno", @@ -1342,7 +1342,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the BL ring. This is commonly used to send data from the cache to various destinations.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; BL - Corebo", @@ -1351,7 +1351,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring. This is commonly used for transferring writeback data to the cache.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; IV - Cachebo", @@ -1360,7 +1360,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the IV ring. This is commonly used for snoops to the cores.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Injection Starvation; Onto AD Ring (to core)", @@ -1369,7 +1369,7 @@ "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the core AD egress spent in starvation", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Injection Starvation; Onto AK Ring", @@ -1378,7 +1378,7 @@ "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both AK egresses spent in starvation", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Injection Starvation; Onto IV Ring", @@ -1387,7 +1387,7 @@ "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the cachebo IV egress spent in starvation", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BT Bypass", diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.json index e1b9799e3036..ccf451534d16 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.json @@ -1,11 +1,316 @@ [ + { + "BriefDescription": "Address Match (Conflict) Count; Conflict Merges", + "EventCode": "0x17", + "EventName": "UNC_I_ADDRESS_MATCH.MERGE_COUNT", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache.; When two requests to the same address from the same source are received back to back, it is possible to merge the two of them together.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Address Match (Conflict) Count; Conflict Stalls", + "EventCode": "0x17", + "EventName": "UNC_I_ADDRESS_MATCH.STALL_COUNT", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache.; When it is not possible to merge two conflicting requests, a stall event occurs. This is bad for performance.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Write Ack Pending Occupancy; Any Source", + "EventCode": "0x14", + "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Write Ack Pending Occupancy; Select Source", + "EventCode": "0x14", + "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.SOURCE", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements.; Tracks all requests from any source port.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Outstanding Write Ownership Occupancy; Any Source", + "EventCode": "0x13", + "EventName": "UNC_I_CACHE_OWN_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle. This can be used with the write transaction count to calculate the average write latency in the uncore. The occupancy increments when a write request is issued, and decrements when the data is returned.; Tracks all requests from any source port.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Outstanding Write Ownership Occupancy; Select Source", + "EventCode": "0x13", + "EventName": "UNC_I_CACHE_OWN_OCCUPANCY.SOURCE", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle. This can be used with the write transaction count to calculate the average write latency in the uncore. The occupancy increments when a write request is issued, and decrements when the data is returned.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Outstanding Read Occupancy; Any Source", + "EventCode": "0x10", + "EventName": "UNC_I_CACHE_READ_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of reads that are outstanding in the uncore in each cycle. This can be used with the read transaction count to calculate the average read latency in the uncore. The occupancy increments when a read request is issued, and decrements when the data is returned.; Tracks all requests from any source port.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Outstanding Read Occupancy; Select Source", + "EventCode": "0x10", + "EventName": "UNC_I_CACHE_READ_OCCUPANCY.SOURCE", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of reads that are outstanding in the uncore in each cycle. This can be used with the read transaction count to calculate the average read latency in the uncore. The occupancy increments when a read request is issued, and decrements when the data is returned.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Total Write Cache Occupancy; Any Source", + "EventCode": "0x12", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Total Write Cache Occupancy; Select Source", + "EventCode": "0x12", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Outstanding Write Occupancy; Any Source", + "EventCode": "0x11", + "EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of writes (and write prefetches) that are outstanding in the uncore in each cycle. This can be used with the transaction count event to calculate the average latency in the uncore. The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore.; Tracks all requests from any source port.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Outstanding Write Occupancy; Select Source", + "EventCode": "0x11", + "EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.SOURCE", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of writes (and write prefetches) that are outstanding in the uncore in each cycle. This can be used with the transaction count event to calculate the average latency in the uncore. The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Clocks in the IRP", + "EventName": "UNC_I_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Number of clocks in the IRP.", + "Unit": "IRP" + }, + { + "EventCode": "0xb", + "EventName": "UNC_I_RxR_AK_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the AK Ingress is full. This queue is where the IRP receives responses from R2PCIe (the ring).", + "Unit": "IRP" + }, + { + "BriefDescription": "AK Ingress Occupancy", + "EventCode": "0xa", + "EventName": "UNC_I_RxR_AK_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the AK Ingress. This queue is where the IRP receives responses from R2PCIe (the ring).", + "Unit": "IRP" + }, + { + "EventCode": "0xc", + "EventName": "UNC_I_RxR_AK_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the AK Ingress in each cycles. This queue is where the IRP receives responses from R2PCIe (the ring).", + "Unit": "IRP" + }, + { + "EventCode": "0x4", + "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "BL Ingress Occupancy - DRS", + "EventCode": "0x1", + "EventName": "UNC_I_RxR_BL_DRS_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "EventCode": "0x7", + "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "EventCode": "0x5", + "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "BL Ingress Occupancy - NCB", + "EventCode": "0x2", + "EventName": "UNC_I_RxR_BL_NCB_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "EventCode": "0x8", + "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "EventCode": "0x6", + "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "BL Ingress Occupancy - NCS", + "EventCode": "0x3", + "EventName": "UNC_I_RxR_BL_NCS_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "EventCode": "0x9", + "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "Tickle Count; Ownership Lost", + "EventCode": "0x16", + "EventName": "UNC_I_TICKLES.LOST_OWNERSHIP", + "PerPkg": "1", + "PublicDescription": "Counts the number of tickles that are received. This is for both explicit (from Cbo) and implicit (internal conflict) tickles.; Tracks the number of requests that lost ownership as a result of a tickle. When a tickle comes in, if the request is not at the head of the queue in the switch, then that request as well as any requests behind it in the switch queue will lose ownership and have to re-acquire it later when they get to the head of the queue. This will therefore track the number of requests that lost ownership and not just the number of tickles.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Tickle Count; Data Returned", + "EventCode": "0x16", + "EventName": "UNC_I_TICKLES.TOP_OF_QUEUE", + "PerPkg": "1", + "PublicDescription": "Counts the number of tickles that are received. This is for both explicit (from Cbo) and implicit (internal conflict) tickles.; Tracks the number of cases when a tickle was received but the requests was at the head of the queue in the switch. In this case, data is returned rather than releasing ownership.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count: Read Prefetches", + "EventCode": "0x15", + "EventName": "UNC_I_TRANSACTIONS.PD_PREFETCHES", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Read Prefetches", + "EventCode": "0x15", + "EventName": "UNC_I_TRANSACTIONS.RD_PREFETCHES", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Reads", + "EventCode": "0x15", + "EventName": "UNC_I_TRANSACTIONS.READS", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Writes", + "EventCode": "0x15", + "EventName": "UNC_I_TRANSACTIONS.WRITES", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "No AD Egress Credit Stalls", + "EventCode": "0x18", + "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.", + "Unit": "IRP" + }, + { + "BriefDescription": "No BL Egress Credit Stalls", + "EventCode": "0x19", + "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "EventCode": "0xe", + "EventName": "UNC_I_TxR_DATA_INSERTS_NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "EventCode": "0xf", + "EventName": "UNC_I_TxR_DATA_INSERTS_NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Request Queue Occupancy", + "EventCode": "0xd", + "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.", + "Unit": "IRP" + }, + { + "BriefDescription": "Write Ordering Stalls", + "EventCode": "0x1a", + "EventName": "UNC_I_WRITE_ORDERING_STALL_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are pending write ACK's in the switch but the switch->IRP pipeline is not utilized.", + "Unit": "IRP" + }, { "BriefDescription": "Number of qfclks", "EventCode": "0x14", "EventName": "UNC_Q_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "Counts the number of clocks in the QPI LL. This clock runs at 1/8th the GT/s speed of the QPI link. For example, a 8GT/s link will have qfclk or 1GHz. JKT does not support dynamic link speeds, so this frequency is fixed.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Count of CTO Events", @@ -13,7 +318,7 @@ "EventName": "UNC_Q_CTO_COUNT", "PerPkg": "1", "PublicDescription": "Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots. If both slots trigger in a given cycle, the event will increment by 2. You can use edge detect to count the number of cases when both events triggered.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress Credits", @@ -22,7 +327,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits. Had there been enough credits, the spawn would have worked as the RBT bit was set and the RBT tag matched.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss", @@ -31,7 +336,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and there weren't enough Egress credits. The valid bit was set.", "UMask": "0x20", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Invalid", @@ -40,7 +345,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits AND the RBT bit was not set, but the RBT tag matched.", "UMask": "0x8", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT Miss, Invalid", @@ -49,7 +354,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match, the valid bit was not set and there weren't enough Egress credits.", "UMask": "0x80", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss", @@ -58,7 +363,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match although the valid bit was set and there were enough Egress credits.", "UMask": "0x10", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Invalid", @@ -67,7 +372,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the route-back table (RBT) specified that the transaction should not trigger a direct2core transaction. This is common for IO transactions. There were enough Egress credits and the RBT tag matched but the valid bit was not set.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Miss and Invalid", @@ -76,7 +381,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and the valid bit was not set although there were enough Egress credits.", "UMask": "0x40", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Success", @@ -85,7 +390,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn was successful. There were sufficient credits, the RBT valid bit was set and there was an RBT tag match. The message was marked to spawn direct2core.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Cycles in L1", @@ -93,205 +398,205 @@ "EventName": "UNC_Q_L1_POWER_CYCLES", "PerPkg": "1", "PublicDescription": "Number of QPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a QPI link. Use edge detect to count the number of instances when the QPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MATCH_MASK", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.AnyDataC", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.AnyResp", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.AnyResp11flits", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.AnyResp9flits", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.DataC_E", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.DataC_E_Cmp", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.DataC_E_FrcAckCnflt", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.DataC_F", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.DataC_F_Cmp", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.DataC_F_FrcAckCnflt", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.DataC_M", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.WbEData", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.WbIData", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.WbSData", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.HOM.AnyReq", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.HOM.AnyResp", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.HOM.RespFwd", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.HOM.RespFwdI", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.HOM.RespFwdIWb", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.HOM.RespFwdS", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.HOM.RespFwdSWb", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.HOM.RespIWb", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.HOM.RespSWb", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.NCB.AnyInt", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.NCB.AnyMsg", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.NCB.AnyMsg11flits", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.NCB.AnyMsg9flits", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.NCS.AnyMsg1or2flits", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.NCS.AnyMsg3flits", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.NCS.NcRd", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.NDR.AnyCmp", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.SNP.AnySnp", "PerPkg": "1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Cycles in L0p", @@ -299,7 +604,7 @@ "EventName": "UNC_Q_RxL0P_POWER_CYCLES", "PerPkg": "1", "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Cycles in L0", @@ -307,7 +612,7 @@ "EventName": "UNC_Q_RxL0_POWER_CYCLES", "PerPkg": "1", "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Bypassed", @@ -315,7 +620,7 @@ "EventName": "UNC_Q_RxL_BYPASSED", "PerPkg": "1", "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "CRC Errors Detected; LinkInit", @@ -324,7 +629,7 @@ "PerPkg": "1", "PublicDescription": "Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during link initialization.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "CRC Errors Detected; Normal Operations", @@ -333,7 +638,7 @@ "PerPkg": "1", "PublicDescription": "Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during normal operation.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "VN0 Credit Consumed; DRS", @@ -342,7 +647,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the DRS message class.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "VN0 Credit Consumed; HOM", @@ -351,7 +656,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the HOM message class.", "UMask": "0x8", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "VN0 Credit Consumed; NCB", @@ -360,7 +665,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCB message class.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "VN0 Credit Consumed; NCS", @@ -369,7 +674,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCS message class.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "VN0 Credit Consumed; NDR", @@ -378,7 +683,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NDR message class.", "UMask": "0x20", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "VN0 Credit Consumed; SNP", @@ -387,7 +692,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the SNP message class.", "UMask": "0x10", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "VN1 Credit Consumed; DRS", @@ -396,7 +701,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the DRS message class.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "VN1 Credit Consumed; HOM", @@ -405,7 +710,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the HOM message class.", "UMask": "0x8", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "VN1 Credit Consumed; NCB", @@ -414,7 +719,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCB message class.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "VN1 Credit Consumed; NCS", @@ -423,7 +728,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCS message class.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "VN1 Credit Consumed; NDR", @@ -432,7 +737,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NDR message class.", "UMask": "0x20", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "VN1 Credit Consumed; SNP", @@ -441,7 +746,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the SNP message class.", "UMask": "0x10", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "VNA Credit Consumed", @@ -449,7 +754,7 @@ "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA", "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Cycles Not Empty", @@ -457,7 +762,7 @@ "EventName": "UNC_Q_RxL_CYCLES_NE", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN0", @@ -466,7 +771,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN1", @@ -475,7 +780,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN0", @@ -484,7 +789,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN1", @@ -493,7 +798,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN0", @@ -502,7 +807,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN1", @@ -511,7 +816,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN0", @@ -520,7 +825,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN1", @@ -529,7 +834,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN0", @@ -538,7 +843,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN1", @@ -547,7 +852,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN0", @@ -556,7 +861,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN1", @@ -565,7 +870,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 0; Data Tx Flits", @@ -574,7 +879,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits received over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 0; Idle and Null Flits", @@ -583,7 +888,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits received over QPI that do not hold protocol payload. When QPI is not in a power saving state, it continuously transmits flits across the link. When there are no protocol flits to send, it will send IDLE and NULL flits across. These flits sometimes do carry a payload, such as credit returns, but are generally not considered part of the QPI bandwidth.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 0; Non-Data protocol Tx Flits", @@ -592,7 +897,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits received across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)", @@ -601,7 +906,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data.", "UMask": "0x18", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 1; DRS Data Flits", @@ -610,7 +915,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).", "UMask": "0x8", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 1; DRS Header Flits", @@ -619,7 +924,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.", "UMask": "0x10", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 1; HOM Flits", @@ -628,7 +933,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits received over QPI on the home channel.", "UMask": "0x6", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits", @@ -637,7 +942,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits received over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 1; HOM Request Flits", @@ -646,7 +951,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request received over QPI on the home channel. This basically counts the number of remote memory requests received over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 1; SNP Flits", @@ -655,7 +960,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits received over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are received on the home channel.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits", @@ -664,7 +969,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.", "UMask": "0xc", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 2; Non-Coherent data Rx Flits", @@ -673,7 +978,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 2; Non-Coherent non-data Rx Flits", @@ -682,7 +987,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.", "UMask": "0x8", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits", @@ -691,7 +996,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits received over QPI. This includes extended headers.", "UMask": "0x10", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD", @@ -700,7 +1005,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK", @@ -709,7 +1014,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations", @@ -717,7 +1022,7 @@ "EventName": "UNC_Q_RxL_INSERTS", "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations - DRS", @@ -725,7 +1030,7 @@ "EventName": "UNC_Q_RxL_INSERTS_DRS", "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN0", @@ -734,7 +1039,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN1", @@ -743,7 +1048,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations - HOM", @@ -751,7 +1056,7 @@ "EventName": "UNC_Q_RxL_INSERTS_HOM", "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN0", @@ -760,7 +1065,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN1", @@ -769,7 +1074,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations - NCB", @@ -777,7 +1082,7 @@ "EventName": "UNC_Q_RxL_INSERTS_NCB", "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN0", @@ -786,7 +1091,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN1", @@ -795,7 +1100,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations - NCS", @@ -803,7 +1108,7 @@ "EventName": "UNC_Q_RxL_INSERTS_NCS", "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN0", @@ -812,7 +1117,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN1", @@ -821,7 +1126,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations - NDR", @@ -829,7 +1134,7 @@ "EventName": "UNC_Q_RxL_INSERTS_NDR", "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN0", @@ -838,7 +1143,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN1", @@ -847,7 +1152,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations - SNP", @@ -855,7 +1160,7 @@ "EventName": "UNC_Q_RxL_INSERTS_SNP", "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN0", @@ -864,7 +1169,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN1", @@ -873,7 +1178,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - All Packets", @@ -881,7 +1186,7 @@ "EventName": "UNC_Q_RxL_OCCUPANCY", "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - DRS", @@ -889,7 +1194,7 @@ "EventName": "UNC_Q_RxL_OCCUPANCY_DRS", "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - DRS; for VN0", @@ -898,7 +1203,7 @@ "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - DRS; for VN1", @@ -907,7 +1212,7 @@ "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - HOM", @@ -915,7 +1220,7 @@ "EventName": "UNC_Q_RxL_OCCUPANCY_HOM", "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - HOM; for VN0", @@ -924,7 +1229,7 @@ "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - HOM; for VN1", @@ -933,7 +1238,7 @@ "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - NCB", @@ -941,7 +1246,7 @@ "EventName": "UNC_Q_RxL_OCCUPANCY_NCB", "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - NCB; for VN0", @@ -950,7 +1255,7 @@ "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - NCB; for VN1", @@ -959,7 +1264,7 @@ "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - NCS", @@ -967,7 +1272,7 @@ "EventName": "UNC_Q_RxL_OCCUPANCY_NCS", "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - NCS; for VN0", @@ -976,7 +1281,7 @@ "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - NCS; for VN1", @@ -985,7 +1290,7 @@ "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - NDR", @@ -993,7 +1298,7 @@ "EventName": "UNC_Q_RxL_OCCUPANCY_NDR", "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - NDR; for VN0", @@ -1002,7 +1307,7 @@ "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - NDR; for VN1", @@ -1011,7 +1316,7 @@ "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - SNP", @@ -1019,7 +1324,7 @@ "EventName": "UNC_Q_RxL_OCCUPANCY_SNP", "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - SNP; for VN0", @@ -1028,7 +1333,7 @@ "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - SNP; for VN1", @@ -1037,7 +1342,7 @@ "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - HOM", @@ -1046,7 +1351,7 @@ "PerPkg": "1", "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - DRS", @@ -1055,7 +1360,7 @@ "PerPkg": "1", "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", "UMask": "0x8", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - SNP", @@ -1064,7 +1369,7 @@ "PerPkg": "1", "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NDR", @@ -1073,7 +1378,7 @@ "PerPkg": "1", "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCS", @@ -1082,7 +1387,7 @@ "PerPkg": "1", "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", "UMask": "0x20", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - NCB", @@ -1091,7 +1396,7 @@ "PerPkg": "1", "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", "UMask": "0x10", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; Egress Credits", @@ -1100,7 +1405,7 @@ "PerPkg": "1", "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet because there were insufficient BGF credits. For details on a message class granularity, use the Egress Credit Occupancy events.", "UMask": "0x40", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; GV", @@ -1109,7 +1414,7 @@ "PerPkg": "1", "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled because a GV transition (frequency transition) was taking place.", "UMask": "0x80", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - HOM", @@ -1118,7 +1423,7 @@ "PerPkg": "1", "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - DRS", @@ -1127,7 +1432,7 @@ "PerPkg": "1", "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", "UMask": "0x8", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - SNP", @@ -1136,7 +1441,7 @@ "PerPkg": "1", "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NDR", @@ -1145,7 +1450,7 @@ "PerPkg": "1", "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCS", @@ -1154,7 +1459,7 @@ "PerPkg": "1", "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", "UMask": "0x20", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - NCB", @@ -1163,7 +1468,7 @@ "PerPkg": "1", "PublicDescription": "Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary.", "UMask": "0x10", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Cycles in L0p", @@ -1171,7 +1476,7 @@ "EventName": "UNC_Q_TxL0P_POWER_CYCLES", "PerPkg": "1", "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Cycles in L0", @@ -1179,7 +1484,7 @@ "EventName": "UNC_Q_TxL0_POWER_CYCLES", "PerPkg": "1", "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Tx Flit Buffer Bypassed", @@ -1187,7 +1492,7 @@ "EventName": "UNC_Q_TxL_BYPASSED", "PerPkg": "1", "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full", @@ -1196,7 +1501,7 @@ "PerPkg": "1", "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is almost full, we block some but not all packets.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full", @@ -1205,7 +1510,7 @@ "PerPkg": "1", "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is totally full, we are not allowed to send any packets.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Tx Flit Buffer Cycles not Empty", @@ -1213,7 +1518,7 @@ "EventName": "UNC_Q_TxL_CYCLES_NE", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits", @@ -1221,7 +1526,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits", @@ -1229,7 +1534,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)", @@ -1237,7 +1542,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency.", "UMask": "0x18", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits", @@ -1245,7 +1550,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header).", "UMask": "0x8", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits", @@ -1253,7 +1558,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers.", "UMask": "0x10", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 1; HOM Flits", @@ -1261,7 +1566,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits transmitted over QPI on the home channel.", "UMask": "0x6", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits", @@ -1269,7 +1574,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits transmitted over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits", @@ -1277,7 +1582,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request transmitted over QPI on the home channel. This basically counts the number of remote memory requests transmitted over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 1; SNP Flits", @@ -1285,7 +1590,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits transmitted over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are transmitted on the home channel.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits", @@ -1294,7 +1599,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI.", "UMask": "0xc", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 2; Non-Coherent data Tx Flits", @@ -1303,7 +1608,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 2; Non-Coherent non-data Tx Flits", @@ -1312,7 +1617,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers.", "UMask": "0x8", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits", @@ -1321,7 +1626,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits transmitted over QPI. This includes extended headers.", "UMask": "0x10", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD", @@ -1330,7 +1635,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK", @@ -1339,7 +1644,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three groups that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each flit is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four fits, each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the system will transfer 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as data bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual data and an additional 16 bits of other information. To calculate data bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Tx Flit Buffer Allocations", @@ -1347,7 +1652,7 @@ "EventName": "UNC_Q_TxL_INSERTS", "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Tx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Tx Flit Buffer Occupancy", @@ -1355,7 +1660,7 @@ "EventName": "UNC_Q_TxL_OCCUPANCY", "PerPkg": "1", "PublicDescription": "Accumulates the number of flits in the TxQ. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN0", @@ -1364,7 +1669,7 @@ "PerPkg": "1", "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN1", @@ -1373,7 +1678,7 @@ "PerPkg": "1", "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN0", @@ -1382,7 +1687,7 @@ "PerPkg": "1", "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for VN1", @@ -1391,7 +1696,7 @@ "PerPkg": "1", "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0", @@ -1400,7 +1705,7 @@ "PerPkg": "1", "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1", @@ -1409,7 +1714,7 @@ "PerPkg": "1", "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN0", @@ -1418,7 +1723,7 @@ "PerPkg": "1", "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for VN1", @@ -1427,7 +1732,7 @@ "PerPkg": "1", "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN0", @@ -1436,7 +1741,7 @@ "PerPkg": "1", "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN1", @@ -1445,7 +1750,7 @@ "PerPkg": "1", "PublicDescription": "Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN0", @@ -1454,7 +1759,7 @@ "PerPkg": "1", "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for Snoop messages on AD.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for VN1", @@ -1463,7 +1768,7 @@ "PerPkg": "1", "PublicDescription": "Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for Snoop messages on AD.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR", @@ -1471,7 +1776,7 @@ "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED", "PerPkg": "1", "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR: for VN0", @@ -1480,7 +1785,7 @@ "PerPkg": "1", "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR: for VN1", @@ -1489,7 +1794,7 @@ "PerPkg": "1", "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR", @@ -1497,7 +1802,7 @@ "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY", "PerPkg": "1", "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. Local NDR message class to AK Egress.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR: for VN0", @@ -1506,7 +1811,7 @@ "PerPkg": "1", "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. Local NDR message class to AK Egress.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR: for VN1", @@ -1515,7 +1820,7 @@ "PerPkg": "1", "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. Local NDR message class to AK Egress.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN0", @@ -1524,7 +1829,7 @@ "PerPkg": "1", "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN1", @@ -1533,7 +1838,7 @@ "PerPkg": "1", "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for Shared VN", @@ -1542,7 +1847,7 @@ "PerPkg": "1", "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN0", @@ -1551,7 +1856,7 @@ "PerPkg": "1", "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for VN1", @@ -1560,7 +1865,7 @@ "PerPkg": "1", "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for Shared VN", @@ -1569,7 +1874,7 @@ "PerPkg": "1", "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN0", @@ -1578,7 +1883,7 @@ "PerPkg": "1", "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN1", @@ -1587,7 +1892,7 @@ "PerPkg": "1", "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN0", @@ -1596,7 +1901,7 @@ "PerPkg": "1", "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for VN1", @@ -1605,7 +1910,7 @@ "PerPkg": "1", "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN0", @@ -1614,7 +1919,7 @@ "PerPkg": "1", "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN1", @@ -1623,7 +1928,7 @@ "PerPkg": "1", "PublicDescription": "Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN0", @@ -1632,7 +1937,7 @@ "PerPkg": "1", "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for VN1", @@ -1641,7 +1946,7 @@ "PerPkg": "1", "PublicDescription": "Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "VNA Credits Returned", @@ -1649,7 +1954,7 @@ "EventName": "UNC_Q_VNA_CREDIT_RETURNS", "PerPkg": "1", "PublicDescription": "Number of VNA credits returned.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "VNA Credits Pending Return - Occupancy", @@ -1657,6 +1962,1326 @@ "EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY", "PerPkg": "1", "PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.", - "Unit": "QPI LL" + "Unit": "QPI" + }, + { + "BriefDescription": "Number of uclks in domain", + "EventCode": "0x1", + "EventName": "UNC_R3_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts the number of uclks in the QPI uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles.", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x2c", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 10", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x2c", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 11", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x2c", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 12", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x2c", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 13", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x2c", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 14&16", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x2c", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 8", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x2c", + "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 9", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x2b", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 0", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x2b", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x2b", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 2", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x2b", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 3", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x2b", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 4", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x2b", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 5", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x2b", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 6", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "CBox AD Credits Empty", + "EventCode": "0x2b", + "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 7", + "UMask": "0x80", + "Unit": "R3QPI" + }, + { + "BriefDescription": "HA/R2 AD Credits Empty", + "EventCode": "0x2f", + "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0", + "PerPkg": "1", + "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA0", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "HA/R2 AD Credits Empty", + "EventCode": "0x2f", + "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1", + "PerPkg": "1", + "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA1", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "HA/R2 AD Credits Empty", + "EventCode": "0x2f", + "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB", + "PerPkg": "1", + "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCB Messages", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "HA/R2 AD Credits Empty", + "EventCode": "0x2f", + "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS", + "PerPkg": "1", + "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCS Messages", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "EventCode": "0x29", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 HOM Messages", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "EventCode": "0x29", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 NDR Messages", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "EventCode": "0x29", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 SNP Messages", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "EventCode": "0x29", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 HOM Messages", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "EventCode": "0x29", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 NDR Messages", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "EventCode": "0x29", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 SNP Messages", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 AD Credits Empty", + "EventCode": "0x29", + "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VNA", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "EventCode": "0x2d", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN0 HOM Messages", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "EventCode": "0x2d", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN0 NDR Messages", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "EventCode": "0x2d", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN0 SNP Messages", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "EventCode": "0x2d", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 HOM Messages", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "EventCode": "0x2d", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 NDR Messages", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "EventCode": "0x2d", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 SNP Messages", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI0 BL Credits Empty", + "EventCode": "0x2d", + "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VNA", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "EventCode": "0x2a", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN0 HOM Messages", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "EventCode": "0x2a", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN0 NDR Messages", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "EventCode": "0x2a", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN0 SNP Messages", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "EventCode": "0x2a", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 HOM Messages", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "EventCode": "0x2a", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 NDR Messages", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "EventCode": "0x2a", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 SNP Messages", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 AD Credits Empty", + "EventCode": "0x2a", + "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VNA", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "EventCode": "0x2e", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 HOM Messages", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "EventCode": "0x2e", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 NDR Messages", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "EventCode": "0x2e", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 SNP Messages", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "EventCode": "0x2e", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 HOM Messages", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "EventCode": "0x2e", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 NDR Messages", + "UMask": "0x40", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "EventCode": "0x2e", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 SNP Messages", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "QPI1 BL Credits Empty", + "EventCode": "0x2e", + "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VNA", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Counterclockwise", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xcc", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even on VRing 0", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CCW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd on VRing 0", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CCW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Clockwise", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x33", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Clockwise and Even on VRing 0", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd on VRing 0", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Counterclockwise", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xcc", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even on VRing 0", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CCW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd on VRing 0", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CCW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Clockwise", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x33", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Clockwise and Even on VRing 0", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd on VRing 0", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Counterclockwise", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xcc", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even on VRing 0", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CCW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd on VRing 0", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CCW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Clockwise", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x33", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Clockwise and Even on VRing 0", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd on VRing 0", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R2 IV Ring in Use; Any", + "EventCode": "0xA", + "EventName": "UNC_R3_RING_IV_USED.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters any polarity", + "UMask": "0xff", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R2 IV Ring in Use; Counterclockwise", + "EventCode": "0xa", + "EventName": "UNC_R3_RING_IV_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Counterclockwise polarity", + "UMask": "0xcc", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R2 IV Ring in Use; Clockwise", + "EventCode": "0xa", + "EventName": "UNC_R3_RING_IV_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Clockwise polarity", + "UMask": "0x33", + "Unit": "R3QPI" + }, + { + "BriefDescription": "AD Ingress Bypassed", + "EventCode": "0x12", + "EventName": "UNC_R3_RxR_AD_BYPASSED", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when the AD Ingress was bypassed and an incoming transaction was bypassed directly across the BGF and into the qfclk domain.", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Bypassed", + "EventCode": "0x12", + "EventName": "UNC_R3_RxR_BYPASSED.AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when the Ingress was bypassed and an incoming transaction was bypassed directly across the BGF and into the qfclk domain.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; HOM", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NDR", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.NDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; SNP", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; DRS", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; HOM", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; NCB", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; NCS", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; NDR", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.NDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; SNP", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; DRS", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY.DRS", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; HOM", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY.HOM", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; HOM Ingress Queue", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; NCB", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY.NCB", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; NCB Ingress Queue", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; NCS", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY.NCS", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; NCS Ingress Queue", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; NDR", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY.NDR", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; NDR Ingress Queue", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; SNP", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY.SNP", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; SNP Ingress Queue", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Egress NACK; AK CCW", + "EventCode": "0x28", + "EventName": "UNC_R3_TxR_NACK_CCW.AD", + "PerPkg": "1", + "PublicDescription": "BL CounterClockwise Egress Queue", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Egress NACK; BL CW", + "EventCode": "0x28", + "EventName": "UNC_R3_TxR_NACK_CCW.AK", + "PerPkg": "1", + "PublicDescription": "AD Clockwise Egress Queue", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Egress NACK; BL CCW", + "EventCode": "0x28", + "EventName": "UNC_R3_TxR_NACK_CCW.BL", + "PerPkg": "1", + "PublicDescription": "AD CounterClockwise Egress Queue", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Egress NACK; AD CW", + "EventCode": "0x26", + "EventName": "UNC_R3_TxR_NACK_CW.AD", + "PerPkg": "1", + "PublicDescription": "AD Clockwise Egress Queue", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Egress NACK; AD CCW", + "EventCode": "0x26", + "EventName": "UNC_R3_TxR_NACK_CW.AK", + "PerPkg": "1", + "PublicDescription": "AD CounterClockwise Egress Queue", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Egress NACK; AK CW", + "EventCode": "0x26", + "EventName": "UNC_R3_TxR_NACK_CW.BL", + "PerPkg": "1", + "PublicDescription": "BL Clockwise Egress Queue", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Message Class", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Message Class", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; DRS Message Class", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.DRS", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; HOM Message Class", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.HOM", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; NCB Message Class", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.NCB", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; NCS Message Class", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; NDR Message Class", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.NDR", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; SNP Message Class", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Message Class", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Message Class", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCB Message Class", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCB", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCS Message Class", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCS", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Message Class", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Message Class", + "EventCode": "0x39", + "EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; DRS Message Class", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.DRS", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; HOM Message Class", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.HOM", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; NCB Message Class", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.NCB", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; NCS Message Class", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; NDR Message Class", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.NDR", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN1 Credit Used; SNP Message Class", + "EventCode": "0x38", + "EventName": "UNC_R3_VN1_CREDITS_USED.SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA credit Acquisitions", + "EventCode": "0x33", + "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED", + "PerPkg": "1", + "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA credit Acquisitions; HOM Message Class", + "EventCode": "0x33", + "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD", + "PerPkg": "1", + "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA credit Acquisitions; HOM Message Class", + "EventCode": "0x33", + "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL", + "PerPkg": "1", + "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; DRS Message Class", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; HOM Message Class", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; NCB Message Class", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; NCS Message Class", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Standard (NCS).", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; NDR Message Class", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; SNP Message Class", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Cycles with no VNA credits available", + "EventCode": "0x31", + "EventName": "UNC_R3_VNA_CREDIT_CYCLES_OUT", + "PerPkg": "1", + "PublicDescription": "Number of QPI uclk cycles when the transmitted has no VNA credits available and therefore cannot send any requests on this channel. Note that this does not mean that no flits can be transmitted, as those holding VN0 credits will still (potentially) be able to transmit. Generally it is the goal of the uncore that VNA credits should not run out, as this can substantially throttle back useful QPI bandwidth.", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Cycles with 1 or more VNA credits in use", + "EventCode": "0x32", + "EventName": "UNC_R3_VNA_CREDIT_CYCLES_USED", + "PerPkg": "1", + "PublicDescription": "Number of QPI uclk cycles with one or more VNA credits in use. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average number of used VNA credits.", + "Unit": "R3QPI" + }, + { + "EventName": "UNC_U_CLOCKTICKS", + "PerPkg": "1", + "Unit": "UBOX" + }, + { + "BriefDescription": "VLW Received", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "VLW Received", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.INT_PRIO", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "VLW Received", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "VLW Received", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "VLW Received", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.DISABLE", + "PerPkg": "1", + "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.ENABLE", + "PerPkg": "1", + "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE", + "PerPkg": "1", + "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE", + "PerPkg": "1", + "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "IDI Lock/SplitLock Cycles", + "EventCode": "0x44", + "EventName": "UNC_U_LOCK_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of times an IDI Lock/SplitLock sequence was started", + "Unit": "UBOX" + }, + { + "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", + "EventCode": "0x45", + "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", + "PerPkg": "1", + "PublicDescription": "PHOLD cycles. Filter from source CoreID.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "RACU Request", + "EventCode": "0x46", + "EventName": "UNC_U_RACU_REQUESTS", + "PerPkg": "1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Correctable Machine Check", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.CMC", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one or all cores", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Livelock", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.LIVELOCK", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; LTError", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.LTERROR", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Monitor T0", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Monitor T1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Other", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.OTHER", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one or all cores; PREQ, PSMI, P2U, Thermal, PCUSMI, PMI", + "UMask": "0x80", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Trap", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.TRAP", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one or all cores", + "UMask": "0x40", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.UMC", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one or all cores", + "UMask": "0x20", + "Unit": "UBOX" } ] diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-io.json b/tools/perf/pmu-events/arch/x86/ivytown/uncore-io.json new file mode 100644 index 000000000000..5887e6ebcfa8 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-io.json @@ -0,0 +1,549 @@ +[ + { + "BriefDescription": "Number of uclks in domain", + "EventCode": "0x1", + "EventName": "UNC_R2_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts the number of uclks in the R2PCIe uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; DRS", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; NCB", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; NCS", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; DRS", + "EventCode": "0x34", + "EventName": "UNC_R2_IIO_CREDITS_REJECT.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; DRS", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; NCB", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; NCS", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xcc", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even on VRing 0", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd on VRing 0", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even on VRing 1", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW_VR1_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1.", + "UMask": "0x40", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd on VRing 1", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW_VR1_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1.", + "UMask": "0x80", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x33", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise and Even on VRing 0", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd on VRing 0", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise and Even on VRing 1", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW_VR1_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1.", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd on VRing 1", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW_VR1_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1.", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xcc", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even on VRing 0", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd on VRing 0", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even on VRing 1", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW_VR1_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1.", + "UMask": "0x40", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd on VRing 1", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW_VR1_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1.", + "UMask": "0x80", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x33", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise and Even on VRing 0", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd on VRing 0", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise and Even on VRing 1", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW_VR1_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1.", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd on VRing 1", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW_VR1_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1.", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0xcc", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even on VRing 0", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd on VRing 0", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even on VRing 1", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW_VR1_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1.", + "UMask": "0x40", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd on VRing 1", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW_VR1_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1.", + "UMask": "0x80", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x33", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise and Even on VRing 0", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW_VR0_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd on VRing 0", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW_VR0_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise and Even on VRing 1", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW_VR1_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1.", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd on VRing 1", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW_VR1_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1.", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 IV Ring in Use; Any", + "EventCode": "0xA", + "EventName": "UNC_R2_RING_IV_USED.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters any polarity", + "UMask": "0xff", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 IV Ring in Use; Counterclockwise", + "EventCode": "0xa", + "EventName": "UNC_R2_RING_IV_USED.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Counterclockwise polarity", + "UMask": "0xcc", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 IV Ring in Use; Clockwise", + "EventCode": "0xa", + "EventName": "UNC_R2_RING_IV_USED.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Clockwise polarity", + "UMask": "0x33", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "AK Ingress Bounced", + "EventCode": "0x12", + "EventName": "UNC_R2_RxR_AK_BOUNCES", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "AK Ingress Bounced; Counterclockwise", + "EventCode": "0x12", + "EventName": "UNC_R2_RxR_AK_BOUNCES.CCW", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "AK Ingress Bounced; Clockwise", + "EventCode": "0x12", + "EventName": "UNC_R2_RxR_AK_BOUNCES.CW", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NCB", + "EventCode": "0x10", + "EventName": "UNC_R2_RxR_CYCLES_NE.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NCS", + "EventCode": "0x10", + "EventName": "UNC_R2_RxR_CYCLES_NE.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Allocations; NCB", + "EventCode": "0x11", + "EventName": "UNC_R2_RxR_INSERTS.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Allocations; NCS", + "EventCode": "0x11", + "EventName": "UNC_R2_RxR_INSERTS.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; DRS", + "EventCode": "0x13", + "EventName": "UNC_R2_RxR_OCCUPANCY.DRS", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; AD", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AD Egress Queue", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; AK", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.AK", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AK Egress Queue", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; BL", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.BL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; BL Egress Queue", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; AD", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AD Egress Queue", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; AK", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.AK", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AK Egress Queue", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; BL", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.BL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; BL Egress Queue", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; AD CCW", + "EventCode": "0x28", + "EventName": "UNC_R2_TxR_NACK_CCW.AD", + "PerPkg": "1", + "PublicDescription": "AD CounterClockwise Egress Queue", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; AK CCW", + "EventCode": "0x28", + "EventName": "UNC_R2_TxR_NACK_CCW.AK", + "PerPkg": "1", + "PublicDescription": "AK CounterClockwise Egress Queue", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CCW NACK; BL CCW", + "EventCode": "0x28", + "EventName": "UNC_R2_TxR_NACK_CCW.BL", + "PerPkg": "1", + "PublicDescription": "BL CounterClockwise Egress Queue", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CW NACK; AD CW", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.AD", + "PerPkg": "1", + "PublicDescription": "AD Clockwise Egress Queue", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CW NACK; AK CW", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.AK", + "PerPkg": "1", + "PublicDescription": "AK Clockwise Egress Queue", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress CW NACK; BL CW", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACK_CW.BL", + "PerPkg": "1", + "PublicDescription": "BL Clockwise Egress Queue", + "UMask": "0x4", + "Unit": "R2PCIe" + } +] diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-other.json b/tools/perf/pmu-events/arch/x86/ivytown/uncore-other.json deleted file mode 100644 index af9d14a6d145..000000000000 --- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-other.json +++ /dev/null @@ -1,2174 +0,0 @@ -[ - { - "BriefDescription": "Address Match (Conflict) Count; Conflict Merges", - "EventCode": "0x17", - "EventName": "UNC_I_ADDRESS_MATCH.MERGE_COUNT", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache.; When two requests to the same address from the same source are received back to back, it is possible to merge the two of them together.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Address Match (Conflict) Count; Conflict Stalls", - "EventCode": "0x17", - "EventName": "UNC_I_ADDRESS_MATCH.STALL_COUNT", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache.; When it is not possible to merge two conflicting requests, a stall event occurs. This is bad for performance.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Write Ack Pending Occupancy; Any Source", - "EventCode": "0x14", - "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.ANY", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Write Ack Pending Occupancy; Select Source", - "EventCode": "0x14", - "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.SOURCE", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements.; Tracks all requests from any source port.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Outstanding Write Ownership Occupancy; Any Source", - "EventCode": "0x13", - "EventName": "UNC_I_CACHE_OWN_OCCUPANCY.ANY", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle. This can be used with the write transaction count to calculate the average write latency in the uncore. The occupancy increments when a write request is issued, and decrements when the data is returned.; Tracks all requests from any source port.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Outstanding Write Ownership Occupancy; Select Source", - "EventCode": "0x13", - "EventName": "UNC_I_CACHE_OWN_OCCUPANCY.SOURCE", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle. This can be used with the write transaction count to calculate the average write latency in the uncore. The occupancy increments when a write request is issued, and decrements when the data is returned.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Outstanding Read Occupancy; Any Source", - "EventCode": "0x10", - "EventName": "UNC_I_CACHE_READ_OCCUPANCY.ANY", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of reads that are outstanding in the uncore in each cycle. This can be used with the read transaction count to calculate the average read latency in the uncore. The occupancy increments when a read request is issued, and decrements when the data is returned.; Tracks all requests from any source port.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Outstanding Read Occupancy; Select Source", - "EventCode": "0x10", - "EventName": "UNC_I_CACHE_READ_OCCUPANCY.SOURCE", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of reads that are outstanding in the uncore in each cycle. This can be used with the read transaction count to calculate the average read latency in the uncore. The occupancy increments when a read request is issued, and decrements when the data is returned.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Total Write Cache Occupancy; Any Source", - "EventCode": "0x12", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Total Write Cache Occupancy; Select Source", - "EventCode": "0x12", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Outstanding Write Occupancy; Any Source", - "EventCode": "0x11", - "EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.ANY", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of writes (and write prefetches) that are outstanding in the uncore in each cycle. This can be used with the transaction count event to calculate the average latency in the uncore. The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore.; Tracks all requests from any source port.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Outstanding Write Occupancy; Select Source", - "EventCode": "0x11", - "EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.SOURCE", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of writes (and write prefetches) that are outstanding in the uncore in each cycle. This can be used with the transaction count event to calculate the average latency in the uncore. The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Clocks in the IRP", - "EventName": "UNC_I_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Number of clocks in the IRP.", - "Unit": "IRP" - }, - { - "EventCode": "0xb", - "EventName": "UNC_I_RxR_AK_CYCLES_FULL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the AK Ingress is full. This queue is where the IRP receives responses from R2PCIe (the ring).", - "Unit": "IRP" - }, - { - "BriefDescription": "AK Ingress Occupancy", - "EventCode": "0xa", - "EventName": "UNC_I_RxR_AK_INSERTS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the AK Ingress. This queue is where the IRP receives responses from R2PCIe (the ring).", - "Unit": "IRP" - }, - { - "EventCode": "0xc", - "EventName": "UNC_I_RxR_AK_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of the AK Ingress in each cycles. This queue is where the IRP receives responses from R2PCIe (the ring).", - "Unit": "IRP" - }, - { - "EventCode": "0x4", - "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "BL Ingress Occupancy - DRS", - "EventCode": "0x1", - "EventName": "UNC_I_RxR_BL_DRS_INSERTS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "EventCode": "0x7", - "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "EventCode": "0x5", - "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "BL Ingress Occupancy - NCB", - "EventCode": "0x2", - "EventName": "UNC_I_RxR_BL_NCB_INSERTS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "EventCode": "0x8", - "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "EventCode": "0x6", - "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "BL Ingress Occupancy - NCS", - "EventCode": "0x3", - "EventName": "UNC_I_RxR_BL_NCS_INSERTS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "EventCode": "0x9", - "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "Tickle Count; Ownership Lost", - "EventCode": "0x16", - "EventName": "UNC_I_TICKLES.LOST_OWNERSHIP", - "PerPkg": "1", - "PublicDescription": "Counts the number of tickles that are received. This is for both explicit (from Cbo) and implicit (internal conflict) tickles.; Tracks the number of requests that lost ownership as a result of a tickle. When a tickle comes in, if the request is not at the head of the queue in the switch, then that request as well as any requests behind it in the switch queue will lose ownership and have to re-acquire it later when they get to the head of the queue. This will therefore track the number of requests that lost ownership and not just the number of tickles.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Tickle Count; Data Returned", - "EventCode": "0x16", - "EventName": "UNC_I_TICKLES.TOP_OF_QUEUE", - "PerPkg": "1", - "PublicDescription": "Counts the number of tickles that are received. This is for both explicit (from Cbo) and implicit (internal conflict) tickles.; Tracks the number of cases when a tickle was received but the requests was at the head of the queue in the switch. In this case, data is returned rather than releasing ownership.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count: Read Prefetches", - "EventCode": "0x15", - "EventName": "UNC_I_TRANSACTIONS.PD_PREFETCHES", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Read Prefetches", - "EventCode": "0x15", - "EventName": "UNC_I_TRANSACTIONS.RD_PREFETCHES", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Reads", - "EventCode": "0x15", - "EventName": "UNC_I_TRANSACTIONS.READS", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Writes", - "EventCode": "0x15", - "EventName": "UNC_I_TRANSACTIONS.WRITES", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "No AD Egress Credit Stalls", - "EventCode": "0x18", - "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES", - "PerPkg": "1", - "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.", - "Unit": "IRP" - }, - { - "BriefDescription": "No BL Egress Credit Stalls", - "EventCode": "0x19", - "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES", - "PerPkg": "1", - "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Read Requests", - "EventCode": "0xe", - "EventName": "UNC_I_TxR_DATA_INSERTS_NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Read Requests", - "EventCode": "0xf", - "EventName": "UNC_I_TxR_DATA_INSERTS_NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Request Queue Occupancy", - "EventCode": "0xd", - "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.", - "Unit": "IRP" - }, - { - "BriefDescription": "Write Ordering Stalls", - "EventCode": "0x1a", - "EventName": "UNC_I_WRITE_ORDERING_STALL_CYCLES", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when there are pending write ACK's in the switch but the switch->IRP pipeline is not utilized.", - "Unit": "IRP" - }, - { - "BriefDescription": "Number of uclks in domain", - "EventCode": "0x1", - "EventName": "UNC_R2_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Counts the number of uclks in the R2PCIe uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credit Acquired; DRS", - "EventCode": "0x33", - "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credit Acquired; NCB", - "EventCode": "0x33", - "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credit Acquired; NCS", - "EventCode": "0x33", - "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; DRS", - "EventCode": "0x34", - "EventName": "UNC_R2_IIO_CREDITS_REJECT.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credits in Use; DRS", - "EventCode": "0x32", - "EventName": "UNC_R2_IIO_CREDITS_USED.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credits in Use; NCB", - "EventCode": "0x32", - "EventName": "UNC_R2_IIO_CREDITS_USED.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class.", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credits in Use; NCS", - "EventCode": "0x32", - "EventName": "UNC_R2_IIO_CREDITS_USED.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class.", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Counterclockwise", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xcc", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even on VRing 0", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CCW_VR0_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd on VRing 0", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CCW_VR0_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even on VRing 1", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CCW_VR1_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1.", - "UMask": "0x40", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd on VRing 1", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CCW_VR1_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1.", - "UMask": "0x80", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Clockwise", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x33", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Clockwise and Even on VRing 0", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CW_VR0_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd on VRing 0", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CW_VR0_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Clockwise and Even on VRing 1", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CW_VR1_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1.", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd on VRing 1", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CW_VR1_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1.", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Counterclockwise", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xcc", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even on VRing 0", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CCW_VR0_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd on VRing 0", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CCW_VR0_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even on VRing 1", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CCW_VR1_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1.", - "UMask": "0x40", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd on VRing 1", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CCW_VR1_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1.", - "UMask": "0x80", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Clockwise", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x33", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Clockwise and Even on VRing 0", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CW_VR0_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd on VRing 0", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CW_VR0_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Clockwise and Even on VRing 1", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CW_VR1_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1.", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd on VRing 1", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CW_VR1_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1.", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Counterclockwise", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xcc", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even on VRing 0", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CCW_VR0_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd on VRing 0", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CCW_VR0_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even on VRing 1", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CCW_VR1_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1.", - "UMask": "0x40", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd on VRing 1", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CCW_VR1_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1.", - "UMask": "0x80", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Clockwise", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x33", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Clockwise and Even on VRing 0", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CW_VR0_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd on VRing 0", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CW_VR0_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Clockwise and Even on VRing 1", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CW_VR1_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1.", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd on VRing 1", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CW_VR1_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1.", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 IV Ring in Use; Any", - "EventCode": "0xA", - "EventName": "UNC_R2_RING_IV_USED.ANY", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters any polarity", - "UMask": "0xff", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 IV Ring in Use; Counterclockwise", - "EventCode": "0xa", - "EventName": "UNC_R2_RING_IV_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Counterclockwise polarity", - "UMask": "0xcc", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 IV Ring in Use; Clockwise", - "EventCode": "0xa", - "EventName": "UNC_R2_RING_IV_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Clockwise polarity", - "UMask": "0x33", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "AK Ingress Bounced", - "EventCode": "0x12", - "EventName": "UNC_R2_RxR_AK_BOUNCES", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "AK Ingress Bounced; Counterclockwise", - "EventCode": "0x12", - "EventName": "UNC_R2_RxR_AK_BOUNCES.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "AK Ingress Bounced; Clockwise", - "EventCode": "0x12", - "EventName": "UNC_R2_RxR_AK_BOUNCES.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; NCB", - "EventCode": "0x10", - "EventName": "UNC_R2_RxR_CYCLES_NE.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; NCS", - "EventCode": "0x10", - "EventName": "UNC_R2_RxR_CYCLES_NE.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Ingress Allocations; NCB", - "EventCode": "0x11", - "EventName": "UNC_R2_RxR_INSERTS.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Ingress Allocations; NCS", - "EventCode": "0x11", - "EventName": "UNC_R2_RxR_INSERTS.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Ingress Occupancy Accumulator; DRS", - "EventCode": "0x13", - "EventName": "UNC_R2_RxR_OCCUPANCY.DRS", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Full; AD", - "EventCode": "0x25", - "EventName": "UNC_R2_TxR_CYCLES_FULL.AD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AD Egress Queue", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Full; AK", - "EventCode": "0x25", - "EventName": "UNC_R2_TxR_CYCLES_FULL.AK", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; AK Egress Queue", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Full; BL", - "EventCode": "0x25", - "EventName": "UNC_R2_TxR_CYCLES_FULL.BL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.; BL Egress Queue", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Not Empty; AD", - "EventCode": "0x23", - "EventName": "UNC_R2_TxR_CYCLES_NE.AD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AD Egress Queue", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Not Empty; AK", - "EventCode": "0x23", - "EventName": "UNC_R2_TxR_CYCLES_NE.AK", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AK Egress Queue", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Not Empty; BL", - "EventCode": "0x23", - "EventName": "UNC_R2_TxR_CYCLES_NE.BL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; BL Egress Queue", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress CCW NACK; AD CCW", - "EventCode": "0x28", - "EventName": "UNC_R2_TxR_NACK_CCW.AD", - "PerPkg": "1", - "PublicDescription": "AD CounterClockwise Egress Queue", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress CCW NACK; AK CCW", - "EventCode": "0x28", - "EventName": "UNC_R2_TxR_NACK_CCW.AK", - "PerPkg": "1", - "PublicDescription": "AK CounterClockwise Egress Queue", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress CCW NACK; BL CCW", - "EventCode": "0x28", - "EventName": "UNC_R2_TxR_NACK_CCW.BL", - "PerPkg": "1", - "PublicDescription": "BL CounterClockwise Egress Queue", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress CW NACK; AD CW", - "EventCode": "0x26", - "EventName": "UNC_R2_TxR_NACK_CW.AD", - "PerPkg": "1", - "PublicDescription": "AD Clockwise Egress Queue", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress CW NACK; AK CW", - "EventCode": "0x26", - "EventName": "UNC_R2_TxR_NACK_CW.AK", - "PerPkg": "1", - "PublicDescription": "AK Clockwise Egress Queue", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress CW NACK; BL CW", - "EventCode": "0x26", - "EventName": "UNC_R2_TxR_NACK_CW.BL", - "PerPkg": "1", - "PublicDescription": "BL Clockwise Egress Queue", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Number of uclks in domain", - "EventCode": "0x1", - "EventName": "UNC_R3_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Counts the number of uclks in the QPI uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles.", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x2c", - "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 10", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x2c", - "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 11", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x2c", - "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 12", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x2c", - "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 13", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x2c", - "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 14&16", - "UMask": "0x40", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x2c", - "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 8", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x2c", - "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 9", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x2b", - "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 0", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x2b", - "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 1", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x2b", - "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 2", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x2b", - "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 3", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x2b", - "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 4", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x2b", - "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 5", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x2b", - "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 6", - "UMask": "0x40", - "Unit": "R3QPI" - }, - { - "BriefDescription": "CBox AD Credits Empty", - "EventCode": "0x2b", - "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 7", - "UMask": "0x80", - "Unit": "R3QPI" - }, - { - "BriefDescription": "HA/R2 AD Credits Empty", - "EventCode": "0x2f", - "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0", - "PerPkg": "1", - "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA0", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "HA/R2 AD Credits Empty", - "EventCode": "0x2f", - "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1", - "PerPkg": "1", - "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; HA1", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "HA/R2 AD Credits Empty", - "EventCode": "0x2f", - "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB", - "PerPkg": "1", - "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCB Messages", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "HA/R2 AD Credits Empty", - "EventCode": "0x2f", - "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS", - "PerPkg": "1", - "PublicDescription": "No credits available to send to either HA or R2 on the BL Ring; R2 NCS Messages", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 AD Credits Empty", - "EventCode": "0x29", - "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 HOM Messages", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 AD Credits Empty", - "EventCode": "0x29", - "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 NDR Messages", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 AD Credits Empty", - "EventCode": "0x29", - "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN0 SNP Messages", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 AD Credits Empty", - "EventCode": "0x29", - "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 HOM Messages", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 AD Credits Empty", - "EventCode": "0x29", - "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 NDR Messages", - "UMask": "0x40", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 AD Credits Empty", - "EventCode": "0x29", - "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VN1 SNP Messages", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 AD Credits Empty", - "EventCode": "0x29", - "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the AD Ring; VNA", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 BL Credits Empty", - "EventCode": "0x2d", - "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_HOM", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN0 HOM Messages", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 BL Credits Empty", - "EventCode": "0x2d", - "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_NDR", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN0 NDR Messages", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 BL Credits Empty", - "EventCode": "0x2d", - "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN0 SNP Messages", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 BL Credits Empty", - "EventCode": "0x2d", - "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 HOM Messages", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 BL Credits Empty", - "EventCode": "0x2d", - "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 NDR Messages", - "UMask": "0x40", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 BL Credits Empty", - "EventCode": "0x2d", - "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VN1 SNP Messages", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI0 BL Credits Empty", - "EventCode": "0x2d", - "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI0 on the BL Ring; VNA", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 AD Credits Empty", - "EventCode": "0x2a", - "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_HOM", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN0 HOM Messages", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 AD Credits Empty", - "EventCode": "0x2a", - "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_NDR", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN0 NDR Messages", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 AD Credits Empty", - "EventCode": "0x2a", - "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN0 SNP Messages", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 AD Credits Empty", - "EventCode": "0x2a", - "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 HOM Messages", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 AD Credits Empty", - "EventCode": "0x2a", - "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 NDR Messages", - "UMask": "0x40", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 AD Credits Empty", - "EventCode": "0x2a", - "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VN1 SNP Messages", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 AD Credits Empty", - "EventCode": "0x2a", - "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the AD Ring; VNA", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 BL Credits Empty", - "EventCode": "0x2e", - "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 HOM Messages", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 BL Credits Empty", - "EventCode": "0x2e", - "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 NDR Messages", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 BL Credits Empty", - "EventCode": "0x2e", - "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN0 SNP Messages", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 BL Credits Empty", - "EventCode": "0x2e", - "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 HOM Messages", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 BL Credits Empty", - "EventCode": "0x2e", - "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 NDR Messages", - "UMask": "0x40", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 BL Credits Empty", - "EventCode": "0x2e", - "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VN1 SNP Messages", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "QPI1 BL Credits Empty", - "EventCode": "0x2e", - "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA", - "PerPkg": "1", - "PublicDescription": "No credits available to send to QPI1 on the BL Ring; VNA", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AD Ring in Use; Counterclockwise", - "EventCode": "0x7", - "EventName": "UNC_R3_RING_AD_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xcc", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even on VRing 0", - "EventCode": "0x7", - "EventName": "UNC_R3_RING_AD_USED.CCW_VR0_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd on VRing 0", - "EventCode": "0x7", - "EventName": "UNC_R3_RING_AD_USED.CCW_VR0_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AD Ring in Use; Clockwise", - "EventCode": "0x7", - "EventName": "UNC_R3_RING_AD_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x33", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AD Ring in Use; Clockwise and Even on VRing 0", - "EventCode": "0x7", - "EventName": "UNC_R3_RING_AD_USED.CW_VR0_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd on VRing 0", - "EventCode": "0x7", - "EventName": "UNC_R3_RING_AD_USED.CW_VR0_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AK Ring in Use; Counterclockwise", - "EventCode": "0x8", - "EventName": "UNC_R3_RING_AK_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xcc", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even on VRing 0", - "EventCode": "0x8", - "EventName": "UNC_R3_RING_AK_USED.CCW_VR0_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd on VRing 0", - "EventCode": "0x8", - "EventName": "UNC_R3_RING_AK_USED.CCW_VR0_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AK Ring in Use; Clockwise", - "EventCode": "0x8", - "EventName": "UNC_R3_RING_AK_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x33", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AK Ring in Use; Clockwise and Even on VRing 0", - "EventCode": "0x8", - "EventName": "UNC_R3_RING_AK_USED.CW_VR0_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd on VRing 0", - "EventCode": "0x8", - "EventName": "UNC_R3_RING_AK_USED.CW_VR0_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 BL Ring in Use; Counterclockwise", - "EventCode": "0x9", - "EventName": "UNC_R3_RING_BL_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0xcc", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even on VRing 0", - "EventCode": "0x9", - "EventName": "UNC_R3_RING_BL_USED.CCW_VR0_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0.", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd on VRing 0", - "EventCode": "0x9", - "EventName": "UNC_R3_RING_BL_USED.CCW_VR0_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 BL Ring in Use; Clockwise", - "EventCode": "0x9", - "EventName": "UNC_R3_RING_BL_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x33", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 BL Ring in Use; Clockwise and Even on VRing 0", - "EventCode": "0x9", - "EventName": "UNC_R3_RING_BL_USED.CW_VR0_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd on VRing 0", - "EventCode": "0x9", - "EventName": "UNC_R3_RING_BL_USED.CW_VR0_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R2 IV Ring in Use; Any", - "EventCode": "0xA", - "EventName": "UNC_R3_RING_IV_USED.ANY", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters any polarity", - "UMask": "0xff", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R2 IV Ring in Use; Counterclockwise", - "EventCode": "0xa", - "EventName": "UNC_R3_RING_IV_USED.CCW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Counterclockwise polarity", - "UMask": "0xcc", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R2 IV Ring in Use; Clockwise", - "EventCode": "0xa", - "EventName": "UNC_R3_RING_IV_USED.CW", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Clockwise polarity", - "UMask": "0x33", - "Unit": "R3QPI" - }, - { - "BriefDescription": "AD Ingress Bypassed", - "EventCode": "0x12", - "EventName": "UNC_R3_RxR_AD_BYPASSED", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when the AD Ingress was bypassed and an incoming transaction was bypassed directly across the BGF and into the qfclk domain.", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Bypassed", - "EventCode": "0x12", - "EventName": "UNC_R3_RxR_BYPASSED.AD", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when the Ingress was bypassed and an incoming transaction was bypassed directly across the BGF and into the qfclk domain.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; HOM", - "EventCode": "0x10", - "EventName": "UNC_R3_RxR_CYCLES_NE.HOM", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; NDR", - "EventCode": "0x10", - "EventName": "UNC_R3_RxR_CYCLES_NE.NDR", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; SNP", - "EventCode": "0x10", - "EventName": "UNC_R3_RxR_CYCLES_NE.SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Allocations; DRS", - "EventCode": "0x11", - "EventName": "UNC_R3_RxR_INSERTS.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Allocations; HOM", - "EventCode": "0x11", - "EventName": "UNC_R3_RxR_INSERTS.HOM", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Allocations; NCB", - "EventCode": "0x11", - "EventName": "UNC_R3_RxR_INSERTS.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Allocations; NCS", - "EventCode": "0x11", - "EventName": "UNC_R3_RxR_INSERTS.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Allocations; NDR", - "EventCode": "0x11", - "EventName": "UNC_R3_RxR_INSERTS.NDR", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Allocations; SNP", - "EventCode": "0x11", - "EventName": "UNC_R3_RxR_INSERTS.SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Occupancy Accumulator; DRS", - "EventCode": "0x13", - "EventName": "UNC_R3_RxR_OCCUPANCY.DRS", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Occupancy Accumulator; HOM", - "EventCode": "0x13", - "EventName": "UNC_R3_RxR_OCCUPANCY.HOM", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; HOM Ingress Queue", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Occupancy Accumulator; NCB", - "EventCode": "0x13", - "EventName": "UNC_R3_RxR_OCCUPANCY.NCB", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; NCB Ingress Queue", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Occupancy Accumulator; NCS", - "EventCode": "0x13", - "EventName": "UNC_R3_RxR_OCCUPANCY.NCS", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; NCS Ingress Queue", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Occupancy Accumulator; NDR", - "EventCode": "0x13", - "EventName": "UNC_R3_RxR_OCCUPANCY.NDR", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; NDR Ingress Queue", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Occupancy Accumulator; SNP", - "EventCode": "0x13", - "EventName": "UNC_R3_RxR_OCCUPANCY.SNP", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; SNP Ingress Queue", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Egress NACK; AK CCW", - "EventCode": "0x28", - "EventName": "UNC_R3_TxR_NACK_CCW.AD", - "PerPkg": "1", - "PublicDescription": "BL CounterClockwise Egress Queue", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Egress NACK; BL CW", - "EventCode": "0x28", - "EventName": "UNC_R3_TxR_NACK_CCW.AK", - "PerPkg": "1", - "PublicDescription": "AD Clockwise Egress Queue", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Egress NACK; BL CCW", - "EventCode": "0x28", - "EventName": "UNC_R3_TxR_NACK_CCW.BL", - "PerPkg": "1", - "PublicDescription": "AD CounterClockwise Egress Queue", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Egress NACK; AD CW", - "EventCode": "0x26", - "EventName": "UNC_R3_TxR_NACK_CW.AD", - "PerPkg": "1", - "PublicDescription": "AD Clockwise Egress Queue", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Egress NACK; AD CCW", - "EventCode": "0x26", - "EventName": "UNC_R3_TxR_NACK_CW.AK", - "PerPkg": "1", - "PublicDescription": "AD CounterClockwise Egress Queue", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Egress NACK; AK CW", - "EventCode": "0x26", - "EventName": "UNC_R3_TxR_NACK_CW.BL", - "PerPkg": "1", - "PublicDescription": "BL Clockwise Egress Queue", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class", - "EventCode": "0x37", - "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class", - "EventCode": "0x37", - "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Message Class", - "EventCode": "0x37", - "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Message Class", - "EventCode": "0x37", - "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class", - "EventCode": "0x37", - "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class", - "EventCode": "0x37", - "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Used; DRS Message Class", - "EventCode": "0x36", - "EventName": "UNC_R3_VN0_CREDITS_USED.DRS", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Used; HOM Message Class", - "EventCode": "0x36", - "EventName": "UNC_R3_VN0_CREDITS_USED.HOM", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Used; NCB Message Class", - "EventCode": "0x36", - "EventName": "UNC_R3_VN0_CREDITS_USED.NCB", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Used; NCS Message Class", - "EventCode": "0x36", - "EventName": "UNC_R3_VN0_CREDITS_USED.NCS", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Used; NDR Message Class", - "EventCode": "0x36", - "EventName": "UNC_R3_VN0_CREDITS_USED.NDR", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Used; SNP Message Class", - "EventCode": "0x36", - "EventName": "UNC_R3_VN0_CREDITS_USED.SNP", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Message Class", - "EventCode": "0x39", - "EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Message Class", - "EventCode": "0x39", - "EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCB Message Class", - "EventCode": "0x39", - "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCB", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCS Message Class", - "EventCode": "0x39", - "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCS", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Message Class", - "EventCode": "0x39", - "EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Message Class", - "EventCode": "0x39", - "EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Used; DRS Message Class", - "EventCode": "0x38", - "EventName": "UNC_R3_VN1_CREDITS_USED.DRS", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Used; HOM Message Class", - "EventCode": "0x38", - "EventName": "UNC_R3_VN1_CREDITS_USED.HOM", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Used; NCB Message Class", - "EventCode": "0x38", - "EventName": "UNC_R3_VN1_CREDITS_USED.NCB", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Used; NCS Message Class", - "EventCode": "0x38", - "EventName": "UNC_R3_VN1_CREDITS_USED.NCS", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ?", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Used; NDR Message Class", - "EventCode": "0x38", - "EventName": "UNC_R3_VN1_CREDITS_USED.NDR", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN1 Credit Used; SNP Message Class", - "EventCode": "0x38", - "EventName": "UNC_R3_VN1_CREDITS_USED.SNP", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA credit Acquisitions", - "EventCode": "0x33", - "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED", - "PerPkg": "1", - "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA credit Acquisitions; HOM Message Class", - "EventCode": "0x33", - "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD", - "PerPkg": "1", - "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA credit Acquisitions; HOM Message Class", - "EventCode": "0x33", - "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL", - "PerPkg": "1", - "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA Credit Reject; DRS Message Class", - "EventCode": "0x34", - "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS", - "PerPkg": "1", - "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA Credit Reject; HOM Message Class", - "EventCode": "0x34", - "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM", - "PerPkg": "1", - "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA Credit Reject; NCB Message Class", - "EventCode": "0x34", - "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB", - "PerPkg": "1", - "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA Credit Reject; NCS Message Class", - "EventCode": "0x34", - "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS", - "PerPkg": "1", - "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Standard (NCS).", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA Credit Reject; NDR Message Class", - "EventCode": "0x34", - "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR", - "PerPkg": "1", - "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA Credit Reject; SNP Message Class", - "EventCode": "0x34", - "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP", - "PerPkg": "1", - "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Cycles with no VNA credits available", - "EventCode": "0x31", - "EventName": "UNC_R3_VNA_CREDIT_CYCLES_OUT", - "PerPkg": "1", - "PublicDescription": "Number of QPI uclk cycles when the transmitted has no VNA credits available and therefore cannot send any requests on this channel. Note that this does not mean that no flits can be transmitted, as those holding VN0 credits will still (potentially) be able to transmit. Generally it is the goal of the uncore that VNA credits should not run out, as this can substantially throttle back useful QPI bandwidth.", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Cycles with 1 or more VNA credits in use", - "EventCode": "0x32", - "EventName": "UNC_R3_VNA_CREDIT_CYCLES_USED", - "PerPkg": "1", - "PublicDescription": "Number of QPI uclk cycles with one or more VNA credits in use. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average number of used VNA credits.", - "Unit": "R3QPI" - }, - { - "EventName": "UNC_U_CLOCKTICKS", - "PerPkg": "1", - "Unit": "UBOX" - }, - { - "BriefDescription": "VLW Received", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", - "PerPkg": "1", - "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x8", - "Unit": "UBOX" - }, - { - "BriefDescription": "VLW Received", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.INT_PRIO", - "PerPkg": "1", - "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x10", - "Unit": "UBOX" - }, - { - "BriefDescription": "VLW Received", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", - "PerPkg": "1", - "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x4", - "Unit": "UBOX" - }, - { - "BriefDescription": "VLW Received", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", - "PerPkg": "1", - "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "VLW Received", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", - "PerPkg": "1", - "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "Filter Match", - "EventCode": "0x41", - "EventName": "UNC_U_FILTER_MATCH.DISABLE", - "PerPkg": "1", - "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "Filter Match", - "EventCode": "0x41", - "EventName": "UNC_U_FILTER_MATCH.ENABLE", - "PerPkg": "1", - "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "Filter Match", - "EventCode": "0x41", - "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE", - "PerPkg": "1", - "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x8", - "Unit": "UBOX" - }, - { - "BriefDescription": "Filter Match", - "EventCode": "0x41", - "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE", - "PerPkg": "1", - "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x4", - "Unit": "UBOX" - }, - { - "BriefDescription": "IDI Lock/SplitLock Cycles", - "EventCode": "0x44", - "EventName": "UNC_U_LOCK_CYCLES", - "PerPkg": "1", - "PublicDescription": "Number of times an IDI Lock/SplitLock sequence was started", - "Unit": "UBOX" - }, - { - "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", - "EventCode": "0x45", - "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", - "PerPkg": "1", - "PublicDescription": "PHOLD cycles. Filter from source CoreID.", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "RACU Request", - "EventCode": "0x46", - "EventName": "UNC_U_RACU_REQUESTS", - "PerPkg": "1", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Correctable Machine Check", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.CMC", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores", - "UMask": "0x10", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Livelock", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.LIVELOCK", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", - "UMask": "0x4", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; LTError", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.LTERROR", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", - "UMask": "0x8", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Monitor T0", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Monitor T1", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores; Filter by core", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Other", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.OTHER", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores; PREQ, PSMI, P2U, Thermal, PCUSMI, PMI", - "UMask": "0x80", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Trap", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.TRAP", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores", - "UMask": "0x40", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.UMC", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores", - "UMask": "0x20", - "Unit": "UBOX" - } -] -- cgit v1.2.3-58-ga151 From 05c74de4ecb66c75b63a348b0cb5a95bab92ce98 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 13 Apr 2023 06:29:43 -0700 Subject: perf vendor events intel: Fix uncore topics for jaketown Remove 'uncore-other' topic classification, move to cache, interconnect and io. Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230413132949.3487664-16-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/jaketown/uncore-cache.json | 194 +-- .../arch/x86/jaketown/uncore-interconnect.json | 1237 +++++++++++++++-- .../pmu-events/arch/x86/jaketown/uncore-io.json | 324 +++++ .../pmu-events/arch/x86/jaketown/uncore-other.json | 1393 -------------------- 4 files changed, 1574 insertions(+), 1574 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/jaketown/uncore-io.json delete mode 100644 tools/perf/pmu-events/arch/x86/jaketown/uncore-other.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json index 47830ca5c682..63395e7ee0ce 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json @@ -3,7 +3,7 @@ "BriefDescription": "Uncore Clocks", "EventName": "UNC_C_CLOCKTICKS", "PerPkg": "1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Counter 0 Occupancy", @@ -11,13 +11,13 @@ "EventName": "UNC_C_COUNTER0_OCCUPANCY", "PerPkg": "1", "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.", - "Unit": "CBO" + "Unit": "CBOX" }, { "EventCode": "0x21", "EventName": "UNC_C_ISMQ_DRD_MISS_OCC", "PerPkg": "1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; Data Read Request", @@ -26,7 +26,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; RTID", @@ -35,7 +35,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.", "UMask": "0x41", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; External Snoop Request", @@ -44,7 +44,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.", "UMask": "0x9", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cache Lookups; Write Requests", @@ -53,7 +53,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:18] bits correspond to [FMESI] state.", "UMask": "0x5", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized; Lines in E state", @@ -62,7 +62,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized", @@ -71,7 +71,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized; Lines in M state", @@ -80,7 +80,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized; Victimized Lines that Match NID", @@ -89,7 +89,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Lines Victimized; Lines in S State", @@ -98,7 +98,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc; RFO HitS", @@ -107,7 +107,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc; Silent Snoop Eviction", @@ -116,7 +116,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc", @@ -125,7 +125,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Cbo Misc; Write Combining Aliasing", @@ -134,7 +134,7 @@ "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Down and Even", @@ -143,7 +143,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Down and Odd", @@ -152,7 +152,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Up and Even", @@ -161,7 +161,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AD Ring In Use; Up and Odd", @@ -170,7 +170,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Down and Even", @@ -179,7 +179,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Down and Odd", @@ -188,7 +188,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Up and Even", @@ -197,7 +197,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "AK Ring In Use; Up and Odd", @@ -206,7 +206,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Down and Even", @@ -215,7 +215,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Down and Odd", @@ -224,7 +224,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Up and Even", @@ -233,7 +233,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Up and Odd", @@ -242,7 +242,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the 'UP' direction is on the clockwise ring and 'DN' is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of LLC responses that bounced on the Ring.; Acknowledgements to core", @@ -250,7 +250,7 @@ "EventName": "UNC_C_RING_BOUNCES.AK_CORE", "PerPkg": "1", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of LLC responses that bounced on the Ring.; Data Responses to core", @@ -258,7 +258,7 @@ "EventName": "UNC_C_RING_BOUNCES.BL_CORE", "PerPkg": "1", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Number of LLC responses that bounced on the Ring.; Snoops of processor's cache.", @@ -266,7 +266,7 @@ "EventName": "UNC_C_RING_BOUNCES.IV_CORE", "PerPkg": "1", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "BL Ring in Use; Any", @@ -275,41 +275,41 @@ "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring in JKT. Therefore, if one wants to monitor the 'Even' ring, they should select both UP_EVEN and DN_EVEN. To monitor the 'Odd' ring, they should select both UP_ODD and DN_ODD.", "UMask": "0xf", - "Unit": "CBO" + "Unit": "CBOX" }, { "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.AD_CACHE", "PerPkg": "1", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.AK_CORE", "PerPkg": "1", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.BL_CORE", "PerPkg": "1", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.IV_CORE", "PerPkg": "1", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "EventCode": "0x7", "EventName": "UNC_C_RING_SRC_THRTL", "PerPkg": "1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ", @@ -318,7 +318,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ", @@ -327,7 +327,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ", @@ -336,7 +336,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID", @@ -345,7 +345,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Allocations; IPQ", @@ -354,7 +354,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Allocations; IRQ", @@ -363,7 +363,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Allocations; IRQ Rejected", @@ -372,7 +372,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Allocations; VFIFO", @@ -381,7 +381,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Internal Starvation Cycles; IPQ", @@ -390,7 +390,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Internal Starvation Cycles; IRQ", @@ -399,7 +399,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ", @@ -408,7 +408,7 @@ "PerPkg": "1", "PublicDescription": "Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; Address Conflict", @@ -417,7 +417,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; Any Reject", @@ -426,7 +426,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; No Egress Credits", @@ -435,7 +435,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Probe Queue Retries; No QPI Credits", @@ -444,7 +444,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; Address Conflict", @@ -452,7 +452,7 @@ "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT", "PerPkg": "1", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; Any Reject", @@ -460,7 +460,7 @@ "EventName": "UNC_C_RxR_IRQ_RETRY.ANY", "PerPkg": "1", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No Egress Credits", @@ -468,7 +468,7 @@ "EventName": "UNC_C_RxR_IRQ_RETRY.FULL", "PerPkg": "1", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No QPI Credits", @@ -476,7 +476,7 @@ "EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS", "PerPkg": "1", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Request Queue Rejects; No RTIDs", @@ -484,7 +484,7 @@ "EventName": "UNC_C_RxR_IRQ_RETRY.RTID", "PerPkg": "1", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; Any Reject", @@ -493,7 +493,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; No Egress Credits", @@ -502,7 +502,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; No IIO Credits", @@ -511,7 +511,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; No QPI Credits", @@ -520,7 +520,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "ISMQ Retries; No RTIDs", @@ -529,7 +529,7 @@ "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Occupancy; IPQ", @@ -538,7 +538,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Occupancy; IRQ", @@ -547,7 +547,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Occupancy; IRQ Rejected", @@ -556,7 +556,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Ingress Occupancy; VFIFO", @@ -565,7 +565,7 @@ "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Evictions", @@ -574,7 +574,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Miss All", @@ -583,7 +583,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0xa", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Miss Opcode Match", @@ -592,7 +592,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID Matched", @@ -601,7 +601,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x48", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID Matched Evictions", @@ -610,7 +610,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x44", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID Matched Miss All", @@ -619,7 +619,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x4a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss", @@ -628,7 +628,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x43", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID and Opcode Matched", @@ -637,7 +637,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x41", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; NID Matched Writebacks", @@ -646,7 +646,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x50", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Opcode Match", @@ -655,7 +655,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Inserts; Writebacks", @@ -664,7 +664,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Any", @@ -673,7 +673,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Evictions", @@ -682,7 +682,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Miss All", @@ -691,7 +691,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0xa", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Miss Opcode Match", @@ -700,7 +700,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x3", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID Matched", @@ -709,7 +709,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x48", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID Matched Evictions", @@ -718,7 +718,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x44", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID Matched", @@ -727,7 +727,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x4a", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss", @@ -736,7 +736,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x43", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; NID and Opcode Matched", @@ -745,7 +745,7 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x41", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "TOR Occupancy; Opcode Match", @@ -754,13 +754,13 @@ "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select 'MISS_OPC_MATCH' and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182)", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "EventCode": "0x4", "EventName": "UNC_C_TxR_ADS_USED", "PerPkg": "1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; AD - Cachebo", @@ -769,7 +769,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.", "UMask": "0x1", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; AD - Corebo", @@ -778,7 +778,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.", "UMask": "0x10", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; AK - Cachebo", @@ -787,7 +787,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; AK - Corebo", @@ -796,7 +796,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.", "UMask": "0x20", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; BL - Cacheno", @@ -805,7 +805,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; BL - Corebo", @@ -814,7 +814,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.", "UMask": "0x40", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Egress Allocations; IV - Cachebo", @@ -823,7 +823,7 @@ "PerPkg": "1", "PublicDescription": "Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.", "UMask": "0x8", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Injection Starvation; Onto AK Ring", @@ -832,7 +832,7 @@ "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.", "UMask": "0x2", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "Injection Starvation; Onto BL Ring", @@ -841,7 +841,7 @@ "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.", "UMask": "0x4", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "HA to iMC Bypass; Not Taken", diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json index b16bb649225d..874f15ea8228 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json @@ -1,11 +1,307 @@ [ + { + "BriefDescription": "Address Match (Conflict) Count; Conflict Merges", + "EventCode": "0x17", + "EventName": "UNC_I_ADDRESS_MATCH.MERGE_COUNT", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Address Match (Conflict) Count; Conflict Stalls", + "EventCode": "0x17", + "EventName": "UNC_I_ADDRESS_MATCH.STALL_COUNT", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Write Ack Pending Occupancy; Any Source", + "EventCode": "0x14", + "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Write Ack Pending Occupancy; Select Source", + "EventCode": "0x14", + "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.SOURCE", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Outstanding Write Ownership Occupancy; Any Source", + "EventCode": "0x13", + "EventName": "UNC_I_CACHE_OWN_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle. This can be used with the write transaction count to calculate the average write latency in the uncore. The occupancy increments when a write request is issued, and decrements when the data is returned.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Outstanding Write Ownership Occupancy; Select Source", + "EventCode": "0x13", + "EventName": "UNC_I_CACHE_OWN_OCCUPANCY.SOURCE", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle. This can be used with the write transaction count to calculate the average write latency in the uncore. The occupancy increments when a write request is issued, and decrements when the data is returned.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Outstanding Read Occupancy; Any Source", + "EventCode": "0x10", + "EventName": "UNC_I_CACHE_READ_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of reads that are outstanding in the uncore in each cycle. This can be used with the read transaction count to calculate the average read latency in the uncore. The occupancy increments when a read request is issued, and decrements when the data is returned.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Outstanding Read Occupancy; Select Source", + "EventCode": "0x10", + "EventName": "UNC_I_CACHE_READ_OCCUPANCY.SOURCE", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of reads that are outstanding in the uncore in each cycle. This can be used with the read transaction count to calculate the average read latency in the uncore. The occupancy increments when a read request is issued, and decrements when the data is returned.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Total Write Cache Occupancy; Any Source", + "EventCode": "0x12", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Total Write Cache Occupancy; Select Source", + "EventCode": "0x12", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Outstanding Write Occupancy; Any Source", + "EventCode": "0x11", + "EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of writes (and write prefetches) that are outstanding in the uncore in each cycle. This can be used with the transaction count event to calculate the average latency in the uncore. The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Outstanding Write Occupancy; Select Source", + "EventCode": "0x11", + "EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.SOURCE", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of writes (and write prefetches) that are outstanding in the uncore in each cycle. This can be used with the transaction count event to calculate the average latency in the uncore. The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Clocks in the IRP", + "EventName": "UNC_I_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Number of clocks in the IRP.", + "Unit": "IRP" + }, + { + "EventCode": "0xB", + "EventName": "UNC_I_RxR_AK_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the AK Ingress is full. This queue is where the IRP receives responses from R2PCIe (the ring).", + "Unit": "IRP" + }, + { + "BriefDescription": "AK Ingress Occupancy", + "EventCode": "0xA", + "EventName": "UNC_I_RxR_AK_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the AK Ingress. This queue is where the IRP receives responses from R2PCIe (the ring).", + "Unit": "IRP" + }, + { + "EventCode": "0xC", + "EventName": "UNC_I_RxR_AK_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the AK Ingress in each cycles. This queue is where the IRP receives responses from R2PCIe (the ring).", + "Unit": "IRP" + }, + { + "EventCode": "0x4", + "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "BL Ingress Occupancy - DRS", + "EventCode": "0x1", + "EventName": "UNC_I_RxR_BL_DRS_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "EventCode": "0x7", + "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "EventCode": "0x5", + "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "BL Ingress Occupancy - NCB", + "EventCode": "0x2", + "EventName": "UNC_I_RxR_BL_NCB_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "EventCode": "0x8", + "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "EventCode": "0x6", + "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "BL Ingress Occupancy - NCS", + "EventCode": "0x3", + "EventName": "UNC_I_RxR_BL_NCS_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "EventCode": "0x9", + "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", + "Unit": "IRP" + }, + { + "BriefDescription": "Tickle Count; Ownership Lost", + "EventCode": "0x16", + "EventName": "UNC_I_TICKLES.LOST_OWNERSHIP", + "PerPkg": "1", + "PublicDescription": "Counts the number of tickles that are received. This is for both explicit (from Cbo) and implicit (internal conflict) tickles.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Tickle Count; Data Returned", + "EventCode": "0x16", + "EventName": "UNC_I_TICKLES.TOP_OF_QUEUE", + "PerPkg": "1", + "PublicDescription": "Counts the number of tickles that are received. This is for both explicit (from Cbo) and implicit (internal conflict) tickles.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Read Prefetches", + "EventCode": "0x15", + "EventName": "UNC_I_TRANSACTIONS.PD_PREFETCHES", + "PerPkg": "1", + "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Reads", + "EventCode": "0x15", + "EventName": "UNC_I_TRANSACTIONS.READS", + "PerPkg": "1", + "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Writes", + "EventCode": "0x15", + "EventName": "UNC_I_TRANSACTIONS.WRITES", + "PerPkg": "1", + "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "No AD Egress Credit Stalls", + "EventCode": "0x18", + "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.", + "Unit": "IRP" + }, + { + "BriefDescription": "No BL Egress Credit Stalls", + "EventCode": "0x19", + "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "EventCode": "0xE", + "EventName": "UNC_I_TxR_DATA_INSERTS_NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "EventCode": "0xF", + "EventName": "UNC_I_TxR_DATA_INSERTS_NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Request Queue Occupancy", + "EventCode": "0xD", + "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.", + "Unit": "IRP" + }, + { + "BriefDescription": "Write Ordering Stalls", + "EventCode": "0x1A", + "EventName": "UNC_I_WRITE_ORDERING_STALL_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when there are pending write ACK's in the switch but the switch->IRP pipeline is not utilized.", + "Unit": "IRP" + }, { "BriefDescription": "Number of qfclks", "EventCode": "0x14", "EventName": "UNC_Q_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "Counts the number of clocks in the QPI LL. This clock runs at 1/8th the 'GT/s' speed of the QPI link. For example, a 8GT/s link will have qfclk or 1GHz. JKT does not support dynamic link speeds, so this frequency is fixed.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Count of CTO Events", @@ -13,7 +309,7 @@ "EventName": "UNC_Q_CTO_COUNT", "PerPkg": "1", "PublicDescription": "Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots. If both slots trigger in a given cycle, the event will increment by 2. You can use edge detect to count the number of cases when both events triggered.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress Credits", @@ -22,7 +318,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egress and RBT", @@ -31,7 +327,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.", "UMask": "0x8", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT Not Set", @@ -40,7 +336,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Success", @@ -49,7 +345,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exclusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Cycles in L1", @@ -57,7 +353,7 @@ "EventName": "UNC_Q_L1_POWER_CYCLES", "PerPkg": "1", "PublicDescription": "Number of QPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a QPI link. Use edge detect to count the number of instances when the QPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Cycles in L0p", @@ -65,7 +361,7 @@ "EventName": "UNC_Q_RxL0P_POWER_CYCLES", "PerPkg": "1", "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Cycles in L0", @@ -73,7 +369,7 @@ "EventName": "UNC_Q_RxL0_POWER_CYCLES", "PerPkg": "1", "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Bypassed", @@ -81,7 +377,7 @@ "EventName": "UNC_Q_RxL_BYPASSED", "PerPkg": "1", "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "CRC Errors Detected; LinkInit", @@ -90,7 +386,7 @@ "PerPkg": "1", "PublicDescription": "Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "CRC Errors Detected; Normal Operations", @@ -99,7 +395,7 @@ "PerPkg": "1", "PublicDescription": "Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "VN0 Credit Consumed; DRS", @@ -108,7 +404,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "VN0 Credit Consumed; HOM", @@ -117,7 +413,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", "UMask": "0x8", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "VN0 Credit Consumed; NCB", @@ -126,7 +422,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "VN0 Credit Consumed; NCS", @@ -135,7 +431,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "VN0 Credit Consumed; NDR", @@ -144,7 +440,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", "UMask": "0x20", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "VN0 Credit Consumed; SNP", @@ -153,7 +449,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", "UMask": "0x10", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "VNA Credit Consumed", @@ -161,7 +457,7 @@ "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA", "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Cycles Not Empty", @@ -169,7 +465,7 @@ "EventName": "UNC_Q_RxL_CYCLES_NE", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 0; Data Tx Flits", @@ -178,7 +474,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 0; Idle and Null Flits", @@ -187,7 +483,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 0; Non-Data protocol Tx Flits", @@ -196,7 +492,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 1; DRS Flits (both Header and Data)", @@ -205,7 +501,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x18", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 1; DRS Data Flits", @@ -214,7 +510,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x8", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 1; DRS Header Flits", @@ -223,7 +519,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x10", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 1; HOM Flits", @@ -232,7 +528,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x6", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 1; HOM Non-Request Flits", @@ -241,7 +537,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 1; HOM Request Flits", @@ -250,7 +546,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 1; SNP Flits", @@ -259,7 +555,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Flits", @@ -268,7 +564,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0xc", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 2; Non-Coherent data Rx Flits", @@ -277,7 +573,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 2; Non-Coherent non-data Rx Flits", @@ -286,7 +582,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x8", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 2; Non-Coherent standard Rx Flits", @@ -295,7 +591,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x10", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AD", @@ -304,7 +600,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Received - Group 2; Non-Data Response Rx Flits - AK", @@ -313,7 +609,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits received from the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations", @@ -321,7 +617,7 @@ "EventName": "UNC_Q_RxL_INSERTS", "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations - DRS", @@ -329,7 +625,7 @@ "EventName": "UNC_Q_RxL_INSERTS_DRS", "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations - HOM", @@ -337,7 +633,7 @@ "EventName": "UNC_Q_RxL_INSERTS_HOM", "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations - NCB", @@ -345,7 +641,7 @@ "EventName": "UNC_Q_RxL_INSERTS_NCB", "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations - NCS", @@ -353,7 +649,7 @@ "EventName": "UNC_Q_RxL_INSERTS_NCS", "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations - NDR", @@ -361,7 +657,7 @@ "EventName": "UNC_Q_RxL_INSERTS_NDR", "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Rx Flit Buffer Allocations - SNP", @@ -369,7 +665,7 @@ "EventName": "UNC_Q_RxL_INSERTS_SNP", "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - All Packets", @@ -377,7 +673,7 @@ "EventName": "UNC_Q_RxL_OCCUPANCY", "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - DRS", @@ -385,7 +681,7 @@ "EventName": "UNC_Q_RxL_OCCUPANCY_DRS", "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - HOM", @@ -393,7 +689,7 @@ "EventName": "UNC_Q_RxL_OCCUPANCY_HOM", "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - NCB", @@ -401,7 +697,7 @@ "EventName": "UNC_Q_RxL_OCCUPANCY_NCB", "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - NCS", @@ -409,7 +705,7 @@ "EventName": "UNC_Q_RxL_OCCUPANCY_NCS", "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - NDR", @@ -417,7 +713,7 @@ "EventName": "UNC_Q_RxL_OCCUPANCY_NDR", "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "RxQ Occupancy - SNP", @@ -425,7 +721,7 @@ "EventName": "UNC_Q_RxL_OCCUPANCY_SNP", "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - HOM", @@ -434,7 +730,7 @@ "PerPkg": "1", "PublicDescription": "Number of stalls trying to send to R3QPI.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - DRS", @@ -443,7 +739,7 @@ "PerPkg": "1", "PublicDescription": "Number of stalls trying to send to R3QPI.", "UMask": "0x8", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - SNP", @@ -452,7 +748,7 @@ "PerPkg": "1", "PublicDescription": "Number of stalls trying to send to R3QPI.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - NDR", @@ -461,7 +757,7 @@ "PerPkg": "1", "PublicDescription": "Number of stalls trying to send to R3QPI.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - NCS", @@ -470,7 +766,7 @@ "PerPkg": "1", "PublicDescription": "Number of stalls trying to send to R3QPI.", "UMask": "0x20", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - NCB", @@ -479,7 +775,7 @@ "PerPkg": "1", "PublicDescription": "Number of stalls trying to send to R3QPI.", "UMask": "0x10", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Stalls Sending to R3QPI; Egress Credits", @@ -488,7 +784,7 @@ "PerPkg": "1", "PublicDescription": "Number of stalls trying to send to R3QPI.", "UMask": "0x40", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Stalls Sending to R3QPI; GV", @@ -497,7 +793,7 @@ "PerPkg": "1", "PublicDescription": "Number of stalls trying to send to R3QPI.", "UMask": "0x80", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Cycles in L0p", @@ -505,7 +801,7 @@ "EventName": "UNC_Q_TxL0P_POWER_CYCLES", "PerPkg": "1", "PublicDescription": "Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Cycles in L0", @@ -513,7 +809,7 @@ "EventName": "UNC_Q_TxL0_POWER_CYCLES", "PerPkg": "1", "PublicDescription": "Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Tx Flit Buffer Bypassed", @@ -521,7 +817,7 @@ "EventName": "UNC_Q_TxL_BYPASSED", "PerPkg": "1", "PublicDescription": "Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is almost full", @@ -530,7 +826,7 @@ "PerPkg": "1", "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is full", @@ -539,7 +835,7 @@ "PerPkg": "1", "PublicDescription": "Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Tx Flit Buffer Cycles not Empty", @@ -547,7 +843,7 @@ "EventName": "UNC_Q_TxL_CYCLES_NE", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits", @@ -555,7 +851,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 0; Idle and Null Flits", @@ -563,7 +859,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 0; Non-Data protocol Tx Flits", @@ -571,7 +867,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both Header and Data)", @@ -579,7 +875,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x18", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits", @@ -587,7 +883,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x8", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits", @@ -595,7 +891,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x10", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 1; HOM Flits", @@ -603,7 +899,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x6", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request Flits", @@ -611,7 +907,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 1; HOM Request Flits", @@ -619,7 +915,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 1; SNP Flits", @@ -627,7 +923,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Bypass Tx Flits", @@ -636,7 +932,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0xc", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 2; Non-Coherent data Tx Flits", @@ -645,7 +941,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x4", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 2; Non-Coherent non-data Tx Flits", @@ -654,7 +950,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x8", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 2; Non-Coherent standard Tx Flits", @@ -663,7 +959,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x10", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AD", @@ -672,7 +968,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x1", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Flits Transferred - Group 2; Non-Data Response Tx Flits - AK", @@ -681,7 +977,7 @@ "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted across the QPI Link. This is one of three 'groups' that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each 'flit' is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four 'fits', each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI 'speed' (for example, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as 'data' bandwidth. For example, when we are transferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual 'data' and an additional 16 bits of other information. To calculate 'data' bandwidth, one should therefore do: data flits * 8B / time.", "UMask": "0x2", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Tx Flit Buffer Allocations", @@ -689,7 +985,7 @@ "EventName": "UNC_Q_TxL_INSERTS", "PerPkg": "1", "PublicDescription": "Number of allocations into the QPI Tx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "Tx Flit Buffer Occupancy", @@ -697,7 +993,7 @@ "EventName": "UNC_Q_TxL_OCCUPANCY", "PerPkg": "1", "PublicDescription": "Accumulates the number of flits in the TxQ. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "VNA Credits Returned", @@ -705,7 +1001,7 @@ "EventName": "UNC_Q_VNA_CREDIT_RETURNS", "PerPkg": "1", "PublicDescription": "Number of VNA credits returned.", - "Unit": "QPI LL" + "Unit": "QPI" }, { "BriefDescription": "VNA Credits Pending Return - Occupancy", @@ -713,6 +1009,779 @@ "EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY", "PerPkg": "1", "PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.", - "Unit": "QPI LL" + "Unit": "QPI" + }, + { + "BriefDescription": "Number of uclks in domain", + "EventCode": "0x1", + "EventName": "UNC_R3_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts the number of uclks in the QPI uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles.", + "Unit": "R3QPI" + }, + { + "BriefDescription": "to IIO BL Credit Acquired", + "EventCode": "0x20", + "EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the NCS/NCB/DRS credit is acquired in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "to IIO BL Credit Acquired", + "EventCode": "0x20", + "EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the NCS/NCB/DRS credit is acquired in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "to IIO BL Credit Acquired", + "EventCode": "0x20", + "EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the NCS/NCB/DRS credit is acquired in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "to IIO BL Credit Rejected", + "EventCode": "0x21", + "EventName": "UNC_R3_IIO_CREDITS_REJECT.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "to IIO BL Credit Rejected", + "EventCode": "0x21", + "EventName": "UNC_R3_IIO_CREDITS_REJECT.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "to IIO BL Credit Rejected", + "EventCode": "0x21", + "EventName": "UNC_R3_IIO_CREDITS_REJECT.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "to IIO BL Credit In Use", + "EventCode": "0x22", + "EventName": "UNC_R3_IIO_CREDITS_USED.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "to IIO BL Credit In Use", + "EventCode": "0x22", + "EventName": "UNC_R3_IIO_CREDITS_USED.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "to IIO BL Credit In Use", + "EventCode": "0x22", + "EventName": "UNC_R3_IIO_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Clockwise and Even", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd", + "EventCode": "0x7", + "EventName": "UNC_R3_RING_AD_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Clockwise and Even", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd", + "EventCode": "0x8", + "EventName": "UNC_R3_RING_AK_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Clockwise and Even", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd", + "EventCode": "0x9", + "EventName": "UNC_R3_RING_BL_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "R3 IV Ring in Use; Any", + "EventCode": "0xa", + "EventName": "UNC_R3_RING_IV_USED.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.", + "UMask": "0xf", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Bypassed", + "EventCode": "0x12", + "EventName": "UNC_R3_RxR_BYPASSED.AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when the Ingress was bypassed and an incoming transaction was bypassed directly across the BGF and into the qfclk domain.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; DRS", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; HOM", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NCB", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NCS", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NDR", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.NDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; SNP", + "EventCode": "0x10", + "EventName": "UNC_R3_RxR_CYCLES_NE.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; DRS", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; HOM", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.HOM", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; NCB", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; NCS", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; NDR", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.NDR", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Allocations; SNP", + "EventCode": "0x11", + "EventName": "UNC_R3_RxR_INSERTS.SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; DRS", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY.DRS", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; HOM", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY.HOM", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; NCB", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY.NCB", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; NCS", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY.NCS", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; NDR", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY.NDR", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Ingress Occupancy Accumulator; SNP", + "EventCode": "0x13", + "EventName": "UNC_R3_RxR_OCCUPANCY.SNP", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Message Class", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Message Class", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class", + "EventCode": "0x37", + "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; DRS Message Class", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.DRS", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; HOM Message Class", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.HOM", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; NCB Message Class", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.NCB", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; NCS Message Class", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; NDR Message Class", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.NDR", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VN0 Credit Used; SNP Message Class", + "EventCode": "0x36", + "EventName": "UNC_R3_VN0_CREDITS_USED.SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA credit Acquisitions", + "EventCode": "0x33", + "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED", + "PerPkg": "1", + "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; DRS Message Class", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.", + "UMask": "0x8", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; HOM Message Class", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.", + "UMask": "0x1", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; NCB Message Class", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.", + "UMask": "0x10", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; NCS Message Class", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.", + "UMask": "0x20", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; NDR Message Class", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.", + "UMask": "0x4", + "Unit": "R3QPI" + }, + { + "BriefDescription": "VNA Credit Reject; SNP Message Class", + "EventCode": "0x34", + "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP", + "PerPkg": "1", + "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.", + "UMask": "0x2", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Cycles with no VNA credits available", + "EventCode": "0x31", + "EventName": "UNC_R3_VNA_CREDIT_CYCLES_OUT", + "PerPkg": "1", + "PublicDescription": "Number of QPI uclk cycles when the transmitted has no VNA credits available and therefore cannot send any requests on this channel. Note that this does not mean that no flits can be transmitted, as those holding VN0 credits will still (potentially) be able to transmit. Generally it is the goal of the uncore that VNA credits should not run out, as this can substantially throttle back useful QPI bandwidth.", + "Unit": "R3QPI" + }, + { + "BriefDescription": "Cycles with 1 or more VNA credits in use", + "EventCode": "0x32", + "EventName": "UNC_R3_VNA_CREDIT_CYCLES_USED", + "PerPkg": "1", + "PublicDescription": "Number of QPI uclk cycles with one or more VNA credits in use. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average number of used VNA credits.", + "Unit": "R3QPI" + }, + { + "EventName": "UNC_U_CLOCKTICKS", + "PerPkg": "1", + "Unit": "UBOX" + }, + { + "BriefDescription": "VLW Received", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "VLW Received", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.INT_PRIO", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "VLW Received", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "VLW Received", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "VLW Received", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.DISABLE", + "PerPkg": "1", + "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.ENABLE", + "PerPkg": "1", + "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE", + "PerPkg": "1", + "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "Filter Match", + "EventCode": "0x41", + "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE", + "PerPkg": "1", + "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "IDI Lock/SplitLock Cycles", + "EventCode": "0x44", + "EventName": "UNC_U_LOCK_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of times an IDI Lock/SplitLock sequence was started", + "Unit": "UBOX" + }, + { + "BriefDescription": "MsgCh Requests by Size; 4B Requests", + "EventCode": "0x47", + "EventName": "UNC_U_MSG_CHNL_SIZE_COUNT.4B", + "PerPkg": "1", + "PublicDescription": "Number of transactions on the message channel filtered by request size. This includes both reads and writes.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "MsgCh Requests by Size; 8B Requests", + "EventCode": "0x47", + "EventName": "UNC_U_MSG_CHNL_SIZE_COUNT.8B", + "PerPkg": "1", + "PublicDescription": "Number of transactions on the message channel filtered by request size. This includes both reads and writes.", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Cycles PHOLD Assert to Ack; ACK to Deassert", + "EventCode": "0x45", + "EventName": "UNC_U_PHOLD_CYCLES.ACK_TO_DEASSERT", + "PerPkg": "1", + "PublicDescription": "PHOLD cycles. Filter from source CoreID.", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", + "EventCode": "0x45", + "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", + "PerPkg": "1", + "PublicDescription": "PHOLD cycles. Filter from source CoreID.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "RACU Request", + "EventCode": "0x46", + "EventName": "UNC_U_RACU_REQUESTS.COUNT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Correctable Machine Check", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.CMC", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one or all cores", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Livelock", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.LIVELOCK", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one or all cores", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; LTError", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.LTERROR", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one or all cores", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Monitor T0", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one or all cores", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Monitor T1", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one or all cores", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Other", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.OTHER", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one or all cores", + "UMask": "0x80", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Trap", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.TRAP", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one or all cores", + "UMask": "0x40", + "Unit": "UBOX" + }, + { + "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check", + "EventCode": "0x43", + "EventName": "UNC_U_U2C_EVENTS.UMC", + "PerPkg": "1", + "PublicDescription": "Events coming from Uncore can be sent to one or all cores", + "UMask": "0x20", + "Unit": "UBOX" } ] diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-io.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-io.json new file mode 100644 index 000000000000..b1ce5f77675e --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-io.json @@ -0,0 +1,324 @@ +[ + { + "BriefDescription": "Number of uclks in domain", + "EventCode": "0x1", + "EventName": "UNC_R2_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts the number of uclks in the R2PCIe uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; DRS", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; NCB", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credit Acquired; NCS", + "EventCode": "0x33", + "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; DRS", + "EventCode": "0x34", + "EventName": "UNC_R2_IIO_CREDITS_REJECT.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; NCB", + "EventCode": "0x34", + "EventName": "UNC_R2_IIO_CREDITS_REJECT.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; NCS", + "EventCode": "0x34", + "EventName": "UNC_R2_IIO_CREDITS_REJECT.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; DRS", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; NCB", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2PCIe IIO Credits in Use; NCS", + "EventCode": "0x32", + "EventName": "UNC_R2_IIO_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise and Even", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd", + "EventCode": "0x7", + "EventName": "UNC_R2_RING_AD_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise and Even", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd", + "EventCode": "0x8", + "EventName": "UNC_R2_RING_AK_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CCW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise and Even", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd", + "EventCode": "0x9", + "EventName": "UNC_R2_RING_BL_USED.CW_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "R2 IV Ring in Use; Any", + "EventCode": "0xa", + "EventName": "UNC_R2_RING_IV_USED.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.", + "UMask": "0xf", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "AK Ingress Bounced", + "EventCode": "0x12", + "EventName": "UNC_R2_RxR_AK_BOUNCES", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; DRS", + "EventCode": "0x10", + "EventName": "UNC_R2_RxR_CYCLES_NE.DRS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x8", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NCB", + "EventCode": "0x10", + "EventName": "UNC_R2_RxR_CYCLES_NE.NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x10", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Ingress Cycles Not Empty; NCS", + "EventCode": "0x10", + "EventName": "UNC_R2_RxR_CYCLES_NE.NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x20", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; AD", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; AK", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.AK", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Full; BL", + "EventCode": "0x25", + "EventName": "UNC_R2_TxR_CYCLES_FULL.BL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; AD", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; AK", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.AK", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress Cycles Not Empty; BL", + "EventCode": "0x23", + "EventName": "UNC_R2_TxR_CYCLES_NE.BL", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x4", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress NACK; AD", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACKS.AD", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that the Egress received a NACK from the ring and could not issue a transaction.", + "UMask": "0x1", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress NACK; AK", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACKS.AK", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that the Egress received a NACK from the ring and could not issue a transaction.", + "UMask": "0x2", + "Unit": "R2PCIe" + }, + { + "BriefDescription": "Egress NACK; BL", + "EventCode": "0x26", + "EventName": "UNC_R2_TxR_NACKS.BL", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that the Egress received a NACK from the ring and could not issue a transaction.", + "UMask": "0x4", + "Unit": "R2PCIe" + } +] diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-other.json b/tools/perf/pmu-events/arch/x86/jaketown/uncore-other.json deleted file mode 100644 index ca727c0e1865..000000000000 --- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-other.json +++ /dev/null @@ -1,1393 +0,0 @@ -[ - { - "BriefDescription": "Address Match (Conflict) Count; Conflict Merges", - "EventCode": "0x17", - "EventName": "UNC_I_ADDRESS_MATCH.MERGE_COUNT", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Address Match (Conflict) Count; Conflict Stalls", - "EventCode": "0x17", - "EventName": "UNC_I_ADDRESS_MATCH.STALL_COUNT", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Write Ack Pending Occupancy; Any Source", - "EventCode": "0x14", - "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.ANY", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Write Ack Pending Occupancy; Select Source", - "EventCode": "0x14", - "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.SOURCE", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Outstanding Write Ownership Occupancy; Any Source", - "EventCode": "0x13", - "EventName": "UNC_I_CACHE_OWN_OCCUPANCY.ANY", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle. This can be used with the write transaction count to calculate the average write latency in the uncore. The occupancy increments when a write request is issued, and decrements when the data is returned.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Outstanding Write Ownership Occupancy; Select Source", - "EventCode": "0x13", - "EventName": "UNC_I_CACHE_OWN_OCCUPANCY.SOURCE", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle. This can be used with the write transaction count to calculate the average write latency in the uncore. The occupancy increments when a write request is issued, and decrements when the data is returned.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Outstanding Read Occupancy; Any Source", - "EventCode": "0x10", - "EventName": "UNC_I_CACHE_READ_OCCUPANCY.ANY", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of reads that are outstanding in the uncore in each cycle. This can be used with the read transaction count to calculate the average read latency in the uncore. The occupancy increments when a read request is issued, and decrements when the data is returned.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Outstanding Read Occupancy; Select Source", - "EventCode": "0x10", - "EventName": "UNC_I_CACHE_READ_OCCUPANCY.SOURCE", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of reads that are outstanding in the uncore in each cycle. This can be used with the read transaction count to calculate the average read latency in the uncore. The occupancy increments when a read request is issued, and decrements when the data is returned.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Total Write Cache Occupancy; Any Source", - "EventCode": "0x12", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Total Write Cache Occupancy; Select Source", - "EventCode": "0x12", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Outstanding Write Occupancy; Any Source", - "EventCode": "0x11", - "EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.ANY", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of writes (and write prefetches) that are outstanding in the uncore in each cycle. This can be used with the transaction count event to calculate the average latency in the uncore. The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Outstanding Write Occupancy; Select Source", - "EventCode": "0x11", - "EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.SOURCE", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of writes (and write prefetches) that are outstanding in the uncore in each cycle. This can be used with the transaction count event to calculate the average latency in the uncore. The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Clocks in the IRP", - "EventName": "UNC_I_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Number of clocks in the IRP.", - "Unit": "IRP" - }, - { - "EventCode": "0xB", - "EventName": "UNC_I_RxR_AK_CYCLES_FULL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the AK Ingress is full. This queue is where the IRP receives responses from R2PCIe (the ring).", - "Unit": "IRP" - }, - { - "BriefDescription": "AK Ingress Occupancy", - "EventCode": "0xA", - "EventName": "UNC_I_RxR_AK_INSERTS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the AK Ingress. This queue is where the IRP receives responses from R2PCIe (the ring).", - "Unit": "IRP" - }, - { - "EventCode": "0xC", - "EventName": "UNC_I_RxR_AK_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of the AK Ingress in each cycles. This queue is where the IRP receives responses from R2PCIe (the ring).", - "Unit": "IRP" - }, - { - "EventCode": "0x4", - "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "BL Ingress Occupancy - DRS", - "EventCode": "0x1", - "EventName": "UNC_I_RxR_BL_DRS_INSERTS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "EventCode": "0x7", - "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "EventCode": "0x5", - "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "BL Ingress Occupancy - NCB", - "EventCode": "0x2", - "EventName": "UNC_I_RxR_BL_NCB_INSERTS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "EventCode": "0x8", - "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "EventCode": "0x6", - "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "BL Ingress Occupancy - NCS", - "EventCode": "0x3", - "EventName": "UNC_I_RxR_BL_NCS_INSERTS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "EventCode": "0x9", - "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes.", - "Unit": "IRP" - }, - { - "BriefDescription": "Tickle Count; Ownership Lost", - "EventCode": "0x16", - "EventName": "UNC_I_TICKLES.LOST_OWNERSHIP", - "PerPkg": "1", - "PublicDescription": "Counts the number of tickles that are received. This is for both explicit (from Cbo) and implicit (internal conflict) tickles.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Tickle Count; Data Returned", - "EventCode": "0x16", - "EventName": "UNC_I_TICKLES.TOP_OF_QUEUE", - "PerPkg": "1", - "PublicDescription": "Counts the number of tickles that are received. This is for both explicit (from Cbo) and implicit (internal conflict) tickles.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Read Prefetches", - "EventCode": "0x15", - "EventName": "UNC_I_TRANSACTIONS.PD_PREFETCHES", - "PerPkg": "1", - "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Reads", - "EventCode": "0x15", - "EventName": "UNC_I_TRANSACTIONS.READS", - "PerPkg": "1", - "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Writes", - "EventCode": "0x15", - "EventName": "UNC_I_TRANSACTIONS.WRITES", - "PerPkg": "1", - "PublicDescription": "Counts the number of 'Inbound' transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "No AD Egress Credit Stalls", - "EventCode": "0x18", - "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES", - "PerPkg": "1", - "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.", - "Unit": "IRP" - }, - { - "BriefDescription": "No BL Egress Credit Stalls", - "EventCode": "0x19", - "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES", - "PerPkg": "1", - "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Read Requests", - "EventCode": "0xE", - "EventName": "UNC_I_TxR_DATA_INSERTS_NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Read Requests", - "EventCode": "0xF", - "EventName": "UNC_I_TxR_DATA_INSERTS_NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Request Queue Occupancy", - "EventCode": "0xD", - "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.", - "Unit": "IRP" - }, - { - "BriefDescription": "Write Ordering Stalls", - "EventCode": "0x1A", - "EventName": "UNC_I_WRITE_ORDERING_STALL_CYCLES", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when there are pending write ACK's in the switch but the switch->IRP pipeline is not utilized.", - "Unit": "IRP" - }, - { - "BriefDescription": "Number of uclks in domain", - "EventCode": "0x1", - "EventName": "UNC_R2_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Counts the number of uclks in the R2PCIe uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles.", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credit Acquired; DRS", - "EventCode": "0x33", - "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credit Acquired; NCB", - "EventCode": "0x33", - "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credit Acquired; NCS", - "EventCode": "0x33", - "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; DRS", - "EventCode": "0x34", - "EventName": "UNC_R2_IIO_CREDITS_REJECT.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; NCB", - "EventCode": "0x34", - "EventName": "UNC_R2_IIO_CREDITS_REJECT.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; NCS", - "EventCode": "0x34", - "EventName": "UNC_R2_IIO_CREDITS_REJECT.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credits in Use; DRS", - "EventCode": "0x32", - "EventName": "UNC_R2_IIO_CREDITS_USED.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credits in Use; NCB", - "EventCode": "0x32", - "EventName": "UNC_R2_IIO_CREDITS_USED.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2PCIe IIO Credits in Use; NCS", - "EventCode": "0x32", - "EventName": "UNC_R2_IIO_CREDITS_USED.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CCW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CCW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Clockwise and Even", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd", - "EventCode": "0x7", - "EventName": "UNC_R2_RING_AD_USED.CW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CCW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CCW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Clockwise and Even", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd", - "EventCode": "0x8", - "EventName": "UNC_R2_RING_AK_USED.CW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CCW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CCW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Clockwise and Even", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd", - "EventCode": "0x9", - "EventName": "UNC_R2_RING_BL_USED.CW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "R2 IV Ring in Use; Any", - "EventCode": "0xa", - "EventName": "UNC_R2_RING_IV_USED.ANY", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.", - "UMask": "0xf", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "AK Ingress Bounced", - "EventCode": "0x12", - "EventName": "UNC_R2_RxR_AK_BOUNCES", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when a request destined for the AK ingress bounced.", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; DRS", - "EventCode": "0x10", - "EventName": "UNC_R2_RxR_CYCLES_NE.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x8", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; NCB", - "EventCode": "0x10", - "EventName": "UNC_R2_RxR_CYCLES_NE.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x10", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; NCS", - "EventCode": "0x10", - "EventName": "UNC_R2_RxR_CYCLES_NE.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x20", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Full; AD", - "EventCode": "0x25", - "EventName": "UNC_R2_TxR_CYCLES_FULL.AD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Full; AK", - "EventCode": "0x25", - "EventName": "UNC_R2_TxR_CYCLES_FULL.AK", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Full; BL", - "EventCode": "0x25", - "EventName": "UNC_R2_TxR_CYCLES_FULL.BL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress buffer is full.", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Not Empty; AD", - "EventCode": "0x23", - "EventName": "UNC_R2_TxR_CYCLES_NE.AD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Not Empty; AK", - "EventCode": "0x23", - "EventName": "UNC_R2_TxR_CYCLES_NE.AK", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress Cycles Not Empty; BL", - "EventCode": "0x23", - "EventName": "UNC_R2_TxR_CYCLES_NE.BL", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress NACK; AD", - "EventCode": "0x26", - "EventName": "UNC_R2_TxR_NACKS.AD", - "PerPkg": "1", - "PublicDescription": "Counts the number of times that the Egress received a NACK from the ring and could not issue a transaction.", - "UMask": "0x1", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress NACK; AK", - "EventCode": "0x26", - "EventName": "UNC_R2_TxR_NACKS.AK", - "PerPkg": "1", - "PublicDescription": "Counts the number of times that the Egress received a NACK from the ring and could not issue a transaction.", - "UMask": "0x2", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Egress NACK; BL", - "EventCode": "0x26", - "EventName": "UNC_R2_TxR_NACKS.BL", - "PerPkg": "1", - "PublicDescription": "Counts the number of times that the Egress received a NACK from the ring and could not issue a transaction.", - "UMask": "0x4", - "Unit": "R2PCIe" - }, - { - "BriefDescription": "Number of uclks in domain", - "EventCode": "0x1", - "EventName": "UNC_R3_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Counts the number of uclks in the QPI uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles.", - "Unit": "R3QPI" - }, - { - "BriefDescription": "to IIO BL Credit Acquired", - "EventCode": "0x20", - "EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the NCS/NCB/DRS credit is acquired in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "to IIO BL Credit Acquired", - "EventCode": "0x20", - "EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the NCS/NCB/DRS credit is acquired in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "to IIO BL Credit Acquired", - "EventCode": "0x20", - "EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the NCS/NCB/DRS credit is acquired in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "to IIO BL Credit Rejected", - "EventCode": "0x21", - "EventName": "UNC_R3_IIO_CREDITS_REJECT.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "to IIO BL Credit Rejected", - "EventCode": "0x21", - "EventName": "UNC_R3_IIO_CREDITS_REJECT.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "to IIO BL Credit Rejected", - "EventCode": "0x21", - "EventName": "UNC_R3_IIO_CREDITS_REJECT.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of times that a request attempted to acquire an NCS/NCB/DRS credit in the QPI for sending messages on BL to the IIO but was rejected because no credit was available. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "to IIO BL Credit In Use", - "EventCode": "0x22", - "EventName": "UNC_R3_IIO_CREDITS_USED.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "to IIO BL Credit In Use", - "EventCode": "0x22", - "EventName": "UNC_R3_IIO_CREDITS_USED.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "to IIO BL Credit In Use", - "EventCode": "0x22", - "EventName": "UNC_R3_IIO_CREDITS_USED.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the NCS/NCB/DRS credit is in use in the QPI for sending messages on BL to the IIO. There is one credit for each of these three message classes (three credits total). NCS is used for reads to PCIe space, NCB is used for transferring data without coherency, and DRS is used for transferring data with coherency (cacheable PCI transactions). This event can only track one message class at a time.", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even", - "EventCode": "0x7", - "EventName": "UNC_R3_RING_AD_USED.CCW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd", - "EventCode": "0x7", - "EventName": "UNC_R3_RING_AD_USED.CCW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AD Ring in Use; Clockwise and Even", - "EventCode": "0x7", - "EventName": "UNC_R3_RING_AD_USED.CW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd", - "EventCode": "0x7", - "EventName": "UNC_R3_RING_AD_USED.CW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even", - "EventCode": "0x8", - "EventName": "UNC_R3_RING_AK_USED.CCW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd", - "EventCode": "0x8", - "EventName": "UNC_R3_RING_AK_USED.CCW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AK Ring in Use; Clockwise and Even", - "EventCode": "0x8", - "EventName": "UNC_R3_RING_AK_USED.CW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd", - "EventCode": "0x8", - "EventName": "UNC_R3_RING_AK_USED.CW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even", - "EventCode": "0x9", - "EventName": "UNC_R3_RING_BL_USED.CCW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd", - "EventCode": "0x9", - "EventName": "UNC_R3_RING_BL_USED.CCW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 BL Ring in Use; Clockwise and Even", - "EventCode": "0x9", - "EventName": "UNC_R3_RING_BL_USED.CW_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd", - "EventCode": "0x9", - "EventName": "UNC_R3_RING_BL_USED.CW_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "R3 IV Ring in Use; Any", - "EventCode": "0xa", - "EventName": "UNC_R3_RING_IV_USED.ANY", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.", - "UMask": "0xf", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Bypassed", - "EventCode": "0x12", - "EventName": "UNC_R3_RxR_BYPASSED.AD", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when the Ingress was bypassed and an incoming transaction was bypassed directly across the BGF and into the qfclk domain.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; DRS", - "EventCode": "0x10", - "EventName": "UNC_R3_RxR_CYCLES_NE.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; HOM", - "EventCode": "0x10", - "EventName": "UNC_R3_RxR_CYCLES_NE.HOM", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; NCB", - "EventCode": "0x10", - "EventName": "UNC_R3_RxR_CYCLES_NE.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; NCS", - "EventCode": "0x10", - "EventName": "UNC_R3_RxR_CYCLES_NE.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; NDR", - "EventCode": "0x10", - "EventName": "UNC_R3_RxR_CYCLES_NE.NDR", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Cycles Not Empty; SNP", - "EventCode": "0x10", - "EventName": "UNC_R3_RxR_CYCLES_NE.SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Allocations; DRS", - "EventCode": "0x11", - "EventName": "UNC_R3_RxR_INSERTS.DRS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Allocations; HOM", - "EventCode": "0x11", - "EventName": "UNC_R3_RxR_INSERTS.HOM", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Allocations; NCB", - "EventCode": "0x11", - "EventName": "UNC_R3_RxR_INSERTS.NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Allocations; NCS", - "EventCode": "0x11", - "EventName": "UNC_R3_RxR_INSERTS.NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Allocations; NDR", - "EventCode": "0x11", - "EventName": "UNC_R3_RxR_INSERTS.NDR", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Allocations; SNP", - "EventCode": "0x11", - "EventName": "UNC_R3_RxR_INSERTS.SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Occupancy Accumulator; DRS", - "EventCode": "0x13", - "EventName": "UNC_R3_RxR_OCCUPANCY.DRS", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Occupancy Accumulator; HOM", - "EventCode": "0x13", - "EventName": "UNC_R3_RxR_OCCUPANCY.HOM", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Occupancy Accumulator; NCB", - "EventCode": "0x13", - "EventName": "UNC_R3_RxR_OCCUPANCY.NCB", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Occupancy Accumulator; NCS", - "EventCode": "0x13", - "EventName": "UNC_R3_RxR_OCCUPANCY.NCS", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Occupancy Accumulator; NDR", - "EventCode": "0x13", - "EventName": "UNC_R3_RxR_OCCUPANCY.NDR", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Ingress Occupancy Accumulator; SNP", - "EventCode": "0x13", - "EventName": "UNC_R3_RxR_OCCUPANCY.SNP", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Message Class", - "EventCode": "0x37", - "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Message Class", - "EventCode": "0x37", - "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Message Class", - "EventCode": "0x37", - "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Message Class", - "EventCode": "0x37", - "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Message Class", - "EventCode": "0x37", - "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Message Class", - "EventCode": "0x37", - "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP", - "PerPkg": "1", - "PublicDescription": "Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Used; DRS Message Class", - "EventCode": "0x36", - "EventName": "UNC_R3_VN0_CREDITS_USED.DRS", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Used; HOM Message Class", - "EventCode": "0x36", - "EventName": "UNC_R3_VN0_CREDITS_USED.HOM", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Used; NCB Message Class", - "EventCode": "0x36", - "EventName": "UNC_R3_VN0_CREDITS_USED.NCB", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Used; NCS Message Class", - "EventCode": "0x36", - "EventName": "UNC_R3_VN0_CREDITS_USED.NCS", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Used; NDR Message Class", - "EventCode": "0x36", - "EventName": "UNC_R3_VN0_CREDITS_USED.NDR", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VN0 Credit Used; SNP Message Class", - "EventCode": "0x36", - "EventName": "UNC_R3_VN0_CREDITS_USED.SNP", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA credit Acquisitions", - "EventCode": "0x33", - "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED", - "PerPkg": "1", - "PublicDescription": "Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credits from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transferred). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transferred in a given message class using an qfclk event.", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA Credit Reject; DRS Message Class", - "EventCode": "0x34", - "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS", - "PerPkg": "1", - "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.", - "UMask": "0x8", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA Credit Reject; HOM Message Class", - "EventCode": "0x34", - "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM", - "PerPkg": "1", - "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.", - "UMask": "0x1", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA Credit Reject; NCB Message Class", - "EventCode": "0x34", - "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB", - "PerPkg": "1", - "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.", - "UMask": "0x10", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA Credit Reject; NCS Message Class", - "EventCode": "0x34", - "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS", - "PerPkg": "1", - "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.", - "UMask": "0x20", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA Credit Reject; NDR Message Class", - "EventCode": "0x34", - "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR", - "PerPkg": "1", - "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.", - "UMask": "0x4", - "Unit": "R3QPI" - }, - { - "BriefDescription": "VNA Credit Reject; SNP Message Class", - "EventCode": "0x34", - "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP", - "PerPkg": "1", - "PublicDescription": "Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.", - "UMask": "0x2", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Cycles with no VNA credits available", - "EventCode": "0x31", - "EventName": "UNC_R3_VNA_CREDIT_CYCLES_OUT", - "PerPkg": "1", - "PublicDescription": "Number of QPI uclk cycles when the transmitted has no VNA credits available and therefore cannot send any requests on this channel. Note that this does not mean that no flits can be transmitted, as those holding VN0 credits will still (potentially) be able to transmit. Generally it is the goal of the uncore that VNA credits should not run out, as this can substantially throttle back useful QPI bandwidth.", - "Unit": "R3QPI" - }, - { - "BriefDescription": "Cycles with 1 or more VNA credits in use", - "EventCode": "0x32", - "EventName": "UNC_R3_VNA_CREDIT_CYCLES_USED", - "PerPkg": "1", - "PublicDescription": "Number of QPI uclk cycles with one or more VNA credits in use. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average number of used VNA credits.", - "Unit": "R3QPI" - }, - { - "EventName": "UNC_U_CLOCKTICKS", - "PerPkg": "1", - "Unit": "UBOX" - }, - { - "BriefDescription": "VLW Received", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", - "PerPkg": "1", - "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x8", - "Unit": "UBOX" - }, - { - "BriefDescription": "VLW Received", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.INT_PRIO", - "PerPkg": "1", - "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x10", - "Unit": "UBOX" - }, - { - "BriefDescription": "VLW Received", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", - "PerPkg": "1", - "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x4", - "Unit": "UBOX" - }, - { - "BriefDescription": "VLW Received", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", - "PerPkg": "1", - "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "VLW Received", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", - "PerPkg": "1", - "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "Filter Match", - "EventCode": "0x41", - "EventName": "UNC_U_FILTER_MATCH.DISABLE", - "PerPkg": "1", - "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "Filter Match", - "EventCode": "0x41", - "EventName": "UNC_U_FILTER_MATCH.ENABLE", - "PerPkg": "1", - "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "Filter Match", - "EventCode": "0x41", - "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE", - "PerPkg": "1", - "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x8", - "Unit": "UBOX" - }, - { - "BriefDescription": "Filter Match", - "EventCode": "0x41", - "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE", - "PerPkg": "1", - "PublicDescription": "Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID.", - "UMask": "0x4", - "Unit": "UBOX" - }, - { - "BriefDescription": "IDI Lock/SplitLock Cycles", - "EventCode": "0x44", - "EventName": "UNC_U_LOCK_CYCLES", - "PerPkg": "1", - "PublicDescription": "Number of times an IDI Lock/SplitLock sequence was started", - "Unit": "UBOX" - }, - { - "BriefDescription": "MsgCh Requests by Size; 4B Requests", - "EventCode": "0x47", - "EventName": "UNC_U_MSG_CHNL_SIZE_COUNT.4B", - "PerPkg": "1", - "PublicDescription": "Number of transactions on the message channel filtered by request size. This includes both reads and writes.", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "MsgCh Requests by Size; 8B Requests", - "EventCode": "0x47", - "EventName": "UNC_U_MSG_CHNL_SIZE_COUNT.8B", - "PerPkg": "1", - "PublicDescription": "Number of transactions on the message channel filtered by request size. This includes both reads and writes.", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "Cycles PHOLD Assert to Ack; ACK to Deassert", - "EventCode": "0x45", - "EventName": "UNC_U_PHOLD_CYCLES.ACK_TO_DEASSERT", - "PerPkg": "1", - "PublicDescription": "PHOLD cycles. Filter from source CoreID.", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", - "EventCode": "0x45", - "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", - "PerPkg": "1", - "PublicDescription": "PHOLD cycles. Filter from source CoreID.", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "RACU Request", - "EventCode": "0x46", - "EventName": "UNC_U_RACU_REQUESTS.COUNT", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Correctable Machine Check", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.CMC", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores", - "UMask": "0x10", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Livelock", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.LIVELOCK", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores", - "UMask": "0x4", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; LTError", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.LTERROR", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores", - "UMask": "0x8", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Monitor T0", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Monitor T1", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Other", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.OTHER", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores", - "UMask": "0x80", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Trap", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.TRAP", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores", - "UMask": "0x40", - "Unit": "UBOX" - }, - { - "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Check", - "EventCode": "0x43", - "EventName": "UNC_U_U2C_EVENTS.UMC", - "PerPkg": "1", - "PublicDescription": "Events coming from Uncore can be sent to one or all cores", - "UMask": "0x20", - "Unit": "UBOX" - } -] -- cgit v1.2.3-58-ga151 From 6c3566c594505d1e3d1d49f2c0a8dac61441505c Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 13 Apr 2023 06:29:44 -0700 Subject: perf vendor events intel: Fix uncore topics for knightslanding Remove 'uncore-other' topic classification, move to cache, io and memory. Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230413132949.3487664-17-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/x86/knightslanding/uncore-cache.json | 3365 ++++++++++++++++++ .../arch/x86/knightslanding/uncore-io.json | 194 ++ .../arch/x86/knightslanding/uncore-memory.json | 68 + .../arch/x86/knightslanding/uncore-other.json | 3625 -------------------- 4 files changed, 3627 insertions(+), 3625 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/knightslanding/uncore-cache.json create mode 100644 tools/perf/pmu-events/arch/x86/knightslanding/uncore-io.json delete mode 100644 tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-cache.json b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-cache.json new file mode 100644 index 000000000000..1b8dcfa5461c --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-cache.json @@ -0,0 +1,3365 @@ +[ + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IPQ_HIT", + "PerPkg": "1", + "UMask": "0x18", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IPQ_MISS", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IRQ_HIT", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IRQ_MISS", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ or PRQ", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.LOC_ALL", + "PerPkg": "1", + "UMask": "0x37", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -PRQ", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.PRQ_HIT", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -PRQ", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.PRQ_MISS", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 0", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 1", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 2", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 3", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 4", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 5", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 6", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 7", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 0-7", + "EventCode": "0x81", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 8", + "EventCode": "0x81", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED_EXT.TGR8", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 0", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 1", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 2", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 3", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 4", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 5", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 6", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 7", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 0-7", + "EventCode": "0x83", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 8", + "EventCode": "0x83", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY_EXT.TGR8", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 0", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 1", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 2", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 3", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 4", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 5", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 6", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 7", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 0-7", + "EventCode": "0x89", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 8", + "EventCode": "0x89", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED_EXT.TGR8", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 0", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 1", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 2", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 3", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 4", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 5", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 6", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 7", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 0-7", + "EventCode": "0x8B", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 8", + "EventCode": "0x8B", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY_EXT.TGR8", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 0", + "EventCode": "0xD0", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 1", + "EventCode": "0xD0", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 2", + "EventCode": "0xD0", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 3", + "EventCode": "0xD0", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 4", + "EventCode": "0xD0", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 5", + "EventCode": "0xD0", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 6", + "EventCode": "0xD0", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 7", + "EventCode": "0xD0", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 0-7", + "EventCode": "0xD1", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.ANY_OF_TGR0_THRU_TGR7", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 8", + "EventCode": "0xD1", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.TGR8", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 0", + "EventCode": "0xD4", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 1", + "EventCode": "0xD4", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 2", + "EventCode": "0xD4", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 3", + "EventCode": "0xD4", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 4", + "EventCode": "0xD4", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 5", + "EventCode": "0xD4", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 6", + "EventCode": "0xD4", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 7", + "EventCode": "0xD4", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 0-7", + "EventCode": "0xD5", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.ANY_OF_TGR0_THRU_TGR7", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 8", + "EventCode": "0xD5", + "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.TGR8", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 0", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 1", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 2", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 3", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 4", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 5", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 6", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 7", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 0-7", + "EventCode": "0x85", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 8", + "EventCode": "0x85", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED_EXT.TGR8", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 0", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 1", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 2", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 3", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 4", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 5", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 6", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 7", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 0-7", + "EventCode": "0x87", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 8", + "EventCode": "0x87", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY_EXT.TGR8", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 0", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 1", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 2", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 3", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 4", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 5", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 6", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 7", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 0-7", + "EventCode": "0x8D", + "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 8", + "EventCode": "0x8D", + "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED_EXT.TGR8", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 0", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 1", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 2", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 3", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 4", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 5", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 6", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 7", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 0-7", + "EventCode": "0x8F", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 8", + "EventCode": "0x8F", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY_EXT.TGR8", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 0", + "EventCode": "0xD2", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 1", + "EventCode": "0xD2", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 2", + "EventCode": "0xD2", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 3", + "EventCode": "0xD2", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 4", + "EventCode": "0xD2", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 5", + "EventCode": "0xD2", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 6", + "EventCode": "0xD2", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 7", + "EventCode": "0xD2", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 0-7", + "EventCode": "0xD3", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.ANY_OF_TGR0_THRU_TGR7", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 8", + "EventCode": "0xD3", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.TGR8", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 0", + "EventCode": "0xD6", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 1", + "EventCode": "0xD6", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 2", + "EventCode": "0xD6", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 3", + "EventCode": "0xD6", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 4", + "EventCode": "0xD6", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 5", + "EventCode": "0xD6", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 6", + "EventCode": "0xD6", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR6", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 7", + "EventCode": "0xD6", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR7", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 0-7", + "EventCode": "0xD7", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.ANY_OF_TGR0_THRU_TGR7", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Transgress Credits For Transgress 8", + "EventCode": "0xD7", + "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.TGR8", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.", + "EventCode": "0x37", + "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.E_STATE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.", + "EventCode": "0x37", + "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.F_STATE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized that Match NID", + "EventCode": "0x37", + "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.LOCAL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Read transactions", + "EventCode": "0x37", + "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.M_STATE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized that Does Not Match NID", + "EventCode": "0x37", + "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.REMOTE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Filters for only snoop requests coming from the remote socket(s) through the IPQ.", + "EventCode": "0x37", + "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.S_STATE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Uncore Clocks", + "EventCode": "0xC0", + "EventName": "UNC_H_CLOCK", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used", + "EventCode": "0x9D", + "EventName": "UNC_H_EGRESS_HORZ_ADS_USED.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used", + "EventCode": "0x9D", + "EventName": "UNC_H_EGRESS_HORZ_ADS_USED.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used", + "EventCode": "0x9D", + "EventName": "UNC_H_EGRESS_HORZ_ADS_USED.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Bypass. AD ring", + "EventCode": "0x9F", + "EventName": "UNC_H_EGRESS_HORZ_BYPASS.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Bypass. AK ring", + "EventCode": "0x9F", + "EventName": "UNC_H_EGRESS_HORZ_BYPASS.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Bypass. BL ring", + "EventCode": "0x9F", + "EventName": "UNC_H_EGRESS_HORZ_BYPASS.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Bypass. IV ring", + "EventCode": "0x9F", + "EventName": "UNC_H_EGRESS_HORZ_BYPASS.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full AD", + "EventCode": "0x96", + "EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full AK", + "EventCode": "0x96", + "EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full BL", + "EventCode": "0x96", + "EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full IV", + "EventCode": "0x96", + "EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty AD", + "EventCode": "0x97", + "EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty AK", + "EventCode": "0x97", + "EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty BL", + "EventCode": "0x97", + "EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty IV", + "EventCode": "0x97", + "EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts AD", + "EventCode": "0x95", + "EventName": "UNC_H_EGRESS_HORZ_INSERTS.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts AK", + "EventCode": "0x95", + "EventName": "UNC_H_EGRESS_HORZ_INSERTS.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts BL", + "EventCode": "0x95", + "EventName": "UNC_H_EGRESS_HORZ_INSERTS.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts IV", + "EventCode": "0x95", + "EventName": "UNC_H_EGRESS_HORZ_INSERTS.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs", + "EventCode": "0x99", + "EventName": "UNC_H_EGRESS_HORZ_NACK.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs", + "EventCode": "0x99", + "EventName": "UNC_H_EGRESS_HORZ_NACK.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs", + "EventCode": "0x99", + "EventName": "UNC_H_EGRESS_HORZ_NACK.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs", + "EventCode": "0x99", + "EventName": "UNC_H_EGRESS_HORZ_NACK.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy AD", + "EventCode": "0x94", + "EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy AK", + "EventCode": "0x94", + "EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy BL", + "EventCode": "0x94", + "EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy IV", + "EventCode": "0x94", + "EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation", + "EventCode": "0x9B", + "EventName": "UNC_H_EGRESS_HORZ_STARVED.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation", + "EventCode": "0x9B", + "EventName": "UNC_H_EGRESS_HORZ_STARVED.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation", + "EventCode": "0x9B", + "EventName": "UNC_H_EGRESS_HORZ_STARVED.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation", + "EventCode": "0x9B", + "EventName": "UNC_H_EGRESS_HORZ_STARVED.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "EventCode": "0xAE", + "EventName": "UNC_H_EGRESS_ORDERING.IV_SNP_GO_DN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "EventCode": "0xAE", + "EventName": "UNC_H_EGRESS_ORDERING.IV_SNP_GO_UP", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used", + "EventCode": "0x9C", + "EventName": "UNC_H_EGRESS_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used", + "EventCode": "0x9C", + "EventName": "UNC_H_EGRESS_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used", + "EventCode": "0x9C", + "EventName": "UNC_H_EGRESS_VERT_ADS_USED.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used", + "EventCode": "0x9C", + "EventName": "UNC_H_EGRESS_VERT_ADS_USED.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used", + "EventCode": "0x9C", + "EventName": "UNC_H_EGRESS_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used", + "EventCode": "0x9C", + "EventName": "UNC_H_EGRESS_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Bypass. AD ring agent 0", + "EventCode": "0x9E", + "EventName": "UNC_H_EGRESS_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Bypass. AD ring agent 1", + "EventCode": "0x9E", + "EventName": "UNC_H_EGRESS_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Bypass. AK ring agent 0", + "EventCode": "0x9E", + "EventName": "UNC_H_EGRESS_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Bypass. AK ring agent 1", + "EventCode": "0x9E", + "EventName": "UNC_H_EGRESS_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Bypass. BL ring agent 0", + "EventCode": "0x9E", + "EventName": "UNC_H_EGRESS_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Bypass. BL ring agent 1", + "EventCode": "0x9E", + "EventName": "UNC_H_EGRESS_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Bypass. IV ring agent 0", + "EventCode": "0x9E", + "EventName": "UNC_H_EGRESS_VERT_BYPASS.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AD - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AD - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AK - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AK - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full BL - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full BL - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full IV - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty AD - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty AD - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty AK - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty AK - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty BL - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty BL - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty IV - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations AD - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_H_EGRESS_VERT_INSERTS.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations AD - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_H_EGRESS_VERT_INSERTS.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations AK - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_H_EGRESS_VERT_INSERTS.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations AK - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_H_EGRESS_VERT_INSERTS.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations BL - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_H_EGRESS_VERT_INSERTS.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations BL - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_H_EGRESS_VERT_INSERTS.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations IV - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_H_EGRESS_VERT_INSERTS.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs", + "EventCode": "0x98", + "EventName": "UNC_H_EGRESS_VERT_NACK.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs", + "EventCode": "0x98", + "EventName": "UNC_H_EGRESS_VERT_NACK.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs Onto AK Ring", + "EventCode": "0x98", + "EventName": "UNC_H_EGRESS_VERT_NACK.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs", + "EventCode": "0x98", + "EventName": "UNC_H_EGRESS_VERT_NACK.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs Onto BL Ring", + "EventCode": "0x98", + "EventName": "UNC_H_EGRESS_VERT_NACK.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs", + "EventCode": "0x98", + "EventName": "UNC_H_EGRESS_VERT_NACK.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs", + "EventCode": "0x98", + "EventName": "UNC_H_EGRESS_VERT_NACK.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy AD - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy AD - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy AK - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy AK - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy BL - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy BL - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy IV - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation", + "EventCode": "0x9A", + "EventName": "UNC_H_EGRESS_VERT_STARVED.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation", + "EventCode": "0x9A", + "EventName": "UNC_H_EGRESS_VERT_STARVED.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation Onto AK Ring", + "EventCode": "0x9A", + "EventName": "UNC_H_EGRESS_VERT_STARVED.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation", + "EventCode": "0x9A", + "EventName": "UNC_H_EGRESS_VERT_STARVED.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation Onto BL Ring", + "EventCode": "0x9A", + "EventName": "UNC_H_EGRESS_VERT_STARVED.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation", + "EventCode": "0x9A", + "EventName": "UNC_H_EGRESS_VERT_STARVED.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation", + "EventCode": "0x9A", + "EventName": "UNC_H_EGRESS_VERT_STARVED.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts cycles source throttling is asserted - horizontal", + "EventCode": "0xA5", + "EventName": "UNC_H_FAST_ASSERTED.HORZ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts cycles source throttling is asserted - vertical", + "EventCode": "0xA5", + "EventName": "UNC_H_FAST_ASSERTED.VERT", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Left and Even", + "EventCode": "0xA7", + "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Left and Odd", + "EventCode": "0xA7", + "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Right and Even", + "EventCode": "0xA7", + "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Right and Odd", + "EventCode": "0xA7", + "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Left and Even", + "EventCode": "0xA9", + "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Left and Odd", + "EventCode": "0xA9", + "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Right and Even", + "EventCode": "0xA9", + "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Right and Odd", + "EventCode": "0xA9", + "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Left and Even", + "EventCode": "0xAB", + "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Left and Odd", + "EventCode": "0xAB", + "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Right and Even", + "EventCode": "0xAB", + "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Right and Odd", + "EventCode": "0xAB", + "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop - Left", + "EventCode": "0xAD", + "EventName": "UNC_H_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop - Right", + "EventCode": "0xAD", + "EventName": "UNC_H_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IPQ", + "EventCode": "0x13", + "EventName": "UNC_H_INGRESS_INSERTS.IPQ", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IRQ", + "EventCode": "0x13", + "EventName": "UNC_H_INGRESS_INSERTS.IRQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IRQ Rejected", + "EventCode": "0x13", + "EventName": "UNC_H_INGRESS_INSERTS.IRQ_REJ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - PRQ", + "EventCode": "0x13", + "EventName": "UNC_H_INGRESS_INSERTS.PRQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - PRQ Rejected", + "EventCode": "0x13", + "EventName": "UNC_H_INGRESS_INSERTS.PRQ_REJ", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles with the IPQ in Internal Starvation.", + "EventCode": "0x14", + "EventName": "UNC_H_INGRESS_INT_STARVED.IPQ", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles with the IRQ in Internal Starvation.", + "EventCode": "0x14", + "EventName": "UNC_H_INGRESS_INT_STARVED.IRQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles with the ISMQ in Internal Starvation.", + "EventCode": "0x14", + "EventName": "UNC_H_INGRESS_INT_STARVED.ISMQ", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress internal starvation cycles. Counts cycles in internal starvation. This occurs when one or more of the entries in the ingress queue are being starved out by other entries in the queue.", + "EventCode": "0x14", + "EventName": "UNC_H_INGRESS_INT_STARVED.PRQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - IPQ", + "EventCode": "0x11", + "EventName": "UNC_H_INGRESS_OCCUPANCY.IPQ", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - IRQ", + "EventCode": "0x11", + "EventName": "UNC_H_INGRESS_OCCUPANCY.IRQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - IRQ Rejected", + "EventCode": "0x11", + "EventName": "UNC_H_INGRESS_OCCUPANCY.IRQ_REJ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - PRQ", + "EventCode": "0x11", + "EventName": "UNC_H_INGRESS_OCCUPANCY.PRQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - PRQ Rejected", + "EventCode": "0x11", + "EventName": "UNC_H_INGRESS_OCCUPANCY.PRQ_REJ", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "EventCode": "0x22", + "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "EventCode": "0x22", + "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "EventCode": "0x22", + "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "EventCode": "0x22", + "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "EventCode": "0x22", + "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "EventCode": "0x22", + "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "EventCode": "0x22", + "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "EventCode": "0x22", + "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "EventCode": "0x23", + "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "EventCode": "0x23", + "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.ANY_REJECT_IPQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "EventCode": "0x23", + "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "EventCode": "0x23", + "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects", + "EventCode": "0x23", + "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x18", + "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x18", + "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x18", + "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x18", + "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x18", + "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x18", + "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x18", + "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x18", + "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x19", + "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x19", + "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.ANY_REJECT_IRQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x19", + "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x19", + "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x19", + "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects", + "EventCode": "0x24", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects", + "EventCode": "0x24", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects", + "EventCode": "0x24", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects", + "EventCode": "0x24", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects", + "EventCode": "0x24", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects", + "EventCode": "0x24", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects", + "EventCode": "0x24", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects", + "EventCode": "0x24", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries", + "EventCode": "0x2C", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries", + "EventCode": "0x2C", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries", + "EventCode": "0x2C", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries", + "EventCode": "0x2C", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries", + "EventCode": "0x2C", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries", + "EventCode": "0x2C", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries", + "EventCode": "0x2C", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries", + "EventCode": "0x2C", + "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "EventCode": "0x2E", + "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "EventCode": "0x2E", + "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "EventCode": "0x2E", + "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "EventCode": "0x2E", + "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "EventCode": "0x2E", + "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "EventCode": "0x2E", + "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "EventCode": "0x2E", + "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "EventCode": "0x2E", + "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "EventCode": "0x2F", + "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "EventCode": "0x2F", + "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.ANY_REJECT_IRQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "EventCode": "0x2F", + "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "EventCode": "0x2F", + "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Queue Retries", + "EventCode": "0x2F", + "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x20", + "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x20", + "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x20", + "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x20", + "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x20", + "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x20", + "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x20", + "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x20", + "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x21", + "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x21", + "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.ANY_REJECT_IRQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x21", + "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x21", + "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Request Queue Rejects", + "EventCode": "0x21", + "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "EventCode": "0x2A", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "EventCode": "0x2A", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "EventCode": "0x2A", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "EventCode": "0x2A", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "EventCode": "0x2A", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "EventCode": "0x2A", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "EventCode": "0x2A", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "EventCode": "0x2A", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "EventCode": "0x2B", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "EventCode": "0x2B", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.ANY_REJECT_IRQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "EventCode": "0x2B", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "EventCode": "0x2B", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "EventCode": "0x2B", + "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Miscellaneous events in the Cbo. CV0 Prefetch Miss", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.CV0_PREF_MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Miscellaneous events in the Cbo. CV0 Prefetch Victim", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.CV0_PREF_VIC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Miscellaneous events in the Cbo. RFO HitS", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.RFO_HIT_S", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Miscellaneous events in the Cbo. Silent Snoop Eviction", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.RSPI_WAS_FSE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Miscellaneous events in the Cbo. Write Combining Aliasing", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.WC_ALIASING", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Number of incoming messages from the Horizontal ring that were bounced, by ring type.", + "EventCode": "0xA1", + "EventName": "UNC_H_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Number of incoming messages from the Horizontal ring that were bounced, by ring type - Acknowledgements to core", + "EventCode": "0xA1", + "EventName": "UNC_H_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Number of incoming messages from the Horizontal ring that were bounced, by ring type - Data Responses to core.", + "EventCode": "0xA1", + "EventName": "UNC_H_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Number of incoming messages from the Horizontal ring that were bounced, by ring type - Snoops of processor's cache.", + "EventCode": "0xA1", + "EventName": "UNC_H_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Number of incoming messages from the Vertical ring that were bounced, by ring type.", + "EventCode": "0xA0", + "EventName": "UNC_H_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Number of incoming messages from the Vertical ring that were bounced, by ring type - Acknowledgements to core", + "EventCode": "0xA0", + "EventName": "UNC_H_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Number of incoming messages from the Vertical ring that were bounced, by ring type - Data Responses to core.", + "EventCode": "0xA0", + "EventName": "UNC_H_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Number of incoming messages from the Vertical ring that were bounced, by ring type - Snoops of processor's cache.", + "EventCode": "0xA0", + "EventName": "UNC_H_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal ring sink starvation count - AD ring", + "EventCode": "0xA3", + "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal ring sink starvation count - AK ring", + "EventCode": "0xA3", + "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal ring sink starvation count - BL ring", + "EventCode": "0xA3", + "EventName": "UNC_H_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal ring sink starvation count - IV ring", + "EventCode": "0xA3", + "EventName": "UNC_H_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical ring sink starvation count - AD ring", + "EventCode": "0xA2", + "EventName": "UNC_H_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical ring sink starvation count - AK ring", + "EventCode": "0xA2", + "EventName": "UNC_H_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical ring sink starvation count - BL ring", + "EventCode": "0xA2", + "EventName": "UNC_H_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical ring sink starvation count - IV ring", + "EventCode": "0xA2", + "EventName": "UNC_H_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts cycles in throttle mode.", + "EventCode": "0xA4", + "EventName": "UNC_H_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.", + "EventCode": "0x34", + "EventName": "UNC_H_SF_LOOKUP.ANY", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Read transactions", + "EventCode": "0x34", + "EventName": "UNC_H_SF_LOOKUP.DATA_READ", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Filters for only snoop requests coming from the remote socket(s) through the IPQ.", + "EventCode": "0x34", + "EventName": "UNC_H_SF_LOOKUP.REMOTE_SNOOP", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.", + "EventCode": "0x34", + "EventName": "UNC_H_SF_LOOKUP.WRITE", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "EventCode": "0xB4", + "EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "EventCode": "0xB4", + "EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "EventCode": "0xB4", + "EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "EventCode": "0xB4", + "EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .", + "EventCode": "0xB2", + "EventName": "UNC_H_TG_INGRESS_BYPASS.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .", + "EventCode": "0xB2", + "EventName": "UNC_H_TG_INGRESS_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .", + "EventCode": "0xB2", + "EventName": "UNC_H_TG_INGRESS_BYPASS.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .", + "EventCode": "0xB2", + "EventName": "UNC_H_TG_INGRESS_BYPASS.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .", + "EventCode": "0xB2", + "EventName": "UNC_H_TG_INGRESS_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .", + "EventCode": "0xB2", + "EventName": "UNC_H_TG_INGRESS_BYPASS.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "EventCode": "0xB3", + "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "EventCode": "0xB3", + "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "EventCode": "0xB3", + "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "EventCode": "0xB3", + "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "EventCode": "0xB3", + "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "EventCode": "0xB3", + "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.IFV", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "EventCode": "0xB3", + "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "EventCode": "0xB1", + "EventName": "UNC_H_TG_INGRESS_INSERTS.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "EventCode": "0xB1", + "EventName": "UNC_H_TG_INGRESS_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "EventCode": "0xB1", + "EventName": "UNC_H_TG_INGRESS_INSERTS.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "EventCode": "0xB1", + "EventName": "UNC_H_TG_INGRESS_INSERTS.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "EventCode": "0xB1", + "EventName": "UNC_H_TG_INGRESS_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "EventCode": "0xB1", + "EventName": "UNC_H_TG_INGRESS_INSERTS.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "EventCode": "0xB0", + "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "EventCode": "0xB0", + "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "EventCode": "0xB0", + "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "EventCode": "0xB0", + "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "EventCode": "0xB0", + "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "EventCode": "0xB0", + "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -SF/LLC Evictions", + "EventCode": "0x35", + "EventName": "UNC_H_TOR_INSERTS.EVICT", + "PerPkg": "1", + "UMask": "0x32", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -Hit (Not a Miss)", + "EventCode": "0x35", + "EventName": "UNC_H_TOR_INSERTS.HIT", + "PerPkg": "1", + "UMask": "0x1f", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ", + "EventCode": "0x35", + "EventName": "UNC_H_TOR_INSERTS.IPQ", + "PerPkg": "1", + "UMask": "0x38", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ", + "EventCode": "0x35", + "EventName": "UNC_H_TOR_INSERTS.IRQ", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -Miss", + "EventCode": "0x35", + "EventName": "UNC_H_TOR_INSERTS.MISS", + "PerPkg": "1", + "UMask": "0x2f", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -PRQ", + "EventCode": "0x35", + "EventName": "UNC_H_TOR_INSERTS.PRQ", + "PerPkg": "1", + "UMask": "0x34", + "Unit": "CHA" + }, + { + "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -SF/LLC Evictions", + "EventCode": "0x36", + "EventName": "UNC_H_TOR_OCCUPANCY.EVICT", + "PerPkg": "1", + "UMask": "0x32", + "Unit": "CHA" + }, + { + "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -Hit (Not a Miss)", + "EventCode": "0x36", + "EventName": "UNC_H_TOR_OCCUPANCY.HIT", + "PerPkg": "1", + "UMask": "0x1f", + "Unit": "CHA" + }, + { + "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IPQ", + "EventCode": "0x36", + "EventName": "UNC_H_TOR_OCCUPANCY.IPQ", + "PerPkg": "1", + "UMask": "0x38", + "Unit": "CHA" + }, + { + "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IPQ hit", + "EventCode": "0x36", + "EventName": "UNC_H_TOR_OCCUPANCY.IPQ_HIT", + "PerPkg": "1", + "UMask": "0x18", + "Unit": "CHA" + }, + { + "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IPQ miss", + "EventCode": "0x36", + "EventName": "UNC_H_TOR_OCCUPANCY.IPQ_MISS", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IRQ or PRQ", + "EventCode": "0x36", + "EventName": "UNC_H_TOR_OCCUPANCY.IRQ", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IRQ or PRQ hit", + "EventCode": "0x36", + "EventName": "UNC_H_TOR_OCCUPANCY.IRQ_HIT", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IRQ or PRQ miss", + "EventCode": "0x36", + "EventName": "UNC_H_TOR_OCCUPANCY.IRQ_MISS", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -Miss", + "EventCode": "0x36", + "EventName": "UNC_H_TOR_OCCUPANCY.MISS", + "PerPkg": "1", + "UMask": "0x2f", + "Unit": "CHA" + }, + { + "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -PRQ", + "EventCode": "0x36", + "EventName": "UNC_H_TOR_OCCUPANCY.PRQ", + "PerPkg": "1", + "UMask": "0x34", + "Unit": "CHA" + }, + { + "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -PRQ hit", + "EventCode": "0x36", + "EventName": "UNC_H_TOR_OCCUPANCY.PRQ_HIT", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "CHA" + }, + { + "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -PRQ miss", + "EventCode": "0x36", + "EventName": "UNC_H_TOR_OCCUPANCY.PRQ_MISS", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "Uncore Clocks", + "EventName": "UNC_H_U_CLOCKTICKS", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Down and Even", + "EventCode": "0xA6", + "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Down and Odd", + "EventCode": "0xA6", + "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Up and Even", + "EventCode": "0xA6", + "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Up and Odd", + "EventCode": "0xA6", + "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Down and Even", + "EventCode": "0xA8", + "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Down and Odd", + "EventCode": "0xA8", + "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Up and Even", + "EventCode": "0xA8", + "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Up and Odd", + "EventCode": "0xA8", + "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Down and Even", + "EventCode": "0xAA", + "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Down and Odd", + "EventCode": "0xAA", + "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Up and Even", + "EventCode": "0xAA", + "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Up and Odd", + "EventCode": "0xAA", + "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop - Down", + "EventCode": "0xAC", + "EventName": "UNC_H_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop - Up", + "EventCode": "0xAC", + "EventName": "UNC_H_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + } +] diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-io.json b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-io.json new file mode 100644 index 000000000000..898f7e425cd4 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-io.json @@ -0,0 +1,194 @@ +[ + { + "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AD_0", + "EventCode": "0x25", + "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AD_0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AD_1", + "EventCode": "0x25", + "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AD_1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AK_0", + "EventCode": "0x25", + "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AK_0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AK_1", + "EventCode": "0x25", + "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AK_1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. BL_0", + "EventCode": "0x25", + "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.BL_0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. BL_1", + "EventCode": "0x25", + "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.BL_1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AD_0", + "EventCode": "0x23", + "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AD_0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AD_1", + "EventCode": "0x23", + "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AD_1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AK_0", + "EventCode": "0x23", + "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AK_0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AK_1", + "EventCode": "0x23", + "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AK_1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. BL_0", + "EventCode": "0x23", + "EventName": "UNC_M2P_EGRESS_CYCLES_NE.BL_0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. BL_1", + "EventCode": "0x23", + "EventName": "UNC_M2P_EGRESS_CYCLES_NE.BL_1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AD_0", + "EventCode": "0x24", + "EventName": "UNC_M2P_EGRESS_INSERTS.AD_0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AD_1", + "EventCode": "0x24", + "EventName": "UNC_M2P_EGRESS_INSERTS.AD_1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_0", + "EventCode": "0x24", + "EventName": "UNC_M2P_EGRESS_INSERTS.AK_0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_1", + "EventCode": "0x24", + "EventName": "UNC_M2P_EGRESS_INSERTS.AK_1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_CRD_0", + "EventCode": "0x24", + "EventName": "UNC_M2P_EGRESS_INSERTS.AK_CRD_0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_CRD_1", + "EventCode": "0x24", + "EventName": "UNC_M2P_EGRESS_INSERTS.AK_CRD_1", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. BL_0", + "EventCode": "0x24", + "EventName": "UNC_M2P_EGRESS_INSERTS.BL_0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. BL_1", + "EventCode": "0x24", + "EventName": "UNC_M2P_EGRESS_INSERTS.BL_1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.ALL", + "EventCode": "0x10", + "EventName": "UNC_M2P_INGRESS_CYCLES_NE.ALL", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_IDI", + "EventCode": "0x10", + "EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_IDI", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_NCB", + "EventCode": "0x10", + "EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_NCB", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_NCS", + "EventCode": "0x10", + "EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_NCS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + } +] diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-memory.json b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-memory.json index 47da947b1a6e..fb752974179b 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-memory.json @@ -1,4 +1,72 @@ [ + { + "BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode.", + "EventCode": "0x02", + "EventName": "UNC_E_EDC_ACCESS.HIT_CLEAN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "EDC_UCLK" + }, + { + "BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode.", + "EventCode": "0x02", + "EventName": "UNC_E_EDC_ACCESS.HIT_DIRTY", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "EDC_UCLK" + }, + { + "BriefDescription": "Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode.", + "EventCode": "0x02", + "EventName": "UNC_E_EDC_ACCESS.MISS_CLEAN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "EDC_UCLK" + }, + { + "BriefDescription": "Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode.", + "EventCode": "0x02", + "EventName": "UNC_E_EDC_ACCESS.MISS_DIRTY", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "EDC_UCLK" + }, + { + "BriefDescription": "Number of EDC Hits or Misses. Miss I", + "EventCode": "0x02", + "EventName": "UNC_E_EDC_ACCESS.MISS_INVALID", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "EDC_UCLK" + }, + { + "BriefDescription": "ECLK count", + "EventName": "UNC_E_E_CLOCKTICKS", + "PerPkg": "1", + "Unit": "EDC_ECLK" + }, + { + "BriefDescription": "Counts the number of read requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all read requests as well as streaming stores that hit or miss in the MCDRAM cache.", + "EventCode": "0x01", + "EventName": "UNC_E_RPQ_INSERTS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "EDC_ECLK" + }, + { + "BriefDescription": "UCLK count", + "EventName": "UNC_E_U_CLOCKTICKS", + "PerPkg": "1", + "Unit": "EDC_UCLK" + }, + { + "BriefDescription": "Counts the number of write requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all streaming stores, writebacks and, read requests that miss in MCDRAM cache.", + "EventCode": "0x02", + "EventName": "UNC_E_WPQ_INSERTS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "EDC_ECLK" + }, { "BriefDescription": "CAS All", "EventCode": "0x03", diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json deleted file mode 100644 index fc85e0c95318..000000000000 --- a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-other.json +++ /dev/null @@ -1,3625 +0,0 @@ -[ - { - "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.IPQ_HIT", - "PerPkg": "1", - "UMask": "0x18", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.IPQ_MISS", - "PerPkg": "1", - "UMask": "0x28", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.IRQ_HIT", - "PerPkg": "1", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.IRQ_MISS", - "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ or PRQ", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.LOC_ALL", - "PerPkg": "1", - "UMask": "0x37", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -PRQ", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.PRQ_HIT", - "PerPkg": "1", - "UMask": "0x14", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -PRQ", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.PRQ_MISS", - "PerPkg": "1", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode.", - "EventCode": "0x02", - "EventName": "UNC_E_EDC_ACCESS.HIT_CLEAN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "EDC_UCLK" - }, - { - "BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode.", - "EventCode": "0x02", - "EventName": "UNC_E_EDC_ACCESS.HIT_DIRTY", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "EDC_UCLK" - }, - { - "BriefDescription": "Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode.", - "EventCode": "0x02", - "EventName": "UNC_E_EDC_ACCESS.MISS_CLEAN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "EDC_UCLK" - }, - { - "BriefDescription": "Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode.", - "EventCode": "0x02", - "EventName": "UNC_E_EDC_ACCESS.MISS_DIRTY", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "EDC_UCLK" - }, - { - "BriefDescription": "Number of EDC Hits or Misses. Miss I", - "EventCode": "0x02", - "EventName": "UNC_E_EDC_ACCESS.MISS_INVALID", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "EDC_UCLK" - }, - { - "BriefDescription": "ECLK count", - "EventName": "UNC_E_E_CLOCKTICKS", - "PerPkg": "1", - "Unit": "EDC_ECLK" - }, - { - "BriefDescription": "Counts the number of read requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all read requests as well as streaming stores that hit or miss in the MCDRAM cache.", - "EventCode": "0x01", - "EventName": "UNC_E_RPQ_INSERTS", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "EDC_ECLK" - }, - { - "BriefDescription": "UCLK count", - "EventName": "UNC_E_U_CLOCKTICKS", - "PerPkg": "1", - "Unit": "EDC_UCLK" - }, - { - "BriefDescription": "Counts the number of write requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all streaming stores, writebacks and, read requests that miss in MCDRAM cache.", - "EventCode": "0x02", - "EventName": "UNC_E_WPQ_INSERTS", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "EDC_ECLK" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 0", - "EventCode": "0x80", - "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 1", - "EventCode": "0x80", - "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 2", - "EventCode": "0x80", - "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 3", - "EventCode": "0x80", - "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 4", - "EventCode": "0x80", - "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 5", - "EventCode": "0x80", - "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 6", - "EventCode": "0x80", - "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR6", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 7", - "EventCode": "0x80", - "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR7", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 0-7", - "EventCode": "0x81", - "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress 8", - "EventCode": "0x81", - "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED_EXT.TGR8", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 0", - "EventCode": "0x82", - "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 1", - "EventCode": "0x82", - "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 2", - "EventCode": "0x82", - "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 3", - "EventCode": "0x82", - "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 4", - "EventCode": "0x82", - "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 5", - "EventCode": "0x82", - "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 6", - "EventCode": "0x82", - "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR6", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 7", - "EventCode": "0x82", - "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR7", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 0-7", - "EventCode": "0x83", - "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgress 8", - "EventCode": "0x83", - "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY_EXT.TGR8", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 0", - "EventCode": "0x88", - "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 1", - "EventCode": "0x88", - "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 2", - "EventCode": "0x88", - "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 3", - "EventCode": "0x88", - "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 4", - "EventCode": "0x88", - "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 5", - "EventCode": "0x88", - "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 6", - "EventCode": "0x88", - "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR6", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 7", - "EventCode": "0x88", - "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR7", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 0-7", - "EventCode": "0x89", - "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress 8", - "EventCode": "0x89", - "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED_EXT.TGR8", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 0", - "EventCode": "0x8A", - "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 1", - "EventCode": "0x8A", - "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 2", - "EventCode": "0x8A", - "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 3", - "EventCode": "0x8A", - "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 4", - "EventCode": "0x8A", - "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 5", - "EventCode": "0x8A", - "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 6", - "EventCode": "0x8A", - "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR6", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 7", - "EventCode": "0x8A", - "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR7", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 0-7", - "EventCode": "0x8B", - "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgress 8", - "EventCode": "0x8B", - "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY_EXT.TGR8", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 0", - "EventCode": "0xD0", - "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 1", - "EventCode": "0xD0", - "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 2", - "EventCode": "0xD0", - "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 3", - "EventCode": "0xD0", - "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 4", - "EventCode": "0xD0", - "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 5", - "EventCode": "0xD0", - "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 6", - "EventCode": "0xD0", - "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR6", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 7", - "EventCode": "0xD0", - "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR7", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 0-7", - "EventCode": "0xD1", - "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.ANY_OF_TGR0_THRU_TGR7", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 8", - "EventCode": "0xD1", - "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.TGR8", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 0", - "EventCode": "0xD4", - "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 1", - "EventCode": "0xD4", - "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 2", - "EventCode": "0xD4", - "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 3", - "EventCode": "0xD4", - "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 4", - "EventCode": "0xD4", - "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 5", - "EventCode": "0xD4", - "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 6", - "EventCode": "0xD4", - "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR6", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 7", - "EventCode": "0xD4", - "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR7", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 0-7", - "EventCode": "0xD5", - "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.ANY_OF_TGR0_THRU_TGR7", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 8", - "EventCode": "0xD5", - "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.TGR8", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 0", - "EventCode": "0x84", - "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 1", - "EventCode": "0x84", - "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 2", - "EventCode": "0x84", - "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 3", - "EventCode": "0x84", - "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 4", - "EventCode": "0x84", - "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 5", - "EventCode": "0x84", - "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 6", - "EventCode": "0x84", - "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR6", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 7", - "EventCode": "0x84", - "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR7", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 0-7", - "EventCode": "0x85", - "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress 8", - "EventCode": "0x85", - "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED_EXT.TGR8", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 0", - "EventCode": "0x86", - "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 1", - "EventCode": "0x86", - "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 2", - "EventCode": "0x86", - "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 3", - "EventCode": "0x86", - "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 4", - "EventCode": "0x86", - "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 5", - "EventCode": "0x86", - "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 6", - "EventCode": "0x86", - "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR6", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 7", - "EventCode": "0x86", - "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR7", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 0-7", - "EventCode": "0x87", - "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgress 8", - "EventCode": "0x87", - "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY_EXT.TGR8", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 0", - "EventCode": "0x8C", - "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 1", - "EventCode": "0x8C", - "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 2", - "EventCode": "0x8C", - "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 3", - "EventCode": "0x8C", - "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 4", - "EventCode": "0x8C", - "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 5", - "EventCode": "0x8C", - "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 6", - "EventCode": "0x8C", - "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR6", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 7", - "EventCode": "0x8C", - "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR7", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 0-7", - "EventCode": "0x8D", - "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress 8", - "EventCode": "0x8D", - "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED_EXT.TGR8", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 0", - "EventCode": "0x8E", - "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 1", - "EventCode": "0x8E", - "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 2", - "EventCode": "0x8E", - "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 3", - "EventCode": "0x8E", - "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 4", - "EventCode": "0x8E", - "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 5", - "EventCode": "0x8E", - "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 6", - "EventCode": "0x8E", - "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR6", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 7", - "EventCode": "0x8E", - "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR7", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 0-7", - "EventCode": "0x8F", - "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgress 8", - "EventCode": "0x8F", - "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY_EXT.TGR8", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 0", - "EventCode": "0xD2", - "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 1", - "EventCode": "0xD2", - "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 2", - "EventCode": "0xD2", - "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 3", - "EventCode": "0xD2", - "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 4", - "EventCode": "0xD2", - "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 5", - "EventCode": "0xD2", - "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 6", - "EventCode": "0xD2", - "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR6", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 7", - "EventCode": "0xD2", - "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR7", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 0-7", - "EventCode": "0xD3", - "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.ANY_OF_TGR0_THRU_TGR7", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 8", - "EventCode": "0xD3", - "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.TGR8", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 0", - "EventCode": "0xD6", - "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 1", - "EventCode": "0xD6", - "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 2", - "EventCode": "0xD6", - "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 3", - "EventCode": "0xD6", - "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 4", - "EventCode": "0xD6", - "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 5", - "EventCode": "0xD6", - "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 6", - "EventCode": "0xD6", - "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR6", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 7", - "EventCode": "0xD6", - "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR7", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 0-7", - "EventCode": "0xD7", - "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.ANY_OF_TGR0_THRU_TGR7", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Transgress Credits For Transgress 8", - "EventCode": "0xD7", - "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.TGR8", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.", - "EventCode": "0x37", - "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.E_STATE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.", - "EventCode": "0x37", - "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.F_STATE", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized that Match NID", - "EventCode": "0x37", - "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.LOCAL", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Read transactions", - "EventCode": "0x37", - "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.M_STATE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized that Does Not Match NID", - "EventCode": "0x37", - "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.REMOTE", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Filters for only snoop requests coming from the remote socket(s) through the IPQ.", - "EventCode": "0x37", - "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.S_STATE", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Uncore Clocks", - "EventCode": "0xC0", - "EventName": "UNC_H_CLOCK", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used", - "EventCode": "0x9D", - "EventName": "UNC_H_EGRESS_HORZ_ADS_USED.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used", - "EventCode": "0x9D", - "EventName": "UNC_H_EGRESS_HORZ_ADS_USED.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used", - "EventCode": "0x9D", - "EventName": "UNC_H_EGRESS_HORZ_ADS_USED.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Bypass. AD ring", - "EventCode": "0x9F", - "EventName": "UNC_H_EGRESS_HORZ_BYPASS.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Bypass. AK ring", - "EventCode": "0x9F", - "EventName": "UNC_H_EGRESS_HORZ_BYPASS.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Bypass. BL ring", - "EventCode": "0x9F", - "EventName": "UNC_H_EGRESS_HORZ_BYPASS.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Bypass. IV ring", - "EventCode": "0x9F", - "EventName": "UNC_H_EGRESS_HORZ_BYPASS.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full AD", - "EventCode": "0x96", - "EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full AK", - "EventCode": "0x96", - "EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full BL", - "EventCode": "0x96", - "EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full IV", - "EventCode": "0x96", - "EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty AD", - "EventCode": "0x97", - "EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty AK", - "EventCode": "0x97", - "EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty BL", - "EventCode": "0x97", - "EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty IV", - "EventCode": "0x97", - "EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts AD", - "EventCode": "0x95", - "EventName": "UNC_H_EGRESS_HORZ_INSERTS.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts AK", - "EventCode": "0x95", - "EventName": "UNC_H_EGRESS_HORZ_INSERTS.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts BL", - "EventCode": "0x95", - "EventName": "UNC_H_EGRESS_HORZ_INSERTS.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts IV", - "EventCode": "0x95", - "EventName": "UNC_H_EGRESS_HORZ_INSERTS.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs", - "EventCode": "0x99", - "EventName": "UNC_H_EGRESS_HORZ_NACK.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs", - "EventCode": "0x99", - "EventName": "UNC_H_EGRESS_HORZ_NACK.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs", - "EventCode": "0x99", - "EventName": "UNC_H_EGRESS_HORZ_NACK.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs", - "EventCode": "0x99", - "EventName": "UNC_H_EGRESS_HORZ_NACK.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy AD", - "EventCode": "0x94", - "EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy AK", - "EventCode": "0x94", - "EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy BL", - "EventCode": "0x94", - "EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy IV", - "EventCode": "0x94", - "EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation", - "EventCode": "0x9B", - "EventName": "UNC_H_EGRESS_HORZ_STARVED.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation", - "EventCode": "0x9B", - "EventName": "UNC_H_EGRESS_HORZ_STARVED.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation", - "EventCode": "0x9B", - "EventName": "UNC_H_EGRESS_HORZ_STARVED.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation", - "EventCode": "0x9B", - "EventName": "UNC_H_EGRESS_HORZ_STARVED.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "EventCode": "0xAE", - "EventName": "UNC_H_EGRESS_ORDERING.IV_SNP_GO_DN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "EventCode": "0xAE", - "EventName": "UNC_H_EGRESS_ORDERING.IV_SNP_GO_UP", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used", - "EventCode": "0x9C", - "EventName": "UNC_H_EGRESS_VERT_ADS_USED.AD_AG0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used", - "EventCode": "0x9C", - "EventName": "UNC_H_EGRESS_VERT_ADS_USED.AD_AG1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used", - "EventCode": "0x9C", - "EventName": "UNC_H_EGRESS_VERT_ADS_USED.AK_AG0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used", - "EventCode": "0x9C", - "EventName": "UNC_H_EGRESS_VERT_ADS_USED.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used", - "EventCode": "0x9C", - "EventName": "UNC_H_EGRESS_VERT_ADS_USED.BL_AG0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used", - "EventCode": "0x9C", - "EventName": "UNC_H_EGRESS_VERT_ADS_USED.BL_AG1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Bypass. AD ring agent 0", - "EventCode": "0x9E", - "EventName": "UNC_H_EGRESS_VERT_BYPASS.AD_AG0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Bypass. AD ring agent 1", - "EventCode": "0x9E", - "EventName": "UNC_H_EGRESS_VERT_BYPASS.AD_AG1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Bypass. AK ring agent 0", - "EventCode": "0x9E", - "EventName": "UNC_H_EGRESS_VERT_BYPASS.AK_AG0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Bypass. AK ring agent 1", - "EventCode": "0x9E", - "EventName": "UNC_H_EGRESS_VERT_BYPASS.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Bypass. BL ring agent 0", - "EventCode": "0x9E", - "EventName": "UNC_H_EGRESS_VERT_BYPASS.BL_AG0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Bypass. BL ring agent 1", - "EventCode": "0x9E", - "EventName": "UNC_H_EGRESS_VERT_BYPASS.BL_AG1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Bypass. IV ring agent 0", - "EventCode": "0x9E", - "EventName": "UNC_H_EGRESS_VERT_BYPASS.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AD - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AD_AG0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AD - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AD_AG1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AK - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AK_AG0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AK - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full BL - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.BL_AG0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full BL - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.BL_AG1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full IV - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.IV_AG0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty AD - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AD_AG0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty AD - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AD_AG1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty AK - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AK_AG0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty AK - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty BL - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.BL_AG0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty BL - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.BL_AG1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty IV - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.IV_AG0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations AD - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_H_EGRESS_VERT_INSERTS.AD_AG0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations AD - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_H_EGRESS_VERT_INSERTS.AD_AG1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations AK - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_H_EGRESS_VERT_INSERTS.AK_AG0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations AK - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_H_EGRESS_VERT_INSERTS.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations BL - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_H_EGRESS_VERT_INSERTS.BL_AG0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations BL - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_H_EGRESS_VERT_INSERTS.BL_AG1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations IV - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_H_EGRESS_VERT_INSERTS.IV_AG0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs", - "EventCode": "0x98", - "EventName": "UNC_H_EGRESS_VERT_NACK.AD_AG0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs", - "EventCode": "0x98", - "EventName": "UNC_H_EGRESS_VERT_NACK.AD_AG1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs Onto AK Ring", - "EventCode": "0x98", - "EventName": "UNC_H_EGRESS_VERT_NACK.AK_AG0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs", - "EventCode": "0x98", - "EventName": "UNC_H_EGRESS_VERT_NACK.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs Onto BL Ring", - "EventCode": "0x98", - "EventName": "UNC_H_EGRESS_VERT_NACK.BL_AG0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs", - "EventCode": "0x98", - "EventName": "UNC_H_EGRESS_VERT_NACK.BL_AG1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs", - "EventCode": "0x98", - "EventName": "UNC_H_EGRESS_VERT_NACK.IV_AG0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy AD - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AD_AG0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy AD - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AD_AG1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy AK - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AK_AG0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy AK - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy BL - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.BL_AG0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy BL - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.BL_AG1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy IV - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.IV_AG0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation", - "EventCode": "0x9A", - "EventName": "UNC_H_EGRESS_VERT_STARVED.AD_AG0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation", - "EventCode": "0x9A", - "EventName": "UNC_H_EGRESS_VERT_STARVED.AD_AG1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation Onto AK Ring", - "EventCode": "0x9A", - "EventName": "UNC_H_EGRESS_VERT_STARVED.AK_AG0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation", - "EventCode": "0x9A", - "EventName": "UNC_H_EGRESS_VERT_STARVED.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation Onto BL Ring", - "EventCode": "0x9A", - "EventName": "UNC_H_EGRESS_VERT_STARVED.BL_AG0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation", - "EventCode": "0x9A", - "EventName": "UNC_H_EGRESS_VERT_STARVED.BL_AG1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation", - "EventCode": "0x9A", - "EventName": "UNC_H_EGRESS_VERT_STARVED.IV_AG0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts cycles source throttling is asserted - horizontal", - "EventCode": "0xA5", - "EventName": "UNC_H_FAST_ASSERTED.HORZ", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts cycles source throttling is asserted - vertical", - "EventCode": "0xA5", - "EventName": "UNC_H_FAST_ASSERTED.VERT", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Left and Even", - "EventCode": "0xA7", - "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Left and Odd", - "EventCode": "0xA7", - "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_ODD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Right and Even", - "EventCode": "0xA7", - "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Right and Odd", - "EventCode": "0xA7", - "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Left and Even", - "EventCode": "0xA9", - "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Left and Odd", - "EventCode": "0xA9", - "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_ODD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Right and Even", - "EventCode": "0xA9", - "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Right and Odd", - "EventCode": "0xA9", - "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Left and Even", - "EventCode": "0xAB", - "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Left and Odd", - "EventCode": "0xAB", - "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_ODD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Right and Even", - "EventCode": "0xAB", - "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Right and Odd", - "EventCode": "0xAB", - "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop - Left", - "EventCode": "0xAD", - "EventName": "UNC_H_HORZ_RING_IV_IN_USE.LEFT", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop - Right", - "EventCode": "0xAD", - "EventName": "UNC_H_HORZ_RING_IV_IN_USE.RIGHT", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IPQ", - "EventCode": "0x13", - "EventName": "UNC_H_INGRESS_INSERTS.IPQ", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IRQ", - "EventCode": "0x13", - "EventName": "UNC_H_INGRESS_INSERTS.IRQ", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IRQ Rejected", - "EventCode": "0x13", - "EventName": "UNC_H_INGRESS_INSERTS.IRQ_REJ", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - PRQ", - "EventCode": "0x13", - "EventName": "UNC_H_INGRESS_INSERTS.PRQ", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - PRQ Rejected", - "EventCode": "0x13", - "EventName": "UNC_H_INGRESS_INSERTS.PRQ_REJ", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles with the IPQ in Internal Starvation.", - "EventCode": "0x14", - "EventName": "UNC_H_INGRESS_INT_STARVED.IPQ", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles with the IRQ in Internal Starvation.", - "EventCode": "0x14", - "EventName": "UNC_H_INGRESS_INT_STARVED.IRQ", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles with the ISMQ in Internal Starvation.", - "EventCode": "0x14", - "EventName": "UNC_H_INGRESS_INT_STARVED.ISMQ", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress internal starvation cycles. Counts cycles in internal starvation. This occurs when one or more of the entries in the ingress queue are being starved out by other entries in the queue.", - "EventCode": "0x14", - "EventName": "UNC_H_INGRESS_INT_STARVED.PRQ", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - IPQ", - "EventCode": "0x11", - "EventName": "UNC_H_INGRESS_OCCUPANCY.IPQ", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - IRQ", - "EventCode": "0x11", - "EventName": "UNC_H_INGRESS_OCCUPANCY.IRQ", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - IRQ Rejected", - "EventCode": "0x11", - "EventName": "UNC_H_INGRESS_OCCUPANCY.IRQ_REJ", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - PRQ", - "EventCode": "0x11", - "EventName": "UNC_H_INGRESS_OCCUPANCY.PRQ", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - PRQ Rejected", - "EventCode": "0x11", - "EventName": "UNC_H_INGRESS_OCCUPANCY.PRQ_REJ", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects", - "EventCode": "0x22", - "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects", - "EventCode": "0x22", - "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects", - "EventCode": "0x22", - "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects", - "EventCode": "0x22", - "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects", - "EventCode": "0x22", - "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects", - "EventCode": "0x22", - "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects", - "EventCode": "0x22", - "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects", - "EventCode": "0x22", - "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects", - "EventCode": "0x23", - "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects", - "EventCode": "0x23", - "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.ANY_REJECT_IPQ0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects", - "EventCode": "0x23", - "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects", - "EventCode": "0x23", - "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects", - "EventCode": "0x23", - "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x18", - "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x18", - "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x18", - "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x18", - "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x18", - "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x18", - "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x18", - "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x18", - "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x19", - "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x19", - "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.ANY_REJECT_IRQ0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x19", - "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x19", - "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x19", - "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects", - "EventCode": "0x24", - "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects", - "EventCode": "0x24", - "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects", - "EventCode": "0x24", - "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects", - "EventCode": "0x24", - "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects", - "EventCode": "0x24", - "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects", - "EventCode": "0x24", - "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects", - "EventCode": "0x24", - "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects", - "EventCode": "0x24", - "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries", - "EventCode": "0x2C", - "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries", - "EventCode": "0x2C", - "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries", - "EventCode": "0x2C", - "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.AK_NON_UPI", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries", - "EventCode": "0x2C", - "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries", - "EventCode": "0x2C", - "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries", - "EventCode": "0x2C", - "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries", - "EventCode": "0x2C", - "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries", - "EventCode": "0x2C", - "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.IV_NON_UPI", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Queue Retries", - "EventCode": "0x2E", - "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Queue Retries", - "EventCode": "0x2E", - "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Queue Retries", - "EventCode": "0x2E", - "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.AK_NON_UPI", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Queue Retries", - "EventCode": "0x2E", - "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Queue Retries", - "EventCode": "0x2E", - "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Queue Retries", - "EventCode": "0x2E", - "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Queue Retries", - "EventCode": "0x2E", - "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Queue Retries", - "EventCode": "0x2E", - "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.IV_NON_UPI", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Queue Retries", - "EventCode": "0x2F", - "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Queue Retries", - "EventCode": "0x2F", - "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.ANY_REJECT_IRQ0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Queue Retries", - "EventCode": "0x2F", - "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Queue Retries", - "EventCode": "0x2F", - "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Queue Retries", - "EventCode": "0x2F", - "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x20", - "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x20", - "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x20", - "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x20", - "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x20", - "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x20", - "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x20", - "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x20", - "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x21", - "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x21", - "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.ANY_REJECT_IRQ0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x21", - "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x21", - "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Request Queue Rejects", - "EventCode": "0x21", - "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "EventCode": "0x2A", - "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "EventCode": "0x2A", - "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "EventCode": "0x2A", - "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AK_NON_UPI", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "EventCode": "0x2A", - "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "EventCode": "0x2A", - "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "EventCode": "0x2A", - "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "EventCode": "0x2A", - "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "EventCode": "0x2A", - "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.IV_NON_UPI", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "EventCode": "0x2B", - "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "EventCode": "0x2B", - "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.ANY_REJECT_IRQ0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "EventCode": "0x2B", - "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "EventCode": "0x2B", - "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "EventCode": "0x2B", - "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Miscellaneous events in the Cbo. CV0 Prefetch Miss", - "EventCode": "0x39", - "EventName": "UNC_H_MISC.CV0_PREF_MISS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Miscellaneous events in the Cbo. CV0 Prefetch Victim", - "EventCode": "0x39", - "EventName": "UNC_H_MISC.CV0_PREF_VIC", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Miscellaneous events in the Cbo. RFO HitS", - "EventCode": "0x39", - "EventName": "UNC_H_MISC.RFO_HIT_S", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Miscellaneous events in the Cbo. Silent Snoop Eviction", - "EventCode": "0x39", - "EventName": "UNC_H_MISC.RSPI_WAS_FSE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Miscellaneous events in the Cbo. Write Combining Aliasing", - "EventCode": "0x39", - "EventName": "UNC_H_MISC.WC_ALIASING", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Number of incoming messages from the Horizontal ring that were bounced, by ring type.", - "EventCode": "0xA1", - "EventName": "UNC_H_RING_BOUNCES_HORZ.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Number of incoming messages from the Horizontal ring that were bounced, by ring type - Acknowledgements to core", - "EventCode": "0xA1", - "EventName": "UNC_H_RING_BOUNCES_HORZ.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Number of incoming messages from the Horizontal ring that were bounced, by ring type - Data Responses to core.", - "EventCode": "0xA1", - "EventName": "UNC_H_RING_BOUNCES_HORZ.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Number of incoming messages from the Horizontal ring that were bounced, by ring type - Snoops of processor's cache.", - "EventCode": "0xA1", - "EventName": "UNC_H_RING_BOUNCES_HORZ.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Number of incoming messages from the Vertical ring that were bounced, by ring type.", - "EventCode": "0xA0", - "EventName": "UNC_H_RING_BOUNCES_VERT.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Number of incoming messages from the Vertical ring that were bounced, by ring type - Acknowledgements to core", - "EventCode": "0xA0", - "EventName": "UNC_H_RING_BOUNCES_VERT.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Number of incoming messages from the Vertical ring that were bounced, by ring type - Data Responses to core.", - "EventCode": "0xA0", - "EventName": "UNC_H_RING_BOUNCES_VERT.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Number of incoming messages from the Vertical ring that were bounced, by ring type - Snoops of processor's cache.", - "EventCode": "0xA0", - "EventName": "UNC_H_RING_BOUNCES_VERT.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal ring sink starvation count - AD ring", - "EventCode": "0xA3", - "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal ring sink starvation count - AK ring", - "EventCode": "0xA3", - "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal ring sink starvation count - BL ring", - "EventCode": "0xA3", - "EventName": "UNC_H_RING_SINK_STARVED_HORZ.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal ring sink starvation count - IV ring", - "EventCode": "0xA3", - "EventName": "UNC_H_RING_SINK_STARVED_HORZ.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical ring sink starvation count - AD ring", - "EventCode": "0xA2", - "EventName": "UNC_H_RING_SINK_STARVED_VERT.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical ring sink starvation count - AK ring", - "EventCode": "0xA2", - "EventName": "UNC_H_RING_SINK_STARVED_VERT.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical ring sink starvation count - BL ring", - "EventCode": "0xA2", - "EventName": "UNC_H_RING_SINK_STARVED_VERT.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical ring sink starvation count - IV ring", - "EventCode": "0xA2", - "EventName": "UNC_H_RING_SINK_STARVED_VERT.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts cycles in throttle mode.", - "EventCode": "0xA4", - "EventName": "UNC_H_RING_SRC_THRTL", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.", - "EventCode": "0x34", - "EventName": "UNC_H_SF_LOOKUP.ANY", - "PerPkg": "1", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Read transactions", - "EventCode": "0x34", - "EventName": "UNC_H_SF_LOOKUP.DATA_READ", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Filters for only snoop requests coming from the remote socket(s) through the IPQ.", - "EventCode": "0x34", - "EventName": "UNC_H_SF_LOOKUP.REMOTE_SNOOP", - "PerPkg": "1", - "UMask": "0x9", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups. Counts the number of times the LLC was accessed. Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.", - "EventCode": "0x34", - "EventName": "UNC_H_SF_LOOKUP.WRITE", - "PerPkg": "1", - "UMask": "0x5", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "EventCode": "0xB4", - "EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "EventCode": "0xB4", - "EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "EventCode": "0xB4", - "EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "EventCode": "0xB4", - "EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .", - "EventCode": "0xB2", - "EventName": "UNC_H_TG_INGRESS_BYPASS.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .", - "EventCode": "0xB2", - "EventName": "UNC_H_TG_INGRESS_BYPASS.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .", - "EventCode": "0xB2", - "EventName": "UNC_H_TG_INGRESS_BYPASS.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .", - "EventCode": "0xB2", - "EventName": "UNC_H_TG_INGRESS_BYPASS.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .", - "EventCode": "0xB2", - "EventName": "UNC_H_TG_INGRESS_BYPASS.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress .", - "EventCode": "0xB2", - "EventName": "UNC_H_TG_INGRESS_BYPASS.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "EventCode": "0xB3", - "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "EventCode": "0xB3", - "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "EventCode": "0xB3", - "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "EventCode": "0xB3", - "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "EventCode": "0xB3", - "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "EventCode": "0xB3", - "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.IFV", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "EventCode": "0xB3", - "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "EventCode": "0xB1", - "EventName": "UNC_H_TG_INGRESS_INSERTS.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "EventCode": "0xB1", - "EventName": "UNC_H_TG_INGRESS_INSERTS.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "EventCode": "0xB1", - "EventName": "UNC_H_TG_INGRESS_INSERTS.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "EventCode": "0xB1", - "EventName": "UNC_H_TG_INGRESS_INSERTS.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "EventCode": "0xB1", - "EventName": "UNC_H_TG_INGRESS_INSERTS.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "EventCode": "0xB1", - "EventName": "UNC_H_TG_INGRESS_INSERTS.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "EventCode": "0xB0", - "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "EventCode": "0xB0", - "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "EventCode": "0xB0", - "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "EventCode": "0xB0", - "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "EventCode": "0xB0", - "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "EventCode": "0xB0", - "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -SF/LLC Evictions", - "EventCode": "0x35", - "EventName": "UNC_H_TOR_INSERTS.EVICT", - "PerPkg": "1", - "UMask": "0x32", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -Hit (Not a Miss)", - "EventCode": "0x35", - "EventName": "UNC_H_TOR_INSERTS.HIT", - "PerPkg": "1", - "UMask": "0x1f", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IPQ", - "EventCode": "0x35", - "EventName": "UNC_H_TOR_INSERTS.IPQ", - "PerPkg": "1", - "UMask": "0x38", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -IRQ", - "EventCode": "0x35", - "EventName": "UNC_H_TOR_INSERTS.IRQ", - "PerPkg": "1", - "UMask": "0x31", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -Miss", - "EventCode": "0x35", - "EventName": "UNC_H_TOR_INSERTS.MISS", - "PerPkg": "1", - "UMask": "0x2f", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent -PRQ", - "EventCode": "0x35", - "EventName": "UNC_H_TOR_INSERTS.PRQ", - "PerPkg": "1", - "UMask": "0x34", - "Unit": "CHA" - }, - { - "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -SF/LLC Evictions", - "EventCode": "0x36", - "EventName": "UNC_H_TOR_OCCUPANCY.EVICT", - "PerPkg": "1", - "UMask": "0x32", - "Unit": "CHA" - }, - { - "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -Hit (Not a Miss)", - "EventCode": "0x36", - "EventName": "UNC_H_TOR_OCCUPANCY.HIT", - "PerPkg": "1", - "UMask": "0x1f", - "Unit": "CHA" - }, - { - "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IPQ", - "EventCode": "0x36", - "EventName": "UNC_H_TOR_OCCUPANCY.IPQ", - "PerPkg": "1", - "UMask": "0x38", - "Unit": "CHA" - }, - { - "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IPQ hit", - "EventCode": "0x36", - "EventName": "UNC_H_TOR_OCCUPANCY.IPQ_HIT", - "PerPkg": "1", - "UMask": "0x18", - "Unit": "CHA" - }, - { - "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IPQ miss", - "EventCode": "0x36", - "EventName": "UNC_H_TOR_OCCUPANCY.IPQ_MISS", - "PerPkg": "1", - "UMask": "0x28", - "Unit": "CHA" - }, - { - "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IRQ or PRQ", - "EventCode": "0x36", - "EventName": "UNC_H_TOR_OCCUPANCY.IRQ", - "PerPkg": "1", - "UMask": "0x31", - "Unit": "CHA" - }, - { - "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IRQ or PRQ hit", - "EventCode": "0x36", - "EventName": "UNC_H_TOR_OCCUPANCY.IRQ_HIT", - "PerPkg": "1", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IRQ or PRQ miss", - "EventCode": "0x36", - "EventName": "UNC_H_TOR_OCCUPANCY.IRQ_MISS", - "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -Miss", - "EventCode": "0x36", - "EventName": "UNC_H_TOR_OCCUPANCY.MISS", - "PerPkg": "1", - "UMask": "0x2f", - "Unit": "CHA" - }, - { - "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -PRQ", - "EventCode": "0x36", - "EventName": "UNC_H_TOR_OCCUPANCY.PRQ", - "PerPkg": "1", - "UMask": "0x34", - "Unit": "CHA" - }, - { - "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -PRQ hit", - "EventCode": "0x36", - "EventName": "UNC_H_TOR_OCCUPANCY.PRQ_HIT", - "PerPkg": "1", - "UMask": "0x14", - "Unit": "CHA" - }, - { - "BriefDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -PRQ miss", - "EventCode": "0x36", - "EventName": "UNC_H_TOR_OCCUPANCY.PRQ_MISS", - "PerPkg": "1", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "Uncore Clocks", - "EventName": "UNC_H_U_CLOCKTICKS", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Down and Even", - "EventCode": "0xA6", - "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_EVEN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Down and Odd", - "EventCode": "0xA6", - "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_ODD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Up and Even", - "EventCode": "0xA6", - "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_EVEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Up and Odd", - "EventCode": "0xA6", - "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_ODD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Down and Even", - "EventCode": "0xA8", - "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_EVEN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Down and Odd", - "EventCode": "0xA8", - "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_ODD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Up and Even", - "EventCode": "0xA8", - "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_EVEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Up and Odd", - "EventCode": "0xA8", - "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_ODD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Down and Even", - "EventCode": "0xAA", - "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_EVEN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Down and Odd", - "EventCode": "0xAA", - "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_ODD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Up and Even", - "EventCode": "0xAA", - "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_EVEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Up and Odd", - "EventCode": "0xAA", - "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_ODD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop - Down", - "EventCode": "0xAC", - "EventName": "UNC_H_VERT_RING_IV_IN_USE.DN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop - Up", - "EventCode": "0xAC", - "EventName": "UNC_H_VERT_RING_IV_IN_USE.UP", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AD_0", - "EventCode": "0x25", - "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AD_0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AD_1", - "EventCode": "0x25", - "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AD_1", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AK_0", - "EventCode": "0x25", - "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AK_0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AK_1", - "EventCode": "0x25", - "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AK_1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. BL_0", - "EventCode": "0x25", - "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.BL_0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. BL_1", - "EventCode": "0x25", - "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.BL_1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AD_0", - "EventCode": "0x23", - "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AD_0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AD_1", - "EventCode": "0x23", - "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AD_1", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AK_0", - "EventCode": "0x23", - "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AK_0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AK_1", - "EventCode": "0x23", - "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AK_1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. BL_0", - "EventCode": "0x23", - "EventName": "UNC_M2P_EGRESS_CYCLES_NE.BL_0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. BL_1", - "EventCode": "0x23", - "EventName": "UNC_M2P_EGRESS_CYCLES_NE.BL_1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AD_0", - "EventCode": "0x24", - "EventName": "UNC_M2P_EGRESS_INSERTS.AD_0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AD_1", - "EventCode": "0x24", - "EventName": "UNC_M2P_EGRESS_INSERTS.AD_1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_0", - "EventCode": "0x24", - "EventName": "UNC_M2P_EGRESS_INSERTS.AK_0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_1", - "EventCode": "0x24", - "EventName": "UNC_M2P_EGRESS_INSERTS.AK_1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_CRD_0", - "EventCode": "0x24", - "EventName": "UNC_M2P_EGRESS_INSERTS.AK_CRD_0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_CRD_1", - "EventCode": "0x24", - "EventName": "UNC_M2P_EGRESS_INSERTS.AK_CRD_1", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. BL_0", - "EventCode": "0x24", - "EventName": "UNC_M2P_EGRESS_INSERTS.BL_0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. BL_1", - "EventCode": "0x24", - "EventName": "UNC_M2P_EGRESS_INSERTS.BL_1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.ALL", - "EventCode": "0x10", - "EventName": "UNC_M2P_INGRESS_CYCLES_NE.ALL", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_IDI", - "EventCode": "0x10", - "EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_IDI", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_NCB", - "EventCode": "0x10", - "EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_NCB", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_NCS", - "EventCode": "0x10", - "EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_NCS", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - } -] -- cgit v1.2.3-58-ga151 From f58468a815a3933710e871812ffe23b15421edc4 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 13 Apr 2023 06:29:45 -0700 Subject: perf vendor events intel: Fix uncore topics for sandybridge Remove 'uncore-other' topic classification, move to cache and interconnect. Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230413132949.3487664-18-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/x86/sandybridge/uncore-cache.json | 50 +++++++-------- .../arch/x86/sandybridge/uncore-interconnect.json | 75 ++++++++++++++++++++++ .../arch/x86/sandybridge/uncore-other.json | 75 ---------------------- 3 files changed, 100 insertions(+), 100 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/sandybridge/uncore-interconnect.json delete mode 100644 tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json index c538557ba4c0..be9a3ed1a940 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json @@ -5,7 +5,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES", "PerPkg": "1", "UMask": "0x86", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.", @@ -13,7 +13,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I", "PerPkg": "1", "UMask": "0x88", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.", @@ -21,7 +21,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M", "PerPkg": "1", "UMask": "0x81", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.", @@ -29,7 +29,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI", "PerPkg": "1", "UMask": "0x8f", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.", @@ -37,7 +37,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES", "PerPkg": "1", "UMask": "0x46", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.", @@ -45,7 +45,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I", "PerPkg": "1", "UMask": "0x48", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.", @@ -53,7 +53,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M", "PerPkg": "1", "UMask": "0x41", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.", @@ -61,7 +61,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI", "PerPkg": "1", "UMask": "0x4f", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.", @@ -69,7 +69,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES", "PerPkg": "1", "UMask": "0x16", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup read request that access cache and found line in I-state.", @@ -77,7 +77,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I", "PerPkg": "1", "UMask": "0x18", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup read request that access cache and found line in M-state.", @@ -85,7 +85,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M", "PerPkg": "1", "UMask": "0x11", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state.", @@ -93,7 +93,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI", "PerPkg": "1", "UMask": "0x1f", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state.", @@ -101,7 +101,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES", "PerPkg": "1", "UMask": "0x26", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup write request that access cache and found line in I-state.", @@ -109,7 +109,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I", "PerPkg": "1", "UMask": "0x28", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup write request that access cache and found line in M-state.", @@ -117,7 +117,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M", "PerPkg": "1", "UMask": "0x21", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state.", @@ -125,7 +125,7 @@ "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI", "PerPkg": "1", "UMask": "0x2f", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.", @@ -133,7 +133,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION", "PerPkg": "1", "UMask": "0x88", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "An external snoop hits a modified line in some processor core.", @@ -141,7 +141,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL", "PerPkg": "1", "UMask": "0x28", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.", @@ -149,7 +149,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", "PerPkg": "1", "UMask": "0x48", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.", @@ -157,7 +157,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION", "PerPkg": "1", "UMask": "0x84", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "An external snoop hits a non-modified line in some processor core.", @@ -165,7 +165,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL", "PerPkg": "1", "UMask": "0x24", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.", @@ -173,7 +173,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", "PerPkg": "1", "UMask": "0x44", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.", @@ -181,7 +181,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", "PerPkg": "1", "UMask": "0x81", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "An external snoop misses in some processor core.", @@ -189,7 +189,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL", "PerPkg": "1", "UMask": "0x21", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.", @@ -197,6 +197,6 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", "PerPkg": "1", "UMask": "0x41", - "Unit": "CBO" + "Unit": "CBOX" } ] diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-interconnect.json new file mode 100644 index 000000000000..c3252c094a9c --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-interconnect.json @@ -0,0 +1,75 @@ +[ + { + "BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.", + "EventCode": "0x83", + "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of requests allocated in Coherency Tracker.", + "EventCode": "0x84", + "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", + "CounterMask": "10", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", + "CounterMask": "1", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts the number of LLC evictions allocated.", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "ARB" + }, + { + "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.", + "EventCode": "0xff", + "EventName": "UNC_CLOCK.SOCKET", + "PerPkg": "1", + "Unit": "ARB" + } +] diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json deleted file mode 100644 index c3252c094a9c..000000000000 --- a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json +++ /dev/null @@ -1,75 +0,0 @@ -[ - { - "BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.", - "EventCode": "0x83", - "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Number of requests allocated in Coherency Tracker.", - "EventCode": "0x84", - "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.", - "EventCode": "0x80", - "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", - "CounterMask": "10", - "EventCode": "0x80", - "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", - "CounterMask": "1", - "EventCode": "0x80", - "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Counts the number of LLC evictions allocated.", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "ARB" - }, - { - "BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "ARB" - }, - { - "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.", - "EventCode": "0xff", - "EventName": "UNC_CLOCK.SOCKET", - "PerPkg": "1", - "Unit": "ARB" - } -] -- cgit v1.2.3-58-ga151 From 9a8b303688f80aa9480d6a196817c90b6a592356 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 13 Apr 2023 06:29:46 -0700 Subject: perf vendor events intel: Fix uncore topics for skylake Move events from 'uncore-other' topic classification to cache and interconnect. Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230413132949.3487664-19-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/skylake/uncore-cache.json | 28 ++++----- .../arch/x86/skylake/uncore-interconnect.json | 67 ++++++++++++++++++++++ .../pmu-events/arch/x86/skylake/uncore-other.json | 65 --------------------- 3 files changed, 81 insertions(+), 79 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/skylake/uncore-interconnect.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json b/tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json index ec9463c94ffe..b4e061477c1a 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json @@ -6,7 +6,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.", "UMask": "0x86", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup any request that access cache and found line in I-state", @@ -15,7 +15,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.", "UMask": "0x88", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup any request that access cache and found line in M-state", @@ -24,7 +24,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.", "UMask": "0x81", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state", @@ -33,7 +33,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.", "UMask": "0x8f", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state", @@ -42,7 +42,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.", "UMask": "0x16", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup read request that access cache and found line in I-state", @@ -51,7 +51,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup read request that access cache and found line in I-state.", "UMask": "0x18", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state", @@ -60,7 +60,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.", "UMask": "0x1f", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state", @@ -69,7 +69,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.", "UMask": "0x26", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup write request that access cache and found line in M-state", @@ -78,7 +78,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.", "UMask": "0x21", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state", @@ -87,7 +87,7 @@ "PerPkg": "1", "PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.", "UMask": "0x2f", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.", @@ -95,7 +95,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", "PerPkg": "1", "UMask": "0x48", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.", @@ -103,7 +103,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", "PerPkg": "1", "UMask": "0x44", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.", @@ -111,7 +111,7 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", "PerPkg": "1", "UMask": "0x81", - "Unit": "CBO" + "Unit": "CBOX" }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.", @@ -119,6 +119,6 @@ "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", "PerPkg": "1", "UMask": "0x41", - "Unit": "CBO" + "Unit": "CBOX" } ] diff --git a/tools/perf/pmu-events/arch/x86/skylake/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/skylake/uncore-interconnect.json new file mode 100644 index 000000000000..fe7e19717371 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/skylake/uncore-interconnect.json @@ -0,0 +1,67 @@ +[ + { + "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.", + "EventCode": "0x84", + "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", + "CounterMask": "1", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk.", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.DATA_READ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.DATA_READ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "ARB" + } +] diff --git a/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json b/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json index ef804df3f41e..58be90d7cc93 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json @@ -1,69 +1,4 @@ [ - { - "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.", - "EventCode": "0x84", - "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Number of all Core entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk. Accounts for Coherent and non-coherent traffic.", - "EventCode": "0x80", - "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", - "CounterMask": "1", - "EventCode": "0x80", - "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Number of Core Data Read entries outstanding for the memory controller. The outstanding interval starts after LLC miss till return of first data chunk.", - "EventCode": "0x80", - "EventName": "UNC_ARB_TRK_OCCUPANCY.DATA_READ", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "ARB" - }, - { - "BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.DATA_READ", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "ARB" - }, - { - "BriefDescription": "Number of Core coherent Data Read requests sent to memory controller whose data is returned directly to requesting agent.", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "ARB" - }, - { - "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "ARB" - }, { "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles", "EventCode": "0xff", -- cgit v1.2.3-58-ga151 From 748d5cf71948d5ad2cac896777dd5ccc6ea494e9 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 13 Apr 2023 06:29:47 -0700 Subject: perf vendor events intel: Fix uncore topics for skylakex Remove 'uncore-other' topic classification, move to cache, interconnect, io and memory. Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Edward Baker Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: http://lore.kernel.org/lkml/20230413132949.3487664-20-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../pmu-events/arch/x86/skylakex/uncore-cache.json | 10649 ++++++++ .../arch/x86/skylakex/uncore-interconnect.json | 11248 ++++++++ .../pmu-events/arch/x86/skylakex/uncore-io.json | 4250 +++ .../arch/x86/skylakex/uncore-memory.json | 2 +- .../pmu-events/arch/x86/skylakex/uncore-other.json | 26143 ------------------- 5 files changed, 26148 insertions(+), 26144 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/skylakex/uncore-cache.json create mode 100644 tools/perf/pmu-events/arch/x86/skylakex/uncore-interconnect.json create mode 100644 tools/perf/pmu-events/arch/x86/skylakex/uncore-io.json delete mode 100644 tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-cache.json b/tools/perf/pmu-events/arch/x86/skylakex/uncore-cache.json new file mode 100644 index 000000000000..543dfc1e5ad7 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-cache.json @@ -0,0 +1,10649 @@ +[ + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Bypass; Intermediate bypass Taken", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the intermediate bypass.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Bypass; Not Taken", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Bypass; Taken", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the full bypass.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Clockticks of the uncore caching & home agent (CHA)", + "EventName": "UNC_CHA_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts clockticks of the clock controlling the uncore caching and home agent (CHA).", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Clockticks", + "EventCode": "0xC0", + "EventName": "UNC_CHA_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Core PMA Events; C1 State", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.C1_STATE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Core PMA Events; C1 Transition", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.C1_TRANSITION", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Core PMA Events; C6 State", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.C6_STATE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Core PMA Events; C6 Transition", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.C6_TRANSITION", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Core PMA Events; GV", + "EventCode": "0x17", + "EventName": "UNC_CHA_CORE_PMA.GV", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Any Cycle with Multiple Snoops", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0xe2", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Any Single Snoop", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_ONE", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0xe1", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Any Snoop to Remote Node", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0xe4", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Multiple Core Requests", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x42", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Single Core Requests", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.CORE_ONE", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x41", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Core Request to Remote Node", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.CORE_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Multiple Eviction", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x82", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Single Eviction", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x81", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Eviction to Remote Node", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EVICT_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x84", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Multiple External Snoops", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x22", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; Single External Snoops", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_ONE", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued; External Snoop to Remote Node", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "Counter 0 Occupancy", + "EventCode": "0x1F", + "EventName": "UNC_CHA_COUNTER0_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.", + "Unit": "CHA" + }, + { + "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed", + "EventCode": "0x53", + "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP", + "PerPkg": "1", + "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed", + "EventCode": "0x53", + "EventName": "UNC_CHA_DIR_LOOKUP.SNP", + "PerPkg": "1", + "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe", + "EventCode": "0x54", + "EventName": "UNC_CHA_DIR_UPDATE.HA", + "PerPkg": "1", + "PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe", + "EventCode": "0x54", + "EventName": "UNC_CHA_DIR_UPDATE.TOR", + "PerPkg": "1", + "PublicDescription": "Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements; Down", + "EventCode": "0xAE", + "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements; Up", + "EventCode": "0xAE", + "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "FaST wire asserted; Horizontal", + "EventCode": "0xA5", + "EventName": "UNC_CHA_FAST_ASSERTED.HORZ", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "FaST wire asserted; Vertical", + "EventCode": "0xA5", + "EventName": "UNC_CHA_FAST_ASSERTED.VERT", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.EX_RDS", + "PerPkg": "1", + "PublicDescription": "Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state. This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*)", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; Shared hit and op is RdInvOwn, RdInv, Inv*", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.WBMTOE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", + "EventCode": "0x5F", + "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*", + "EventCode": "0x5E", + "EventName": "UNC_CHA_HITME_LOOKUP.READ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", + "EventCode": "0x5E", + "EventName": "UNC_CHA_HITME_LOOKUP.WRITE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Misses in HitMe Cache; No SF/LLC HitS/F and op is RdInvOwn", + "EventCode": "0x60", + "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Misses in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*", + "EventCode": "0x60", + "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of Misses in HitMe Cache; SF/LLC HitS/F and op is RdInvOwn", + "EventCode": "0x60", + "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Deallocate HitME$ on Reads without RspFwdI*", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a local request", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", + "PerPkg": "1", + "PublicDescription": "Received RspFwdI* for a local request, but converted HitME$ to SF entry", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache on RdInvOwn even if not RspFwdI*", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM", + "PerPkg": "1", + "PublicDescription": "Updated HitME$ on RspFwdI* or local HitM/E received for a remote request", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache to SHARed", + "EventCode": "0x61", + "EventName": "UNC_CHA_HITME_UPDATE.SHARED", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Left and Even", + "EventCode": "0xA7", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", + "EventCode": "0xA7", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Right and Even", + "EventCode": "0xA7", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", + "EventCode": "0xA7", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Even", + "EventCode": "0xA9", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", + "EventCode": "0xA9", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Right and Even", + "EventCode": "0xA9", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", + "EventCode": "0xA9", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Left and Even", + "EventCode": "0xAB", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", + "EventCode": "0xAB", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Right and Even", + "EventCode": "0xAB", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", + "EventCode": "0xAB", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal IV Ring in Use; Left", + "EventCode": "0xAD", + "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal IV Ring in Use; Right", + "EventCode": "0xAD", + "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Normal priority reads issued to the memory controller from the CHA", + "EventCode": "0x59", + "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", + "PerPkg": "1", + "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "HA to iMC Reads Issued; ISOCH", + "EventCode": "0x59", + "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY", + "PerPkg": "1", + "PublicDescription": "Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", + "PerPkg": "1", + "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Writes Issued to the iMC by the HA; Full Line MIG", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_MIG", + "PerPkg": "1", + "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Full Line", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "PerPkg": "1", + "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Writes Issued to the iMC by the HA; Partial Non-ISOCH", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Writes Issued to the iMC by the HA; Partial MIG", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG", + "PerPkg": "1", + "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.; Filter for memory controller 5 only.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Partial", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "PerPkg": "1", + "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations", + "EventCode": "0x62", + "EventName": "UNC_CHA_IODC_ALLOC.INVITOM", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations dropped due to IODC Full", + "EventCode": "0x62", + "EventName": "UNC_CHA_IODC_ALLOC.IODCFULL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IDOC allocation dropped due to OSB gate", + "EventCode": "0x62", + "EventName": "UNC_CHA_IODC_ALLOC.OSBGATED", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to any reason", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.ALL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to conflicting transaction", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.SNPOUT", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoE", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoI", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOI", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbPushMtoI", + "EventCode": "0x63", + "EventName": "UNC_CHA_IODC_DEALLOC.WBPUSHMTOI", + "PerPkg": "1", + "PublicDescription": "Moved to Cbo section", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Any Request", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.ANY", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Read transactions", + "UMask": "0x3", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Local", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Remote", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.", + "UMask": "0x91", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; External Snoop Request", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ.", + "UMask": "0x9", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Write Requests", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.WRITE", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.", + "UMask": "0x5", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.F_STATE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Local - All Lines", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x2f", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Local - Lines in E State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x22", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Local - Lines in F State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_F", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Local - Lines in M State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Local - Lines in S State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Remote - All Lines", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x8f", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Remote - Lines in E State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x82", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Remote - Lines in F State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_F", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x88", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Remote - Lines in M State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x81", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Remote - Lines in S State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x84", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Lines in E state", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Lines in F State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_F", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Lines in M state", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized; Lines in S State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S", + "PerPkg": "1", + "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc; CV0 Prefetch Miss", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.CV0_PREF_MISS", + "PerPkg": "1", + "PublicDescription": "Miscellaneous events in the Cbo.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc; CV0 Prefetch Victim", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.CV0_PREF_VIC", + "PerPkg": "1", + "PublicDescription": "Miscellaneous events in the Cbo.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Number of times that an RFO hit in S state.", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.RFO_HIT_S", + "PerPkg": "1", + "PublicDescription": "Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc; Silent Snoop Eviction", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE", + "PerPkg": "1", + "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc; Write Combining Aliasing", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.WC_ALIASING", + "PerPkg": "1", + "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB", + "PerPkg": "1", + "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC0_SMI2", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.EDC0_SMI2", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 2 only.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC1_SMI3", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.EDC1_SMI3", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 3 only.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC2_SMI4", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.EDC2_SMI4", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 4 only.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC3_SMI5", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.EDC3_SMI5", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 5 only.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC0_SMI0", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC0_SMI0", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 0 only.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC1_SMI1", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC1_SMI1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 1 only.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Read requests", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS", + "PerPkg": "1", + "PublicDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) .", + "UMask": "0x3", + "Unit": "CHA" + }, + { + "BriefDescription": "Read requests from a unit on this socket", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Read requests from a remote socket", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Write requests", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES", + "PerPkg": "1", + "PublicDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", + "UMask": "0xc", + "Unit": "CHA" + }, + { + "BriefDescription": "Write Requests from a unit on this socket", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Read and Write Requests; Writes Remote", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD", + "EventCode": "0xA1", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK", + "EventCode": "0xA1", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL", + "EventCode": "0xA1", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV", + "EventCode": "0xA1", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; AD", + "EventCode": "0xA0", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core", + "EventCode": "0xA0", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core", + "EventCode": "0xA0", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.", + "EventCode": "0xA0", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; AD", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; AK", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; BL", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; IV", + "EventCode": "0xA3", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; AD", + "EventCode": "0xA2", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core", + "EventCode": "0xA2", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core", + "EventCode": "0xA2", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.", + "EventCode": "0xA2", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Source Throttle", + "EventCode": "0xA4", + "EventName": "UNC_CHA_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; IPQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IPQ", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; IRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IRQ", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; IRQ Rejected", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; PRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.PRQ", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; PRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; RRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.RRQ", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations; WBQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.WBQ", + "PerPkg": "1", + "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; AD REQ on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; AD RSP on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; Non UPI AK Request", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; BL NCB on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; BL NCS on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; BL RSP on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; BL WB on VN0", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; Non UPI IV Request", + "EventCode": "0x22", + "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; Allow Snoop", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; ANY0", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; HA", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; Merging these two together to make room for ANY_REJECT_*0", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; LLC Victim", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; PhyAddr Match", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; SF Victim", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress Probe Queue Rejects; Victim", + "EventCode": "0x23", + "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Merging these two together to make room for ANY_REJECT_*0", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; AD REQ on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; AD RSP on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; Non UPI AK Request", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; BL NCB on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; BL NCS on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; BL RSP on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; BL WB on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; Non UPI IV Request", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; AD REQ on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; AD RSP on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; Non UPI AK Request", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; BL NCB on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; BL NCS on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; BL RSP on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; BL WB on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; Non UPI IV Request", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; ANY0", + "EventCode": "0x25", + "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects; HA", + "EventCode": "0x25", + "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; ANY0", + "EventCode": "0x2D", + "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries; HA", + "EventCode": "0x2D", + "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy; IPQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ", + "PerPkg": "1", + "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy; IRQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ", + "PerPkg": "1", + "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy; RRQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ", + "PerPkg": "1", + "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy; WBQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ", + "PerPkg": "1", + "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; AD REQ on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; AD RSP on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; Non UPI AK Request", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; BL NCB on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; BL NCS on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; BL RSP on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; BL WB on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; Non UPI IV Request", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; Allow Snoop", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; ANY0", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; HA", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; Merging these two together to make room for ANY_REJECT_*0", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; LLC Victim", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; PhyAddr Match", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; SF Victim", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries; Victim", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM", + "PerPkg": "1", + "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC OR SF Way", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; AD REQ on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; AD RSP on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; Non UPI AK Request", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; BL NCB on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; BL NCS on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; BL RSP on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; BL WB on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; Non UPI IV Request", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; Allow Snoop", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; ANY0", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; HA", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; Merging these two together to make room for ANY_REJECT_*0", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; LLC Victim", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; PhyAddr Match", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; SF Victim", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries; Victim", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", + "PerPkg": "1", + "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; AD REQ on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; AD RSP on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; Non UPI AK Request", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; BL NCB on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; BL NCS on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; BL RSP on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; BL WB on VN0", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; Non UPI IV Request", + "EventCode": "0x26", + "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; Allow Snoop", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; ANY0", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; HA", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; Merging these two together to make room for ANY_REJECT_*0", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; LLC Victim", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; PhyAddr Match", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; SF Victim", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "RRQ Rejects; Victim", + "EventCode": "0x27", + "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; AD REQ on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; AD RSP on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; Non UPI AK Request", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; BL NCB on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; BL NCS on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; BL RSP on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; BL WB on VN0", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; Non UPI IV Request", + "EventCode": "0x28", + "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; Allow Snoop", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; ANY0", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; HA", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; Merging these two together to make room for ANY_REJECT_*0", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; LLC Victim", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; PhyAddr Match", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; SF Victim", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "WBQ Rejects; Victim", + "EventCode": "0x29", + "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM", + "PerPkg": "1", + "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "EventCode": "0xB4", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "EventCode": "0xB4", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "EventCode": "0xB4", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "EventCode": "0xB4", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AD - Credit", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass; BL - Credit", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_CHA_RxR_BYPASS.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; AK - Bounce", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; IFV - Credit", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation; IV - Bounce", + "EventCode": "0xB3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AD - Credit", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations; BL - Credit", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_CHA_RxR_INSERTS.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop filter capacity evictions for E-state entries.", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.E_STATE", + "PerPkg": "1", + "PublicDescription": "Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop filter capacity evictions for M-state entries.", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.M_STATE", + "PerPkg": "1", + "PublicDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop filter capacity evictions for S-state entries.", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.S_STATE", + "PerPkg": "1", + "PublicDescription": "Counts snoop filter capacity evictions for entries tracking shared lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; All", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of snoops issued by the HA.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; Broadcast snoop for Local Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast snoops issued by the HA. This filter includes only requests coming from local sockets.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; Broadcast snoops for Remote Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast snoops issued by the HA.This filter includes only requests coming from remote sockets.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; Directed snoops for Local Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of directed snoops issued by the HA. This filter includes only requests coming from local sockets.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; Directed snoops for Remote Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of directed snoops issued by the HA. This filter includes only requests coming from remote sockets.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Local Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL", + "PerPkg": "1", + "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the local socket.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Remote Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE", + "PerPkg": "1", + "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the remote socket.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "RspCnflct* Snoop Responses Received", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCTS", + "PerPkg": "1", + "PublicDescription": "Counts when a a transaction with the opcode type RspCnflct* Snoop Response was received. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent. This triggers conflict resolution hardware. This covers both the opcode RspCnflct and RspCnflctWbI.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received; RspFwd", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD", + "PerPkg": "1", + "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspFwd to a CA request. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "RspI Snoop Responses Received", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPI", + "PerPkg": "1", + "PublicDescription": "Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data).", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "RspIFwd Snoop Responses Received", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD", + "PerPkg": "1", + "PublicDescription": "Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received : RspS", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPS", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received : RspS : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for snoop responses of RspS. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "RspSFwd Snoop Responses Received", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD", + "PerPkg": "1", + "PublicDescription": "Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Rsp*Fwd*WB Snoop Responses Received", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSP_FWD_WB", + "PerPkg": "1", + "PublicDescription": "Counts when a transaction with the opcode type Rsp*Fwd*WB Snoop Response was received which indicates the data was written back to its home socket, and the cacheline was forwarded to the requestor socket. This snoop response is only used in >= 4 socket systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to its home socket to be written back to memory.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Rsp*WB Snoop Responses Received", + "EventCode": "0x5C", + "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB", + "PerPkg": "1", + "PublicDescription": "Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to its home. This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured. This response will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspCnflct", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoops responses of RspConflict to local CA requests. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspFwd", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspFwd to local CA requests. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspI", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoops responses of RspI to local CA requests. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspIFwd", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoop responses of RspIFwd to local CA requests. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspS", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoop responses of RspS to local CA requests. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; RspSFwd", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspSFwd to local CA requests. This is returned when a remote caching agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of Rsp*Fwd*WB to local CA requests. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local; Rsp*WB", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB", + "PerPkg": "1", + "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspIWB or RspSWB to local CA requests. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Hits from Local", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ALL_HIT", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x15", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; All from Local iA and IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ALL_IO_IA", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests", + "UMask": "0x35", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Misses from Local", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ALL_MISS", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x25", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; SF/LLC Evictions", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.EVICT", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Hit (Not a Miss)", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.HIT", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; HITs (hit is defined to be not a miss [see below], as a result for any request allocated into the TOR, one of either HIT or MISS must be true)", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; All from Local iA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests from iA Cores", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Hits from Local iA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", + "Filter": "config1=0x40233", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", + "Filter": "config1=0x40433", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", + "Filter": "config1=0x4b233", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", + "Filter": "config1=0x4b433", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefRFO", + "Filter": "config1=0x4b033", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", + "Filter": "config1=0x40033", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "Filter": "config1=0x40233", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "Filter": "config1=0x40433", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", + "Filter": "config1=0x4b233", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", + "Filter": "config1=0x4b433", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefRFO", + "Filter": "config1=0x4b033", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", + "Filter": "config1=0x40033", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; All from Local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally generated IO traffic", + "UMask": "0x34", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Hits from Local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x14", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Misses from Local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; ItoM misses from Local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Filter": "config1=0x49033", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that are generated from local IO ItoM requests that miss the LLC. An ItoM request is used by IIO to request a data write without first reading the data for ownership.", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; RdCur misses from Local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RDCUR", + "Filter": "config1=0x43C33", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that are generated from local IO RdCur requests and miss the LLC. A RdCur request is used by IIO to read data without changing state.", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; RFO misses from Local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "Filter": "config1=0x40033", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that are generated from local IO RFO requests that miss the LLC. A read for ownership (RFO) requests a cache line to be cached in E state with the intent to modify.", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; IPQ", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IPQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IPQ_HIT", + "PerPkg": "1", + "UMask": "0x18", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IPQ_MISS", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; IRQ", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IRQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", + "PerPkg": "1", + "UMask": "0x37", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; Miss", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.MISS", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; Misses. (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to a local memory controller, in the event that the CHA is the home node)). Basically, if the LLC/SF/MLC complex were not able to service the request without involving another agent...it is a miss. If only IDI snoops were required, it is not a miss (that means the SF/MLC com", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; PRQ", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.PRQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL", + "PerPkg": "1", + "UMask": "0x30", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.RRQ_HIT", + "PerPkg": "1", + "UMask": "0x50", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS", + "PerPkg": "1", + "UMask": "0x60", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.WBQ_HIT", + "PerPkg": "1", + "UMask": "0x90", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.WBQ_MISS", + "PerPkg": "1", + "UMask": "0xa0", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; All from Local", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All remotely generated requests", + "UMask": "0x37", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Hits from Local", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_HIT", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "UMask": "0x17", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Misses from Local", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_MISS", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "UMask": "0x27", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; SF/LLC Evictions", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Hit (Not a Miss)", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; HITs (hit is defined to be not a miss [see below], as a result for any request allocated into the TOR, one of either HIT or MISS must be true)", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; All from Local iA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; All locally initiated requests from iA Cores", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Hits from Local iA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "Filter": "config1=0x40233", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "Filter": "config1=0x40433", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", + "Filter": "config1=0x4b233", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", + "Filter": "config1=0x4b433", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", + "Filter": "config1=0x4b033", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "Filter": "config1=0x40033", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Misses from Local iA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "Filter": "config1=0x40233", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "Filter": "config1=0x40433", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", + "Filter": "config1=0x4b233", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", + "Filter": "config1=0x4b433", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", + "Filter": "config1=0x4b033", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "Filter": "config1=0x40033", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; All from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; All locally generated IO traffic", + "UMask": "0x34", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Hits from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "UMask": "0x14", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Misses from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; ITOM Misses from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", + "Filter": "config1=0x49033", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO ItoM requests that miss the LLC. An ItoM is used by IIO to request a data write without first reading the data for ownership.", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; RDCUR misses from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RDCUR", + "Filter": "config1=0x43C33", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO RdCur requests that miss the LLC. A RdCur request is used by IIO to read data without changing state.", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; RFO misses from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", + "Filter": "config1=0x40033", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO RFO requests that miss the LLC. A read for ownership (RFO) requests data to be cached in E state with the intent to modify.", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; IPQ", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_HIT", + "PerPkg": "1", + "UMask": "0x18", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_MISS", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; IRQ", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", + "PerPkg": "1", + "UMask": "0x37", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; Miss", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; Misses. (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to a local memory controller, in the event that the CHA is the home node)). Basically, if the LLC/SF/MLC complex were not able to service the request without involving another agent...it is a miss. If only IDI snoops were required, it is not a miss (that means the SF/MLC com", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; PRQ", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ", + "PerPkg": "1", + "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_HORZ_NACK.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used; IV", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.IV", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.IV", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; IV", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_INSERTS.IV", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; IV", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK.IV", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; IV", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.IV", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; AD REQ Credits", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; AD RSP VN0 Credits", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; BL NCB Credits", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; BL NCS Credits", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; BL RSP Credits", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; BL DRS Credits", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_WB", + "PerPkg": "1", + "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; VN0 Credits", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credit Allocations; VNA Credits", + "EventCode": "0x38", + "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VNA", + "PerPkg": "1", + "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; AD REQ VN0 Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_REQ", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; AD RSP VN0 Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_RSP", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCB VN0 Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCB", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCS VN0 Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCS", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL RSP VN0 Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_RSP", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL DRS VN0 Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_WB", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; AD VNA Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_AD", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "UPI Ingress Credits In Use Cycles; BL VNA Credits", + "EventCode": "0x3B", + "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_BL", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Down and Even", + "EventCode": "0xA6", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Down and Odd", + "EventCode": "0xA6", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Up and Even", + "EventCode": "0xA6", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Up and Odd", + "EventCode": "0xA6", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Down and Even", + "EventCode": "0xA8", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Down and Odd", + "EventCode": "0xA8", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Up and Even", + "EventCode": "0xA8", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Up and Odd", + "EventCode": "0xA8", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Down and Even", + "EventCode": "0xAA", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Down and Odd", + "EventCode": "0xAA", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Up and Even", + "EventCode": "0xAA", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Up and Odd", + "EventCode": "0xAA", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical IV Ring in Use; Down", + "EventCode": "0xAC", + "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical IV Ring in Use; Up", + "EventCode": "0xAC", + "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "WbPushMtoI; Pushed to LLC", + "EventCode": "0x56", + "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when the CHA was received WbPushMtoI; Counts the number of times when the CHA was able to push WbPushMToI to LLC", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "WbPushMtoI; Pushed to Memory", + "EventCode": "0x56", + "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when the CHA was received WbPushMtoI; Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC0_SMI2", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 2 only.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC1_SMI3", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 3 only.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC2_SMI4", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 4 only.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC3_SMI5", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 5 only.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC0_SMI0", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 0 only.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC1_SMI1", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 1 only.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Any RspIFwdFE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response I to Fwd F/E", + "UMask": "0xe4", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response I to Fwd M", + "UMask": "0xf0", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdFE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response S to Fwd F/E", + "UMask": "0xe2", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdM", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response S to Fwd M", + "UMask": "0xe8", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Any RspHitFSE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response any to Hit F/S/E", + "UMask": "0xe1", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdFE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response I to Fwd F/E", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdM", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response I to Fwd M", + "UMask": "0x50", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdFE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response S to Fwd F/E", + "UMask": "0x42", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdM", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response S to Fwd M", + "UMask": "0x48", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Core RspHitFSE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response any to Hit F/S/E", + "UMask": "0x41", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdFE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response I to Fwd F/E", + "UMask": "0x84", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdM", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response I to Fwd M", + "UMask": "0x90", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdFE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response S to Fwd F/E", + "UMask": "0x82", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdM", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response S to Fwd M", + "UMask": "0x88", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; Evict RspHitFSE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response any to Hit F/S/E", + "UMask": "0x81", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; External RspIFwdFE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response I to Fwd F/E", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; External RspIFwdM", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response I to Fwd M", + "UMask": "0x30", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; External RspSFwdFE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response S to Fwd F/E", + "UMask": "0x22", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; External RspSFwdM", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response S to Fwd M", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoop Responses; External RspHitFSE", + "EventCode": "0x32", + "EventName": "UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE", + "PerPkg": "1", + "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response any to Hit F/S/E", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CLOCKTICKS", + "Deprecated": "1", + "EventName": "UNC_C_CLOCKTICKS", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_FAST_ASSERTED.HORZ", + "Deprecated": "1", + "EventCode": "0xA5", + "EventName": "UNC_C_FAST_ASSERTED", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.ANY", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.ANY", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.DATA_READ", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOCAL", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.LOCAL", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.REMOTE", + "PerPkg": "1", + "UMask": "0x91", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITE", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_C_LLC_LOOKUP.WRITE", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.E_STATE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.F_STATE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.LOCAL", + "PerPkg": "1", + "UMask": "0x2f", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.M_STATE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.REMOTE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S", + "Deprecated": "1", + "EventCode": "0x37", + "EventName": "UNC_C_LLC_VICTIMS.S_STATE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SRC_THRTL", + "Deprecated": "1", + "EventCode": "0xA4", + "EventName": "UNC_C_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.EVICT", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.EVICT", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.HIT", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.HIT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IPQ", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IPQ", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IPQ_HIT", + "PerPkg": "1", + "UMask": "0x18", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IPQ_MISS", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IRQ", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IRQ_HIT", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.IRQ_MISS", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.LOC_ALL", + "PerPkg": "1", + "UMask": "0x37", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.LOC_IA", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.LOC_IO", + "PerPkg": "1", + "UMask": "0x34", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.MISS", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.PRQ", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.PRQ", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_HIT", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.PRQ_HIT", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_MISS", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.PRQ_MISS", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.REM_ALL", + "PerPkg": "1", + "UMask": "0x30", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.RRQ_HIT", + "PerPkg": "1", + "UMask": "0x50", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.RRQ_MISS", + "PerPkg": "1", + "UMask": "0x60", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.WBQ_HIT", + "PerPkg": "1", + "UMask": "0x90", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_C_TOR_INSERTS.WBQ_MISS", + "PerPkg": "1", + "UMask": "0xa0", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.EVICT", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.EVICT", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.HIT", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.HIT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IPQ", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IPQ", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_HIT", + "PerPkg": "1", + "UMask": "0x18", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_MISS", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IRQ", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_HIT", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_HIT", + "PerPkg": "1", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_MISS", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_MISS", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.LOC_ALL", + "PerPkg": "1", + "UMask": "0x37", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IA", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IO", + "PerPkg": "1", + "UMask": "0x34", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.MISS", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.PRQ", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.PRQ", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_HIT", + "PerPkg": "1", + "UMask": "0x14", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "Deprecated": "1", + "EventCode": "0x36", + "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_MISS", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0", + "Deprecated": "1", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1", + "Deprecated": "1", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2", + "Deprecated": "1", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3", + "Deprecated": "1", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4", + "Deprecated": "1", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5", + "Deprecated": "1", + "EventCode": "0x80", + "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0", + "Deprecated": "1", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1", + "Deprecated": "1", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2", + "Deprecated": "1", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3", + "Deprecated": "1", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4", + "Deprecated": "1", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5", + "Deprecated": "1", + "EventCode": "0x82", + "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0", + "Deprecated": "1", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1", + "Deprecated": "1", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2", + "Deprecated": "1", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3", + "Deprecated": "1", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4", + "Deprecated": "1", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5", + "Deprecated": "1", + "EventCode": "0x88", + "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0", + "Deprecated": "1", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1", + "Deprecated": "1", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2", + "Deprecated": "1", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3", + "Deprecated": "1", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4", + "Deprecated": "1", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5", + "Deprecated": "1", + "EventCode": "0x8A", + "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0", + "Deprecated": "1", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1", + "Deprecated": "1", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2", + "Deprecated": "1", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3", + "Deprecated": "1", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4", + "Deprecated": "1", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5", + "Deprecated": "1", + "EventCode": "0x86", + "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0", + "Deprecated": "1", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1", + "Deprecated": "1", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2", + "Deprecated": "1", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3", + "Deprecated": "1", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4", + "Deprecated": "1", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5", + "Deprecated": "1", + "EventCode": "0x8E", + "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0", + "Deprecated": "1", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1", + "Deprecated": "1", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2", + "Deprecated": "1", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3", + "Deprecated": "1", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4", + "Deprecated": "1", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5", + "Deprecated": "1", + "EventCode": "0x8C", + "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", + "Deprecated": "1", + "EventCode": "0x57", + "EventName": "UNC_H_BYPASS_CHA_IMC.INTERMEDIATE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", + "Deprecated": "1", + "EventCode": "0x57", + "EventName": "UNC_H_BYPASS_CHA_IMC.NOT_TAKEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.TAKEN", + "Deprecated": "1", + "EventCode": "0x57", + "EventName": "UNC_H_BYPASS_CHA_IMC.TAKEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CMS_CLOCKTICKS", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_H_CLOCK", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C1_STATE", + "Deprecated": "1", + "EventCode": "0x17", + "EventName": "UNC_H_CORE_PMA.C1_STATE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C1_TRANSITION", + "Deprecated": "1", + "EventCode": "0x17", + "EventName": "UNC_H_CORE_PMA.C1_TRANSITION", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C6_STATE", + "Deprecated": "1", + "EventCode": "0x17", + "EventName": "UNC_H_CORE_PMA.C6_STATE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C6_TRANSITION", + "Deprecated": "1", + "EventCode": "0x17", + "EventName": "UNC_H_CORE_PMA.C6_TRANSITION", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.GV", + "Deprecated": "1", + "EventCode": "0x17", + "EventName": "UNC_H_CORE_PMA.GV", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_GTONE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.ANY_GTONE", + "PerPkg": "1", + "UMask": "0xe2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_ONE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.ANY_ONE", + "PerPkg": "1", + "UMask": "0xe1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_REMOTE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.ANY_REMOTE", + "PerPkg": "1", + "UMask": "0xe4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.CORE_GTONE", + "PerPkg": "1", + "UMask": "0x42", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_ONE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.CORE_ONE", + "PerPkg": "1", + "UMask": "0x41", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_REMOTE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.CORE_REMOTE", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.EVICT_GTONE", + "PerPkg": "1", + "UMask": "0x82", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_ONE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.EVICT_ONE", + "PerPkg": "1", + "UMask": "0x81", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_REMOTE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.EVICT_REMOTE", + "PerPkg": "1", + "UMask": "0x84", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_GTONE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.EXT_GTONE", + "PerPkg": "1", + "UMask": "0x22", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_ONE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.EXT_ONE", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_REMOTE", + "Deprecated": "1", + "EventCode": "0x33", + "EventName": "UNC_H_CORE_SNP.EXT_REMOTE", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_COUNTER0_OCCUPANCY", + "Deprecated": "1", + "EventCode": "0x1F", + "EventName": "UNC_H_COUNTER0_OCCUPANCY", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP", + "Deprecated": "1", + "EventCode": "0x53", + "EventName": "UNC_H_DIR_LOOKUP.NO_SNP", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP", + "Deprecated": "1", + "EventCode": "0x53", + "EventName": "UNC_H_DIR_LOOKUP.SNP", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA", + "Deprecated": "1", + "EventCode": "0x54", + "EventName": "UNC_H_DIR_UPDATE.HA", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR", + "Deprecated": "1", + "EventCode": "0x54", + "EventName": "UNC_H_DIR_UPDATE.TOR", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Deprecated": "1", + "EventCode": "0xAE", + "EventName": "UNC_H_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Deprecated": "1", + "EventCode": "0xAE", + "EventName": "UNC_H_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS", + "Deprecated": "1", + "EventCode": "0x5F", + "EventName": "UNC_H_HITME_HIT.EX_RDS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.SHARED_OWNREQ", + "Deprecated": "1", + "EventCode": "0x5F", + "EventName": "UNC_H_HITME_HIT.SHARED_OWNREQ", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.WBMTOE", + "Deprecated": "1", + "EventCode": "0x5F", + "EventName": "UNC_H_HITME_HIT.WBMTOE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.WBMTOI_OR_S", + "Deprecated": "1", + "EventCode": "0x5F", + "EventName": "UNC_H_HITME_HIT.WBMTOI_OR_S", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_LOOKUP.READ", + "Deprecated": "1", + "EventCode": "0x5E", + "EventName": "UNC_H_HITME_LOOKUP.READ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_LOOKUP.WRITE", + "Deprecated": "1", + "EventCode": "0x5E", + "EventName": "UNC_H_HITME_LOOKUP.WRITE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN", + "Deprecated": "1", + "EventCode": "0x60", + "EventName": "UNC_H_HITME_MISS.NOTSHARED_RDINVOWN", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.READ_OR_INV", + "Deprecated": "1", + "EventCode": "0x60", + "EventName": "UNC_H_HITME_MISS.READ_OR_INV", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.SHARED_RDINVOWN", + "Deprecated": "1", + "EventCode": "0x60", + "EventName": "UNC_H_HITME_MISS.SHARED_RDINVOWN", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.DEALLOCATE", + "Deprecated": "1", + "EventCode": "0x61", + "EventName": "UNC_H_HITME_UPDATE.DEALLOCATE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", + "Deprecated": "1", + "EventCode": "0x61", + "EventName": "UNC_H_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.RDINVOWN", + "Deprecated": "1", + "EventCode": "0x61", + "EventName": "UNC_H_HITME_UPDATE.RDINVOWN", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.RSPFWDI_REM", + "Deprecated": "1", + "EventCode": "0x61", + "EventName": "UNC_H_HITME_UPDATE.RSPFWDI_REM", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.SHARED", + "Deprecated": "1", + "EventCode": "0x61", + "EventName": "UNC_H_HITME_UPDATE.SHARED", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "Deprecated": "1", + "EventCode": "0xA7", + "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", + "Deprecated": "1", + "EventCode": "0xA7", + "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "Deprecated": "1", + "EventCode": "0xA7", + "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "Deprecated": "1", + "EventCode": "0xA7", + "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "Deprecated": "1", + "EventCode": "0xA9", + "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", + "Deprecated": "1", + "EventCode": "0xA9", + "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "Deprecated": "1", + "EventCode": "0xA9", + "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "Deprecated": "1", + "EventCode": "0xA9", + "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "Deprecated": "1", + "EventCode": "0xAB", + "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", + "Deprecated": "1", + "EventCode": "0xAB", + "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "Deprecated": "1", + "EventCode": "0xAB", + "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "Deprecated": "1", + "EventCode": "0xAB", + "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", + "Deprecated": "1", + "EventCode": "0xAD", + "EventName": "UNC_H_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", + "Deprecated": "1", + "EventCode": "0xAD", + "EventName": "UNC_H_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_READS_COUNT.NORMAL", + "Deprecated": "1", + "EventCode": "0x59", + "EventName": "UNC_H_IMC_READS_COUNT.NORMAL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_READS_COUNT.PRIORITY", + "Deprecated": "1", + "EventCode": "0x59", + "EventName": "UNC_H_IMC_READS_COUNT.PRIORITY", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL", + "Deprecated": "1", + "EventCode": "0x5B", + "EventName": "UNC_H_IMC_WRITES_COUNT.FULL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL_MIG", + "Deprecated": "1", + "EventCode": "0x5B", + "EventName": "UNC_H_IMC_WRITES_COUNT.FULL_MIG", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "Deprecated": "1", + "EventCode": "0x5B", + "EventName": "UNC_H_IMC_WRITES_COUNT.FULL_PRIORITY", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "Deprecated": "1", + "EventCode": "0x5B", + "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG", + "Deprecated": "1", + "EventCode": "0x5B", + "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL_MIG", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "Deprecated": "1", + "EventCode": "0x5B", + "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.INVITOM", + "Deprecated": "1", + "EventCode": "0x62", + "EventName": "UNC_H_IODC_ALLOC.INVITOM", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.IODCFULL", + "Deprecated": "1", + "EventCode": "0x62", + "EventName": "UNC_H_IODC_ALLOC.IODCFULL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.OSBGATED", + "Deprecated": "1", + "EventCode": "0x62", + "EventName": "UNC_H_IODC_ALLOC.OSBGATED", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.ALL", + "Deprecated": "1", + "EventCode": "0x63", + "EventName": "UNC_H_IODC_DEALLOC.ALL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.SNPOUT", + "Deprecated": "1", + "EventCode": "0x63", + "EventName": "UNC_H_IODC_DEALLOC.SNPOUT", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBMTOE", + "Deprecated": "1", + "EventCode": "0x63", + "EventName": "UNC_H_IODC_DEALLOC.WBMTOE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBMTOI", + "Deprecated": "1", + "EventCode": "0x63", + "EventName": "UNC_H_IODC_DEALLOC.WBMTOI", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBPUSHMTOI", + "Deprecated": "1", + "EventCode": "0x63", + "EventName": "UNC_H_IODC_DEALLOC.WBPUSHMTOI", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.CV0_PREF_MISS", + "Deprecated": "1", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.CV0_PREF_MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.CV0_PREF_VIC", + "Deprecated": "1", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.CV0_PREF_VIC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S", + "Deprecated": "1", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.RFO_HIT_S", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RSPI_WAS_FSE", + "Deprecated": "1", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.RSPI_WAS_FSE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.WC_ALIASING", + "Deprecated": "1", + "EventCode": "0x39", + "EventName": "UNC_H_MISC.WC_ALIASING", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_OSB", + "Deprecated": "1", + "EventCode": "0x55", + "EventName": "UNC_H_OSB", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC0_SMI2", + "Deprecated": "1", + "EventCode": "0x58", + "EventName": "UNC_H_READ_NO_CREDITS.EDC0_SMI2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC1_SMI3", + "Deprecated": "1", + "EventCode": "0x58", + "EventName": "UNC_H_READ_NO_CREDITS.EDC1_SMI3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC2_SMI4", + "Deprecated": "1", + "EventCode": "0x58", + "EventName": "UNC_H_READ_NO_CREDITS.EDC2_SMI4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC3_SMI5", + "Deprecated": "1", + "EventCode": "0x58", + "EventName": "UNC_H_READ_NO_CREDITS.EDC3_SMI5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.MC0_SMI0", + "Deprecated": "1", + "EventCode": "0x58", + "EventName": "UNC_H_READ_NO_CREDITS.MC0_SMI0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.MC1_SMI1", + "Deprecated": "1", + "EventCode": "0x58", + "EventName": "UNC_H_READ_NO_CREDITS.MC1_SMI1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "read requests from home agent", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.READS", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "CHA" + }, + { + "BriefDescription": "read requests from local home agent", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.READS_LOCAL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "read requests from remote home agent", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.READS_REMOTE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "write requests from home agent", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.WRITES", + "PerPkg": "1", + "UMask": "0xc", + "Unit": "CHA" + }, + { + "BriefDescription": "write requests from local home agent", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.WRITES_LOCAL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "write requests from remote home agent", + "Deprecated": "1", + "EventCode": "0x50", + "EventName": "UNC_H_REQUESTS.WRITES_REMOTE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.AD", + "Deprecated": "1", + "EventCode": "0xA1", + "EventName": "UNC_H_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.AK", + "Deprecated": "1", + "EventCode": "0xA1", + "EventName": "UNC_H_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.BL", + "Deprecated": "1", + "EventCode": "0xA1", + "EventName": "UNC_H_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.IV", + "Deprecated": "1", + "EventCode": "0xA1", + "EventName": "UNC_H_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.AD", + "Deprecated": "1", + "EventCode": "0xA0", + "EventName": "UNC_H_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.AK", + "Deprecated": "1", + "EventCode": "0xA0", + "EventName": "UNC_H_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.BL", + "Deprecated": "1", + "EventCode": "0xA0", + "EventName": "UNC_H_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.IV", + "Deprecated": "1", + "EventCode": "0xA0", + "EventName": "UNC_H_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AD", + "Deprecated": "1", + "EventCode": "0xA3", + "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AK", + "Deprecated": "1", + "EventCode": "0xA3", + "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", + "Deprecated": "1", + "EventCode": "0xA3", + "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.BL", + "Deprecated": "1", + "EventCode": "0xA3", + "EventName": "UNC_H_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.IV", + "Deprecated": "1", + "EventCode": "0xA3", + "EventName": "UNC_H_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.AD", + "Deprecated": "1", + "EventCode": "0xA2", + "EventName": "UNC_H_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.AK", + "Deprecated": "1", + "EventCode": "0xA2", + "EventName": "UNC_H_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.BL", + "Deprecated": "1", + "EventCode": "0xA2", + "EventName": "UNC_H_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.IV", + "Deprecated": "1", + "EventCode": "0xA2", + "EventName": "UNC_H_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IPQ", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.IPQ", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.IRQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ_REJ", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.IRQ_REJ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.PRQ", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.PRQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.PRQ_REJ", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.PRQ_REJ", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.RRQ", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.RRQ", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.WBQ", + "Deprecated": "1", + "EventCode": "0x13", + "EventName": "UNC_H_RxC_INSERTS.WBQ", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x22", + "EventName": "UNC_H_RxC_IPQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x22", + "EventName": "UNC_H_RxC_IPQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x22", + "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x22", + "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x22", + "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x22", + "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ANY0", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.ANY_IPQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.HA", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.VICTIM", + "Deprecated": "1", + "EventCode": "0x23", + "EventName": "UNC_H_RxC_IPQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x18", + "EventName": "UNC_H_RxC_IRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x18", + "EventName": "UNC_H_RxC_IRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x18", + "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x18", + "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x18", + "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x18", + "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ANY0", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.ANY_REJECT_IRQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.HA", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.VICTIM", + "Deprecated": "1", + "EventCode": "0x19", + "EventName": "UNC_H_RxC_IRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x24", + "EventName": "UNC_H_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x24", + "EventName": "UNC_H_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x24", + "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x24", + "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x24", + "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x24", + "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x2C", + "EventName": "UNC_H_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x2C", + "EventName": "UNC_H_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x2C", + "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x2C", + "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x2C", + "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x2C", + "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.ANY0", + "Deprecated": "1", + "EventCode": "0x25", + "EventName": "UNC_H_RxC_ISMQ1_REJECT.ANY_ISMQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.HA", + "Deprecated": "1", + "EventCode": "0x25", + "EventName": "UNC_H_RxC_ISMQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.ANY0", + "Deprecated": "1", + "EventCode": "0x2D", + "EventName": "UNC_H_RxC_ISMQ1_RETRY.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.HA", + "Deprecated": "1", + "EventCode": "0x2D", + "EventName": "UNC_H_RxC_ISMQ1_RETRY.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IPQ", + "Deprecated": "1", + "EventCode": "0x11", + "EventName": "UNC_H_RxC_OCCUPANCY.IPQ", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ", + "Deprecated": "1", + "EventCode": "0x11", + "EventName": "UNC_H_RxC_OCCUPANCY.IRQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.RRQ", + "Deprecated": "1", + "EventCode": "0x11", + "EventName": "UNC_H_RxC_OCCUPANCY.RRQ", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.WBQ", + "Deprecated": "1", + "EventCode": "0x11", + "EventName": "UNC_H_RxC_OCCUPANCY.WBQ", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x2E", + "EventName": "UNC_H_RxC_OTHER0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x2E", + "EventName": "UNC_H_RxC_OTHER0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x2E", + "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x2E", + "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x2E", + "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x2E", + "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ANY0", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.HA", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.VICTIM", + "Deprecated": "1", + "EventCode": "0x2F", + "EventName": "UNC_H_RxC_OTHER1_RETRY.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x20", + "EventName": "UNC_H_RxC_PRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x20", + "EventName": "UNC_H_RxC_PRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x20", + "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x20", + "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x20", + "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x20", + "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ANY0", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.ANY_PRQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.HA", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.VICTIM", + "Deprecated": "1", + "EventCode": "0x21", + "EventName": "UNC_H_RxC_PRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x2A", + "EventName": "UNC_H_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x2A", + "EventName": "UNC_H_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x2A", + "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x2A", + "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x2A", + "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x2A", + "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.HA", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", + "Deprecated": "1", + "EventCode": "0x2B", + "EventName": "UNC_H_RxC_REQ_Q1_RETRY.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x26", + "EventName": "UNC_H_RxC_RRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x26", + "EventName": "UNC_H_RxC_RRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x26", + "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x26", + "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x26", + "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x26", + "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ANY0", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.ANY_RRQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.HA", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.VICTIM", + "Deprecated": "1", + "EventCode": "0x27", + "EventName": "UNC_H_RxC_RRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0", + "Deprecated": "1", + "EventCode": "0x28", + "EventName": "UNC_H_RxC_WBQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x28", + "EventName": "UNC_H_RxC_WBQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0", + "Deprecated": "1", + "EventCode": "0x28", + "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0", + "Deprecated": "1", + "EventCode": "0x28", + "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0", + "Deprecated": "1", + "EventCode": "0x28", + "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0", + "Deprecated": "1", + "EventCode": "0x28", + "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ANY0", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.ANY_WBQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.HA", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.VICTIM", + "Deprecated": "1", + "EventCode": "0x29", + "EventName": "UNC_H_RxC_WBQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.AD_BNC", + "Deprecated": "1", + "EventCode": "0xB4", + "EventName": "UNC_H_RxR_BUSY_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.AD_CRD", + "Deprecated": "1", + "EventCode": "0xB4", + "EventName": "UNC_H_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.BL_BNC", + "Deprecated": "1", + "EventCode": "0xB4", + "EventName": "UNC_H_RxR_BUSY_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.BL_CRD", + "Deprecated": "1", + "EventCode": "0xB4", + "EventName": "UNC_H_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AD_BNC", + "Deprecated": "1", + "EventCode": "0xB2", + "EventName": "UNC_H_RxR_BYPASS.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AD_CRD", + "Deprecated": "1", + "EventCode": "0xB2", + "EventName": "UNC_H_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AK_BNC", + "Deprecated": "1", + "EventCode": "0xB2", + "EventName": "UNC_H_RxR_BYPASS.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.BL_BNC", + "Deprecated": "1", + "EventCode": "0xB2", + "EventName": "UNC_H_RxR_BYPASS.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.BL_CRD", + "Deprecated": "1", + "EventCode": "0xB2", + "EventName": "UNC_H_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.IV_BNC", + "Deprecated": "1", + "EventCode": "0xB2", + "EventName": "UNC_H_RxR_BYPASS.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AD_BNC", + "Deprecated": "1", + "EventCode": "0xB3", + "EventName": "UNC_H_RxR_CRD_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AD_CRD", + "Deprecated": "1", + "EventCode": "0xB3", + "EventName": "UNC_H_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AK_BNC", + "Deprecated": "1", + "EventCode": "0xB3", + "EventName": "UNC_H_RxR_CRD_STARVED.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.BL_BNC", + "Deprecated": "1", + "EventCode": "0xB3", + "EventName": "UNC_H_RxR_CRD_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.BL_CRD", + "Deprecated": "1", + "EventCode": "0xB3", + "EventName": "UNC_H_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.IFV", + "Deprecated": "1", + "EventCode": "0xB3", + "EventName": "UNC_H_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.IV_BNC", + "Deprecated": "1", + "EventCode": "0xB3", + "EventName": "UNC_H_RxR_CRD_STARVED.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AD_BNC", + "Deprecated": "1", + "EventCode": "0xB1", + "EventName": "UNC_H_RxR_INSERTS.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AD_CRD", + "Deprecated": "1", + "EventCode": "0xB1", + "EventName": "UNC_H_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AK_BNC", + "Deprecated": "1", + "EventCode": "0xB1", + "EventName": "UNC_H_RxR_INSERTS.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.BL_BNC", + "Deprecated": "1", + "EventCode": "0xB1", + "EventName": "UNC_H_RxR_INSERTS.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.BL_CRD", + "Deprecated": "1", + "EventCode": "0xB1", + "EventName": "UNC_H_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.IV_BNC", + "Deprecated": "1", + "EventCode": "0xB1", + "EventName": "UNC_H_RxR_INSERTS.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AD_BNC", + "Deprecated": "1", + "EventCode": "0xB0", + "EventName": "UNC_H_RxR_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AD_CRD", + "Deprecated": "1", + "EventCode": "0xB0", + "EventName": "UNC_H_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AK_BNC", + "Deprecated": "1", + "EventCode": "0xB0", + "EventName": "UNC_H_RxR_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.BL_BNC", + "Deprecated": "1", + "EventCode": "0xB0", + "EventName": "UNC_H_RxR_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.BL_CRD", + "Deprecated": "1", + "EventCode": "0xB0", + "EventName": "UNC_H_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.IV_BNC", + "Deprecated": "1", + "EventCode": "0xB0", + "EventName": "UNC_H_RxR_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.E_STATE", + "Deprecated": "1", + "EventCode": "0x3D", + "EventName": "UNC_H_SF_EVICTION.E_STATE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.M_STATE", + "Deprecated": "1", + "EventCode": "0x3D", + "EventName": "UNC_H_SF_EVICTION.M_STATE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.S_STATE", + "Deprecated": "1", + "EventCode": "0x3D", + "EventName": "UNC_H_SF_EVICTION.S_STATE", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.ALL", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_LOCAL", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.BCST_LOC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_REMOTE", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.BCST_REM", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.DIRECT_LOC", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.DIRECT_REM", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.LOCAL", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.LOCAL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.REMOTE", + "Deprecated": "1", + "EventCode": "0x51", + "EventName": "UNC_H_SNOOPS_SENT.REMOTE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPCNFLCTS", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPFWD", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPFWD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPI", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPI", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPIFWD", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPS", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_WBWB", + "Deprecated": "1", + "EventCode": "0x5C", + "EventName": "UNC_H_SNOOP_RESP.RSP_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPCNFLCT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPFWD", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPI", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPI", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPIFWD", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPS", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPSFWD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_FWD_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB", + "Deprecated": "1", + "EventCode": "0x5D", + "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_WB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "Deprecated": "1", + "EventCode": "0xD0", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "Deprecated": "1", + "EventCode": "0xD0", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "Deprecated": "1", + "EventCode": "0xD0", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "Deprecated": "1", + "EventCode": "0xD0", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "Deprecated": "1", + "EventCode": "0xD0", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "Deprecated": "1", + "EventCode": "0xD0", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "Deprecated": "1", + "EventCode": "0xD2", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "Deprecated": "1", + "EventCode": "0xD2", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "Deprecated": "1", + "EventCode": "0xD2", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "Deprecated": "1", + "EventCode": "0xD2", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "Deprecated": "1", + "EventCode": "0xD2", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "Deprecated": "1", + "EventCode": "0xD2", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "Deprecated": "1", + "EventCode": "0xD4", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "Deprecated": "1", + "EventCode": "0xD4", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "Deprecated": "1", + "EventCode": "0xD4", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "Deprecated": "1", + "EventCode": "0xD4", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "Deprecated": "1", + "EventCode": "0xD4", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "Deprecated": "1", + "EventCode": "0xD4", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "Deprecated": "1", + "EventCode": "0xD6", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "Deprecated": "1", + "EventCode": "0xD6", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "Deprecated": "1", + "EventCode": "0xD6", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "Deprecated": "1", + "EventCode": "0xD6", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "Deprecated": "1", + "EventCode": "0xD6", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "Deprecated": "1", + "EventCode": "0xD6", + "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC", + "Deprecated": "1", + "EventCode": "0x9D", + "EventName": "UNC_H_TxR_HORZ_ADS_USED.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", + "Deprecated": "1", + "EventCode": "0x9D", + "EventName": "UNC_H_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC", + "Deprecated": "1", + "EventCode": "0x9D", + "EventName": "UNC_H_TxR_HORZ_ADS_USED.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC", + "Deprecated": "1", + "EventCode": "0x9D", + "EventName": "UNC_H_TxR_HORZ_ADS_USED.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", + "Deprecated": "1", + "EventCode": "0x9D", + "EventName": "UNC_H_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AD_BNC", + "Deprecated": "1", + "EventCode": "0x9F", + "EventName": "UNC_H_TxR_HORZ_BYPASS.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", + "Deprecated": "1", + "EventCode": "0x9F", + "EventName": "UNC_H_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AK_BNC", + "Deprecated": "1", + "EventCode": "0x9F", + "EventName": "UNC_H_TxR_HORZ_BYPASS.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.BL_BNC", + "Deprecated": "1", + "EventCode": "0x9F", + "EventName": "UNC_H_TxR_HORZ_BYPASS.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", + "Deprecated": "1", + "EventCode": "0x9F", + "EventName": "UNC_H_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.IV_BNC", + "Deprecated": "1", + "EventCode": "0x9F", + "EventName": "UNC_H_TxR_HORZ_BYPASS.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC", + "Deprecated": "1", + "EventCode": "0x96", + "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", + "Deprecated": "1", + "EventCode": "0x96", + "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC", + "Deprecated": "1", + "EventCode": "0x96", + "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC", + "Deprecated": "1", + "EventCode": "0x96", + "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", + "Deprecated": "1", + "EventCode": "0x96", + "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC", + "Deprecated": "1", + "EventCode": "0x96", + "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC", + "Deprecated": "1", + "EventCode": "0x97", + "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", + "Deprecated": "1", + "EventCode": "0x97", + "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC", + "Deprecated": "1", + "EventCode": "0x97", + "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC", + "Deprecated": "1", + "EventCode": "0x97", + "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", + "Deprecated": "1", + "EventCode": "0x97", + "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC", + "Deprecated": "1", + "EventCode": "0x97", + "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AD_BNC", + "Deprecated": "1", + "EventCode": "0x95", + "EventName": "UNC_H_TxR_HORZ_INSERTS.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", + "Deprecated": "1", + "EventCode": "0x95", + "EventName": "UNC_H_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AK_BNC", + "Deprecated": "1", + "EventCode": "0x95", + "EventName": "UNC_H_TxR_HORZ_INSERTS.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.BL_BNC", + "Deprecated": "1", + "EventCode": "0x95", + "EventName": "UNC_H_TxR_HORZ_INSERTS.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", + "Deprecated": "1", + "EventCode": "0x95", + "EventName": "UNC_H_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.IV_BNC", + "Deprecated": "1", + "EventCode": "0x95", + "EventName": "UNC_H_TxR_HORZ_INSERTS.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AD_BNC", + "Deprecated": "1", + "EventCode": "0x99", + "EventName": "UNC_H_TxR_HORZ_NACK.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AD_CRD", + "Deprecated": "1", + "EventCode": "0x99", + "EventName": "UNC_H_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AK_BNC", + "Deprecated": "1", + "EventCode": "0x99", + "EventName": "UNC_H_TxR_HORZ_NACK.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.BL_BNC", + "Deprecated": "1", + "EventCode": "0x99", + "EventName": "UNC_H_TxR_HORZ_NACK.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.BL_CRD", + "Deprecated": "1", + "EventCode": "0x99", + "EventName": "UNC_H_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.IV_BNC", + "Deprecated": "1", + "EventCode": "0x99", + "EventName": "UNC_H_TxR_HORZ_NACK.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC", + "Deprecated": "1", + "EventCode": "0x94", + "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", + "Deprecated": "1", + "EventCode": "0x94", + "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC", + "Deprecated": "1", + "EventCode": "0x94", + "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC", + "Deprecated": "1", + "EventCode": "0x94", + "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", + "Deprecated": "1", + "EventCode": "0x94", + "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC", + "Deprecated": "1", + "EventCode": "0x94", + "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.AD_BNC", + "Deprecated": "1", + "EventCode": "0x9B", + "EventName": "UNC_H_TxR_HORZ_STARVED.AD_BNC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.AK_BNC", + "Deprecated": "1", + "EventCode": "0x9B", + "EventName": "UNC_H_TxR_HORZ_STARVED.AK_BNC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.BL_BNC", + "Deprecated": "1", + "EventCode": "0x9B", + "EventName": "UNC_H_TxR_HORZ_STARVED.BL_BNC", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.IV_BNC", + "Deprecated": "1", + "EventCode": "0x9B", + "EventName": "UNC_H_TxR_HORZ_STARVED.IV_BNC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", + "Deprecated": "1", + "EventCode": "0x9C", + "EventName": "UNC_H_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", + "Deprecated": "1", + "EventCode": "0x9C", + "EventName": "UNC_H_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AK_AG0", + "Deprecated": "1", + "EventCode": "0x9C", + "EventName": "UNC_H_TxR_VERT_ADS_USED.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AK_AG1", + "Deprecated": "1", + "EventCode": "0x9C", + "EventName": "UNC_H_TxR_VERT_ADS_USED.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", + "Deprecated": "1", + "EventCode": "0x9C", + "EventName": "UNC_H_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", + "Deprecated": "1", + "EventCode": "0x9C", + "EventName": "UNC_H_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AD_AG0", + "Deprecated": "1", + "EventCode": "0x9E", + "EventName": "UNC_H_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AD_AG1", + "Deprecated": "1", + "EventCode": "0x9E", + "EventName": "UNC_H_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AK_AG0", + "Deprecated": "1", + "EventCode": "0x9E", + "EventName": "UNC_H_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AK_AG1", + "Deprecated": "1", + "EventCode": "0x9E", + "EventName": "UNC_H_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.BL_AG0", + "Deprecated": "1", + "EventCode": "0x9E", + "EventName": "UNC_H_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.BL_AG1", + "Deprecated": "1", + "EventCode": "0x9E", + "EventName": "UNC_H_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.IV", + "Deprecated": "1", + "EventCode": "0x9E", + "EventName": "UNC_H_TxR_VERT_BYPASS.IV_AG1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0", + "Deprecated": "1", + "EventCode": "0x92", + "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1", + "Deprecated": "1", + "EventCode": "0x92", + "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0", + "Deprecated": "1", + "EventCode": "0x92", + "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1", + "Deprecated": "1", + "EventCode": "0x92", + "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0", + "Deprecated": "1", + "EventCode": "0x92", + "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1", + "Deprecated": "1", + "EventCode": "0x92", + "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.IV", + "Deprecated": "1", + "EventCode": "0x92", + "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0", + "Deprecated": "1", + "EventCode": "0x93", + "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1", + "Deprecated": "1", + "EventCode": "0x93", + "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0", + "Deprecated": "1", + "EventCode": "0x93", + "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1", + "Deprecated": "1", + "EventCode": "0x93", + "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0", + "Deprecated": "1", + "EventCode": "0x93", + "EventName": "UNC_H_TxR_VERT_CYCLES_NE.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1", + "Deprecated": "1", + "EventCode": "0x93", + "EventName": "UNC_H_TxR_VERT_CYCLES_NE.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.IV", + "Deprecated": "1", + "EventCode": "0x93", + "EventName": "UNC_H_TxR_VERT_CYCLES_NE.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AD_AG0", + "Deprecated": "1", + "EventCode": "0x91", + "EventName": "UNC_H_TxR_VERT_INSERTS.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AD_AG1", + "Deprecated": "1", + "EventCode": "0x91", + "EventName": "UNC_H_TxR_VERT_INSERTS.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AK_AG0", + "Deprecated": "1", + "EventCode": "0x91", + "EventName": "UNC_H_TxR_VERT_INSERTS.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AK_AG1", + "Deprecated": "1", + "EventCode": "0x91", + "EventName": "UNC_H_TxR_VERT_INSERTS.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.BL_AG0", + "Deprecated": "1", + "EventCode": "0x91", + "EventName": "UNC_H_TxR_VERT_INSERTS.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.BL_AG1", + "Deprecated": "1", + "EventCode": "0x91", + "EventName": "UNC_H_TxR_VERT_INSERTS.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.IV", + "Deprecated": "1", + "EventCode": "0x91", + "EventName": "UNC_H_TxR_VERT_INSERTS.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AD_AG0", + "Deprecated": "1", + "EventCode": "0x98", + "EventName": "UNC_H_TxR_VERT_NACK.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AD_AG1", + "Deprecated": "1", + "EventCode": "0x98", + "EventName": "UNC_H_TxR_VERT_NACK.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AK_AG0", + "Deprecated": "1", + "EventCode": "0x98", + "EventName": "UNC_H_TxR_VERT_NACK.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AK_AG1", + "Deprecated": "1", + "EventCode": "0x98", + "EventName": "UNC_H_TxR_VERT_NACK.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.BL_AG0", + "Deprecated": "1", + "EventCode": "0x98", + "EventName": "UNC_H_TxR_VERT_NACK.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.BL_AG1", + "Deprecated": "1", + "EventCode": "0x98", + "EventName": "UNC_H_TxR_VERT_NACK.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.IV", + "Deprecated": "1", + "EventCode": "0x98", + "EventName": "UNC_H_TxR_VERT_NACK.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0", + "Deprecated": "1", + "EventCode": "0x90", + "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1", + "Deprecated": "1", + "EventCode": "0x90", + "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0", + "Deprecated": "1", + "EventCode": "0x90", + "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1", + "Deprecated": "1", + "EventCode": "0x90", + "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0", + "Deprecated": "1", + "EventCode": "0x90", + "EventName": "UNC_H_TxR_VERT_OCCUPANCY.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1", + "Deprecated": "1", + "EventCode": "0x90", + "EventName": "UNC_H_TxR_VERT_OCCUPANCY.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.IV", + "Deprecated": "1", + "EventCode": "0x90", + "EventName": "UNC_H_TxR_VERT_OCCUPANCY.IV_AG0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AD_AG0", + "Deprecated": "1", + "EventCode": "0x9A", + "EventName": "UNC_H_TxR_VERT_STARVED.AD_AG0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AD_AG1", + "Deprecated": "1", + "EventCode": "0x9A", + "EventName": "UNC_H_TxR_VERT_STARVED.AD_AG1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AK_AG0", + "Deprecated": "1", + "EventCode": "0x9A", + "EventName": "UNC_H_TxR_VERT_STARVED.AK_AG0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AK_AG1", + "Deprecated": "1", + "EventCode": "0x9A", + "EventName": "UNC_H_TxR_VERT_STARVED.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.BL_AG0", + "Deprecated": "1", + "EventCode": "0x9A", + "EventName": "UNC_H_TxR_VERT_STARVED.BL_AG0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.BL_AG1", + "Deprecated": "1", + "EventCode": "0x9A", + "EventName": "UNC_H_TxR_VERT_STARVED.BL_AG1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.IV", + "Deprecated": "1", + "EventCode": "0x9A", + "EventName": "UNC_H_TxR_VERT_STARVED.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", + "Deprecated": "1", + "EventCode": "0xA6", + "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", + "Deprecated": "1", + "EventCode": "0xA6", + "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", + "Deprecated": "1", + "EventCode": "0xA6", + "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", + "Deprecated": "1", + "EventCode": "0xA6", + "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", + "Deprecated": "1", + "EventCode": "0xA8", + "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", + "Deprecated": "1", + "EventCode": "0xA8", + "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", + "Deprecated": "1", + "EventCode": "0xA8", + "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", + "Deprecated": "1", + "EventCode": "0xA8", + "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", + "Deprecated": "1", + "EventCode": "0xAA", + "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", + "Deprecated": "1", + "EventCode": "0xAA", + "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", + "Deprecated": "1", + "EventCode": "0xAA", + "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", + "Deprecated": "1", + "EventCode": "0xAA", + "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_IV_IN_USE.DN", + "Deprecated": "1", + "EventCode": "0xAC", + "EventName": "UNC_H_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_IV_IN_USE.UP", + "Deprecated": "1", + "EventCode": "0xAC", + "EventName": "UNC_H_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WB_PUSH_MTOI.LLC", + "Deprecated": "1", + "EventCode": "0x56", + "EventName": "UNC_H_WB_PUSH_MTOI.LLC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WB_PUSH_MTOI.MEM", + "Deprecated": "1", + "EventCode": "0x56", + "EventName": "UNC_H_WB_PUSH_MTOI.MEM", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2", + "Deprecated": "1", + "EventCode": "0x5A", + "EventName": "UNC_H_WRITE_NO_CREDITS.EDC0_SMI2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3", + "Deprecated": "1", + "EventCode": "0x5A", + "EventName": "UNC_H_WRITE_NO_CREDITS.EDC1_SMI3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4", + "Deprecated": "1", + "EventCode": "0x5A", + "EventName": "UNC_H_WRITE_NO_CREDITS.EDC2_SMI4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5", + "Deprecated": "1", + "EventCode": "0x5A", + "EventName": "UNC_H_WRITE_NO_CREDITS.EDC3_SMI5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0", + "Deprecated": "1", + "EventCode": "0x5A", + "EventName": "UNC_H_WRITE_NO_CREDITS.MC0_SMI0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1", + "Deprecated": "1", + "EventCode": "0x5A", + "EventName": "UNC_H_WRITE_NO_CREDITS.MC1_SMI1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.ANY_RSPI_FWDFE", + "PerPkg": "1", + "UMask": "0xe4", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.ANY_RSPI_FWDM", + "PerPkg": "1", + "UMask": "0xf0", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.ANY_RSPS_FWDFE", + "PerPkg": "1", + "UMask": "0xe2", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.ANY_RSPS_FWDM", + "PerPkg": "1", + "UMask": "0xe8", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.ANY_RSP_HITFSE", + "PerPkg": "1", + "UMask": "0xe1", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.CORE_RSPI_FWDFE", + "PerPkg": "1", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.CORE_RSPI_FWDM", + "PerPkg": "1", + "UMask": "0x50", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.CORE_RSPS_FWDFE", + "PerPkg": "1", + "UMask": "0x42", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.CORE_RSPS_FWDM", + "PerPkg": "1", + "UMask": "0x48", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.CORE_RSP_HITFSE", + "PerPkg": "1", + "UMask": "0x41", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EVICT_RSPI_FWDFE", + "PerPkg": "1", + "UMask": "0x84", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EVICT_RSPI_FWDM", + "PerPkg": "1", + "UMask": "0x90", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EVICT_RSPS_FWDFE", + "PerPkg": "1", + "UMask": "0x82", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EVICT_RSPS_FWDM", + "PerPkg": "1", + "UMask": "0x88", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EVICT_RSP_HITFSE", + "PerPkg": "1", + "UMask": "0x81", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EXT_RSPI_FWDFE", + "PerPkg": "1", + "UMask": "0x24", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EXT_RSPI_FWDM", + "PerPkg": "1", + "UMask": "0x30", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EXT_RSPS_FWDFE", + "PerPkg": "1", + "UMask": "0x22", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EXT_RSPS_FWDM", + "PerPkg": "1", + "UMask": "0x28", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE", + "Deprecated": "1", + "EventCode": "0x32", + "EventName": "UNC_H_XSNP_RESP.EXT_RSP_HITFSE", + "PerPkg": "1", + "UMask": "0x21", + "Unit": "CHA" + } +] diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/skylakex/uncore-interconnect.json new file mode 100644 index 000000000000..26a5a20bf37a --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-interconnect.json @@ -0,0 +1,11248 @@ +[ + { + "BriefDescription": "Total Write Cache Occupancy; Any Source", + "EventCode": "0xF", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Total Write Cache Occupancy; Snoops", + "EventCode": "0xF", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Total IRP occupancy of inbound read and write requests.", + "EventCode": "0xF", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", + "PerPkg": "1", + "PublicDescription": "Total IRP occupancy of inbound read and write requests. This is effectively the sum of read occupancy and write occupancy.", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "IRP Clocks", + "EventCode": "0x1", + "EventName": "UNC_I_CLOCKTICKS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; CLFlush", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; CRd", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.CRD", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; DRd", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.DRD", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; PCIDCAHin5t", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; PCIRdCur", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.PCITOM", + "PerPkg": "1", + "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.RFO", + "PerPkg": "1", + "PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops; WbMtoI", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.WBMTOI", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherency related operations servied by the IRP", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "FAF RF full", + "EventCode": "0x17", + "EventName": "UNC_I_FAF_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.", + "EventCode": "0x18", + "EventName": "UNC_I_FAF_INSERTS", + "PerPkg": "1", + "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.", + "Unit": "IRP" + }, + { + "BriefDescription": "Occupancy of the IRP FAF queue.", + "EventCode": "0x19", + "EventName": "UNC_I_FAF_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.", + "Unit": "IRP" + }, + { + "BriefDescription": "FAF allocation -- sent to ADQ", + "EventCode": "0x16", + "EventName": "UNC_I_FAF_TRANSACTIONS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "All Inserts Inbound (p2p + faf + cset)", + "EventCode": "0x1E", + "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "All Inserts Outbound (BL, AK, Snoops)", + "EventCode": "0x1E", + "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.2ND_RD_INSERT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.2ND_WR_INSERT", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Fastpath Rejects", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.FAST_REJ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Fastpath Requests", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.FAST_REQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.FAST_XFER", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.PF_ACK_HINT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 0", + "EventCode": "0x1C", + "EventName": "UNC_I_MISC0.UNKNOWN", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Lost Forward", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.LOST_FWD", + "PerPkg": "1", + "PublicDescription": "Snoop pulled away ownership before a write was committed", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Received Invalid", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", + "PerPkg": "1", + "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Received Valid", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", + "PerPkg": "1", + "PublicDescription": "Secondary received a transfer that did have sufficient MESI state", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SLOW_E", + "PerPkg": "1", + "PublicDescription": "Secondary received a transfer that did have sufficient MESI state", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SLOW_I", + "PerPkg": "1", + "PublicDescription": "Snoop took cacheline ownership before write from data was committed.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SLOW_M", + "PerPkg": "1", + "PublicDescription": "Snoop took cacheline ownership before write from data was committed.", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line", + "EventCode": "0x1D", + "EventName": "UNC_I_MISC1.SLOW_S", + "PerPkg": "1", + "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Requests", + "EventCode": "0x14", + "EventName": "UNC_I_P2P_INSERTS", + "PerPkg": "1", + "PublicDescription": "P2P requests from the ITC", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Occupancy", + "EventCode": "0x15", + "EventName": "UNC_I_P2P_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "P2P B & S Queue Occupancy", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; P2P completions", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; match if local only", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.LOC", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; match if local and target matches", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; P2P Message", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.MSG", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; P2P reads", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.RD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; Match if remote only", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.REM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; match if remote and target matches", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions; P2P Writes", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.WR", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO", + "UMask": "0x7e", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache", + "UMask": "0x74", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache", + "UMask": "0x72", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache", + "UMask": "0x78", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that miss the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_MISS", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that miss the IIO cache", + "UMask": "0x71", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Hit E or S", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_ES", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Hit I", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_I", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Hit M", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_M", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; Miss", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.MISS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; SnpCode", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPCODE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; SnpData", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPDATA", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses; SnpInv", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPINV", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Atomic", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.ATOMIC", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Other", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.OTHER", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions.", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Read Prefetches", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.RD_PREF", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Reads", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.READS", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count; Writes", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.WRITES", + "PerPkg": "1", + "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound write (fast path) requests received by the IRP.", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "PerPkg": "1", + "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "AK Egress Allocations", + "EventCode": "0xB", + "EventName": "UNC_I_TxC_AK_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL DRS Egress Cycles Full", + "EventCode": "0x5", + "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL DRS Egress Inserts", + "EventCode": "0x2", + "EventName": "UNC_I_TxC_BL_DRS_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL DRS Egress Occupancy", + "EventCode": "0x8", + "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCB Egress Cycles Full", + "EventCode": "0x6", + "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCB Egress Inserts", + "EventCode": "0x3", + "EventName": "UNC_I_TxC_BL_NCB_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCB Egress Occupancy", + "EventCode": "0x9", + "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCS Egress Cycles Full", + "EventCode": "0x7", + "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCS Egress Inserts", + "EventCode": "0x4", + "EventName": "UNC_I_TxC_BL_NCS_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCS Egress Occupancy", + "EventCode": "0xA", + "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "No AD Egress Credit Stalls", + "EventCode": "0x1A", + "EventName": "UNC_I_TxR2_AD_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.", + "Unit": "IRP" + }, + { + "BriefDescription": "No BL Egress Credit Stalls", + "EventCode": "0x1B", + "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "EventCode": "0xD", + "EventName": "UNC_I_TxS_DATA_INSERTS_NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "EventCode": "0xE", + "EventName": "UNC_I_TxS_DATA_INSERTS_NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Request Queue Occupancy", + "EventCode": "0xC", + "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.", + "Unit": "IRP" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Traffic in which the M2M to iMC Bypass was not taken", + "EventCode": "0x22", + "EventName": "UNC_M2M_BYPASS_M2M_Egress.NOT_TAKEN", + "PerPkg": "1", + "PublicDescription": "Counts traffic in which the M2M (Mesh to Memory) to iMC (Memory Controller) bypass was not taken", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC Bypass; Taken", + "EventCode": "0x22", + "EventName": "UNC_M2M_BYPASS_M2M_Egress.TAKEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC Bypass; Not Taken", + "EventCode": "0x21", + "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC Bypass; Taken", + "EventCode": "0x21", + "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles - at UCLK", + "EventName": "UNC_M2M_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Clockticks", + "EventCode": "0xC0", + "EventName": "UNC_M2M_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled", + "EventCode": "0x24", + "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", + "PerPkg": "1", + "PublicDescription": "Counts cycles when direct to core mode (which bypasses the CHA) was disabled", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages sent direct to core (bypassing the CHA)", + "EventCode": "0x23", + "EventName": "UNC_M2M_DIRECT2CORE_TAKEN", + "PerPkg": "1", + "PublicDescription": "Counts when messages were sent direct to core (bypassing the CHA)", + "Unit": "M2M" + }, + { + "BriefDescription": "Number of reads in which direct to core transaction were overridden", + "EventCode": "0x25", + "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", + "PerPkg": "1", + "PublicDescription": "Counts reads in which direct to core transactions (which would have bypassed the CHA) were overridden", + "Unit": "M2M" + }, + { + "BriefDescription": "Number of reads in which direct to Intel(R) UPI transactions were overridden", + "EventCode": "0x28", + "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS", + "PerPkg": "1", + "PublicDescription": "Counts reads in which direct to Intel(R) Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overridden", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles when direct to Intel(R) UPI was disabled", + "EventCode": "0x27", + "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE", + "PerPkg": "1", + "PublicDescription": "Counts cycles when the ability to send messages direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA) was disabled", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages sent direct to the Intel(R) UPI", + "EventCode": "0x26", + "EventName": "UNC_M2M_DIRECT2UPI_TAKEN", + "PerPkg": "1", + "PublicDescription": "Counts when messages were sent direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA)", + "Unit": "M2M" + }, + { + "BriefDescription": "Number of reads that a message sent direct2 Intel(R) UPI was overridden", + "EventCode": "0x29", + "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE", + "PerPkg": "1", + "PublicDescription": "Counts when a read message that was sent direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA) was overridden", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On NonDirty Line in A State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On NonDirty Line in I State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On NonDirty Line in L State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On NonDirty Line in S State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On Dirty Line in A State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On Dirty Line in I State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On Dirty Line in L State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Hit; On Dirty Line in S State", + "EventCode": "0x2A", + "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in Any State (A, I, S or unused)", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in the A (SnoopAll) state, indicating the cacheline is stored in another socket in any state, and we must snoop the other sockets to make sure we get the latest data. The data may be stored in any state in the local socket.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the I (Invalid) state indicating the cacheline is not stored in another socket, and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)", + "EventCode": "0x2D", + "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the S (Shared) state indicating the cacheline is either stored in another socket in the S(hared) state , and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On NonDirty Line in A State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On NonDirty Line in I State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On NonDirty Line in L State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On NonDirty Line in S State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On Dirty Line in A State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On Dirty Line in I State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On Dirty Line in L State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Directory Miss; On Dirty Line in S State", + "EventCode": "0x2B", + "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from A to I", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from A (SnoopAll) to I (Invalid)", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from A to S", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from A (SnoopAll) to S (Shared)", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from/to Any state", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory to a new state", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from I to A", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from I (Invalid) to A (SnoopAll)", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from I to S", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from I (Invalid) to S (Shared)", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from S to A", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from S (Shared) to A (SnoopAll)", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Multi-socket cacheline Directory update from S to I", + "EventCode": "0x2E", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from S (Shared) to I (Invalid)", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements; Down", + "EventCode": "0xAE", + "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements; Up", + "EventCode": "0xAE", + "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "FaST wire asserted; Horizontal", + "EventCode": "0xA5", + "EventName": "UNC_M2M_FAST_ASSERTED.HORZ", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "FaST wire asserted; Vertical", + "EventCode": "0xA5", + "EventName": "UNC_M2M_FAST_ASSERTED.VERT", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Left and Even", + "EventCode": "0xA7", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", + "EventCode": "0xA7", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Right and Even", + "EventCode": "0xA7", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", + "EventCode": "0xA7", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Even", + "EventCode": "0xA9", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", + "EventCode": "0xA9", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Right and Even", + "EventCode": "0xA9", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", + "EventCode": "0xA9", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Left and Even", + "EventCode": "0xAB", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", + "EventCode": "0xAB", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Right and Even", + "EventCode": "0xAB", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", + "EventCode": "0xAB", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal IV Ring in Use; Left", + "EventCode": "0xAD", + "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal IV Ring in Use; Right", + "EventCode": "0xAD", + "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Reads to iMC issued", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.ALL", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller).", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC; All, regardless of priority.", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.FROM_TRANSGRESS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC; Critical Priority", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.ISOCH", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Reads to iMC issued at Normal Priority (Non-Isochronous)", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.NORMAL", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller). It only counts normal priority non-isochronous reads.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Writes to iMC issued", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.ALL", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) issues writes to the iMC (Memory Controller).", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority.", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FROM_TRANSGRESS", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC; Full Line Non-ISOCH", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FULL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC; ISOCH Full Line", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority.", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.NI", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Partial Non-Isochronous writes to the iMC", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) issues partial writes to the iMC (Memory Controller). It only counts normal priority non-isochronous writes.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC; ISOCH Partial", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Number Packet Header Matches; MC Match", + "EventCode": "0x4C", + "EventName": "UNC_M2M_PKT_MATCH.MC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Number Packet Header Matches; Mesh Match", + "EventCode": "0x4C", + "EventName": "UNC_M2M_PKT_MATCH.MESH", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Full", + "EventCode": "0x53", + "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Not Empty", + "EventCode": "0x54", + "EventName": "UNC_M2M_PREFCAM_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch requests that got turn into a demand request", + "EventCode": "0x56", + "EventName": "UNC_M2M_PREFCAM_DEMAND_PROMOTIONS", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) promotes a outstanding request in the prefetch queue due to a subsequent demand read request that entered the M2M with the same address. Explanatory Side Note: The Prefetch queue is made of CAM (Content Addressable Memory)", + "Unit": "M2M" + }, + { + "BriefDescription": "Inserts into the Memory Controller Prefetch Queue", + "EventCode": "0x57", + "EventName": "UNC_M2M_PREFCAM_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts when the M2M (Mesh to Memory) receives a prefetch request and inserts it into its outstanding prefetch queue. Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Occupancy", + "EventCode": "0x55", + "EventName": "UNC_M2M_PREFCAM_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD", + "EventCode": "0xA1", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK", + "EventCode": "0xA1", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL", + "EventCode": "0xA1", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV", + "EventCode": "0xA1", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; AD", + "EventCode": "0xA0", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core", + "EventCode": "0xA0", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core", + "EventCode": "0xA0", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.", + "EventCode": "0xA0", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; AD", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; AK", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; BL", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; IV", + "EventCode": "0xA3", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; AD", + "EventCode": "0xA2", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core", + "EventCode": "0xA2", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core", + "EventCode": "0xA2", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.", + "EventCode": "0xA2", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Source Throttle", + "EventCode": "0xA4", + "EventName": "UNC_M2M_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0", + "Deprecated": "1", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1", + "Deprecated": "1", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2", + "Deprecated": "1", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 0", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 1", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 2", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 0", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 1", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 2", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Full", + "EventCode": "0x4", + "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Not Empty", + "EventCode": "0x3", + "EventName": "UNC_M2M_RxC_AD_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Queue Inserts", + "EventCode": "0x1", + "EventName": "UNC_M2M_RxC_AD_INSERTS", + "PerPkg": "1", + "PublicDescription": "Counts when the a new entry is Received(RxC) and then added to the AD (Address Ring) Ingress Queue from the CMS (Common Mesh Stop). This is generally used for reads, and", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Occupancy", + "EventCode": "0x2", + "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Full", + "EventCode": "0x8", + "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Not Empty", + "EventCode": "0x7", + "EventName": "UNC_M2M_RxC_BL_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Allocations", + "EventCode": "0x5", + "EventName": "UNC_M2M_RxC_BL_INSERTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Occupancy", + "EventCode": "0x6", + "EventName": "UNC_M2M_RxC_BL_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "EventCode": "0xB4", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "EventCode": "0xB4", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "EventCode": "0xB4", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "EventCode": "0xB4", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AD - Credit", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass; BL - Credit", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_M2M_RxR_BYPASS.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; AK - Bounce", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; IFV - Credit", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation; IV - Bounce", + "EventCode": "0xB3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AD - Credit", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; BL - Credit", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_M2M_RxR_INSERTS.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Number AD Ingress Credits", + "EventCode": "0x41", + "EventName": "UNC_M2M_TGR_AD_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number BL Ingress Credits", + "EventCode": "0x42", + "EventName": "UNC_M2M_TGR_BL_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Full; Channel 0", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Full; Channel 1", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Full; Channel 2", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Not Empty; Channel 0", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Not Empty; Channel 1", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Not Empty; Channel 2", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Inserts; Channel 0", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Inserts; Channel 1", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Inserts; Channel 2", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Occupancy; Channel 0", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Occupancy; Channel 1", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Occupancy; Channel 2", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Pending Occupancy", + "EventCode": "0x48", + "EventName": "UNC_M2M_TRACKER_PENDING_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Credit Acquired", + "EventCode": "0xD", + "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Credits Occupancy", + "EventCode": "0xE", + "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Full", + "EventCode": "0xC", + "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Not Empty", + "EventCode": "0xB", + "EventName": "UNC_M2M_TxC_AD_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Allocations", + "EventCode": "0x9", + "EventName": "UNC_M2M_TxC_AD_INSERTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No AD Egress (to CMS) Credits", + "EventCode": "0xF", + "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits", + "EventCode": "0x10", + "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Occupancy", + "EventCode": "0xA", + "EventName": "UNC_M2M_TxC_AD_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound Ring Transactions on AK; CRD Transactions to Cbo", + "EventCode": "0x39", + "EventName": "UNC_M2M_TxC_AK.CRD_CBO", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound Ring Transactions on AK; NDR Transactions", + "EventCode": "0x39", + "EventName": "UNC_M2M_TxC_AK.NDR", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side", + "EventCode": "0x1D", + "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side", + "EventCode": "0x1D", + "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side", + "EventCode": "0x1E", + "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side", + "EventCode": "0x1E", + "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; All", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Near Side", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Far Side", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1", + "PerPkg": "1", + "UMask": "0x88", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1", + "PerPkg": "1", + "UMask": "0xa0", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1", + "PerPkg": "1", + "UMask": "0x90", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty; All", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Near Side", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Far Side", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty; Read Credit Request", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty; Write Compare Request", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty; Write Credit Request", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; All", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Near Side", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Far Side", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; Prefetch Read Cam Hit", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; Read Credit Request", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; Write Compare Request", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations; Write Credit Request", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side", + "EventCode": "0x1F", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side", + "EventCode": "0x1F", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side", + "EventCode": "0x20", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side", + "EventCode": "0x20", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy; All", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Near Side", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Far Side", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy; Read Credit Request", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy; Write Compare Request", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy; Write Credit Request", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Sideband", + "EventCode": "0x6B", + "EventName": "UNC_M2M_TxC_AK_SIDEBAND.RD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Sideband", + "EventCode": "0x6B", + "EventName": "UNC_M2M_TxC_AK_SIDEBAND.WR", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_CACHE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_CORE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_UPI", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side", + "EventCode": "0x19", + "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side", + "EventCode": "0x19", + "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side", + "EventCode": "0x1A", + "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side", + "EventCode": "0x1A", + "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Full; All", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Near Side", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Far Side", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Not Empty; All", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Near Side", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Far Side", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Allocations; All", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Near Side", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Far Side", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side", + "EventCode": "0x1B", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side", + "EventCode": "0x1B", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side", + "EventCode": "0x1C", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side", + "EventCode": "0x1C", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Occupancy; All", + "EventCode": "0x16", + "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Near Side", + "EventCode": "0x16", + "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Far Side", + "EventCode": "0x16", + "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_HORZ_NACK.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used; IV", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.IV", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.IV", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; IV", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_INSERTS.IV", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; IV", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK.IV", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; IV", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.IV", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Down and Even", + "EventCode": "0xA6", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Down and Odd", + "EventCode": "0xA6", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Up and Even", + "EventCode": "0xA6", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Up and Odd", + "EventCode": "0xA6", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Down and Even", + "EventCode": "0xA8", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Down and Odd", + "EventCode": "0xA8", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Up and Even", + "EventCode": "0xA8", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Up and Odd", + "EventCode": "0xA8", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Down and Even", + "EventCode": "0xAA", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Down and Odd", + "EventCode": "0xAA", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Up and Even", + "EventCode": "0xAA", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Up and Odd", + "EventCode": "0xAA", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical IV Ring in Use; Down", + "EventCode": "0xAC", + "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical IV Ring in Use; Up", + "EventCode": "0xAC", + "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0", + "Deprecated": "1", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1", + "Deprecated": "1", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2", + "Deprecated": "1", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 0", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 1", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 2", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Full; Channel 0", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Full; Channel 1", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Full; Channel 2", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty; Channel 0", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty; Channel 1", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty; Channel 2", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts; Channel 0", + "EventCode": "0x61", + "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts; Channel 1", + "EventCode": "0x61", + "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts; Channel 2", + "EventCode": "0x61", + "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy; Channel 0", + "EventCode": "0x60", + "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy; Channel 1", + "EventCode": "0x60", + "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy; Channel 2", + "EventCode": "0x60", + "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5", + "EventCode": "0x80", + "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5", + "EventCode": "0x82", + "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5", + "EventCode": "0x88", + "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5", + "EventCode": "0x8A", + "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5", + "EventCode": "0x84", + "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5", + "EventCode": "0x86", + "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5", + "EventCode": "0x8E", + "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5", + "EventCode": "0x8C", + "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty; Requests", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty; Snoops", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty; VNA Messages", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CBox AD Credits Empty; Writebacks", + "EventCode": "0x22", + "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB", + "PerPkg": "1", + "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of uclks in domain", + "EventCode": "0x1", + "EventName": "UNC_M3UPI_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Clockticks", + "EventCode": "0xC0", + "EventName": "UNC_M3UPI_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "D2C Sent", + "EventCode": "0x2B", + "EventName": "UNC_M3UPI_D2C_SENT", + "PerPkg": "1", + "PublicDescription": "Count cases BL sends direct to core", + "Unit": "M3UPI" + }, + { + "BriefDescription": "D2U Sent", + "EventCode": "0x2A", + "EventName": "UNC_M3UPI_D2U_SENT", + "PerPkg": "1", + "PublicDescription": "Cases where SMI3 sends D2U command", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements; Down", + "EventCode": "0xAE", + "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements; Up", + "EventCode": "0xAE", + "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "FaST wire asserted; Horizontal", + "EventCode": "0xA5", + "EventName": "UNC_M3UPI_FAST_ASSERTED.HORZ", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "FaST wire asserted; Vertical", + "EventCode": "0xA5", + "EventName": "UNC_M3UPI_FAST_ASSERTED.VERT", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Left and Even", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Right and Even", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", + "EventCode": "0xA7", + "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Even", + "EventCode": "0xA9", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", + "EventCode": "0xA9", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Right and Even", + "EventCode": "0xA9", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", + "EventCode": "0xA9", + "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Left and Even", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Right and Even", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", + "EventCode": "0xAB", + "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal IV Ring in Use; Left", + "EventCode": "0xAD", + "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Horizontal IV Ring in Use; Right", + "EventCode": "0xAD", + "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO0_IIO1_NCB", + "PerPkg": "1", + "PublicDescription": "No vn0 and vna credits available to send to M2", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; IIO2", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB", + "PerPkg": "1", + "PublicDescription": "No vn0 and vna credits available to send to M2", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; IIO3", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB", + "PerPkg": "1", + "PublicDescription": "No vn0 and vna credits available to send to M2", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; IIO4", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB", + "PerPkg": "1", + "PublicDescription": "No vn0 and vna credits available to send to M2", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; IIO5", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB", + "PerPkg": "1", + "PublicDescription": "No vn0 and vna credits available to send to M2", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; All IIO targets for NCS are in single mask. ORs them together", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS", + "PerPkg": "1", + "PublicDescription": "No vn0 and vna credits available to send to M2", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "M2 BL Credits Empty; Selected M2p BL NCS credits", + "EventCode": "0x23", + "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL", + "PerPkg": "1", + "PublicDescription": "No vn0 and vna credits available to send to M2", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received; AD - Slot 0", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0", + "PerPkg": "1", + "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received; AD - Slot 1", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1", + "PerPkg": "1", + "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received; AD - Slot 2", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2", + "PerPkg": "1", + "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received; AK - Slot 0", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0", + "PerPkg": "1", + "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received; AK - Slot 2", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2", + "PerPkg": "1", + "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Multi Slot Flit Received; BL - Slot 0", + "EventCode": "0x3E", + "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0", + "PerPkg": "1", + "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV", + "EventCode": "0xA1", + "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; AD", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.", + "EventCode": "0xA0", + "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; AD", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; AK", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; BL", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring; IV", + "EventCode": "0xA3", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; AD", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.", + "EventCode": "0xA2", + "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Source Throttle", + "EventCode": "0xA4", + "EventName": "UNC_M3UPI_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; REQ on AD", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "VN0 message requested but lost arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; RSP on AD", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "VN0 message requested but lost arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; SNP on AD", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "VN0 message requested but lost arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; NCB on BL", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "VN0 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; NCS on BL", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "VN0 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; RSP on BL", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "VN0 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN0; WB on BL", + "EventCode": "0x4B", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "VN0 message requested but lost arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; REQ on AD", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "VN1 message requested but lost arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; RSP on AD", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "VN1 message requested but lost arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; SNP on AD", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "VN1 message requested but lost arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; NCB on BL", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "VN1 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; NCS on BL", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "VN1 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; RSP on BL", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "VN1 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Lost Arb for VN1; WB on BL", + "EventCode": "0x4C", + "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "VN1 message requested but lost arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; AD, BL Parallel Win", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN", + "PerPkg": "1", + "PublicDescription": "AD and BL messages won arbitration concurrently / in parallel", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN0", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0", + "PerPkg": "1", + "PublicDescription": "Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN1", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1", + "PerPkg": "1", + "PublicDescription": "Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN0", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0", + "PerPkg": "1", + "PublicDescription": "Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN1", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1", + "PerPkg": "1", + "PublicDescription": "Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN0", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN0", + "PerPkg": "1", + "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win to vn0, delaying vn1 win, because vn0 offered parallel ad/bl", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN1", + "EventCode": "0x4D", + "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN1", + "PerPkg": "1", + "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win to vn1, delaying vn0 win, because vn1 offered parallel ad/bl", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; REQ on AD", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; RSP on AD", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; SNP on AD", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; NCB on BL", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; NCS on BL", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; RSP on BL", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN0; WB on BL", + "EventCode": "0x49", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; REQ on AD", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; RSP on AD", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; SNP on AD", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; NCB on BL", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; NCS on BL", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; RSP on BL", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Can't Arb for VN1; WB on BL", + "EventCode": "0x4A", + "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; REQ on AD", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; RSP on AD", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; SNP on AD", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; NCB on BL", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; NCS on BL", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; RSP on BL", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN0; WB on BL", + "EventCode": "0x47", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; REQ on AD", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; RSP on AD", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; SNP on AD", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; NCB on BL", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; NCS on BL", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; RSP on BL", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "No Credits to Arb for VN1; WB on BL", + "EventCode": "0x48", + "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on BL Arb", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB", + "PerPkg": "1", + "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while bl message is in arbitration", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on Idle", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE", + "PerPkg": "1", + "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while pipeline is idle", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 1", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT", + "PerPkg": "1", + "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 1 while merging with bl message in same flit", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 2", + "EventCode": "0x40", + "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT", + "PerPkg": "1", + "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 2 while merging with bl message in same flit", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; REQ on AD", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; RSP on AD", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; SNP on AD", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; NCB on BL", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; NCS on BL", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; RSP on BL", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message lost contest for flit; WB on BL", + "EventCode": "0x50", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; REQ on AD", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; RSP on AD", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; SNP on AD", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; NCB on BL", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; NCS on BL", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; RSP on BL", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message lost contest for flit; WB on BL", + "EventCode": "0x51", + "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events; Any In BGF FIFO", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO", + "PerPkg": "1", + "PublicDescription": "Indication that at least one packet (flit) is in the bgf (fifo only)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events; Any in BGF Path", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH", + "PerPkg": "1", + "PublicDescription": "Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Miscellaneous Credit Events; No D2K For Arb", + "EventCode": "0x60", + "EventName": "UNC_M3UPI_RxC_CRD_MISC.NO_D2K_FOR_ARB", + "PerPkg": "1", + "PublicDescription": "VN0 or VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy; D2K Credits", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD", + "PerPkg": "1", + "PublicDescription": "D2K completion fifo credit occupancy (credits in use), accumulated across all cycles", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy; Packets in BGF FIFO", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO", + "PerPkg": "1", + "PublicDescription": "Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy; Packets in BGF Path", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH", + "PerPkg": "1", + "PublicDescription": "Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO", + "PerPkg": "1", + "PublicDescription": "count of bl messages in pump-1-pending state, in completion fifo only", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL", + "PerPkg": "1", + "PublicDescription": "count of bl messages in pump-1-pending state, in marker table and in fifo", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy; Transmit Credits", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD", + "PerPkg": "1", + "PublicDescription": "Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Credit Occupancy; VNA In Use", + "EventCode": "0x61", + "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE", + "PerPkg": "1", + "PublicDescription": "Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL", + "EventCode": "0x43", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL", + "EventCode": "0x44", + "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent; All", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.ALL", + "PerPkg": "1", + "PublicDescription": "Data flit is ready for transmission but could not be sent", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent; No BGF Credits", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_BGF", + "PerPkg": "1", + "PublicDescription": "Data flit is ready for transmission but could not be sent", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Data Flit Not Sent; No TxQ Credits", + "EventCode": "0x57", + "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_TXQ", + "PerPkg": "1", + "PublicDescription": "Data flit is ready for transmission but could not be sent", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 0", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT", + "PerPkg": "1", + "PublicDescription": "generating bl data flit sequence; waiting for data pump 0", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT", + "PerPkg": "1", + "PublicDescription": "pump-1-pending logic is at capacity (pending table plus completion fifo at limit)", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY", + "PerPkg": "1", + "PublicDescription": "pump-1-pending logic is tracking at least one message", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL", + "PerPkg": "1", + "PublicDescription": "pump-1-pending completion fifo is full", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0", + "PerPkg": "1", + "PublicDescription": "pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO", + "PerPkg": "1", + "PublicDescription": "a bl message finished but is in limbo and moved to pump-1-pending logic", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 1", + "EventCode": "0x59", + "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT", + "PerPkg": "1", + "PublicDescription": "generating bl data flit sequence; waiting for data pump 1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC", + "EventCode": "0x5A", + "EventName": "UNC_M3UPI_RxC_FLITS_MISC", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit; One Message", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG", + "PerPkg": "1", + "PublicDescription": "One message in flit; VNA or non-VNA flit", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit; One Message in non-VNA", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG_VNX", + "PerPkg": "1", + "PublicDescription": "One message in flit; non-VNA flit", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit; Two Messages", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.2_MSGS", + "PerPkg": "1", + "PublicDescription": "Two messages in flit; VNA flit", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit; Three Messages", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.3_MSGS", + "PerPkg": "1", + "PublicDescription": "Three messages in flit; VNA flit", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_2", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Sent Header Flit", + "EventCode": "0x56", + "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_3", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; All", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Needs Data Flit", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA", + "PerPkg": "1", + "PublicDescription": "BL message requires data flit sequence", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 0", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT", + "PerPkg": "1", + "PublicDescription": "Waiting for header pump 0", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ", + "PerPkg": "1", + "PublicDescription": "Header pump 1 is not required for flit", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Bubble", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE", + "PerPkg": "1", + "PublicDescription": "Header pump 1 is not required for flit but flit transmission delayed", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Not Avail", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL", + "PerPkg": "1", + "PublicDescription": "Header pump 1 is not required for flit and not available", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 1", + "EventCode": "0x58", + "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT", + "PerPkg": "1", + "PublicDescription": "Waiting for header pump 1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Accumulate", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM", + "PerPkg": "1", + "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Accumulate Ready", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ", + "PerPkg": "1", + "PublicDescription": "Events related to Header Flit Generation - Set 1; header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Accumulate Wasted", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED", + "PerPkg": "1", + "PublicDescription": "Events related to Header Flit Generation - Set 1; Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Blocked", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED", + "PerPkg": "1", + "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Message", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG", + "PerPkg": "1", + "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting is in run-ahead to start new flit, and message is actually slotted into new flit", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Parallel Ok", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR", + "PerPkg": "1", + "PublicDescription": "Events related to Header Flit Generation - Set 1; New header flit construction may proceed in parallel with data flit sequence", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Parallel Flit Finished", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_FLIT", + "PerPkg": "1", + "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit finished assembly in parallel with data flit sequence", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 1; Parallel Message", + "EventCode": "0x53", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_MSG", + "PerPkg": "1", + "PublicDescription": "Events related to Header Flit Generation - Set 1; Message is slotted into header flit in parallel with data flit sequence", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL", + "PerPkg": "1", + "PublicDescription": "Events related to Header Flit Generation - Set 2; Rate-matching stall injected", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall - No Message", + "EventCode": "0x54", + "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG", + "PerPkg": "1", + "PublicDescription": "Events related to Header Flit Generation - Set 2; Rate matching stall injected, but no additional message slotted during stall cycle", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; All", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ALL", + "PerPkg": "1", + "PublicDescription": "header flit is ready for transmission but could not be sent", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; No BGF Credits", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_CRD", + "PerPkg": "1", + "PublicDescription": "header flit is ready for transmission but could not be sent; No BGF credits available", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; No BGF Credits + No Extra Message Slotted", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_NO_MSG", + "PerPkg": "1", + "PublicDescription": "header flit is ready for transmission but could not be sent; No BGF credits available; no additional message slotted into flit", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; No TxQ Credits", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_CRD", + "PerPkg": "1", + "PublicDescription": "header flit is ready for transmission but could not be sent; No TxQ credits available", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; No TxQ Credits + No Extra Message Slotted", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_NO_MSG", + "PerPkg": "1", + "PublicDescription": "header flit is ready for transmission but could not be sent; No TxQ credits available; no additional message slotted into flit", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; Sent - One Slot Taken", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ONE_TAKEN", + "PerPkg": "1", + "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with only one slot taken (two slots free)", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; Sent - Three Slots Taken", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.THREE_TAKEN", + "PerPkg": "1", + "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with three slots taken (no slots free)", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Header Not Sent; Sent - Two Slots Taken", + "EventCode": "0x55", + "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.TWO_TAKEN", + "PerPkg": "1", + "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with only two slots taken (one slots free)", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Can't Slot AD", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD", + "PerPkg": "1", + "PublicDescription": "some AD message could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1})", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Can't Slot BL", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL", + "PerPkg": "1", + "PublicDescription": "some BL message could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1})", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Parallel AD Lost", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_AD_LOST", + "PerPkg": "1", + "PublicDescription": "some AD message lost contest for slot 0 (logical OR of all AD events under INGR_SLOT_LOST_MC_VN{0,1})", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Parallel Attempt", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT", + "PerPkg": "1", + "PublicDescription": "ad and bl messages attempted to slot into the same flit in parallel", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Parallel BL Lost", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_BL_LOST", + "PerPkg": "1", + "PublicDescription": "some BL message lost contest for slot 0 (logical OR of all BL events under INGR_SLOT_LOST_MC_VN{0,1})", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; Parallel Success", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS", + "PerPkg": "1", + "PublicDescription": "ad and bl messages were actually slotted into the same flit in paralle", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; VN0", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.VN0", + "PerPkg": "1", + "PublicDescription": "vn0 message(s) that couldn't be slotted into last vn0 flit are held in slotting stage while processing vn1 flit", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Message Held; VN1", + "EventCode": "0x52", + "EventName": "UNC_M3UPI_RxC_HELD.VN1", + "PerPkg": "1", + "PublicDescription": "vn1 message(s) that couldn't be slotted into last vn1 flit are held in slotting stage while processing vn0 flit", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; REQ on AD", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on AD", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; SNP on AD", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCB on BL", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCS on BL", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on BL", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; WB on BL", + "EventCode": "0x41", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; REQ on AD", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on AD", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; SNP on AD", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCB on BL", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCS on BL", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on BL", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; WB on BL", + "EventCode": "0x42", + "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; REQ on AD", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on AD", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; SNP on AD", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCB on BL", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCS on BL", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on BL", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; WB on BL", + "EventCode": "0x45", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; REQ on AD", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on AD", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; SNP on AD", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCB on BL", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCS on BL", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on BL", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; WB on BL", + "EventCode": "0x46", + "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; REQ on AD", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; RSP on AD", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; SNP on AD", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; NCB on BL", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; NCS on BL", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; RSP on BL", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 message can't slot into flit; WB on BL", + "EventCode": "0x4E", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; REQ on AD", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; RSP on AD", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; SNP on AD", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; NCB on BL", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; NCS on BL", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Standard (NCS) messages on BL.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; RSP on BL", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 message can't slot into flit; WB on BL", + "EventCode": "0x4F", + "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB", + "PerPkg": "1", + "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "SMI3 Prefetch Messages; Lost Arbitration", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARB_LOST", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "SMI3 Prefetch Messages; Arrived", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARRIVED", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "SMI3 Prefetch Messages; Dropped - Old", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_OLD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "SMI3 Prefetch Messages; Dropped - Wrap", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_WRAP", + "PerPkg": "1", + "PublicDescription": "Dropped because it was overwritten by new message while prefetch queue was full", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "SMI3 Prefetch Messages; Slotted", + "EventCode": "0x62", + "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.SLOTTED", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits; Any In Use", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE", + "PerPkg": "1", + "PublicDescription": "At least one remote vna credit is in use", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits; Corrected", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED", + "PerPkg": "1", + "PublicDescription": "Number of remote vna credits corrected (local return) per cycle", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits; Level < 1", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1", + "PerPkg": "1", + "PublicDescription": "Remote vna credit level is less than 1 (i.e. no vna credits available)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits; Level < 4", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4", + "PerPkg": "1", + "PublicDescription": "Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits; Level < 5", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5", + "PerPkg": "1", + "PublicDescription": "Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Remote VNA Credits; Used", + "EventCode": "0x5B", + "EventName": "UNC_M3UPI_RxC_VNA_CRD.USED", + "PerPkg": "1", + "PublicDescription": "Number of remote vna credits consumed per cycle", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "EventCode": "0xB4", + "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AD - Credit", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass; BL - Credit", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", + "EventCode": "0xB2", + "EventName": "UNC_M3UPI_RxR_BYPASS.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the CMS Ingress", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; AK - Bounce", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; IFV - Credit", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Injection Starvation; IV - Bounce", + "EventCode": "0xB3", + "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AD - Credit", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations; BL - Credit", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", + "EventCode": "0xB1", + "EventName": "UNC_M3UPI_RxR_INSERTS.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", + "EventCode": "0xB0", + "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5", + "EventCode": "0xD0", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5", + "EventCode": "0xD2", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5", + "EventCode": "0xD4", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5", + "EventCode": "0xD6", + "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN0 REQ Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "AD arb but no win; arb request asserted but not won", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN0 RSP Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "AD arb but no win; arb request asserted but not won", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN0 SNP Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "AD arb but no win; arb request asserted but not won", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN0 WB Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB", + "PerPkg": "1", + "PublicDescription": "AD arb but no win; arb request asserted but not won", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN1 REQ Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "AD arb but no win; arb request asserted but not won", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN1 RSP Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "AD arb but no win; arb request asserted but not won", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN1 SNP Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "AD arb but no win; arb request asserted but not won", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for AD; VN1 WB Messages", + "EventCode": "0x30", + "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB", + "PerPkg": "1", + "PublicDescription": "AD arb but no win; arb request asserted but not won", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0", + "PerPkg": "1", + "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1", + "PerPkg": "1", + "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2", + "PerPkg": "1", + "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD FlowQ Bypass", + "EventCode": "0x2C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP", + "PerPkg": "1", + "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN0 REQ Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN0 RSP Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN0 SNP Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN0 WB Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN1 REQ Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN1 RSP Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN1 SNP Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Not Empty; VN1 WB Messages", + "EventCode": "0x27", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB", + "PerPkg": "1", + "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN0 REQ Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN0 RSP Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN0 SNP Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN0 WB Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN1 REQ Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN1 RSP Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Inserts; VN1 SNP Messages", + "EventCode": "0x2D", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN0 REQ Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN0 RSP Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN0 SNP Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN0 WB Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN1 REQ Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN1 RSP Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AD Flow Q Occupancy; VN1 SNP Messages", + "EventCode": "0x1C", + "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; CHA on VN0", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_CHA", + "PerPkg": "1", + "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to CHA", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN0", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_NON_IDLE", + "PerPkg": "1", + "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of non-idle cycles in issuing Vn0 Snpf", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN0", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI0", + "PerPkg": "1", + "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to peer UPI0", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN0", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI1", + "PerPkg": "1", + "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to peer UPI1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; CHA on VN1", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_CHA", + "PerPkg": "1", + "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to CHA", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN1", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_NON_IDLE", + "PerPkg": "1", + "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of non-idle cycles in issuing Vn1 Snpf", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN1", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI0", + "PerPkg": "1", + "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to peer UPI0", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN1", + "EventCode": "0x3C", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI1", + "PerPkg": "1", + "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to peer UPI1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Snoop Arbitration; FlowQ Won", + "EventCode": "0x3D", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_NONSNP", + "PerPkg": "1", + "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn0", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won", + "EventCode": "0x3D", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_VN2SNP", + "PerPkg": "1", + "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ Vn0 SnpF issued when SnpF pending on Vn1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Snoop Arbitration; FlowQ Won", + "EventCode": "0x3D", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_NONSNP", + "PerPkg": "1", + "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won", + "EventCode": "0x3D", + "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_VN0SNP", + "PerPkg": "1", + "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ Vn1 SnpF issued when SnpF pending on Vn0", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 REQ Messages", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 SNP Messages", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 WB Messages", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_WB", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 REQ Messages", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 SNP Messages", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 WB Messages", + "EventCode": "0x34", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_WB", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - New Message; VN0 REQ Messages", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - New Message; VN0 SNP Messages", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - New Message; VN0 WB Messages", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_WB", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - New Message; VN1 REQ Messages", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - New Message; VN1 SNP Messages", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - New Message; VN1 WB Messages", + "EventCode": "0x33", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_WB", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN0 REQ Messages", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN0 RSP Messages", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN0 SNP Messages", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN0 WB Messages", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_WB", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN1 REQ Messages", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN1 RSP Messages", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN1 SNP Messages", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD - No Credit; VN1 WB Messages", + "EventCode": "0x32", + "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_WB", + "PerPkg": "1", + "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AK Flow Q Inserts", + "EventCode": "0x2F", + "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "AK Flow Q Occupancy", + "EventCode": "0x1E", + "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY", + "PerPkg": "1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN0 NCB Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB", + "PerPkg": "1", + "PublicDescription": "BL arb but no win; arb request asserted but not won", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN0 NCS Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS", + "PerPkg": "1", + "PublicDescription": "BL arb but no win; arb request asserted but not won", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN0 RSP Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "BL arb but no win; arb request asserted but not won", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN0 WB Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB", + "PerPkg": "1", + "PublicDescription": "BL arb but no win; arb request asserted but not won", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN1 NCS Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB", + "PerPkg": "1", + "PublicDescription": "BL arb but no win; arb request asserted but not won", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN1 NCB Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS", + "PerPkg": "1", + "PublicDescription": "BL arb but no win; arb request asserted but not won", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN1 RSP Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "BL arb but no win; arb request asserted but not won", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Failed ARB for BL; VN1 WB Messages", + "EventCode": "0x35", + "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB", + "PerPkg": "1", + "PublicDescription": "BL arb but no win; arb request asserted but not won", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN0 REQ Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN0 RSP Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN0 SNP Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN0 WB Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN1 REQ Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN1 RSP Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN1 SNP Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Not Empty; VN1 WB Messages", + "EventCode": "0x28", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB", + "PerPkg": "1", + "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN0 RSP Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN0 WB Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN0 NCS Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN0 NCB Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN1 RSP Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN1 WB Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN1_NCB Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Inserts; VN1_NCS Messages", + "EventCode": "0x2E", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN0 NCB Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN0 NCS Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN0 RSP Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN0 WB Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN1_NCS Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN1_NCB Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN1 RSP Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "BL Flow Q Occupancy; VN1 WB Messages", + "EventCode": "0x1D", + "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB Messages", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCB", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for BL - New Message; VN0 NCS Messages", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCS", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB Messages", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_WB", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for BL - New Message; VN1 WB Messages", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCB", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for BL - New Message; VN1 NCB Messages", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCS", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for BL - New Message; VN1 RSP Messages", + "EventCode": "0x38", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_WB", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCB Messages", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCB", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCS Messages", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCS", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 RSP Messages", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 WB Messages", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_WB", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCS Messages", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCB", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCB Messages", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCS", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x80", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 RSP Messages", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 WB Messages", + "EventCode": "0x37", + "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_WB", + "PerPkg": "1", + "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", + "EventCode": "0x9D", + "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", + "EventCode": "0x9F", + "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce", + "EventCode": "0x96", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce", + "EventCode": "0x97", + "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", + "EventCode": "0x95", + "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", + "EventCode": "0x99", + "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", + "EventCode": "0x94", + "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_BNC", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK_BNC", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_BNC", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce", + "EventCode": "0x9B", + "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV_BNC", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical ADS Used; IV", + "EventCode": "0x9E", + "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV", + "PerPkg": "1", + "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", + "EventCode": "0x92", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.IV", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV", + "EventCode": "0x93", + "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.IV", + "PerPkg": "1", + "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Allocations; IV", + "EventCode": "0x91", + "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.IV", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs; IV", + "EventCode": "0x98", + "EventName": "UNC_M3UPI_TxR_VERT_NACK.IV", + "PerPkg": "1", + "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy; IV", + "EventCode": "0x90", + "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.IV", + "PerPkg": "1", + "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", + "EventCode": "0x9A", + "EventName": "UNC_M3UPI_TxR_VERT_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VN0 REQ Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPIs on the AD Ring", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VN0 RSP Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPIs on the AD Ring", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VN0 SNP Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPIs on the AD Ring", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VN1 REQ Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPIs on the AD Ring", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VN1 RSP Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPIs on the AD Ring", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VN1 SNP Messages", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPIs on the AD Ring", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 AD Credits Empty; VNA", + "EventCode": "0x20", + "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPIs on the AD Ring", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty; VN0 RSP Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty; VN0 REQ Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty; VN0 SNP Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty; VN1 RSP Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty; VN1 REQ Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty; VN1 SNP Messages", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x40", + "Unit": "M3UPI" + }, + { + "BriefDescription": "UPI0 BL Credits Empty; VNA", + "EventCode": "0x21", + "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA", + "PerPkg": "1", + "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Prefetches generated by the flow control queue of the M3UPI unit.", + "EventCode": "0x29", + "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN", + "PerPkg": "1", + "PublicDescription": "Count cases where flow control queue that sits between the Intel(R) Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller)", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Down and Even", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Down and Odd", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Up and Even", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AD Ring In Use; Up and Odd", + "EventCode": "0xA6", + "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Down and Even", + "EventCode": "0xA8", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Down and Odd", + "EventCode": "0xA8", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Up and Even", + "EventCode": "0xA8", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical AK Ring In Use; Up and Odd", + "EventCode": "0xA8", + "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Down and Even", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Down and Odd", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Up and Even", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical BL Ring in Use; Up and Odd", + "EventCode": "0xAA", + "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical IV Ring in Use; Down", + "EventCode": "0xAC", + "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "Vertical IV Ring in Use; Up", + "EventCode": "0xAC", + "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used; WB on BL", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used; NCB on BL", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used; REQ on AD", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used; RSP on AD", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used; SNP on AD", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 Credit Used; RSP on BL", + "EventCode": "0x5C", + "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB", + "PerPkg": "1", + "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits; WB on BL", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB", + "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN0 Credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits; NCB on BL", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS", + "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN0 Credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits; REQ on AD", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ", + "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN0 Credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits; RSP on AD", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP", + "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN0 Credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits; SNP on AD", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP", + "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN0 Credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN0 No Credits; RSP on BL", + "EventCode": "0x5E", + "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB", + "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN0 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used; WB on BL", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used; NCB on BL", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used; REQ on AD", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used; RSP on AD", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used; SNP on AD", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 Credit Used; RSP on BL", + "EventCode": "0x5D", + "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB", + "PerPkg": "1", + "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits; WB on BL", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB", + "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN1 Credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", + "UMask": "0x10", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits; NCB on BL", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS", + "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN1 Credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", + "UMask": "0x20", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits; REQ on AD", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ", + "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN1 Credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", + "UMask": "0x1", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits; RSP on AD", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP", + "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN1 Credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x4", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits; SNP on AD", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP", + "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN1 Credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", + "UMask": "0x2", + "Unit": "M3UPI" + }, + { + "BriefDescription": "VN1 No Credits; RSP on BL", + "EventCode": "0x5F", + "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB", + "PerPkg": "1", + "PublicDescription": "Number of Cycles there were no VN1 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", + "UMask": "0x8", + "Unit": "M3UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_TxC_BL.DRS_UPI", + "Deprecated": "1", + "EventCode": "0x40", + "EventName": "UNC_NoUnit_TxC_BL.DRS_UPI", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Clocks of the Intel(R) Ultra Path Interconnect (UPI)", + "EventCode": "0x1", + "EventName": "UNC_UPI_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts clockticks of the fixed frequency clock controlling the Intel(R) Ultra Path Interconnect (UPI). This clock runs at1/8th the 'GT/s' speed of the UPI link. For example, a 9.6GT/s link will have a fixed Frequency of 1.2 Ghz.", + "Unit": "UPI" + }, + { + "BriefDescription": "Data Response packets that go direct to core", + "EventCode": "0x12", + "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C", + "PerPkg": "1", + "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to core bypassing the CHA.", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_DIRECT_ATTEMPTS.D2U", + "Deprecated": "1", + "EventCode": "0x12", + "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "Data Response packets that go direct to Intel(R) UPI", + "EventCode": "0x12", + "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2U", + "PerPkg": "1", + "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to Intel(R) Ultra Path Interconnect (UPI) bypassing the CHA .", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "EventCode": "0x18", + "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles Intel(R) UPI is in L1 power mode (shutdown)", + "EventCode": "0x21", + "EventName": "UNC_UPI_L1_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts cycles when the Intel(R) Ultra Path Interconnect (UPI) is in L1 power mode. L1 is a mode that totally shuts down the UPI link. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdown.", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "EventCode": "0x14", + "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "EventCode": "0x16", + "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "EventCode": "0x15", + "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1", + "EventCode": "0x20", + "EventName": "UNC_UPI_PHY_INIT_CYCLES", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "L1 Req Nack", + "EventCode": "0x23", + "EventName": "UNC_UPI_POWER_L1_NACK", + "PerPkg": "1", + "PublicDescription": "Counts the number of times a link sends/receives a LinkReqNAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx originally requested the power change). A Tx LinkReqNAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).", + "Unit": "UPI" + }, + { + "BriefDescription": "L1 Req (same as L1 Ack).", + "EventCode": "0x22", + "EventName": "UNC_UPI_POWER_L1_REQ", + "PerPkg": "1", + "PublicDescription": "Counts the number of times a link sends/receives a LinkReqAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqAck refers to receiving an Ack (meaning this agent's Tx originally requested the power change). A Tx LinkReqAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "EventCode": "0x46", + "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles the Rx of the Intel(R) UPI is in L0p power mode", + "EventCode": "0x25", + "EventName": "UNC_UPI_RxL0P_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts cycles when the receive side (Rx) of the Intel(R) Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles in L0. Receive side.", + "EventCode": "0x24", + "EventName": "UNC_UPI_RxL0_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", + "PerPkg": "1", + "PublicDescription": "Match Message Class - NCB", + "UMask": "0xe", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC", + "PerPkg": "1", + "PublicDescription": "Match Message Class - NCB", + "UMask": "0x10e", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", + "PerPkg": "1", + "PublicDescription": "Match Message Class - NCS", + "UMask": "0xf", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC", + "PerPkg": "1", + "PublicDescription": "Match Message Class - NCS", + "UMask": "0x10f", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Request", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", + "PerPkg": "1", + "PublicDescription": "REQ Message Class", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Request Opcode", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC", + "PerPkg": "1", + "PublicDescription": "Match REQ Opcodes - Specified in Umask[7:4]", + "UMask": "0x108", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Response - Conflict", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT", + "PerPkg": "1", + "UMask": "0x1aa", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Response - Invalid", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI", + "PerPkg": "1", + "UMask": "0x12a", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", + "PerPkg": "1", + "PublicDescription": "Match Message Class -WB", + "UMask": "0xc", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC", + "PerPkg": "1", + "PublicDescription": "Match Message Class -WB", + "UMask": "0x10c", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA", + "PerPkg": "1", + "PublicDescription": "Match Message Class - RSP", + "UMask": "0xa", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", + "PerPkg": "1", + "PublicDescription": "Match Message Class - RSP", + "UMask": "0x10a", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Snoop", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", + "PerPkg": "1", + "PublicDescription": "SNP Message Class", + "UMask": "0x9", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Snoop Opcode", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC", + "PerPkg": "1", + "PublicDescription": "Match SNP Opcodes - Specified in Umask[7:4]", + "UMask": "0x109", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Writeback", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB", + "PerPkg": "1", + "PublicDescription": "Match Message Class -WB", + "UMask": "0xd", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port; Writeback", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC", + "PerPkg": "1", + "PublicDescription": "Match Message Class -WB", + "UMask": "0x10d", + "Unit": "UPI" + }, + { + "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", + "EventCode": "0x31", + "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", + "PerPkg": "1", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", + "EventCode": "0x31", + "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", + "PerPkg": "1", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer (Receive Queue) and passed directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", + "EventCode": "0x31", + "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", + "PerPkg": "1", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "CRC Errors Detected", + "EventCode": "0xB", + "EventName": "UNC_UPI_RxL_CRC_ERRORS", + "PerPkg": "1", + "PublicDescription": "Number of CRC errors detected in the UPI Agent. Each UPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the UPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).", + "Unit": "UPI" + }, + { + "BriefDescription": "LLR Requests Sent", + "EventCode": "0x8", + "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT", + "PerPkg": "1", + "PublicDescription": "Number of LLR Requests were transmitted. This should generally be <= the number of CRC errors detected. If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs.", + "Unit": "UPI" + }, + { + "BriefDescription": "VN0 Credit Consumed", + "EventCode": "0x39", + "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", + "Unit": "UPI" + }, + { + "BriefDescription": "VN1 Credit Consumed", + "EventCode": "0x3A", + "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", + "Unit": "UPI" + }, + { + "BriefDescription": "VNA Credit Consumed", + "EventCode": "0x38", + "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA", + "PerPkg": "1", + "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid data FLITs received from any slot", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", + "PerPkg": "1", + "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel(R) Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.", + "UMask": "0xf", + "Unit": "UPI" + }, + { + "BriefDescription": "Null FLITs received from any slot", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", + "PerPkg": "1", + "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel(R) Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.", + "UMask": "0x27", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received; Data", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.DATA", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received; Idle", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.IDLE", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).", + "UMask": "0x47", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received; LLCRD Not Empty", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.LLCRD", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received; LLCTRL", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.LLCTRL", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.", + "UMask": "0x40", + "Unit": "UPI" + }, + { + "BriefDescription": "Protocol header and credit FLITs received from any slot", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", + "PerPkg": "1", + "PublicDescription": "Counts protocol header and credit FLITs (80 bit FLow control unITs) received from any of the 3 UPI slots on this UPI unit.", + "UMask": "0x97", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.ALL_NULL", + "Deprecated": "1", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.NULL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received; Protocol Header", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.PROTHDR", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)", + "UMask": "0x80", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.PROTHDR", + "Deprecated": "1", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.PROT_HDR", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received; Slot 0", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.SLOT0", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 0 - Other mask bits determine types of headers to count.", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received; Slot 1", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.SLOT1", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 1 - Other mask bits determine types of headers to count.", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received; Slot 2", + "EventCode": "0x3", + "EventName": "UNC_UPI_RxL_FLITS.SLOT2", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 2 - Other mask bits determine types of headers to count.", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.NCB", + "PerPkg": "1", + "UMask": "0xc", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.NCS", + "PerPkg": "1", + "UMask": "0xd", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.REQ", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.RSP", + "PerPkg": "1", + "UMask": "0xa", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.SNP", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.WB", + "Deprecated": "1", + "EventCode": "0x5", + "EventName": "UNC_UPI_RxL_HDR_MATCH.WB", + "PerPkg": "1", + "UMask": "0xb", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Flit Buffer Allocations; Slot 0", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT0", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Flit Buffer Allocations; Slot 1", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT1", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Flit Buffer Allocations; Slot 2", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT2", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets; Slot 0", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets; Slot 1", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets; Slot 2", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "EventCode": "0x33", + "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "EventCode": "0x2A", + "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles in which the Tx of the Intel(R) Ultra Path Interconnect (UPI) is in L0p power mode", + "EventCode": "0x27", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Counts cycles when the transmit side (Tx) of the Intel(R) Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "EventCode": "0x28", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "EventCode": "0x29", + "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles in L0. Transmit side.", + "EventCode": "0x26", + "EventName": "UNC_UPI_TxL0_POWER_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", + "PerPkg": "1", + "PublicDescription": "Match Message Class - NCB", + "UMask": "0xe", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC", + "PerPkg": "1", + "PublicDescription": "Match Message Class - NCB", + "UMask": "0x10e", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", + "PerPkg": "1", + "PublicDescription": "Match Message Class - NCS", + "UMask": "0xf", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC", + "PerPkg": "1", + "PublicDescription": "Match Message Class - NCS", + "UMask": "0x10f", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Request", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", + "PerPkg": "1", + "PublicDescription": "REQ Message Class", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Request Opcode", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC", + "PerPkg": "1", + "PublicDescription": "Match REQ Opcodes - Specified in Umask[7:4]", + "UMask": "0x108", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Conflict", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT", + "PerPkg": "1", + "UMask": "0x1aa", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Invalid", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI", + "PerPkg": "1", + "UMask": "0x12a", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", + "PerPkg": "1", + "PublicDescription": "Match Message Class -WB", + "UMask": "0xc", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC", + "PerPkg": "1", + "PublicDescription": "Match Message Class -WB", + "UMask": "0x10c", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", + "PerPkg": "1", + "PublicDescription": "Match Message Class - RSP", + "UMask": "0xa", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", + "PerPkg": "1", + "PublicDescription": "Match Message Class - RSP", + "UMask": "0x10a", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", + "PerPkg": "1", + "PublicDescription": "SNP Message Class", + "UMask": "0x9", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop Opcode", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC", + "PerPkg": "1", + "PublicDescription": "Match SNP Opcodes - Specified in Umask[7:4]", + "UMask": "0x109", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB", + "PerPkg": "1", + "PublicDescription": "Match Message Class -WB", + "UMask": "0xd", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC", + "PerPkg": "1", + "PublicDescription": "Match Message Class -WB", + "UMask": "0x10d", + "Unit": "UPI" + }, + { + "BriefDescription": "FLITs that bypassed the TxL Buffer", + "EventCode": "0x41", + "EventName": "UNC_UPI_TxL_BYPASSED", + "PerPkg": "1", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel(R) Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link. However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR mode, increasing latency to transfer out to the link.", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid data FLITs transmitted via any slot", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", + "PerPkg": "1", + "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel(R) Ultra Path Interconnect (UPI) slots on this UPI unit.", + "UMask": "0xf", + "Unit": "UPI" + }, + { + "BriefDescription": "Null FLITs transmitted from any slot", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", + "PerPkg": "1", + "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel(R) Ulra Path Interconnect (UPI) slots on this UPI unit.", + "UMask": "0x27", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent; Data", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.DATA", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "Idle FLITs transmitted", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.IDLE", + "PerPkg": "1", + "PublicDescription": "Counts when the Intel Ultra Path Interconnect(UPI) transmits an idle FLIT(80 bit FLow control unITs). Every UPI cycle must be sending either data FLITs, protocol/credit FLITs or idle FLITs.", + "UMask": "0x47", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent; LLCRD Not Empty", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.LLCRD", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent; LLCTRL", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.LLCTRL", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.", + "UMask": "0x40", + "Unit": "UPI" + }, + { + "BriefDescription": "Protocol header and credit FLITs transmitted across any slot", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", + "PerPkg": "1", + "PublicDescription": "Counts protocol header and credit FLITs (80 bit FLow control unITs) transmitted across any of the 3 UPI (Ultra Path Interconnect) slots on this UPI unit.", + "UMask": "0x97", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.ALL_NULL", + "Deprecated": "1", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.NULL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent; Protocol Header", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.PROTHDR", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)", + "UMask": "0x80", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.PROTHDR", + "Deprecated": "1", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.PROT_HDR", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent; Slot 0", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.SLOT0", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 0 - Other mask bits determine types of headers to count.", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent; Slot 1", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.SLOT1", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 1 - Other mask bits determine types of headers to count.", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent; Slot 2", + "EventCode": "0x2", + "EventName": "UNC_UPI_TxL_FLITS.SLOT2", + "PerPkg": "1", + "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 2 - Other mask bits determine types of headers to count.", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.DATA_HDR", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.DUAL_SLOT_HDR", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.LOC", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.NCB", + "PerPkg": "1", + "UMask": "0xe", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.NCS", + "PerPkg": "1", + "UMask": "0xf", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.NON_DATA_HDR", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.REM", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.REQ", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_DATA", + "PerPkg": "1", + "UMask": "0xc", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_NODATA", + "PerPkg": "1", + "UMask": "0xa", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.SGL_SLOT_HDR", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.SNP", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "UPI" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.WB", + "Deprecated": "1", + "EventCode": "0x4", + "EventName": "UNC_UPI_TxL_HDR_MATCH.WB", + "PerPkg": "1", + "UMask": "0xc", + "Unit": "UPI" + }, + { + "BriefDescription": "Tx Flit Buffer Allocations", + "EventCode": "0x40", + "EventName": "UNC_UPI_TxL_INSERTS", + "PerPkg": "1", + "PublicDescription": "Number of allocations into the UPI Tx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", + "Unit": "UPI" + }, + { + "BriefDescription": "Tx Flit Buffer Occupancy", + "EventCode": "0x42", + "EventName": "UNC_UPI_TxL_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Accumulates the number of flits in the TxQ. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.", + "Unit": "UPI" + }, + { + "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "EventCode": "0x45", + "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "VNA Credits Pending Return - Occupancy", + "EventCode": "0x44", + "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.", + "Unit": "UPI" + }, + { + "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", + "EventCode": "0xff", + "EventName": "UNC_U_CLOCKTICKS", + "PerPkg": "1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.INT_PRIO", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received; IPI", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.; Inter Processor Interrupts", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received; MSI", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.; Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received; VLW", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", + "PerPkg": "1", + "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "IDI Lock/SplitLock Cycles", + "EventCode": "0x44", + "EventName": "UNC_U_LOCK_CYCLES", + "PerPkg": "1", + "PublicDescription": "Number of times an IDI Lock/SplitLock sequence was started", + "Unit": "UBOX" + }, + { + "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", + "EventCode": "0x45", + "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", + "PerPkg": "1", + "PublicDescription": "PHOLD cycles.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_RACU_DRNG.RDRAND", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.RDRAND", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_RACU_DRNG.RDSEED", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.RDSEED", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "RACU Request", + "EventCode": "0x46", + "EventName": "UNC_U_RACU_REQUESTS", + "PerPkg": "1", + "PublicDescription": "Number outstanding register requests within message channel tracker", + "Unit": "UBOX" + }, + { + "BriefDescription": "UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data", + "EventCode": "0x2", + "EventName": "UPI_DATA_BANDWIDTH_TX", + "PerPkg": "1", + "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel(R) Ultra Path Interconnect (UPI) slots on this UPI unit.", + "ScaleUnit": "7.11E-06Bytes", + "UMask": "0xf", + "Unit": "UPI" + } +] diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-io.json b/tools/perf/pmu-events/arch/x86/skylakex/uncore-io.json new file mode 100644 index 000000000000..2a3a709018bb --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-io.json @@ -0,0 +1,4250 @@ +[ + { + "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0", + "EventCode": "0x83", + "EventName": "LLC_MISSES.PCIE_READ", + "FCMask": "0x07", + "Filter": "ch_mask=0x1f", + "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "MetricName": "LLC_MISSES.PCIE_READ", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "ScaleUnit": "4Bytes", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0", + "EventCode": "0x83", + "EventName": "LLC_MISSES.PCIE_WRITE", + "FCMask": "0x07", + "Filter": "ch_mask=0x1f", + "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "MetricName": "LLC_MISSES.PCIE_WRITE", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "ScaleUnit": "4Bytes", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Clockticks of the IIO Traffic Controller", + "EventCode": "0x1", + "EventName": "UNC_IIO_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Counts clockticks of the 1GHz trafiic controller clock in the IIO unit.", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x0f", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts; Port 0", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x01", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts; Port 1", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts; Port 2", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts; Port 3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0xf", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", + "FCMask": "0x04", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part2", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made to IIO Part0 by the CPU", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made to IIO Part1 by the CPU", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made to IIO Part2 by the CPU", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of 4 bytes made to IIO Part3 by the CPU", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth reading at IIO, part 0", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth reading at IIO, part 1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth reading at IIO, part 2", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth reading at IIO, part 3", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card reading from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card reading from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO, part 0", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO, part 1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO, part 2", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO, part 3", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card writing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card writing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Num Link Correctable Errors", + "EventCode": "0xF", + "EventName": "UNC_IIO_LINK_NUM_CORR_ERR", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Num Link Retries", + "EventCode": "0xE", + "EventName": "UNC_IIO_LINK_NUM_RETRIES", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number packets that passed the Mask/Match Filter", + "EventCode": "0x21", + "EventName": "UNC_IIO_MASK_MATCH", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0", + "PerPkg": "1", + "PublicDescription": "Asserted if all bits specified by mask match", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and PCIE bus", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1", + "PerPkg": "1", + "PublicDescription": "Asserted if all bits specified by mask match", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and !(PCIE bus)", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1", + "PerPkg": "1", + "PublicDescription": "Asserted if all bits specified by mask match", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus; PCIE bus", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1", + "PerPkg": "1", + "PublicDescription": "Asserted if all bits specified by mask match", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1", + "PerPkg": "1", + "PublicDescription": "Asserted if all bits specified by mask match", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus", + "EventCode": "0x2", + "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1", + "PerPkg": "1", + "PublicDescription": "Asserted if all bits specified by mask match", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0", + "PerPkg": "1", + "PublicDescription": "Asserted if any bits specified by mask match", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and PCIE bus", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1", + "PerPkg": "1", + "PublicDescription": "Asserted if any bits specified by mask match", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and !(PCIE bus)", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1", + "PerPkg": "1", + "PublicDescription": "Asserted if any bits specified by mask match", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus; PCIE bus", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1", + "PerPkg": "1", + "PublicDescription": "Asserted if any bits specified by mask match", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1", + "PerPkg": "1", + "PublicDescription": "Asserted if any bits specified by mask match", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) and !(PCIE bus)", + "EventCode": "0x3", + "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1", + "PerPkg": "1", + "PublicDescription": "Asserted if any bits specified by mask match", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Counting disabled", + "EventName": "UNC_IIO_NOTHING", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1", + "Deprecated": "1", + "EventCode": "0x83", + "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1", + "Deprecated": "1", + "EventCode": "0xC0", + "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Symbol Times on Link", + "EventCode": "0x82", + "EventName": "UNC_IIO_SYMBOL_TIMES", + "PerPkg": "1", + "PublicDescription": "Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.MSG.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART2", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART3", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x8", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD0", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1", + "Deprecated": "1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD1", + "FCMask": "0x7", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part0", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part1", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part2", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part0 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part1 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part1 to the MMIO space of an IIO target.In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; context cache miss", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.CTXT_MISS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; L1 miss", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.L1_MISS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; L2 miss", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.L2_MISS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; L3 miss", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.L3_MISS", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; Vtd hit", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.L4_PAGE_HIT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; TLB miss", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.TLB1_MISS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; TLB is full", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.TLB_FULL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Access; TLB miss", + "EventCode": "0x41", + "EventName": "UNC_IIO_VTD_ACCESS.TLB_MISS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "VTd Occupancy", + "EventCode": "0x40", + "EventName": "UNC_IIO_VTD_OCCUPANCY", + "PerPkg": "1", + "Unit": "IIO" + } +] diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json b/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json index e0840c24e7aa..6f8ff2262ce7 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json @@ -1952,7 +1952,7 @@ "EventCode": "0x81", "EventName": "UNC_M_WPQ_OCCUPANCY", "PerPkg": "1", - "PublicDescription": "Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller). They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. Is there a filter of sorts???", + "PublicDescription": "Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller). They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. Is there a filter of sorts?", "Unit": "iMC" }, { diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json deleted file mode 100644 index 92a4bdcd4bd7..000000000000 --- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json +++ /dev/null @@ -1,26143 +0,0 @@ -[ - { - "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0", - "EventCode": "0x83", - "EventName": "LLC_MISSES.PCIE_READ", - "FCMask": "0x07", - "Filter": "ch_mask=0x1f", - "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "MetricName": "LLC_MISSES.PCIE_READ", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "ScaleUnit": "4Bytes", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0", - "EventCode": "0x83", - "EventName": "LLC_MISSES.PCIE_WRITE", - "FCMask": "0x07", - "Filter": "ch_mask=0x1f", - "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "MetricName": "LLC_MISSES.PCIE_WRITE", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "ScaleUnit": "4Bytes", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA to iMC Bypass; Intermediate bypass Taken", - "EventCode": "0x57", - "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the intermediate bypass.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA to iMC Bypass; Not Taken", - "EventCode": "0x57", - "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA to iMC Bypass; Taken", - "EventCode": "0x57", - "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the full bypass.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Clockticks of the uncore caching & home agent (CHA)", - "EventName": "UNC_CHA_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Counts clockticks of the clock controlling the uncore caching and home agent (CHA).", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Clockticks", - "EventCode": "0xC0", - "EventName": "UNC_CHA_CMS_CLOCKTICKS", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "Core PMA Events; C1 State", - "EventCode": "0x17", - "EventName": "UNC_CHA_CORE_PMA.C1_STATE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Core PMA Events; C1 Transition", - "EventCode": "0x17", - "EventName": "UNC_CHA_CORE_PMA.C1_TRANSITION", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Core PMA Events; C6 State", - "EventCode": "0x17", - "EventName": "UNC_CHA_CORE_PMA.C6_STATE", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Core PMA Events; C6 Transition", - "EventCode": "0x17", - "EventName": "UNC_CHA_CORE_PMA.C6_TRANSITION", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Core PMA Events; GV", - "EventCode": "0x17", - "EventName": "UNC_CHA_CORE_PMA.GV", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Any Cycle with Multiple Snoops", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE", - "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0xe2", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Any Single Snoop", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.ANY_ONE", - "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0xe1", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Any Snoop to Remote Node", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.ANY_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0xe4", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Multiple Core Requests", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE", - "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x42", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Single Core Requests", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.CORE_ONE", - "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x41", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Core Request to Remote Node", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.CORE_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Multiple Eviction", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE", - "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x82", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Single Eviction", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE", - "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x81", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Eviction to Remote Node", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EVICT_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x84", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Multiple External Snoops", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE", - "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x22", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; Single External Snoops", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EXT_ONE", - "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued; External Snoop to Remote Node", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EXT_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "Counter 0 Occupancy", - "EventCode": "0x1F", - "EventName": "UNC_CHA_COUNTER0_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.", - "Unit": "CHA" - }, - { - "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Not Needed", - "EventCode": "0x53", - "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP", - "PerPkg": "1", - "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Multi-socket cacheline Directory state lookups; Snoop Needed", - "EventCode": "0x53", - "EventName": "UNC_CHA_DIR_LOOKUP.SNP", - "PerPkg": "1", - "PublicDescription": "Counts transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from the HA pipe", - "EventCode": "0x54", - "EventName": "UNC_CHA_DIR_UPDATE.HA", - "PerPkg": "1", - "PublicDescription": "Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Multi-socket cacheline Directory state updates; Directory Updated memory write from TOR pipe", - "EventCode": "0x54", - "EventName": "UNC_CHA_DIR_UPDATE.TOR", - "PerPkg": "1", - "PublicDescription": "Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements; Down", - "EventCode": "0xAE", - "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", - "PerPkg": "1", - "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements; Up", - "EventCode": "0xAE", - "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", - "PerPkg": "1", - "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "FaST wire asserted; Horizontal", - "EventCode": "0xA5", - "EventName": "UNC_CHA_FAST_ASSERTED.HORZ", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "FaST wire asserted; Vertical", - "EventCode": "0xA5", - "EventName": "UNC_CHA_FAST_ASSERTED.VERT", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Read request from a remote socket which hit in the HitMe Cache to a line In the E state", - "EventCode": "0x5F", - "EventName": "UNC_CHA_HITME_HIT.EX_RDS", - "PerPkg": "1", - "PublicDescription": "Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state. This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*)", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of Hits in HitMe Cache; Shared hit and op is RdInvOwn, RdInv, Inv*", - "EventCode": "0x5F", - "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoE", - "EventCode": "0x5F", - "EventName": "UNC_CHA_HITME_HIT.WBMTOE", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of Hits in HitMe Cache; op is WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", - "EventCode": "0x5F", - "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*", - "EventCode": "0x5E", - "EventName": "UNC_CHA_HITME_LOOKUP.READ", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of times HitMe Cache is accessed; op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", - "EventCode": "0x5E", - "EventName": "UNC_CHA_HITME_LOOKUP.WRITE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of Misses in HitMe Cache; No SF/LLC HitS/F and op is RdInvOwn", - "EventCode": "0x60", - "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of Misses in HitMe Cache; op is RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*", - "EventCode": "0x60", - "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of Misses in HitMe Cache; SF/LLC HitS/F and op is RdInvOwn", - "EventCode": "0x60", - "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Deallocate HitME$ on Reads without RspFwdI*", - "EventCode": "0x61", - "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a local request", - "EventCode": "0x61", - "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", - "PerPkg": "1", - "PublicDescription": "Received RspFwdI* for a local request, but converted HitME$ to SF entry", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache on RdInvOwn even if not RspFwdI*", - "EventCode": "0x61", - "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; op is RspIFwd or RspIFwdWb for a remote request", - "EventCode": "0x61", - "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM", - "PerPkg": "1", - "PublicDescription": "Updated HitME$ on RspFwdI* or local HitM/E received for a remote request", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts the number of Allocate/Update to HitMe Cache; Update HitMe Cache to SHARed", - "EventCode": "0x61", - "EventName": "UNC_CHA_HITME_UPDATE.SHARED", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AD Ring In Use; Left and Even", - "EventCode": "0xA7", - "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", - "EventCode": "0xA7", - "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AD Ring In Use; Right and Even", - "EventCode": "0xA7", - "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", - "EventCode": "0xA7", - "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AK Ring In Use; Left and Even", - "EventCode": "0xA9", - "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", - "EventCode": "0xA9", - "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AK Ring In Use; Right and Even", - "EventCode": "0xA9", - "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", - "EventCode": "0xA9", - "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal BL Ring in Use; Left and Even", - "EventCode": "0xAB", - "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", - "EventCode": "0xAB", - "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal BL Ring in Use; Right and Even", - "EventCode": "0xAB", - "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", - "EventCode": "0xAB", - "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal IV Ring in Use; Left", - "EventCode": "0xAD", - "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal IV Ring in Use; Right", - "EventCode": "0xAD", - "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Normal priority reads issued to the memory controller from the CHA", - "EventCode": "0x59", - "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", - "PerPkg": "1", - "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "HA to iMC Reads Issued; ISOCH", - "EventCode": "0x59", - "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY", - "PerPkg": "1", - "PublicDescription": "Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line Non-ISOCH", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", - "PerPkg": "1", - "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Writes Issued to the iMC by the HA; Full Line MIG", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_MIG", - "PerPkg": "1", - "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Full Line", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", - "PerPkg": "1", - "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Writes Issued to the iMC by the HA; Partial Non-ISOCH", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", - "PerPkg": "1", - "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Writes Issued to the iMC by the HA; Partial MIG", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG", - "PerPkg": "1", - "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.; Filter for memory controller 5 only.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Partial", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", - "PerPkg": "1", - "PublicDescription": "Counts the total number of writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations", - "EventCode": "0x62", - "EventName": "UNC_CHA_IODC_ALLOC.INVITOM", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IODC allocations dropped due to IODC Full", - "EventCode": "0x62", - "EventName": "UNC_CHA_IODC_ALLOC.IODCFULL", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts Number of times IODC entry allocation is attempted; Number of IDOC allocation dropped due to OSB gate", - "EventCode": "0x62", - "EventName": "UNC_CHA_IODC_ALLOC.OSBGATED", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to any reason", - "EventCode": "0x63", - "EventName": "UNC_CHA_IODC_DEALLOC.ALL", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to conflicting transaction", - "EventCode": "0x63", - "EventName": "UNC_CHA_IODC_DEALLOC.SNPOUT", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoE", - "EventCode": "0x63", - "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbMtoI", - "EventCode": "0x63", - "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOI", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Counts number of IODC deallocations; IODC deallocated due to WbPushMtoI", - "EventCode": "0x63", - "EventName": "UNC_CHA_IODC_DEALLOC.WBPUSHMTOI", - "PerPkg": "1", - "PublicDescription": "Moved to Cbo section", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache and Snoop Filter Lookups; Any Request", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.ANY", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Read transactions", - "UMask": "0x3", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache and Snoop Filter Lookups; Local", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.", - "UMask": "0x31", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache and Snoop Filter Lookups; Remote", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.", - "UMask": "0x91", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache and Snoop Filter Lookups; External Snoop Request", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ.", - "UMask": "0x9", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache and Snoop Filter Lookups; Write Requests", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.WRITE", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.", - "UMask": "0x5", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.F_STATE", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Local - All Lines", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x2f", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Local - Lines in E State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x22", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Local - Lines in F State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_F", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x28", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Local - Lines in M State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Local - Lines in S State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Remote - All Lines", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x8f", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Remote - Lines in E State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x82", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Remote - Lines in F State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_F", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x88", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Remote - Lines in M State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x81", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Remote - Lines in S State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x84", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Lines in E state", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Lines in F State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_F", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Lines in M state", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized; Lines in S State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S", - "PerPkg": "1", - "PublicDescription": "Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cbo Misc; CV0 Prefetch Miss", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.CV0_PREF_MISS", - "PerPkg": "1", - "PublicDescription": "Miscellaneous events in the Cbo.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Cbo Misc; CV0 Prefetch Victim", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.CV0_PREF_VIC", - "PerPkg": "1", - "PublicDescription": "Miscellaneous events in the Cbo.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Number of times that an RFO hit in S state.", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.RFO_HIT_S", - "PerPkg": "1", - "PublicDescription": "Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cbo Misc; Silent Snoop Eviction", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE", - "PerPkg": "1", - "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cbo Misc; Write Combining Aliasing", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.WC_ALIASING", - "PerPkg": "1", - "PublicDescription": "Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "OSB Snoop Broadcast", - "EventCode": "0x55", - "EventName": "UNC_CHA_OSB", - "PerPkg": "1", - "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC0_SMI2", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.EDC0_SMI2", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 2 only.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC1_SMI3", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.EDC1_SMI3", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 3 only.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC2_SMI4", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.EDC2_SMI4", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 4 only.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC3_SMI5", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.EDC3_SMI5", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 5 only.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC0_SMI0", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC0_SMI0", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 0 only.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC1_SMI1", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC1_SMI1", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.; Filter for memory controller 1 only.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", - "PerPkg": "1", - "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Local requests for exclusive ownership of a cache line without receiving data", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Read requests", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.READS", - "PerPkg": "1", - "PublicDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) .", - "UMask": "0x3", - "Unit": "CHA" - }, - { - "BriefDescription": "Read requests from a unit on this socket", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", - "PerPkg": "1", - "PublicDescription": "Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Read requests from a remote socket", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write).", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Write requests", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.WRITES", - "PerPkg": "1", - "PublicDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", - "UMask": "0xc", - "Unit": "CHA" - }, - { - "BriefDescription": "Write Requests from a unit on this socket", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", - "PerPkg": "1", - "PublicDescription": "Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Read and Write Requests; Writes Remote", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD", - "EventCode": "0xA1", - "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK", - "EventCode": "0xA1", - "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL", - "EventCode": "0xA1", - "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV", - "EventCode": "0xA1", - "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.; AD", - "EventCode": "0xA0", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core", - "EventCode": "0xA0", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core", - "EventCode": "0xA0", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.", - "EventCode": "0xA0", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; AD", - "EventCode": "0xA3", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; AK", - "EventCode": "0xA3", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1", - "EventCode": "0xA3", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; BL", - "EventCode": "0xA3", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; IV", - "EventCode": "0xA3", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring; AD", - "EventCode": "0xA2", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core", - "EventCode": "0xA2", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core", - "EventCode": "0xA2", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.", - "EventCode": "0xA2", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Source Throttle", - "EventCode": "0xA4", - "EventName": "UNC_CHA_RING_SRC_THRTL", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations; IPQ", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.IPQ", - "PerPkg": "1", - "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations; IRQ", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.IRQ", - "PerPkg": "1", - "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations; IRQ Rejected", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ", - "PerPkg": "1", - "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations; PRQ", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.PRQ", - "PerPkg": "1", - "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations; PRQ", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ", - "PerPkg": "1", - "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations; RRQ", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.RRQ", - "PerPkg": "1", - "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations; WBQ", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.WBQ", - "PerPkg": "1", - "PublicDescription": "Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; AD REQ on VN0", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; AD RSP on VN0", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; Non UPI AK Request", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; BL NCB on VN0", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; BL NCS on VN0", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; BL RSP on VN0", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; BL WB on VN0", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; Non UPI IV Request", - "EventCode": "0x22", - "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; Allow Snoop", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; ANY0", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; HA", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; Merging these two together to make room for ANY_REJECT_*0", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; LLC Victim", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; PhyAddr Match", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; SF Victim", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress Probe Queue Rejects; Victim", - "EventCode": "0x23", - "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Merging these two together to make room for ANY_REJECT_*0", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects; AD REQ on VN0", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects; AD RSP on VN0", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects; Non UPI AK Request", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects; BL NCB on VN0", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects; BL NCS on VN0", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects; BL RSP on VN0", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects; BL WB on VN0", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects; Non UPI IV Request", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries; AD REQ on VN0", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries; AD RSP on VN0", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries; Non UPI AK Request", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries; BL NCB on VN0", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries; BL NCS on VN0", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries; BL RSP on VN0", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries; BL WB on VN0", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries; Non UPI IV Request", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects; ANY0", - "EventCode": "0x25", - "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects; HA", - "EventCode": "0x25", - "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries; ANY0", - "EventCode": "0x2D", - "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries; HA", - "EventCode": "0x2D", - "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Occupancy; IPQ", - "EventCode": "0x11", - "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ", - "PerPkg": "1", - "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Occupancy; IRQ", - "EventCode": "0x11", - "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ", - "PerPkg": "1", - "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Occupancy; RRQ", - "EventCode": "0x11", - "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ", - "PerPkg": "1", - "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Occupancy; WBQ", - "EventCode": "0x11", - "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ", - "PerPkg": "1", - "PublicDescription": "Counts number of entries in the specified Ingress queue in each cycle.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; AD REQ on VN0", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; AD RSP on VN0", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; Non UPI AK Request", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; BL NCB on VN0", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; BL NCS on VN0", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; BL RSP on VN0", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; BL WB on VN0", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; Non UPI IV Request", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; Allow Snoop", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; ANY0", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; HA", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; Merging these two together to make room for ANY_REJECT_*0", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; LLC Victim", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; PhyAddr Match", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; SF Victim", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries; Victim", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM", - "PerPkg": "1", - "PublicDescription": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD REQ on VN0", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD RSP on VN0", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI AK Request", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCB on VN0", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL NCS on VN0", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL RSP on VN0", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL WB on VN0", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non UPI IV Request", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Allow Snoop", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY0", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC OR SF Way", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC Victim", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF Victim", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Victim", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; AD REQ on VN0", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; AD RSP on VN0", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; Non UPI AK Request", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; BL NCB on VN0", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; BL NCS on VN0", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; BL RSP on VN0", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; BL WB on VN0", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; Non UPI IV Request", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; Allow Snoop", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; ANY0", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; HA", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; Merging these two together to make room for ANY_REJECT_*0", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; LLC Victim", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; PhyAddr Match", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; SF Victim", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries; Victim", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", - "PerPkg": "1", - "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; AD REQ on VN0", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; AD RSP on VN0", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; Non UPI AK Request", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; BL NCB on VN0", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; BL NCS on VN0", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; BL RSP on VN0", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; BL WB on VN0", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; Non UPI IV Request", - "EventCode": "0x26", - "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; Allow Snoop", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; ANY0", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; HA", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; Merging these two together to make room for ANY_REJECT_*0", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; LLC Victim", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; PhyAddr Match", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; SF Victim", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "RRQ Rejects; Victim", - "EventCode": "0x27", - "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; AD REQ on VN0", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; AD RSP on VN0", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; Non UPI AK Request", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; BL NCB on VN0", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; BL NCS on VN0", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; BL RSP on VN0", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; BL WB on VN0", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; Non UPI IV Request", - "EventCode": "0x28", - "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; Allow Snoop", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; ANY0", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; HA", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; Merging these two together to make room for ANY_REJECT_*0", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; LLC Victim", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; PhyAddr Match", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; SF Victim", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "WBQ Rejects; Victim", - "EventCode": "0x29", - "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM", - "PerPkg": "1", - "PublicDescription": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation; AD - Bounce", - "EventCode": "0xB4", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation; AD - Credit", - "EventCode": "0xB4", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation; BL - Bounce", - "EventCode": "0xB4", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation; BL - Credit", - "EventCode": "0xB4", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", - "EventCode": "0xB2", - "EventName": "UNC_CHA_RxR_BYPASS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass; AD - Credit", - "EventCode": "0xB2", - "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", - "EventCode": "0xB2", - "EventName": "UNC_CHA_RxR_BYPASS.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", - "EventCode": "0xB2", - "EventName": "UNC_CHA_RxR_BYPASS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass; BL - Credit", - "EventCode": "0xB2", - "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", - "EventCode": "0xB2", - "EventName": "UNC_CHA_RxR_BYPASS.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation; AD - Bounce", - "EventCode": "0xB3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation; AD - Credit", - "EventCode": "0xB3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation; AK - Bounce", - "EventCode": "0xB3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation; BL - Bounce", - "EventCode": "0xB3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation; BL - Credit", - "EventCode": "0xB3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation; IFV - Credit", - "EventCode": "0xB3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation; IV - Bounce", - "EventCode": "0xB3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", - "EventCode": "0xB1", - "EventName": "UNC_CHA_RxR_INSERTS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations; AD - Credit", - "EventCode": "0xB1", - "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", - "EventCode": "0xB1", - "EventName": "UNC_CHA_RxR_INSERTS.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", - "EventCode": "0xB1", - "EventName": "UNC_CHA_RxR_INSERTS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations; BL - Credit", - "EventCode": "0xB1", - "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", - "EventCode": "0xB1", - "EventName": "UNC_CHA_RxR_INSERTS.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", - "EventCode": "0xB0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", - "EventCode": "0xB0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", - "EventCode": "0xB0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", - "EventCode": "0xB0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", - "EventCode": "0xB0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", - "EventCode": "0xB0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop filter capacity evictions for E-state entries.", - "EventCode": "0x3D", - "EventName": "UNC_CHA_SF_EVICTION.E_STATE", - "PerPkg": "1", - "PublicDescription": "Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop filter capacity evictions for M-state entries.", - "EventCode": "0x3D", - "EventName": "UNC_CHA_SF_EVICTION.M_STATE", - "PerPkg": "1", - "PublicDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop filter capacity evictions for S-state entries.", - "EventCode": "0x3D", - "EventName": "UNC_CHA_SF_EVICTION.S_STATE", - "PerPkg": "1", - "PublicDescription": "Counts snoop filter capacity evictions for entries tracking shared lines in the cores cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a cores cache replaces a tracked cacheline with a new cacheline.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent; All", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.ALL", - "PerPkg": "1", - "PublicDescription": "Counts the number of snoops issued by the HA.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent; Broadcast snoop for Local Requests", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL", - "PerPkg": "1", - "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast snoops issued by the HA. This filter includes only requests coming from local sockets.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent; Broadcast snoops for Remote Requests", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast snoops issued by the HA.This filter includes only requests coming from remote sockets.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent; Directed snoops for Local Requests", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", - "PerPkg": "1", - "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of directed snoops issued by the HA. This filter includes only requests coming from local sockets.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent; Directed snoops for Remote Requests", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of directed snoops issued by the HA. This filter includes only requests coming from remote sockets.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Local Requests", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL", - "PerPkg": "1", - "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the local socket.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sent for Remote Requests", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE", - "PerPkg": "1", - "PublicDescription": "Counts the number of snoops issued by the HA.; Counts the number of broadcast or directed snoops issued by the HA per request. This filter includes only requests coming from the remote socket.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "RspCnflct* Snoop Responses Received", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCTS", - "PerPkg": "1", - "PublicDescription": "Counts when a a transaction with the opcode type RspCnflct* Snoop Response was received. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent. This triggers conflict resolution hardware. This covers both the opcode RspCnflct and RspCnflctWbI.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received; RspFwd", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD", - "PerPkg": "1", - "PublicDescription": "Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspFwd to a CA request. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "RspI Snoop Responses Received", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPI", - "PerPkg": "1", - "PublicDescription": "Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data).", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "RspIFwd Snoop Responses Received", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD", - "PerPkg": "1", - "PublicDescription": "Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received : RspS", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPS", - "PerPkg": "1", - "PublicDescription": "Snoop Responses Received : RspS : Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1. : Filters for snoop responses of RspS. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "RspSFwd Snoop Responses Received", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD", - "PerPkg": "1", - "PublicDescription": "Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Rsp*Fwd*WB Snoop Responses Received", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSP_FWD_WB", - "PerPkg": "1", - "PublicDescription": "Counts when a transaction with the opcode type Rsp*Fwd*WB Snoop Response was received which indicates the data was written back to its home socket, and the cacheline was forwarded to the requestor socket. This snoop response is only used in >= 4 socket systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to its home socket to be written back to memory.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Rsp*WB Snoop Responses Received", - "EventCode": "0x5C", - "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB", - "PerPkg": "1", - "PublicDescription": "Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to its home. This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured. This response will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local; RspCnflct", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", - "PerPkg": "1", - "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoops responses of RspConflict to local CA requests. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local; RspFwd", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", - "PerPkg": "1", - "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspFwd to local CA requests. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local; RspI", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI", - "PerPkg": "1", - "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoops responses of RspI to local CA requests. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local; RspIFwd", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", - "PerPkg": "1", - "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoop responses of RspIFwd to local CA requests. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local; RspS", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS", - "PerPkg": "1", - "PublicDescription": "Number of snoop responses received for a Local request; Filters for snoop responses of RspS to local CA requests. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local; RspSFwd", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", - "PerPkg": "1", - "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspSFwd to local CA requests. This is returned when a remote caching agent forwards data but holds on to its current copy. This is common for data and code reads that hit in a remote socket in E or F state.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB", - "PerPkg": "1", - "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of Rsp*Fwd*WB to local CA requests. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local; Rsp*WB", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB", - "PerPkg": "1", - "PublicDescription": "Number of snoop responses received for a Local request; Filters for a snoop response of RspIWB or RspSWB to local CA requests. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; Hits from Local", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.ALL_HIT", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "UMask": "0x15", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; All from Local iA and IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.ALL_IO_IA", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests", - "UMask": "0x35", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; Misses from Local", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.ALL_MISS", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "UMask": "0x25", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; SF/LLC Evictions", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.EVICT", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; Hit (Not a Miss)", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.HIT", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; HITs (hit is defined to be not a miss [see below], as a result for any request allocated into the TOR, one of either HIT or MISS must be true)", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; All from Local iA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests from iA Cores", - "UMask": "0x31", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; Hits from Local iA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", - "Filter": "config1=0x40233", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", - "Filter": "config1=0x40433", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", - "Filter": "config1=0x4b233", - "PerPkg": "1", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", - "Filter": "config1=0x4b433", - "PerPkg": "1", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefRFO", - "Filter": "config1=0x4b033", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", - "Filter": "config1=0x40033", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", - "Filter": "config1=0x40233", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", - "Filter": "config1=0x40433", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", - "Filter": "config1=0x4b233", - "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", - "Filter": "config1=0x4b433", - "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefRFO", - "Filter": "config1=0x4b033", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", - "Filter": "config1=0x40033", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; All from Local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally generated IO traffic", - "UMask": "0x34", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; Hits from Local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "UMask": "0x14", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; Misses from Local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; ItoM misses from Local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", - "Filter": "config1=0x49033", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that are generated from local IO ItoM requests that miss the LLC. An ItoM request is used by IIO to request a data write without first reading the data for ownership.", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; RdCur misses from Local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RDCUR", - "Filter": "config1=0x43C33", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that are generated from local IO RdCur requests and miss the LLC. A RdCur request is used by IIO to read data without changing state.", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; RFO misses from Local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", - "Filter": "config1=0x40033", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that are generated from local IO RFO requests that miss the LLC. A read for ownership (RFO) requests a cache line to be cached in E state with the intent to modify.", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; IPQ", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IPQ", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IPQ_HIT", - "PerPkg": "1", - "UMask": "0x18", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IPQ_MISS", - "PerPkg": "1", - "UMask": "0x28", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; IRQ", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IRQ", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", - "PerPkg": "1", - "UMask": "0x37", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; Miss", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.MISS", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; Misses. (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to a local memory controller, in the event that the CHA is the home node)). Basically, if the LLC/SF/MLC complex were not able to service the request without involving another agent...it is a miss. If only IDI snoops were required, it is not a miss (that means the SF/MLC com", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; PRQ", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.PRQ", - "PerPkg": "1", - "PublicDescription": "Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL", - "PerPkg": "1", - "UMask": "0x30", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.RRQ_HIT", - "PerPkg": "1", - "UMask": "0x50", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS", - "PerPkg": "1", - "UMask": "0x60", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.WBQ_HIT", - "PerPkg": "1", - "UMask": "0x90", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.WBQ_MISS", - "PerPkg": "1", - "UMask": "0xa0", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; All from Local", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select MISS_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All remotely generated requests", - "UMask": "0x37", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; Hits from Local", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_HIT", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "UMask": "0x17", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; Misses from Local", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_MISS", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "UMask": "0x27", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; SF/LLC Evictions", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; Hit (Not a Miss)", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; HITs (hit is defined to be not a miss [see below], as a result for any request allocated into the TOR, one of either HIT or MISS must be true)", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; All from Local iA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; All locally initiated requests from iA Cores", - "UMask": "0x31", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; Hits from Local iA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", - "Filter": "config1=0x40233", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", - "Filter": "config1=0x40433", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", - "Filter": "config1=0x4b233", - "PerPkg": "1", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", - "Filter": "config1=0x4b433", - "PerPkg": "1", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", - "Filter": "config1=0x4b033", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", - "Filter": "config1=0x40033", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; Misses from Local iA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", - "Filter": "config1=0x40233", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", - "Filter": "config1=0x40433", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", - "Filter": "config1=0x4b233", - "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", - "Filter": "config1=0x4b433", - "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", - "Filter": "config1=0x4b033", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", - "Filter": "config1=0x40033", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; All from Local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; All locally generated IO traffic", - "UMask": "0x34", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; Hits from Local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "UMask": "0x14", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; Misses from Local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; ITOM Misses from Local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", - "Filter": "config1=0x49033", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO ItoM requests that miss the LLC. An ItoM is used by IIO to request a data write without first reading the data for ownership.", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; RDCUR misses from Local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RDCUR", - "Filter": "config1=0x43C33", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO RdCur requests that miss the LLC. A RdCur request is used by IIO to read data without changing state.", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; RFO misses from Local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", - "Filter": "config1=0x40033", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that are generated from local IO RFO requests that miss the LLC. A read for ownership (RFO) requests data to be cached in E state with the intent to modify.", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; IPQ", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_HIT", - "PerPkg": "1", - "UMask": "0x18", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_MISS", - "PerPkg": "1", - "UMask": "0x28", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; IRQ", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", - "PerPkg": "1", - "UMask": "0x37", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; Miss", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T; Misses. (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to a local memory controller, in the event that the CHA is the home node)). Basically, if the LLC/SF/MLC complex were not able to service the request without involving another agent...it is a miss. If only IDI snoops were required, it is not a miss (that means the SF/MLC com", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; PRQ", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ", - "PerPkg": "1", - "PublicDescription": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. T", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", - "EventCode": "0x9F", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", - "EventCode": "0x9F", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", - "EventCode": "0x9F", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", - "EventCode": "0x9F", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", - "EventCode": "0x9F", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", - "EventCode": "0x9F", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce", - "EventCode": "0x97", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit", - "EventCode": "0x97", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce", - "EventCode": "0x97", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce", - "EventCode": "0x97", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit", - "EventCode": "0x97", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce", - "EventCode": "0x97", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", - "EventCode": "0x95", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", - "EventCode": "0x95", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", - "EventCode": "0x95", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", - "EventCode": "0x95", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", - "EventCode": "0x95", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", - "EventCode": "0x95", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", - "EventCode": "0x99", - "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", - "EventCode": "0x99", - "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", - "EventCode": "0x99", - "EventName": "UNC_CHA_TxR_HORZ_NACK.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", - "EventCode": "0x99", - "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", - "EventCode": "0x99", - "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", - "EventCode": "0x99", - "EventName": "UNC_CHA_TxR_HORZ_NACK.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce", - "EventCode": "0x9B", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce", - "EventCode": "0x9B", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce", - "EventCode": "0x9B", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce", - "EventCode": "0x9B", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used; IV", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.IV", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.IV", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; IV", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_INSERTS.IV", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; IV", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK.IV", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; IV", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.IV", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED.IV", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credit Allocations; AD REQ Credits", - "EventCode": "0x38", - "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credit Allocations; AD RSP VN0 Credits", - "EventCode": "0x38", - "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credit Allocations; BL NCB Credits", - "EventCode": "0x38", - "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credit Allocations; BL NCS Credits", - "EventCode": "0x38", - "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credit Allocations; BL RSP Credits", - "EventCode": "0x38", - "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credit Allocations; BL DRS Credits", - "EventCode": "0x38", - "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_WB", - "PerPkg": "1", - "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credit Allocations; VN0 Credits", - "EventCode": "0x38", - "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VN0", - "PerPkg": "1", - "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credit Allocations; VNA Credits", - "EventCode": "0x38", - "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VNA", - "PerPkg": "1", - "PublicDescription": "Counts the number of UPI credits acquired for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This can be used with the Credit Occupancy event in order to calculate average credit lifetime. This event supports filtering to cover the VNA/VN0 credits and the different message classes. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credits In Use Cycles; AD REQ VN0 Credits", - "EventCode": "0x3B", - "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_REQ", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credits In Use Cycles; AD RSP VN0 Credits", - "EventCode": "0x3B", - "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_RSP", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCB VN0 Credits", - "EventCode": "0x3B", - "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCB", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCS VN0 Credits", - "EventCode": "0x3B", - "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCS", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credits In Use Cycles; BL RSP VN0 Credits", - "EventCode": "0x3B", - "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_RSP", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credits In Use Cycles; BL DRS VN0 Credits", - "EventCode": "0x3B", - "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_WB", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credits In Use Cycles; AD VNA Credits", - "EventCode": "0x3B", - "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_AD", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "UPI Ingress Credits In Use Cycles; BL VNA Credits", - "EventCode": "0x3B", - "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_BL", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AD Ring In Use; Down and Even", - "EventCode": "0xA6", - "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AD Ring In Use; Down and Odd", - "EventCode": "0xA6", - "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AD Ring In Use; Up and Even", - "EventCode": "0xA6", - "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AD Ring In Use; Up and Odd", - "EventCode": "0xA6", - "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AK Ring In Use; Down and Even", - "EventCode": "0xA8", - "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AK Ring In Use; Down and Odd", - "EventCode": "0xA8", - "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AK Ring In Use; Up and Even", - "EventCode": "0xA8", - "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AK Ring In Use; Up and Odd", - "EventCode": "0xA8", - "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical BL Ring in Use; Down and Even", - "EventCode": "0xAA", - "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical BL Ring in Use; Down and Odd", - "EventCode": "0xAA", - "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical BL Ring in Use; Up and Even", - "EventCode": "0xAA", - "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical BL Ring in Use; Up and Odd", - "EventCode": "0xAA", - "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical IV Ring in Use; Down", - "EventCode": "0xAC", - "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical IV Ring in Use; Up", - "EventCode": "0xAC", - "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "WbPushMtoI; Pushed to LLC", - "EventCode": "0x56", - "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when the CHA was received WbPushMtoI; Counts the number of times when the CHA was able to push WbPushMToI to LLC", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "WbPushMtoI; Pushed to Memory", - "EventCode": "0x56", - "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when the CHA was received WbPushMtoI; Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC0_SMI2", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 2 only.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC1_SMI3", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 3 only.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC2_SMI4", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 4 only.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC3_SMI5", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 5 only.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC0_SMI0", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 0 only.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC1_SMI1", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1", - "PerPkg": "1", - "PublicDescription": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.; Filter for memory controller 1 only.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Any RspIFwdFE", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response I to Fwd F/E", - "UMask": "0xe4", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response I to Fwd M", - "UMask": "0xf0", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdFE", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response S to Fwd F/E", - "UMask": "0xe2", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdM", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response S to Fwd M", - "UMask": "0xe8", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Any RspHitFSE", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Any Request - Response any to Hit F/S/E", - "UMask": "0xe1", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdFE", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response I to Fwd F/E", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdM", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response I to Fwd M", - "UMask": "0x50", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdFE", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response S to Fwd F/E", - "UMask": "0x42", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdM", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response S to Fwd M", - "UMask": "0x48", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Core RspHitFSE", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Core Request - Response any to Hit F/S/E", - "UMask": "0x41", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdFE", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response I to Fwd F/E", - "UMask": "0x84", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdM", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response I to Fwd M", - "UMask": "0x90", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdFE", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response S to Fwd F/E", - "UMask": "0x82", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdM", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response S to Fwd M", - "UMask": "0x88", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; Evict RspHitFSE", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; Eviction Request - Response any to Hit F/S/E", - "UMask": "0x81", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; External RspIFwdFE", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response I to Fwd F/E", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; External RspIFwdM", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response I to Fwd M", - "UMask": "0x30", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; External RspSFwdFE", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response S to Fwd F/E", - "UMask": "0x22", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; External RspSFwdM", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response S to Fwd M", - "UMask": "0x28", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoop Responses; External RspHitFSE", - "EventCode": "0x32", - "EventName": "UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE", - "PerPkg": "1", - "PublicDescription": "Counts the number of core cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s): from Evictions, Core or External (i.e. from a remote node) Requests. And the event can be filtered based on the responses: RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.; External Request - Response any to Hit F/S/E", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CLOCKTICKS", - "Deprecated": "1", - "EventName": "UNC_C_CLOCKTICKS", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_FAST_ASSERTED.HORZ", - "Deprecated": "1", - "EventCode": "0xA5", - "EventName": "UNC_C_FAST_ASSERTED", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.ANY", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_C_LLC_LOOKUP.ANY", - "PerPkg": "1", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_C_LLC_LOOKUP.DATA_READ", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.LOCAL", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_C_LLC_LOOKUP.LOCAL", - "PerPkg": "1", - "UMask": "0x31", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_C_LLC_LOOKUP.REMOTE", - "PerPkg": "1", - "UMask": "0x91", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP", - "PerPkg": "1", - "UMask": "0x9", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.WRITE", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_C_LLC_LOOKUP.WRITE", - "PerPkg": "1", - "UMask": "0x5", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.E_STATE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.F_STATE", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.LOCAL_ALL", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.LOCAL", - "PerPkg": "1", - "UMask": "0x2f", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.M_STATE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.REMOTE_ALL", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.REMOTE", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S", - "Deprecated": "1", - "EventCode": "0x37", - "EventName": "UNC_C_LLC_VICTIMS.S_STATE", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SRC_THRTL", - "Deprecated": "1", - "EventCode": "0xA4", - "EventName": "UNC_C_RING_SRC_THRTL", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.EVICT", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.EVICT", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.HIT", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.HIT", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IPQ", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.IPQ", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.IPQ_HIT", - "PerPkg": "1", - "UMask": "0x18", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.IPQ_MISS", - "PerPkg": "1", - "UMask": "0x28", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.IRQ", - "PerPkg": "1", - "UMask": "0x31", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_HIT", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.IRQ_HIT", - "PerPkg": "1", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA_MISS", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.IRQ_MISS", - "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.LOC_ALL", - "PerPkg": "1", - "UMask": "0x37", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IA", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.LOC_IA", - "PerPkg": "1", - "UMask": "0x31", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.LOC_IO", - "PerPkg": "1", - "UMask": "0x34", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.MISS", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.MISS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.PRQ", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.PRQ", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_HIT", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.PRQ_HIT", - "PerPkg": "1", - "UMask": "0x14", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.IO_MISS", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.PRQ_MISS", - "PerPkg": "1", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.REM_ALL", - "PerPkg": "1", - "UMask": "0x30", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.RRQ_HIT", - "PerPkg": "1", - "UMask": "0x50", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.RRQ_MISS", - "PerPkg": "1", - "UMask": "0x60", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.WBQ_HIT", - "PerPkg": "1", - "UMask": "0x90", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_C_TOR_INSERTS.WBQ_MISS", - "PerPkg": "1", - "UMask": "0xa0", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.EVICT", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.EVICT", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.HIT", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.HIT", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IPQ", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.IPQ", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_HIT", - "PerPkg": "1", - "UMask": "0x18", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_MISS", - "PerPkg": "1", - "UMask": "0x28", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.IRQ", - "PerPkg": "1", - "UMask": "0x31", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_HIT", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_HIT", - "PerPkg": "1", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA_MISS", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_MISS", - "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.LOC_ALL", - "PerPkg": "1", - "UMask": "0x37", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IA", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IA", - "PerPkg": "1", - "UMask": "0x31", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IO", - "PerPkg": "1", - "UMask": "0x34", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.MISS", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.MISS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.PRQ", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.PRQ", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_HIT", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_HIT", - "PerPkg": "1", - "UMask": "0x14", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_OCCUPANCY.IO_MISS", - "Deprecated": "1", - "EventCode": "0x36", - "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_MISS", - "PerPkg": "1", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0", - "Deprecated": "1", - "EventCode": "0x80", - "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1", - "Deprecated": "1", - "EventCode": "0x80", - "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2", - "Deprecated": "1", - "EventCode": "0x80", - "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3", - "Deprecated": "1", - "EventCode": "0x80", - "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4", - "Deprecated": "1", - "EventCode": "0x80", - "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5", - "Deprecated": "1", - "EventCode": "0x80", - "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0", - "Deprecated": "1", - "EventCode": "0x82", - "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1", - "Deprecated": "1", - "EventCode": "0x82", - "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2", - "Deprecated": "1", - "EventCode": "0x82", - "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3", - "Deprecated": "1", - "EventCode": "0x82", - "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4", - "Deprecated": "1", - "EventCode": "0x82", - "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5", - "Deprecated": "1", - "EventCode": "0x82", - "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0", - "Deprecated": "1", - "EventCode": "0x88", - "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1", - "Deprecated": "1", - "EventCode": "0x88", - "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2", - "Deprecated": "1", - "EventCode": "0x88", - "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3", - "Deprecated": "1", - "EventCode": "0x88", - "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4", - "Deprecated": "1", - "EventCode": "0x88", - "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5", - "Deprecated": "1", - "EventCode": "0x88", - "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0", - "Deprecated": "1", - "EventCode": "0x8A", - "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1", - "Deprecated": "1", - "EventCode": "0x8A", - "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2", - "Deprecated": "1", - "EventCode": "0x8A", - "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3", - "Deprecated": "1", - "EventCode": "0x8A", - "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4", - "Deprecated": "1", - "EventCode": "0x8A", - "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5", - "Deprecated": "1", - "EventCode": "0x8A", - "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0", - "Deprecated": "1", - "EventCode": "0x86", - "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1", - "Deprecated": "1", - "EventCode": "0x86", - "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2", - "Deprecated": "1", - "EventCode": "0x86", - "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3", - "Deprecated": "1", - "EventCode": "0x86", - "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4", - "Deprecated": "1", - "EventCode": "0x86", - "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5", - "Deprecated": "1", - "EventCode": "0x86", - "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0", - "Deprecated": "1", - "EventCode": "0x8E", - "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1", - "Deprecated": "1", - "EventCode": "0x8E", - "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2", - "Deprecated": "1", - "EventCode": "0x8E", - "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3", - "Deprecated": "1", - "EventCode": "0x8E", - "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4", - "Deprecated": "1", - "EventCode": "0x8E", - "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5", - "Deprecated": "1", - "EventCode": "0x8E", - "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0", - "Deprecated": "1", - "EventCode": "0x8C", - "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1", - "Deprecated": "1", - "EventCode": "0x8C", - "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2", - "Deprecated": "1", - "EventCode": "0x8C", - "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3", - "Deprecated": "1", - "EventCode": "0x8C", - "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4", - "Deprecated": "1", - "EventCode": "0x8C", - "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5", - "Deprecated": "1", - "EventCode": "0x8C", - "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", - "Deprecated": "1", - "EventCode": "0x57", - "EventName": "UNC_H_BYPASS_CHA_IMC.INTERMEDIATE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", - "Deprecated": "1", - "EventCode": "0x57", - "EventName": "UNC_H_BYPASS_CHA_IMC.NOT_TAKEN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_BYPASS_CHA_IMC.TAKEN", - "Deprecated": "1", - "EventCode": "0x57", - "EventName": "UNC_H_BYPASS_CHA_IMC.TAKEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CMS_CLOCKTICKS", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_H_CLOCK", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C1_STATE", - "Deprecated": "1", - "EventCode": "0x17", - "EventName": "UNC_H_CORE_PMA.C1_STATE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C1_TRANSITION", - "Deprecated": "1", - "EventCode": "0x17", - "EventName": "UNC_H_CORE_PMA.C1_TRANSITION", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C6_STATE", - "Deprecated": "1", - "EventCode": "0x17", - "EventName": "UNC_H_CORE_PMA.C6_STATE", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.C6_TRANSITION", - "Deprecated": "1", - "EventCode": "0x17", - "EventName": "UNC_H_CORE_PMA.C6_TRANSITION", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_PMA.GV", - "Deprecated": "1", - "EventCode": "0x17", - "EventName": "UNC_H_CORE_PMA.GV", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_GTONE", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.ANY_GTONE", - "PerPkg": "1", - "UMask": "0xe2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_ONE", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.ANY_ONE", - "PerPkg": "1", - "UMask": "0xe1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.ANY_REMOTE", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.ANY_REMOTE", - "PerPkg": "1", - "UMask": "0xe4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.CORE_GTONE", - "PerPkg": "1", - "UMask": "0x42", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_ONE", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.CORE_ONE", - "PerPkg": "1", - "UMask": "0x41", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_REMOTE", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.CORE_REMOTE", - "PerPkg": "1", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.EVICT_GTONE", - "PerPkg": "1", - "UMask": "0x82", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_ONE", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.EVICT_ONE", - "PerPkg": "1", - "UMask": "0x81", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_REMOTE", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.EVICT_REMOTE", - "PerPkg": "1", - "UMask": "0x84", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_GTONE", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.EXT_GTONE", - "PerPkg": "1", - "UMask": "0x22", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_ONE", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.EXT_ONE", - "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EXT_REMOTE", - "Deprecated": "1", - "EventCode": "0x33", - "EventName": "UNC_H_CORE_SNP.EXT_REMOTE", - "PerPkg": "1", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_COUNTER0_OCCUPANCY", - "Deprecated": "1", - "EventCode": "0x1F", - "EventName": "UNC_H_COUNTER0_OCCUPANCY", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP", - "Deprecated": "1", - "EventCode": "0x53", - "EventName": "UNC_H_DIR_LOOKUP.NO_SNP", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP", - "Deprecated": "1", - "EventCode": "0x53", - "EventName": "UNC_H_DIR_LOOKUP.SNP", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA", - "Deprecated": "1", - "EventCode": "0x54", - "EventName": "UNC_H_DIR_UPDATE.HA", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR", - "Deprecated": "1", - "EventCode": "0x54", - "EventName": "UNC_H_DIR_UPDATE.TOR", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", - "Deprecated": "1", - "EventCode": "0xAE", - "EventName": "UNC_H_EGRESS_ORDERING.IV_SNOOPGO_DN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", - "Deprecated": "1", - "EventCode": "0xAE", - "EventName": "UNC_H_EGRESS_ORDERING.IV_SNOOPGO_UP", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS", - "Deprecated": "1", - "EventCode": "0x5F", - "EventName": "UNC_H_HITME_HIT.EX_RDS", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.SHARED_OWNREQ", - "Deprecated": "1", - "EventCode": "0x5F", - "EventName": "UNC_H_HITME_HIT.SHARED_OWNREQ", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.WBMTOE", - "Deprecated": "1", - "EventCode": "0x5F", - "EventName": "UNC_H_HITME_HIT.WBMTOE", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.WBMTOI_OR_S", - "Deprecated": "1", - "EventCode": "0x5F", - "EventName": "UNC_H_HITME_HIT.WBMTOI_OR_S", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_LOOKUP.READ", - "Deprecated": "1", - "EventCode": "0x5E", - "EventName": "UNC_H_HITME_LOOKUP.READ", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_LOOKUP.WRITE", - "Deprecated": "1", - "EventCode": "0x5E", - "EventName": "UNC_H_HITME_LOOKUP.WRITE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN", - "Deprecated": "1", - "EventCode": "0x60", - "EventName": "UNC_H_HITME_MISS.NOTSHARED_RDINVOWN", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.READ_OR_INV", - "Deprecated": "1", - "EventCode": "0x60", - "EventName": "UNC_H_HITME_MISS.READ_OR_INV", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_MISS.SHARED_RDINVOWN", - "Deprecated": "1", - "EventCode": "0x60", - "EventName": "UNC_H_HITME_MISS.SHARED_RDINVOWN", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.DEALLOCATE", - "Deprecated": "1", - "EventCode": "0x61", - "EventName": "UNC_H_HITME_UPDATE.DEALLOCATE", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", - "Deprecated": "1", - "EventCode": "0x61", - "EventName": "UNC_H_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.RDINVOWN", - "Deprecated": "1", - "EventCode": "0x61", - "EventName": "UNC_H_HITME_UPDATE.RDINVOWN", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.RSPFWDI_REM", - "Deprecated": "1", - "EventCode": "0x61", - "EventName": "UNC_H_HITME_UPDATE.RSPFWDI_REM", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HITME_UPDATE.SHARED", - "Deprecated": "1", - "EventCode": "0x61", - "EventName": "UNC_H_HITME_UPDATE.SHARED", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", - "Deprecated": "1", - "EventCode": "0xA7", - "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", - "Deprecated": "1", - "EventCode": "0xA7", - "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_ODD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", - "Deprecated": "1", - "EventCode": "0xA7", - "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", - "Deprecated": "1", - "EventCode": "0xA7", - "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", - "Deprecated": "1", - "EventCode": "0xA9", - "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", - "Deprecated": "1", - "EventCode": "0xA9", - "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_ODD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", - "Deprecated": "1", - "EventCode": "0xA9", - "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", - "Deprecated": "1", - "EventCode": "0xA9", - "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", - "Deprecated": "1", - "EventCode": "0xAB", - "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", - "Deprecated": "1", - "EventCode": "0xAB", - "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_ODD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", - "Deprecated": "1", - "EventCode": "0xAB", - "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", - "Deprecated": "1", - "EventCode": "0xAB", - "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", - "Deprecated": "1", - "EventCode": "0xAD", - "EventName": "UNC_H_HORZ_RING_IV_IN_USE.LEFT", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", - "Deprecated": "1", - "EventCode": "0xAD", - "EventName": "UNC_H_HORZ_RING_IV_IN_USE.RIGHT", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_READS_COUNT.NORMAL", - "Deprecated": "1", - "EventCode": "0x59", - "EventName": "UNC_H_IMC_READS_COUNT.NORMAL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_READS_COUNT.PRIORITY", - "Deprecated": "1", - "EventCode": "0x59", - "EventName": "UNC_H_IMC_READS_COUNT.PRIORITY", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL", - "Deprecated": "1", - "EventCode": "0x5B", - "EventName": "UNC_H_IMC_WRITES_COUNT.FULL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL_MIG", - "Deprecated": "1", - "EventCode": "0x5B", - "EventName": "UNC_H_IMC_WRITES_COUNT.FULL_MIG", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", - "Deprecated": "1", - "EventCode": "0x5B", - "EventName": "UNC_H_IMC_WRITES_COUNT.FULL_PRIORITY", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL", - "Deprecated": "1", - "EventCode": "0x5B", - "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG", - "Deprecated": "1", - "EventCode": "0x5B", - "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL_MIG", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", - "Deprecated": "1", - "EventCode": "0x5B", - "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL_PRIORITY", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.INVITOM", - "Deprecated": "1", - "EventCode": "0x62", - "EventName": "UNC_H_IODC_ALLOC.INVITOM", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.IODCFULL", - "Deprecated": "1", - "EventCode": "0x62", - "EventName": "UNC_H_IODC_ALLOC.IODCFULL", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_ALLOC.OSBGATED", - "Deprecated": "1", - "EventCode": "0x62", - "EventName": "UNC_H_IODC_ALLOC.OSBGATED", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.ALL", - "Deprecated": "1", - "EventCode": "0x63", - "EventName": "UNC_H_IODC_DEALLOC.ALL", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.SNPOUT", - "Deprecated": "1", - "EventCode": "0x63", - "EventName": "UNC_H_IODC_DEALLOC.SNPOUT", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBMTOE", - "Deprecated": "1", - "EventCode": "0x63", - "EventName": "UNC_H_IODC_DEALLOC.WBMTOE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBMTOI", - "Deprecated": "1", - "EventCode": "0x63", - "EventName": "UNC_H_IODC_DEALLOC.WBMTOI", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_IODC_DEALLOC.WBPUSHMTOI", - "Deprecated": "1", - "EventCode": "0x63", - "EventName": "UNC_H_IODC_DEALLOC.WBPUSHMTOI", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.CV0_PREF_MISS", - "Deprecated": "1", - "EventCode": "0x39", - "EventName": "UNC_H_MISC.CV0_PREF_MISS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.CV0_PREF_VIC", - "Deprecated": "1", - "EventCode": "0x39", - "EventName": "UNC_H_MISC.CV0_PREF_VIC", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S", - "Deprecated": "1", - "EventCode": "0x39", - "EventName": "UNC_H_MISC.RFO_HIT_S", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.RSPI_WAS_FSE", - "Deprecated": "1", - "EventCode": "0x39", - "EventName": "UNC_H_MISC.RSPI_WAS_FSE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_MISC.WC_ALIASING", - "Deprecated": "1", - "EventCode": "0x39", - "EventName": "UNC_H_MISC.WC_ALIASING", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_OSB", - "Deprecated": "1", - "EventCode": "0x55", - "EventName": "UNC_H_OSB", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC0_SMI2", - "Deprecated": "1", - "EventCode": "0x58", - "EventName": "UNC_H_READ_NO_CREDITS.EDC0_SMI2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC1_SMI3", - "Deprecated": "1", - "EventCode": "0x58", - "EventName": "UNC_H_READ_NO_CREDITS.EDC1_SMI3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC2_SMI4", - "Deprecated": "1", - "EventCode": "0x58", - "EventName": "UNC_H_READ_NO_CREDITS.EDC2_SMI4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.EDC3_SMI5", - "Deprecated": "1", - "EventCode": "0x58", - "EventName": "UNC_H_READ_NO_CREDITS.EDC3_SMI5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.MC0_SMI0", - "Deprecated": "1", - "EventCode": "0x58", - "EventName": "UNC_H_READ_NO_CREDITS.MC0_SMI0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_READ_NO_CREDITS.MC1_SMI1", - "Deprecated": "1", - "EventCode": "0x58", - "EventName": "UNC_H_READ_NO_CREDITS.MC1_SMI1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "read requests from home agent", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.READS", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "CHA" - }, - { - "BriefDescription": "read requests from local home agent", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.READS_LOCAL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "read requests from remote home agent", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.READS_REMOTE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "write requests from home agent", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.WRITES", - "PerPkg": "1", - "UMask": "0xc", - "Unit": "CHA" - }, - { - "BriefDescription": "write requests from local home agent", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.WRITES_LOCAL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "write requests from remote home agent", - "Deprecated": "1", - "EventCode": "0x50", - "EventName": "UNC_H_REQUESTS.WRITES_REMOTE", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.AD", - "Deprecated": "1", - "EventCode": "0xA1", - "EventName": "UNC_H_RING_BOUNCES_HORZ.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.AK", - "Deprecated": "1", - "EventCode": "0xA1", - "EventName": "UNC_H_RING_BOUNCES_HORZ.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.BL", - "Deprecated": "1", - "EventCode": "0xA1", - "EventName": "UNC_H_RING_BOUNCES_HORZ.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_HORZ.IV", - "Deprecated": "1", - "EventCode": "0xA1", - "EventName": "UNC_H_RING_BOUNCES_HORZ.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.AD", - "Deprecated": "1", - "EventCode": "0xA0", - "EventName": "UNC_H_RING_BOUNCES_VERT.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.AK", - "Deprecated": "1", - "EventCode": "0xA0", - "EventName": "UNC_H_RING_BOUNCES_VERT.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.BL", - "Deprecated": "1", - "EventCode": "0xA0", - "EventName": "UNC_H_RING_BOUNCES_VERT.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_BOUNCES_VERT.IV", - "Deprecated": "1", - "EventCode": "0xA0", - "EventName": "UNC_H_RING_BOUNCES_VERT.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AD", - "Deprecated": "1", - "EventCode": "0xA3", - "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AK", - "Deprecated": "1", - "EventCode": "0xA3", - "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", - "Deprecated": "1", - "EventCode": "0xA3", - "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.BL", - "Deprecated": "1", - "EventCode": "0xA3", - "EventName": "UNC_H_RING_SINK_STARVED_HORZ.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_HORZ.IV", - "Deprecated": "1", - "EventCode": "0xA3", - "EventName": "UNC_H_RING_SINK_STARVED_HORZ.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.AD", - "Deprecated": "1", - "EventCode": "0xA2", - "EventName": "UNC_H_RING_SINK_STARVED_VERT.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.AK", - "Deprecated": "1", - "EventCode": "0xA2", - "EventName": "UNC_H_RING_SINK_STARVED_VERT.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.BL", - "Deprecated": "1", - "EventCode": "0xA2", - "EventName": "UNC_H_RING_SINK_STARVED_VERT.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RING_SINK_STARVED_VERT.IV", - "Deprecated": "1", - "EventCode": "0xA2", - "EventName": "UNC_H_RING_SINK_STARVED_VERT.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IPQ", - "Deprecated": "1", - "EventCode": "0x13", - "EventName": "UNC_H_RxC_INSERTS.IPQ", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ", - "Deprecated": "1", - "EventCode": "0x13", - "EventName": "UNC_H_RxC_INSERTS.IRQ", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ_REJ", - "Deprecated": "1", - "EventCode": "0x13", - "EventName": "UNC_H_RxC_INSERTS.IRQ_REJ", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.PRQ", - "Deprecated": "1", - "EventCode": "0x13", - "EventName": "UNC_H_RxC_INSERTS.PRQ", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.PRQ_REJ", - "Deprecated": "1", - "EventCode": "0x13", - "EventName": "UNC_H_RxC_INSERTS.PRQ_REJ", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.RRQ", - "Deprecated": "1", - "EventCode": "0x13", - "EventName": "UNC_H_RxC_INSERTS.RRQ", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.WBQ", - "Deprecated": "1", - "EventCode": "0x13", - "EventName": "UNC_H_RxC_INSERTS.WBQ", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0", - "Deprecated": "1", - "EventCode": "0x22", - "EventName": "UNC_H_RxC_IPQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x22", - "EventName": "UNC_H_RxC_IPQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0", - "Deprecated": "1", - "EventCode": "0x22", - "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0", - "Deprecated": "1", - "EventCode": "0x22", - "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x22", - "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0", - "Deprecated": "1", - "EventCode": "0x22", - "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP", - "Deprecated": "1", - "EventCode": "0x23", - "EventName": "UNC_H_RxC_IPQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.ANY0", - "Deprecated": "1", - "EventCode": "0x23", - "EventName": "UNC_H_RxC_IPQ1_REJECT.ANY_IPQ0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.HA", - "Deprecated": "1", - "EventCode": "0x23", - "EventName": "UNC_H_RxC_IPQ1_REJECT.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", - "Deprecated": "1", - "EventCode": "0x23", - "EventName": "UNC_H_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM", - "Deprecated": "1", - "EventCode": "0x23", - "EventName": "UNC_H_RxC_IPQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH", - "Deprecated": "1", - "EventCode": "0x23", - "EventName": "UNC_H_RxC_IPQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM", - "Deprecated": "1", - "EventCode": "0x23", - "EventName": "UNC_H_RxC_IPQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IPQ1_REJECT.VICTIM", - "Deprecated": "1", - "EventCode": "0x23", - "EventName": "UNC_H_RxC_IPQ1_REJECT.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", - "Deprecated": "1", - "EventCode": "0x18", - "EventName": "UNC_H_RxC_IRQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x18", - "EventName": "UNC_H_RxC_IRQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", - "Deprecated": "1", - "EventCode": "0x18", - "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", - "Deprecated": "1", - "EventCode": "0x18", - "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x18", - "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", - "Deprecated": "1", - "EventCode": "0x18", - "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", - "Deprecated": "1", - "EventCode": "0x19", - "EventName": "UNC_H_RxC_IRQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.ANY0", - "Deprecated": "1", - "EventCode": "0x19", - "EventName": "UNC_H_RxC_IRQ1_REJECT.ANY_REJECT_IRQ0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.HA", - "Deprecated": "1", - "EventCode": "0x19", - "EventName": "UNC_H_RxC_IRQ1_REJECT.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", - "Deprecated": "1", - "EventCode": "0x19", - "EventName": "UNC_H_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", - "Deprecated": "1", - "EventCode": "0x19", - "EventName": "UNC_H_RxC_IRQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", - "Deprecated": "1", - "EventCode": "0x19", - "EventName": "UNC_H_RxC_IRQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", - "Deprecated": "1", - "EventCode": "0x19", - "EventName": "UNC_H_RxC_IRQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.VICTIM", - "Deprecated": "1", - "EventCode": "0x19", - "EventName": "UNC_H_RxC_IRQ1_REJECT.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", - "Deprecated": "1", - "EventCode": "0x24", - "EventName": "UNC_H_RxC_ISMQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x24", - "EventName": "UNC_H_RxC_ISMQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", - "Deprecated": "1", - "EventCode": "0x24", - "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", - "Deprecated": "1", - "EventCode": "0x24", - "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x24", - "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", - "Deprecated": "1", - "EventCode": "0x24", - "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", - "Deprecated": "1", - "EventCode": "0x2C", - "EventName": "UNC_H_RxC_ISMQ0_RETRY.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x2C", - "EventName": "UNC_H_RxC_ISMQ0_RETRY.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", - "Deprecated": "1", - "EventCode": "0x2C", - "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", - "Deprecated": "1", - "EventCode": "0x2C", - "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x2C", - "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", - "Deprecated": "1", - "EventCode": "0x2C", - "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.ANY0", - "Deprecated": "1", - "EventCode": "0x25", - "EventName": "UNC_H_RxC_ISMQ1_REJECT.ANY_ISMQ0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_REJECT.HA", - "Deprecated": "1", - "EventCode": "0x25", - "EventName": "UNC_H_RxC_ISMQ1_REJECT.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.ANY0", - "Deprecated": "1", - "EventCode": "0x2D", - "EventName": "UNC_H_RxC_ISMQ1_RETRY.ANY", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_ISMQ1_RETRY.HA", - "Deprecated": "1", - "EventCode": "0x2D", - "EventName": "UNC_H_RxC_ISMQ1_RETRY.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IPQ", - "Deprecated": "1", - "EventCode": "0x11", - "EventName": "UNC_H_RxC_OCCUPANCY.IPQ", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ", - "Deprecated": "1", - "EventCode": "0x11", - "EventName": "UNC_H_RxC_OCCUPANCY.IRQ", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.RRQ", - "Deprecated": "1", - "EventCode": "0x11", - "EventName": "UNC_H_RxC_OCCUPANCY.RRQ", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.WBQ", - "Deprecated": "1", - "EventCode": "0x11", - "EventName": "UNC_H_RxC_OCCUPANCY.WBQ", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", - "Deprecated": "1", - "EventCode": "0x2E", - "EventName": "UNC_H_RxC_OTHER0_RETRY.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x2E", - "EventName": "UNC_H_RxC_OTHER0_RETRY.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", - "Deprecated": "1", - "EventCode": "0x2E", - "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", - "Deprecated": "1", - "EventCode": "0x2E", - "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x2E", - "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", - "Deprecated": "1", - "EventCode": "0x2E", - "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", - "Deprecated": "1", - "EventCode": "0x2F", - "EventName": "UNC_H_RxC_OTHER1_RETRY.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.ANY0", - "Deprecated": "1", - "EventCode": "0x2F", - "EventName": "UNC_H_RxC_OTHER1_RETRY.ANY", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.HA", - "Deprecated": "1", - "EventCode": "0x2F", - "EventName": "UNC_H_RxC_OTHER1_RETRY.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", - "Deprecated": "1", - "EventCode": "0x2F", - "EventName": "UNC_H_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", - "Deprecated": "1", - "EventCode": "0x2F", - "EventName": "UNC_H_RxC_OTHER1_RETRY.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", - "Deprecated": "1", - "EventCode": "0x2F", - "EventName": "UNC_H_RxC_OTHER1_RETRY.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", - "Deprecated": "1", - "EventCode": "0x2F", - "EventName": "UNC_H_RxC_OTHER1_RETRY.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_OTHER1_RETRY.VICTIM", - "Deprecated": "1", - "EventCode": "0x2F", - "EventName": "UNC_H_RxC_OTHER1_RETRY.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", - "Deprecated": "1", - "EventCode": "0x20", - "EventName": "UNC_H_RxC_PRQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x20", - "EventName": "UNC_H_RxC_PRQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", - "Deprecated": "1", - "EventCode": "0x20", - "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", - "Deprecated": "1", - "EventCode": "0x20", - "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x20", - "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", - "Deprecated": "1", - "EventCode": "0x20", - "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", - "Deprecated": "1", - "EventCode": "0x21", - "EventName": "UNC_H_RxC_PRQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.ANY0", - "Deprecated": "1", - "EventCode": "0x21", - "EventName": "UNC_H_RxC_PRQ1_REJECT.ANY_PRQ0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.HA", - "Deprecated": "1", - "EventCode": "0x21", - "EventName": "UNC_H_RxC_PRQ1_REJECT.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", - "Deprecated": "1", - "EventCode": "0x21", - "EventName": "UNC_H_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", - "Deprecated": "1", - "EventCode": "0x21", - "EventName": "UNC_H_RxC_PRQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", - "Deprecated": "1", - "EventCode": "0x21", - "EventName": "UNC_H_RxC_PRQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", - "Deprecated": "1", - "EventCode": "0x21", - "EventName": "UNC_H_RxC_PRQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_PRQ1_REJECT.VICTIM", - "Deprecated": "1", - "EventCode": "0x21", - "EventName": "UNC_H_RxC_PRQ1_REJECT.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", - "Deprecated": "1", - "EventCode": "0x2A", - "EventName": "UNC_H_RxC_REQ_Q0_RETRY.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x2A", - "EventName": "UNC_H_RxC_REQ_Q0_RETRY.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", - "Deprecated": "1", - "EventCode": "0x2A", - "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", - "Deprecated": "1", - "EventCode": "0x2A", - "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x2A", - "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", - "Deprecated": "1", - "EventCode": "0x2A", - "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", - "Deprecated": "1", - "EventCode": "0x2B", - "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", - "Deprecated": "1", - "EventCode": "0x2B", - "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ANY", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.HA", - "Deprecated": "1", - "EventCode": "0x2B", - "EventName": "UNC_H_RxC_REQ_Q1_RETRY.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", - "Deprecated": "1", - "EventCode": "0x2B", - "EventName": "UNC_H_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", - "Deprecated": "1", - "EventCode": "0x2B", - "EventName": "UNC_H_RxC_REQ_Q1_RETRY.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", - "Deprecated": "1", - "EventCode": "0x2B", - "EventName": "UNC_H_RxC_REQ_Q1_RETRY.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", - "Deprecated": "1", - "EventCode": "0x2B", - "EventName": "UNC_H_RxC_REQ_Q1_RETRY.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", - "Deprecated": "1", - "EventCode": "0x2B", - "EventName": "UNC_H_RxC_REQ_Q1_RETRY.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0", - "Deprecated": "1", - "EventCode": "0x26", - "EventName": "UNC_H_RxC_RRQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x26", - "EventName": "UNC_H_RxC_RRQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0", - "Deprecated": "1", - "EventCode": "0x26", - "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0", - "Deprecated": "1", - "EventCode": "0x26", - "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x26", - "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0", - "Deprecated": "1", - "EventCode": "0x26", - "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP", - "Deprecated": "1", - "EventCode": "0x27", - "EventName": "UNC_H_RxC_RRQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.ANY0", - "Deprecated": "1", - "EventCode": "0x27", - "EventName": "UNC_H_RxC_RRQ1_REJECT.ANY_RRQ0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.HA", - "Deprecated": "1", - "EventCode": "0x27", - "EventName": "UNC_H_RxC_RRQ1_REJECT.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", - "Deprecated": "1", - "EventCode": "0x27", - "EventName": "UNC_H_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM", - "Deprecated": "1", - "EventCode": "0x27", - "EventName": "UNC_H_RxC_RRQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH", - "Deprecated": "1", - "EventCode": "0x27", - "EventName": "UNC_H_RxC_RRQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM", - "Deprecated": "1", - "EventCode": "0x27", - "EventName": "UNC_H_RxC_RRQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_RRQ1_REJECT.VICTIM", - "Deprecated": "1", - "EventCode": "0x27", - "EventName": "UNC_H_RxC_RRQ1_REJECT.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0", - "Deprecated": "1", - "EventCode": "0x28", - "EventName": "UNC_H_RxC_WBQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x28", - "EventName": "UNC_H_RxC_WBQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0", - "Deprecated": "1", - "EventCode": "0x28", - "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0", - "Deprecated": "1", - "EventCode": "0x28", - "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0", - "Deprecated": "1", - "EventCode": "0x28", - "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0", - "Deprecated": "1", - "EventCode": "0x28", - "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP", - "Deprecated": "1", - "EventCode": "0x29", - "EventName": "UNC_H_RxC_WBQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.ANY0", - "Deprecated": "1", - "EventCode": "0x29", - "EventName": "UNC_H_RxC_WBQ1_REJECT.ANY_WBQ0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.HA", - "Deprecated": "1", - "EventCode": "0x29", - "EventName": "UNC_H_RxC_WBQ1_REJECT.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", - "Deprecated": "1", - "EventCode": "0x29", - "EventName": "UNC_H_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM", - "Deprecated": "1", - "EventCode": "0x29", - "EventName": "UNC_H_RxC_WBQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH", - "Deprecated": "1", - "EventCode": "0x29", - "EventName": "UNC_H_RxC_WBQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM", - "Deprecated": "1", - "EventCode": "0x29", - "EventName": "UNC_H_RxC_WBQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxC_WBQ1_REJECT.VICTIM", - "Deprecated": "1", - "EventCode": "0x29", - "EventName": "UNC_H_RxC_WBQ1_REJECT.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.AD_BNC", - "Deprecated": "1", - "EventCode": "0xB4", - "EventName": "UNC_H_RxR_BUSY_STARVED.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.AD_CRD", - "Deprecated": "1", - "EventCode": "0xB4", - "EventName": "UNC_H_RxR_BUSY_STARVED.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.BL_BNC", - "Deprecated": "1", - "EventCode": "0xB4", - "EventName": "UNC_H_RxR_BUSY_STARVED.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BUSY_STARVED.BL_CRD", - "Deprecated": "1", - "EventCode": "0xB4", - "EventName": "UNC_H_RxR_BUSY_STARVED.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AD_BNC", - "Deprecated": "1", - "EventCode": "0xB2", - "EventName": "UNC_H_RxR_BYPASS.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AD_CRD", - "Deprecated": "1", - "EventCode": "0xB2", - "EventName": "UNC_H_RxR_BYPASS.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.AK_BNC", - "Deprecated": "1", - "EventCode": "0xB2", - "EventName": "UNC_H_RxR_BYPASS.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.BL_BNC", - "Deprecated": "1", - "EventCode": "0xB2", - "EventName": "UNC_H_RxR_BYPASS.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.BL_CRD", - "Deprecated": "1", - "EventCode": "0xB2", - "EventName": "UNC_H_RxR_BYPASS.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_BYPASS.IV_BNC", - "Deprecated": "1", - "EventCode": "0xB2", - "EventName": "UNC_H_RxR_BYPASS.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AD_BNC", - "Deprecated": "1", - "EventCode": "0xB3", - "EventName": "UNC_H_RxR_CRD_STARVED.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AD_CRD", - "Deprecated": "1", - "EventCode": "0xB3", - "EventName": "UNC_H_RxR_CRD_STARVED.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.AK_BNC", - "Deprecated": "1", - "EventCode": "0xB3", - "EventName": "UNC_H_RxR_CRD_STARVED.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.BL_BNC", - "Deprecated": "1", - "EventCode": "0xB3", - "EventName": "UNC_H_RxR_CRD_STARVED.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.BL_CRD", - "Deprecated": "1", - "EventCode": "0xB3", - "EventName": "UNC_H_RxR_CRD_STARVED.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.IFV", - "Deprecated": "1", - "EventCode": "0xB3", - "EventName": "UNC_H_RxR_CRD_STARVED.IFV", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_CRD_STARVED.IV_BNC", - "Deprecated": "1", - "EventCode": "0xB3", - "EventName": "UNC_H_RxR_CRD_STARVED.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AD_BNC", - "Deprecated": "1", - "EventCode": "0xB1", - "EventName": "UNC_H_RxR_INSERTS.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AD_CRD", - "Deprecated": "1", - "EventCode": "0xB1", - "EventName": "UNC_H_RxR_INSERTS.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.AK_BNC", - "Deprecated": "1", - "EventCode": "0xB1", - "EventName": "UNC_H_RxR_INSERTS.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.BL_BNC", - "Deprecated": "1", - "EventCode": "0xB1", - "EventName": "UNC_H_RxR_INSERTS.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.BL_CRD", - "Deprecated": "1", - "EventCode": "0xB1", - "EventName": "UNC_H_RxR_INSERTS.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_INSERTS.IV_BNC", - "Deprecated": "1", - "EventCode": "0xB1", - "EventName": "UNC_H_RxR_INSERTS.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AD_BNC", - "Deprecated": "1", - "EventCode": "0xB0", - "EventName": "UNC_H_RxR_OCCUPANCY.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AD_CRD", - "Deprecated": "1", - "EventCode": "0xB0", - "EventName": "UNC_H_RxR_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.AK_BNC", - "Deprecated": "1", - "EventCode": "0xB0", - "EventName": "UNC_H_RxR_OCCUPANCY.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.BL_BNC", - "Deprecated": "1", - "EventCode": "0xB0", - "EventName": "UNC_H_RxR_OCCUPANCY.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.BL_CRD", - "Deprecated": "1", - "EventCode": "0xB0", - "EventName": "UNC_H_RxR_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_RxR_OCCUPANCY.IV_BNC", - "Deprecated": "1", - "EventCode": "0xB0", - "EventName": "UNC_H_RxR_OCCUPANCY.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.E_STATE", - "Deprecated": "1", - "EventCode": "0x3D", - "EventName": "UNC_H_SF_EVICTION.E_STATE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.M_STATE", - "Deprecated": "1", - "EventCode": "0x3D", - "EventName": "UNC_H_SF_EVICTION.M_STATE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SF_EVICTION.S_STATE", - "Deprecated": "1", - "EventCode": "0x3D", - "EventName": "UNC_H_SF_EVICTION.S_STATE", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.ALL", - "Deprecated": "1", - "EventCode": "0x51", - "EventName": "UNC_H_SNOOPS_SENT.", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_LOCAL", - "Deprecated": "1", - "EventCode": "0x51", - "EventName": "UNC_H_SNOOPS_SENT.BCST_LOC", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.BCST_REMOTE", - "Deprecated": "1", - "EventCode": "0x51", - "EventName": "UNC_H_SNOOPS_SENT.BCST_REM", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", - "Deprecated": "1", - "EventCode": "0x51", - "EventName": "UNC_H_SNOOPS_SENT.DIRECT_LOC", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", - "Deprecated": "1", - "EventCode": "0x51", - "EventName": "UNC_H_SNOOPS_SENT.DIRECT_REM", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.LOCAL", - "Deprecated": "1", - "EventCode": "0x51", - "EventName": "UNC_H_SNOOPS_SENT.LOCAL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOPS_SENT.REMOTE", - "Deprecated": "1", - "EventCode": "0x51", - "EventName": "UNC_H_SNOOPS_SENT.REMOTE", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPCNFLCTS", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPFWD", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSPFWD", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPI", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSPI", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSPIFWD", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPS", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSPS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_WBWB", - "Deprecated": "1", - "EventCode": "0x5C", - "EventName": "UNC_H_SNOOP_RESP.RSP_WB", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", - "Deprecated": "1", - "EventCode": "0x5D", - "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPCNFLCT", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", - "Deprecated": "1", - "EventCode": "0x5D", - "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPFWD", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPI", - "Deprecated": "1", - "EventCode": "0x5D", - "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPI", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", - "Deprecated": "1", - "EventCode": "0x5D", - "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPIFWD", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPS", - "Deprecated": "1", - "EventCode": "0x5D", - "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", - "Deprecated": "1", - "EventCode": "0x5D", - "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPSFWD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB", - "Deprecated": "1", - "EventCode": "0x5D", - "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_FWD_WB", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB", - "Deprecated": "1", - "EventCode": "0x5D", - "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_WB", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", - "Deprecated": "1", - "EventCode": "0xD0", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", - "Deprecated": "1", - "EventCode": "0xD0", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", - "Deprecated": "1", - "EventCode": "0xD0", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", - "Deprecated": "1", - "EventCode": "0xD0", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", - "Deprecated": "1", - "EventCode": "0xD0", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", - "Deprecated": "1", - "EventCode": "0xD0", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", - "Deprecated": "1", - "EventCode": "0xD2", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", - "Deprecated": "1", - "EventCode": "0xD2", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", - "Deprecated": "1", - "EventCode": "0xD2", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", - "Deprecated": "1", - "EventCode": "0xD2", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", - "Deprecated": "1", - "EventCode": "0xD2", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", - "Deprecated": "1", - "EventCode": "0xD2", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", - "Deprecated": "1", - "EventCode": "0xD4", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", - "Deprecated": "1", - "EventCode": "0xD4", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", - "Deprecated": "1", - "EventCode": "0xD4", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", - "Deprecated": "1", - "EventCode": "0xD4", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", - "Deprecated": "1", - "EventCode": "0xD4", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", - "Deprecated": "1", - "EventCode": "0xD4", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", - "Deprecated": "1", - "EventCode": "0xD6", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", - "Deprecated": "1", - "EventCode": "0xD6", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", - "Deprecated": "1", - "EventCode": "0xD6", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", - "Deprecated": "1", - "EventCode": "0xD6", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", - "Deprecated": "1", - "EventCode": "0xD6", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", - "Deprecated": "1", - "EventCode": "0xD6", - "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC", - "Deprecated": "1", - "EventCode": "0x9D", - "EventName": "UNC_H_TxR_HORZ_ADS_USED.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", - "Deprecated": "1", - "EventCode": "0x9D", - "EventName": "UNC_H_TxR_HORZ_ADS_USED.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC", - "Deprecated": "1", - "EventCode": "0x9D", - "EventName": "UNC_H_TxR_HORZ_ADS_USED.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC", - "Deprecated": "1", - "EventCode": "0x9D", - "EventName": "UNC_H_TxR_HORZ_ADS_USED.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", - "Deprecated": "1", - "EventCode": "0x9D", - "EventName": "UNC_H_TxR_HORZ_ADS_USED.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AD_BNC", - "Deprecated": "1", - "EventCode": "0x9F", - "EventName": "UNC_H_TxR_HORZ_BYPASS.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", - "Deprecated": "1", - "EventCode": "0x9F", - "EventName": "UNC_H_TxR_HORZ_BYPASS.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.AK_BNC", - "Deprecated": "1", - "EventCode": "0x9F", - "EventName": "UNC_H_TxR_HORZ_BYPASS.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.BL_BNC", - "Deprecated": "1", - "EventCode": "0x9F", - "EventName": "UNC_H_TxR_HORZ_BYPASS.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", - "Deprecated": "1", - "EventCode": "0x9F", - "EventName": "UNC_H_TxR_HORZ_BYPASS.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_BYPASS.IV_BNC", - "Deprecated": "1", - "EventCode": "0x9F", - "EventName": "UNC_H_TxR_HORZ_BYPASS.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC", - "Deprecated": "1", - "EventCode": "0x96", - "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", - "Deprecated": "1", - "EventCode": "0x96", - "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC", - "Deprecated": "1", - "EventCode": "0x96", - "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC", - "Deprecated": "1", - "EventCode": "0x96", - "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", - "Deprecated": "1", - "EventCode": "0x96", - "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC", - "Deprecated": "1", - "EventCode": "0x96", - "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC", - "Deprecated": "1", - "EventCode": "0x97", - "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", - "Deprecated": "1", - "EventCode": "0x97", - "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC", - "Deprecated": "1", - "EventCode": "0x97", - "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC", - "Deprecated": "1", - "EventCode": "0x97", - "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", - "Deprecated": "1", - "EventCode": "0x97", - "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC", - "Deprecated": "1", - "EventCode": "0x97", - "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AD_BNC", - "Deprecated": "1", - "EventCode": "0x95", - "EventName": "UNC_H_TxR_HORZ_INSERTS.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", - "Deprecated": "1", - "EventCode": "0x95", - "EventName": "UNC_H_TxR_HORZ_INSERTS.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.AK_BNC", - "Deprecated": "1", - "EventCode": "0x95", - "EventName": "UNC_H_TxR_HORZ_INSERTS.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.BL_BNC", - "Deprecated": "1", - "EventCode": "0x95", - "EventName": "UNC_H_TxR_HORZ_INSERTS.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", - "Deprecated": "1", - "EventCode": "0x95", - "EventName": "UNC_H_TxR_HORZ_INSERTS.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_INSERTS.IV_BNC", - "Deprecated": "1", - "EventCode": "0x95", - "EventName": "UNC_H_TxR_HORZ_INSERTS.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AD_BNC", - "Deprecated": "1", - "EventCode": "0x99", - "EventName": "UNC_H_TxR_HORZ_NACK.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AD_CRD", - "Deprecated": "1", - "EventCode": "0x99", - "EventName": "UNC_H_TxR_HORZ_NACK.AD_CRD", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.AK_BNC", - "Deprecated": "1", - "EventCode": "0x99", - "EventName": "UNC_H_TxR_HORZ_NACK.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.BL_BNC", - "Deprecated": "1", - "EventCode": "0x99", - "EventName": "UNC_H_TxR_HORZ_NACK.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.BL_CRD", - "Deprecated": "1", - "EventCode": "0x99", - "EventName": "UNC_H_TxR_HORZ_NACK.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_NACK.IV_BNC", - "Deprecated": "1", - "EventCode": "0x99", - "EventName": "UNC_H_TxR_HORZ_NACK.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC", - "Deprecated": "1", - "EventCode": "0x94", - "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", - "Deprecated": "1", - "EventCode": "0x94", - "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC", - "Deprecated": "1", - "EventCode": "0x94", - "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC", - "Deprecated": "1", - "EventCode": "0x94", - "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", - "Deprecated": "1", - "EventCode": "0x94", - "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC", - "Deprecated": "1", - "EventCode": "0x94", - "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.AD_BNC", - "Deprecated": "1", - "EventCode": "0x9B", - "EventName": "UNC_H_TxR_HORZ_STARVED.AD_BNC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.AK_BNC", - "Deprecated": "1", - "EventCode": "0x9B", - "EventName": "UNC_H_TxR_HORZ_STARVED.AK_BNC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.BL_BNC", - "Deprecated": "1", - "EventCode": "0x9B", - "EventName": "UNC_H_TxR_HORZ_STARVED.BL_BNC", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_HORZ_STARVED.IV_BNC", - "Deprecated": "1", - "EventCode": "0x9B", - "EventName": "UNC_H_TxR_HORZ_STARVED.IV_BNC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", - "Deprecated": "1", - "EventCode": "0x9C", - "EventName": "UNC_H_TxR_VERT_ADS_USED.AD_AG0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", - "Deprecated": "1", - "EventCode": "0x9C", - "EventName": "UNC_H_TxR_VERT_ADS_USED.AD_AG1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AK_AG0", - "Deprecated": "1", - "EventCode": "0x9C", - "EventName": "UNC_H_TxR_VERT_ADS_USED.AK_AG0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.AK_AG1", - "Deprecated": "1", - "EventCode": "0x9C", - "EventName": "UNC_H_TxR_VERT_ADS_USED.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", - "Deprecated": "1", - "EventCode": "0x9C", - "EventName": "UNC_H_TxR_VERT_ADS_USED.BL_AG0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", - "Deprecated": "1", - "EventCode": "0x9C", - "EventName": "UNC_H_TxR_VERT_ADS_USED.BL_AG1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AD_AG0", - "Deprecated": "1", - "EventCode": "0x9E", - "EventName": "UNC_H_TxR_VERT_BYPASS.AD_AG0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AD_AG1", - "Deprecated": "1", - "EventCode": "0x9E", - "EventName": "UNC_H_TxR_VERT_BYPASS.AD_AG1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AK_AG0", - "Deprecated": "1", - "EventCode": "0x9E", - "EventName": "UNC_H_TxR_VERT_BYPASS.AK_AG0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.AK_AG1", - "Deprecated": "1", - "EventCode": "0x9E", - "EventName": "UNC_H_TxR_VERT_BYPASS.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.BL_AG0", - "Deprecated": "1", - "EventCode": "0x9E", - "EventName": "UNC_H_TxR_VERT_BYPASS.BL_AG0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.BL_AG1", - "Deprecated": "1", - "EventCode": "0x9E", - "EventName": "UNC_H_TxR_VERT_BYPASS.BL_AG1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_BYPASS.IV", - "Deprecated": "1", - "EventCode": "0x9E", - "EventName": "UNC_H_TxR_VERT_BYPASS.IV_AG1", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0", - "Deprecated": "1", - "EventCode": "0x92", - "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AD_AG0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1", - "Deprecated": "1", - "EventCode": "0x92", - "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AD_AG1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0", - "Deprecated": "1", - "EventCode": "0x92", - "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AK_AG0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1", - "Deprecated": "1", - "EventCode": "0x92", - "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0", - "Deprecated": "1", - "EventCode": "0x92", - "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.BL_AG0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1", - "Deprecated": "1", - "EventCode": "0x92", - "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.BL_AG1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_FULL.IV", - "Deprecated": "1", - "EventCode": "0x92", - "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.IV_AG0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0", - "Deprecated": "1", - "EventCode": "0x93", - "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AD_AG0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1", - "Deprecated": "1", - "EventCode": "0x93", - "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AD_AG1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0", - "Deprecated": "1", - "EventCode": "0x93", - "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AK_AG0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1", - "Deprecated": "1", - "EventCode": "0x93", - "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0", - "Deprecated": "1", - "EventCode": "0x93", - "EventName": "UNC_H_TxR_VERT_CYCLES_NE.BL_AG0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1", - "Deprecated": "1", - "EventCode": "0x93", - "EventName": "UNC_H_TxR_VERT_CYCLES_NE.BL_AG1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_CYCLES_NE.IV", - "Deprecated": "1", - "EventCode": "0x93", - "EventName": "UNC_H_TxR_VERT_CYCLES_NE.IV_AG0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AD_AG0", - "Deprecated": "1", - "EventCode": "0x91", - "EventName": "UNC_H_TxR_VERT_INSERTS.AD_AG0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AD_AG1", - "Deprecated": "1", - "EventCode": "0x91", - "EventName": "UNC_H_TxR_VERT_INSERTS.AD_AG1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AK_AG0", - "Deprecated": "1", - "EventCode": "0x91", - "EventName": "UNC_H_TxR_VERT_INSERTS.AK_AG0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.AK_AG1", - "Deprecated": "1", - "EventCode": "0x91", - "EventName": "UNC_H_TxR_VERT_INSERTS.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.BL_AG0", - "Deprecated": "1", - "EventCode": "0x91", - "EventName": "UNC_H_TxR_VERT_INSERTS.BL_AG0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.BL_AG1", - "Deprecated": "1", - "EventCode": "0x91", - "EventName": "UNC_H_TxR_VERT_INSERTS.BL_AG1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_INSERTS.IV", - "Deprecated": "1", - "EventCode": "0x91", - "EventName": "UNC_H_TxR_VERT_INSERTS.IV_AG0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AD_AG0", - "Deprecated": "1", - "EventCode": "0x98", - "EventName": "UNC_H_TxR_VERT_NACK.AD_AG0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AD_AG1", - "Deprecated": "1", - "EventCode": "0x98", - "EventName": "UNC_H_TxR_VERT_NACK.AD_AG1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AK_AG0", - "Deprecated": "1", - "EventCode": "0x98", - "EventName": "UNC_H_TxR_VERT_NACK.AK_AG0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.AK_AG1", - "Deprecated": "1", - "EventCode": "0x98", - "EventName": "UNC_H_TxR_VERT_NACK.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.BL_AG0", - "Deprecated": "1", - "EventCode": "0x98", - "EventName": "UNC_H_TxR_VERT_NACK.BL_AG0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.BL_AG1", - "Deprecated": "1", - "EventCode": "0x98", - "EventName": "UNC_H_TxR_VERT_NACK.BL_AG1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_NACK.IV", - "Deprecated": "1", - "EventCode": "0x98", - "EventName": "UNC_H_TxR_VERT_NACK.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0", - "Deprecated": "1", - "EventCode": "0x90", - "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AD_AG0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1", - "Deprecated": "1", - "EventCode": "0x90", - "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AD_AG1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0", - "Deprecated": "1", - "EventCode": "0x90", - "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AK_AG0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1", - "Deprecated": "1", - "EventCode": "0x90", - "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0", - "Deprecated": "1", - "EventCode": "0x90", - "EventName": "UNC_H_TxR_VERT_OCCUPANCY.BL_AG0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1", - "Deprecated": "1", - "EventCode": "0x90", - "EventName": "UNC_H_TxR_VERT_OCCUPANCY.BL_AG1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_OCCUPANCY.IV", - "Deprecated": "1", - "EventCode": "0x90", - "EventName": "UNC_H_TxR_VERT_OCCUPANCY.IV_AG0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AD_AG0", - "Deprecated": "1", - "EventCode": "0x9A", - "EventName": "UNC_H_TxR_VERT_STARVED.AD_AG0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AD_AG1", - "Deprecated": "1", - "EventCode": "0x9A", - "EventName": "UNC_H_TxR_VERT_STARVED.AD_AG1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AK_AG0", - "Deprecated": "1", - "EventCode": "0x9A", - "EventName": "UNC_H_TxR_VERT_STARVED.AK_AG0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.AK_AG1", - "Deprecated": "1", - "EventCode": "0x9A", - "EventName": "UNC_H_TxR_VERT_STARVED.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.BL_AG0", - "Deprecated": "1", - "EventCode": "0x9A", - "EventName": "UNC_H_TxR_VERT_STARVED.BL_AG0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.BL_AG1", - "Deprecated": "1", - "EventCode": "0x9A", - "EventName": "UNC_H_TxR_VERT_STARVED.BL_AG1", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TxR_VERT_STARVED.IV", - "Deprecated": "1", - "EventCode": "0x9A", - "EventName": "UNC_H_TxR_VERT_STARVED.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", - "Deprecated": "1", - "EventCode": "0xA6", - "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_EVEN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", - "Deprecated": "1", - "EventCode": "0xA6", - "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_ODD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", - "Deprecated": "1", - "EventCode": "0xA6", - "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_EVEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", - "Deprecated": "1", - "EventCode": "0xA6", - "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_ODD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", - "Deprecated": "1", - "EventCode": "0xA8", - "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_EVEN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", - "Deprecated": "1", - "EventCode": "0xA8", - "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_ODD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", - "Deprecated": "1", - "EventCode": "0xA8", - "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_EVEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", - "Deprecated": "1", - "EventCode": "0xA8", - "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_ODD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", - "Deprecated": "1", - "EventCode": "0xAA", - "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_EVEN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", - "Deprecated": "1", - "EventCode": "0xAA", - "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_ODD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", - "Deprecated": "1", - "EventCode": "0xAA", - "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_EVEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", - "Deprecated": "1", - "EventCode": "0xAA", - "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_ODD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_IV_IN_USE.DN", - "Deprecated": "1", - "EventCode": "0xAC", - "EventName": "UNC_H_VERT_RING_IV_IN_USE.DN", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_VERT_RING_IV_IN_USE.UP", - "Deprecated": "1", - "EventCode": "0xAC", - "EventName": "UNC_H_VERT_RING_IV_IN_USE.UP", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WB_PUSH_MTOI.LLC", - "Deprecated": "1", - "EventCode": "0x56", - "EventName": "UNC_H_WB_PUSH_MTOI.LLC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WB_PUSH_MTOI.MEM", - "Deprecated": "1", - "EventCode": "0x56", - "EventName": "UNC_H_WB_PUSH_MTOI.MEM", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2", - "Deprecated": "1", - "EventCode": "0x5A", - "EventName": "UNC_H_WRITE_NO_CREDITS.EDC0_SMI2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3", - "Deprecated": "1", - "EventCode": "0x5A", - "EventName": "UNC_H_WRITE_NO_CREDITS.EDC1_SMI3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4", - "Deprecated": "1", - "EventCode": "0x5A", - "EventName": "UNC_H_WRITE_NO_CREDITS.EDC2_SMI4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5", - "Deprecated": "1", - "EventCode": "0x5A", - "EventName": "UNC_H_WRITE_NO_CREDITS.EDC3_SMI5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0", - "Deprecated": "1", - "EventCode": "0x5A", - "EventName": "UNC_H_WRITE_NO_CREDITS.MC0_SMI0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1", - "Deprecated": "1", - "EventCode": "0x5A", - "EventName": "UNC_H_WRITE_NO_CREDITS.MC1_SMI1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.ANY_RSPI_FWDFE", - "PerPkg": "1", - "UMask": "0xe4", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.ANY_RSPI_FWDM", - "PerPkg": "1", - "UMask": "0xf0", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.ANY_RSPS_FWDFE", - "PerPkg": "1", - "UMask": "0xe2", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.ANY_RSPS_FWDM", - "PerPkg": "1", - "UMask": "0xe8", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.ANY_RSP_HITFSE", - "PerPkg": "1", - "UMask": "0xe1", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.CORE_RSPI_FWDFE", - "PerPkg": "1", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.CORE_RSPI_FWDM", - "PerPkg": "1", - "UMask": "0x50", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.CORE_RSPS_FWDFE", - "PerPkg": "1", - "UMask": "0x42", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.CORE_RSPS_FWDM", - "PerPkg": "1", - "UMask": "0x48", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.CORE_RSP_HITFSE", - "PerPkg": "1", - "UMask": "0x41", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.EVICT_RSPI_FWDFE", - "PerPkg": "1", - "UMask": "0x84", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.EVICT_RSPI_FWDM", - "PerPkg": "1", - "UMask": "0x90", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.EVICT_RSPS_FWDFE", - "PerPkg": "1", - "UMask": "0x82", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.EVICT_RSPS_FWDM", - "PerPkg": "1", - "UMask": "0x88", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.EVICT_RSP_HITFSE", - "PerPkg": "1", - "UMask": "0x81", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.EXT_RSPI_FWDFE", - "PerPkg": "1", - "UMask": "0x24", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.EXT_RSPI_FWDM", - "PerPkg": "1", - "UMask": "0x30", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.EXT_RSPS_FWDFE", - "PerPkg": "1", - "UMask": "0x22", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.EXT_RSPS_FWDM", - "PerPkg": "1", - "UMask": "0x28", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE", - "Deprecated": "1", - "EventCode": "0x32", - "EventName": "UNC_H_XSNP_RESP.EXT_RSP_HITFSE", - "PerPkg": "1", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "Clockticks of the IIO Traffic Controller", - "EventCode": "0x1", - "EventName": "UNC_IIO_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Counts clockticks of the 1GHz trafiic controller clock in the IIO unit.", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", - "FCMask": "0x4", - "PerPkg": "1", - "PortMask": "0x0f", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", - "FCMask": "0x4", - "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", - "FCMask": "0x4", - "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", - "FCMask": "0x4", - "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", - "FCMask": "0x4", - "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts; Port 0", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x01", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts; Port 1", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x02", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts; Port 2", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x04", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts; Port 3", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x08", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", - "FCMask": "0x04", - "PerPkg": "1", - "UMask": "0xf", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", - "FCMask": "0x04", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 1", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", - "FCMask": "0x04", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 2", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", - "FCMask": "0x04", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 3", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", - "FCMask": "0x04", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; x4 card is plugged in to slot 3", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part0", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part2", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for 4 bytes made by the CPU to IIO Part3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core reading from Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of 4 bytes made to IIO Part0 by the CPU", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of 4 bytes made to IIO Part1 by the CPU", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of 4 bytes made to IIO Part2 by the CPU", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of 4 bytes made to IIO Part3 by the CPU", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Core writing to Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part0", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part2", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request for 4 bytes made by a different IIO unit to IIO Part3", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) reading from this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part0 by a different IIO unit", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part1 by a different IIO unit", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part2 by a different IIO unit", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of 4 bytes made to IIO Part3 by a different IIO unit", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU; Another card (different IIO stack) writing to this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests initiated by the main die to the attached device.; VTd - Type 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Completion of atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 0", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 2", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 3", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every read request for 4 bytes of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Card reading from DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Card reading from DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 0", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 2", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 3", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every write request of 4 bytes of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Card writing to DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Card writing to DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; x4 card is plugged in to slot 3", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part0 to an IIO target", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part1 to an IIO target", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part2 to an IIO target", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request for 4 bytes made by IIO Part3 to an IIO target", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer read request for 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Card reading from another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of 4 bytes made by IIO Part0 to an IIO target", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer write request of 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU; Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number of double word (4 bytes) requests the attached device made of the main die.; VTd - Type 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Num Link Correctable Errors", - "EventCode": "0xF", - "EventName": "UNC_IIO_LINK_NUM_CORR_ERR", - "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "Num Link Retries", - "EventCode": "0xE", - "EventName": "UNC_IIO_LINK_NUM_RETRIES", - "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number packets that passed the Mask/Match Filter", - "EventCode": "0x21", - "EventName": "UNC_IIO_MASK_MATCH", - "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus", - "EventCode": "0x2", - "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0", - "PerPkg": "1", - "PublicDescription": "Asserted if all bits specified by mask match", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and PCIE bus", - "EventCode": "0x2", - "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1", - "PerPkg": "1", - "PublicDescription": "Asserted if all bits specified by mask match", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus and !(PCIE bus)", - "EventCode": "0x2", - "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1", - "PerPkg": "1", - "PublicDescription": "Asserted if all bits specified by mask match", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "AND Mask/match for debug bus; PCIE bus", - "EventCode": "0x2", - "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1", - "PerPkg": "1", - "PublicDescription": "Asserted if all bits specified by mask match", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "AND Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus", - "EventCode": "0x2", - "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1", - "PerPkg": "1", - "PublicDescription": "Asserted if all bits specified by mask match", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "AND Mask/match for debug bus", - "EventCode": "0x2", - "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1", - "PerPkg": "1", - "PublicDescription": "Asserted if all bits specified by mask match", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus", - "EventCode": "0x3", - "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0", - "PerPkg": "1", - "PublicDescription": "Asserted if any bits specified by mask match", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and PCIE bus", - "EventCode": "0x3", - "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1", - "PerPkg": "1", - "PublicDescription": "Asserted if any bits specified by mask match", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and !(PCIE bus)", - "EventCode": "0x3", - "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1", - "PerPkg": "1", - "PublicDescription": "Asserted if any bits specified by mask match", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "OR Mask/match for debug bus; PCIE bus", - "EventCode": "0x3", - "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1", - "PerPkg": "1", - "PublicDescription": "Asserted if any bits specified by mask match", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) and PCIE bus", - "EventCode": "0x3", - "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1", - "PerPkg": "1", - "PublicDescription": "Asserted if any bits specified by mask match", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) and !(PCIE bus)", - "EventCode": "0x3", - "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1", - "PerPkg": "1", - "PublicDescription": "Asserted if any bits specified by mask match", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Counting disabled", - "EventName": "UNC_IIO_NOTHING", - "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1", - "Deprecated": "1", - "EventCode": "0x83", - "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1", - "Deprecated": "1", - "EventCode": "0xC0", - "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Symbol Times on Link", - "EventCode": "0x82", - "EventName": "UNC_IIO_SYMBOL_TIMES", - "PerPkg": "1", - "PublicDescription": "Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MSG.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MSG.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MSG.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MSG.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MSG.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.MSG.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x2", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART2", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x4", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART3", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x8", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD0", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x10", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1", - "Deprecated": "1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD1", - "FCMask": "0x7", - "PerPkg": "1", - "PortMask": "0x20", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; x4 card is plugged in to slot 3", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part0", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part2", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for up to a 64 byte transaction is made by the CPU to IIO Part3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core reading from Card's MMIO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part0 by the CPU", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part1 by the CPU", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part2 by the CPU", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of up to a 64 byte transaction is made to IIO Part3 by the CPU", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Core writing to Card's MMIO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part0", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part1", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part2", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request for up to a 64 byte transaction is made by a different IIO unit to IIO Part3", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) reading from this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part0 by a different IIO unit", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part1 by a different IIO unit", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part2 by a different IIO unit", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made to IIO Part3 by a different IIO unit", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU; Another card (different IIO stack) writing to this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Outbound. Number of requests, to the attached device, initiated by the main die.; VTd - Type 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Completion of atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part0 to Memory", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part1 to Memory", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part2 to Memory", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Read request for up to a 64 byte transaction is made by IIO Part3 to Memory", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every read request for up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part0 to Memory", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part1 to Memory", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part2 to Memory", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Write request of up to a 64 byte transaction is made by IIO Part3 to Memory", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every write request of up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; x4 card is plugged in to slot 3", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part0 to an IIO target", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part1 to an IIO target", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part2 to an IIO target", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer read request of up to a 64 byte transaction is made by IIO Part3 to an IIO target", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Card reading from another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part0 to an IIO target", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part1 to an IIO target", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part1 to the MMIO space of an IIO target.In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part2 to an IIO target", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Peer to peer write request of up to a 64 byte transaction is made by IIO Part3 to an IIO target", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU; Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Also known as Inbound. Number of 64 byte cache line requests initiated by the attached device.; VTd - Type 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Access; context cache miss", - "EventCode": "0x41", - "EventName": "UNC_IIO_VTD_ACCESS.CTXT_MISS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Access; L1 miss", - "EventCode": "0x41", - "EventName": "UNC_IIO_VTD_ACCESS.L1_MISS", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Access; L2 miss", - "EventCode": "0x41", - "EventName": "UNC_IIO_VTD_ACCESS.L2_MISS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Access; L3 miss", - "EventCode": "0x41", - "EventName": "UNC_IIO_VTD_ACCESS.L3_MISS", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Access; Vtd hit", - "EventCode": "0x41", - "EventName": "UNC_IIO_VTD_ACCESS.L4_PAGE_HIT", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Access; TLB miss", - "EventCode": "0x41", - "EventName": "UNC_IIO_VTD_ACCESS.TLB1_MISS", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Access; TLB is full", - "EventCode": "0x41", - "EventName": "UNC_IIO_VTD_ACCESS.TLB_FULL", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Access; TLB miss", - "EventCode": "0x41", - "EventName": "UNC_IIO_VTD_ACCESS.TLB_MISS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "VTd Occupancy", - "EventCode": "0x40", - "EventName": "UNC_IIO_VTD_OCCUPANCY", - "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "Total Write Cache Occupancy; Any Source", - "EventCode": "0xF", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Total Write Cache Occupancy; Snoops", - "EventCode": "0xF", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Total IRP occupancy of inbound read and write requests.", - "EventCode": "0xF", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", - "PerPkg": "1", - "PublicDescription": "Total IRP occupancy of inbound read and write requests. This is effectively the sum of read occupancy and write occupancy.", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "IRP Clocks", - "EventCode": "0x1", - "EventName": "UNC_I_CLOCKTICKS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; CLFlush", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x80", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; CRd", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.CRD", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; DRd", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.DRD", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; PCIDCAHin5t", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; PCIRdCur", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.PCITOM", - "PerPkg": "1", - "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.RFO", - "PerPkg": "1", - "PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops; WbMtoI", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.WBMTOI", - "PerPkg": "1", - "PublicDescription": "Counts the number of coherency related operations servied by the IRP", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "FAF RF full", - "EventCode": "0x17", - "EventName": "UNC_I_FAF_FULL", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.", - "EventCode": "0x18", - "EventName": "UNC_I_FAF_INSERTS", - "PerPkg": "1", - "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.", - "Unit": "IRP" - }, - { - "BriefDescription": "Occupancy of the IRP FAF queue.", - "EventCode": "0x19", - "EventName": "UNC_I_FAF_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.", - "Unit": "IRP" - }, - { - "BriefDescription": "FAF allocation -- sent to ADQ", - "EventCode": "0x16", - "EventName": "UNC_I_FAF_TRANSACTIONS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "All Inserts Inbound (p2p + faf + cset)", - "EventCode": "0x1E", - "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "All Inserts Outbound (BL, AK, Snoops)", - "EventCode": "0x1E", - "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary", - "EventCode": "0x1C", - "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary", - "EventCode": "0x1C", - "EventName": "UNC_I_MISC0.2ND_RD_INSERT", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary", - "EventCode": "0x1C", - "EventName": "UNC_I_MISC0.2ND_WR_INSERT", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Fastpath Rejects", - "EventCode": "0x1C", - "EventName": "UNC_I_MISC0.FAST_REJ", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Fastpath Requests", - "EventCode": "0x1C", - "EventName": "UNC_I_MISC0.FAST_REQ", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From Primary to Secondary", - "EventCode": "0x1C", - "EventName": "UNC_I_MISC0.FAST_XFER", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From Primary to Secondary", - "EventCode": "0x1C", - "EventName": "UNC_I_MISC0.PF_ACK_HINT", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 0", - "EventCode": "0x1C", - "EventName": "UNC_I_MISC0.UNKNOWN", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Lost Forward", - "EventCode": "0x1D", - "EventName": "UNC_I_MISC1.LOST_FWD", - "PerPkg": "1", - "PublicDescription": "Snoop pulled away ownership before a write was committed", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Received Invalid", - "EventCode": "0x1D", - "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", - "PerPkg": "1", - "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Received Valid", - "EventCode": "0x1D", - "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", - "PerPkg": "1", - "PublicDescription": "Secondary received a transfer that did have sufficient MESI state", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line", - "EventCode": "0x1D", - "EventName": "UNC_I_MISC1.SLOW_E", - "PerPkg": "1", - "PublicDescription": "Secondary received a transfer that did have sufficient MESI state", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line", - "EventCode": "0x1D", - "EventName": "UNC_I_MISC1.SLOW_I", - "PerPkg": "1", - "PublicDescription": "Snoop took cacheline ownership before write from data was committed.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line", - "EventCode": "0x1D", - "EventName": "UNC_I_MISC1.SLOW_M", - "PerPkg": "1", - "PublicDescription": "Snoop took cacheline ownership before write from data was committed.", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line", - "EventCode": "0x1D", - "EventName": "UNC_I_MISC1.SLOW_S", - "PerPkg": "1", - "PublicDescription": "Secondary received a transfer that did not have sufficient MESI state", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Requests", - "EventCode": "0x14", - "EventName": "UNC_I_P2P_INSERTS", - "PerPkg": "1", - "PublicDescription": "P2P requests from the ITC", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Occupancy", - "EventCode": "0x15", - "EventName": "UNC_I_P2P_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "P2P B & S Queue Occupancy", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions; P2P completions", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions; match if local only", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.LOC", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions; match if local and target matches", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions; P2P Message", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.MSG", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions; P2P reads", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.RD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions; Match if remote only", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.REM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions; match if remote and target matches", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions; P2P Writes", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.WR", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT", - "PerPkg": "1", - "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO", - "UMask": "0x7e", - "Unit": "IRP" - }, - { - "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES", - "PerPkg": "1", - "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache", - "UMask": "0x74", - "Unit": "IRP" - }, - { - "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I", - "PerPkg": "1", - "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache", - "UMask": "0x72", - "Unit": "IRP" - }, - { - "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", - "PerPkg": "1", - "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache", - "UMask": "0x78", - "Unit": "IRP" - }, - { - "BriefDescription": "Responses to snoops of any type that miss the IIO cache", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_MISS", - "PerPkg": "1", - "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that miss the IIO cache", - "UMask": "0x71", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; Hit E or S", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.HIT_ES", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; Hit I", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.HIT_I", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; Hit M", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.HIT_M", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; Miss", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.MISS", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; SnpCode", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.SNPCODE", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; SnpData", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.SNPDATA", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses; SnpInv", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.SNPINV", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Atomic", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.ATOMIC", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of atomic transactions", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Other", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.OTHER", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of 'other' kinds of transactions.", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Read Prefetches", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.RD_PREF", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches.", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Reads", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.READS", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches).", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count; Writes", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.WRITES", - "PerPkg": "1", - "PublicDescription": "Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound write (fast path) requests received by the IRP.", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.WR_PREF", - "PerPkg": "1", - "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "AK Egress Allocations", - "EventCode": "0xB", - "EventName": "UNC_I_TxC_AK_INSERTS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL DRS Egress Cycles Full", - "EventCode": "0x5", - "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL DRS Egress Inserts", - "EventCode": "0x2", - "EventName": "UNC_I_TxC_BL_DRS_INSERTS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL DRS Egress Occupancy", - "EventCode": "0x8", - "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL NCB Egress Cycles Full", - "EventCode": "0x6", - "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL NCB Egress Inserts", - "EventCode": "0x3", - "EventName": "UNC_I_TxC_BL_NCB_INSERTS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL NCB Egress Occupancy", - "EventCode": "0x9", - "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL NCS Egress Cycles Full", - "EventCode": "0x7", - "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL NCS Egress Inserts", - "EventCode": "0x4", - "EventName": "UNC_I_TxC_BL_NCS_INSERTS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL NCS Egress Occupancy", - "EventCode": "0xA", - "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "No AD Egress Credit Stalls", - "EventCode": "0x1A", - "EventName": "UNC_I_TxR2_AD_STALL_CREDIT_CYCLES", - "PerPkg": "1", - "PublicDescription": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.", - "Unit": "IRP" - }, - { - "BriefDescription": "No BL Egress Credit Stalls", - "EventCode": "0x1B", - "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", - "PerPkg": "1", - "PublicDescription": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Read Requests", - "EventCode": "0xD", - "EventName": "UNC_I_TxS_DATA_INSERTS_NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Read Requests", - "EventCode": "0xE", - "EventName": "UNC_I_TxS_DATA_INSERTS_NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of requests issued to the switch (towards the devices).", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Request Queue Occupancy", - "EventCode": "0xC", - "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjunction with the allocations event in order to calculate average latency of outbound requests.", - "Unit": "IRP" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Traffic in which the M2M to iMC Bypass was not taken", - "EventCode": "0x22", - "EventName": "UNC_M2M_BYPASS_M2M_Egress.NOT_TAKEN", - "PerPkg": "1", - "PublicDescription": "Counts traffic in which the M2M (Mesh to Memory) to iMC (Memory Controller) bypass was not taken", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC Bypass; Taken", - "EventCode": "0x22", - "EventName": "UNC_M2M_BYPASS_M2M_Egress.TAKEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC Bypass; Not Taken", - "EventCode": "0x21", - "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC Bypass; Taken", - "EventCode": "0x21", - "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles - at UCLK", - "EventName": "UNC_M2M_CLOCKTICKS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Clockticks", - "EventCode": "0xC0", - "EventName": "UNC_M2M_CMS_CLOCKTICKS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles when direct to core mode (which bypasses the CHA) was disabled", - "EventCode": "0x24", - "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", - "PerPkg": "1", - "PublicDescription": "Counts cycles when direct to core mode (which bypasses the CHA) was disabled", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages sent direct to core (bypassing the CHA)", - "EventCode": "0x23", - "EventName": "UNC_M2M_DIRECT2CORE_TAKEN", - "PerPkg": "1", - "PublicDescription": "Counts when messages were sent direct to core (bypassing the CHA)", - "Unit": "M2M" - }, - { - "BriefDescription": "Number of reads in which direct to core transaction were overridden", - "EventCode": "0x25", - "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", - "PerPkg": "1", - "PublicDescription": "Counts reads in which direct to core transactions (which would have bypassed the CHA) were overridden", - "Unit": "M2M" - }, - { - "BriefDescription": "Number of reads in which direct to Intel(R) UPI transactions were overridden", - "EventCode": "0x28", - "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS", - "PerPkg": "1", - "PublicDescription": "Counts reads in which direct to Intel(R) Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overridden", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles when direct to Intel(R) UPI was disabled", - "EventCode": "0x27", - "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE", - "PerPkg": "1", - "PublicDescription": "Counts cycles when the ability to send messages direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA) was disabled", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages sent direct to the Intel(R) UPI", - "EventCode": "0x26", - "EventName": "UNC_M2M_DIRECT2UPI_TAKEN", - "PerPkg": "1", - "PublicDescription": "Counts when messages were sent direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA)", - "Unit": "M2M" - }, - { - "BriefDescription": "Number of reads that a message sent direct2 Intel(R) UPI was overridden", - "EventCode": "0x29", - "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE", - "PerPkg": "1", - "PublicDescription": "Counts when a read message that was sent direct to the Intel(R) Ultra Path Interconnect (bypassing the CHA) was overridden", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Hit; On NonDirty Line in A State", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Hit; On NonDirty Line in I State", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Hit; On NonDirty Line in L State", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Hit; On NonDirty Line in S State", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Hit; On Dirty Line in A State", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Hit; On Dirty Line in I State", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Hit; On Dirty Line in L State", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Hit; On Dirty Line in S State", - "EventCode": "0x2A", - "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory lookups (any state found)", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in Any State (A, I, S or unused)", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory lookups (cacheline found in A state)", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in the A (SnoopAll) state, indicating the cacheline is stored in another socket in any state, and we must snoop the other sockets to make sure we get the latest data. The data may be stored in any state in the local socket.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in I state)", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the I (Invalid) state indicating the cacheline is not stored in another socket, and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory lookup (cacheline found in S state)", - "EventCode": "0x2D", - "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the S (Shared) state indicating the cacheline is either stored in another socket in the S(hared) state , and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Miss; On NonDirty Line in A State", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Miss; On NonDirty Line in I State", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Miss; On NonDirty Line in L State", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Miss; On NonDirty Line in S State", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Miss; On Dirty Line in A State", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Miss; On Dirty Line in I State", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Miss; On Dirty Line in L State", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Directory Miss; On Dirty Line in S State", - "EventCode": "0x2B", - "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory update from A to I", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from A (SnoopAll) to I (Invalid)", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory update from A to S", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from A (SnoopAll) to S (Shared)", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory update from/to Any state", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory to a new state", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory update from I to A", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from I (Invalid) to A (SnoopAll)", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory update from I to S", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from I (Invalid) to S (Shared)", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory update from S to A", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from S (Shared) to A (SnoopAll)", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Multi-socket cacheline Directory update from S to I", - "EventCode": "0x2E", - "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from S (Shared) to I (Invalid)", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements; Down", - "EventCode": "0xAE", - "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN", - "PerPkg": "1", - "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements; Up", - "EventCode": "0xAE", - "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP", - "PerPkg": "1", - "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "FaST wire asserted; Horizontal", - "EventCode": "0xA5", - "EventName": "UNC_M2M_FAST_ASSERTED.HORZ", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "FaST wire asserted; Vertical", - "EventCode": "0xA5", - "EventName": "UNC_M2M_FAST_ASSERTED.VERT", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AD Ring In Use; Left and Even", - "EventCode": "0xA7", - "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", - "EventCode": "0xA7", - "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AD Ring In Use; Right and Even", - "EventCode": "0xA7", - "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", - "EventCode": "0xA7", - "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AK Ring In Use; Left and Even", - "EventCode": "0xA9", - "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", - "EventCode": "0xA9", - "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AK Ring In Use; Right and Even", - "EventCode": "0xA9", - "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", - "EventCode": "0xA9", - "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal BL Ring in Use; Left and Even", - "EventCode": "0xAB", - "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", - "EventCode": "0xAB", - "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal BL Ring in Use; Right and Even", - "EventCode": "0xAB", - "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", - "EventCode": "0xAB", - "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal IV Ring in Use; Left", - "EventCode": "0xAD", - "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal IV Ring in Use; Right", - "EventCode": "0xAD", - "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Reads to iMC issued", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.ALL", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller).", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC; All, regardless of priority.", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.FROM_TRANSGRESS", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC; Critical Priority", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.ISOCH", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Reads to iMC issued at Normal Priority (Non-Isochronous)", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.NORMAL", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller). It only counts normal priority non-isochronous reads.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Writes to iMC issued", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.ALL", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) issues writes to the iMC (Memory Controller).", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority.", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.FROM_TRANSGRESS", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC; Full Line Non-ISOCH", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.FULL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC; ISOCH Full Line", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC; All, regardless of priority.", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.NI", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Partial Non-Isochronous writes to the iMC", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) issues partial writes to the iMC (Memory Controller). It only counts normal priority non-isochronous writes.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC; ISOCH Partial", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Number Packet Header Matches; MC Match", - "EventCode": "0x4C", - "EventName": "UNC_M2M_PKT_MATCH.MC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Number Packet Header Matches; Mesh Match", - "EventCode": "0x4C", - "EventName": "UNC_M2M_PKT_MATCH.MESH", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Cycles Full", - "EventCode": "0x53", - "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Cycles Not Empty", - "EventCode": "0x54", - "EventName": "UNC_M2M_PREFCAM_CYCLES_NE", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch requests that got turn into a demand request", - "EventCode": "0x56", - "EventName": "UNC_M2M_PREFCAM_DEMAND_PROMOTIONS", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) promotes a outstanding request in the prefetch queue due to a subsequent demand read request that entered the M2M with the same address. Explanatory Side Note: The Prefetch queue is made of CAM (Content Addressable Memory)", - "Unit": "M2M" - }, - { - "BriefDescription": "Inserts into the Memory Controller Prefetch Queue", - "EventCode": "0x57", - "EventName": "UNC_M2M_PREFCAM_INSERTS", - "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) receives a prefetch request and inserts it into its outstanding prefetch queue. Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Occupancy", - "EventCode": "0x55", - "EventName": "UNC_M2M_PREFCAM_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD", - "EventCode": "0xA1", - "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK", - "EventCode": "0xA1", - "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL", - "EventCode": "0xA1", - "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV", - "EventCode": "0xA1", - "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.; AD", - "EventCode": "0xA0", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core", - "EventCode": "0xA0", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core", - "EventCode": "0xA0", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.", - "EventCode": "0xA0", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; AD", - "EventCode": "0xA3", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; AK", - "EventCode": "0xA3", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1", - "EventCode": "0xA3", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; BL", - "EventCode": "0xA3", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; IV", - "EventCode": "0xA3", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring; AD", - "EventCode": "0xA2", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core", - "EventCode": "0xA2", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core", - "EventCode": "0xA2", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.", - "EventCode": "0xA2", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Source Throttle", - "EventCode": "0xA4", - "EventName": "UNC_M2M_RING_SRC_THRTL", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0", - "Deprecated": "1", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1", - "Deprecated": "1", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2", - "Deprecated": "1", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 0", - "EventCode": "0x43", - "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 1", - "EventCode": "0x43", - "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Channel 2", - "EventCode": "0x43", - "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 0", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 1", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Channel 2", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Ingress (from CMS) Full", - "EventCode": "0x4", - "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Ingress (from CMS) Not Empty", - "EventCode": "0x3", - "EventName": "UNC_M2M_RxC_AD_CYCLES_NE", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Ingress (from CMS) Queue Inserts", - "EventCode": "0x1", - "EventName": "UNC_M2M_RxC_AD_INSERTS", - "PerPkg": "1", - "PublicDescription": "Counts when the a new entry is Received(RxC) and then added to the AD (Address Ring) Ingress Queue from the CMS (Common Mesh Stop). This is generally used for reads, and", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Ingress (from CMS) Occupancy", - "EventCode": "0x2", - "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Ingress (from CMS) Full", - "EventCode": "0x8", - "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Ingress (from CMS) Not Empty", - "EventCode": "0x7", - "EventName": "UNC_M2M_RxC_BL_CYCLES_NE", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Ingress (from CMS) Allocations", - "EventCode": "0x5", - "EventName": "UNC_M2M_RxC_BL_INSERTS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Ingress (from CMS) Occupancy", - "EventCode": "0x6", - "EventName": "UNC_M2M_RxC_BL_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation; AD - Bounce", - "EventCode": "0xB4", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation; AD - Credit", - "EventCode": "0xB4", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation; BL - Bounce", - "EventCode": "0xB4", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation; BL - Credit", - "EventCode": "0xB4", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", - "EventCode": "0xB2", - "EventName": "UNC_M2M_RxR_BYPASS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass; AD - Credit", - "EventCode": "0xB2", - "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", - "EventCode": "0xB2", - "EventName": "UNC_M2M_RxR_BYPASS.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", - "EventCode": "0xB2", - "EventName": "UNC_M2M_RxR_BYPASS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass; BL - Credit", - "EventCode": "0xB2", - "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", - "EventCode": "0xB2", - "EventName": "UNC_M2M_RxR_BYPASS.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation; AD - Bounce", - "EventCode": "0xB3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation; AD - Credit", - "EventCode": "0xB3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation; AK - Bounce", - "EventCode": "0xB3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation; BL - Bounce", - "EventCode": "0xB3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation; BL - Credit", - "EventCode": "0xB3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation; IFV - Credit", - "EventCode": "0xB3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation; IV - Bounce", - "EventCode": "0xB3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", - "EventCode": "0xB1", - "EventName": "UNC_M2M_RxR_INSERTS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations; AD - Credit", - "EventCode": "0xB1", - "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", - "EventCode": "0xB1", - "EventName": "UNC_M2M_RxR_INSERTS.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", - "EventCode": "0xB1", - "EventName": "UNC_M2M_RxR_INSERTS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations; BL - Credit", - "EventCode": "0xB1", - "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", - "EventCode": "0xB1", - "EventName": "UNC_M2M_RxR_INSERTS.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", - "EventCode": "0xB0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", - "EventCode": "0xB0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", - "EventCode": "0xB0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", - "EventCode": "0xB0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", - "EventCode": "0xB0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", - "EventCode": "0xB0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Number AD Ingress Credits", - "EventCode": "0x41", - "EventName": "UNC_M2M_TGR_AD_CREDITS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Number BL Ingress Credits", - "EventCode": "0x42", - "EventName": "UNC_M2M_TGR_BL_CREDITS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Cycles Full; Channel 0", - "EventCode": "0x45", - "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Cycles Full; Channel 1", - "EventCode": "0x45", - "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Cycles Full; Channel 2", - "EventCode": "0x45", - "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Cycles Not Empty; Channel 0", - "EventCode": "0x46", - "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Cycles Not Empty; Channel 1", - "EventCode": "0x46", - "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Cycles Not Empty; Channel 2", - "EventCode": "0x46", - "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Inserts; Channel 0", - "EventCode": "0x49", - "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Inserts; Channel 1", - "EventCode": "0x49", - "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Inserts; Channel 2", - "EventCode": "0x49", - "EventName": "UNC_M2M_TRACKER_INSERTS.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Occupancy; Channel 0", - "EventCode": "0x47", - "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Occupancy; Channel 1", - "EventCode": "0x47", - "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Occupancy; Channel 2", - "EventCode": "0x47", - "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Pending Occupancy", - "EventCode": "0x48", - "EventName": "UNC_M2M_TRACKER_PENDING_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Egress (to CMS) Credit Acquired", - "EventCode": "0xD", - "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Egress (to CMS) Credits Occupancy", - "EventCode": "0xE", - "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Egress (to CMS) Full", - "EventCode": "0xC", - "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Egress (to CMS) Not Empty", - "EventCode": "0xB", - "EventName": "UNC_M2M_TxC_AD_CYCLES_NE", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Egress (to CMS) Allocations", - "EventCode": "0x9", - "EventName": "UNC_M2M_TxC_AD_INSERTS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles with No AD Egress (to CMS) Credits", - "EventCode": "0xF", - "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits", - "EventCode": "0x10", - "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Egress (to CMS) Occupancy", - "EventCode": "0xA", - "EventName": "UNC_M2M_TxC_AD_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Outbound Ring Transactions on AK; CRD Transactions to Cbo", - "EventCode": "0x39", - "EventName": "UNC_M2M_TxC_AK.CRD_CBO", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Outbound Ring Transactions on AK; NDR Transactions", - "EventCode": "0x39", - "EventName": "UNC_M2M_TxC_AK.NDR", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side", - "EventCode": "0x1D", - "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side", - "EventCode": "0x1D", - "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side", - "EventCode": "0x1E", - "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side", - "EventCode": "0x1E", - "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full; All", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Near Side", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - Far Side", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1", - "PerPkg": "1", - "UMask": "0x88", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full; Write Compare Request", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1", - "PerPkg": "1", - "UMask": "0xa0", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1", - "PerPkg": "1", - "UMask": "0x90", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Not Empty; All", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Near Side", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Stop - Far Side", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Not Empty; Read Credit Request", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Not Empty; Write Compare Request", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Not Empty; Write Credit Request", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations; All", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Near Side", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh Stop - Far Side", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations; Prefetch Read Cam Hit", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations; Read Credit Request", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations; Write Compare Request", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations; Write Credit Request", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side", - "EventCode": "0x1F", - "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side", - "EventCode": "0x1F", - "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Near Side", - "EventCode": "0x20", - "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits; Common Mesh Stop - Far Side", - "EventCode": "0x20", - "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Occupancy; All", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Near Side", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Stop - Far Side", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Occupancy; Read Credit Request", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Occupancy; Write Compare Request", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Occupancy; Write Credit Request", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Sideband", - "EventCode": "0x6B", - "EventName": "UNC_M2M_TxC_AK_SIDEBAND.RD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Sideband", - "EventCode": "0x6B", - "EventName": "UNC_M2M_TxC_AK_SIDEBAND.WR", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Cache", - "EventCode": "0x40", - "EventName": "UNC_M2M_TxC_BL.DRS_CACHE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to Core", - "EventCode": "0x40", - "EventName": "UNC_M2M_TxC_BL.DRS_CORE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data to QPI", - "EventCode": "0x40", - "EventName": "UNC_M2M_TxC_BL.DRS_UPI", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Near Side", - "EventCode": "0x19", - "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Mesh Stop - Far Side", - "EventCode": "0x19", - "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Near Side", - "EventCode": "0x1A", - "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common Mesh Stop - Far Side", - "EventCode": "0x1A", - "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Full; All", - "EventCode": "0x18", - "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Near Side", - "EventCode": "0x18", - "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - Far Side", - "EventCode": "0x18", - "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Not Empty; All", - "EventCode": "0x17", - "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Near Side", - "EventCode": "0x17", - "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Stop - Far Side", - "EventCode": "0x17", - "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Allocations; All", - "EventCode": "0x15", - "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Near Side", - "EventCode": "0x15", - "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh Stop - Far Side", - "EventCode": "0x15", - "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side", - "EventCode": "0x1B", - "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side", - "EventCode": "0x1B", - "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Near Side", - "EventCode": "0x1C", - "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits; Common Mesh Stop - Far Side", - "EventCode": "0x1C", - "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Occupancy; All", - "EventCode": "0x16", - "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Near Side", - "EventCode": "0x16", - "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Stop - Far Side", - "EventCode": "0x16", - "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", - "EventCode": "0x9F", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", - "EventCode": "0x9F", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", - "EventCode": "0x9F", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", - "EventCode": "0x9F", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", - "EventCode": "0x9F", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", - "EventCode": "0x9F", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce", - "EventCode": "0x97", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit", - "EventCode": "0x97", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce", - "EventCode": "0x97", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce", - "EventCode": "0x97", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit", - "EventCode": "0x97", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce", - "EventCode": "0x97", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", - "EventCode": "0x95", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", - "EventCode": "0x95", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", - "EventCode": "0x95", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", - "EventCode": "0x95", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", - "EventCode": "0x95", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", - "EventCode": "0x95", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", - "EventCode": "0x99", - "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", - "EventCode": "0x99", - "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", - "EventCode": "0x99", - "EventName": "UNC_M2M_TxR_HORZ_NACK.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", - "EventCode": "0x99", - "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", - "EventCode": "0x99", - "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", - "EventCode": "0x99", - "EventName": "UNC_M2M_TxR_HORZ_NACK.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce", - "EventCode": "0x9B", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce", - "EventCode": "0x9B", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce", - "EventCode": "0x9B", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce", - "EventCode": "0x9B", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used; IV", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.IV", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.IV", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; IV", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_INSERTS.IV", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; IV", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK.IV", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; IV", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.IV", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED.IV", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AD Ring In Use; Down and Even", - "EventCode": "0xA6", - "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AD Ring In Use; Down and Odd", - "EventCode": "0xA6", - "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AD Ring In Use; Up and Even", - "EventCode": "0xA6", - "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AD Ring In Use; Up and Odd", - "EventCode": "0xA6", - "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AK Ring In Use; Down and Even", - "EventCode": "0xA8", - "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AK Ring In Use; Down and Odd", - "EventCode": "0xA8", - "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AK Ring In Use; Up and Even", - "EventCode": "0xA8", - "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AK Ring In Use; Up and Odd", - "EventCode": "0xA8", - "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical BL Ring in Use; Down and Even", - "EventCode": "0xAA", - "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical BL Ring in Use; Down and Odd", - "EventCode": "0xAA", - "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical BL Ring in Use; Up and Even", - "EventCode": "0xAA", - "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical BL Ring in Use; Up and Odd", - "EventCode": "0xAA", - "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical IV Ring in Use; Down", - "EventCode": "0xAC", - "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical IV Ring in Use; Up", - "EventCode": "0xAC", - "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0", - "Deprecated": "1", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1", - "Deprecated": "1", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2", - "Deprecated": "1", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 0", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 1", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Channel 2", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 0", - "EventCode": "0x4E", - "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 1", - "EventCode": "0x4E", - "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Channel 2", - "EventCode": "0x4E", - "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Full; Channel 0", - "EventCode": "0x4A", - "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Full; Channel 1", - "EventCode": "0x4A", - "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Full; Channel 2", - "EventCode": "0x4A", - "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Not Empty; Channel 0", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Not Empty; Channel 1", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Not Empty; Channel 2", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Inserts; Channel 0", - "EventCode": "0x61", - "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Inserts; Channel 1", - "EventCode": "0x61", - "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Inserts; Channel 2", - "EventCode": "0x61", - "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Occupancy; Channel 0", - "EventCode": "0x60", - "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Occupancy; Channel 1", - "EventCode": "0x60", - "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Occupancy; Channel 2", - "EventCode": "0x60", - "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 0", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 1", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 2", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 3", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 4", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgress 5", - "EventCode": "0x80", - "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 0", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 1", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 2", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 3", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 4", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgress 5", - "EventCode": "0x82", - "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 0", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 1", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 2", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 3", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 4", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgress 5", - "EventCode": "0x88", - "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 0", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 1", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 2", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 3", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 4", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgress 5", - "EventCode": "0x8A", - "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 0", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 1", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 2", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 3", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 4", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgress 5", - "EventCode": "0x84", - "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 0", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 1", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 2", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 3", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 4", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgress 5", - "EventCode": "0x86", - "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 0", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 1", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 2", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 3", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 4", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgress 5", - "EventCode": "0x8E", - "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 0", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 1", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 2", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 3", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 4", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgress 5", - "EventCode": "0x8C", - "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CBox AD Credits Empty; Requests", - "EventCode": "0x22", - "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CBox AD Credits Empty; Snoops", - "EventCode": "0x22", - "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CBox AD Credits Empty; VNA Messages", - "EventCode": "0x22", - "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CBox AD Credits Empty; Writebacks", - "EventCode": "0x22", - "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB", - "PerPkg": "1", - "PublicDescription": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Number of uclks in domain", - "EventCode": "0x1", - "EventName": "UNC_M3UPI_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Clockticks", - "EventCode": "0xC0", - "EventName": "UNC_M3UPI_CMS_CLOCKTICKS", - "PerPkg": "1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "D2C Sent", - "EventCode": "0x2B", - "EventName": "UNC_M3UPI_D2C_SENT", - "PerPkg": "1", - "PublicDescription": "Count cases BL sends direct to core", - "Unit": "M3UPI" - }, - { - "BriefDescription": "D2U Sent", - "EventCode": "0x2A", - "EventName": "UNC_M3UPI_D2U_SENT", - "PerPkg": "1", - "PublicDescription": "Cases where SMI3 sends D2U command", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements; Down", - "EventCode": "0xAE", - "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN", - "PerPkg": "1", - "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements; Up", - "EventCode": "0xAE", - "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP", - "PerPkg": "1", - "PublicDescription": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "FaST wire asserted; Horizontal", - "EventCode": "0xA5", - "EventName": "UNC_M3UPI_FAST_ASSERTED.HORZ", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "FaST wire asserted; Vertical", - "EventCode": "0xA5", - "EventName": "UNC_M3UPI_FAST_ASSERTED.VERT", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AD Ring In Use; Left and Even", - "EventCode": "0xA7", - "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", - "EventCode": "0xA7", - "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AD Ring In Use; Right and Even", - "EventCode": "0xA7", - "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", - "EventCode": "0xA7", - "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AK Ring In Use; Left and Even", - "EventCode": "0xA9", - "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", - "EventCode": "0xA9", - "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AK Ring In Use; Right and Even", - "EventCode": "0xA9", - "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", - "EventCode": "0xA9", - "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal BL Ring in Use; Left and Even", - "EventCode": "0xAB", - "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", - "EventCode": "0xAB", - "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal BL Ring in Use; Right and Even", - "EventCode": "0xAB", - "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", - "EventCode": "0xAB", - "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal IV Ring in Use; Left", - "EventCode": "0xAD", - "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Horizontal IV Ring in Use; Right", - "EventCode": "0xAD", - "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "M2 BL Credits Empty; IIO0 and IIO1 share the same ring destination. (1 VN0 credit only)", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO0_IIO1_NCB", - "PerPkg": "1", - "PublicDescription": "No vn0 and vna credits available to send to M2", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "M2 BL Credits Empty; IIO2", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB", - "PerPkg": "1", - "PublicDescription": "No vn0 and vna credits available to send to M2", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "M2 BL Credits Empty; IIO3", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB", - "PerPkg": "1", - "PublicDescription": "No vn0 and vna credits available to send to M2", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "M2 BL Credits Empty; IIO4", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB", - "PerPkg": "1", - "PublicDescription": "No vn0 and vna credits available to send to M2", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "M2 BL Credits Empty; IIO5", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB", - "PerPkg": "1", - "PublicDescription": "No vn0 and vna credits available to send to M2", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "M2 BL Credits Empty; All IIO targets for NCS are in single mask. ORs them together", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS", - "PerPkg": "1", - "PublicDescription": "No vn0 and vna credits available to send to M2", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "M2 BL Credits Empty; Selected M2p BL NCS credits", - "EventCode": "0x23", - "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL", - "PerPkg": "1", - "PublicDescription": "No vn0 and vna credits available to send to M2", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Multi Slot Flit Received; AD - Slot 0", - "EventCode": "0x3E", - "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0", - "PerPkg": "1", - "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Multi Slot Flit Received; AD - Slot 1", - "EventCode": "0x3E", - "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1", - "PerPkg": "1", - "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Multi Slot Flit Received; AD - Slot 2", - "EventCode": "0x3E", - "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2", - "PerPkg": "1", - "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Multi Slot Flit Received; AK - Slot 0", - "EventCode": "0x3E", - "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0", - "PerPkg": "1", - "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Multi Slot Flit Received; AK - Slot 2", - "EventCode": "0x3E", - "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2", - "PerPkg": "1", - "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Multi Slot Flit Received; BL - Slot 0", - "EventCode": "0x3E", - "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0", - "PerPkg": "1", - "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring.; AD", - "EventCode": "0xA1", - "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring.; AK", - "EventCode": "0xA1", - "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring.; BL", - "EventCode": "0xA1", - "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring.; IV", - "EventCode": "0xA1", - "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.; AD", - "EventCode": "0xA0", - "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.; Acknowledgements to core", - "EventCode": "0xA0", - "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.; Data Responses to core", - "EventCode": "0xA0", - "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.; Snoops of processor's cache.", - "EventCode": "0xA0", - "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV", - "PerPkg": "1", - "PublicDescription": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; AD", - "EventCode": "0xA3", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; AK", - "EventCode": "0xA3", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowledgements to Agent 1", - "EventCode": "0xA3", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; BL", - "EventCode": "0xA3", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring; IV", - "EventCode": "0xA3", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring; AD", - "EventCode": "0xA2", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledgements to core", - "EventCode": "0xA2", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring; Data Responses to core", - "EventCode": "0xA2", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of processor's cache.", - "EventCode": "0xA2", - "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Source Throttle", - "EventCode": "0xA4", - "EventName": "UNC_M3UPI_RING_SRC_THRTL", - "PerPkg": "1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN0; REQ on AD", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ", - "PerPkg": "1", - "PublicDescription": "VN0 message requested but lost arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN0; RSP on AD", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP", - "PerPkg": "1", - "PublicDescription": "VN0 message requested but lost arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN0; SNP on AD", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP", - "PerPkg": "1", - "PublicDescription": "VN0 message requested but lost arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN0; NCB on BL", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB", - "PerPkg": "1", - "PublicDescription": "VN0 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN0; NCS on BL", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS", - "PerPkg": "1", - "PublicDescription": "VN0 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN0; RSP on BL", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP", - "PerPkg": "1", - "PublicDescription": "VN0 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN0; WB on BL", - "EventCode": "0x4B", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB", - "PerPkg": "1", - "PublicDescription": "VN0 message requested but lost arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN1; REQ on AD", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ", - "PerPkg": "1", - "PublicDescription": "VN1 message requested but lost arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN1; RSP on AD", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP", - "PerPkg": "1", - "PublicDescription": "VN1 message requested but lost arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN1; SNP on AD", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP", - "PerPkg": "1", - "PublicDescription": "VN1 message requested but lost arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN1; NCB on BL", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB", - "PerPkg": "1", - "PublicDescription": "VN1 message requested but lost arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN1; NCS on BL", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS", - "PerPkg": "1", - "PublicDescription": "VN1 message requested but lost arbitration; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN1; RSP on BL", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP", - "PerPkg": "1", - "PublicDescription": "VN1 message requested but lost arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Lost Arb for VN1; WB on BL", - "EventCode": "0x4C", - "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB", - "PerPkg": "1", - "PublicDescription": "VN1 message requested but lost arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Arb Miscellaneous; AD, BL Parallel Win", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN", - "PerPkg": "1", - "PublicDescription": "AD and BL messages won arbitration concurrently / in parallel", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN0", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0", - "PerPkg": "1", - "PublicDescription": "Arbitration stage made no progress on pending ad vn0 messages because slotting stage cannot accept new message", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD VN1", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1", - "PerPkg": "1", - "PublicDescription": "Arbitration stage made no progress on pending ad vn1 messages because slotting stage cannot accept new message", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN0", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0", - "PerPkg": "1", - "PublicDescription": "Arbitration stage made no progress on pending bl vn0 messages because slotting stage cannot accept new message", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL VN1", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1", - "PerPkg": "1", - "PublicDescription": "Arbitration stage made no progress on pending bl vn1 messages because slotting stage cannot accept new message", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN0", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN0", - "PerPkg": "1", - "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win to vn0, delaying vn1 win, because vn0 offered parallel ad/bl", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN1", - "EventCode": "0x4D", - "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN1", - "PerPkg": "1", - "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win to vn1, delaying vn0 win, because vn1 offered parallel ad/bl", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN0; REQ on AD", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_REQ", - "PerPkg": "1", - "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN0; RSP on AD", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_RSP", - "PerPkg": "1", - "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN0; SNP on AD", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_SNP", - "PerPkg": "1", - "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN0; NCB on BL", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCB", - "PerPkg": "1", - "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN0; NCS on BL", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCS", - "PerPkg": "1", - "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN0; RSP on BL", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_RSP", - "PerPkg": "1", - "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN0; WB on BL", - "EventCode": "0x49", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_WB", - "PerPkg": "1", - "PublicDescription": "VN0 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN1; REQ on AD", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_REQ", - "PerPkg": "1", - "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN1; RSP on AD", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_RSP", - "PerPkg": "1", - "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN1; SNP on AD", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_SNP", - "PerPkg": "1", - "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN1; NCB on BL", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCB", - "PerPkg": "1", - "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN1; NCS on BL", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCS", - "PerPkg": "1", - "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN1; RSP on BL", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_RSP", - "PerPkg": "1", - "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Can't Arb for VN1; WB on BL", - "EventCode": "0x4A", - "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_WB", - "PerPkg": "1", - "PublicDescription": "VN1 message was not able to request arbitration while some other message won arbitration; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN0; REQ on AD", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_REQ", - "PerPkg": "1", - "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN0; RSP on AD", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_RSP", - "PerPkg": "1", - "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN0; SNP on AD", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_SNP", - "PerPkg": "1", - "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN0; NCB on BL", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCB", - "PerPkg": "1", - "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN0; NCS on BL", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCS", - "PerPkg": "1", - "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN0; RSP on BL", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_RSP", - "PerPkg": "1", - "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN0; WB on BL", - "EventCode": "0x47", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_WB", - "PerPkg": "1", - "PublicDescription": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN1; REQ on AD", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_REQ", - "PerPkg": "1", - "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN1; RSP on AD", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_RSP", - "PerPkg": "1", - "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN1; SNP on AD", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_SNP", - "PerPkg": "1", - "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN1; NCB on BL", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCB", - "PerPkg": "1", - "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN1; NCS on BL", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCS", - "PerPkg": "1", - "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN1; RSP on BL", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_RSP", - "PerPkg": "1", - "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "No Credits to Arb for VN1; WB on BL", - "EventCode": "0x48", - "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_WB", - "PerPkg": "1", - "PublicDescription": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on BL Arb", - "EventCode": "0x40", - "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB", - "PerPkg": "1", - "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while bl message is in arbitration", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on Idle", - "EventCode": "0x40", - "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE", - "PerPkg": "1", - "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to slot 0 of independent flit while pipeline is idle", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 1", - "EventCode": "0x40", - "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT", - "PerPkg": "1", - "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 1 while merging with bl message in same flit", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 2", - "EventCode": "0x40", - "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT", - "PerPkg": "1", - "PublicDescription": "Number of times message is bypassed around the Ingress Queue; AD is taking bypass to flit slot 2 while merging with bl message in same flit", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message lost contest for flit; REQ on AD", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message lost contest for flit; RSP on AD", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message lost contest for flit; SNP on AD", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_SNP", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message lost contest for flit; NCB on BL", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message lost contest for flit; NCS on BL", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message lost contest for flit; RSP on BL", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message lost contest for flit; WB on BL", - "EventCode": "0x50", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_WB", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message lost contest for flit; REQ on AD", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message lost contest for flit; RSP on AD", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message lost contest for flit; SNP on AD", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_SNP", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message lost contest for flit; NCB on BL", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message lost contest for flit; NCS on BL", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message lost contest for flit; RSP on BL", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message lost contest for flit; WB on BL", - "EventCode": "0x51", - "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_WB", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Miscellaneous Credit Events; Any In BGF FIFO", - "EventCode": "0x60", - "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO", - "PerPkg": "1", - "PublicDescription": "Indication that at least one packet (flit) is in the bgf (fifo only)", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Miscellaneous Credit Events; Any in BGF Path", - "EventCode": "0x60", - "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH", - "PerPkg": "1", - "PublicDescription": "Indication that at least one packet (flit) is in the bgf path (i.e. pipe to fifo)", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Miscellaneous Credit Events; No D2K For Arb", - "EventCode": "0x60", - "EventName": "UNC_M3UPI_RxC_CRD_MISC.NO_D2K_FOR_ARB", - "PerPkg": "1", - "PublicDescription": "VN0 or VN1 BL RSP message was blocked from arbitration request due to lack of D2K CMP credits", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Credit Occupancy; D2K Credits", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD", - "PerPkg": "1", - "PublicDescription": "D2K completion fifo credit occupancy (credits in use), accumulated across all cycles", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Credit Occupancy; Packets in BGF FIFO", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO", - "PerPkg": "1", - "PublicDescription": "Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Credit Occupancy; Packets in BGF Path", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH", - "PerPkg": "1", - "PublicDescription": "Occupancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e. pipe to fifo or fifo)", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Credit Occupancy", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO", - "PerPkg": "1", - "PublicDescription": "count of bl messages in pump-1-pending state, in completion fifo only", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Credit Occupancy", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL", - "PerPkg": "1", - "PublicDescription": "count of bl messages in pump-1-pending state, in marker table and in fifo", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Credit Occupancy; Transmit Credits", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD", - "PerPkg": "1", - "PublicDescription": "Link layer transmit queue credit occupancy (credits in use), accumulated across all cycles", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Credit Occupancy; VNA In Use", - "EventCode": "0x61", - "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE", - "PerPkg": "1", - "PublicDescription": "Remote UPI VNA credit occupancy (number of credits in use), accumulated across all cycles", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL", - "EventCode": "0x43", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles when the UPI Ingress is not empty. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; REQ on AD", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on AD", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; SNP on AD", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCB on BL", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; NCS on BL", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; RSP on BL", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Empty; WB on BL", - "EventCode": "0x44", - "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Data Flit Not Sent; All", - "EventCode": "0x57", - "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.ALL", - "PerPkg": "1", - "PublicDescription": "Data flit is ready for transmission but could not be sent", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Data Flit Not Sent; No BGF Credits", - "EventCode": "0x57", - "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_BGF", - "PerPkg": "1", - "PublicDescription": "Data flit is ready for transmission but could not be sent", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Data Flit Not Sent; No TxQ Credits", - "EventCode": "0x57", - "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_TXQ", - "PerPkg": "1", - "PublicDescription": "Data flit is ready for transmission but could not be sent", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 0", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT", - "PerPkg": "1", - "PublicDescription": "generating bl data flit sequence; waiting for data pump 0", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Generating BL Data Flit Sequence", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT", - "PerPkg": "1", - "PublicDescription": "pump-1-pending logic is at capacity (pending table plus completion fifo at limit)", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Generating BL Data Flit Sequence", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY", - "PerPkg": "1", - "PublicDescription": "pump-1-pending logic is tracking at least one message", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Generating BL Data Flit Sequence", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL", - "PerPkg": "1", - "PublicDescription": "pump-1-pending completion fifo is full", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Generating BL Data Flit Sequence", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0", - "PerPkg": "1", - "PublicDescription": "pump-1-pending logic is at or near capacity, such that pump-0-only bl messages are getting stalled in slotting stage", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Generating BL Data Flit Sequence", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO", - "PerPkg": "1", - "PublicDescription": "a bl message finished but is in limbo and moved to pump-1-pending logic", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pump 1", - "EventCode": "0x59", - "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT", - "PerPkg": "1", - "PublicDescription": "generating bl data flit sequence; waiting for data pump 1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC", - "EventCode": "0x5A", - "EventName": "UNC_M3UPI_RxC_FLITS_MISC", - "PerPkg": "1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sent Header Flit; One Message", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG", - "PerPkg": "1", - "PublicDescription": "One message in flit; VNA or non-VNA flit", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sent Header Flit; One Message in non-VNA", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG_VNX", - "PerPkg": "1", - "PublicDescription": "One message in flit; non-VNA flit", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sent Header Flit; Two Messages", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SENT.2_MSGS", - "PerPkg": "1", - "PublicDescription": "Two messages in flit; VNA flit", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sent Header Flit; Three Messages", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SENT.3_MSGS", - "PerPkg": "1", - "PublicDescription": "Three messages in flit; VNA flit", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sent Header Flit", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_1", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sent Header Flit", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_2", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Sent Header Flit", - "EventCode": "0x56", - "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_3", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Slotting BL Message Into Header Flit; All", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Slotting BL Message Into Header Flit; Needs Data Flit", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA", - "PerPkg": "1", - "PublicDescription": "BL message requires data flit sequence", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 0", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT", - "PerPkg": "1", - "PublicDescription": "Waiting for header pump 0", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ", - "PerPkg": "1", - "PublicDescription": "Header pump 1 is not required for flit", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Bubble", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE", - "PerPkg": "1", - "PublicDescription": "Header pump 1 is not required for flit but flit transmission delayed", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Slotting BL Message Into Header Flit; Don't Need Pump 1 - Not Avail", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL", - "PerPkg": "1", - "PublicDescription": "Header pump 1 is not required for flit and not available", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Slotting BL Message Into Header Flit; Wait on Pump 1", - "EventCode": "0x58", - "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT", - "PerPkg": "1", - "PublicDescription": "Waiting for header pump 1", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 1; Accumulate", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM", - "PerPkg": "1", - "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting control state machine is in any accumulate state; multi-message flit may be assembled over multiple cycles", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 1; Accumulate Ready", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ", - "PerPkg": "1", - "PublicDescription": "Events related to Header Flit Generation - Set 1; header flit slotting control state machine is in accum_ready state; flit is ready to send but transmission is blocked; more messages may be slotted into flit", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 1; Accumulate Wasted", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED", - "PerPkg": "1", - "PublicDescription": "Events related to Header Flit Generation - Set 1; Flit is being assembled over multiple cycles, but no additional message is being slotted into flit in current cycle; accumulate cycle is wasted", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Blocked", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED", - "PerPkg": "1", - "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting entered run-ahead state; new header flit is started while transmission of prior, fully assembled flit is blocked", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Message", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG", - "PerPkg": "1", - "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit slotting is in run-ahead to start new flit, and message is actually slotted into new flit", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 1; Parallel Ok", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR", - "PerPkg": "1", - "PublicDescription": "Events related to Header Flit Generation - Set 1; New header flit construction may proceed in parallel with data flit sequence", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 1; Parallel Flit Finished", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_FLIT", - "PerPkg": "1", - "PublicDescription": "Events related to Header Flit Generation - Set 1; Header flit finished assembly in parallel with data flit sequence", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 1; Parallel Message", - "EventCode": "0x53", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_MSG", - "PerPkg": "1", - "PublicDescription": "Events related to Header Flit Generation - Set 1; Message is slotted into header flit in parallel with data flit sequence", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall", - "EventCode": "0x54", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL", - "PerPkg": "1", - "PublicDescription": "Events related to Header Flit Generation - Set 2; Rate-matching stall injected", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall - No Message", - "EventCode": "0x54", - "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG", - "PerPkg": "1", - "PublicDescription": "Events related to Header Flit Generation - Set 2; Rate matching stall injected, but no additional message slotted during stall cycle", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Header Not Sent; All", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ALL", - "PerPkg": "1", - "PublicDescription": "header flit is ready for transmission but could not be sent", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Header Not Sent; No BGF Credits", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_CRD", - "PerPkg": "1", - "PublicDescription": "header flit is ready for transmission but could not be sent; No BGF credits available", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Header Not Sent; No BGF Credits + No Extra Message Slotted", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_NO_MSG", - "PerPkg": "1", - "PublicDescription": "header flit is ready for transmission but could not be sent; No BGF credits available; no additional message slotted into flit", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Header Not Sent; No TxQ Credits", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_CRD", - "PerPkg": "1", - "PublicDescription": "header flit is ready for transmission but could not be sent; No TxQ credits available", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Header Not Sent; No TxQ Credits + No Extra Message Slotted", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_NO_MSG", - "PerPkg": "1", - "PublicDescription": "header flit is ready for transmission but could not be sent; No TxQ credits available; no additional message slotted into flit", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Header Not Sent; Sent - One Slot Taken", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ONE_TAKEN", - "PerPkg": "1", - "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with only one slot taken (two slots free)", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Header Not Sent; Sent - Three Slots Taken", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.THREE_TAKEN", - "PerPkg": "1", - "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with three slots taken (no slots free)", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Header Not Sent; Sent - Two Slots Taken", - "EventCode": "0x55", - "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.TWO_TAKEN", - "PerPkg": "1", - "PublicDescription": "header flit is ready for transmission but could not be sent; sending header flit with only two slots taken (one slots free)", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Message Held; Can't Slot AD", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD", - "PerPkg": "1", - "PublicDescription": "some AD message could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1})", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Message Held; Can't Slot BL", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL", - "PerPkg": "1", - "PublicDescription": "some BL message could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1})", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Message Held; Parallel AD Lost", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_AD_LOST", - "PerPkg": "1", - "PublicDescription": "some AD message lost contest for slot 0 (logical OR of all AD events under INGR_SLOT_LOST_MC_VN{0,1})", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Message Held; Parallel Attempt", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT", - "PerPkg": "1", - "PublicDescription": "ad and bl messages attempted to slot into the same flit in parallel", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Message Held; Parallel BL Lost", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_BL_LOST", - "PerPkg": "1", - "PublicDescription": "some BL message lost contest for slot 0 (logical OR of all BL events under INGR_SLOT_LOST_MC_VN{0,1})", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Message Held; Parallel Success", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS", - "PerPkg": "1", - "PublicDescription": "ad and bl messages were actually slotted into the same flit in paralle", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Message Held; VN0", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_HELD.VN0", - "PerPkg": "1", - "PublicDescription": "vn0 message(s) that couldn't be slotted into last vn0 flit are held in slotting stage while processing vn1 flit", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Message Held; VN1", - "EventCode": "0x52", - "EventName": "UNC_M3UPI_RxC_HELD.VN1", - "PerPkg": "1", - "PublicDescription": "vn1 message(s) that couldn't be slotted into last vn1 flit are held in slotting stage while processing vn0 flit", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; REQ on AD", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on AD", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; SNP on AD", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCB on BL", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCS on BL", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP on BL", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; WB on BL", - "EventCode": "0x41", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; REQ on AD", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on AD", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; SNP on AD", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCB on BL", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCS on BL", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP on BL", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; WB on BL", - "EventCode": "0x42", - "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the UPI VN1 Ingress. This tracks one of the three rings that are used by the UPI agent. This can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; REQ on AD", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on AD", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; SNP on AD", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCB on BL", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCS on BL", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP on BL", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; WB on BL", - "EventCode": "0x45", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; REQ on AD", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on AD", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; SNP on AD", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCB on BL", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCS on BL", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP on BL", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; WB on BL", - "EventCode": "0x46", - "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB", - "PerPkg": "1", - "PublicDescription": "Accumulates the occupancy of a given UPI VN1 Ingress queue in each cycle. This tracks one of the three ring Ingress buffers. This can be used with the UPI VN1 Ingress Not Empty event to calculate average occupancy or the UPI VN1 Ingress Allocations event in order to calculate average queuing latency.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message can't slot into flit; REQ on AD", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message can't slot into flit; RSP on AD", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message can't slot into flit; SNP on AD", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message can't slot into flit; NCB on BL", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message can't slot into flit; NCS on BL", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message can't slot into flit; RSP on BL", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 message can't slot into flit; WB on BL", - "EventCode": "0x4E", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message can't slot into flit; REQ on AD", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message can't slot into flit; RSP on AD", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message can't slot into flit; SNP on AD", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message can't slot into flit; NCB on BL", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message can't slot into flit; NCS on BL", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Non-Coherent Standard (NCS) messages on BL.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message can't slot into flit; RSP on BL", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 message can't slot into flit; WB on BL", - "EventCode": "0x4F", - "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB", - "PerPkg": "1", - "PublicDescription": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "SMI3 Prefetch Messages; Lost Arbitration", - "EventCode": "0x62", - "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARB_LOST", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "SMI3 Prefetch Messages; Arrived", - "EventCode": "0x62", - "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARRIVED", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "SMI3 Prefetch Messages; Dropped - Old", - "EventCode": "0x62", - "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_OLD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "SMI3 Prefetch Messages; Dropped - Wrap", - "EventCode": "0x62", - "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_WRAP", - "PerPkg": "1", - "PublicDescription": "Dropped because it was overwritten by new message while prefetch queue was full", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "SMI3 Prefetch Messages; Slotted", - "EventCode": "0x62", - "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.SLOTTED", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Remote VNA Credits; Any In Use", - "EventCode": "0x5B", - "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE", - "PerPkg": "1", - "PublicDescription": "At least one remote vna credit is in use", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Remote VNA Credits; Corrected", - "EventCode": "0x5B", - "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED", - "PerPkg": "1", - "PublicDescription": "Number of remote vna credits corrected (local return) per cycle", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Remote VNA Credits; Level < 1", - "EventCode": "0x5B", - "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1", - "PerPkg": "1", - "PublicDescription": "Remote vna credit level is less than 1 (i.e. no vna credits available)", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Remote VNA Credits; Level < 4", - "EventCode": "0x5B", - "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4", - "PerPkg": "1", - "PublicDescription": "Remote vna credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Remote VNA Credits; Level < 5", - "EventCode": "0x5B", - "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5", - "PerPkg": "1", - "PublicDescription": "Remote vna credit level is less than 5; parallel ad/bl arb on vna not possible", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Remote VNA Credits; Used", - "EventCode": "0x5B", - "EventName": "UNC_M3UPI_RxC_VNA_CRD.USED", - "PerPkg": "1", - "PublicDescription": "Number of remote vna credits consumed per cycle", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation; AD - Bounce", - "EventCode": "0xB4", - "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation; AD - Credit", - "EventCode": "0xB4", - "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation; BL - Bounce", - "EventCode": "0xB4", - "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation; BL - Credit", - "EventCode": "0xB4", - "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", - "EventCode": "0xB2", - "EventName": "UNC_M3UPI_RxR_BYPASS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Bypass; AD - Credit", - "EventCode": "0xB2", - "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", - "EventCode": "0xB2", - "EventName": "UNC_M3UPI_RxR_BYPASS.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", - "EventCode": "0xB2", - "EventName": "UNC_M3UPI_RxR_BYPASS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Bypass; BL - Credit", - "EventCode": "0xB2", - "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", - "EventCode": "0xB2", - "EventName": "UNC_M3UPI_RxR_BYPASS.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the CMS Ingress", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation; AD - Bounce", - "EventCode": "0xB3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation; AD - Credit", - "EventCode": "0xB3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation; AK - Bounce", - "EventCode": "0xB3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation; BL - Bounce", - "EventCode": "0xB3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation; BL - Credit", - "EventCode": "0xB3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation; IFV - Credit", - "EventCode": "0xB3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Injection Starvation; IV - Bounce", - "EventCode": "0xB3", - "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", - "EventCode": "0xB1", - "EventName": "UNC_M3UPI_RxR_INSERTS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Allocations; AD - Credit", - "EventCode": "0xB1", - "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", - "EventCode": "0xB1", - "EventName": "UNC_M3UPI_RxR_INSERTS.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", - "EventCode": "0xB1", - "EventName": "UNC_M3UPI_RxR_INSERTS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Allocations; BL - Credit", - "EventCode": "0xB1", - "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", - "EventCode": "0xB1", - "EventName": "UNC_M3UPI_RxR_INSERTS.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", - "EventCode": "0xB0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", - "EventCode": "0xB0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", - "EventCode": "0xB0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", - "EventCode": "0xB0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", - "EventCode": "0xB0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", - "EventCode": "0xB0", - "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 0", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 1", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 2", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 3", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 4", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For Transgress 5", - "EventCode": "0xD0", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 0", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 1", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 2", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 3", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 4", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For Transgress 5", - "EventCode": "0xD2", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 0", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 1", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 2", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 3", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 4", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For Transgress 5", - "EventCode": "0xD4", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 0", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 1", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 2", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 3", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 4", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For Transgress 5", - "EventCode": "0xD6", - "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for AD; VN0 REQ Messages", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ", - "PerPkg": "1", - "PublicDescription": "AD arb but no win; arb request asserted but not won", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for AD; VN0 RSP Messages", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "AD arb but no win; arb request asserted but not won", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for AD; VN0 SNP Messages", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "AD arb but no win; arb request asserted but not won", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for AD; VN0 WB Messages", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB", - "PerPkg": "1", - "PublicDescription": "AD arb but no win; arb request asserted but not won", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for AD; VN1 REQ Messages", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ", - "PerPkg": "1", - "PublicDescription": "AD arb but no win; arb request asserted but not won", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for AD; VN1 RSP Messages", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "AD arb but no win; arb request asserted but not won", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for AD; VN1 SNP Messages", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "AD arb but no win; arb request asserted but not won", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for AD; VN1 WB Messages", - "EventCode": "0x30", - "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB", - "PerPkg": "1", - "PublicDescription": "AD arb but no win; arb request asserted but not won", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD FlowQ Bypass", - "EventCode": "0x2C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0", - "PerPkg": "1", - "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD FlowQ Bypass", - "EventCode": "0x2C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1", - "PerPkg": "1", - "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD FlowQ Bypass", - "EventCode": "0x2C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2", - "PerPkg": "1", - "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD FlowQ Bypass", - "EventCode": "0x2C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP", - "PerPkg": "1", - "PublicDescription": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Not Empty; VN0 REQ Messages", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Not Empty; VN0 RSP Messages", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Not Empty; VN0 SNP Messages", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Not Empty; VN0 WB Messages", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Not Empty; VN1 REQ Messages", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Not Empty; VN1 RSP Messages", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Not Empty; VN1 SNP Messages", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Not Empty; VN1 WB Messages", - "EventCode": "0x27", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB", - "PerPkg": "1", - "PublicDescription": "Number of cycles the AD Egress queue is Not Empty", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Inserts; VN0 REQ Messages", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Inserts; VN0 RSP Messages", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Inserts; VN0 SNP Messages", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Inserts; VN0 WB Messages", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Inserts; VN1 REQ Messages", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Inserts; VN1 RSP Messages", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Inserts; VN1 SNP Messages", - "EventCode": "0x2D", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Occupancy; VN0 REQ Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Occupancy; VN0 RSP Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Occupancy; VN0 SNP Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Occupancy; VN0 WB Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Occupancy; VN1 REQ Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Occupancy; VN1 RSP Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AD Flow Q Occupancy; VN1 SNP Messages", - "EventCode": "0x1C", - "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Number of Snoop Targets; CHA on VN0", - "EventCode": "0x3C", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_CHA", - "PerPkg": "1", - "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to CHA", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN0", - "EventCode": "0x3C", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_NON_IDLE", - "PerPkg": "1", - "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of non-idle cycles in issuing Vn0 Snpf", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN0", - "EventCode": "0x3C", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI0", - "PerPkg": "1", - "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to peer UPI0", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN0", - "EventCode": "0x3C", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI1", - "PerPkg": "1", - "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN0 Snpf to peer UPI1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Number of Snoop Targets; CHA on VN1", - "EventCode": "0x3C", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_CHA", - "PerPkg": "1", - "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to CHA", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Number of Snoop Targets; Non Idle cycles on VN1", - "EventCode": "0x3C", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_NON_IDLE", - "PerPkg": "1", - "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of non-idle cycles in issuing Vn1 Snpf", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN1", - "EventCode": "0x3C", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI0", - "PerPkg": "1", - "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to peer UPI0", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN1", - "EventCode": "0x3C", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI1", - "PerPkg": "1", - "PublicDescription": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency; Number of VN1 Snpf to peer UPI1", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Snoop Arbitration; FlowQ Won", - "EventCode": "0x3D", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_NONSNP", - "PerPkg": "1", - "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn0", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won", - "EventCode": "0x3D", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_VN2SNP", - "PerPkg": "1", - "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ Vn0 SnpF issued when SnpF pending on Vn1", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Snoop Arbitration; FlowQ Won", - "EventCode": "0x3D", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_NONSNP", - "PerPkg": "1", - "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ txn issued when SnpF pending on Vn1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won", - "EventCode": "0x3D", - "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_VN0SNP", - "PerPkg": "1", - "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ Vn1 SnpF issued when SnpF pending on Vn0", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 REQ Messages", - "EventCode": "0x34", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_REQ", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 SNP Messages", - "EventCode": "0x34", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - Credit Available; VN0 WB Messages", - "EventCode": "0x34", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_WB", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 REQ Messages", - "EventCode": "0x34", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_REQ", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 SNP Messages", - "EventCode": "0x34", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - Credit Available; VN1 WB Messages", - "EventCode": "0x34", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_WB", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request with prior cycle credit check complete and credit avail", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - New Message; VN0 REQ Messages", - "EventCode": "0x33", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_REQ", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - New Message; VN0 SNP Messages", - "EventCode": "0x33", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - New Message; VN0 WB Messages", - "EventCode": "0x33", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_WB", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - New Message; VN1 REQ Messages", - "EventCode": "0x33", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_REQ", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - New Message; VN1 SNP Messages", - "EventCode": "0x33", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - New Message; VN1 WB Messages", - "EventCode": "0x33", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_WB", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - No Credit; VN0 REQ Messages", - "EventCode": "0x32", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_REQ", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - No Credit; VN0 RSP Messages", - "EventCode": "0x32", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - No Credit; VN0 SNP Messages", - "EventCode": "0x32", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - No Credit; VN0 WB Messages", - "EventCode": "0x32", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_WB", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - No Credit; VN1 REQ Messages", - "EventCode": "0x32", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_REQ", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - No Credit; VN1 RSP Messages", - "EventCode": "0x32", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - No Credit; VN1 SNP Messages", - "EventCode": "0x32", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD - No Credit; VN1 WB Messages", - "EventCode": "0x32", - "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_WB", - "PerPkg": "1", - "PublicDescription": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AK Flow Q Inserts", - "EventCode": "0x2F", - "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS", - "PerPkg": "1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "AK Flow Q Occupancy", - "EventCode": "0x1E", - "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY", - "PerPkg": "1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL; VN0 NCB Messages", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB", - "PerPkg": "1", - "PublicDescription": "BL arb but no win; arb request asserted but not won", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL; VN0 NCS Messages", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS", - "PerPkg": "1", - "PublicDescription": "BL arb but no win; arb request asserted but not won", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL; VN0 RSP Messages", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "BL arb but no win; arb request asserted but not won", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL; VN0 WB Messages", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB", - "PerPkg": "1", - "PublicDescription": "BL arb but no win; arb request asserted but not won", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL; VN1 NCS Messages", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB", - "PerPkg": "1", - "PublicDescription": "BL arb but no win; arb request asserted but not won", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL; VN1 NCB Messages", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS", - "PerPkg": "1", - "PublicDescription": "BL arb but no win; arb request asserted but not won", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL; VN1 RSP Messages", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "BL arb but no win; arb request asserted but not won", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Failed ARB for BL; VN1 WB Messages", - "EventCode": "0x35", - "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB", - "PerPkg": "1", - "PublicDescription": "BL arb but no win; arb request asserted but not won", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Not Empty; VN0 REQ Messages", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Not Empty; VN0 RSP Messages", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Not Empty; VN0 SNP Messages", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Not Empty; VN0 WB Messages", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Not Empty; VN1 REQ Messages", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Not Empty; VN1 RSP Messages", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Not Empty; VN1 SNP Messages", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Not Empty; VN1 WB Messages", - "EventCode": "0x28", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB", - "PerPkg": "1", - "PublicDescription": "Number of cycles the BL Egress queue is Not Empty", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Inserts; VN0 RSP Messages", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Inserts; VN0 WB Messages", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Inserts; VN0 NCS Messages", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Inserts; VN0 NCB Messages", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Inserts; VN1 RSP Messages", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Inserts; VN1 WB Messages", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Inserts; VN1_NCB Messages", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Inserts; VN1_NCS Messages", - "EventCode": "0x2E", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB", - "PerPkg": "1", - "PublicDescription": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency. Only a single FlowQ queue can be tracked at any given time. It is not possible to filter based on direction or polarity.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy; VN0 NCB Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy; VN0 NCS Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy; VN0 RSP Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy; VN0 WB Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy; VN1_NCS Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy; VN1_NCB Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy; VN1 RSP Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "BL Flow Q Occupancy; VN1 WB Messages", - "EventCode": "0x1D", - "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB Messages", - "EventCode": "0x38", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCB", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for BL - New Message; VN0 NCS Messages", - "EventCode": "0x38", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCS", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB Messages", - "EventCode": "0x38", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_WB", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for BL - New Message; VN1 WB Messages", - "EventCode": "0x38", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCB", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for BL - New Message; VN1 NCB Messages", - "EventCode": "0x38", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCS", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for BL - New Message; VN1 RSP Messages", - "EventCode": "0x38", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_WB", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCB Messages", - "EventCode": "0x37", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCB", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 NCS Messages", - "EventCode": "0x37", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCS", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 RSP Messages", - "EventCode": "0x37", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN0 WB Messages", - "EventCode": "0x37", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_WB", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCS Messages", - "EventCode": "0x37", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCB", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 NCB Messages", - "EventCode": "0x37", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCS", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x80", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 RSP Messages", - "EventCode": "0x37", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN1 WB Messages", - "EventCode": "0x37", - "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_WB", - "PerPkg": "1", - "PublicDescription": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", - "EventCode": "0x9D", - "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", - "EventCode": "0x9D", - "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", - "EventCode": "0x9D", - "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", - "EventCode": "0x9D", - "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", - "EventCode": "0x9D", - "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", - "EventCode": "0x9F", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", - "EventCode": "0x9F", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", - "EventCode": "0x9F", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", - "EventCode": "0x9F", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", - "EventCode": "0x9F", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", - "EventCode": "0x9F", - "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Bounce", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AD - Credit", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; AK - Bounce", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Bounce", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; BL - Credit", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; IV - Bounce", - "EventCode": "0x96", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Bounce", - "EventCode": "0x97", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AD - Credit", - "EventCode": "0x97", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; AK - Bounce", - "EventCode": "0x97", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Bounce", - "EventCode": "0x97", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; BL - Credit", - "EventCode": "0x97", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty; IV - Bounce", - "EventCode": "0x97", - "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", - "EventCode": "0x95", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", - "EventCode": "0x95", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", - "EventCode": "0x95", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", - "EventCode": "0x95", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", - "EventCode": "0x95", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", - "EventCode": "0x95", - "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", - "EventCode": "0x99", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", - "EventCode": "0x99", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", - "EventCode": "0x99", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", - "EventCode": "0x99", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", - "EventCode": "0x99", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", - "EventCode": "0x99", - "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", - "EventCode": "0x94", - "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; AD - Bounce", - "EventCode": "0x9B", - "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; AK - Bounce", - "EventCode": "0x9B", - "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; BL - Bounce", - "EventCode": "0x9B", - "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation; IV - Bounce", - "EventCode": "0x9B", - "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV_BNC", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", - "EventCode": "0x9E", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", - "EventCode": "0x9E", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", - "EventCode": "0x9E", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", - "EventCode": "0x9E", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", - "EventCode": "0x9E", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", - "EventCode": "0x9E", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical ADS Used; IV", - "EventCode": "0x9E", - "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV", - "PerPkg": "1", - "PublicDescription": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", - "EventCode": "0x92", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.IV", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AD - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; AK - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; BL - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty; IV", - "EventCode": "0x93", - "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.IV", - "PerPkg": "1", - "PublicDescription": "Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Allocations; IV", - "EventCode": "0x91", - "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.IV", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs; IV", - "EventCode": "0x98", - "EventName": "UNC_M3UPI_TxR_VERT_NACK.IV", - "PerPkg": "1", - "PublicDescription": "Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy; IV", - "EventCode": "0x90", - "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.IV", - "PerPkg": "1", - "PublicDescription": "Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AD - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; AK - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; BL - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", - "EventCode": "0x9A", - "EventName": "UNC_M3UPI_TxR_VERT_STARVED.IV", - "PerPkg": "1", - "PublicDescription": "Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 AD Credits Empty; VN0 REQ Messages", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 AD Credits Empty; VN0 RSP Messages", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 AD Credits Empty; VN0 SNP Messages", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 AD Credits Empty; VN1 REQ Messages", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 AD Credits Empty; VN1 RSP Messages", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 AD Credits Empty; VN1 SNP Messages", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 AD Credits Empty; VNA", - "EventCode": "0x20", - "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPIs on the AD Ring", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 BL Credits Empty; VN0 RSP Messages", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 BL Credits Empty; VN0 REQ Messages", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 BL Credits Empty; VN0 SNP Messages", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 BL Credits Empty; VN1 RSP Messages", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 BL Credits Empty; VN1 REQ Messages", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 BL Credits Empty; VN1 SNP Messages", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "UMask": "0x40", - "Unit": "M3UPI" - }, - { - "BriefDescription": "UPI0 BL Credits Empty; VNA", - "EventCode": "0x21", - "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA", - "PerPkg": "1", - "PublicDescription": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Prefetches generated by the flow control queue of the M3UPI unit.", - "EventCode": "0x29", - "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN", - "PerPkg": "1", - "PublicDescription": "Count cases where flow control queue that sits between the Intel(R) Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller)", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AD Ring In Use; Down and Even", - "EventCode": "0xA6", - "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AD Ring In Use; Down and Odd", - "EventCode": "0xA6", - "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AD Ring In Use; Up and Even", - "EventCode": "0xA6", - "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AD Ring In Use; Up and Odd", - "EventCode": "0xA6", - "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AK Ring In Use; Down and Even", - "EventCode": "0xA8", - "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AK Ring In Use; Down and Odd", - "EventCode": "0xA8", - "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AK Ring In Use; Up and Even", - "EventCode": "0xA8", - "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical AK Ring In Use; Up and Odd", - "EventCode": "0xA8", - "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical BL Ring in Use; Down and Even", - "EventCode": "0xAA", - "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical BL Ring in Use; Down and Odd", - "EventCode": "0xAA", - "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical BL Ring in Use; Up and Even", - "EventCode": "0xAA", - "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical BL Ring in Use; Up and Odd", - "EventCode": "0xAA", - "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical IV Ring in Use; Down", - "EventCode": "0xAC", - "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "Vertical IV Ring in Use; Up", - "EventCode": "0xAC", - "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP", - "PerPkg": "1", - "PublicDescription": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Credit Used; WB on BL", - "EventCode": "0x5C", - "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Credit Used; NCB on BL", - "EventCode": "0x5C", - "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Credit Used; REQ on AD", - "EventCode": "0x5C", - "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Credit Used; RSP on AD", - "EventCode": "0x5C", - "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Credit Used; SNP on AD", - "EventCode": "0x5C", - "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 Credit Used; RSP on BL", - "EventCode": "0x5C", - "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB", - "PerPkg": "1", - "PublicDescription": "Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 No Credits; WB on BL", - "EventCode": "0x5E", - "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB", - "PerPkg": "1", - "PublicDescription": "Number of Cycles there were no VN0 Credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 No Credits; NCB on BL", - "EventCode": "0x5E", - "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS", - "PerPkg": "1", - "PublicDescription": "Number of Cycles there were no VN0 Credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 No Credits; REQ on AD", - "EventCode": "0x5E", - "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ", - "PerPkg": "1", - "PublicDescription": "Number of Cycles there were no VN0 Credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 No Credits; RSP on AD", - "EventCode": "0x5E", - "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP", - "PerPkg": "1", - "PublicDescription": "Number of Cycles there were no VN0 Credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 No Credits; SNP on AD", - "EventCode": "0x5E", - "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP", - "PerPkg": "1", - "PublicDescription": "Number of Cycles there were no VN0 Credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN0 No Credits; RSP on BL", - "EventCode": "0x5E", - "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB", - "PerPkg": "1", - "PublicDescription": "Number of Cycles there were no VN0 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Credit Used; WB on BL", - "EventCode": "0x5D", - "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Credit Used; NCB on BL", - "EventCode": "0x5D", - "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Credit Used; REQ on AD", - "EventCode": "0x5D", - "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Credit Used; RSP on AD", - "EventCode": "0x5D", - "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Credit Used; SNP on AD", - "EventCode": "0x5D", - "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 Credit Used; RSP on BL", - "EventCode": "0x5D", - "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB", - "PerPkg": "1", - "PublicDescription": "Number of times a VN1 credit was used on the WB message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 No Credits; WB on BL", - "EventCode": "0x5F", - "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB", - "PerPkg": "1", - "PublicDescription": "Number of Cycles there were no VN1 Credits; Data Response (WB) messages on BL. WB is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using WB.", - "UMask": "0x10", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 No Credits; NCB on BL", - "EventCode": "0x5F", - "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS", - "PerPkg": "1", - "PublicDescription": "Number of Cycles there were no VN1 Credits; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to transmit data without coherency. For example, non-coherent read data returns.", - "UMask": "0x20", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 No Credits; REQ on AD", - "EventCode": "0x5F", - "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ", - "PerPkg": "1", - "PublicDescription": "Number of Cycles there were no VN1 Credits; Home (REQ) messages on AD. REQ is generally used to send requests, request responses, and snoop responses.", - "UMask": "0x1", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 No Credits; RSP on AD", - "EventCode": "0x5F", - "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP", - "PerPkg": "1", - "PublicDescription": "Number of Cycles there were no VN1 Credits; Response (RSP) messages on AD. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x4", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 No Credits; SNP on AD", - "EventCode": "0x5F", - "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP", - "PerPkg": "1", - "PublicDescription": "Number of Cycles there were no VN1 Credits; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", - "UMask": "0x2", - "Unit": "M3UPI" - }, - { - "BriefDescription": "VN1 No Credits; RSP on BL", - "EventCode": "0x5F", - "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB", - "PerPkg": "1", - "PublicDescription": "Number of Cycles there were no VN1 Credits; Response (RSP) messages on BL. RSP packets are used to transmit a variety of protocol flits including grants and completions (CMP).", - "UMask": "0x8", - "Unit": "M3UPI" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_M2M_TxC_BL.DRS_UPI", - "Deprecated": "1", - "EventCode": "0x40", - "EventName": "UNC_NoUnit_TxC_BL.DRS_UPI", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Clocks of the Intel(R) Ultra Path Interconnect (UPI)", - "EventCode": "0x1", - "EventName": "UNC_UPI_CLOCKTICKS", - "PerPkg": "1", - "PublicDescription": "Counts clockticks of the fixed frequency clock controlling the Intel(R) Ultra Path Interconnect (UPI). This clock runs at1/8th the 'GT/s' speed of the UPI link. For example, a 9.6GT/s link will have a fixed Frequency of 1.2 Ghz.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Data Response packets that go direct to core", - "EventCode": "0x12", - "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C", - "PerPkg": "1", - "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to core bypassing the CHA.", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_DIRECT_ATTEMPTS.D2U", - "Deprecated": "1", - "EventCode": "0x12", - "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Data Response packets that go direct to Intel(R) UPI", - "EventCode": "0x12", - "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2U", - "PerPkg": "1", - "PublicDescription": "Counts Data Response (DRS) packets that attempted to go direct to Intel(R) Ultra Path Interconnect (UPI) bypassing the CHA .", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", - "EventCode": "0x18", - "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Cycles Intel(R) UPI is in L1 power mode (shutdown)", - "EventCode": "0x21", - "EventName": "UNC_UPI_L1_POWER_CYCLES", - "PerPkg": "1", - "PublicDescription": "Counts cycles when the Intel(R) Ultra Path Interconnect (UPI) is in L1 power mode. L1 is a mode that totally shuts down the UPI link. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdown.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", - "EventCode": "0x14", - "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", - "EventCode": "0x14", - "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", - "EventCode": "0x14", - "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", - "EventCode": "0x14", - "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", - "EventCode": "0x14", - "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED", - "EventCode": "0x16", - "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", - "EventCode": "0x15", - "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1", - "EventCode": "0x20", - "EventName": "UNC_UPI_PHY_INIT_CYCLES", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "L1 Req Nack", - "EventCode": "0x23", - "EventName": "UNC_UPI_POWER_L1_NACK", - "PerPkg": "1", - "PublicDescription": "Counts the number of times a link sends/receives a LinkReqNAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx originally requested the power change). A Tx LinkReqNAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).", - "Unit": "UPI LL" - }, - { - "BriefDescription": "L1 Req (same as L1 Ack).", - "EventCode": "0x22", - "EventName": "UNC_UPI_POWER_L1_REQ", - "PerPkg": "1", - "PublicDescription": "Counts the number of times a link sends/receives a LinkReqAck. When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states. This requests can either be accepted or denied. If the Rx side replies with an Ack, the power mode will change. If it replies with NAck, no change will take place. This can be filtered based on Rx and Tx. An Rx LinkReqAck refers to receiving an Ack (meaning this agent's Tx originally requested the power change). A Tx LinkReqAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", - "EventCode": "0x46", - "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", - "EventCode": "0x46", - "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", - "EventCode": "0x46", - "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", - "EventCode": "0x46", - "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Cycles the Rx of the Intel(R) UPI is in L0p power mode", - "EventCode": "0x25", - "EventName": "UNC_UPI_RxL0P_POWER_CYCLES", - "PerPkg": "1", - "PublicDescription": "Counts cycles when the receive side (Rx) of the Intel(R) Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Cycles in L0. Receive side.", - "EventCode": "0x24", - "EventName": "UNC_UPI_RxL0_POWER_CYCLES", - "PerPkg": "1", - "PublicDescription": "Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", - "PerPkg": "1", - "PublicDescription": "Match Message Class - NCB", - "UMask": "0xe", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Bypass", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC", - "PerPkg": "1", - "PublicDescription": "Match Message Class - NCB", - "UMask": "0x10e", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", - "PerPkg": "1", - "PublicDescription": "Match Message Class - NCS", - "UMask": "0xf", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Non-Coherent Standard", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC", - "PerPkg": "1", - "PublicDescription": "Match Message Class - NCS", - "UMask": "0x10f", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Request", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", - "PerPkg": "1", - "PublicDescription": "REQ Message Class", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Request Opcode", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC", - "PerPkg": "1", - "PublicDescription": "Match REQ Opcodes - Specified in Umask[7:4]", - "UMask": "0x108", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Response - Conflict", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT", - "PerPkg": "1", - "UMask": "0x1aa", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Response - Invalid", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI", - "PerPkg": "1", - "UMask": "0x12a", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", - "PerPkg": "1", - "PublicDescription": "Match Message Class -WB", - "UMask": "0xc", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Response - Data", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC", - "PerPkg": "1", - "PublicDescription": "Match Message Class -WB", - "UMask": "0x10c", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA", - "PerPkg": "1", - "PublicDescription": "Match Message Class - RSP", - "UMask": "0xa", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Response - No Data", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", - "PerPkg": "1", - "PublicDescription": "Match Message Class - RSP", - "UMask": "0x10a", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Snoop", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", - "PerPkg": "1", - "PublicDescription": "SNP Message Class", - "UMask": "0x9", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Snoop Opcode", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC", - "PerPkg": "1", - "PublicDescription": "Match SNP Opcodes - Specified in Umask[7:4]", - "UMask": "0x109", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Writeback", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB", - "PerPkg": "1", - "PublicDescription": "Match Message Class -WB", - "UMask": "0xd", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Receive path of a UPI Port; Writeback", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC", - "PerPkg": "1", - "PublicDescription": "Match Message Class -WB", - "UMask": "0x10d", - "Unit": "UPI LL" - }, - { - "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", - "EventCode": "0x31", - "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", - "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", - "EventCode": "0x31", - "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", - "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer (Receive Queue) and passed directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", - "EventCode": "0x31", - "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", - "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "CRC Errors Detected", - "EventCode": "0xB", - "EventName": "UNC_UPI_RxL_CRC_ERRORS", - "PerPkg": "1", - "PublicDescription": "Number of CRC errors detected in the UPI Agent. Each UPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the UPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).", - "Unit": "UPI LL" - }, - { - "BriefDescription": "LLR Requests Sent", - "EventCode": "0x8", - "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT", - "PerPkg": "1", - "PublicDescription": "Number of LLR Requests were transmitted. This should generally be <= the number of CRC errors detected. If multiple errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "VN0 Credit Consumed", - "EventCode": "0x39", - "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0", - "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "VN1 Credit Consumed", - "EventCode": "0x3A", - "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1", - "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "VNA Credit Consumed", - "EventCode": "0x38", - "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA", - "PerPkg": "1", - "PublicDescription": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid data FLITs received from any slot", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", - "PerPkg": "1", - "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel(R) Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.", - "UMask": "0xf", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Null FLITs received from any slot", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", - "PerPkg": "1", - "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel(R) Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit.", - "UMask": "0x27", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received; Data", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.DATA", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received; Idle", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.IDLE", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).", - "UMask": "0x47", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received; LLCRD Not Empty", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.LLCRD", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2", - "UMask": "0x10", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received; LLCTRL", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.LLCTRL", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.", - "UMask": "0x40", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Protocol header and credit FLITs received from any slot", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", - "PerPkg": "1", - "PublicDescription": "Counts protocol header and credit FLITs (80 bit FLow control unITs) received from any of the 3 UPI slots on this UPI unit.", - "UMask": "0x97", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.ALL_NULL", - "Deprecated": "1", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.NULL", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received; Protocol Header", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.PROTHDR", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)", - "UMask": "0x80", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_FLITS.PROTHDR", - "Deprecated": "1", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.PROT_HDR", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received; Slot 0", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.SLOT0", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 0 - Other mask bits determine types of headers to count.", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received; Slot 1", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.SLOT1", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 1 - Other mask bits determine types of headers to count.", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Received; Slot 2", - "EventCode": "0x3", - "EventName": "UNC_UPI_RxL_FLITS.SLOT2", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 2 - Other mask bits determine types of headers to count.", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", - "Deprecated": "1", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_HDR_MATCH.NCB", - "PerPkg": "1", - "UMask": "0xc", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", - "Deprecated": "1", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_HDR_MATCH.NCS", - "PerPkg": "1", - "UMask": "0xd", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", - "Deprecated": "1", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_HDR_MATCH.REQ", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", - "Deprecated": "1", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_HDR_MATCH.RSP", - "PerPkg": "1", - "UMask": "0xa", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", - "Deprecated": "1", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_HDR_MATCH.SNP", - "PerPkg": "1", - "UMask": "0x9", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_RxL_BASIC_HDR_MATCH.WB", - "Deprecated": "1", - "EventCode": "0x5", - "EventName": "UNC_UPI_RxL_HDR_MATCH.WB", - "PerPkg": "1", - "UMask": "0xb", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Flit Buffer Allocations; Slot 0", - "EventCode": "0x30", - "EventName": "UNC_UPI_RxL_INSERTS.SLOT0", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Flit Buffer Allocations; Slot 1", - "EventCode": "0x30", - "EventName": "UNC_UPI_RxL_INSERTS.SLOT1", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Flit Buffer Allocations; Slot 2", - "EventCode": "0x30", - "EventName": "UNC_UPI_RxL_INSERTS.SLOT2", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the UPI Rx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Occupancy - All Packets; Slot 0", - "EventCode": "0x32", - "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Occupancy - All Packets; Slot 1", - "EventCode": "0x32", - "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "RxQ Occupancy - All Packets; Slot 2", - "EventCode": "0x32", - "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of elements in the UPI RxQ in each cycle. Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", - "EventCode": "0x33", - "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", - "EventCode": "0x33", - "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", - "EventCode": "0x33", - "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", - "EventCode": "0x33", - "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", - "EventCode": "0x33", - "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", - "EventCode": "0x33", - "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", - "EventCode": "0x2A", - "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Cycles in which the Tx of the Intel(R) Ultra Path Interconnect (UPI) is in L0p power mode", - "EventCode": "0x27", - "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", - "PerPkg": "1", - "PublicDescription": "Counts cycles when the transmit side (Tx) of the Intel(R) Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", - "EventCode": "0x28", - "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", - "EventCode": "0x29", - "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Cycles in L0. Transmit side.", - "EventCode": "0x26", - "EventName": "UNC_UPI_TxL0_POWER_CYCLES", - "PerPkg": "1", - "PublicDescription": "Number of UPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", - "PerPkg": "1", - "PublicDescription": "Match Message Class - NCB", - "UMask": "0xe", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Bypass", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC", - "PerPkg": "1", - "PublicDescription": "Match Message Class - NCB", - "UMask": "0x10e", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", - "PerPkg": "1", - "PublicDescription": "Match Message Class - NCS", - "UMask": "0xf", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Non-Coherent Standard", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC", - "PerPkg": "1", - "PublicDescription": "Match Message Class - NCS", - "UMask": "0x10f", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Request", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", - "PerPkg": "1", - "PublicDescription": "REQ Message Class", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Request Opcode", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC", - "PerPkg": "1", - "PublicDescription": "Match REQ Opcodes - Specified in Umask[7:4]", - "UMask": "0x108", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Conflict", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT", - "PerPkg": "1", - "UMask": "0x1aa", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Invalid", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI", - "PerPkg": "1", - "UMask": "0x12a", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", - "PerPkg": "1", - "PublicDescription": "Match Message Class -WB", - "UMask": "0xc", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Response - Data", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC", - "PerPkg": "1", - "PublicDescription": "Match Message Class -WB", - "UMask": "0x10c", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", - "PerPkg": "1", - "PublicDescription": "Match Message Class - RSP", - "UMask": "0xa", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Response - No Data", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", - "PerPkg": "1", - "PublicDescription": "Match Message Class - RSP", - "UMask": "0x10a", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", - "PerPkg": "1", - "PublicDescription": "SNP Message Class", - "UMask": "0x9", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop Opcode", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC", - "PerPkg": "1", - "PublicDescription": "Match SNP Opcodes - Specified in Umask[7:4]", - "UMask": "0x109", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB", - "PerPkg": "1", - "PublicDescription": "Match Message Class -WB", - "UMask": "0xd", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Matches on Transmit path of a UPI Port; Writeback", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC", - "PerPkg": "1", - "PublicDescription": "Match Message Class -WB", - "UMask": "0x10d", - "Unit": "UPI LL" - }, - { - "BriefDescription": "FLITs that bypassed the TxL Buffer", - "EventCode": "0x41", - "EventName": "UNC_UPI_TxL_BYPASSED", - "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel(R) Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link. However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR mode, increasing latency to transfer out to the link.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid data FLITs transmitted via any slot", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", - "PerPkg": "1", - "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel(R) Ultra Path Interconnect (UPI) slots on this UPI unit.", - "UMask": "0xf", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Null FLITs transmitted from any slot", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", - "PerPkg": "1", - "PublicDescription": "Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel(R) Ulra Path Interconnect (UPI) slots on this UPI unit.", - "UMask": "0x27", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent; Data", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.DATA", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Data Flits (which consume all slots), but how much to count is based on Slot0-2 mask, so count can be 0-3 depending on which slots are enabled for counting..", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Idle FLITs transmitted", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.IDLE", - "PerPkg": "1", - "PublicDescription": "Counts when the Intel Ultra Path Interconnect(UPI) transmits an idle FLIT(80 bit FLow control unITs). Every UPI cycle must be sending either data FLITs, protocol/credit FLITs or idle FLITs.", - "UMask": "0x47", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent; LLCRD Not Empty", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.LLCRD", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables counting of LLCRD (with non-zero payload). This only applies to slot 2 since LLCRD is only allowed in slot 2", - "UMask": "0x10", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent; LLCTRL", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.LLCTRL", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Equivalent to an idle packet. Enables counting of slot 0 LLCTRL messages.", - "UMask": "0x40", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Protocol header and credit FLITs transmitted across any slot", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", - "PerPkg": "1", - "PublicDescription": "Counts protocol header and credit FLITs (80 bit FLow control unITs) transmitted across any of the 3 UPI (Ultra Path Interconnect) slots on this UPI unit.", - "UMask": "0x97", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.ALL_NULL", - "Deprecated": "1", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.NULL", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent; Protocol Header", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.PROTHDR", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slot uMask bits)", - "UMask": "0x80", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_FLITS.PROTHDR", - "Deprecated": "1", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.PROT_HDR", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent; Slot 0", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.SLOT0", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 0 - Other mask bits determine types of headers to count.", - "UMask": "0x1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent; Slot 1", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.SLOT1", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 1 - Other mask bits determine types of headers to count.", - "UMask": "0x2", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Valid Flits Sent; Slot 2", - "EventCode": "0x2", - "EventName": "UNC_UPI_TxL_FLITS.SLOT2", - "PerPkg": "1", - "PublicDescription": "Shows legal flit time (hides impact of L0p and L0c).; Count Slot 2 - Other mask bits determine types of headers to count.", - "UMask": "0x4", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.DATA_HDR", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.DUAL_SLOT_HDR", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.LOC", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.NCB", - "PerPkg": "1", - "UMask": "0xe", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.NCS", - "PerPkg": "1", - "UMask": "0xf", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.NON_DATA_HDR", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.REM", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.REQ", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_DATA", - "PerPkg": "1", - "UMask": "0xc", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_NODATA", - "PerPkg": "1", - "UMask": "0xa", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.SGL_SLOT_HDR", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.SNP", - "PerPkg": "1", - "UMask": "0x9", - "Unit": "UPI LL" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_UPI_TxL_BASIC_HDR_MATCH.WB", - "Deprecated": "1", - "EventCode": "0x4", - "EventName": "UNC_UPI_TxL_HDR_MATCH.WB", - "PerPkg": "1", - "UMask": "0xc", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Tx Flit Buffer Allocations", - "EventCode": "0x40", - "EventName": "UNC_UPI_TxL_INSERTS", - "PerPkg": "1", - "PublicDescription": "Number of allocations into the UPI Tx Flit Buffer. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Tx Flit Buffer Occupancy", - "EventCode": "0x42", - "EventName": "UNC_UPI_TxL_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Accumulates the number of flits in the TxQ. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", - "EventCode": "0x45", - "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", - "PerPkg": "1", - "Unit": "UPI LL" - }, - { - "BriefDescription": "VNA Credits Pending Return - Occupancy", - "EventCode": "0x44", - "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.", - "Unit": "UPI LL" - }, - { - "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", - "EventCode": "0xff", - "EventName": "UNC_U_CLOCKTICKS", - "PerPkg": "1", - "Unit": "UBOX" - }, - { - "BriefDescription": "Message Received", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", - "PerPkg": "1", - "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.", - "UMask": "0x8", - "Unit": "UBOX" - }, - { - "BriefDescription": "Message Received", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.INT_PRIO", - "PerPkg": "1", - "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.", - "UMask": "0x10", - "Unit": "UBOX" - }, - { - "BriefDescription": "Message Received; IPI", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", - "PerPkg": "1", - "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.; Inter Processor Interrupts", - "UMask": "0x4", - "Unit": "UBOX" - }, - { - "BriefDescription": "Message Received; MSI", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", - "PerPkg": "1", - "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.; Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "Message Received; VLW", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", - "PerPkg": "1", - "PublicDescription": "Virtual Logical Wire (legacy) message were received from Uncore.", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "IDI Lock/SplitLock Cycles", - "EventCode": "0x44", - "EventName": "UNC_U_LOCK_CYCLES", - "PerPkg": "1", - "PublicDescription": "Number of times an IDI Lock/SplitLock sequence was started", - "Unit": "UBOX" - }, - { - "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", - "EventCode": "0x45", - "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", - "PerPkg": "1", - "PublicDescription": "PHOLD cycles.", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", - "EventCode": "0x4C", - "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_RACU_DRNG.RDRAND", - "EventCode": "0x4C", - "EventName": "UNC_U_RACU_DRNG.RDRAND", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_RACU_DRNG.RDSEED", - "EventCode": "0x4C", - "EventName": "UNC_U_RACU_DRNG.RDSEED", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "RACU Request", - "EventCode": "0x46", - "EventName": "UNC_U_RACU_REQUESTS", - "PerPkg": "1", - "PublicDescription": "Number outstanding register requests within message channel tracker", - "Unit": "UBOX" - }, - { - "BriefDescription": "UPI interconnect send bandwidth for payload. Derived from unc_upi_txl_flits.all_data", - "EventCode": "0x2", - "EventName": "UPI_DATA_BANDWIDTH_TX", - "PerPkg": "1", - "PublicDescription": "Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel(R) Ultra Path Interconnect (UPI) slots on this UPI unit.", - "ScaleUnit": "7.11E-06Bytes", - "UMask": "0xf", - "Unit": "UPI LL" - } -] -- cgit v1.2.3-58-ga151 From 2bb848f820a5df2f9684435886c44caee8f5a056 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 13 Apr 2023 06:29:48 -0700 Subject: perf vendor events intel: Fix uncore topics for snowridgex Remove 'uncore-other' topic classification, move to cache, interconnect and io. Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Edward Baker Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: http://lore.kernel.org/lkml/20230413132949.3487664-21-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/x86/snowridgex/uncore-cache.json | 7100 ++++++ .../arch/x86/snowridgex/uncore-interconnect.json | 6016 +++++ .../pmu-events/arch/x86/snowridgex/uncore-io.json | 8944 ++++++++ .../arch/x86/snowridgex/uncore-other.json | 22056 ------------------- 4 files changed, 22060 insertions(+), 22056 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/snowridgex/uncore-cache.json create mode 100644 tools/perf/pmu-events/arch/x86/snowridgex/uncore-interconnect.json create mode 100644 tools/perf/pmu-events/arch/x86/snowridgex/uncore-io.json delete mode 100644 tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-cache.json b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-cache.json new file mode 100644 index 000000000000..a68a5bb05c22 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-cache.json @@ -0,0 +1,7100 @@ +[ + { + "BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.ia_miss", + "EventCode": "0x35", + "EventName": "LLC_MISSES.MMIO_READ", + "Filter": "config1=0x40040e33", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss", + "EventCode": "0x35", + "EventName": "LLC_MISSES.MMIO_WRITE", + "Filter": "config1=0x40041e33", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss", + "EventCode": "0x35", + "EventName": "LLC_MISSES.UNCACHEABLE", + "Filter": "config1=0x40e33", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss", + "EventCode": "0x35", + "EventName": "LLC_REFERENCES.STREAMING_FULL", + "Filter": "config1=0x41833", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "ScaleUnit": "64Bytes", + "UMask": "0xc001fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss", + "EventCode": "0x35", + "EventName": "LLC_REFERENCES.STREAMING_PARTIAL", + "Filter": "config1=0x41a33", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "ScaleUnit": "64Bytes", + "UMask": "0xc001fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7", + "EventCode": "0x80", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10", + "EventCode": "0x81", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8", + "EventCode": "0x81", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9", + "EventCode": "0x81", + "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7", + "EventCode": "0x82", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10", + "EventCode": "0x83", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8", + "EventCode": "0x83", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9", + "EventCode": "0x83", + "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7", + "EventCode": "0x88", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10", + "EventCode": "0x89", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8", + "EventCode": "0x89", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9", + "EventCode": "0x89", + "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7", + "EventCode": "0x8A", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10", + "EventCode": "0x8B", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8", + "EventCode": "0x8B", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9", + "EventCode": "0x8B", + "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7", + "EventCode": "0x84", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10", + "EventCode": "0x85", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8", + "EventCode": "0x85", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9", + "EventCode": "0x85", + "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7", + "EventCode": "0x86", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10", + "EventCode": "0x87", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8", + "EventCode": "0x87", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9", + "EventCode": "0x87", + "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", + "EventCode": "0x8C", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10", + "EventCode": "0x8D", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8", + "EventCode": "0x8D", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9", + "EventCode": "0x8D", + "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7", + "EventCode": "0x8E", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10", + "EventCode": "0x8F", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8", + "EventCode": "0x8F", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9", + "EventCode": "0x8F", + "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", + "PerPkg": "1", + "PublicDescription": "CHA to iMC Bypass : Intermediate bypass Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the intermediate bypass.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Bypass : Not Taken", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", + "PerPkg": "1", + "PublicDescription": "CHA to iMC Bypass : Not Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Bypass : Taken", + "EventCode": "0x57", + "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN", + "PerPkg": "1", + "PublicDescription": "CHA to iMC Bypass : Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the full bypass.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Uncore cache clock ticks", + "EventName": "UNC_CHA_CLOCKTICKS", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Clockticks", + "EventCode": "0xc0", + "EventName": "UNC_CHA_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0xf2", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Any Single Snoop", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.ANY_ONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Any Single Snoop : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0xf1", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Multiple Core Requests", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Multiple Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x42", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Single Core Requests", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.CORE_ONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Single Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x41", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Multiple Eviction", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Multiple Eviction : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x82", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Single Eviction", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Single Eviction : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x81", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Multiple External Snoops", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Multiple External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x22", + "Unit": "CHA" + }, + { + "BriefDescription": "Core Cross Snoops Issued : Single External Snoops", + "EventCode": "0x33", + "EventName": "UNC_CHA_CORE_SNP.EXT_ONE", + "PerPkg": "1", + "PublicDescription": "Core Cross Snoops Issued : Single External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", + "UMask": "0x21", + "Unit": "CHA" + }, + { + "BriefDescription": "Counter 0 Occupancy", + "EventCode": "0x1F", + "EventName": "UNC_CHA_COUNTER0_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Counter 0 Occupancy : Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6E", + "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6E", + "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6E", + "EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.GO", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.NOP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Direct GO", + "EventCode": "0x6D", + "EventName": "UNC_CHA_DIRECT_GO_OPC.PULL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Distress signal asserted : DPT Local", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_LOCAL", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Distress signal asserted : DPT Remote", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_NONLOCAL", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Distress signal asserted : DPT Stalled - IV", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_IV", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_NOCRD", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Distress signal asserted : Horizontal", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.HORZ", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Distress signal asserted : Vertical", + "EventCode": "0xAF", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.VERT", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Down", + "EventCode": "0xBA", + "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Up", + "EventCode": "0xBA", + "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Left and Even", + "EventCode": "0xB6", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", + "EventCode": "0xB6", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Right and Even", + "EventCode": "0xB6", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", + "EventCode": "0xB6", + "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "EventCode": "0xBB", + "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "EventCode": "0xBB", + "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "EventCode": "0xBB", + "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "EventCode": "0xBB", + "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "EventCode": "0xB7", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "EventCode": "0xB7", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "EventCode": "0xB7", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "EventCode": "0xB7", + "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Left and Even", + "EventCode": "0xB8", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", + "EventCode": "0xB8", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Right and Even", + "EventCode": "0xB8", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", + "EventCode": "0xB8", + "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal IV Ring in Use : Left", + "EventCode": "0xB9", + "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Horizontal IV Ring in Use : Right", + "EventCode": "0xB9", + "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Normal priority reads issued to the memory controller from the CHA", + "EventCode": "0x59", + "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", + "PerPkg": "1", + "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "HA to iMC Reads Issued : ISOCH", + "EventCode": "0x59", + "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY", + "PerPkg": "1", + "PublicDescription": "HA to iMC Reads Issued : ISOCH : Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", + "PerPkg": "1", + "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to any of the memory controller channels.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "PerPkg": "1", + "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line : Counts the total number of full line writes issued from the HA into the memory controller.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "PerPkg": "1", + "PublicDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH : Counts the total number of full line writes issued from the HA into the memory controller.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "PerPkg": "1", + "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial : Counts the total number of full line writes issued from the HA into the memory controller.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Any Request", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.", + "UMask": "0x1fffff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : All Request Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.ANY_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : All Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local or remote transaction to the LLC, including prefetch.", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE", + "PerPkg": "1", + "UMask": "0x1bd0ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Code Reads", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Code Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x1bd0ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : CRd Request Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : CRd Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Code Read Misses", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_MISS", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Code Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x1bd001", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Local request Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Local request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local transaction to the LLC, including prefetches from the Core", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD", + "PerPkg": "1", + "UMask": "0x1bc1ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions", + "UMask": "0x1bc1ff", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL", + "PerPkg": "1", + "UMask": "0x1fc1ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Data Read Request Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Data Read Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Read transactions.", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Data Read Misses", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Data Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x1bc101", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DMND_READ_LOCAL", + "PerPkg": "1", + "UMask": "0x841ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : E State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.E", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Exclusive State", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : F State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : F State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Forward State", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Flush or Invalidate Requests", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.", + "UMask": "0x1a44ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Flush or Invalidate Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Flush or Invalidate Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : I State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.I", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : I State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Miss", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Transactions homed locally Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Transactions homed locally Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC.", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : M State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.M", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : M State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Modified State", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : All Misses", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : All Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x1fe001", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Write Request Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Write Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Writeback transactions to the LLC This includes all write transactions -- both Cacheable and UC.", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Reads", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x1bd9ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_LOC_HOM", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x9d9ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_REM_HOM", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x11d9ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Read Misses", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x1bd901", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Locally HOMed Read Misses", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_LOC_HOM", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Locally HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0xbd901", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Remotely HOMed Read Misses", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_REM_HOM", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Remotely HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x13d901", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_OR_SNOOP_REMOTE_MISS_REM_HOM", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x161901", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_REMOTE_LOC_HOM", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0xa19ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Reads that Hit the Snoop Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.READ_SF_HIT", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Reads that Hit the Snoop Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x1bd90e", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : RFO Requests", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.", + "UMask": "0x1bc8ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : RFO Request Filter", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO_F", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : RFO Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : RFO Misses", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO_MISS", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : RFO Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", + "UMask": "0x1bc801", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.RFO_LOCAL", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO_PREF_LOCAL", + "PerPkg": "1", + "UMask": "0x888ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : S State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.S", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Shared State", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : SnoopFilter - E State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.SF_E", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : SnoopFilter - E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit Exclusive State", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : SnoopFilter - H State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.SF_H", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : SnoopFilter - H State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit HitMe State", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : SnoopFilter - S State", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.SF_S", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : SnoopFilter - S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit Shared State", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups : Filters Requests for those that write info into the cache", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Write Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.", + "UMask": "0x1a42ff", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated.", + "Deprecated": "1", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL", + "PerPkg": "1", + "UMask": "0x842ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : All Lines Victimized", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.ALL", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : All Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0xf", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Lines in E state", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Lines in E state : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Local - All Lines", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Local - All Lines : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x200f", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Local - Lines in E State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Local - Lines in E State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x2002", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Local - Lines in M State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Local - Lines in M State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x2001", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Local Only", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Local Only : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Local - Lines in S State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Local - Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x2004", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Lines in M state", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Lines in M state : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Lines in S State", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc : CV0 Prefetch Miss", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.CV0_PREF_MISS", + "PerPkg": "1", + "PublicDescription": "Cbo Misc : CV0 Prefetch Miss : Miscellaneous events in the Cbo.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc : CV0 Prefetch Victim", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.CV0_PREF_VIC", + "PerPkg": "1", + "PublicDescription": "Cbo Misc : CV0 Prefetch Victim : Miscellaneous events in the Cbo.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Number of times that an RFO hit in S state.", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.RFO_HIT_S", + "PerPkg": "1", + "PublicDescription": "Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc : Silent Snoop Eviction", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE", + "PerPkg": "1", + "PublicDescription": "Cbo Misc : Silent Snoop Eviction : Miscellaneous events in the Cbo. : Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cbo Misc : Write Combining Aliasing", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.WC_ALIASING", + "PerPkg": "1", + "PublicDescription": "Cbo Misc : Write Combining Aliasing : Miscellaneous events in the Cbo. : Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0", + "EventCode": "0xE6", + "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1", + "EventCode": "0xE6", + "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.ADEGRCREDIT", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.AKEGRCREDIT", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.ALLRSFWAYS_RES", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.BLEGRCREDIT", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.FSF_VICP", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLOWSNP", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLWAYRSV", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_PAMATCH", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_WAYMATCH", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.HACREDIT", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.IDX_INPIPE", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.IPQ_SETMATCH_VICP", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.IRQ_SETMATCH_VICP", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.ISMQ_SETMATCH_VICP", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.IVEGRCREDIT", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.LLC_WAYS_RES", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.NOTALLOWSNOOP", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.ONE_FSF_VIC", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.ONE_RSP_CON", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.PTL_INPIPE", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.RMW_SETMATCH", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.RRQ_SETMATCH_VICP", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.SETMATCHENTRYWSCT", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.SF_WAYS_RES", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.TOPA_MATCH", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.TORID_MATCH_GO_P", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_REQ", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_RSP", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCB", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCS", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_RSP", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_WB", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "Pipe Rejects", + "EventCode": "0x42", + "EventName": "UNC_CHA_PIPE_REJECT.WAY_MATCH", + "PerPkg": "1", + "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC0", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC0 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 0 only.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC1", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC1 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 1 only.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC10", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC10", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC10 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 10 only.", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC11", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC11", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC11 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 11 only.", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC12", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC12", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC12 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 12 only.", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC13", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC13", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC13 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 13 only.", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC2", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC2 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 2 only.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC3", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC3 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 3 only.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC4", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC4 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 4 only.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC5", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC5 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 5 only.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC6", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC6", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC6 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 6 only.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC7", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC7", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC7 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 7 only.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC8", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC8", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC8 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 8 only.", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC9", + "EventCode": "0x58", + "EventName": "UNC_CHA_READ_NO_CREDITS.MC9", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC9 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 9 only.", + "Unit": "CHA" + }, + { + "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and remote INVITOE requests sent to the CHA's home agent", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.INVITOE", + "PerPkg": "1", + "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", + "UMask": "0x30", + "Unit": "CHA" + }, + { + "BriefDescription": "Local read requests that miss the SF/LLC and remote read requests sent to the CHA's home agent", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS", + "PerPkg": "1", + "PublicDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) .", + "UMask": "0x3", + "Unit": "CHA" + }, + { + "BriefDescription": "Local write requests that miss the SF/LLC and remote write requests sent to the CHA's home agent", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES", + "PerPkg": "1", + "PublicDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", + "UMask": "0xc", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD", + "EventCode": "0xAC", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK", + "EventCode": "0xAC", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL", + "EventCode": "0xAC", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV", + "EventCode": "0xAC", + "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : AD", + "EventCode": "0xAA", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core", + "EventCode": "0xAA", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.", + "EventCode": "0xAA", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.AKC", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core", + "EventCode": "0xAA", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.", + "EventCode": "0xAA", + "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : AD", + "EventCode": "0xAD", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : AK", + "EventCode": "0xAD", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1", + "EventCode": "0xAD", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : BL", + "EventCode": "0xAD", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : IV", + "EventCode": "0xAD", + "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : AD", + "EventCode": "0xAB", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core", + "EventCode": "0xAB", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring", + "EventCode": "0xAB", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AKC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core", + "EventCode": "0xAB", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.", + "EventCode": "0xAB", + "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Source Throttle", + "EventCode": "0xae", + "EventName": "UNC_CHA_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : IRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IRQ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Allocations : IRQ : Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Allocations : IRQ Rejected : Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : PRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.PRQ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Allocations : PRQ", + "EventCode": "0x13", + "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request", + "EventCode": "0x18", + "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IRQ0 Reject counter was true", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way : Way conflict with another request that caused the reject", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC Victim", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Victim", + "EventCode": "0x19", + "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request", + "EventCode": "0x24", + "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request", + "EventCode": "0x2C", + "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 1 : ANY0", + "EventCode": "0x25", + "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Rejects - Set 1 : HA", + "EventCode": "0x25", + "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA", + "PerPkg": "1", + "PublicDescription": "ISMQ Rejects - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 1 : ANY0", + "EventCode": "0x2D", + "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "ISMQ Retries - Set 1 : HA", + "EventCode": "0x2D", + "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA", + "PerPkg": "1", + "PublicDescription": "ISMQ Retries - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Ingress (from CMS) Occupancy : IRQ", + "EventCode": "0x11", + "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Occupancy : IRQ : Counts number of entries in the specified Ingress queue in each cycle.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : AD REQ on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : AD REQ on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a request", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : AD RSP on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : AD RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a response", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : Non UPI AK Request", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : Non UPI AK Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject AK ring message", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : BL NCB on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : BL NCB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCB", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : BL NCS on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : BL NCS on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCS", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : BL RSP on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : BL RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a response", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : BL WB on VN0", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : BL WB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 0 : Non UPI IV Request", + "EventCode": "0x2E", + "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 0 : Non UPI IV Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject IV ring message", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : Allow Snoop", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 1 : Allow Snoop : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : ANY0", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 1 : ANY0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Any condition listed in the Other0 Reject counter was true", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : HA", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 1 : HA : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : LLC OR SF Way", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 1 : LLC OR SF Way : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Way conflict with another request that caused the reject", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : LLC Victim", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 1 : LLC Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : PhyAddr Match", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 1 : PhyAddr Match : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Address match with an outstanding request that was rejected.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : SF Victim", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 1 : SF Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Requests did not generate Snoop filter victim", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Other Retries - Set 1 : Victim", + "EventCode": "0x2F", + "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM", + "PerPkg": "1", + "PublicDescription": "Other Retries - Set 1 : Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request", + "EventCode": "0x20", + "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the PRQ0 Reject counter was true", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC Victim", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Victim", + "EventCode": "0x21", + "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : AD REQ on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a request", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : AD RSP on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a response", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Request", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : Non UPI AK Request : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject AK ring message", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : BL NCB on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCB", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : BL NCS on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCS", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : BL RSP on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a response", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : BL WB on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a writeback", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Request", + "EventCode": "0x2A", + "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 0 : Non UPI IV Request : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject IV ring message", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : Allow Snoop : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : ANY0", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : ANY0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Any condition listed in the WBQ0 Reject counter was true", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : HA", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : HA : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : LLC OR SF Way : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Way conflict with another request that caused the reject", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : LLC Victim", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : LLC Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : PhyAddr Match : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Address match with an outstanding request that was rejected.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : SF Victim", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : SF Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Requests did not generate Snoop filter victim", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Request Queue Retries - Set 1 : Victim", + "EventCode": "0x2B", + "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", + "PerPkg": "1", + "PublicDescription": "Request Queue Retries - Set 1 : Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - All", + "EventCode": "0xE5", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Credited", + "EventCode": "0xE5", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", + "EventCode": "0xE5", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - All", + "EventCode": "0xE5", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Credited", + "EventCode": "0xE5", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", + "EventCode": "0xE5", + "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - All", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - Credited", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AK", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - All", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - Credited", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Bypass : IV", + "EventCode": "0xE2", + "EventName": "UNC_CHA_RxR_BYPASS.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - All", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Credited", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : AK", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - All", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Credited", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : IFV - Credited", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation : IV", + "EventCode": "0xE3", + "EventName": "UNC_CHA_RxR_CRD_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Injection Starvation", + "EventCode": "0xe4", + "EventName": "UNC_CHA_RxR_CRD_STARVED_1", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - All", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - Credited", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AK", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - All", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - Credited", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Allocations : IV", + "EventCode": "0xE1", + "EventName": "UNC_CHA_RxR_INSERTS.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - All", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AK", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - All", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : IV", + "EventCode": "0xE0", + "EventName": "UNC_CHA_RxR_OCCUPANCY.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop filter capacity evictions for E-state entries.", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.E_STATE", + "PerPkg": "1", + "PublicDescription": "Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop filter capacity evictions for M-state entries.", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.M_STATE", + "PerPkg": "1", + "PublicDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop filter capacity evictions for S-state entries.", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.S_STATE", + "PerPkg": "1", + "PublicDescription": "Counts snoop filter capacity evictions for entries tracking shared lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : All", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.ALL", + "PerPkg": "1", + "PublicDescription": "Snoops Sent : All : Counts the number of snoops issued by the HA.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : Broadcast snoops for Local Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL", + "PerPkg": "1", + "PublicDescription": "Snoops Sent : Broadcast snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA responding to local requests", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : Directed snoops for Local Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", + "PerPkg": "1", + "PublicDescription": "Snoops Sent : Directed snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA responding to local requests", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoops Sent : Snoops sent for Local Requests", + "EventCode": "0x51", + "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL", + "PerPkg": "1", + "PublicDescription": "Snoops Sent : Snoops sent for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA responding to local requests", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : RspCnflct", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received Local : RspCnflct : Number of snoop responses received for a Local request : Filters for snoops responses of RspConflict to local CA requests. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : RspFwd", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received Local : RspFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspFwd to local CA requests. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received Local : Rsp*FWD*WB : Number of snoop responses received for a Local request : Filters for a snoop response of Rsp*Fwd*WB to local CA requests. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : RspI", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received Local : RspI : Number of snoop responses received for a Local request : Filters for snoops responses of RspI to local CA requests. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : RspIFwd", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received Local : RspIFwd : Number of snoop responses received for a Local request : Filters for snoop responses of RspIFwd to local CA requests. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : RspS", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received Local : RspS : Number of snoop responses received for a Local request : Filters for snoop responses of RspS to local CA requests. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : RspSFwd", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received Local : RspSFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspSFwd to local CA requests. This is returned when a remote caching agent forwards data but holds on to its currently copy. This is common for data and code reads that hit in a remote socket in E or F state.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop Responses Received Local : Rsp*WB", + "EventCode": "0x5D", + "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB", + "PerPkg": "1", + "PublicDescription": "Snoop Responses Received Local : Rsp*WB : Number of snoop responses received for a Local request : Filters for a snoop response of RspIWB or RspSWB to local CA requests. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Misc Snoop Responses Received : MtoI RspIDataM", + "EventCode": "0x6B", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM", + "EventCode": "0x6B", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit LLC", + "EventCode": "0x6B", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit SF", + "EventCode": "0x6B", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit LLC", + "EventCode": "0x6B", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit SF", + "EventCode": "0x6B", + "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7", + "EventCode": "0xD0", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7", + "EventCode": "0xD2", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7", + "EventCode": "0xD4", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7", + "EventCode": "0xD6", + "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10", + "EventCode": "0xD1", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8", + "EventCode": "0xD1", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9", + "EventCode": "0xD1", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10", + "EventCode": "0xD3", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8", + "EventCode": "0xD3", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9", + "EventCode": "0xD3", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10", + "EventCode": "0xD5", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8", + "EventCode": "0xD5", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9", + "EventCode": "0xD5", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10", + "EventCode": "0xD7", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8", + "EventCode": "0xD7", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9", + "EventCode": "0xD7", + "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ALL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001ffff", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DDR4 Access", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DDR4 Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.DDR", + "Deprecated": "1", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.DDR4", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : SF/LLC Evictions", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.EVICT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : SF/LLC Evictions : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just Hits", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.HIT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Just Hits : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All requests from iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CLFlushes issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8c7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CLFlushOpts issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CLFlushOpts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8d7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRDs issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRDs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc80fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; CRd Pref from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter", + "UMask": "0xc88fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc837ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc827ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8a7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc80ffd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc88ffd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to page walks that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc837fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc827fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8a7fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc807fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc887fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc80ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc88ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc837fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc827fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8a7fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", + "UMask": "0xc867fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", + "UMask": "0xc86ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc807fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc887fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc877de01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc867fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc87fde01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc807ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc887ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE", + "PerPkg": "1", + "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc3fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WBEFtoIs issued by an IA Core. Non Modified Write Backs", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI", + "PerPkg": "1", + "PublicDescription": "WbEFtoIs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc37ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WBMtoEs issued by an IA Core. Non Modified Write Backs", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE", + "PerPkg": "1", + "PublicDescription": "WbMtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc2fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI", + "PerPkg": "1", + "PublicDescription": "WbMtoIs issued by iA Cores . (Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc27ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WBStoIs issued by an IA Core. Non Modified Write Backs", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI", + "PerPkg": "1", + "PublicDescription": "WbStoIs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc67ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc867ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All requests from IO Devices", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CLFlushes issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8c3ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All requests from IO Devices that hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc43fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcd43fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8f3fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc803fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc43ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcd43ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All requests from IO Devices that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc43fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcd43fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8f3fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc803fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8f3ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by IO Devices", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc803ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WbMtoIs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc23ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : IRQ - iA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : IRQ - iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From an iA Core", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : IRQ - Non iA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : IRQ - Non iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just ISOC", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ISOC", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Just ISOC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just Local Targets", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Just Local Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All from Local iA and IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All from Local iA and IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests", + "UMask": "0xc000ff05", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All from Local iA", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All from Local iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores", + "UMask": "0xc000ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All from Local IO", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All from Local IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic", + "UMask": "0xc000ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just Misses", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.MISS", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Just Misses : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : MMCFG Access", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.MMCFG", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : MMCFG Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just NearMem", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.NEARMEM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Just NearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just NonCoherent", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.NONCOH", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Just NonCoherent : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Just NotNearMem", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Just NotNearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : PRQ - IOSF", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PRQ - IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From a PCIe Device", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : PRQ - Non IOSF", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PRQ - Non IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DDR4 Access", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DDR4 Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : SF/LLC Evictions", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : SF/LLC Evictions : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just Hits", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Just Hits : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All requests from iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8c7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8d7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRDs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc80fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; CRd Pref from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter", + "UMask": "0xc88fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc837ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc827ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8a7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc80ffd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc88ffd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc837fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc827fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8a7fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc807fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc887fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc80ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc88ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc837fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc827fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8a7fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", + "UMask": "0xc867fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy; WCiL misses from local IA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", + "UMask": "0xc86ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc807fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc887fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc877de01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc867fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc87fde01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc807ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc887ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc27ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc86fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc867ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All requests from IO Devices", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Devices", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8c3ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc43fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcd43fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8f3fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc803fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc43ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcd43ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc001fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc43fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcd43fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8f3fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc803fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8f3ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc803ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xcc23ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : IRQ - iA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : IRQ - iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From an iA Core", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : IRQ - Non iA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : IRQ - Non iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just ISOC", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Just ISOC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just Local Targets", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Just Local Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All from Local iA and IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All from Local iA and IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests", + "UMask": "0xc000ff05", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All from Local iA", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All from Local iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores", + "UMask": "0xc000ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All from Local IO", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All from Local IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic", + "UMask": "0xc000ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just Misses", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Just Misses : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : MMCFG Access", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : MMCFG Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just NearMem", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Just NearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just NonCoherent", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Just NonCoherent : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Just NotNearMem", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Just NotNearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : PRQ - IOSF", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PRQ - IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From a PCIe Device", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : PRQ - Non IOSF", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PRQ - Non IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - All", + "EventCode": "0xA6", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", + "EventCode": "0xA6", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", + "EventCode": "0xA6", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - All", + "EventCode": "0xA6", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", + "EventCode": "0xA6", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", + "EventCode": "0xA6", + "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - All", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AK", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - All", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : IV", + "EventCode": "0xA7", + "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV", + "EventCode": "0xA2", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV", + "EventCode": "0xA3", + "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AK", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : IV", + "EventCode": "0xA1", + "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AK", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : IV", + "EventCode": "0xA4", + "EventName": "UNC_CHA_TxR_HORZ_NACK.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AK", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : IV", + "EventCode": "0xA0", + "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All", + "EventCode": "0xA5", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited", + "EventCode": "0xA5", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK", + "EventCode": "0xA5", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited", + "EventCode": "0xA5", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All", + "EventCode": "0xA5", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited", + "EventCode": "0xA5", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV", + "EventCode": "0xA5", + "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", + "EventCode": "0x9D", + "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1", + "EventCode": "0x95", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1", + "EventCode": "0x97", + "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_CHA_TxR_VERT_INSERTS0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : IV", + "EventCode": "0x98", + "EventName": "UNC_CHA_TxR_VERT_NACK0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", + "EventCode": "0x99", + "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : IV", + "EventCode": "0x9A", + "EventName": "UNC_CHA_TxR_VERT_STARVED0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", + "EventCode": "0x9B", + "EventName": "UNC_CHA_TxR_VERT_STARVED1.TGC", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Down and Even", + "EventCode": "0xB0", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Down and Odd", + "EventCode": "0xB0", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Up and Even", + "EventCode": "0xB0", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Up and Odd", + "EventCode": "0xB0", + "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Down and Even", + "EventCode": "0xB4", + "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", + "EventCode": "0xB4", + "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Up and Even", + "EventCode": "0xB4", + "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", + "EventCode": "0xB4", + "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Down and Even", + "EventCode": "0xB1", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Down and Odd", + "EventCode": "0xB1", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Up and Even", + "EventCode": "0xB1", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Up and Odd", + "EventCode": "0xB1", + "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Down and Even", + "EventCode": "0xB2", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Down and Odd", + "EventCode": "0xB2", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Up and Even", + "EventCode": "0xB2", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Up and Odd", + "EventCode": "0xB2", + "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical IV Ring in Use : Down", + "EventCode": "0xB3", + "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical IV Ring in Use : Up", + "EventCode": "0xB3", + "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Down and Even", + "EventCode": "0xB5", + "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", + "EventCode": "0xB5", + "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Up and Even", + "EventCode": "0xB5", + "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", + "EventCode": "0xB5", + "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "WbPushMtoI : Pushed to LLC", + "EventCode": "0x56", + "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC", + "PerPkg": "1", + "PublicDescription": "WbPushMtoI : Pushed to LLC : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was able to push WbPushMToI to LLC", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "WbPushMtoI : Pushed to Memory", + "EventCode": "0x56", + "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM", + "PerPkg": "1", + "PublicDescription": "WbPushMtoI : Pushed to Memory : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM)", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC0 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 0 only.", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC1 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 1 only.", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC10", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC10", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC10 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 10 only.", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC11", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC11", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC11 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 11 only.", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC12", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC12", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC12 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 12 only.", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC13", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC13", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC13 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 13 only.", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC2 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 2 only.", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC3 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 3 only.", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC4 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 4 only.", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC5 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 5 only.", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC6", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC6", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC6 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 6 only.", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC7", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC7", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC7 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 7 only.", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC8", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC8", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC8 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 8 only.", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC9", + "EventCode": "0x5A", + "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC9", + "PerPkg": "1", + "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC9 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 9 only.", + "Unit": "CHA" + }, + { + "BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT", + "PerPkg": "1", + "PublicDescription": "XPT Prefetches : Dropped (on 0?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD", + "PerPkg": "1", + "PublicDescription": "XPT Prefetches : Dropped (on 0?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT", + "PerPkg": "1", + "PublicDescription": "XPT Prefetches : Dropped (on 1?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD", + "PerPkg": "1", + "PublicDescription": "XPT Prefetches : Dropped (on 1?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "XPT Prefetches : Sent (on 0?)", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.SENT0", + "PerPkg": "1", + "PublicDescription": "XPT Prefetches : Sent (on 0?) : Number of XPT prefetches sent", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "XPT Prefetches : Sent (on 1?)", + "EventCode": "0x6f", + "EventName": "UNC_CHA_XPT_PREF.SENT1", + "PerPkg": "1", + "PublicDescription": "XPT Prefetches : Sent (on 1?) : Number of XPT prefetches sent", + "UMask": "0x10", + "Unit": "CHA" + } +] diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-interconnect.json new file mode 100644 index 000000000000..de3840078e21 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-interconnect.json @@ -0,0 +1,6016 @@ +[ + { + "BriefDescription": "Total Write Cache Occupancy : Any Source", + "EventCode": "0x0F", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", + "PerPkg": "1", + "PublicDescription": "Total Write Cache Occupancy : Any Source : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events. : Tracks all requests from any source port.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Total Write Cache Occupancy : Snoops", + "EventCode": "0x0F", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q", + "PerPkg": "1", + "PublicDescription": "Total Write Cache Occupancy : Snoops : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory.", + "EventCode": "0x0f", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", + "PerPkg": "1", + "PublicDescription": "Total IRP occupancy of inbound read and write requests to coherent memory. This is effectively the sum of read occupancy and write occupancy.", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Clockticks of the IO coherency tracker (IRP)", + "EventCode": "0x01", + "EventName": "UNC_I_CLOCKTICKS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops : CLFlush", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", + "PerPkg": "1", + "PublicDescription": "Coherent Ops : CLFlush : Counts the number of coherency related operations servied by the IRP", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.PCITOM", + "PerPkg": "1", + "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.RFO", + "PerPkg": "1", + "PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops : WbMtoI", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.WBMTOI", + "PerPkg": "1", + "PublicDescription": "Coherent Ops : WbMtoI : Counts the number of coherency related operations servied by the IRP", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "FAF RF full", + "EventCode": "0x17", + "EventName": "UNC_I_FAF_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.", + "EventCode": "0x18", + "EventName": "UNC_I_FAF_INSERTS", + "PerPkg": "1", + "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.", + "Unit": "IRP" + }, + { + "BriefDescription": "Occupancy of the IRP FAF queue.", + "EventCode": "0x19", + "EventName": "UNC_I_FAF_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.", + "Unit": "IRP" + }, + { + "BriefDescription": "FAF allocation -- sent to ADQ", + "EventCode": "0x16", + "EventName": "UNC_I_FAF_TRANSACTIONS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", + "EventCode": "0x20", + "EventName": "UNC_I_IRP_ALL.EVICTS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)", + "EventCode": "0x20", + "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", + "EventCode": "0x20", + "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary", + "EventCode": "0x1E", + "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary", + "EventCode": "0x1e", + "EventName": "UNC_I_MISC0.2ND_RD_INSERT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary", + "EventCode": "0x1e", + "EventName": "UNC_I_MISC0.2ND_WR_INSERT", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", + "EventCode": "0x1E", + "EventName": "UNC_I_MISC0.FAST_REJ", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests", + "EventCode": "0x1e", + "EventName": "UNC_I_MISC0.FAST_REQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary", + "EventCode": "0x1E", + "EventName": "UNC_I_MISC0.FAST_XFER", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary", + "EventCode": "0x1E", + "EventName": "UNC_I_MISC0.PF_ACK_HINT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch", + "EventCode": "0x1E", + "EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Lost Forward", + "EventCode": "0x1F", + "EventName": "UNC_I_MISC1.LOST_FWD", + "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Received Invalid", + "EventCode": "0x1F", + "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", + "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Received Invalid : Secondary received a transfer that did not have sufficient MESI state", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Received Valid", + "EventCode": "0x1F", + "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", + "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Received Valid : Secondary received a transfer that did have sufficient MESI state", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line", + "EventCode": "0x1f", + "EventName": "UNC_I_MISC1.SLOW_E", + "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Slow Transfer of E Line : Secondary received a transfer that did have sufficient MESI state", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line", + "EventCode": "0x1f", + "EventName": "UNC_I_MISC1.SLOW_I", + "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Slow Transfer of I Line : Snoop took cacheline ownership before write from data was committed.", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line", + "EventCode": "0x1f", + "EventName": "UNC_I_MISC1.SLOW_M", + "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Slow Transfer of M Line : Snoop took cacheline ownership before write from data was committed.", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line", + "EventCode": "0x1f", + "EventName": "UNC_I_MISC1.SLOW_S", + "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Slow Transfer of S Line : Secondary received a transfer that did not have sufficient MESI state", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Requests", + "EventCode": "0x14", + "EventName": "UNC_I_P2P_INSERTS", + "PerPkg": "1", + "PublicDescription": "P2P Requests : P2P requests from the ITC", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Occupancy", + "EventCode": "0x15", + "EventName": "UNC_I_P2P_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "P2P Occupancy : P2P B & S Queue Occupancy", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions : P2P completions", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions : match if local only", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.LOC", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions : match if local and target matches", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions : P2P Message", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.MSG", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions : P2P reads", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.RD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions : Match if remote only", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.REM", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions : match if remote and target matches", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "P2P Transactions : P2P Writes", + "EventCode": "0x13", + "EventName": "UNC_I_P2P_TRANSACTIONS.WR", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO", + "UMask": "0x7e", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache", + "UMask": "0x74", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache", + "UMask": "0x72", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache", + "UMask": "0x78", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that miss the IIO cache", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_MISS", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that miss the IIO cache", + "UMask": "0x71", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : Hit E or S", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_ES", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : Hit I", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_I", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : Hit M", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.HIT_M", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : Miss", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.MISS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : SnpCode", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPCODE", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : SnpData", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPDATA", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Snoop Responses : SnpInv", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.SNPINV", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count : Atomic", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.ATOMIC", + "PerPkg": "1", + "PublicDescription": "Inbound Transaction Count : Atomic : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of atomic transactions", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count : Other", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.OTHER", + "PerPkg": "1", + "PublicDescription": "Inbound Transaction Count : Other : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of 'other' kinds of transactions.", + "UMask": "0x20", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound Transaction Count : Writes", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.WRITES", + "PerPkg": "1", + "PublicDescription": "Inbound Transaction Count : Writes : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", + "UMask": "0x2", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound write (fast path) requests received by the IRP.", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "PerPkg": "1", + "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "AK Egress Allocations", + "EventCode": "0x0B", + "EventName": "UNC_I_TxC_AK_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL DRS Egress Cycles Full", + "EventCode": "0x05", + "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL DRS Egress Inserts", + "EventCode": "0x02", + "EventName": "UNC_I_TxC_BL_DRS_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL DRS Egress Occupancy", + "EventCode": "0x08", + "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCB Egress Cycles Full", + "EventCode": "0x06", + "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCB Egress Inserts", + "EventCode": "0x03", + "EventName": "UNC_I_TxC_BL_NCB_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCB Egress Occupancy", + "EventCode": "0x09", + "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCS Egress Cycles Full", + "EventCode": "0x07", + "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCS Egress Inserts", + "EventCode": "0x04", + "EventName": "UNC_I_TxC_BL_NCS_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "BL NCS Egress Occupancy", + "EventCode": "0x0A", + "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", + "EventCode": "0x1C", + "EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": ": Counts the number times when it is not possible to issue a request to the M2PCIe because there are no Egress Credits available on AD0, A1 or AD0&AD1 both. Stalls on both AD0 and AD1 will count as 2", + "Unit": "IRP" + }, + { + "BriefDescription": "No AD0 Egress Credits Stalls", + "EventCode": "0x1A", + "EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "No AD0 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD0 Egress Credits available.", + "Unit": "IRP" + }, + { + "BriefDescription": "No AD1 Egress Credits Stalls", + "EventCode": "0x1B", + "EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "No AD1 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD1 Egress Credits available.", + "Unit": "IRP" + }, + { + "BriefDescription": "No BL Egress Credit Stalls", + "EventCode": "0x1D", + "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", + "PerPkg": "1", + "PublicDescription": "No BL Egress Credit Stalls : Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "EventCode": "0x0D", + "EventName": "UNC_I_TxS_DATA_INSERTS_NCB", + "PerPkg": "1", + "PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Read Requests", + "EventCode": "0x0E", + "EventName": "UNC_I_TxS_DATA_INSERTS_NCS", + "PerPkg": "1", + "PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).", + "Unit": "IRP" + }, + { + "BriefDescription": "Outbound Request Queue Occupancy", + "EventCode": "0x0C", + "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Outbound Request Queue Occupancy : Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.", + "Unit": "IRP" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7", + "EventCode": "0x80", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10", + "EventCode": "0x81", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8", + "EventCode": "0x81", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9", + "EventCode": "0x81", + "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7", + "EventCode": "0x82", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10", + "EventCode": "0x83", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8", + "EventCode": "0x83", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9", + "EventCode": "0x83", + "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7", + "EventCode": "0x88", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10", + "EventCode": "0x89", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8", + "EventCode": "0x89", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9", + "EventCode": "0x89", + "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7", + "EventCode": "0x8A", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10", + "EventCode": "0x8B", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8", + "EventCode": "0x8B", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9", + "EventCode": "0x8B", + "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7", + "EventCode": "0x84", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10", + "EventCode": "0x85", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8", + "EventCode": "0x85", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9", + "EventCode": "0x85", + "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7", + "EventCode": "0x86", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10", + "EventCode": "0x87", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8", + "EventCode": "0x87", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9", + "EventCode": "0x87", + "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", + "EventCode": "0x8C", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10", + "EventCode": "0x8D", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8", + "EventCode": "0x8D", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9", + "EventCode": "0x8D", + "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7", + "EventCode": "0x8E", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10", + "EventCode": "0x8F", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8", + "EventCode": "0x8F", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9", + "EventCode": "0x8F", + "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC Bypass : Not Taken", + "EventCode": "0x22", + "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.NOT_TAKEN", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC Bypass : Taken", + "EventCode": "0x22", + "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.TAKEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC Bypass : Not Taken", + "EventCode": "0x21", + "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC Bypass : Taken", + "EventCode": "0x21", + "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Clockticks of the mesh to memory (M2M)", + "EventName": "UNC_M2M_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Clockticks", + "EventCode": "0xc0", + "EventName": "UNC_M2M_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles when direct to core mode, which bypasses the CHA, was disabled", + "EventCode": "0x24", + "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", + "EventCode": "0x60", + "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number of reads in which direct to core transaction was overridden", + "EventCode": "0x25", + "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Distress signal asserted : DPT Local", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_LOCAL", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Distress signal asserted : DPT Remote", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_NONLOCAL", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Distress signal asserted : DPT Stalled - IV", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_IV", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_NOCRD", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Distress signal asserted : Horizontal", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.HORZ", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Distress signal asserted : Vertical", + "EventCode": "0xAF", + "EventName": "UNC_M2M_DISTRESS_ASSERTED.VERT", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Down", + "EventCode": "0xBA", + "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Up", + "EventCode": "0xBA", + "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Left and Even", + "EventCode": "0xB6", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", + "EventCode": "0xB6", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Right and Even", + "EventCode": "0xB6", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", + "EventCode": "0xB6", + "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "EventCode": "0xBB", + "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "EventCode": "0xBB", + "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "EventCode": "0xBB", + "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "EventCode": "0xBB", + "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "EventCode": "0xB7", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "EventCode": "0xB7", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "EventCode": "0xB7", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "EventCode": "0xB7", + "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Left and Even", + "EventCode": "0xB8", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", + "EventCode": "0xB8", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Right and Even", + "EventCode": "0xB8", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", + "EventCode": "0xB8", + "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal IV Ring in Use : Left", + "EventCode": "0xB9", + "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Horizontal IV Ring in Use : Right", + "EventCode": "0xB9", + "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - All Channels", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.ALL", + "PerPkg": "1", + "UMask": "0x704", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch0", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH0_ALL", + "PerPkg": "1", + "UMask": "0x104", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch0", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR", + "PerPkg": "1", + "UMask": "0x140", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch0", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH0_ISOCH", + "PerPkg": "1", + "UMask": "0x102", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch0", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH0_NORMAL", + "PerPkg": "1", + "UMask": "0x101", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch1", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH1_ALL", + "PerPkg": "1", + "UMask": "0x204", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch1", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR", + "PerPkg": "1", + "UMask": "0x240", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch1", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH1_ISOCH", + "PerPkg": "1", + "UMask": "0x202", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch1", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.CH1_NORMAL", + "PerPkg": "1", + "UMask": "0x201", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : From TGR - All Channels", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.FROM_TGR", + "PerPkg": "1", + "UMask": "0x740", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - All Channels", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.ISOCH", + "PerPkg": "1", + "UMask": "0x702", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - All Channels", + "EventCode": "0x37", + "EventName": "UNC_M2M_IMC_READS.NORMAL", + "PerPkg": "1", + "UMask": "0x701", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : All Writes - All Channels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.ALL", + "PerPkg": "1", + "UMask": "0x1c10", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_ALL", + "PerPkg": "1", + "UMask": "0x410", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL", + "PerPkg": "1", + "UMask": "0x401", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH", + "PerPkg": "1", + "UMask": "0x404", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL", + "PerPkg": "1", + "UMask": "0x402", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch0", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH", + "PerPkg": "1", + "UMask": "0x408", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_ALL", + "PerPkg": "1", + "UMask": "0x810", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL", + "PerPkg": "1", + "UMask": "0x801", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH", + "PerPkg": "1", + "UMask": "0x804", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL", + "PerPkg": "1", + "UMask": "0x802", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch1", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH", + "PerPkg": "1", + "UMask": "0x808", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : From TGR - All Channels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FROM_TGR", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - All Channels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FULL", + "PerPkg": "1", + "UMask": "0x1c01", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - All Channels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH", + "PerPkg": "1", + "UMask": "0x1c04", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - All Channels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.NI_MISS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - All Channels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", + "PerPkg": "1", + "UMask": "0x1c02", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - All Channels", + "EventCode": "0x38", + "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH", + "PerPkg": "1", + "UMask": "0x1c08", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts", + "EventCode": "0x64", + "EventName": "UNC_M2M_MIRR_WRQ_INSERTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy", + "EventCode": "0x65", + "EventName": "UNC_M2M_MIRR_WRQ_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0", + "EventCode": "0xE6", + "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1", + "EventCode": "0xE6", + "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Number Packet Header Matches : MC Match", + "EventCode": "0x4C", + "EventName": "UNC_M2M_PKT_MATCH.MC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Number Packet Header Matches : Mesh Match", + "EventCode": "0x4C", + "EventName": "UNC_M2M_PKT_MATCH.MESH", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS", + "EventCode": "0x73", + "EventName": "UNC_M2M_PREFCAM_CIS_DROPS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Full : All Channels", + "EventCode": "0x6B", + "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.ALLCH", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Full : Channel 0", + "EventCode": "0x6B", + "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Full : Channel 1", + "EventCode": "0x6B", + "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Not Empty : All Channels", + "EventCode": "0x6C", + "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.ALLCH", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 0", + "EventCode": "0x6C", + "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 1", + "EventCode": "0x6C", + "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA0_INVAL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA1_INVAL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_MISS_INVAL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_RSP_PDRESET", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA0_INVAL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA1_INVAL", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_MISS_INVAL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Deallocs", + "EventCode": "0x6E", + "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_RSP_PDRESET", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped : XPT - Ch 0", + "EventCode": "0x6F", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped : XPT - Ch 1", + "EventCode": "0x6F", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped : XPT - All Channels", + "EventCode": "0x6f", + "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH", + "PerPkg": "1", + "UMask": "0x15", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - Ch 0", + "EventCode": "0x74", + "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 0", + "EventCode": "0x74", + "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPTUPI", + "PerPkg": "1", + "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 0", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - Ch 1", + "EventCode": "0x74", + "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 1", + "EventCode": "0x74", + "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPTUPI", + "PerPkg": "1", + "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 2", + "EventCode": "0x74", + "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH2_XPTUPI", + "PerPkg": "1", + "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 2", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- All Channels", + "EventCode": "0x74", + "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPTUPI_ALLCH", + "PerPkg": "1", + "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - All Channels", + "UMask": "0x15", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - All Channels", + "EventCode": "0x74", + "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPT_ALLCH", + "PerPkg": "1", + "UMask": "0x15", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT - Ch 0", + "EventCode": "0x75", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 0", + "EventCode": "0x75", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPTUPI", + "PerPkg": "1", + "PublicDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 0", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT - Ch 1", + "EventCode": "0x75", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 1", + "EventCode": "0x75", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPTUPI", + "PerPkg": "1", + "PublicDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 2", + "EventCode": "0x75", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH2_XPTUPI", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - All Channels", + "EventCode": "0x75", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPTUPI_ALLCH", + "PerPkg": "1", + "UMask": "0x15", + "Unit": "M2M" + }, + { + "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT - All Channels", + "EventCode": "0x75", + "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPT_ALLCH", + "PerPkg": "1", + "UMask": "0x15", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.ERRORBLK_RxC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.NOT_PF_SAD_REGION", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_AD_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_FULL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_HIT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_SECURE_DROP", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.RPQ_PROXY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.STOP_B2B", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.WPQ_PROXY", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "EventCode": "0x70", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.XPT_THRESH", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.ERRORBLK_RxC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.NOT_PF_SAD_REGION", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_AD_CRD", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_FULL", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_HIT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_SECURE_DROP", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.RPQ_PROXY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.STOP_B2B", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.WPQ_PROXY", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "EventCode": "0x71", + "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.XPT_THRESH", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0", + "EventCode": "0x6D", + "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1", + "EventCode": "0x6D", + "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels", + "EventCode": "0x6D", + "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH", + "PerPkg": "1", + "UMask": "0x15", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Occupancy : All Channels", + "EventCode": "0x6A", + "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Occupancy : Channel 0", + "EventCode": "0x6A", + "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Prefetch CAM Occupancy : Channel 1", + "EventCode": "0x6A", + "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": ": All Channels", + "EventCode": "0x76", + "EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "M2M" + }, + { + "BriefDescription": ": Channel 0", + "EventCode": "0x76", + "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": ": Channel 1", + "EventCode": "0x76", + "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_RxC_CYCLES_NE", + "EventCode": "0x79", + "EventName": "UNC_M2M_PREFCAM_RxC_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "EventCode": "0x7A", + "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", + "EventCode": "0x7A", + "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", + "EventCode": "0x7A", + "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_RxC_INSERTS", + "EventCode": "0x78", + "EventName": "UNC_M2M_PREFCAM_RxC_INSERTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", + "EventCode": "0x77", + "EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD", + "EventCode": "0xAC", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK", + "EventCode": "0xAC", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL", + "EventCode": "0xAC", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV", + "EventCode": "0xAC", + "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : AD", + "EventCode": "0xAA", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core", + "EventCode": "0xAA", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.", + "EventCode": "0xAA", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.AKC", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core", + "EventCode": "0xAA", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.", + "EventCode": "0xAA", + "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : AD", + "EventCode": "0xAD", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : AK", + "EventCode": "0xAD", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1", + "EventCode": "0xAD", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : BL", + "EventCode": "0xAD", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : IV", + "EventCode": "0xAD", + "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : AD", + "EventCode": "0xAB", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core", + "EventCode": "0xAB", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring", + "EventCode": "0xAB", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AKC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core", + "EventCode": "0xAB", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.", + "EventCode": "0xAB", + "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Source Throttle", + "EventCode": "0xae", + "EventName": "UNC_M2M_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 0", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 1", + "EventCode": "0x43", + "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 0", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 1", + "EventCode": "0x44", + "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Full", + "EventCode": "0x04", + "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Not Empty", + "EventCode": "0x03", + "EventName": "UNC_M2M_RxC_AD_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Allocations", + "EventCode": "0x01", + "EventName": "UNC_M2M_RxC_AD_INSERTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Occupancy", + "EventCode": "0x02", + "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches", + "EventCode": "0x77", + "EventName": "UNC_M2M_RxC_AD_PREF_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations", + "EventCode": "0x5C", + "EventName": "UNC_M2M_RxC_AK_WR_CMP", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Full", + "EventCode": "0x08", + "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Not Empty", + "EventCode": "0x07", + "EventName": "UNC_M2M_RxC_BL_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Allocations", + "EventCode": "0x05", + "EventName": "UNC_M2M_RxC_BL_INSERTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Ingress (from CMS) Occupancy", + "EventCode": "0x06", + "EventName": "UNC_M2M_RxC_BL_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - All", + "EventCode": "0xE5", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Credited", + "EventCode": "0xE5", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", + "EventCode": "0xE5", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - All", + "EventCode": "0xE5", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Credited", + "EventCode": "0xE5", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", + "EventCode": "0xE5", + "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - All", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - Credited", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AK", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - All", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - Credited", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Bypass : IV", + "EventCode": "0xE2", + "EventName": "UNC_M2M_RxR_BYPASS.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - All", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Credited", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : AK", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - All", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Credited", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : IFV - Credited", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation : IV", + "EventCode": "0xE3", + "EventName": "UNC_M2M_RxR_CRD_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Injection Starvation", + "EventCode": "0xe4", + "EventName": "UNC_M2M_RxR_CRD_STARVED_1", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - All", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - Credited", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AK", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - All", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - Credited", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Allocations : IV", + "EventCode": "0xE1", + "EventName": "UNC_M2M_RxR_INSERTS.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - All", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AK", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - All", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : IV", + "EventCode": "0xE0", + "EventName": "UNC_M2M_RxR_OCCUPANCY.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7", + "EventCode": "0xD0", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7", + "EventCode": "0xD2", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7", + "EventCode": "0xD4", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7", + "EventCode": "0xD6", + "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10", + "EventCode": "0xD1", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8", + "EventCode": "0xD1", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9", + "EventCode": "0xD1", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10", + "EventCode": "0xD3", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8", + "EventCode": "0xD3", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9", + "EventCode": "0xD3", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10", + "EventCode": "0xD5", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8", + "EventCode": "0xD5", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9", + "EventCode": "0xD5", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10", + "EventCode": "0xD7", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8", + "EventCode": "0xD7", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9", + "EventCode": "0xD7", + "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Number AD Ingress Credits", + "EventCode": "0x41", + "EventName": "UNC_M2M_TGR_AD_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Number BL Ingress Credits", + "EventCode": "0x42", + "EventName": "UNC_M2M_TGR_BL_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Full : Channel 0", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_FULL.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Full : Channel 1", + "EventCode": "0x45", + "EventName": "UNC_M2M_TRACKER_FULL.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Inserts : Channel 0", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Inserts : Channel 1", + "EventCode": "0x49", + "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Not Empty : Channel 0", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_NE.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Cycles Not Empty : Channel 1", + "EventCode": "0x46", + "EventName": "UNC_M2M_TRACKER_NE.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Occupancy : Channel 0", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Tracker Occupancy : Channel 1", + "EventCode": "0x47", + "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Credit Acquired", + "EventCode": "0x0d", + "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Credits Occupancy", + "EventCode": "0x0e", + "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Full", + "EventCode": "0x0c", + "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Not Empty", + "EventCode": "0x0b", + "EventName": "UNC_M2M_TxC_AD_CYCLES_NE", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Allocations", + "EventCode": "0x09", + "EventName": "UNC_M2M_TxC_AD_INSERTS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No AD Egress (to CMS) Credits", + "EventCode": "0x0f", + "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits", + "EventCode": "0x10", + "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AD Egress (to CMS) Occupancy", + "EventCode": "0x0A", + "EventName": "UNC_M2M_TxC_AD_OCCUPANCY", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound Ring Transactions on AK : CRD Transactions to Cbo", + "EventCode": "0x39", + "EventName": "UNC_M2M_TxC_AK.CRD_CBO", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound Ring Transactions on AK : NDR Transactions", + "EventCode": "0x39", + "EventName": "UNC_M2M_TxC_AK.NDR", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AKC Credits", + "EventCode": "0x5F", + "EventName": "UNC_M2M_TxC_AKC_CREDITS", + "PerPkg": "1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side", + "EventCode": "0x1D", + "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side", + "EventCode": "0x1D", + "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full : All", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Near Side", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Far Side", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1", + "PerPkg": "1", + "UMask": "0x88", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1", + "PerPkg": "1", + "UMask": "0xa0", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Full", + "EventCode": "0x14", + "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1", + "PerPkg": "1", + "UMask": "0x90", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty : All", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Near Side", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Far Side", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Not Empty", + "EventCode": "0x13", + "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations : All", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Near Side", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Far Side", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Allocations", + "EventCode": "0x11", + "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side", + "EventCode": "0x1F", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side", + "EventCode": "0x1F", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side", + "EventCode": "0x20", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side", + "EventCode": "0x20", + "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy : All", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Near Side", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Far Side", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "AK Egress (to CMS) Occupancy", + "EventCode": "0x12", + "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Cache", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_CACHE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Core", + "EventCode": "0x40", + "EventName": "UNC_M2M_TxC_BL.DRS_CORE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side", + "EventCode": "0x19", + "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side", + "EventCode": "0x19", + "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Full : All", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Near Side", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Far Side", + "EventCode": "0x18", + "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Not Empty : All", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Near Side", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Far Side", + "EventCode": "0x17", + "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Allocations : All", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL", + "PerPkg": "1", + "UMask": "0x3", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Near Side", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Far Side", + "EventCode": "0x15", + "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side", + "EventCode": "0x1B", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side", + "EventCode": "0x1B", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side", + "EventCode": "0x1C", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side", + "EventCode": "0x1C", + "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - All", + "EventCode": "0xA6", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", + "EventCode": "0xA6", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", + "EventCode": "0xA6", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - All", + "EventCode": "0xA6", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", + "EventCode": "0xA6", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", + "EventCode": "0xA6", + "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - All", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AK", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - All", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : IV", + "EventCode": "0xA7", + "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV", + "EventCode": "0xA2", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV", + "EventCode": "0xA3", + "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AK", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : IV", + "EventCode": "0xA1", + "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AK", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : IV", + "EventCode": "0xA4", + "EventName": "UNC_M2M_TxR_HORZ_NACK.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AK", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : IV", + "EventCode": "0xA0", + "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x80", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV", + "EventCode": "0xA5", + "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "EventCode": "0x9C", + "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", + "EventCode": "0x9D", + "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", + "EventCode": "0x9E", + "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1", + "EventCode": "0x95", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1", + "EventCode": "0x97", + "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2M_TxR_VERT_INSERTS0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : IV", + "EventCode": "0x98", + "EventName": "UNC_M2M_TxR_VERT_NACK0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", + "EventCode": "0x99", + "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x40", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : IV", + "EventCode": "0x9A", + "EventName": "UNC_M2M_TxR_VERT_STARVED0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", + "EventCode": "0x9B", + "EventName": "UNC_M2M_TxR_VERT_STARVED1.TGC", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Down and Even", + "EventCode": "0xB0", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Down and Odd", + "EventCode": "0xB0", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Up and Even", + "EventCode": "0xB0", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Up and Odd", + "EventCode": "0xB0", + "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Down and Even", + "EventCode": "0xB4", + "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", + "EventCode": "0xB4", + "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Up and Even", + "EventCode": "0xB4", + "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", + "EventCode": "0xB4", + "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Down and Even", + "EventCode": "0xB1", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Down and Odd", + "EventCode": "0xB1", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Up and Even", + "EventCode": "0xB1", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Up and Odd", + "EventCode": "0xB1", + "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Down and Even", + "EventCode": "0xB2", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Down and Odd", + "EventCode": "0xB2", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Up and Even", + "EventCode": "0xB2", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Up and Odd", + "EventCode": "0xB2", + "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical IV Ring in Use : Down", + "EventCode": "0xB3", + "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical IV Ring in Use : Up", + "EventCode": "0xB3", + "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Down and Even", + "EventCode": "0xB5", + "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", + "EventCode": "0xB5", + "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Up and Even", + "EventCode": "0xB5", + "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", + "EventCode": "0xB5", + "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "WPQ Flush : Channel 0", + "EventCode": "0x58", + "EventName": "UNC_M2M_WPQ_FLUSH.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "WPQ Flush : Channel 1", + "EventCode": "0x58", + "EventName": "UNC_M2M_WPQ_FLUSH.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 2", + "EventCode": "0x4D", + "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 0", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 1", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 2", + "EventCode": "0x4E", + "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Full : Channel 0", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WR_TRACKER_FULL.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Full : Channel 1", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WR_TRACKER_FULL.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Full : Mirror", + "EventCode": "0x4A", + "EventName": "UNC_M2M_WR_TRACKER_FULL.MIRR", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts : Channel 0", + "EventCode": "0x56", + "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Inserts : Channel 1", + "EventCode": "0x56", + "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty : Channel 0", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WR_TRACKER_NE.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty : Channel 1", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WR_TRACKER_NE.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty : Mirror", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Cycles Not Empty", + "EventCode": "0x4B", + "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0", + "EventCode": "0x63", + "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1", + "EventCode": "0x63", + "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 0", + "EventCode": "0x62", + "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 1", + "EventCode": "0x62", + "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy : Channel 0", + "EventCode": "0x55", + "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy : Channel 1", + "EventCode": "0x55", + "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy : Mirror", + "EventCode": "0x55", + "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy", + "EventCode": "0x55", + "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_NONTGR", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Occupancy", + "EventCode": "0x55", + "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_PWR", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Posted Inserts : Channel 0", + "EventCode": "0x5E", + "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Posted Inserts : Channel 1", + "EventCode": "0x5E", + "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Posted Occupancy : Channel 0", + "EventCode": "0x5D", + "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2M" + }, + { + "BriefDescription": "Write Tracker Posted Occupancy : Channel 1", + "EventCode": "0x5D", + "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2M" + }, + { + "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", + "EventCode": "0xff", + "EventName": "UNC_U_CLOCKTICKS", + "PerPkg": "1", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received : Doorbell", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received : Interrupt", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.INT_PRIO", + "PerPkg": "1", + "PublicDescription": "Message Received : Interrupt : Interrupts", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received : IPI", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", + "PerPkg": "1", + "PublicDescription": "Message Received : IPI : Inter Processor Interrupts", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received : MSI", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", + "PerPkg": "1", + "PublicDescription": "Message Received : MSI : Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Message Received : VLW", + "EventCode": "0x42", + "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", + "PerPkg": "1", + "PublicDescription": "Message Received : VLW : Virtual Logical Wire (legacy) message were received from Uncore.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "IDI Lock/SplitLock Cycles", + "EventCode": "0x44", + "EventName": "UNC_U_LOCK_CYCLES", + "PerPkg": "1", + "PublicDescription": "IDI Lock/SplitLock Cycles : Number of times an IDI Lock/SplitLock sequence was started", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", + "EventCode": "0x4D", + "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", + "EventCode": "0x4D", + "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", + "EventCode": "0x4D", + "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", + "EventCode": "0x4D", + "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", + "EventCode": "0x4E", + "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", + "EventCode": "0x4F", + "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", + "EventCode": "0x4F", + "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK", + "EventCode": "0x45", + "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", + "PerPkg": "1", + "PublicDescription": "Cycles PHOLD Assert to Ack : Assert to ACK : PHOLD cycles.", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_RACU_DRNG.RDRAND", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.RDRAND", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UBOX" + }, + { + "BriefDescription": "UNC_U_RACU_DRNG.RDSEED", + "EventCode": "0x4C", + "EventName": "UNC_U_RACU_DRNG.RDSEED", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UBOX" + }, + { + "BriefDescription": "RACU Request", + "EventCode": "0x46", + "EventName": "UNC_U_RACU_REQUESTS", + "PerPkg": "1", + "PublicDescription": "RACU Request : Number outstanding register requests within message channel tracker", + "Unit": "UBOX" + } +] diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-io.json b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-io.json new file mode 100644 index 000000000000..996028071ee4 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-io.json @@ -0,0 +1,8944 @@ +[ + { + "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0", + "EventCode": "0x83", + "EventName": "LLC_MISSES.PCIE_READ", + "FCMask": "0x07", + "Filter": "ch_mask=0x1f", + "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "MetricName": "LLC_MISSES.PCIE_READ", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "ScaleUnit": "4Bytes", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0", + "EventCode": "0x83", + "EventName": "LLC_MISSES.PCIE_WRITE", + "FCMask": "0x07", + "Filter": "ch_mask=0x1f", + "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "MetricName": "LLC_MISSES.PCIE_WRITE", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "ScaleUnit": "4Bytes", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN", + "PerPkg": "1", + "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN", + "UMask": "0x20", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN", + "PerPkg": "1", + "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN", + "UMask": "0x21", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN", + "PerPkg": "1", + "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN", + "UMask": "0x22", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN", + "PerPkg": "1", + "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN", + "UMask": "0x23", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN", + "PerPkg": "1", + "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN", + "UMask": "0x24", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN", + "PerPkg": "1", + "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN", + "UMask": "0x25", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN", + "PerPkg": "1", + "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN", + "UMask": "0x26", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN", + "PerPkg": "1", + "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN", + "UMask": "0x27", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller", + "EventCode": "0x01", + "EventName": "UNC_IIO_CLOCKTICKS", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Free running counter that increments for IIO clocktick", + "EventCode": "0xff", + "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", + "PerPkg": "1", + "PublicDescription": "Free running counter that increments for integrated IO (IIO) traffic controller clockticks", + "UMask": "0x10", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts : All Ports", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0xff", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7", + "UMask": "0x3", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7", + "UMask": "0xff", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7", + "UMask": "0xff", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 1", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 2", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 3", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 3 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 4", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 4 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 5", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 5 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 6", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 6 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 7", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 7 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth reading at IIO, part 0", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth reading at IIO, part 1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth reading at IIO, part 2", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth reading at IIO, part 3", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO, part 0", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO, part 1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO, part 2", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "PCI Express bandwidth writing at IIO, part 3", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Messages", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests : Passing data to be written", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests : Passing data to be written : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests : Issuing final read or write of line", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests : Issuing final read or write of line : How often different queues (e.g. channel / fc) ask to send request into pipeline", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests : Processing response from IOMMU", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests : Processing response from IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests : Issuing to IOMMU", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests : Issuing to IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests : Request Ownership", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests : Request Ownership : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests : Writing line", + "EventCode": "0x86", + "EventName": "UNC_IIO_INBOUND_ARB_REQ.WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests : Writing line : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests granted : Passing data to be written", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.DATA", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests granted : Passing data to be written : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests granted : Issuing final read or write of line", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests granted : Issuing final read or write of line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests granted : Processing response from IOMMU", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests granted : Processing response from IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests granted : Issuing to IOMMU", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests granted : Issuing to IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests granted : Request Ownership", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests granted : Request Ownership : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Incoming arbitration requests granted : Writing line", + "EventCode": "0x87", + "EventName": "UNC_IIO_INBOUND_ARB_WON.WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Incoming arbitration requests granted : Writing line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOTLB Hits to a 1G Page", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.1G_HITS", + "PerPkg": "1", + "PublicDescription": ": IOTLB Hits to a 1G Page : Counts if a transaction to a 1G page, on its first lookup, hits the IOTLB.", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOTLB Hits to a 2M Page", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.2M_HITS", + "PerPkg": "1", + "PublicDescription": ": IOTLB Hits to a 2M Page : Counts if a transaction to a 2M page, on its first lookup, hits the IOTLB.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOTLB Hits to a 4K Page", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.4K_HITS", + "PerPkg": "1", + "PublicDescription": ": IOTLB Hits to a 4K Page : Counts if a transaction to a 4K page, on its first lookup, hits the IOTLB.", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOTLB lookups all", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS", + "PerPkg": "1", + "PublicDescription": ": IOTLB lookups all : Some transactions have to look up IOTLB multiple times. Counts every time a request looks up IOTLB.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": ": Context cache hits", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS", + "PerPkg": "1", + "PublicDescription": ": Context cache hits : Counts each time a first look up of the transaction hits the RCC.", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": ": Context cache lookups", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS", + "PerPkg": "1", + "PublicDescription": ": Context cache lookups : Counts each time a transaction looks up root context cache.", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOTLB lookups first", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS", + "PerPkg": "1", + "PublicDescription": ": IOTLB lookups first : Some transactions have to look up IOTLB multiple times. Counts the first time a request looks up IOTLB.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOTLB Fills (same as IOTLB miss)", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.MISSES", + "PerPkg": "1", + "PublicDescription": ": IOTLB Fills (same as IOTLB miss) : When a transaction misses IOTLB, it does a page walk to look up memory and bring in the relevant page translation. Counts when this page translation is written to IOTLB.", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": ": Cycles PWT full", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.CYC_PWT_FULL", + "PerPkg": "1", + "PublicDescription": ": Cycles PWT full : Counts cycles the IOMMU has reached its maximum limit for outstanding page walks.", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": ": IOMMU memory access", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES", + "PerPkg": "1", + "PublicDescription": ": IOMMU memory access : IOMMU sends out memory fetches when it misses the cache look up which is indicated by this signal. M2IOSF only uses low priority channel", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": ": PWC Hit to a 1G page", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS", + "PerPkg": "1", + "PublicDescription": ": PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": ": PWC Hit to a 2M page", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS", + "PerPkg": "1", + "PublicDescription": ": PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": ": PWC Hit to a 4K page", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_4K_HITS", + "PerPkg": "1", + "PublicDescription": ": PWC Hit to a 4K page : Counts each time a transaction's first look up hits the SLPWC at the 4K level", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": ": PWT Hit to a 256T page", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS", + "PerPkg": "1", + "PublicDescription": ": PWT Hit to a 256T page : Counts each time a transaction's first look up hits the SLPWC at the 512G level", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": ": PageWalk cache fill", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS", + "PerPkg": "1", + "PublicDescription": ": PageWalk cache fill : When a transaction misses SLPWC, it does a page walk to look up memory and bring in the relevant page translation. When this page translation is written to SLPWC, ObsPwcFillValid_nnnH is asserted.", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": ": PageWalk cache lookup", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS", + "PerPkg": "1", + "PublicDescription": ": PageWalk cache lookup : Counts each time a transaction looks up second level page walk cache.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": ": Interrupt Entry cache hit", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS", + "PerPkg": "1", + "PublicDescription": ": Interrupt Entry cache hit : Counts each time a transaction's first look up hits the IEC.", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": ": Interrupt Entry cache lookup", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS", + "PerPkg": "1", + "PublicDescription": ": Interrupt Entry cache lookup : Counts the number of transaction looks up that interrupt remapping cache.", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": ": Device-selective Context cache invalidation cycles", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DEVICE", + "PerPkg": "1", + "PublicDescription": ": Device-selective Context cache invalidation cycles : Counts number of Device selective context cache invalidation events", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": ": Domain-selective Context cache invalidation cycles", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DOMAIN", + "PerPkg": "1", + "PublicDescription": ": Domain-selective Context cache invalidation cycles : Counts number of Domain selective context cache invalidation events", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": ": Context cache global invalidation cycles", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_GBL", + "PerPkg": "1", + "PublicDescription": ": Context cache global invalidation cycles : Counts number of Context Cache global invalidation events", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": ": Domain-selective IOTLB invalidation cycles", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_DOMAIN", + "PerPkg": "1", + "PublicDescription": ": Domain-selective IOTLB invalidation cycles : Counts number of Domain selective invalidation events", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": ": Global IOTLB invalidation cycles", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_GBL", + "PerPkg": "1", + "PublicDescription": ": Global IOTLB invalidation cycles : Indicates that IOMMU is doing global invalidation.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": ": Page-selective IOTLB invalidation cycles", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PAGE", + "PerPkg": "1", + "PublicDescription": ": Page-selective IOTLB invalidation cycles : Counts number of Page-selective within Domain Invalidation events", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0", + "PerPkg": "1", + "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus : Asserted if all bits specified by mask match", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1", + "PerPkg": "1", + "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if all bits specified by mask match", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1", + "PerPkg": "1", + "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if all bits specified by mask match", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus : PCIE bus", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1", + "PerPkg": "1", + "PublicDescription": "AND Mask/match for debug bus : PCIE bus : Asserted if all bits specified by mask match", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1", + "PerPkg": "1", + "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if all bits specified by mask match", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)", + "EventCode": "0x02", + "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1", + "PerPkg": "1", + "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if all bits specified by mask match", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0", + "PerPkg": "1", + "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus : Asserted if any bits specified by mask match", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1", + "PerPkg": "1", + "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if any bits specified by mask match", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1", + "PerPkg": "1", + "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if any bits specified by mask match", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus : PCIE bus", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1", + "PerPkg": "1", + "PublicDescription": "OR Mask/match for debug bus : PCIE bus : Asserted if any bits specified by mask match", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1", + "PerPkg": "1", + "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if any bits specified by mask match", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)", + "EventCode": "0x03", + "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1", + "PerPkg": "1", + "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if any bits specified by mask match", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Counting disabled", + "EventCode": "0x80", + "EventName": "UNC_IIO_NOTHING", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Occupancy of outbound request queue : To device", + "EventCode": "0xC5", + "EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Occupancy of outbound request queue : To device : Counts number of outbound requests/completions IIO is currently processing", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": ": Passing data to be written", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": ": Passing data to be written : Only for posted requests", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": ": Issuing final read or write of line", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": ": Processing response from IOMMU", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": ": Issuing to IOMMU", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": ": Request Ownership", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": ": Request Ownership : Only for posted requests", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": ": Writing line", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": ": Writing line : Only for posted requests", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number requests sent to PCIe from main die : From IRP", + "EventCode": "0xC2", + "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.IRP", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Number requests sent to PCIe from main die : From IRP : Captures Posted/Non-posted allocations from IRP. i.e. either non-confined P2P traffic or from the CPU", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number requests sent to PCIe from main die : From ITC", + "EventCode": "0xC2", + "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.ITC", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Number requests sent to PCIe from main die : From ITC : Confined P2P", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number requests sent to PCIe from main die : Completion allocations", + "EventCode": "0xc2", + "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.PREALLOC", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number requests PCIe makes of the main die : Drop request", + "EventCode": "0x85", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU.ALL.DROP", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Number requests PCIe makes of the main die : Drop request : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU. : Packet error detected, must be dropped", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number requests PCIe makes of the main die : All", + "EventCode": "0x85", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Abort", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Confined P2P", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Local P2P", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Multi-cast", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Memory", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : MsgB", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Remote P2P", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Num requests sent by PCIe - by target : Ubox", + "EventCode": "0x8E", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "ITC address map 1", + "EventCode": "0x8F", + "EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU", + "PerPkg": "1", + "Unit": "IIO" + }, + { + "BriefDescription": "Outbound cacheline requests issued : 64B requests issued to device", + "EventCode": "0xD0", + "EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Outbound cacheline requests issued : 64B requests issued to device : Each outbound cacheline granular request may need to make multiple passes through the pipeline. Each time a cacheline completes all its passes it advances line", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Outbound TLP (transaction layer packet) requests issued : To device", + "EventCode": "0xD1", + "EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Outbound TLP (transaction layer packet) requests issued : To device : Each time an outbound completes all its passes it advances the pointer", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "PWT occupancy", + "EventCode": "0x42", + "EventName": "UNC_IIO_PWT_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "PWT occupancy : Indicates how many page walks are outstanding at any point in time.", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request - cacheline complete : Passing data to be written", + "EventCode": "0x91", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request - cacheline complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request - cacheline complete : Issuing final read or write of line", + "EventCode": "0x91", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request - cacheline complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request - cacheline complete : Request Ownership", + "EventCode": "0x91", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request - cacheline complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request - cacheline complete : Writing line", + "EventCode": "0x91", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request - cacheline complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request complete : Passing data to be written", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.DATA", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request complete : Issuing final read or write of line", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request complete : Processing response from IOMMU", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request complete : Processing response from IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request complete : Issuing to IOMMU", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request complete : Issuing to IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request complete : Request Ownership", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request complete : Writing line", + "EventCode": "0x92", + "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request - pass complete : Passing data to be written", + "EventCode": "0x90", + "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request - pass complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request - pass complete : Issuing final read or write of line", + "EventCode": "0x90", + "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request - pass complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request - pass complete : Request Ownership", + "EventCode": "0x90", + "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request - pass complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Request - pass complete : Writing line", + "EventCode": "0x90", + "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "PCIe Request - pass complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Symbol Times on Link", + "EventCode": "0x82", + "EventName": "UNC_IIO_SYMBOL_TIMES", + "PerPkg": "1", + "PublicDescription": "Symbol Times on Link : Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Messages", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x100", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x200", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7", + "EventCode": "0x80", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10", + "EventCode": "0x81", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8", + "EventCode": "0x81", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9", + "EventCode": "0x81", + "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7", + "EventCode": "0x82", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10", + "EventCode": "0x83", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8", + "EventCode": "0x83", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9", + "EventCode": "0x83", + "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7", + "EventCode": "0x88", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10", + "EventCode": "0x89", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8", + "EventCode": "0x89", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9", + "EventCode": "0x89", + "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7", + "EventCode": "0x8a", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10", + "EventCode": "0x8b", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8", + "EventCode": "0x8b", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9", + "EventCode": "0x8b", + "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7", + "EventCode": "0x84", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10", + "EventCode": "0x85", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8", + "EventCode": "0x85", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9", + "EventCode": "0x85", + "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7", + "EventCode": "0x86", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10", + "EventCode": "0x87", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8", + "EventCode": "0x87", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9", + "EventCode": "0x87", + "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", + "EventCode": "0x8c", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10", + "EventCode": "0x8d", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8", + "EventCode": "0x8d", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9", + "EventCode": "0x8d", + "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR0", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR1", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR2", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR3", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR4", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR5", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR6", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7", + "EventCode": "0x8e", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR7", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10", + "EventCode": "0x8f", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR10", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8", + "EventCode": "0x8f", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR8", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9", + "EventCode": "0x8f", + "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR9", + "PerPkg": "1", + "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Clockticks of the mesh to PCI (M2P)", + "EventCode": "0x01", + "EventName": "UNC_M2P_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Clockticks", + "EventCode": "0xc0", + "EventName": "UNC_M2P_CMS_CLOCKTICKS", + "PerPkg": "1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Distress signal asserted : DPT Local", + "EventCode": "0xaf", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_LOCAL", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Distress signal asserted : DPT Remote", + "EventCode": "0xaf", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_NONLOCAL", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Distress signal asserted : DPT Stalled - IV", + "EventCode": "0xaf", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_IV", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit", + "EventCode": "0xaf", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_NOCRD", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Distress signal asserted : Horizontal", + "EventCode": "0xaf", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.HORZ", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Distress signal asserted : Vertical", + "EventCode": "0xaf", + "EventName": "UNC_M2P_DISTRESS_ASSERTED.VERT", + "PerPkg": "1", + "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Down", + "EventCode": "0xba", + "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN", + "PerPkg": "1", + "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress Blocking due to Ordering requirements : Up", + "EventCode": "0xba", + "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP", + "PerPkg": "1", + "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Left and Even", + "EventCode": "0xb6", + "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", + "EventCode": "0xb6", + "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Right and Even", + "EventCode": "0xb6", + "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", + "EventCode": "0xb6", + "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "EventCode": "0xbb", + "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "EventCode": "0xbb", + "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "EventCode": "0xbb", + "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "EventCode": "0xbb", + "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "EventCode": "0xb7", + "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "EventCode": "0xb7", + "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "EventCode": "0xb7", + "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "EventCode": "0xb7", + "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Left and Even", + "EventCode": "0xb8", + "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", + "EventCode": "0xb8", + "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Right and Even", + "EventCode": "0xb8", + "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", + "EventCode": "0xb8", + "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "PerPkg": "1", + "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal IV Ring in Use : Left", + "EventCode": "0xb9", + "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.LEFT", + "PerPkg": "1", + "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Horizontal IV Ring in Use : Right", + "EventCode": "0xb9", + "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.RIGHT", + "PerPkg": "1", + "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", + "EventCode": "0x33", + "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS", + "EventCode": "0x34", + "EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the DRS message class.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB", + "EventCode": "0x34", + "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCB message class.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS", + "EventCode": "0x34", + "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCS message class.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1", + "EventCode": "0x32", + "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1", + "PerPkg": "1", + "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCB", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCS", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCB", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCS", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCB", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCS", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCB", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCS", + "EventCode": "0x46", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCB", + "EventCode": "0x47", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCS", + "EventCode": "0x47", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCB", + "EventCode": "0x47", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCS", + "EventCode": "0x47", + "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCB", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCS", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCB", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCS", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCB", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCS", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS", + "EventCode": "0x19", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCB", + "EventCode": "0x1a", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCS", + "EventCode": "0x1a", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCB", + "EventCode": "0x1a", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCS", + "EventCode": "0x1a", + "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Shared Credits Returned : Agent0", + "EventCode": "0x17", + "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Shared Credits Returned : Agent1", + "EventCode": "0x17", + "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local P2P Shared Credits Returned : Agent2", + "EventCode": "0x17", + "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent0", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent1", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent2", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent3", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent4", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent5", + "EventCode": "0x44", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCB", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCS", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCB", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCS", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCB", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCS", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCB", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCS", + "EventCode": "0x40", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCB", + "EventCode": "0x41", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCS", + "EventCode": "0x41", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCB", + "EventCode": "0x41", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCS", + "EventCode": "0x41", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCB", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCS", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCB", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCS", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCB", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCS", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCB", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCS", + "EventCode": "0x4a", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCB", + "EventCode": "0x4b", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCS", + "EventCode": "0x4b", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCB", + "EventCode": "0x4b", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCS", + "EventCode": "0x4b", + "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0", + "EventCode": "0xe6", + "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1", + "EventCode": "0xe6", + "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "P2P Credit Occupancy : All", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "P2P Credit Occupancy : Local NCB", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "P2P Credit Occupancy : Local NCS", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "P2P Credit Occupancy : Remote NCB", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "P2P Credit Occupancy : Remote NCS", + "EventCode": "0x14", + "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Dedicated Credits Received : All", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Dedicated Credits Received : Local NCB", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Dedicated Credits Received : Local NCS", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Dedicated Credits Received : Remote NCB", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Dedicated Credits Received : Remote NCS", + "EventCode": "0x16", + "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Shared Credits Received : All", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Shared Credits Received : Local NCB", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Shared Credits Received : Local NCS", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Shared Credits Received : Remote NCB", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Shared Credits Received : Remote NCS", + "EventCode": "0x15", + "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Shared Credits Returned : Agent0", + "EventCode": "0x18", + "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Shared Credits Returned : Agent1", + "EventCode": "0x18", + "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote P2P Shared Credits Returned : Agent2", + "EventCode": "0x18", + "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent0", + "EventCode": "0x45", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent1", + "EventCode": "0x45", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent2", + "EventCode": "0x45", + "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD", + "EventCode": "0xac", + "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AD", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK", + "EventCode": "0xac", + "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AK", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL", + "EventCode": "0xac", + "EventName": "UNC_M2P_RING_BOUNCES_HORZ.BL", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV", + "EventCode": "0xac", + "EventName": "UNC_M2P_RING_BOUNCES_HORZ.IV", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : AD", + "EventCode": "0xaa", + "EventName": "UNC_M2P_RING_BOUNCES_VERT.AD", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core", + "EventCode": "0xaa", + "EventName": "UNC_M2P_RING_BOUNCES_VERT.AK", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring.", + "EventCode": "0xaa", + "EventName": "UNC_M2P_RING_BOUNCES_VERT.AKC", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core", + "EventCode": "0xaa", + "EventName": "UNC_M2P_RING_BOUNCES_VERT.BL", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.", + "EventCode": "0xaa", + "EventName": "UNC_M2P_RING_BOUNCES_VERT.IV", + "PerPkg": "1", + "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : AD", + "EventCode": "0xad", + "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : AK", + "EventCode": "0xad", + "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1", + "EventCode": "0xad", + "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK_AG1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : BL", + "EventCode": "0xad", + "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Horizontal Ring : IV", + "EventCode": "0xad", + "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : AD", + "EventCode": "0xab", + "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AD", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core", + "EventCode": "0xab", + "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AK", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring", + "EventCode": "0xab", + "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AKC", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core", + "EventCode": "0xab", + "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.BL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.", + "EventCode": "0xab", + "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.IV", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Source Throttle", + "EventCode": "0xae", + "EventName": "UNC_M2P_RING_SRC_THRTL", + "PerPkg": "1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.ALL", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "EventCode": "0x10", + "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.ALL", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Ingress (from CMS) Queue Inserts", + "EventCode": "0x11", + "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS", + "PerPkg": "1", + "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - All", + "EventCode": "0xe5", + "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Credited", + "EventCode": "0xe5", + "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", + "EventCode": "0xe5", + "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - All", + "EventCode": "0xe5", + "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Credited", + "EventCode": "0xe5", + "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", + "EventCode": "0xe5", + "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - All", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - Credited", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AK", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - All", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - Credited", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Bypass : IV", + "EventCode": "0xe2", + "EventName": "UNC_M2P_RxR_BYPASS.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - All", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Credited", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : AK", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - All", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Credited", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : IFV - Credited", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.IFV", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation : IV", + "EventCode": "0xe3", + "EventName": "UNC_M2P_RxR_CRD_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Injection Starvation", + "EventCode": "0xe4", + "EventName": "UNC_M2P_RxR_CRD_STARVED_1", + "PerPkg": "1", + "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - All", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - Credited", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AK", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - All", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - Credited", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Allocations : IV", + "EventCode": "0xe1", + "EventName": "UNC_M2P_RxR_INSERTS.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - All", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AK", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.AK", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - All", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Transgress Ingress Occupancy : IV", + "EventCode": "0xe0", + "EventName": "UNC_M2P_RxR_OCCUPANCY.IV", + "PerPkg": "1", + "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0", + "EventCode": "0xd0", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1", + "EventCode": "0xd0", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2", + "EventCode": "0xd0", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3", + "EventCode": "0xd0", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4", + "EventCode": "0xd0", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5", + "EventCode": "0xd0", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6", + "EventCode": "0xd0", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7", + "EventCode": "0xd0", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0", + "EventCode": "0xd2", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1", + "EventCode": "0xd2", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2", + "EventCode": "0xd2", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3", + "EventCode": "0xd2", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4", + "EventCode": "0xd2", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5", + "EventCode": "0xd2", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6", + "EventCode": "0xd2", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7", + "EventCode": "0xd2", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0", + "EventCode": "0xd4", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1", + "EventCode": "0xd4", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2", + "EventCode": "0xd4", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3", + "EventCode": "0xd4", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4", + "EventCode": "0xd4", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5", + "EventCode": "0xd4", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6", + "EventCode": "0xd4", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7", + "EventCode": "0xd4", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0", + "EventCode": "0xd6", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1", + "EventCode": "0xd6", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2", + "EventCode": "0xd6", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3", + "EventCode": "0xd6", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4", + "EventCode": "0xd6", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5", + "EventCode": "0xd6", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6", + "EventCode": "0xd6", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7", + "EventCode": "0xd6", + "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10", + "EventCode": "0xd1", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8", + "EventCode": "0xd1", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9", + "EventCode": "0xd1", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10", + "EventCode": "0xd3", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8", + "EventCode": "0xd3", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9", + "EventCode": "0xd3", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10", + "EventCode": "0xd5", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8", + "EventCode": "0xd5", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9", + "EventCode": "0xd5", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10", + "EventCode": "0xd7", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8", + "EventCode": "0xd7", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9", + "EventCode": "0xd7", + "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "PerPkg": "1", + "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ", + "EventCode": "0x2d", + "EventName": "UNC_M2P_TxC_CREDITS.PRQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Full", + "EventCode": "0x25", + "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "EventCode": "0x23", + "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress", + "EventCode": "0x24", + "EventName": "UNC_M2P_TxC_INSERTS.AD_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress", + "EventCode": "0x24", + "EventName": "UNC_M2P_TxC_INSERTS.AD_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress", + "EventCode": "0x24", + "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress", + "EventCode": "0x24", + "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress", + "EventCode": "0x24", + "EventName": "UNC_M2P_TxC_INSERTS.BL_0", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Egress (to CMS) Ingress", + "EventCode": "0x24", + "EventName": "UNC_M2P_TxC_INSERTS.BL_1", + "PerPkg": "1", + "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - All", + "EventCode": "0xa6", + "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", + "EventCode": "0xa6", + "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", + "EventCode": "0xa6", + "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - All", + "EventCode": "0xa6", + "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", + "EventCode": "0xa6", + "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", + "EventCode": "0xa6", + "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - All", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AK", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - All", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Bypass Used : IV", + "EventCode": "0xa7", + "EventName": "UNC_M2P_TxR_HORZ_BYPASS.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AK", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV", + "EventCode": "0xa2", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.IV", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AK", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_ALL", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_CRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV", + "EventCode": "0xa3", + "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.IV", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AK", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Inserts : IV", + "EventCode": "0xa1", + "EventName": "UNC_M2P_TxR_HORZ_INSERTS.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AK", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress NACKs : IV", + "EventCode": "0xa4", + "EventName": "UNC_M2P_TxR_HORZ_NACK.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x11", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AK", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", + "UMask": "0x44", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_CRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Occupancy : IV", + "EventCode": "0xa0", + "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All", + "EventCode": "0xa5", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited", + "EventCode": "0xa5", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK", + "EventCode": "0xa5", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.AK", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited", + "EventCode": "0xa5", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.AKC_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x80", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All", + "EventCode": "0xa5", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_ALL", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited", + "EventCode": "0xa5", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_UNCRD", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV", + "EventCode": "0xa5", + "EventName": "UNC_M2P_TxR_HORZ_STARVED.IV", + "PerPkg": "1", + "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "EventCode": "0x9c", + "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "EventCode": "0x9c", + "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "EventCode": "0x9c", + "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "EventCode": "0x9c", + "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "EventCode": "0x9d", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "EventCode": "0x9d", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", + "EventCode": "0x9d", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", + "EventCode": "0x9d", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "EventCode": "0x9d", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "EventCode": "0x9d", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", + "EventCode": "0x9d", + "EventName": "UNC_M2P_TxR_VERT_BYPASS.IV_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", + "EventCode": "0x9e", + "EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", + "EventCode": "0x9e", + "EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1", + "EventCode": "0x94", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1", + "EventCode": "0x94", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1", + "EventCode": "0x94", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0", + "EventCode": "0x94", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0", + "EventCode": "0x95", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1", + "EventCode": "0x95", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1", + "EventCode": "0x96", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1", + "EventCode": "0x96", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1", + "EventCode": "0x96", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0", + "EventCode": "0x96", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0", + "EventCode": "0x97", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1", + "EventCode": "0x97", + "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", + "EventCode": "0x92", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", + "EventCode": "0x92", + "EventName": "UNC_M2P_TxR_VERT_INSERTS0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", + "EventCode": "0x93", + "EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", + "EventCode": "0x93", + "EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", + "EventCode": "0x98", + "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", + "EventCode": "0x98", + "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : IV", + "EventCode": "0x98", + "EventName": "UNC_M2P_TxR_VERT_NACK0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", + "EventCode": "0x99", + "EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", + "EventCode": "0x99", + "EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", + "EventCode": "0x90", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", + "EventCode": "0x90", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", + "EventCode": "0x91", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", + "EventCode": "0x91", + "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0", + "EventCode": "0x9a", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1", + "EventCode": "0x9a", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x10", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0", + "EventCode": "0x9a", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1", + "EventCode": "0x9a", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x20", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0", + "EventCode": "0x9a", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1", + "EventCode": "0x9a", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x40", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : IV", + "EventCode": "0x9a", + "EventName": "UNC_M2P_TxR_VERT_STARVED0.IV_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", + "EventCode": "0x9b", + "EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG0", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1", + "EventCode": "0x9b", + "EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG1", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", + "EventCode": "0x9b", + "EventName": "UNC_M2P_TxR_VERT_STARVED1.TGC", + "PerPkg": "1", + "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Down and Even", + "EventCode": "0xb0", + "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Down and Odd", + "EventCode": "0xb0", + "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Up and Even", + "EventCode": "0xb0", + "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AD Ring In Use : Up and Odd", + "EventCode": "0xb0", + "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Down and Even", + "EventCode": "0xb4", + "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", + "EventCode": "0xb4", + "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Up and Even", + "EventCode": "0xb4", + "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", + "EventCode": "0xb4", + "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Down and Even", + "EventCode": "0xb1", + "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Down and Odd", + "EventCode": "0xb1", + "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Up and Even", + "EventCode": "0xb1", + "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical AK Ring In Use : Up and Odd", + "EventCode": "0xb1", + "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Down and Even", + "EventCode": "0xb2", + "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Down and Odd", + "EventCode": "0xb2", + "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Up and Even", + "EventCode": "0xb2", + "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical BL Ring in Use : Up and Odd", + "EventCode": "0xb2", + "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical IV Ring in Use : Down", + "EventCode": "0xb3", + "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.DN", + "PerPkg": "1", + "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical IV Ring in Use : Up", + "EventCode": "0xb3", + "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.UP", + "PerPkg": "1", + "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Down and Even", + "EventCode": "0xb5", + "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x4", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", + "EventCode": "0xb5", + "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x8", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Up and Even", + "EventCode": "0xb5", + "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_EVEN", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x1", + "Unit": "M2PCIe" + }, + { + "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", + "EventCode": "0xb5", + "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_ODD", + "PerPkg": "1", + "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", + "UMask": "0x2", + "Unit": "M2PCIe" + } +] diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json deleted file mode 100644 index 8bd041bc0c57..000000000000 --- a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-other.json +++ /dev/null @@ -1,22056 +0,0 @@ -[ - { - "BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.ia_miss", - "EventCode": "0x35", - "EventName": "LLC_MISSES.MMIO_READ", - "Filter": "config1=0x40040e33", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts.ia_miss", - "EventCode": "0x35", - "EventName": "LLC_MISSES.MMIO_WRITE", - "Filter": "config1=0x40041e33", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0", - "EventCode": "0x83", - "EventName": "LLC_MISSES.PCIE_READ", - "FCMask": "0x07", - "Filter": "ch_mask=0x1f", - "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "MetricName": "LLC_MISSES.PCIE_READ", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "ScaleUnit": "4Bytes", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth writing at IIO. Derived from unc_iio_data_req_of_cpu.mem_write.part0", - "EventCode": "0x83", - "EventName": "LLC_MISSES.PCIE_WRITE", - "FCMask": "0x07", - "Filter": "ch_mask=0x1f", - "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "MetricName": "LLC_MISSES.PCIE_WRITE", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "ScaleUnit": "4Bytes", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.ia_miss", - "EventCode": "0x35", - "EventName": "LLC_MISSES.UNCACHEABLE", - "Filter": "config1=0x40e33", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "Streaming stores (full cache line). Derived from unc_cha_tor_inserts.ia_miss", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.STREAMING_FULL", - "Filter": "config1=0x41833", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "ScaleUnit": "64Bytes", - "UMask": "0xc001fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "Streaming stores (partial cache line). Derived from unc_cha_tor_inserts.ia_miss", - "EventCode": "0x35", - "EventName": "LLC_REFERENCES.STREAMING_PARTIAL", - "Filter": "config1=0x41a33", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "ScaleUnit": "64Bytes", - "UMask": "0xc001fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7", - "EventCode": "0x80", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10", - "EventCode": "0x81", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8", - "EventCode": "0x81", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9", - "EventCode": "0x81", - "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7", - "EventCode": "0x82", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10", - "EventCode": "0x83", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8", - "EventCode": "0x83", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9", - "EventCode": "0x83", - "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7", - "EventCode": "0x88", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10", - "EventCode": "0x89", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8", - "EventCode": "0x89", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9", - "EventCode": "0x89", - "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7", - "EventCode": "0x8A", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10", - "EventCode": "0x8B", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8", - "EventCode": "0x8B", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9", - "EventCode": "0x8B", - "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7", - "EventCode": "0x84", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10", - "EventCode": "0x85", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8", - "EventCode": "0x85", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9", - "EventCode": "0x85", - "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7", - "EventCode": "0x86", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10", - "EventCode": "0x87", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8", - "EventCode": "0x87", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9", - "EventCode": "0x87", - "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", - "EventCode": "0x8C", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10", - "EventCode": "0x8D", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8", - "EventCode": "0x8D", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9", - "EventCode": "0x8D", - "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7", - "EventCode": "0x8E", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10", - "EventCode": "0x8F", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8", - "EventCode": "0x8F", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9", - "EventCode": "0x8F", - "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken", - "EventCode": "0x57", - "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", - "PerPkg": "1", - "PublicDescription": "CHA to iMC Bypass : Intermediate bypass Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the intermediate bypass.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA to iMC Bypass : Not Taken", - "EventCode": "0x57", - "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", - "PerPkg": "1", - "PublicDescription": "CHA to iMC Bypass : Not Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that could not take the bypass, and issues a read to memory. Note that transactions that did not take the bypass but did not issue read to memory will not be counted.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA to iMC Bypass : Taken", - "EventCode": "0x57", - "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN", - "PerPkg": "1", - "PublicDescription": "CHA to iMC Bypass : Taken : Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filtered by when the bypass was taken and when it was not. : Filter for transactions that succeeded in taking the full bypass.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Uncore cache clock ticks", - "EventName": "UNC_CHA_CLOCKTICKS", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Clockticks", - "EventCode": "0xc0", - "EventName": "UNC_CHA_CMS_CLOCKTICKS", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE", - "PerPkg": "1", - "PublicDescription": "Core Cross Snoops Issued : Any Cycle with Multiple Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0xf2", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued : Any Single Snoop", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.ANY_ONE", - "PerPkg": "1", - "PublicDescription": "Core Cross Snoops Issued : Any Single Snoop : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0xf1", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued : Multiple Core Requests", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE", - "PerPkg": "1", - "PublicDescription": "Core Cross Snoops Issued : Multiple Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x42", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued : Single Core Requests", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.CORE_ONE", - "PerPkg": "1", - "PublicDescription": "Core Cross Snoops Issued : Single Core Requests : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x41", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued : Multiple Eviction", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE", - "PerPkg": "1", - "PublicDescription": "Core Cross Snoops Issued : Multiple Eviction : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x82", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued : Single Eviction", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE", - "PerPkg": "1", - "PublicDescription": "Core Cross Snoops Issued : Single Eviction : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x81", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued : Multiple External Snoops", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE", - "PerPkg": "1", - "PublicDescription": "Core Cross Snoops Issued : Multiple External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x22", - "Unit": "CHA" - }, - { - "BriefDescription": "Core Cross Snoops Issued : Single External Snoops", - "EventCode": "0x33", - "EventName": "UNC_CHA_CORE_SNP.EXT_ONE", - "PerPkg": "1", - "PublicDescription": "Core Cross Snoops Issued : Single External Snoops : Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s).", - "UMask": "0x21", - "Unit": "CHA" - }, - { - "BriefDescription": "Counter 0 Occupancy", - "EventCode": "0x1F", - "EventName": "UNC_CHA_COUNTER0_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Counter 0 Occupancy : Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.", - "Unit": "CHA" - }, - { - "BriefDescription": "Direct GO", - "EventCode": "0x6E", - "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Direct GO", - "EventCode": "0x6E", - "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Direct GO", - "EventCode": "0x6E", - "EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Direct GO", - "EventCode": "0x6D", - "EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Direct GO", - "EventCode": "0x6D", - "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Direct GO", - "EventCode": "0x6D", - "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Direct GO", - "EventCode": "0x6D", - "EventName": "UNC_CHA_DIRECT_GO_OPC.GO", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Direct GO", - "EventCode": "0x6D", - "EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Direct GO", - "EventCode": "0x6D", - "EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Direct GO", - "EventCode": "0x6D", - "EventName": "UNC_CHA_DIRECT_GO_OPC.NOP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Direct GO", - "EventCode": "0x6D", - "EventName": "UNC_CHA_DIRECT_GO_OPC.PULL", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Distress signal asserted : DPT Local", - "EventCode": "0xAF", - "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_LOCAL", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Distress signal asserted : DPT Remote", - "EventCode": "0xAF", - "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_NONLOCAL", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Distress signal asserted : DPT Stalled - IV", - "EventCode": "0xAF", - "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_IV", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit", - "EventCode": "0xAF", - "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_NOCRD", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Distress signal asserted : Horizontal", - "EventCode": "0xAF", - "EventName": "UNC_CHA_DISTRESS_ASSERTED.HORZ", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Distress signal asserted : Vertical", - "EventCode": "0xAF", - "EventName": "UNC_CHA_DISTRESS_ASSERTED.VERT", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements : Down", - "EventCode": "0xBA", - "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", - "PerPkg": "1", - "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements : Up", - "EventCode": "0xBA", - "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", - "PerPkg": "1", - "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Left and Even", - "EventCode": "0xB6", - "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", - "EventCode": "0xB6", - "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Right and Even", - "EventCode": "0xB6", - "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", - "EventCode": "0xB6", - "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Even", - "EventCode": "0xBB", - "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", - "EventCode": "0xBB", - "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Even", - "EventCode": "0xBB", - "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", - "EventCode": "0xBB", - "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Even", - "EventCode": "0xB7", - "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", - "EventCode": "0xB7", - "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Even", - "EventCode": "0xB7", - "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", - "EventCode": "0xB7", - "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Left and Even", - "EventCode": "0xB8", - "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", - "EventCode": "0xB8", - "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Right and Even", - "EventCode": "0xB8", - "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", - "EventCode": "0xB8", - "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal IV Ring in Use : Left", - "EventCode": "0xB9", - "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", - "PerPkg": "1", - "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Horizontal IV Ring in Use : Right", - "EventCode": "0xB9", - "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", - "PerPkg": "1", - "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Normal priority reads issued to the memory controller from the CHA", - "EventCode": "0x59", - "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", - "PerPkg": "1", - "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "HA to iMC Reads Issued : ISOCH", - "EventCode": "0x59", - "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY", - "PerPkg": "1", - "PublicDescription": "HA to iMC Reads Issued : ISOCH : Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", - "PerPkg": "1", - "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to any of the memory controller channels.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", - "PerPkg": "1", - "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH Full Line : Counts the total number of full line writes issued from the HA into the memory controller.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", - "PerPkg": "1", - "PublicDescription": "CHA to iMC Full Line Writes Issued : Partial Non-ISOCH : Counts the total number of full line writes issued from the HA into the memory controller.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial", - "EventCode": "0x5B", - "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", - "PerPkg": "1", - "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH Partial : Counts the total number of full line writes issued from the HA into the memory controller.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache and Snoop Filter Lookups; Any Request", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.ALL", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ.", - "UMask": "0x1fffff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : All Request Filter", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.ANY_F", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : All Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local or remote transaction to the LLC, including prefetch.", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.CODE_READ", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.CODE", - "PerPkg": "1", - "UMask": "0x1bd0ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Code Reads", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Code Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x1bd0ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : CRd Request Filter", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : CRd Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Local or remote CRd transactions to the LLC. This includes CRd prefetch.", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Code Read Misses", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_MISS", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Code Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x1bd001", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Local request Filter", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Local request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Any local transaction to the LLC, including prefetches from the Core", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD", - "PerPkg": "1", - "UMask": "0x1bc1ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", - "PerPkg": "1", - "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions", - "UMask": "0x1bc1ff", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL", - "PerPkg": "1", - "UMask": "0x1fc1ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Data Read Request Filter", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Data Read Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Read transactions.", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Data Read Misses", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Data Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x1bc101", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.DMND_READ_LOCAL", - "PerPkg": "1", - "UMask": "0x841ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : E State", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.E", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Exclusive State", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : F State", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.F", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : F State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Forward State", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Flush or Invalidate Requests", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Flush : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing.", - "UMask": "0x1a44ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Flush or Invalidate Filter", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Flush or Invalidate Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : I State", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.I", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : I State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Miss", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Transactions homed locally Filter", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Transactions homed locally Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Transaction whose address resides in the local MC.", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : M State", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.M", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : M State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Modified State", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : All Misses", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : All Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x1fe001", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Write Request Filter", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Write Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Writeback transactions to the LLC This includes all write transactions -- both Cacheable and UC.", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Reads", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Reads : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x1bd9ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_LOC_HOM", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Locally Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x9d9ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_REM_HOM", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Locally Requested Reads that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x11d9ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Read Misses", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x1bd901", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Locally HOMed Read Misses", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_LOC_HOM", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Locally HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0xbd901", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Remotely HOMed Read Misses", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_REM_HOM", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Remotely HOMed Read Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x13d901", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ_OR_SNOOP_REMOTE_MISS_REM_HOM", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Remotely requested Read or Snoop Misses that are Remotely HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x161901", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ_REMOTE_LOC_HOM", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Remotely Requested Reads that are Locally HOMed : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0xa19ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Reads that Hit the Snoop Filter", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.READ_SF_HIT", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Reads that Hit the Snoop Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x1bd90e", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : RFO Requests", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.RFO", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : RFO Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.", - "UMask": "0x1bc8ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : RFO Request Filter", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.RFO_F", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : RFO Request Filter : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Local or remote RFO transactions to the LLC. This includes RFO prefetch.", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : RFO Misses", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.RFO_MISS", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : RFO Misses : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing.", - "UMask": "0x1bc801", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_LLC_LOOKUP.RFO_LOCAL", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.RFO_PREF_LOCAL", - "PerPkg": "1", - "UMask": "0x888ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : S State", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.S", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : Hit Shared State", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : SnoopFilter - E State", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.SF_E", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : SnoopFilter - E State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit Exclusive State", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : SnoopFilter - H State", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.SF_H", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : SnoopFilter - H State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit HitMe State", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : SnoopFilter - S State", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.SF_S", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : SnoopFilter - S State : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS select a state or states (in the umask field) to match. Otherwise, the event will count nothing. : SF Hit Shared State", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cache Lookups : Filters Requests for those that write info into the cache", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER", - "PerPkg": "1", - "PublicDescription": "Cache Lookups : Write Requests : Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. : Writeback transactions from L2 to the LLC This includes all write transactions -- both Cacheable and UC.", - "UMask": "0x1a42ff", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated.", - "Deprecated": "1", - "EventCode": "0x34", - "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL", - "PerPkg": "1", - "UMask": "0x842ff", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized : All Lines Victimized", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.ALL", - "PerPkg": "1", - "PublicDescription": "Lines Victimized : All Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0xf", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized : Lines in E state", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE", - "PerPkg": "1", - "PublicDescription": "Lines Victimized : Lines in E state : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized : Local - All Lines", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", - "PerPkg": "1", - "PublicDescription": "Lines Victimized : Local - All Lines : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x200f", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized : Local - Lines in E State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", - "PerPkg": "1", - "PublicDescription": "Lines Victimized : Local - Lines in E State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x2002", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized : Local - Lines in M State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", - "PerPkg": "1", - "PublicDescription": "Lines Victimized : Local - Lines in M State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x2001", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized : Local Only", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY", - "PerPkg": "1", - "PublicDescription": "Lines Victimized : Local Only : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized : Local - Lines in S State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", - "PerPkg": "1", - "PublicDescription": "Lines Victimized : Local - Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x2004", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized : Lines in M state", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE", - "PerPkg": "1", - "PublicDescription": "Lines Victimized : Lines in M state : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Lines Victimized : Lines in S State", - "EventCode": "0x37", - "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE", - "PerPkg": "1", - "PublicDescription": "Lines Victimized : Lines in S State : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cbo Misc : CV0 Prefetch Miss", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.CV0_PREF_MISS", - "PerPkg": "1", - "PublicDescription": "Cbo Misc : CV0 Prefetch Miss : Miscellaneous events in the Cbo.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Cbo Misc : CV0 Prefetch Victim", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.CV0_PREF_VIC", - "PerPkg": "1", - "PublicDescription": "Cbo Misc : CV0 Prefetch Victim : Miscellaneous events in the Cbo.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Number of times that an RFO hit in S state.", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.RFO_HIT_S", - "PerPkg": "1", - "PublicDescription": "Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cbo Misc : Silent Snoop Eviction", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE", - "PerPkg": "1", - "PublicDescription": "Cbo Misc : Silent Snoop Eviction : Miscellaneous events in the Cbo. : Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cbo Misc : Write Combining Aliasing", - "EventCode": "0x39", - "EventName": "UNC_CHA_MISC.WC_ALIASING", - "PerPkg": "1", - "PublicDescription": "Cbo Misc : Write Combining Aliasing : Miscellaneous events in the Cbo. : Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0", - "EventCode": "0xE6", - "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1", - "EventCode": "0xE6", - "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.ADEGRCREDIT", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.AKEGRCREDIT", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.ALLRSFWAYS_RES", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.BLEGRCREDIT", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.FSF_VICP", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLOWSNP", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLWAYRSV", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_PAMATCH", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_WAYMATCH", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.HACREDIT", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.IDX_INPIPE", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.IPQ_SETMATCH_VICP", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.IRQ_SETMATCH_VICP", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.ISMQ_SETMATCH_VICP", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.IVEGRCREDIT", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.LLC_WAYS_RES", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.NOTALLOWSNOOP", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.ONE_FSF_VIC", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.ONE_RSP_CON", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.PTL_INPIPE", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.RMW_SETMATCH", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.RRQ_SETMATCH_VICP", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.SETMATCHENTRYWSCT", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.SF_WAYS_RES", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.TOPA_MATCH", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.TORID_MATCH_GO_P", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_REQ", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_RSP", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCB", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCS", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_RSP", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_WB", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.WAY_MATCH", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC0", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC0 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 0 only.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC1", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC1 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 1 only.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC10", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC10", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC10 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 10 only.", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC11", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC11", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC11 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 11 only.", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC12", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC12", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC12 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 12 only.", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC13", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC13", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC13 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 13 only.", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC2", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC2 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 2 only.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC3", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC3 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 3 only.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC4", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC4 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 4 only.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC5", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC5 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 5 only.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC6", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC6", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC6 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 6 only.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC7", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC7", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC7 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 7 only.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC8", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC8", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC8 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 8 only.", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC9", - "EventCode": "0x58", - "EventName": "UNC_CHA_READ_NO_CREDITS.MC9", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC9 : Counts the number of times when there are no credits available for sending reads from the CHA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue. : Filter for memory controller 9 only.", - "Unit": "CHA" - }, - { - "BriefDescription": "Local INVITOE requests (exclusive ownership of a cache line without receiving data) that miss the SF/LLC and remote INVITOE requests sent to the CHA's home agent", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.INVITOE", - "PerPkg": "1", - "PublicDescription": "Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA.", - "UMask": "0x30", - "Unit": "CHA" - }, - { - "BriefDescription": "Local read requests that miss the SF/LLC and remote read requests sent to the CHA's home agent", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.READS", - "PerPkg": "1", - "PublicDescription": "Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) .", - "UMask": "0x3", - "Unit": "CHA" - }, - { - "BriefDescription": "Local write requests that miss the SF/LLC and remote write requests sent to the CHA's home agent", - "EventCode": "0x50", - "EventName": "UNC_CHA_REQUESTS.WRITES", - "PerPkg": "1", - "PublicDescription": "Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc.", - "UMask": "0xc", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD", - "EventCode": "0xAC", - "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK", - "EventCode": "0xAC", - "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL", - "EventCode": "0xAC", - "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV", - "EventCode": "0xAC", - "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : AD", - "EventCode": "0xAA", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core", - "EventCode": "0xAA", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.", - "EventCode": "0xAA", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.AKC", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core", - "EventCode": "0xAA", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.", - "EventCode": "0xAA", - "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : AD", - "EventCode": "0xAD", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : AK", - "EventCode": "0xAD", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1", - "EventCode": "0xAD", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : BL", - "EventCode": "0xAD", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : IV", - "EventCode": "0xAD", - "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : AD", - "EventCode": "0xAB", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core", - "EventCode": "0xAB", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring", - "EventCode": "0xAB", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AKC", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core", - "EventCode": "0xAB", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.", - "EventCode": "0xAB", - "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Source Throttle", - "EventCode": "0xae", - "EventName": "UNC_CHA_RING_SRC_THRTL", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations : IRQ", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.IRQ", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Allocations : IRQ : Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Allocations : IRQ Rejected : Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations : PRQ", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.PRQ", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Allocations : PRQ", - "EventCode": "0x13", - "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Counts number of allocations per cycle into the specified Ingress queue.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request", - "EventCode": "0x18", - "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0", - "PerPkg": "1", - "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the IRQ0 Reject counter was true", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC or SF Way : Way conflict with another request that caused the reject", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LLC Victim", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Request Queue Rejects; PhyAddr Match", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Victim", - "EventCode": "0x19", - "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "ISMQ Rejects - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request", - "EventCode": "0x24", - "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "ISMQ Retries - Set 0 : AD REQ on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a request", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "ISMQ Retries - Set 0 : AD RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No AD VN0 credit for generating a response", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "ISMQ Retries - Set 0 : Non UPI AK Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject AK ring message", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "ISMQ Retries - Set 0 : BL NCB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCB", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "ISMQ Retries - Set 0 : BL NCS on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for NCS", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "ISMQ Retries - Set 0 : BL RSP on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a response", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "ISMQ Retries - Set 0 : BL WB on VN0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : No BL VN0 credit for generating a writeback", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request", - "EventCode": "0x2C", - "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "ISMQ Retries - Set 0 : Non UPI IV Request : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Can't inject IV ring message", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects - Set 1 : ANY0", - "EventCode": "0x25", - "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0", - "PerPkg": "1", - "PublicDescription": "ISMQ Rejects - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Rejects - Set 1 : HA", - "EventCode": "0x25", - "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA", - "PerPkg": "1", - "PublicDescription": "ISMQ Rejects - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries - Set 1 : ANY0", - "EventCode": "0x2D", - "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0", - "PerPkg": "1", - "PublicDescription": "ISMQ Retries - Set 1 : ANY0 : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. : Any condition listed in the ISMQ0 Reject counter was true", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "ISMQ Retries - Set 1 : HA", - "EventCode": "0x2D", - "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA", - "PerPkg": "1", - "PublicDescription": "ISMQ Retries - Set 1 : HA : Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Ingress (from CMS) Occupancy : IRQ", - "EventCode": "0x11", - "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Occupancy : IRQ : Counts number of entries in the specified Ingress queue in each cycle.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 0 : AD REQ on VN0", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 0 : AD REQ on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a request", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 0 : AD RSP on VN0", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 0 : AD RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No AD VN0 credit for generating a response", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 0 : Non UPI AK Request", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 0 : Non UPI AK Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject AK ring message", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 0 : BL NCB on VN0", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 0 : BL NCB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCB", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 0 : BL NCS on VN0", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 0 : BL NCS on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for NCS", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 0 : BL RSP on VN0", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 0 : BL RSP on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a response", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 0 : BL WB on VN0", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 0 : BL WB on VN0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : No BL VN0 credit for generating a writeback", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 0 : Non UPI IV Request", - "EventCode": "0x2E", - "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 0 : Non UPI IV Request : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Can't inject IV ring message", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 1 : Allow Snoop", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 1 : Allow Snoop : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 1 : ANY0", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 1 : ANY0 : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Any condition listed in the Other0 Reject counter was true", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 1 : HA", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 1 : HA : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 1 : LLC OR SF Way", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 1 : LLC OR SF Way : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Way conflict with another request that caused the reject", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 1 : LLC Victim", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 1 : LLC Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 1 : PhyAddr Match", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 1 : PhyAddr Match : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Address match with an outstanding request that was rejected.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 1 : SF Victim", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 1 : SF Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject) : Requests did not generate Snoop filter victim", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Other Retries - Set 1 : Victim", - "EventCode": "0x2F", - "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM", - "PerPkg": "1", - "PublicDescription": "Other Retries - Set 1 : Victim : Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD REQ on VN0 : No AD VN0 credit for generating a request", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD RSP on VN0 : No AD VN0 credit for generating a response", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI AK Request : Can't inject AK ring message", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCB on VN0 : No BL VN0 credit for NCB", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL NCS on VN0 : No BL VN0 credit for NCS", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL RSP on VN0 : No BL VN0 credit for generating a response", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL WB on VN0 : No BL VN0 credit for generating a writeback", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request", - "EventCode": "0x20", - "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : Non UPI IV Request : Can't inject IV ring message", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Allow Snoop", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0", - "PerPkg": "1", - "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : ANY0 : Any condition listed in the PRQ0 Reject counter was true", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", - "PerPkg": "1", - "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC OR SF Way : Way conflict with another request that caused the reject", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LLC Victim", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", - "PerPkg": "1", - "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : PhyAddr Match : Address match with an outstanding request that was rejected.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", - "PerPkg": "1", - "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF Victim : Requests did not generate Snoop filter victim", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Victim", - "EventCode": "0x21", - "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 0 : AD REQ on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a request", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 0 : AD RSP on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No AD VN0 credit for generating a response", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Request", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 0 : Non UPI AK Request : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject AK ring message", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 0 : BL NCB on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCB", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 0 : BL NCS on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for NCS", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 0 : BL RSP on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a response", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 0 : BL WB on VN0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : No BL VN0 credit for generating a writeback", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Request", - "EventCode": "0x2A", - "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 0 : Non UPI IV Request : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Can't inject IV ring message", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 1 : Allow Snoop : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 1 : ANY0", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 1 : ANY0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Any condition listed in the WBQ0 Reject counter was true", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 1 : HA", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 1 : HA : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 1 : LLC OR SF Way : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Way conflict with another request that caused the reject", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 1 : LLC Victim", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 1 : LLC Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 1 : PhyAddr Match : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Address match with an outstanding request that was rejected.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 1 : SF Victim", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 1 : SF Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Requests did not generate Snoop filter victim", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Request Queue Retries - Set 1 : Victim", - "EventCode": "0x2B", - "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", - "PerPkg": "1", - "PublicDescription": "Request Queue Retries - Set 1 : Victim : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - All", - "EventCode": "0xE5", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Credited", - "EventCode": "0xE5", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", - "EventCode": "0xE5", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - All", - "EventCode": "0xE5", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Credited", - "EventCode": "0xE5", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", - "EventCode": "0xE5", - "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AD - All", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AD - Credited", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AK", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass : BL - All", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass : BL - Credited", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Bypass : IV", - "EventCode": "0xE2", - "EventName": "UNC_CHA_RxR_BYPASS.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - All", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Credited", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : AK", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - All", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Credited", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : IFV - Credited", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation : IV", - "EventCode": "0xE3", - "EventName": "UNC_CHA_RxR_CRD_STARVED.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Injection Starvation", - "EventCode": "0xe4", - "EventName": "UNC_CHA_RxR_CRD_STARVED_1", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AD - All", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AD - Credited", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AK", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations : BL - All", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations : BL - Credited", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Allocations : IV", - "EventCode": "0xE1", - "EventName": "UNC_CHA_RxR_INSERTS.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AD - All", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AK", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : BL - All", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : IV", - "EventCode": "0xE0", - "EventName": "UNC_CHA_RxR_OCCUPANCY.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop filter capacity evictions for E-state entries.", - "EventCode": "0x3D", - "EventName": "UNC_CHA_SF_EVICTION.E_STATE", - "PerPkg": "1", - "PublicDescription": "Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop filter capacity evictions for M-state entries.", - "EventCode": "0x3D", - "EventName": "UNC_CHA_SF_EVICTION.M_STATE", - "PerPkg": "1", - "PublicDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop filter capacity evictions for S-state entries.", - "EventCode": "0x3D", - "EventName": "UNC_CHA_SF_EVICTION.S_STATE", - "PerPkg": "1", - "PublicDescription": "Counts snoop filter capacity evictions for entries tracking shared lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent : All", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.ALL", - "PerPkg": "1", - "PublicDescription": "Snoops Sent : All : Counts the number of snoops issued by the HA.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent : Broadcast snoops for Local Requests", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL", - "PerPkg": "1", - "PublicDescription": "Snoops Sent : Broadcast snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast snoops issued by the HA responding to local requests", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent : Directed snoops for Local Requests", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", - "PerPkg": "1", - "PublicDescription": "Snoops Sent : Directed snoops for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of directed snoops issued by the HA responding to local requests", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoops Sent : Snoops sent for Local Requests", - "EventCode": "0x51", - "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL", - "PerPkg": "1", - "PublicDescription": "Snoops Sent : Snoops sent for Local Requests : Counts the number of snoops issued by the HA. : Counts the number of broadcast or directed snoops issued by the HA responding to local requests", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local : RspCnflct", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", - "PerPkg": "1", - "PublicDescription": "Snoop Responses Received Local : RspCnflct : Number of snoop responses received for a Local request : Filters for snoops responses of RspConflict to local CA requests. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local : RspFwd", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", - "PerPkg": "1", - "PublicDescription": "Snoop Responses Received Local : RspFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspFwd to local CA requests. This snoop response is only possible for RdCur when a snoop HITM/E in a remote caching agent and it directly forwards data to a requestor without changing the requestor's cache line state.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB", - "PerPkg": "1", - "PublicDescription": "Snoop Responses Received Local : Rsp*FWD*WB : Number of snoop responses received for a Local request : Filters for a snoop response of Rsp*Fwd*WB to local CA requests. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local : RspI", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI", - "PerPkg": "1", - "PublicDescription": "Snoop Responses Received Local : RspI : Number of snoop responses received for a Local request : Filters for snoops responses of RspI to local CA requests. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data).", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local : RspIFwd", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", - "PerPkg": "1", - "PublicDescription": "Snoop Responses Received Local : RspIFwd : Number of snoop responses received for a Local request : Filters for snoop responses of RspIFwd to local CA requests. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local : RspS", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS", - "PerPkg": "1", - "PublicDescription": "Snoop Responses Received Local : RspS : Number of snoop responses received for a Local request : Filters for snoop responses of RspS to local CA requests. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local : RspSFwd", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", - "PerPkg": "1", - "PublicDescription": "Snoop Responses Received Local : RspSFwd : Number of snoop responses received for a Local request : Filters for a snoop response of RspSFwd to local CA requests. This is returned when a remote caching agent forwards data but holds on to its currently copy. This is common for data and code reads that hit in a remote socket in E or F state.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Snoop Responses Received Local : Rsp*WB", - "EventCode": "0x5D", - "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB", - "PerPkg": "1", - "PublicDescription": "Snoop Responses Received Local : Rsp*WB : Number of snoop responses received for a Local request : Filters for a snoop response of RspIWB or RspSWB to local CA requests. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Misc Snoop Responses Received : MtoI RspIDataM", - "EventCode": "0x6B", - "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM", - "EventCode": "0x6B", - "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit LLC", - "EventCode": "0x6B", - "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Misc Snoop Responses Received : Pull Data Partial - Hit SF", - "EventCode": "0x6B", - "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit LLC", - "EventCode": "0x6B", - "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hit SF", - "EventCode": "0x6B", - "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7", - "EventCode": "0xD0", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7", - "EventCode": "0xD2", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7", - "EventCode": "0xD4", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7", - "EventCode": "0xD6", - "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10", - "EventCode": "0xD1", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8", - "EventCode": "0xD1", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9", - "EventCode": "0xD1", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10", - "EventCode": "0xD3", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8", - "EventCode": "0xD3", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9", - "EventCode": "0xD3", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10", - "EventCode": "0xD5", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8", - "EventCode": "0xD5", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9", - "EventCode": "0xD5", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10", - "EventCode": "0xD7", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8", - "EventCode": "0xD7", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9", - "EventCode": "0xD7", - "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.ALL", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001ffff", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DDR4 Access", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.DDR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DDR4 Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_CHA_TOR_INSERTS.DDR", - "Deprecated": "1", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.DDR4", - "PerPkg": "1", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : SF/LLC Evictions", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.EVICT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : SF/LLC Evictions : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Just Hits", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.HIT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Just Hits : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All requests from iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : CLFlushes issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8c7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CLFlushOpts issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : CLFlushOpts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8d7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CRDs issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : CRDs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc80fff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; CRd Pref from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter", - "UMask": "0xc88fff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc837ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc827ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8a7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc80ffd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc88ffd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to page walks that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc837fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc827fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8a7fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc807fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc887fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc80ffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc88ffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores due to a page walk that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc837fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc827fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8a7fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; WCiLF misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", - "UMask": "0xc867fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; WCiL misses from local IA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", - "UMask": "0xc86ffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc807fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc887fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc877de01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86ffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc867fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc87fde01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFOs issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFOs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc807ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc887ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. Non Modified Write Backs", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE", - "PerPkg": "1", - "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc3fff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WBEFtoIs issued by an IA Core. Non Modified Write Backs", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI", - "PerPkg": "1", - "PublicDescription": "WbEFtoIs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc37ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WBMtoEs issued by an IA Core. Non Modified Write Backs", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE", - "PerPkg": "1", - "PublicDescription": "WbMtoEs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc2fff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. Modified Write Backs", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI", - "PerPkg": "1", - "PublicDescription": "WbMtoIs issued by iA Cores . (Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc27ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WBStoIs issued by an IA Core. Non Modified Write Backs", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI", - "PerPkg": "1", - "PublicDescription": "WbStoIs issued by iA Cores . (Non Modified Write Backs) :Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc67ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86fff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc867ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All requests from IO Devices", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : CLFlushes issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8c3ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All requests from IO Devices that hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc43fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcd43fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8f3fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc803fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc43ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcd43ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All requests from IO Devices that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc43fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcd43fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8f3fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc803fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8f3ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : RFOs issued by IO Devices", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc803ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : WbMtoIs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc23ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : IRQ - iA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : IRQ - iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From an iA Core", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : IRQ - Non iA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : IRQ - Non iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Just ISOC", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.ISOC", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Just ISOC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Just Local Targets", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Just Local Targets : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All from Local iA and IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All from Local iA and IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests", - "UMask": "0xc000ff05", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All from Local iA", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All from Local iA : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores", - "UMask": "0xc000ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : All from Local IO", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : All from Local IO : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic", - "UMask": "0xc000ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Match the Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Just Misses", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.MISS", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Just Misses : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : MMCFG Access", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.MMCFG", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : MMCFG Access : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Just NearMem", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.NEARMEM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Just NearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Just NonCoherent", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.NONCOH", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Just NonCoherent : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Just NotNearMem", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Just NotNearMem : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : Match the PreMorphed Opcode in b[29:19] of the extended umask field : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : PRQ - IOSF", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : PRQ - IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From a PCIe Device", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts : PRQ - Non IOSF", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts : PRQ - Non IOSF : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DDR4 Access", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DDR4 Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : SF/LLC Evictions", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : SF/LLC Evictions : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Just Hits", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Just Hits : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All requests from iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8c7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CLFlushOpts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8d7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CRDs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc80fff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; CRd Pref from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter", - "UMask": "0xc88fff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc837ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc827ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8a7ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc80ffd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc88ffd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc837fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc827fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8a7fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc807fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc887fd01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc80ffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc88ffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores due to a page walk that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc837fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc827fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8a7fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", - "UMask": "0xc867fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy; WCiL misses from local IA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy; Data read from local IA that misses in the snoop filter", - "UMask": "0xc86ffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc807fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc887fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc877de01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86ffe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc867fe01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that Missed LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc87fde01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc807ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc887ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc27ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc86fff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc867ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All requests from IO Devices", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Devices", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8c3ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc43fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcd43fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8f3fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc803fd04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc43ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcd43ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc001fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc43fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcd43fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8f3fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc803fe04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc8f3ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xc803ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0xcc23ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : IRQ - iA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : IRQ - iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From an iA Core", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : IRQ - Non iA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : IRQ - Non iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Just ISOC", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Just ISOC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Just Local Targets", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Just Local Targets : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All from Local iA and IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All from Local iA and IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests", - "UMask": "0xc000ff05", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All from Local iA", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All from Local iA : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally initiated requests from iA Cores", - "UMask": "0xc000ff01", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : All from Local IO", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : All from Local IO : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : All locally generated IO traffic", - "UMask": "0xc000ff04", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Match the Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Just Misses", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Just Misses : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : MMCFG Access", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : MMCFG Access : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Just NearMem", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Just NearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Just NonCoherent", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Just NonCoherent : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Just NotNearMem", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Just NotNearMem : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : Match the PreMorphed Opcode in b[29:19] of the extended umask field : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : PRQ - IOSF", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : PRQ - IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. : From a PCIe Device", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Occupancy : PRQ - Non IOSF", - "EventCode": "0x36", - "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF", - "PerPkg": "1", - "PublicDescription": "TOR Occupancy : PRQ - Non IOSF : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : AD - All", - "EventCode": "0xA6", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", - "EventCode": "0xA6", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", - "EventCode": "0xA6", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : BL - All", - "EventCode": "0xA6", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", - "EventCode": "0xA6", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", - "EventCode": "0xA6", - "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AD - All", - "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", - "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", - "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AK", - "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited", - "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : BL - All", - "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", - "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", - "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : IV", - "EventCode": "0xA7", - "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All", - "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited", - "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited", - "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK", - "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited", - "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All", - "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited", - "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited", - "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV", - "EventCode": "0xA2", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All", - "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited", - "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited", - "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK", - "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited", - "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All", - "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited", - "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited", - "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV", - "EventCode": "0xA3", - "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", - "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited", - "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited", - "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AK", - "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited", - "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", - "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited", - "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited", - "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : IV", - "EventCode": "0xA1", - "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", - "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", - "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited", - "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AK", - "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited", - "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", - "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", - "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited", - "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : IV", - "EventCode": "0xA4", - "EventName": "UNC_CHA_TxR_HORZ_NACK.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", - "EventCode": "0xA0", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited", - "EventCode": "0xA0", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited", - "EventCode": "0xA0", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AK", - "EventCode": "0xA0", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited", - "EventCode": "0xA0", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", - "EventCode": "0xA0", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited", - "EventCode": "0xA0", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited", - "EventCode": "0xA0", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : IV", - "EventCode": "0xA0", - "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All", - "EventCode": "0xA5", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited", - "EventCode": "0xA5", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK", - "EventCode": "0xA5", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited", - "EventCode": "0xA5", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All", - "EventCode": "0xA5", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited", - "EventCode": "0xA5", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV", - "EventCode": "0xA5", - "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", - "EventCode": "0x9D", - "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", - "EventCode": "0x9E", - "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0", - "EventCode": "0x95", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1", - "EventCode": "0x95", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0", - "EventCode": "0x97", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1", - "EventCode": "0x97", - "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_CHA_TxR_VERT_INSERTS0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : IV", - "EventCode": "0x98", - "EventName": "UNC_CHA_TxR_VERT_NACK0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", - "EventCode": "0x99", - "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", - "EventCode": "0x99", - "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : IV", - "EventCode": "0x9A", - "EventName": "UNC_CHA_TxR_VERT_STARVED0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", - "EventCode": "0x9B", - "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1", - "EventCode": "0x9B", - "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", - "EventCode": "0x9B", - "EventName": "UNC_CHA_TxR_VERT_STARVED1.TGC", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Down and Even", - "EventCode": "0xB0", - "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Down and Odd", - "EventCode": "0xB0", - "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Up and Even", - "EventCode": "0xB0", - "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Up and Odd", - "EventCode": "0xB0", - "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Down and Even", - "EventCode": "0xB4", - "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", - "EventCode": "0xB4", - "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Up and Even", - "EventCode": "0xB4", - "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", - "EventCode": "0xB4", - "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Down and Even", - "EventCode": "0xB1", - "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Down and Odd", - "EventCode": "0xB1", - "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Up and Even", - "EventCode": "0xB1", - "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Up and Odd", - "EventCode": "0xB1", - "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Down and Even", - "EventCode": "0xB2", - "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Down and Odd", - "EventCode": "0xB2", - "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Up and Even", - "EventCode": "0xB2", - "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Up and Odd", - "EventCode": "0xB2", - "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical IV Ring in Use : Down", - "EventCode": "0xB3", - "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN", - "PerPkg": "1", - "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical IV Ring in Use : Up", - "EventCode": "0xB3", - "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP", - "PerPkg": "1", - "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Down and Even", - "EventCode": "0xB5", - "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", - "EventCode": "0xB5", - "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Up and Even", - "EventCode": "0xB5", - "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", - "EventCode": "0xB5", - "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "WbPushMtoI : Pushed to LLC", - "EventCode": "0x56", - "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC", - "PerPkg": "1", - "PublicDescription": "WbPushMtoI : Pushed to LLC : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was able to push WbPushMToI to LLC", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "WbPushMtoI : Pushed to Memory", - "EventCode": "0x56", - "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM", - "PerPkg": "1", - "PublicDescription": "WbPushMtoI : Pushed to Memory : Counts the number of times when the CHA was received WbPushMtoI : Counts the number of times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to MEM)", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC0 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 0 only.", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC1 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 1 only.", - "UMask": "0x2", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC10", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC10", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC10 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 10 only.", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC11", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC11", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC11 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 11 only.", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC12", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC12", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC12 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 12 only.", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC13", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC13", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC13 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 13 only.", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC2 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 2 only.", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC3 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 3 only.", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC4 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 4 only.", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC5 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 5 only.", - "UMask": "0x20", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC6", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC6", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC6 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 6 only.", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC7", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC7", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC7 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 7 only.", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC8", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC8", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC8 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 8 only.", - "Unit": "CHA" - }, - { - "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC9", - "EventCode": "0x5A", - "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC9", - "PerPkg": "1", - "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC9 : Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC. In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue. : Filter for memory controller 9 only.", - "Unit": "CHA" - }, - { - "BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict", - "EventCode": "0x6f", - "EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT", - "PerPkg": "1", - "PublicDescription": "XPT Prefetches : Dropped (on 0?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention", - "UMask": "0x8", - "Unit": "CHA" - }, - { - "BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits", - "EventCode": "0x6f", - "EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD", - "PerPkg": "1", - "PublicDescription": "XPT Prefetches : Dropped (on 0?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits", - "UMask": "0x4", - "Unit": "CHA" - }, - { - "BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict", - "EventCode": "0x6f", - "EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT", - "PerPkg": "1", - "PublicDescription": "XPT Prefetches : Dropped (on 1?) - Conflict : Number of XPT prefetches dropped due to AD CMS write port contention", - "UMask": "0x80", - "Unit": "CHA" - }, - { - "BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits", - "EventCode": "0x6f", - "EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD", - "PerPkg": "1", - "PublicDescription": "XPT Prefetches : Dropped (on 1?) - No Credits : Number of XPT prefetches dropped due to lack of XPT AD egress credits", - "UMask": "0x40", - "Unit": "CHA" - }, - { - "BriefDescription": "XPT Prefetches : Sent (on 0?)", - "EventCode": "0x6f", - "EventName": "UNC_CHA_XPT_PREF.SENT0", - "PerPkg": "1", - "PublicDescription": "XPT Prefetches : Sent (on 0?) : Number of XPT prefetches sent", - "UMask": "0x1", - "Unit": "CHA" - }, - { - "BriefDescription": "XPT Prefetches : Sent (on 1?)", - "EventCode": "0x6f", - "EventName": "UNC_CHA_XPT_PREF.SENT1", - "PerPkg": "1", - "PublicDescription": "XPT Prefetches : Sent (on 1?) : Number of XPT prefetches sent", - "UMask": "0x10", - "Unit": "CHA" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventCode": "0xff", - "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN", - "PerPkg": "1", - "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN", - "UMask": "0x20", - "Unit": "iio_free_running" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventCode": "0xff", - "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN", - "PerPkg": "1", - "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN", - "UMask": "0x21", - "Unit": "iio_free_running" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventCode": "0xff", - "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN", - "PerPkg": "1", - "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN", - "UMask": "0x22", - "Unit": "iio_free_running" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventCode": "0xff", - "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN", - "PerPkg": "1", - "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN", - "UMask": "0x23", - "Unit": "iio_free_running" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventCode": "0xff", - "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN", - "PerPkg": "1", - "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN", - "UMask": "0x24", - "Unit": "iio_free_running" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventCode": "0xff", - "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN", - "PerPkg": "1", - "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN", - "UMask": "0x25", - "Unit": "iio_free_running" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventCode": "0xff", - "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN", - "PerPkg": "1", - "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN", - "UMask": "0x26", - "Unit": "iio_free_running" - }, - { - "BriefDescription": "Free running counter that increments for every 32 bytes of data sent from the IO agent to the SOC", - "EventCode": "0xff", - "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN", - "PerPkg": "1", - "PublicDescription": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN", - "UMask": "0x27", - "Unit": "iio_free_running" - }, - { - "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller", - "EventCode": "0x01", - "EventName": "UNC_IIO_CLOCKTICKS", - "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "Free running counter that increments for IIO clocktick", - "EventCode": "0xff", - "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", - "PerPkg": "1", - "PublicDescription": "Free running counter that increments for integrated IO (IIO) traffic controller clockticks", - "UMask": "0x10", - "Unit": "iio_free_running" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts : All Ports", - "EventCode": "0xC2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL", - "FCMask": "0x04", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", - "FCMask": "0x04", - "PerPkg": "1", - "PortMask": "0xff", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", - "FCMask": "0x04", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", - "FCMask": "0x04", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", - "FCMask": "0x04", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", - "FCMask": "0x04", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4", - "FCMask": "0x04", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5", - "FCMask": "0x04", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6", - "FCMask": "0x04", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7", - "EventCode": "0xc2", - "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7", - "FCMask": "0x04", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7", - "UMask": "0x3", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7", - "EventCode": "0xD5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL", - "FCMask": "0x04", - "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7", - "UMask": "0xff", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", - "FCMask": "0x04", - "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7", - "UMask": "0xff", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", - "FCMask": "0x04", - "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 1", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", - "FCMask": "0x04", - "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer Occupancy : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 2", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", - "FCMask": "0x04", - "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer Occupancy : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 3", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", - "FCMask": "0x04", - "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer Occupancy : Part 3 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 4", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", - "FCMask": "0x04", - "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer Occupancy : Part 4 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 5", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", - "FCMask": "0x04", - "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer Occupancy : Part 5 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 6", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", - "FCMask": "0x04", - "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer Occupancy : Part 6 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 7", - "EventCode": "0xd5", - "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", - "FCMask": "0x04", - "PerPkg": "1", - "PublicDescription": "PCIe Completion Buffer Occupancy : Part 7 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested by the CPU : Core reading from Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested by the CPU : Core writing to Card's PCICFG space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested by the CPU : Core reading from Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested by the CPU : Core writing to Card's IO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", - "EventCode": "0xc0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) reading from this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC0", - "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested by the CPU : Another card (different IIO stack) writing to this card. : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested of the CPU : Atomic requests targeting DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 0", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 2", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth reading at IIO, part 3", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 0", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 1", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 2", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "PCI Express bandwidth writing at IIO, part 3", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Messages", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested of the CPU : Messages : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested of the CPU : Card reading from another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Data requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x83", - "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Incoming arbitration requests : Passing data to be written", - "EventCode": "0x86", - "EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Incoming arbitration requests : Passing data to be written : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Incoming arbitration requests : Issuing final read or write of line", - "EventCode": "0x86", - "EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Incoming arbitration requests : Issuing final read or write of line : How often different queues (e.g. channel / fc) ask to send request into pipeline", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Incoming arbitration requests : Processing response from IOMMU", - "EventCode": "0x86", - "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Incoming arbitration requests : Processing response from IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Incoming arbitration requests : Issuing to IOMMU", - "EventCode": "0x86", - "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Incoming arbitration requests : Issuing to IOMMU : How often different queues (e.g. channel / fc) ask to send request into pipeline", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Incoming arbitration requests : Request Ownership", - "EventCode": "0x86", - "EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Incoming arbitration requests : Request Ownership : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Incoming arbitration requests : Writing line", - "EventCode": "0x86", - "EventName": "UNC_IIO_INBOUND_ARB_REQ.WR", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Incoming arbitration requests : Writing line : How often different queues (e.g. channel / fc) ask to send request into pipeline : Only for posted requests", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Incoming arbitration requests granted : Passing data to be written", - "EventCode": "0x87", - "EventName": "UNC_IIO_INBOUND_ARB_WON.DATA", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Incoming arbitration requests granted : Passing data to be written : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Incoming arbitration requests granted : Issuing final read or write of line", - "EventCode": "0x87", - "EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Incoming arbitration requests granted : Issuing final read or write of line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Incoming arbitration requests granted : Processing response from IOMMU", - "EventCode": "0x87", - "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Incoming arbitration requests granted : Processing response from IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Incoming arbitration requests granted : Issuing to IOMMU", - "EventCode": "0x87", - "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Incoming arbitration requests granted : Issuing to IOMMU : How often different queues (e.g. channel / fc) are allowed to send request into pipeline", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Incoming arbitration requests granted : Request Ownership", - "EventCode": "0x87", - "EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Incoming arbitration requests granted : Request Ownership : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Incoming arbitration requests granted : Writing line", - "EventCode": "0x87", - "EventName": "UNC_IIO_INBOUND_ARB_WON.WR", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Incoming arbitration requests granted : Writing line : How often different queues (e.g. channel / fc) are allowed to send request into pipeline : Only for posted requests", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": ": IOTLB Hits to a 1G Page", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.1G_HITS", - "PerPkg": "1", - "PublicDescription": ": IOTLB Hits to a 1G Page : Counts if a transaction to a 1G page, on its first lookup, hits the IOTLB.", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": ": IOTLB Hits to a 2M Page", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.2M_HITS", - "PerPkg": "1", - "PublicDescription": ": IOTLB Hits to a 2M Page : Counts if a transaction to a 2M page, on its first lookup, hits the IOTLB.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": ": IOTLB Hits to a 4K Page", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.4K_HITS", - "PerPkg": "1", - "PublicDescription": ": IOTLB Hits to a 4K Page : Counts if a transaction to a 4K page, on its first lookup, hits the IOTLB.", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": ": IOTLB lookups all", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS", - "PerPkg": "1", - "PublicDescription": ": IOTLB lookups all : Some transactions have to look up IOTLB multiple times. Counts every time a request looks up IOTLB.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": ": Context cache hits", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS", - "PerPkg": "1", - "PublicDescription": ": Context cache hits : Counts each time a first look up of the transaction hits the RCC.", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": ": Context cache lookups", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS", - "PerPkg": "1", - "PublicDescription": ": Context cache lookups : Counts each time a transaction looks up root context cache.", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": ": IOTLB lookups first", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS", - "PerPkg": "1", - "PublicDescription": ": IOTLB lookups first : Some transactions have to look up IOTLB multiple times. Counts the first time a request looks up IOTLB.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": ": IOTLB Fills (same as IOTLB miss)", - "EventCode": "0x40", - "EventName": "UNC_IIO_IOMMU0.MISSES", - "PerPkg": "1", - "PublicDescription": ": IOTLB Fills (same as IOTLB miss) : When a transaction misses IOTLB, it does a page walk to look up memory and bring in the relevant page translation. Counts when this page translation is written to IOTLB.", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": ": Cycles PWT full", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.CYC_PWT_FULL", - "PerPkg": "1", - "PublicDescription": ": Cycles PWT full : Counts cycles the IOMMU has reached its maximum limit for outstanding page walks.", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": ": IOMMU memory access", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES", - "PerPkg": "1", - "PublicDescription": ": IOMMU memory access : IOMMU sends out memory fetches when it misses the cache look up which is indicated by this signal. M2IOSF only uses low priority channel", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": ": PWC Hit to a 1G page", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS", - "PerPkg": "1", - "PublicDescription": ": PWC Hit to a 1G page : Counts each time a transaction's first look up hits the SLPWC at the 1G level", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": ": PWC Hit to a 2M page", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS", - "PerPkg": "1", - "PublicDescription": ": PWC Hit to a 2M page : Counts each time a transaction's first look up hits the SLPWC at the 2M level", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": ": PWC Hit to a 4K page", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.PWC_4K_HITS", - "PerPkg": "1", - "PublicDescription": ": PWC Hit to a 4K page : Counts each time a transaction's first look up hits the SLPWC at the 4K level", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": ": PWT Hit to a 256T page", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS", - "PerPkg": "1", - "PublicDescription": ": PWT Hit to a 256T page : Counts each time a transaction's first look up hits the SLPWC at the 512G level", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": ": PageWalk cache fill", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS", - "PerPkg": "1", - "PublicDescription": ": PageWalk cache fill : When a transaction misses SLPWC, it does a page walk to look up memory and bring in the relevant page translation. When this page translation is written to SLPWC, ObsPwcFillValid_nnnH is asserted.", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": ": PageWalk cache lookup", - "EventCode": "0x41", - "EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS", - "PerPkg": "1", - "PublicDescription": ": PageWalk cache lookup : Counts each time a transaction looks up second level page walk cache.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": ": Interrupt Entry cache hit", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS", - "PerPkg": "1", - "PublicDescription": ": Interrupt Entry cache hit : Counts each time a transaction's first look up hits the IEC.", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": ": Interrupt Entry cache lookup", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS", - "PerPkg": "1", - "PublicDescription": ": Interrupt Entry cache lookup : Counts the number of transaction looks up that interrupt remapping cache.", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": ": Device-selective Context cache invalidation cycles", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DEVICE", - "PerPkg": "1", - "PublicDescription": ": Device-selective Context cache invalidation cycles : Counts number of Device selective context cache invalidation events", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": ": Domain-selective Context cache invalidation cycles", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DOMAIN", - "PerPkg": "1", - "PublicDescription": ": Domain-selective Context cache invalidation cycles : Counts number of Domain selective context cache invalidation events", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": ": Context cache global invalidation cycles", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_GBL", - "PerPkg": "1", - "PublicDescription": ": Context cache global invalidation cycles : Counts number of Context Cache global invalidation events", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": ": Domain-selective IOTLB invalidation cycles", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_DOMAIN", - "PerPkg": "1", - "PublicDescription": ": Domain-selective IOTLB invalidation cycles : Counts number of Domain selective invalidation events", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": ": Global IOTLB invalidation cycles", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_GBL", - "PerPkg": "1", - "PublicDescription": ": Global IOTLB invalidation cycles : Indicates that IOMMU is doing global invalidation.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": ": Page-selective IOTLB invalidation cycles", - "EventCode": "0x43", - "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PAGE", - "PerPkg": "1", - "PublicDescription": ": Page-selective IOTLB invalidation cycles : Counts number of Page-selective within Domain Invalidation events", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus", - "EventCode": "0x02", - "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0", - "PerPkg": "1", - "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus : Asserted if all bits specified by mask match", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus", - "EventCode": "0x02", - "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1", - "PerPkg": "1", - "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if all bits specified by mask match", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)", - "EventCode": "0x02", - "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1", - "PerPkg": "1", - "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if all bits specified by mask match", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "AND Mask/match for debug bus : PCIE bus", - "EventCode": "0x02", - "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1", - "PerPkg": "1", - "PublicDescription": "AND Mask/match for debug bus : PCIE bus : Asserted if all bits specified by mask match", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus", - "EventCode": "0x02", - "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1", - "PerPkg": "1", - "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if all bits specified by mask match", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)", - "EventCode": "0x02", - "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1", - "PerPkg": "1", - "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if all bits specified by mask match", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus", - "EventCode": "0x03", - "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0", - "PerPkg": "1", - "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus : Asserted if any bits specified by mask match", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus", - "EventCode": "0x03", - "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1", - "PerPkg": "1", - "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and PCIE bus : Asserted if any bits specified by mask match", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus)", - "EventCode": "0x03", - "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1", - "PerPkg": "1", - "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus and !(PCIE bus) : Asserted if any bits specified by mask match", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "OR Mask/match for debug bus : PCIE bus", - "EventCode": "0x03", - "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1", - "PerPkg": "1", - "PublicDescription": "OR Mask/match for debug bus : PCIE bus : Asserted if any bits specified by mask match", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus", - "EventCode": "0x03", - "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1", - "PerPkg": "1", - "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and PCIE bus : Asserted if any bits specified by mask match", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus)", - "EventCode": "0x03", - "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1", - "PerPkg": "1", - "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus) and !(PCIE bus) : Asserted if any bits specified by mask match", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Counting disabled", - "EventCode": "0x80", - "EventName": "UNC_IIO_NOTHING", - "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "Occupancy of outbound request queue : To device", - "EventCode": "0xC5", - "EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Occupancy of outbound request queue : To device : Counts number of outbound requests/completions IIO is currently processing", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": ": Passing data to be written", - "EventCode": "0x88", - "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": ": Passing data to be written : Only for posted requests", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": ": Issuing final read or write of line", - "EventCode": "0x88", - "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": ": Processing response from IOMMU", - "EventCode": "0x88", - "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": ": Issuing to IOMMU", - "EventCode": "0x88", - "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": ": Request Ownership", - "EventCode": "0x88", - "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": ": Request Ownership : Only for posted requests", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": ": Writing line", - "EventCode": "0x88", - "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": ": Writing line : Only for posted requests", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number requests sent to PCIe from main die : From IRP", - "EventCode": "0xC2", - "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.IRP", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Number requests sent to PCIe from main die : From IRP : Captures Posted/Non-posted allocations from IRP. i.e. either non-confined P2P traffic or from the CPU", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number requests sent to PCIe from main die : From ITC", - "EventCode": "0xC2", - "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.ITC", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Number requests sent to PCIe from main die : From ITC : Confined P2P", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number requests sent to PCIe from main die : Completion allocations", - "EventCode": "0xc2", - "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.PREALLOC", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number requests PCIe makes of the main die : Drop request", - "EventCode": "0x85", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU.ALL.DROP", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Number requests PCIe makes of the main die : Drop request : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU. : Packet error detected, must be dropped", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number requests PCIe makes of the main die : All", - "EventCode": "0x85", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Num requests sent by PCIe - by target : Abort", - "EventCode": "0x8E", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Num requests sent by PCIe - by target : Confined P2P", - "EventCode": "0x8E", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Num requests sent by PCIe - by target : Local P2P", - "EventCode": "0x8E", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Num requests sent by PCIe - by target : Multi-cast", - "EventCode": "0x8E", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Num requests sent by PCIe - by target : Memory", - "EventCode": "0x8E", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Num requests sent by PCIe - by target : MsgB", - "EventCode": "0x8E", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Num requests sent by PCIe - by target : Remote P2P", - "EventCode": "0x8E", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Num requests sent by PCIe - by target : Ubox", - "EventCode": "0x8E", - "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "ITC address map 1", - "EventCode": "0x8F", - "EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU", - "PerPkg": "1", - "Unit": "IIO" - }, - { - "BriefDescription": "Outbound cacheline requests issued : 64B requests issued to device", - "EventCode": "0xD0", - "EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Outbound cacheline requests issued : 64B requests issued to device : Each outbound cacheline granular request may need to make multiple passes through the pipeline. Each time a cacheline completes all its passes it advances line", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Outbound TLP (transaction layer packet) requests issued : To device", - "EventCode": "0xD1", - "EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "Outbound TLP (transaction layer packet) requests issued : To device : Each time an outbound completes all its passes it advances the pointer", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "PWT occupancy", - "EventCode": "0x42", - "EventName": "UNC_IIO_PWT_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "PWT occupancy : Indicates how many page walks are outstanding at any point in time.", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request - cacheline complete : Passing data to be written", - "EventCode": "0x91", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request - cacheline complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request - cacheline complete : Issuing final read or write of line", - "EventCode": "0x91", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request - cacheline complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request - cacheline complete : Request Ownership", - "EventCode": "0x91", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request - cacheline complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request - cacheline complete : Writing line", - "EventCode": "0x91", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request - cacheline complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes all its passes (e.g. finishes posting writes to all multi-cast targets) it advances line : Only for posted requests", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request complete : Passing data to be written", - "EventCode": "0x92", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.DATA", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request complete : Issuing final read or write of line", - "EventCode": "0x92", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request complete : Processing response from IOMMU", - "EventCode": "0x92", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request complete : Processing response from IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request complete : Issuing to IOMMU", - "EventCode": "0x92", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request complete : Issuing to IOMMU : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer.", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request complete : Request Ownership", - "EventCode": "0x92", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request complete : Writing line", - "EventCode": "0x92", - "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.WR", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a single PCIe request completes all its cacheline granular requests, it advances pointer. : Only for posted requests", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request - pass complete : Passing data to be written", - "EventCode": "0x90", - "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request - pass complete : Passing data to be written : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request - pass complete : Issuing final read or write of line", - "EventCode": "0x90", - "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request - pass complete : Issuing final read or write of line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request - pass complete : Request Ownership", - "EventCode": "0x90", - "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request - pass complete : Request Ownership : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "PCIe Request - pass complete : Writing line", - "EventCode": "0x90", - "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0xFF", - "PublicDescription": "PCIe Request - pass complete : Writing line : Each PCIe request is broken down into a series of cacheline granular requests and each cacheline size request may need to make multiple passes through the pipeline (e.g. for posted interrupts or multi-cast). Each time a cacheline completes a single pass (e.g. posts a write to single multi-cast target) it advances state : Only for posted requests", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Symbol Times on Link", - "EventCode": "0x82", - "EventName": "UNC_IIO_SYMBOL_TIMES", - "PerPkg": "1", - "PublicDescription": "Symbol Times on Link : Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's PCICFG space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's IO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x20", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", - "EventCode": "0xc1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 0", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) reading from this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : IOMMU - Type 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card.", - "EventCode": "0xC1", - "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested by the CPU : Another card (different IIO stack) writing to this card. : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested of the CPU : Atomic requests targeting DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x10", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x80", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x4", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x1", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Messages", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested of the CPU : Messages : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x40", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested of the CPU : Card reading from another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x8", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x100", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x200", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : IOMMU - Type 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x01", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x02", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x04", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x08", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x10", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x20", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x40", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack)", - "EventCode": "0x84", - "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7", - "FCMask": "0x07", - "PerPkg": "1", - "PortMask": "0x80", - "PublicDescription": "Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", - "UMask": "0x2", - "Unit": "IIO" - }, - { - "BriefDescription": "Total Write Cache Occupancy : Any Source", - "EventCode": "0x0F", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", - "PerPkg": "1", - "PublicDescription": "Total Write Cache Occupancy : Any Source : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events. : Tracks all requests from any source port.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Total Write Cache Occupancy : Snoops", - "EventCode": "0x0F", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q", - "PerPkg": "1", - "PublicDescription": "Total Write Cache Occupancy : Snoops : Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory.", - "EventCode": "0x0f", - "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", - "PerPkg": "1", - "PublicDescription": "Total IRP occupancy of inbound read and write requests to coherent memory. This is effectively the sum of read occupancy and write occupancy.", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Clockticks of the IO coherency tracker (IRP)", - "EventCode": "0x01", - "EventName": "UNC_I_CLOCKTICKS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops : CLFlush", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", - "PerPkg": "1", - "PublicDescription": "Coherent Ops : CLFlush : Counts the number of coherency related operations servied by the IRP", - "UMask": "0x80", - "Unit": "IRP" - }, - { - "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.PCITOM", - "PerPkg": "1", - "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline.", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.RFO", - "PerPkg": "1", - "PublicDescription": "RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache.", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Coherent Ops : WbMtoI", - "EventCode": "0x10", - "EventName": "UNC_I_COHERENT_OPS.WBMTOI", - "PerPkg": "1", - "PublicDescription": "Coherent Ops : WbMtoI : Counts the number of coherency related operations servied by the IRP", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "FAF RF full", - "EventCode": "0x17", - "EventName": "UNC_I_FAF_FULL", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.", - "EventCode": "0x18", - "EventName": "UNC_I_FAF_INSERTS", - "PerPkg": "1", - "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.", - "Unit": "IRP" - }, - { - "BriefDescription": "Occupancy of the IRP FAF queue.", - "EventCode": "0x19", - "EventName": "UNC_I_FAF_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.", - "Unit": "IRP" - }, - { - "BriefDescription": "FAF allocation -- sent to ADQ", - "EventCode": "0x16", - "EventName": "UNC_I_FAF_TRANSACTIONS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", - "EventCode": "0x20", - "EventName": "UNC_I_IRP_ALL.EVICTS", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)", - "EventCode": "0x20", - "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", - "EventCode": "0x20", - "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary", - "EventCode": "0x1E", - "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary", - "EventCode": "0x1e", - "EventName": "UNC_I_MISC0.2ND_RD_INSERT", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary", - "EventCode": "0x1e", - "EventName": "UNC_I_MISC0.2ND_WR_INSERT", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", - "EventCode": "0x1E", - "EventName": "UNC_I_MISC0.FAST_REJ", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests", - "EventCode": "0x1e", - "EventName": "UNC_I_MISC0.FAST_REQ", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers From Primary to Secondary", - "EventCode": "0x1E", - "EventName": "UNC_I_MISC0.FAST_XFER", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints From Primary to Secondary", - "EventCode": "0x1E", - "EventName": "UNC_I_MISC0.PF_ACK_HINT", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn't find prefetch", - "EventCode": "0x1E", - "EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1 : Lost Forward", - "EventCode": "0x1F", - "EventName": "UNC_I_MISC1.LOST_FWD", - "PerPkg": "1", - "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1 : Received Invalid", - "EventCode": "0x1F", - "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", - "PerPkg": "1", - "PublicDescription": "Misc Events - Set 1 : Received Invalid : Secondary received a transfer that did not have sufficient MESI state", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1 : Received Valid", - "EventCode": "0x1F", - "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", - "PerPkg": "1", - "PublicDescription": "Misc Events - Set 1 : Received Valid : Secondary received a transfer that did have sufficient MESI state", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line", - "EventCode": "0x1f", - "EventName": "UNC_I_MISC1.SLOW_E", - "PerPkg": "1", - "PublicDescription": "Misc Events - Set 1 : Slow Transfer of E Line : Secondary received a transfer that did have sufficient MESI state", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line", - "EventCode": "0x1f", - "EventName": "UNC_I_MISC1.SLOW_I", - "PerPkg": "1", - "PublicDescription": "Misc Events - Set 1 : Slow Transfer of I Line : Snoop took cacheline ownership before write from data was committed.", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line", - "EventCode": "0x1f", - "EventName": "UNC_I_MISC1.SLOW_M", - "PerPkg": "1", - "PublicDescription": "Misc Events - Set 1 : Slow Transfer of M Line : Snoop took cacheline ownership before write from data was committed.", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line", - "EventCode": "0x1f", - "EventName": "UNC_I_MISC1.SLOW_S", - "PerPkg": "1", - "PublicDescription": "Misc Events - Set 1 : Slow Transfer of S Line : Secondary received a transfer that did not have sufficient MESI state", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Requests", - "EventCode": "0x14", - "EventName": "UNC_I_P2P_INSERTS", - "PerPkg": "1", - "PublicDescription": "P2P Requests : P2P requests from the ITC", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Occupancy", - "EventCode": "0x15", - "EventName": "UNC_I_P2P_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "P2P Occupancy : P2P B & S Queue Occupancy", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions : P2P completions", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions : match if local only", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.LOC", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions : match if local and target matches", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions : P2P Message", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.MSG", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions : P2P reads", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.RD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions : Match if remote only", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.REM", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions : match if remote and target matches", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "P2P Transactions : P2P Writes", - "EventCode": "0x13", - "EventName": "UNC_I_P2P_TRANSACTIONS.WR", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Responses to snoops of any type that hit M, E, S or I line in the IIO", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT", - "PerPkg": "1", - "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M, E, S or I line in the IIO", - "UMask": "0x7e", - "Unit": "IRP" - }, - { - "BriefDescription": "Responses to snoops of any type that hit E or S line in the IIO cache", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES", - "PerPkg": "1", - "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit E or S line in the IIO cache", - "UMask": "0x74", - "Unit": "IRP" - }, - { - "BriefDescription": "Responses to snoops of any type that hit I line in the IIO cache", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I", - "PerPkg": "1", - "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit I line in the IIO cache", - "UMask": "0x72", - "Unit": "IRP" - }, - { - "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", - "PerPkg": "1", - "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache", - "UMask": "0x78", - "Unit": "IRP" - }, - { - "BriefDescription": "Responses to snoops of any type that miss the IIO cache", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.ALL_MISS", - "PerPkg": "1", - "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that miss the IIO cache", - "UMask": "0x71", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses : Hit E or S", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.HIT_ES", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses : Hit I", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.HIT_I", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses : Hit M", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.HIT_M", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses : Miss", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.MISS", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses : SnpCode", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.SNPCODE", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses : SnpData", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.SNPDATA", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Snoop Responses : SnpInv", - "EventCode": "0x12", - "EventName": "UNC_I_SNOOP_RESP.SNPINV", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count : Atomic", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.ATOMIC", - "PerPkg": "1", - "PublicDescription": "Inbound Transaction Count : Atomic : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of atomic transactions", - "UMask": "0x10", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count : Other", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.OTHER", - "PerPkg": "1", - "PublicDescription": "Inbound Transaction Count : Other : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Tracks the number of 'other' kinds of transactions.", - "UMask": "0x20", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound Transaction Count : Writes", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.WRITES", - "PerPkg": "1", - "PublicDescription": "Inbound Transaction Count : Writes : Counts the number of Inbound transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID. : Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry.", - "UMask": "0x2", - "Unit": "IRP" - }, - { - "BriefDescription": "Inbound write (fast path) requests received by the IRP.", - "EventCode": "0x11", - "EventName": "UNC_I_TRANSACTIONS.WR_PREF", - "PerPkg": "1", - "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", - "UMask": "0x8", - "Unit": "IRP" - }, - { - "BriefDescription": "AK Egress Allocations", - "EventCode": "0x0B", - "EventName": "UNC_I_TxC_AK_INSERTS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL DRS Egress Cycles Full", - "EventCode": "0x05", - "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL DRS Egress Inserts", - "EventCode": "0x02", - "EventName": "UNC_I_TxC_BL_DRS_INSERTS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL DRS Egress Occupancy", - "EventCode": "0x08", - "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL NCB Egress Cycles Full", - "EventCode": "0x06", - "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL NCB Egress Inserts", - "EventCode": "0x03", - "EventName": "UNC_I_TxC_BL_NCB_INSERTS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL NCB Egress Occupancy", - "EventCode": "0x09", - "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL NCS Egress Cycles Full", - "EventCode": "0x07", - "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL NCS Egress Inserts", - "EventCode": "0x04", - "EventName": "UNC_I_TxC_BL_NCS_INSERTS", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "BL NCS Egress Occupancy", - "EventCode": "0x0A", - "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY", - "PerPkg": "1", - "Unit": "IRP" - }, - { - "BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", - "EventCode": "0x1C", - "EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", - "PerPkg": "1", - "PublicDescription": ": Counts the number times when it is not possible to issue a request to the M2PCIe because there are no Egress Credits available on AD0, A1 or AD0&AD1 both. Stalls on both AD0 and AD1 will count as 2", - "Unit": "IRP" - }, - { - "BriefDescription": "No AD0 Egress Credits Stalls", - "EventCode": "0x1A", - "EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES", - "PerPkg": "1", - "PublicDescription": "No AD0 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD0 Egress Credits available.", - "Unit": "IRP" - }, - { - "BriefDescription": "No AD1 Egress Credits Stalls", - "EventCode": "0x1B", - "EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES", - "PerPkg": "1", - "PublicDescription": "No AD1 Egress Credits Stalls : Counts the number times when it is not possible to issue a request to the M2PCIe because there are no AD1 Egress Credits available.", - "Unit": "IRP" - }, - { - "BriefDescription": "No BL Egress Credit Stalls", - "EventCode": "0x1D", - "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", - "PerPkg": "1", - "PublicDescription": "No BL Egress Credit Stalls : Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Read Requests", - "EventCode": "0x0D", - "EventName": "UNC_I_TxS_DATA_INSERTS_NCB", - "PerPkg": "1", - "PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Read Requests", - "EventCode": "0x0E", - "EventName": "UNC_I_TxS_DATA_INSERTS_NCS", - "PerPkg": "1", - "PublicDescription": "Outbound Read Requests : Counts the number of requests issued to the switch (towards the devices).", - "Unit": "IRP" - }, - { - "BriefDescription": "Outbound Request Queue Occupancy", - "EventCode": "0x0C", - "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", - "PerPkg": "1", - "PublicDescription": "Outbound Request Queue Occupancy : Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.", - "Unit": "IRP" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7", - "EventCode": "0x80", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10", - "EventCode": "0x81", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8", - "EventCode": "0x81", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9", - "EventCode": "0x81", - "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7", - "EventCode": "0x82", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10", - "EventCode": "0x83", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8", - "EventCode": "0x83", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9", - "EventCode": "0x83", - "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7", - "EventCode": "0x88", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10", - "EventCode": "0x89", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8", - "EventCode": "0x89", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9", - "EventCode": "0x89", - "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7", - "EventCode": "0x8A", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10", - "EventCode": "0x8B", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8", - "EventCode": "0x8B", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9", - "EventCode": "0x8B", - "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7", - "EventCode": "0x84", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10", - "EventCode": "0x85", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8", - "EventCode": "0x85", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9", - "EventCode": "0x85", - "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7", - "EventCode": "0x86", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10", - "EventCode": "0x87", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8", - "EventCode": "0x87", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9", - "EventCode": "0x87", - "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", - "EventCode": "0x8C", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10", - "EventCode": "0x8D", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8", - "EventCode": "0x8D", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9", - "EventCode": "0x8D", - "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7", - "EventCode": "0x8E", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10", - "EventCode": "0x8F", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8", - "EventCode": "0x8F", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9", - "EventCode": "0x8F", - "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC Bypass : Not Taken", - "EventCode": "0x22", - "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.NOT_TAKEN", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC Bypass : Taken", - "EventCode": "0x22", - "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.TAKEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC Bypass : Not Taken", - "EventCode": "0x21", - "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC Bypass : Taken", - "EventCode": "0x21", - "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Clockticks of the mesh to memory (M2M)", - "EventName": "UNC_M2M_CLOCKTICKS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Clockticks", - "EventCode": "0xc0", - "EventName": "UNC_M2M_CMS_CLOCKTICKS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles when direct to core mode, which bypasses the CHA, was disabled", - "EventCode": "0x24", - "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", - "EventCode": "0x60", - "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Number of reads in which direct to core transaction was overridden", - "EventCode": "0x25", - "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Distress signal asserted : DPT Local", - "EventCode": "0xAF", - "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_LOCAL", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Distress signal asserted : DPT Remote", - "EventCode": "0xAF", - "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_NONLOCAL", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Distress signal asserted : DPT Stalled - IV", - "EventCode": "0xAF", - "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_IV", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit", - "EventCode": "0xAF", - "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_NOCRD", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Distress signal asserted : Horizontal", - "EventCode": "0xAF", - "EventName": "UNC_M2M_DISTRESS_ASSERTED.HORZ", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Distress signal asserted : Vertical", - "EventCode": "0xAF", - "EventName": "UNC_M2M_DISTRESS_ASSERTED.VERT", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements : Down", - "EventCode": "0xBA", - "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN", - "PerPkg": "1", - "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements : Up", - "EventCode": "0xBA", - "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP", - "PerPkg": "1", - "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Left and Even", - "EventCode": "0xB6", - "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", - "EventCode": "0xB6", - "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Right and Even", - "EventCode": "0xB6", - "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", - "EventCode": "0xB6", - "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Even", - "EventCode": "0xBB", - "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", - "EventCode": "0xBB", - "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Even", - "EventCode": "0xBB", - "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", - "EventCode": "0xBB", - "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Even", - "EventCode": "0xB7", - "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", - "EventCode": "0xB7", - "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Even", - "EventCode": "0xB7", - "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", - "EventCode": "0xB7", - "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Left and Even", - "EventCode": "0xB8", - "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", - "EventCode": "0xB8", - "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Right and Even", - "EventCode": "0xB8", - "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", - "EventCode": "0xB8", - "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal IV Ring in Use : Left", - "EventCode": "0xB9", - "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT", - "PerPkg": "1", - "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Horizontal IV Ring in Use : Right", - "EventCode": "0xB9", - "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT", - "PerPkg": "1", - "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - All Channels", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.ALL", - "PerPkg": "1", - "UMask": "0x704", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch0", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH0_ALL", - "PerPkg": "1", - "UMask": "0x104", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch0", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR", - "PerPkg": "1", - "UMask": "0x140", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch0", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH0_ISOCH", - "PerPkg": "1", - "UMask": "0x102", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch0", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH0_NORMAL", - "PerPkg": "1", - "UMask": "0x101", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : All, regardless of priority. - Ch1", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH1_ALL", - "PerPkg": "1", - "UMask": "0x204", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch1", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR", - "PerPkg": "1", - "UMask": "0x240", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - Ch1", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH1_ISOCH", - "PerPkg": "1", - "UMask": "0x202", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - Ch1", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.CH1_NORMAL", - "PerPkg": "1", - "UMask": "0x201", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : From TGR - All Channels", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.FROM_TGR", - "PerPkg": "1", - "UMask": "0x740", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : Critical Priority - All Channels", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.ISOCH", - "PerPkg": "1", - "UMask": "0x702", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - All Channels", - "EventCode": "0x37", - "EventName": "UNC_M2M_IMC_READS.NORMAL", - "PerPkg": "1", - "UMask": "0x701", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : All Writes - All Channels", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.ALL", - "PerPkg": "1", - "UMask": "0x1c10", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch0", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_ALL", - "PerPkg": "1", - "UMask": "0x410", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch0", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch0", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL", - "PerPkg": "1", - "UMask": "0x401", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch0", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH", - "PerPkg": "1", - "UMask": "0x404", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch0", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch0", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL", - "PerPkg": "1", - "UMask": "0x402", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch0", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH", - "PerPkg": "1", - "UMask": "0x408", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch1", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_ALL", - "PerPkg": "1", - "UMask": "0x810", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch1", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - Ch1", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL", - "PerPkg": "1", - "UMask": "0x801", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - Ch1", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH", - "PerPkg": "1", - "UMask": "0x804", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - Ch1", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - Ch1", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL", - "PerPkg": "1", - "UMask": "0x802", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch1", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH", - "PerPkg": "1", - "UMask": "0x808", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : From TGR - All Channels", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.FROM_TGR", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOCH - All Channels", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.FULL", - "PerPkg": "1", - "UMask": "0x1c01", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - All Channels", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH", - "PerPkg": "1", - "UMask": "0x1c04", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss - All Channels", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.NI_MISS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH - All Channels", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", - "PerPkg": "1", - "UMask": "0x1c02", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - All Channels", - "EventCode": "0x38", - "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH", - "PerPkg": "1", - "UMask": "0x1c08", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Inserts", - "EventCode": "0x64", - "EventName": "UNC_M2M_MIRR_WRQ_INSERTS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Occupancy", - "EventCode": "0x65", - "EventName": "UNC_M2M_MIRR_WRQ_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0", - "EventCode": "0xE6", - "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1", - "EventCode": "0xE6", - "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Number Packet Header Matches : MC Match", - "EventCode": "0x4C", - "EventName": "UNC_M2M_PKT_MATCH.MC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Number Packet Header Matches : Mesh Match", - "EventCode": "0x4C", - "EventName": "UNC_M2M_PKT_MATCH.MESH", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS", - "EventCode": "0x73", - "EventName": "UNC_M2M_PREFCAM_CIS_DROPS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Cycles Full : All Channels", - "EventCode": "0x6B", - "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.ALLCH", - "PerPkg": "1", - "UMask": "0x7", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Cycles Full : Channel 0", - "EventCode": "0x6B", - "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Cycles Full : Channel 1", - "EventCode": "0x6B", - "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Cycles Not Empty : All Channels", - "EventCode": "0x6C", - "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.ALLCH", - "PerPkg": "1", - "UMask": "0x7", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 0", - "EventCode": "0x6C", - "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 1", - "EventCode": "0x6C", - "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Deallocs", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA0_INVAL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Deallocs", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA1_INVAL", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Deallocs", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_MISS_INVAL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Deallocs", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_RSP_PDRESET", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Deallocs", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA0_INVAL", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Deallocs", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA1_INVAL", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Deallocs", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_MISS_INVAL", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Deallocs", - "EventCode": "0x6E", - "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_RSP_PDRESET", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped : XPT - Ch 0", - "EventCode": "0x6F", - "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped : XPT - Ch 1", - "EventCode": "0x6F", - "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped : XPT - All Channels", - "EventCode": "0x6f", - "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH", - "PerPkg": "1", - "UMask": "0x15", - "Unit": "M2M" - }, - { - "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - Ch 0", - "EventCode": "0x74", - "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPT", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 0", - "EventCode": "0x74", - "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPTUPI", - "PerPkg": "1", - "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 0", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - Ch 1", - "EventCode": "0x74", - "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPT", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 1", - "EventCode": "0x74", - "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPTUPI", - "PerPkg": "1", - "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- Ch 2", - "EventCode": "0x74", - "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH2_XPTUPI", - "PerPkg": "1", - "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - Ch 2", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & UPI- All Channels", - "EventCode": "0x74", - "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPTUPI_ALLCH", - "PerPkg": "1", - "PublicDescription": "Demands Merged with CAMed Prefetches : XPT & UPI - All Channels", - "UMask": "0x15", - "Unit": "M2M" - }, - { - "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - All Channels", - "EventCode": "0x74", - "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPT_ALLCH", - "PerPkg": "1", - "UMask": "0x15", - "Unit": "M2M" - }, - { - "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT - Ch 0", - "EventCode": "0x75", - "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPT", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 0", - "EventCode": "0x75", - "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPTUPI", - "PerPkg": "1", - "PublicDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 0", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT - Ch 1", - "EventCode": "0x75", - "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPT", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 1", - "EventCode": "0x75", - "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPTUPI", - "PerPkg": "1", - "PublicDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI- Ch 1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - Ch 2", - "EventCode": "0x75", - "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH2_XPTUPI", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT & UPI - All Channels", - "EventCode": "0x75", - "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPTUPI_ALLCH", - "PerPkg": "1", - "UMask": "0x15", - "Unit": "M2M" - }, - { - "BriefDescription": "Demands Not Merged with CAMed Prefetches : XPT - All Channels", - "EventCode": "0x75", - "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPT_ALLCH", - "PerPkg": "1", - "UMask": "0x15", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.ERRORBLK_RxC", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.NOT_PF_SAD_REGION", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_AD_CRD", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_FULL", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_HIT", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_SECURE_DROP", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.RPQ_PROXY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.STOP_B2B", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.WPQ_PROXY", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", - "EventCode": "0x70", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.XPT_THRESH", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.ERRORBLK_RxC", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.NOT_PF_SAD_REGION", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_AD_CRD", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_FULL", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_HIT", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_SECURE_DROP", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.RPQ_PROXY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.STOP_B2B", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.WPQ_PROXY", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", - "EventCode": "0x71", - "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.XPT_THRESH", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0", - "EventCode": "0x6D", - "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1", - "EventCode": "0x6D", - "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels", - "EventCode": "0x6D", - "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH", - "PerPkg": "1", - "UMask": "0x15", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Occupancy : All Channels", - "EventCode": "0x6A", - "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH", - "PerPkg": "1", - "UMask": "0x7", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Occupancy : Channel 0", - "EventCode": "0x6A", - "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Prefetch CAM Occupancy : Channel 1", - "EventCode": "0x6A", - "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": ": All Channels", - "EventCode": "0x76", - "EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH", - "PerPkg": "1", - "UMask": "0x7", - "Unit": "M2M" - }, - { - "BriefDescription": ": Channel 0", - "EventCode": "0x76", - "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": ": Channel 1", - "EventCode": "0x76", - "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "UNC_M2M_PREFCAM_RxC_CYCLES_NE", - "EventCode": "0x79", - "EventName": "UNC_M2M_PREFCAM_RxC_CYCLES_NE", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", - "EventCode": "0x7A", - "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", - "EventCode": "0x7A", - "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", - "EventCode": "0x7A", - "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "UNC_M2M_PREFCAM_RxC_INSERTS", - "EventCode": "0x78", - "EventName": "UNC_M2M_PREFCAM_RxC_INSERTS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", - "EventCode": "0x77", - "EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD", - "EventCode": "0xAC", - "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK", - "EventCode": "0xAC", - "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL", - "EventCode": "0xAC", - "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV", - "EventCode": "0xAC", - "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : AD", - "EventCode": "0xAA", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core", - "EventCode": "0xAA", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.", - "EventCode": "0xAA", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.AKC", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core", - "EventCode": "0xAA", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.", - "EventCode": "0xAA", - "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : AD", - "EventCode": "0xAD", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : AK", - "EventCode": "0xAD", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1", - "EventCode": "0xAD", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : BL", - "EventCode": "0xAD", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : IV", - "EventCode": "0xAD", - "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : AD", - "EventCode": "0xAB", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core", - "EventCode": "0xAB", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring", - "EventCode": "0xAB", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AKC", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core", - "EventCode": "0xAB", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.", - "EventCode": "0xAB", - "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Source Throttle", - "EventCode": "0xae", - "EventName": "UNC_M2M_RING_SRC_THRTL", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 0", - "EventCode": "0x43", - "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : Channel 1", - "EventCode": "0x43", - "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 0", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : Channel 1", - "EventCode": "0x44", - "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Ingress (from CMS) Full", - "EventCode": "0x04", - "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Ingress (from CMS) Not Empty", - "EventCode": "0x03", - "EventName": "UNC_M2M_RxC_AD_CYCLES_NE", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Ingress (from CMS) Allocations", - "EventCode": "0x01", - "EventName": "UNC_M2M_RxC_AD_INSERTS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Ingress (from CMS) Occupancy", - "EventCode": "0x02", - "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches", - "EventCode": "0x77", - "EventName": "UNC_M2M_RxC_AD_PREF_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations", - "EventCode": "0x5C", - "EventName": "UNC_M2M_RxC_AK_WR_CMP", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Ingress (from CMS) Full", - "EventCode": "0x08", - "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Ingress (from CMS) Not Empty", - "EventCode": "0x07", - "EventName": "UNC_M2M_RxC_BL_CYCLES_NE", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Ingress (from CMS) Allocations", - "EventCode": "0x05", - "EventName": "UNC_M2M_RxC_BL_INSERTS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Ingress (from CMS) Occupancy", - "EventCode": "0x06", - "EventName": "UNC_M2M_RxC_BL_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - All", - "EventCode": "0xE5", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Credited", - "EventCode": "0xE5", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", - "EventCode": "0xE5", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - All", - "EventCode": "0xE5", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Credited", - "EventCode": "0xE5", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", - "EventCode": "0xE5", - "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AD - All", - "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AD - Credited", - "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", - "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AK", - "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", - "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass : BL - All", - "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass : BL - Credited", - "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", - "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Bypass : IV", - "EventCode": "0xE2", - "EventName": "UNC_M2M_RxR_BYPASS.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - All", - "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Credited", - "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", - "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : AK", - "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - All", - "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Credited", - "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", - "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : IFV - Credited", - "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation : IV", - "EventCode": "0xE3", - "EventName": "UNC_M2M_RxR_CRD_STARVED.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Injection Starvation", - "EventCode": "0xe4", - "EventName": "UNC_M2M_RxR_CRD_STARVED_1", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AD - All", - "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AD - Credited", - "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited", - "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AK", - "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited", - "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations : BL - All", - "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations : BL - Credited", - "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited", - "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Allocations : IV", - "EventCode": "0xE1", - "EventName": "UNC_M2M_RxR_INSERTS.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AD - All", - "EventCode": "0xE0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", - "EventCode": "0xE0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited", - "EventCode": "0xE0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AK", - "EventCode": "0xE0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited", - "EventCode": "0xE0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : BL - All", - "EventCode": "0xE0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", - "EventCode": "0xE0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited", - "EventCode": "0xE0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : IV", - "EventCode": "0xE0", - "EventName": "UNC_M2M_RxR_OCCUPANCY.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7", - "EventCode": "0xD0", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7", - "EventCode": "0xD2", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7", - "EventCode": "0xD4", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7", - "EventCode": "0xD6", - "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10", - "EventCode": "0xD1", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8", - "EventCode": "0xD1", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9", - "EventCode": "0xD1", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10", - "EventCode": "0xD3", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8", - "EventCode": "0xD3", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9", - "EventCode": "0xD3", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10", - "EventCode": "0xD5", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8", - "EventCode": "0xD5", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9", - "EventCode": "0xD5", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10", - "EventCode": "0xD7", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8", - "EventCode": "0xD7", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9", - "EventCode": "0xD7", - "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Number AD Ingress Credits", - "EventCode": "0x41", - "EventName": "UNC_M2M_TGR_AD_CREDITS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Number BL Ingress Credits", - "EventCode": "0x42", - "EventName": "UNC_M2M_TGR_BL_CREDITS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Cycles Full : Channel 0", - "EventCode": "0x45", - "EventName": "UNC_M2M_TRACKER_FULL.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Cycles Full : Channel 1", - "EventCode": "0x45", - "EventName": "UNC_M2M_TRACKER_FULL.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Inserts : Channel 0", - "EventCode": "0x49", - "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Inserts : Channel 1", - "EventCode": "0x49", - "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Cycles Not Empty : Channel 0", - "EventCode": "0x46", - "EventName": "UNC_M2M_TRACKER_NE.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Cycles Not Empty : Channel 1", - "EventCode": "0x46", - "EventName": "UNC_M2M_TRACKER_NE.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Occupancy : Channel 0", - "EventCode": "0x47", - "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Tracker Occupancy : Channel 1", - "EventCode": "0x47", - "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Egress (to CMS) Credit Acquired", - "EventCode": "0x0d", - "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Egress (to CMS) Credits Occupancy", - "EventCode": "0x0e", - "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Egress (to CMS) Full", - "EventCode": "0x0c", - "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Egress (to CMS) Not Empty", - "EventCode": "0x0b", - "EventName": "UNC_M2M_TxC_AD_CYCLES_NE", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Egress (to CMS) Allocations", - "EventCode": "0x09", - "EventName": "UNC_M2M_TxC_AD_INSERTS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles with No AD Egress (to CMS) Credits", - "EventCode": "0x0f", - "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Credits", - "EventCode": "0x10", - "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AD Egress (to CMS) Occupancy", - "EventCode": "0x0A", - "EventName": "UNC_M2M_TxC_AD_OCCUPANCY", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "Outbound Ring Transactions on AK : CRD Transactions to Cbo", - "EventCode": "0x39", - "EventName": "UNC_M2M_TxC_AK.CRD_CBO", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Outbound Ring Transactions on AK : NDR Transactions", - "EventCode": "0x39", - "EventName": "UNC_M2M_TxC_AK.NDR", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AKC Credits", - "EventCode": "0x5F", - "EventName": "UNC_M2M_TxC_AKC_CREDITS", - "PerPkg": "1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side", - "EventCode": "0x1D", - "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side", - "EventCode": "0x1D", - "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full : All", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Near Side", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - Far Side", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1", - "PerPkg": "1", - "UMask": "0x88", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1", - "PerPkg": "1", - "UMask": "0xa0", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Full", - "EventCode": "0x14", - "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1", - "PerPkg": "1", - "UMask": "0x90", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Not Empty : All", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Near Side", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh Stop - Far Side", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Not Empty", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Not Empty", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Not Empty", - "EventCode": "0x13", - "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations : All", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Near Side", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh Stop - Far Side", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Allocations", - "EventCode": "0x11", - "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side", - "EventCode": "0x1F", - "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side", - "EventCode": "0x1F", - "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Near Side", - "EventCode": "0x20", - "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Credits : Common Mesh Stop - Far Side", - "EventCode": "0x20", - "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Occupancy : All", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Near Side", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh Stop - Far Side", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Occupancy", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Occupancy", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "AK Egress (to CMS) Occupancy", - "EventCode": "0x12", - "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Cache", - "EventCode": "0x40", - "EventName": "UNC_M2M_TxC_BL.DRS_CACHE", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Outbound DRS Ring Transactions to Cache : Data to Core", - "EventCode": "0x40", - "EventName": "UNC_M2M_TxC_BL.DRS_CORE", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Near Side", - "EventCode": "0x19", - "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common Mesh Stop - Far Side", - "EventCode": "0x19", - "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Full : All", - "EventCode": "0x18", - "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Near Side", - "EventCode": "0x18", - "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - Far Side", - "EventCode": "0x18", - "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Not Empty : All", - "EventCode": "0x17", - "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Near Side", - "EventCode": "0x17", - "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh Stop - Far Side", - "EventCode": "0x17", - "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Allocations : All", - "EventCode": "0x15", - "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL", - "PerPkg": "1", - "UMask": "0x3", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Near Side", - "EventCode": "0x15", - "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh Stop - Far Side", - "EventCode": "0x15", - "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side", - "EventCode": "0x1B", - "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side", - "EventCode": "0x1B", - "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Near Side", - "EventCode": "0x1C", - "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Credits : Common Mesh Stop - Far Side", - "EventCode": "0x1C", - "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : AD - All", - "EventCode": "0xA6", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", - "EventCode": "0xA6", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", - "EventCode": "0xA6", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : BL - All", - "EventCode": "0xA6", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", - "EventCode": "0xA6", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", - "EventCode": "0xA6", - "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AD - All", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AK", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : BL - All", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : IV", - "EventCode": "0xA7", - "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV", - "EventCode": "0xA2", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV", - "EventCode": "0xA3", - "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AK", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : IV", - "EventCode": "0xA1", - "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AK", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : IV", - "EventCode": "0xA4", - "EventName": "UNC_M2M_TxR_HORZ_NACK.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AK", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : IV", - "EventCode": "0xA0", - "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All", - "EventCode": "0xA5", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited", - "EventCode": "0xA5", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK", - "EventCode": "0xA5", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited", - "EventCode": "0xA5", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x80", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All", - "EventCode": "0xA5", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited", - "EventCode": "0xA5", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV", - "EventCode": "0xA5", - "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", - "EventCode": "0x9C", - "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", - "EventCode": "0x9D", - "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", - "EventCode": "0x9E", - "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0", - "EventCode": "0x95", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1", - "EventCode": "0x95", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0", - "EventCode": "0x97", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1", - "EventCode": "0x97", - "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M2M_TxR_VERT_INSERTS0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : IV", - "EventCode": "0x98", - "EventName": "UNC_M2M_TxR_VERT_NACK0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", - "EventCode": "0x99", - "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", - "EventCode": "0x99", - "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x40", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : IV", - "EventCode": "0x9A", - "EventName": "UNC_M2M_TxR_VERT_STARVED0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", - "EventCode": "0x9B", - "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1", - "EventCode": "0x9B", - "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", - "EventCode": "0x9B", - "EventName": "UNC_M2M_TxR_VERT_STARVED1.TGC", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Down and Even", - "EventCode": "0xB0", - "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Down and Odd", - "EventCode": "0xB0", - "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Up and Even", - "EventCode": "0xB0", - "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Up and Odd", - "EventCode": "0xB0", - "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Down and Even", - "EventCode": "0xB4", - "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", - "EventCode": "0xB4", - "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Up and Even", - "EventCode": "0xB4", - "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", - "EventCode": "0xB4", - "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Down and Even", - "EventCode": "0xB1", - "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Down and Odd", - "EventCode": "0xB1", - "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Up and Even", - "EventCode": "0xB1", - "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Up and Odd", - "EventCode": "0xB1", - "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Down and Even", - "EventCode": "0xB2", - "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Down and Odd", - "EventCode": "0xB2", - "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Up and Even", - "EventCode": "0xB2", - "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Up and Odd", - "EventCode": "0xB2", - "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical IV Ring in Use : Down", - "EventCode": "0xB3", - "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN", - "PerPkg": "1", - "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical IV Ring in Use : Up", - "EventCode": "0xB3", - "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP", - "PerPkg": "1", - "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Down and Even", - "EventCode": "0xB5", - "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", - "EventCode": "0xB5", - "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Up and Even", - "EventCode": "0xB5", - "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", - "EventCode": "0xB5", - "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "WPQ Flush : Channel 0", - "EventCode": "0x58", - "EventName": "UNC_M2M_WPQ_FLUSH.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "WPQ Flush : Channel 1", - "EventCode": "0x58", - "EventName": "UNC_M2M_WPQ_FLUSH.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 0", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 1", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Channel 2", - "EventCode": "0x4D", - "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 0", - "EventCode": "0x4E", - "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 1", - "EventCode": "0x4E", - "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Channel 2", - "EventCode": "0x4E", - "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Full : Channel 0", - "EventCode": "0x4A", - "EventName": "UNC_M2M_WR_TRACKER_FULL.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Full : Channel 1", - "EventCode": "0x4A", - "EventName": "UNC_M2M_WR_TRACKER_FULL.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Full : Mirror", - "EventCode": "0x4A", - "EventName": "UNC_M2M_WR_TRACKER_FULL.MIRR", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Inserts : Channel 0", - "EventCode": "0x56", - "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Inserts : Channel 1", - "EventCode": "0x56", - "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Not Empty : Channel 0", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WR_TRACKER_NE.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Not Empty : Channel 1", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WR_TRACKER_NE.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Not Empty : Mirror", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Not Empty", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Cycles Not Empty", - "EventCode": "0x4B", - "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0", - "EventCode": "0x63", - "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1", - "EventCode": "0x63", - "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 0", - "EventCode": "0x62", - "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel 1", - "EventCode": "0x62", - "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Occupancy : Channel 0", - "EventCode": "0x55", - "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Occupancy : Channel 1", - "EventCode": "0x55", - "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Occupancy : Mirror", - "EventCode": "0x55", - "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Occupancy", - "EventCode": "0x55", - "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_NONTGR", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Occupancy", - "EventCode": "0x55", - "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_PWR", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Posted Inserts : Channel 0", - "EventCode": "0x5E", - "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Posted Inserts : Channel 1", - "EventCode": "0x5E", - "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Posted Occupancy : Channel 0", - "EventCode": "0x5D", - "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2M" - }, - { - "BriefDescription": "Write Tracker Posted Occupancy : Channel 1", - "EventCode": "0x5D", - "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2M" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0", - "EventCode": "0x80", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1", - "EventCode": "0x80", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2", - "EventCode": "0x80", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3", - "EventCode": "0x80", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4", - "EventCode": "0x80", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5", - "EventCode": "0x80", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6", - "EventCode": "0x80", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7", - "EventCode": "0x80", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10", - "EventCode": "0x81", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8", - "EventCode": "0x81", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9", - "EventCode": "0x81", - "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0", - "EventCode": "0x82", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1", - "EventCode": "0x82", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2", - "EventCode": "0x82", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3", - "EventCode": "0x82", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4", - "EventCode": "0x82", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5", - "EventCode": "0x82", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6", - "EventCode": "0x82", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7", - "EventCode": "0x82", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10", - "EventCode": "0x83", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8", - "EventCode": "0x83", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9", - "EventCode": "0x83", - "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0", - "EventCode": "0x88", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1", - "EventCode": "0x88", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2", - "EventCode": "0x88", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3", - "EventCode": "0x88", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4", - "EventCode": "0x88", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5", - "EventCode": "0x88", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6", - "EventCode": "0x88", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7", - "EventCode": "0x88", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10", - "EventCode": "0x89", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8", - "EventCode": "0x89", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9", - "EventCode": "0x89", - "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0", - "EventCode": "0x8a", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1", - "EventCode": "0x8a", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2", - "EventCode": "0x8a", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3", - "EventCode": "0x8a", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4", - "EventCode": "0x8a", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5", - "EventCode": "0x8a", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6", - "EventCode": "0x8a", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7", - "EventCode": "0x8a", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10", - "EventCode": "0x8b", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8", - "EventCode": "0x8b", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9", - "EventCode": "0x8b", - "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0", - "EventCode": "0x84", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1", - "EventCode": "0x84", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2", - "EventCode": "0x84", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3", - "EventCode": "0x84", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4", - "EventCode": "0x84", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5", - "EventCode": "0x84", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6", - "EventCode": "0x84", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7", - "EventCode": "0x84", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10", - "EventCode": "0x85", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8", - "EventCode": "0x85", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9", - "EventCode": "0x85", - "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgress 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0", - "EventCode": "0x86", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1", - "EventCode": "0x86", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2", - "EventCode": "0x86", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3", - "EventCode": "0x86", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4", - "EventCode": "0x86", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5", - "EventCode": "0x86", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6", - "EventCode": "0x86", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7", - "EventCode": "0x86", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10", - "EventCode": "0x87", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8", - "EventCode": "0x87", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9", - "EventCode": "0x87", - "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0", - "EventCode": "0x8c", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1", - "EventCode": "0x8c", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2", - "EventCode": "0x8c", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3", - "EventCode": "0x8c", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", - "EventCode": "0x8c", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", - "EventCode": "0x8c", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4", - "EventCode": "0x8c", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5", - "EventCode": "0x8c", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10", - "EventCode": "0x8d", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8", - "EventCode": "0x8d", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9", - "EventCode": "0x8d", - "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgress 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0", - "EventCode": "0x8e", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR0", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1", - "EventCode": "0x8e", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR1", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2", - "EventCode": "0x8e", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR2", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3", - "EventCode": "0x8e", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR3", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4", - "EventCode": "0x8e", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR4", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5", - "EventCode": "0x8e", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR5", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6", - "EventCode": "0x8e", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR6", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7", - "EventCode": "0x8e", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR7", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10", - "EventCode": "0x8f", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR10", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8", - "EventCode": "0x8f", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR8", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9", - "EventCode": "0x8f", - "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR9", - "PerPkg": "1", - "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transgress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per transgress", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Clockticks of the mesh to PCI (M2P)", - "EventCode": "0x01", - "EventName": "UNC_M2P_CLOCKTICKS", - "PerPkg": "1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Clockticks", - "EventCode": "0xc0", - "EventName": "UNC_M2P_CMS_CLOCKTICKS", - "PerPkg": "1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Distress signal asserted : DPT Local", - "EventCode": "0xaf", - "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_LOCAL", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Local : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle triggered by this tile", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Distress signal asserted : DPT Remote", - "EventCode": "0xaf", - "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_NONLOCAL", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Remote : Counts the number of cycles either the local or incoming distress signals are asserted. : Dynamic Prefetch Throttle received by this tile", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Distress signal asserted : DPT Stalled - IV", - "EventCode": "0xaf", - "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_IV", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Stalled - IV : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while regular IVs were received, causing DPT to be stalled", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Distress signal asserted : DPT Stalled - No Credit", - "EventCode": "0xaf", - "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_NOCRD", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : DPT Stalled - No Credit : Counts the number of cycles either the local or incoming distress signals are asserted. : DPT occurred while credit not available causing DPT to be stalled", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Distress signal asserted : Horizontal", - "EventCode": "0xaf", - "EventName": "UNC_M2P_DISTRESS_ASSERTED.HORZ", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : Horizontal : Counts the number of cycles either the local or incoming distress signals are asserted. : If TGR egress is full, then agents will throttle outgoing AD IDI transactions", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Distress signal asserted : Vertical", - "EventCode": "0xaf", - "EventName": "UNC_M2P_DISTRESS_ASSERTED.VERT", - "PerPkg": "1", - "PublicDescription": "Distress signal asserted : Vertical : Counts the number of cycles either the local or incoming distress signals are asserted. : If IRQ egress is full, then agents will throttle outgoing AD IDI transactions", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements : Down", - "EventCode": "0xba", - "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN", - "PerPkg": "1", - "PublicDescription": "Egress Blocking due to Ordering requirements : Down : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress Blocking due to Ordering requirements : Up", - "EventCode": "0xba", - "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP", - "PerPkg": "1", - "PublicDescription": "Egress Blocking due to Ordering requirements : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Left and Even", - "EventCode": "0xb6", - "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", - "EventCode": "0xb6", - "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Right and Even", - "EventCode": "0xb6", - "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", - "EventCode": "0xb6", - "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Even", - "EventCode": "0xbb", - "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", - "EventCode": "0xbb", - "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Even", - "EventCode": "0xbb", - "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", - "EventCode": "0xbb", - "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Even", - "EventCode": "0xb7", - "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", - "EventCode": "0xb7", - "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Even", - "EventCode": "0xb7", - "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Even : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", - "EventCode": "0xb7", - "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : Counts the number of cycles that the Horizontal AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Left and Even", - "EventCode": "0xb8", - "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Left and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", - "EventCode": "0xb8", - "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Right and Even", - "EventCode": "0xb8", - "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_EVEN", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Right and Even : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", - "EventCode": "0xb8", - "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_ODD", - "PerPkg": "1", - "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : Counts the number of cycles that the Horizontal BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal IV Ring in Use : Left", - "EventCode": "0xb9", - "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.LEFT", - "PerPkg": "1", - "PublicDescription": "Horizontal IV Ring in Use : Left : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Horizontal IV Ring in Use : Right", - "EventCode": "0xb9", - "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.RIGHT", - "PerPkg": "1", - "PublicDescription": "Horizontal IV Ring in Use : Right : Counts the number of cycles that the Horizontal IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", - "EventCode": "0x33", - "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", - "EventCode": "0x33", - "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", - "EventCode": "0x33", - "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", - "EventCode": "0x33", - "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", - "EventCode": "0x33", - "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", - "EventCode": "0x33", - "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts the number of credits that are acquired in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS", - "EventCode": "0x34", - "EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the DRS message class.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB", - "EventCode": "0x34", - "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCB message class.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS", - "EventCode": "0x34", - "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS : Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits to the IIO for the NCS message class.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0", - "EventCode": "0x32", - "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1", - "EventCode": "0x32", - "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS message class.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0", - "EventCode": "0x32", - "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1", - "EventCode": "0x32", - "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB message class.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0", - "EventCode": "0x32", - "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS message class.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1", - "EventCode": "0x32", - "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1", - "PerPkg": "1", - "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1 : Counts the number of cycles when one or more credits in the M2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS message class.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCB", - "EventCode": "0x46", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF0 - NCS", - "EventCode": "0x46", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCB", - "EventCode": "0x46", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF1 - NCS", - "EventCode": "0x46", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCB", - "EventCode": "0x46", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF2 - NCS", - "EventCode": "0x46", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCB", - "EventCode": "0x46", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF3 - NCS", - "EventCode": "0x46", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCB", - "EventCode": "0x47", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF4 - NCS", - "EventCode": "0x47", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCB", - "EventCode": "0x47", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF5 - NCS", - "EventCode": "0x47", - "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCB", - "EventCode": "0x19", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF0 - NCS", - "EventCode": "0x19", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCB", - "EventCode": "0x19", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF1 - NCS", - "EventCode": "0x19", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCB", - "EventCode": "0x19", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF2 - NCS", - "EventCode": "0x19", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCB", - "EventCode": "0x19", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2IOSF3 - NCS", - "EventCode": "0x19", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCB", - "EventCode": "0x1a", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF4 - NCS", - "EventCode": "0x1a", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCB", - "EventCode": "0x1a", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2IOSF5 - NCS", - "EventCode": "0x1a", - "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Shared Credits Returned : Agent0", - "EventCode": "0x17", - "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Shared Credits Returned : Agent1", - "EventCode": "0x17", - "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local P2P Shared Credits Returned : Agent2", - "EventCode": "0x17", - "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent0", - "EventCode": "0x44", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent1", - "EventCode": "0x44", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent2", - "EventCode": "0x44", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent3", - "EventCode": "0x44", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent4", - "EventCode": "0x44", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Returned to credit ring : Agent5", - "EventCode": "0x44", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCB", - "EventCode": "0x40", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 - NCS", - "EventCode": "0x40", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCB", - "EventCode": "0x40", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 - NCS", - "EventCode": "0x40", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCB", - "EventCode": "0x40", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 - NCS", - "EventCode": "0x40", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCB", - "EventCode": "0x40", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 - NCS", - "EventCode": "0x40", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCB", - "EventCode": "0x41", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 - NCS", - "EventCode": "0x41", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCB", - "EventCode": "0x41", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 - NCS", - "EventCode": "0x41", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCB", - "EventCode": "0x4a", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF0 - NCS", - "EventCode": "0x4a", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCB", - "EventCode": "0x4a", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF1 - NCS", - "EventCode": "0x4a", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCB", - "EventCode": "0x4a", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF2 - NCS", - "EventCode": "0x4a", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCB", - "EventCode": "0x4a", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IOSF3 - NCS", - "EventCode": "0x4a", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCB", - "EventCode": "0x4b", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF4 - NCS", - "EventCode": "0x4b", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCB", - "EventCode": "0x4b", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IOSF5 - NCS", - "EventCode": "0x4b", - "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI0", - "EventCode": "0xe6", - "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : Number of cycles MBE is high for MS2IDI1", - "EventCode": "0xe6", - "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "P2P Credit Occupancy : All", - "EventCode": "0x14", - "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "P2P Credit Occupancy : Local NCB", - "EventCode": "0x14", - "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "P2P Credit Occupancy : Local NCS", - "EventCode": "0x14", - "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "P2P Credit Occupancy : Remote NCB", - "EventCode": "0x14", - "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "P2P Credit Occupancy : Remote NCS", - "EventCode": "0x14", - "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Dedicated Credits Received : All", - "EventCode": "0x16", - "EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Dedicated Credits Received : Local NCB", - "EventCode": "0x16", - "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Dedicated Credits Received : Local NCS", - "EventCode": "0x16", - "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Dedicated Credits Received : Remote NCB", - "EventCode": "0x16", - "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Dedicated Credits Received : Remote NCS", - "EventCode": "0x16", - "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Shared Credits Received : All", - "EventCode": "0x15", - "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Shared Credits Received : Local NCB", - "EventCode": "0x15", - "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Shared Credits Received : Local NCS", - "EventCode": "0x15", - "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Shared Credits Received : Remote NCB", - "EventCode": "0x15", - "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Shared Credits Received : Remote NCS", - "EventCode": "0x15", - "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote P2P Shared Credits Returned : Agent0", - "EventCode": "0x18", - "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote P2P Shared Credits Returned : Agent1", - "EventCode": "0x18", - "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote P2P Shared Credits Returned : Agent2", - "EventCode": "0x18", - "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent0", - "EventCode": "0x45", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent1", - "EventCode": "0x45", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Remote Shared P2P Credit Returned to credit ring : Agent2", - "EventCode": "0x45", - "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : AD", - "EventCode": "0xac", - "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AD", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : AD : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : AK", - "EventCode": "0xac", - "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AK", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : AK : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : BL", - "EventCode": "0xac", - "EventName": "UNC_M2P_RING_BOUNCES_HORZ.BL", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : BL : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Messages that bounced on the Horizontal Ring. : IV", - "EventCode": "0xac", - "EventName": "UNC_M2P_RING_BOUNCES_HORZ.IV", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Horizontal Ring. : IV : Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : AD", - "EventCode": "0xaa", - "EventName": "UNC_M2P_RING_BOUNCES_VERT.AD", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : AD : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core", - "EventCode": "0xaa", - "EventName": "UNC_M2P_RING_BOUNCES_VERT.AK", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Acknowledgements to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring.", - "EventCode": "0xaa", - "EventName": "UNC_M2P_RING_BOUNCES_VERT.AKC", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core", - "EventCode": "0xaa", - "EventName": "UNC_M2P_RING_BOUNCES_VERT.BL", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Data Responses to core : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache.", - "EventCode": "0xaa", - "EventName": "UNC_M2P_RING_BOUNCES_VERT.IV", - "PerPkg": "1", - "PublicDescription": "Messages that bounced on the Vertical Ring. : Snoops of processor's cache. : Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : AD", - "EventCode": "0xad", - "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : AK", - "EventCode": "0xad", - "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowledgements to Agent 1", - "EventCode": "0xad", - "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK_AG1", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : BL", - "EventCode": "0xad", - "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Sink Starvation on Horizontal Ring : IV", - "EventCode": "0xad", - "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : AD", - "EventCode": "0xab", - "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AD", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledgements to core", - "EventCode": "0xab", - "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AK", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring", - "EventCode": "0xab", - "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AKC", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : Data Responses to core", - "EventCode": "0xab", - "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.BL", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of processor's cache.", - "EventCode": "0xab", - "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.IV", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Source Throttle", - "EventCode": "0xae", - "EventName": "UNC_M2P_RING_SRC_THRTL", - "PerPkg": "1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", - "EventCode": "0x10", - "EventName": "UNC_M2P_RxC_CYCLES_NE.ALL", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", - "EventCode": "0x10", - "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", - "EventCode": "0x10", - "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", - "EventCode": "0x10", - "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", - "EventCode": "0x10", - "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", - "EventCode": "0x10", - "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : Counts the number of cycles when the M2PCIe Ingress is not empty.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Inserts", - "EventCode": "0x11", - "EventName": "UNC_M2P_RxC_INSERTS.ALL", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Inserts", - "EventCode": "0x11", - "EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Inserts", - "EventCode": "0x11", - "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Inserts", - "EventCode": "0x11", - "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Inserts", - "EventCode": "0x11", - "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Ingress (from CMS) Queue Inserts", - "EventCode": "0x11", - "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS", - "PerPkg": "1", - "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts the number of entries inserted into the M2PCIe Ingress Queue. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - All", - "EventCode": "0xe5", - "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Credited", - "EventCode": "0xe5", - "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", - "EventCode": "0xe5", - "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - All", - "EventCode": "0xe5", - "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Credited", - "EventCode": "0xe5", - "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", - "EventCode": "0xe5", - "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AD - All", - "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AD - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AD - Credited", - "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AD - Credited : Number of packets bypassing the CMS Ingress", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", - "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited : Number of packets bypassing the CMS Ingress", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AK", - "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AK : Number of packets bypassing the CMS Ingress", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", - "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited : Number of packets bypassing the CMS Ingress", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Bypass : BL - All", - "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : BL - All : Number of packets bypassing the CMS Ingress : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Bypass : BL - Credited", - "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : BL - Credited : Number of packets bypassing the CMS Ingress", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", - "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited : Number of packets bypassing the CMS Ingress", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Bypass : IV", - "EventCode": "0xe2", - "EventName": "UNC_M2P_RxR_BYPASS.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Bypass : IV : Number of packets bypassing the CMS Ingress", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - All", - "EventCode": "0xe3", - "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Credited", - "EventCode": "0xe3", - "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : AD - Uncredited", - "EventCode": "0xe3", - "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AD - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : AK", - "EventCode": "0xe3", - "EventName": "UNC_M2P_RxR_CRD_STARVED.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : AK : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - All", - "EventCode": "0xe3", - "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - All : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Credited", - "EventCode": "0xe3", - "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : BL - Uncredited", - "EventCode": "0xe3", - "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : BL - Uncredited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : IFV - Credited", - "EventCode": "0xe3", - "EventName": "UNC_M2P_RxR_CRD_STARVED.IFV", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : IFV - Credited : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation : IV", - "EventCode": "0xe3", - "EventName": "UNC_M2P_RxR_CRD_STARVED.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : IV : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Injection Starvation", - "EventCode": "0xe4", - "EventName": "UNC_M2P_RxR_CRD_STARVED_1", - "PerPkg": "1", - "PublicDescription": "Transgress Injection Starvation : Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit.", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AD - All", - "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AD - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AD - Credited", - "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AD - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AD - Uncredited", - "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AD - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AK", - "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AK : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Allocations : AKC - Uncredited", - "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : AKC - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Allocations : BL - All", - "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : BL - All : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Allocations : BL - Credited", - "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : BL - Credited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Allocations : BL - Uncredited", - "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : BL - Uncredited : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Allocations : IV", - "EventCode": "0xe1", - "EventName": "UNC_M2P_RxR_INSERTS.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Allocations : IV : Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AD - All", - "EventCode": "0xe0", - "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AD - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", - "EventCode": "0xe0", - "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AD - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredited", - "EventCode": "0xe0", - "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AK", - "EventCode": "0xe0", - "EventName": "UNC_M2P_RxR_OCCUPANCY.AK", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AK : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredited", - "EventCode": "0xe0", - "EventName": "UNC_M2P_RxR_OCCUPANCY.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : BL - All", - "EventCode": "0xe0", - "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : BL - All : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", - "EventCode": "0xe0", - "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : BL - Credited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredited", - "EventCode": "0xe0", - "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredited : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Transgress Ingress Occupancy : IV", - "EventCode": "0xe0", - "EventName": "UNC_M2P_RxR_OCCUPANCY.IV", - "PerPkg": "1", - "PublicDescription": "Transgress Ingress Occupancy : IV : Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0", - "EventCode": "0xd0", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1", - "EventCode": "0xd0", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2", - "EventCode": "0xd0", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3", - "EventCode": "0xd0", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4", - "EventCode": "0xd0", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5", - "EventCode": "0xd0", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6", - "EventCode": "0xd0", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7", - "EventCode": "0xd0", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0", - "EventCode": "0xd2", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1", - "EventCode": "0xd2", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2", - "EventCode": "0xd2", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3", - "EventCode": "0xd2", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4", - "EventCode": "0xd2", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5", - "EventCode": "0xd2", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6", - "EventCode": "0xd2", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7", - "EventCode": "0xd2", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0", - "EventCode": "0xd4", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1", - "EventCode": "0xd4", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2", - "EventCode": "0xd4", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3", - "EventCode": "0xd4", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4", - "EventCode": "0xd4", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5", - "EventCode": "0xd4", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6", - "EventCode": "0xd4", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7", - "EventCode": "0xd4", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0", - "EventCode": "0xd6", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1", - "EventCode": "0xd6", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2", - "EventCode": "0xd6", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3", - "EventCode": "0xd6", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4", - "EventCode": "0xd6", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5", - "EventCode": "0xd6", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6", - "EventCode": "0xd6", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7", - "EventCode": "0xd6", - "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10", - "EventCode": "0xd1", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8", - "EventCode": "0xd1", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9", - "EventCode": "0xd1", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent0 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10", - "EventCode": "0xd3", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8", - "EventCode": "0xd3", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9", - "EventCode": "0xd3", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No AD Agent1 Transgress Credits : For Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10", - "EventCode": "0xd5", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8", - "EventCode": "0xd5", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9", - "EventCode": "0xd5", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent0 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10", - "EventCode": "0xd7", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8", - "EventCode": "0xd7", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9", - "EventCode": "0xd7", - "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", - "PerPkg": "1", - "PublicDescription": "Stall on No BL Agent1 Transgress Credits : For Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ", - "EventCode": "0x2d", - "EventName": "UNC_M2P_TxC_CREDITS.PRQ", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Full", - "EventCode": "0x25", - "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_0", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Full", - "EventCode": "0x25", - "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_1", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Full", - "EventCode": "0x25", - "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_0", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Full", - "EventCode": "0x25", - "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_1", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Full", - "EventCode": "0x25", - "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_0", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Full", - "EventCode": "0x25", - "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_1", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Full : Counts the number of cycles when the M2PCIe Egress is full. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Not Empty", - "EventCode": "0x23", - "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_0", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Not Empty", - "EventCode": "0x23", - "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_1", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Not Empty", - "EventCode": "0x23", - "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_0", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Not Empty", - "EventCode": "0x23", - "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_1", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Not Empty", - "EventCode": "0x23", - "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_0", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Cycles Not Empty", - "EventCode": "0x23", - "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_1", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts the number of cycles when the M2PCIe Egress is not empty. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple egress buffers can be tracked at a given time using multiple counters.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Ingress", - "EventCode": "0x24", - "EventName": "UNC_M2P_TxC_INSERTS.AD_0", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Ingress", - "EventCode": "0x24", - "EventName": "UNC_M2P_TxC_INSERTS.AD_1", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Ingress", - "EventCode": "0x24", - "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_0", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Ingress", - "EventCode": "0x24", - "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_1", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Ingress", - "EventCode": "0x24", - "EventName": "UNC_M2P_TxC_INSERTS.BL_0", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Egress (to CMS) Ingress", - "EventCode": "0x24", - "EventName": "UNC_M2P_TxC_INSERTS.BL_1", - "PerPkg": "1", - "PublicDescription": "Egress (to CMS) Ingress : Counts the number of number of messages inserted into the the M2PCIe Egress queue. This tracks messages for one of the two CMS ports that are used by the M2PCIe agent. This can be used in conjunction with the M2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : AD - All", - "EventCode": "0xa6", - "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", - "EventCode": "0xa6", - "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", - "EventCode": "0xa6", - "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : BL - All", - "EventCode": "0xa6", - "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", - "EventCode": "0xa6", - "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", - "EventCode": "0xa6", - "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AD - All", - "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", - "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", - "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AK", - "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited", - "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : BL - All", - "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", - "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", - "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Bypass Used : IV", - "EventCode": "0xa7", - "EventName": "UNC_M2P_TxR_HORZ_BYPASS.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All", - "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited", - "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited", - "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AK", - "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AK", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited", - "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All", - "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited", - "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited", - "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : IV", - "EventCode": "0xa2", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.IV", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full : IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All", - "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited", - "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited", - "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK", - "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AK", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited", - "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All", - "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_ALL", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited", - "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_CRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited", - "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV", - "EventCode": "0xa3", - "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.IV", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Empty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty. The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", - "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited", - "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredited", - "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AK", - "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited", - "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", - "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited", - "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredited", - "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredited : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Inserts : IV", - "EventCode": "0xa1", - "EventName": "UNC_M2P_TxR_HORZ_INSERTS.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number of allocations into the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", - "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", - "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited", - "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AK", - "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited", - "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", - "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Counts number of Egress packets NACK'ed on to the Horizontal Ring : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", - "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited", - "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredited : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress NACKs : IV", - "EventCode": "0xa4", - "EventName": "UNC_M2P_TxR_HORZ_NACK.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Horizontal Ring", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", - "EventCode": "0xa0", - "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x11", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credited", - "EventCode": "0xa0", - "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited", - "EventCode": "0xa0", - "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AK", - "EventCode": "0xa0", - "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited", - "EventCode": "0xa0", - "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", - "EventCode": "0xa0", - "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh. : All == Credited + Uncredited", - "UMask": "0x44", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credited", - "EventCode": "0xa0", - "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_CRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited", - "EventCode": "0xa0", - "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncredited : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Occupancy : IV", - "EventCode": "0xa0", - "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occupancy event for the Transgress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - All", - "EventCode": "0xa5", - "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited", - "EventCode": "0xa5", - "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AD - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AK", - "EventCode": "0xa5", - "EventName": "UNC_M2P_TxR_HORZ_STARVED.AK", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AK : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited", - "EventCode": "0xa5", - "EventName": "UNC_M2P_TxR_HORZ_STARVED.AKC_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : AKC - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x80", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - All", - "EventCode": "0xa5", - "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_ALL", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - All : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time. : All == Credited + Uncredited", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited", - "EventCode": "0xa5", - "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_UNCRD", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : BL - Uncredited : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Horizontal Egress Injection Starvation : IV", - "EventCode": "0xa5", - "EventName": "UNC_M2P_TxR_HORZ_STARVED.IV", - "PerPkg": "1", - "PublicDescription": "CMS Horizontal Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", - "EventCode": "0x9c", - "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", - "EventCode": "0x9c", - "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", - "EventCode": "0x9c", - "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", - "EventCode": "0x9c", - "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", - "EventCode": "0x9d", - "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", - "EventCode": "0x9d", - "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", - "EventCode": "0x9d", - "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", - "EventCode": "0x9d", - "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", - "EventCode": "0x9d", - "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", - "EventCode": "0x9d", - "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", - "EventCode": "0x9d", - "EventName": "UNC_M2P_TxR_VERT_BYPASS.IV_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", - "EventCode": "0x9e", - "EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", - "EventCode": "0x9e", - "EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1", - "EventCode": "0x94", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1", - "EventCode": "0x94", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1", - "EventCode": "0x94", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0", - "EventCode": "0x94", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0", - "EventCode": "0x95", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1", - "EventCode": "0x95", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1", - "EventCode": "0x96", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1", - "EventCode": "0x96", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1", - "EventCode": "0x96", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0", - "EventCode": "0x96", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0", - "EventCode": "0x97", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1", - "EventCode": "0x97", - "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empty : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Empty. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", - "EventCode": "0x92", - "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", - "EventCode": "0x92", - "EventName": "UNC_M2P_TxR_VERT_INSERTS0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", - "EventCode": "0x93", - "EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", - "EventCode": "0x93", - "EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 : Number of allocations into the Common Mesh Stop Egress. The Egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", - "EventCode": "0x98", - "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", - "EventCode": "0x98", - "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : IV", - "EventCode": "0x98", - "EventName": "UNC_M2P_TxR_VERT_NACK0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", - "EventCode": "0x99", - "EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", - "EventCode": "0x99", - "EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : Counts number of Egress packets NACK'ed on to the Vertical Ring", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is commonly used for outbound requests.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is commonly used to send data from the cache to various destinations.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", - "EventCode": "0x90", - "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is commonly used for transferring writeback data to the cache.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", - "EventCode": "0x90", - "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is commonly used for snoops to the cores.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", - "EventCode": "0x91", - "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", - "EventCode": "0x91", - "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : Occupancy event for the Egress buffers in the Common Mesh Stop The egress is used to queue up requests destined for the Vertical Ring on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is commonly used for credit returns and GO responses.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0", - "EventCode": "0x9a", - "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1", - "EventCode": "0x9a", - "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AD - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x10", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0", - "EventCode": "0x9a", - "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1", - "EventCode": "0x9a", - "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AK - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x20", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0", - "EventCode": "0x9a", - "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1", - "EventCode": "0x9a", - "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : BL - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x40", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : IV", - "EventCode": "0x9a", - "EventName": "UNC_M2P_TxR_VERT_STARVED0.IV_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : IV : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", - "EventCode": "0x9b", - "EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG0", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1", - "EventCode": "0x9b", - "EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG1", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 1 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0", - "EventCode": "0x9b", - "EventName": "UNC_M2P_TxR_VERT_STARVED1.TGC", - "PerPkg": "1", - "PublicDescription": "CMS Vertical Egress Injection Starvation : AKC - Agent 0 : Counts injection starvation. This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Down and Even", - "EventCode": "0xb0", - "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Down and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Down and Odd", - "EventCode": "0xb0", - "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Up and Even", - "EventCode": "0xb0", - "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Up and Even : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AD Ring In Use : Up and Odd", - "EventCode": "0xb0", - "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Down and Even", - "EventCode": "0xb4", - "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Down and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", - "EventCode": "0xb4", - "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Up and Even", - "EventCode": "0xb4", - "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", - "EventCode": "0xb4", - "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AKC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Down and Even", - "EventCode": "0xb1", - "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Down and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Down and Odd", - "EventCode": "0xb1", - "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Up and Even", - "EventCode": "0xb1", - "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Up and Even : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical AK Ring In Use : Up and Odd", - "EventCode": "0xb1", - "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Counts the number of cycles that the Vertical AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Down and Even", - "EventCode": "0xb2", - "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Down and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Down and Odd", - "EventCode": "0xb2", - "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Up and Even", - "EventCode": "0xb2", - "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Up and Even : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical BL Ring in Use : Up and Odd", - "EventCode": "0xb2", - "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Counts the number of cycles that the Vertical BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical IV Ring in Use : Down", - "EventCode": "0xb3", - "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.DN", - "PerPkg": "1", - "PublicDescription": "Vertical IV Ring in Use : Down : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical IV Ring in Use : Up", - "EventCode": "0xb3", - "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.UP", - "PerPkg": "1", - "PublicDescription": "Vertical IV Ring in Use : Up : Counts the number of cycles that the Vertical IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. There is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_ODD.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Down and Even", - "EventCode": "0xb5", - "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Down and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x4", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", - "EventCode": "0xb5", - "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x8", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Up and Even", - "EventCode": "0xb5", - "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_EVEN", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x1", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", - "EventCode": "0xb5", - "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_ODD", - "PerPkg": "1", - "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Counts the number of cycles that the Vertical TGC ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.", - "UMask": "0x2", - "Unit": "M2PCIe" - }, - { - "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", - "EventCode": "0xff", - "EventName": "UNC_U_CLOCKTICKS", - "PerPkg": "1", - "Unit": "UBOX" - }, - { - "BriefDescription": "Message Received : Doorbell", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UBOX" - }, - { - "BriefDescription": "Message Received : Interrupt", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.INT_PRIO", - "PerPkg": "1", - "PublicDescription": "Message Received : Interrupt : Interrupts", - "UMask": "0x10", - "Unit": "UBOX" - }, - { - "BriefDescription": "Message Received : IPI", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", - "PerPkg": "1", - "PublicDescription": "Message Received : IPI : Inter Processor Interrupts", - "UMask": "0x4", - "Unit": "UBOX" - }, - { - "BriefDescription": "Message Received : MSI", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", - "PerPkg": "1", - "PublicDescription": "Message Received : MSI : Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only)", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "Message Received : VLW", - "EventCode": "0x42", - "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", - "PerPkg": "1", - "PublicDescription": "Message Received : VLW : Virtual Logical Wire (legacy) message were received from Uncore.", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "IDI Lock/SplitLock Cycles", - "EventCode": "0x44", - "EventName": "UNC_U_LOCK_CYCLES", - "PerPkg": "1", - "PublicDescription": "IDI Lock/SplitLock Cycles : Number of times an IDI Lock/SplitLock sequence was started", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", - "EventCode": "0x4D", - "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", - "EventCode": "0x4D", - "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", - "EventCode": "0x4D", - "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", - "EventCode": "0x4D", - "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", - "EventCode": "0x4E", - "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", - "EventCode": "0x4E", - "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", - "EventCode": "0x4E", - "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", - "EventCode": "0x4E", - "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", - "PerPkg": "1", - "UMask": "0x8", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", - "EventCode": "0x4E", - "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", - "PerPkg": "1", - "UMask": "0x20", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", - "EventCode": "0x4E", - "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", - "PerPkg": "1", - "UMask": "0x40", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", - "EventCode": "0x4E", - "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", - "PerPkg": "1", - "UMask": "0x10", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", - "EventCode": "0x4E", - "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", - "PerPkg": "1", - "UMask": "0x80", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", - "EventCode": "0x4F", - "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", - "EventCode": "0x4F", - "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK", - "EventCode": "0x45", - "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", - "PerPkg": "1", - "PublicDescription": "Cycles PHOLD Assert to Ack : Assert to ACK : PHOLD cycles.", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", - "EventCode": "0x4C", - "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", - "PerPkg": "1", - "UMask": "0x4", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_RACU_DRNG.RDRAND", - "EventCode": "0x4C", - "EventName": "UNC_U_RACU_DRNG.RDRAND", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "UBOX" - }, - { - "BriefDescription": "UNC_U_RACU_DRNG.RDSEED", - "EventCode": "0x4C", - "EventName": "UNC_U_RACU_DRNG.RDSEED", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "UBOX" - }, - { - "BriefDescription": "RACU Request", - "EventCode": "0x46", - "EventName": "UNC_U_RACU_REQUESTS", - "PerPkg": "1", - "PublicDescription": "RACU Request : Number outstanding register requests within message channel tracker", - "Unit": "UBOX" - } -] -- cgit v1.2.3-58-ga151 From ee31f6fea61c332100d2161081abbdfe65411fe9 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 13 Apr 2023 06:29:49 -0700 Subject: perf vendor events intel: Fix uncore topics for tigerlake Move events from 'uncore-other' topic classification to interconnect. Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Caleb Biggers Cc: Edward Baker Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Xing Zhengjun Link: https://lore.kernel.org/r/20230413132949.3487664-22-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/x86/tigerlake/uncore-interconnect.json | 90 ++++++++++++++++++++++ .../arch/x86/tigerlake/uncore-other.json | 88 --------------------- 2 files changed, 90 insertions(+), 88 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/tigerlake/uncore-interconnect.json (limited to 'tools') diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-interconnect.json new file mode 100644 index 000000000000..eed1b90a2779 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-interconnect.json @@ -0,0 +1,90 @@ +[ + { + "BriefDescription": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "EventCode": "0x84", + "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core.", + "EventCode": "0x85", + "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core.", + "EventCode": "0x85", + "EventName": "UNC_ARB_DAT_OCCUPANCY.RD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_REQ_TRK_REQUEST.DRD", + "EventCode": "0x81", + "EventName": "UNC_ARB_DAT_REQUESTS.RD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL", + "EventCode": "0x85", + "EventName": "UNC_ARB_IFA_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_OCCUPANCY.RD]", + "EventCode": "0x80", + "EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_REQUESTS.RD]", + "EventCode": "0x81", + "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle count number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from it's allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_OCCUPANCY.DRD]", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.RD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + }, + { + "BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_REQUEST.DRD]", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.RD", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "ARB" + } +] diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json index 6e43aaf64e28..c6596ba09195 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json @@ -1,92 +1,4 @@ [ - { - "BriefDescription": "UNC_ARB_COH_TRK_REQUESTS.ALL", - "EventCode": "0x84", - "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core.", - "EventCode": "0x85", - "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core.", - "EventCode": "0x85", - "EventName": "UNC_ARB_DAT_OCCUPANCY.RD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "ARB" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_REQ_TRK_REQUEST.DRD", - "EventCode": "0x81", - "EventName": "UNC_ARB_DAT_REQUESTS.RD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "ARB" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL", - "EventCode": "0x85", - "EventName": "UNC_ARB_IFA_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_OCCUPANCY.RD]", - "EventCode": "0x80", - "EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "ARB" - }, - { - "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_REQUESTS.RD]", - "EventCode": "0x81", - "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "ARB" - }, - { - "BriefDescription": "Each cycle count number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from it's allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.", - "EventCode": "0x80", - "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_OCCUPANCY.DRD]", - "EventCode": "0x80", - "EventName": "UNC_ARB_TRK_OCCUPANCY.RD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "ARB" - }, - { - "BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.ALL", - "PerPkg": "1", - "UMask": "0x1", - "Unit": "ARB" - }, - { - "BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_REQUEST.DRD]", - "EventCode": "0x81", - "EventName": "UNC_ARB_TRK_REQUESTS.RD", - "PerPkg": "1", - "UMask": "0x2", - "Unit": "ARB" - }, { "BriefDescription": "UNC_CLOCK.SOCKET", "EventCode": "0xff", -- cgit v1.2.3-58-ga151 From c160118a90d4acf335993d8d59b02ae2147a524e Mon Sep 17 00:00:00 2001 From: Markus Elfring Date: Thu, 13 Apr 2023 14:46:39 +0200 Subject: perf map: Delete two variable initialisations before null pointer checks in sort__sym_from_cmp() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Addresses of two data structure members were determined before corresponding null pointer checks in the implementation of the function “sort__sym_from_cmp”. Thus avoid the risk for undefined behaviour by removing extra initialisations for the local variables “from_l” and “from_r” (also because they were already reassigned with the same value behind this pointer check). This issue was detected by using the Coccinelle software. Fixes: 1b9e97a2a95e4941 ("perf tools: Fix report -F symbol_from for data without branch info") Signed-off-by: Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: German Gomez Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Link: https://lore.kernel.org/cocci/54a21fea-64e3-de67-82ef-d61b90ffad05@web.de/ Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/sort.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/sort.c b/tools/perf/util/sort.c index 80c9960c37e5..f2ffaf90648e 100644 --- a/tools/perf/util/sort.c +++ b/tools/perf/util/sort.c @@ -1020,8 +1020,7 @@ static int hist_entry__dso_to_filter(struct hist_entry *he, int type, static int64_t sort__sym_from_cmp(struct hist_entry *left, struct hist_entry *right) { - struct addr_map_symbol *from_l = &left->branch_info->from; - struct addr_map_symbol *from_r = &right->branch_info->from; + struct addr_map_symbol *from_l, *from_r; if (!left->branch_info || !right->branch_info) return cmp_null(left->branch_info, right->branch_info); -- cgit v1.2.3-58-ga151 From 17354d1528f902b3a4f66023cd24012e7999c4dc Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Fri, 14 Apr 2023 11:26:42 -0300 Subject: perf test: Simplify for_each_test() to avoid tripping on -Werror=array-bounds When cross building on debian to the mips 32-bit arch we get these warnings: In function '__cmd_test', inlined from 'cmd_test' at tests/builtin-test.c:561:9: tests/builtin-test.c:260:66: error: array subscript 1 is outside array bounds of 'struct test_suite *[1]' [-Werror=array-bounds] 260 | for (k = 0, t = tests[j][k]; tests[j][k]; k++, t = tests[j][k]) | ^ tests/builtin-test.c:369:9: note: in expansion of macro 'for_each_test' 369 | for_each_test(j, k, t) { | ^~~~~~~~~~~~~ tests/builtin-test.c: In function 'cmd_test': tests/builtin-test.c:36:27: note: at offset 4 into object 'arch_tests' of size 4 36 | struct test_suite *__weak arch_tests[] = { | ^~~~~~~~~~ cc1: all warnings being treated as errors Switch to using a while(!sentinel) for the second level of the 'tests' array to avoid that compiler complaint. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/builtin-test.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/tests/builtin-test.c b/tools/perf/tests/builtin-test.c index 35cc3807cc9e..b89d69afcef0 100644 --- a/tools/perf/tests/builtin-test.c +++ b/tools/perf/tests/builtin-test.c @@ -256,8 +256,8 @@ static int run_test(struct test_suite *test, int subtest) } #define for_each_test(j, k, t) \ - for (j = 0; j < ARRAY_SIZE(tests); j++) \ - for (k = 0, t = tests[j][k]; tests[j][k]; k++, t = tests[j][k]) + for (j = 0, k = 0; j < ARRAY_SIZE(tests); j++, k = 0) \ + while ((t = tests[j][k++]) != NULL) static int test_and_print(struct test_suite *t, int subtest) { -- cgit v1.2.3-58-ga151 From 4121234a32887a49d5da06e4c219f67abb6e744f Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Mon, 17 Apr 2023 12:47:49 -0300 Subject: libperf: Add perf_cpu_map__refcnt() interanl accessor to use in the maps test To remove one more direct access to 'struct perf_cpu_map' so that we can intercept accesses to its instantiations and refcount check it to catch use after free, etc. Cc: Adrian Hunter Cc: Alexey Bayduraev Cc: Dmitriy Vyukov Cc: Ian Rogers Cc: Jiri Olsa Cc: Namhyung Kim Cc: Riccardo Mancini Cc: Stephane Eranian Cc: Stephen Brennan Link: https://lore.kernel.org/lkml/ZD1qdYjG+DL6KOfP@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/lib/perf/cpumap.c | 6 +++--- tools/lib/perf/include/internal/cpumap.h | 4 ++++ tools/perf/tests/cpumap.c | 4 ++-- 3 files changed, 9 insertions(+), 5 deletions(-) (limited to 'tools') diff --git a/tools/lib/perf/cpumap.c b/tools/lib/perf/cpumap.c index 6bbcbb83eb14..27c3e73c6db2 100644 --- a/tools/lib/perf/cpumap.c +++ b/tools/lib/perf/cpumap.c @@ -40,7 +40,7 @@ struct perf_cpu_map *perf_cpu_map__dummy_new(void) static void cpu_map__delete(struct perf_cpu_map *map) { if (map) { - WARN_ONCE(refcount_read(&map->refcnt) != 0, + WARN_ONCE(refcount_read(perf_cpu_map__refcnt(map)) != 0, "cpu_map refcnt unbalanced\n"); free(map); } @@ -49,13 +49,13 @@ static void cpu_map__delete(struct perf_cpu_map *map) struct perf_cpu_map *perf_cpu_map__get(struct perf_cpu_map *map) { if (map) - refcount_inc(&map->refcnt); + refcount_inc(perf_cpu_map__refcnt(map)); return map; } void perf_cpu_map__put(struct perf_cpu_map *map) { - if (map && refcount_dec_and_test(&map->refcnt)) + if (map && refcount_dec_and_test(perf_cpu_map__refcnt(map))) cpu_map__delete(map); } diff --git a/tools/lib/perf/include/internal/cpumap.h b/tools/lib/perf/include/internal/cpumap.h index b82fd6607a00..1e840dd53a11 100644 --- a/tools/lib/perf/include/internal/cpumap.h +++ b/tools/lib/perf/include/internal/cpumap.h @@ -30,4 +30,8 @@ bool perf_cpu_map__is_subset(const struct perf_cpu_map *a, const struct perf_cpu void perf_cpu_map__set_nr(struct perf_cpu_map *map, int nr_cpus); +static inline refcount_t *perf_cpu_map__refcnt(struct perf_cpu_map *map) +{ + return &map->refcnt; +} #endif /* __LIBPERF_INTERNAL_CPUMAP_H */ diff --git a/tools/perf/tests/cpumap.c b/tools/perf/tests/cpumap.c index 3150fc1fed6f..b1a924314e09 100644 --- a/tools/perf/tests/cpumap.c +++ b/tools/perf/tests/cpumap.c @@ -68,7 +68,7 @@ static int process_event_cpus(struct perf_tool *tool __maybe_unused, TEST_ASSERT_VAL("wrong nr", perf_cpu_map__nr(map) == 2); TEST_ASSERT_VAL("wrong cpu", perf_cpu_map__cpu(map, 0).cpu == 1); TEST_ASSERT_VAL("wrong cpu", perf_cpu_map__cpu(map, 1).cpu == 256); - TEST_ASSERT_VAL("wrong refcnt", refcount_read(&map->refcnt) == 1); + TEST_ASSERT_VAL("wrong refcnt", refcount_read(perf_cpu_map__refcnt(map)) == 1); perf_cpu_map__put(map); return 0; } @@ -94,7 +94,7 @@ static int process_event_range_cpus(struct perf_tool *tool __maybe_unused, TEST_ASSERT_VAL("wrong nr", perf_cpu_map__nr(map) == 256); TEST_ASSERT_VAL("wrong cpu", perf_cpu_map__cpu(map, 0).cpu == 1); TEST_ASSERT_VAL("wrong cpu", perf_cpu_map__max(map).cpu == 256); - TEST_ASSERT_VAL("wrong refcnt", refcount_read(&map->refcnt) == 1); + TEST_ASSERT_VAL("wrong refcnt", refcount_read(perf_cpu_map__refcnt(map)) == 1); perf_cpu_map__put(map); return 0; } -- cgit v1.2.3-58-ga151 From a9b867f68e89a54fcac334b77e6d243e872573c9 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 7 Apr 2023 16:04:01 -0700 Subject: libperf: Add reference count checking macros The macros serve as a way to debug use of a reference counted struct. The macros add a memory allocated pointer that is interposed between the reference counted original struct at a get and freed by a put. The pointer replaces the original struct, so use of the struct name via APIs remains unchanged. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexey Bayduraev Cc: Andi Kleen Cc: Andrew Morton Cc: Andy Shevchenko Cc: Darren Hart Cc: Davidlohr Bueso Cc: Dmitriy Vyukov Cc: Eric Dumazet Cc: German Gomez Cc: Hao Luo Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Madhavan Srinivasan Cc: Mark Rutland Cc: Masami Hiramatsu Cc: Miaoqian Lin Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Riccardo Mancini Cc: Shunsuke Nakamura Cc: Song Liu Cc: Stephane Eranian Cc: Stephen Brennan Cc: Steven Rostedt (VMware) Cc: Thomas Gleixner Cc: Thomas Richter Cc: Yury Norov Link: http://lore.kernel.org/lkml/20230407230405.2931830-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/lib/perf/include/internal/rc_check.h | 94 ++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 tools/lib/perf/include/internal/rc_check.h (limited to 'tools') diff --git a/tools/lib/perf/include/internal/rc_check.h b/tools/lib/perf/include/internal/rc_check.h new file mode 100644 index 000000000000..c0626d8beb59 --- /dev/null +++ b/tools/lib/perf/include/internal/rc_check.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause) */ +#ifndef __LIBPERF_INTERNAL_RC_CHECK_H +#define __LIBPERF_INTERNAL_RC_CHECK_H + +#include +#include + +/* + * Shared reference count checking macros. + * + * Reference count checking is an approach to sanitizing the use of reference + * counted structs. It leverages address and leak sanitizers to make sure gets + * are paired with a put. Reference count checking adds a malloc-ed layer of + * indirection on a get, and frees it on a put. A missed put will be reported as + * a memory leak. A double put will be reported as a double free. Accessing + * after a put will cause a use-after-free and/or a segfault. + */ + +#ifndef REFCNT_CHECKING +/* Replaces "struct foo" so that the pointer may be interposed. */ +#define DECLARE_RC_STRUCT(struct_name) \ + struct struct_name + +/* Declare a reference counted struct variable. */ +#define RC_STRUCT(struct_name) struct struct_name + +/* + * Interpose the indirection. Result will hold the indirection and object is the + * reference counted struct. + */ +#define ADD_RC_CHK(result, object) (result = object, object) + +/* Strip the indirection layer. */ +#define RC_CHK_ACCESS(object) object + +/* Frees the object and the indirection layer. */ +#define RC_CHK_FREE(object) free(object) + +/* A get operation adding the indirection layer. */ +#define RC_CHK_GET(result, object) ADD_RC_CHK(result, object) + +/* A put operation removing the indirection layer. */ +#define RC_CHK_PUT(object) {} + +#else + +/* Replaces "struct foo" so that the pointer may be interposed. */ +#define DECLARE_RC_STRUCT(struct_name) \ + struct original_##struct_name; \ + struct struct_name { \ + struct original_##struct_name *orig; \ + }; \ + struct original_##struct_name + +/* Declare a reference counted struct variable. */ +#define RC_STRUCT(struct_name) struct original_##struct_name + +/* + * Interpose the indirection. Result will hold the indirection and object is the + * reference counted struct. + */ +#define ADD_RC_CHK(result, object) \ + ( \ + object ? (result = malloc(sizeof(*result)), \ + result ? (result->orig = object, result) \ + : (result = NULL, NULL)) \ + : (result = NULL, NULL) \ + ) + +/* Strip the indirection layer. */ +#define RC_CHK_ACCESS(object) object->orig + +/* Frees the object and the indirection layer. */ +#define RC_CHK_FREE(object) \ + do { \ + zfree(&object->orig); \ + free(object); \ + } while(0) + +/* A get operation adding the indirection layer. */ +#define RC_CHK_GET(result, object) ADD_RC_CHK(result, (object ? object->orig : NULL)) + +/* A put operation removing the indirection layer. */ +#define RC_CHK_PUT(object) \ + do { \ + if (object) { \ + object->orig = NULL; \ + free(object); \ + } \ + } while(0) + +#endif + +#endif /* __LIBPERF_INTERNAL_RC_CHECK_H */ -- cgit v1.2.3-58-ga151 From d57fd4926ab81ad5749c6950047ea40863a52e18 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Mon, 17 Apr 2023 16:19:38 -0300 Subject: perf cpumap: Remove initializations done in perf_cpu_map__alloc() When extracting this patch from Ian's original patch I forgot to remove the setting of ->nr and ->refcnt, no need to do those initializations again as those are done in perf_cpu_map__alloc() already, duh. Cc: Ian Rogers Fixes: 1f94479edb4decdc ("libperf: Make perf_cpu_map__alloc() available as an internal function for tools/perf to use") Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/cpumap.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/cpumap.c b/tools/perf/util/cpumap.c index 072831f0cad4..7008705d745c 100644 --- a/tools/perf/util/cpumap.c +++ b/tools/perf/util/cpumap.c @@ -163,13 +163,8 @@ struct perf_cpu_map *perf_cpu_map__empty_new(int nr) struct perf_cpu_map *cpus = perf_cpu_map__alloc(nr); if (cpus != NULL) { - int i; - - cpus->nr = nr; - for (i = 0; i < nr; i++) + for (int i = 0; i < nr; i++) cpus->map[i].cpu = -1; - - refcount_set(&cpus->refcnt, 1); } return cpus; -- cgit v1.2.3-58-ga151 From 491b13c46d4165eacc294b880f388e00ed85e5aa Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 17 Apr 2023 16:28:28 -0300 Subject: perf cpumap: Use perf_cpu_map__cpu(map, cpu) instead of accessing map->map[cpu] directly So that we can validate the 'map' instance wrt refcount checking. Cc: Adrian Hunter Cc: Alexey Bayduraev Cc: Dmitriy Vyukov Cc: Ian Rogers Cc: Jiri Olsa Cc: Namhyung Kim Cc: Riccardo Mancini Cc: Stephane Eranian Cc: Stephen Brennan Link: https://lore.kernel.org/lkml/20230407230405.2931830-3-irogers@google.com [ Extracted from a larger patch ] Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/cpumap.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/cpumap.c b/tools/perf/util/cpumap.c index 7008705d745c..240557de129e 100644 --- a/tools/perf/util/cpumap.c +++ b/tools/perf/util/cpumap.c @@ -582,26 +582,26 @@ size_t cpu_map__snprint(struct perf_cpu_map *map, char *buf, size_t size) bool last = i == perf_cpu_map__nr(map); if (!last) - cpu = map->map[i]; + cpu = perf_cpu_map__cpu(map, i); if (start == -1) { start = i; if (last) { ret += snprintf(buf + ret, size - ret, "%s%d", COMMA, - map->map[i].cpu); + perf_cpu_map__cpu(map, i).cpu); } - } else if (((i - start) != (cpu.cpu - map->map[start].cpu)) || last) { + } else if (((i - start) != (cpu.cpu - perf_cpu_map__cpu(map, start).cpu)) || last) { int end = i - 1; if (start == end) { ret += snprintf(buf + ret, size - ret, "%s%d", COMMA, - map->map[start].cpu); + perf_cpu_map__cpu(map, start).cpu); } else { ret += snprintf(buf + ret, size - ret, "%s%d-%d", COMMA, - map->map[start].cpu, map->map[end].cpu); + perf_cpu_map__cpu(map, start).cpu, perf_cpu_map__cpu(map, end).cpu); } first = false; start = i; -- cgit v1.2.3-58-ga151 From da885a0e5e0610e011f14a70c2dc7c4ddf79c6d6 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 17 Apr 2023 16:50:02 -0300 Subject: perf cpumap: Add reference count checking Enabled when REFCNT_CHECKING is defined. The change adds a memory allocated pointer that is interposed between the reference counted cpu map at a get and freed by a put. The pointer replaces the original perf_cpu_map struct, so use of the perf_cpu_map via APIs remains unchanged. Any use of the cpu map without the API requires two versions, handled via the RC_CHK_ACCESS macro. This change is intended to catch: - use after put: using a cpumap after you have put it will cause a segv. - unbalanced puts: two puts for a get will result in a double free that can be captured and reported by tools like address sanitizer, including with the associated stack traces of allocation and frees. - missing puts: if a put is missing then the get turns into a memory leak that can be reported by leak sanitizer, including the stack trace at the point the get occurs. Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Alexey Bayduraev Cc: Andi Kleen Cc: Andrew Morton Cc: Andy Shevchenko Cc: Darren Hart Cc: Davidlohr Bueso Cc: Dmitriy Vyukov Cc: Eric Dumazet Cc: German Gomez Cc: Hao Luo Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kan Liang Cc: Leo Yan Cc: Madhavan Srinivasan Cc: Mark Rutland Cc: Masami Hiramatsu Cc: Miaoqian Lin Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Riccardo Mancini Cc: Shunsuke Nakamura Cc: Song Liu Cc: Stephen Brennan Cc: Steven Rostedt (VMware) Cc: Thomas Gleixner Cc: Thomas Richter , Cc: Yury Norov Link: https://lore.kernel.org/lkml/20230407230405.2931830-3-irogers@google.com [ Extracted from a larger patch ] Signed-off-by: Arnaldo Carvalho de Melo --- tools/lib/perf/Makefile | 2 +- tools/lib/perf/cpumap.c | 85 +++++++++++++++++--------------- tools/lib/perf/include/internal/cpumap.h | 5 +- tools/perf/util/cpumap.c | 12 ++--- tools/perf/util/pmu.c | 4 +- 5 files changed, 58 insertions(+), 50 deletions(-) (limited to 'tools') diff --git a/tools/lib/perf/Makefile b/tools/lib/perf/Makefile index d8cad124e4c5..3a9b2140aa04 100644 --- a/tools/lib/perf/Makefile +++ b/tools/lib/perf/Makefile @@ -188,7 +188,7 @@ install_lib: libs cp -fpR $(LIBPERF_ALL) $(DESTDIR)$(libdir_SQ) HDRS := bpf_perf.h core.h cpumap.h threadmap.h evlist.h evsel.h event.h mmap.h -INTERNAL_HDRS := cpumap.h evlist.h evsel.h lib.h mmap.h threadmap.h xyarray.h +INTERNAL_HDRS := cpumap.h evlist.h evsel.h lib.h mmap.h rc_check.h threadmap.h xyarray.h INSTALL_HDRS_PFX := $(DESTDIR)$(prefix)/include/perf INSTALL_HDRS := $(addprefix $(INSTALL_HDRS_PFX)/, $(HDRS)) diff --git a/tools/lib/perf/cpumap.c b/tools/lib/perf/cpumap.c index 27c3e73c6db2..1229b18bcdb1 100644 --- a/tools/lib/perf/cpumap.c +++ b/tools/lib/perf/cpumap.c @@ -12,19 +12,19 @@ void perf_cpu_map__set_nr(struct perf_cpu_map *map, int nr_cpus) { - map->nr = nr_cpus; + RC_CHK_ACCESS(map)->nr = nr_cpus; } struct perf_cpu_map *perf_cpu_map__alloc(int nr_cpus) { - struct perf_cpu_map *cpus = malloc(sizeof(*cpus) + sizeof(struct perf_cpu) * nr_cpus); + RC_STRUCT(perf_cpu_map) *cpus = malloc(sizeof(*cpus) + sizeof(struct perf_cpu) * nr_cpus); + struct perf_cpu_map *result; - if (cpus != NULL) { + if (ADD_RC_CHK(result, cpus)) { cpus->nr = nr_cpus; refcount_set(&cpus->refcnt, 1); - } - return cpus; + return result; } struct perf_cpu_map *perf_cpu_map__dummy_new(void) @@ -32,7 +32,7 @@ struct perf_cpu_map *perf_cpu_map__dummy_new(void) struct perf_cpu_map *cpus = perf_cpu_map__alloc(1); if (cpus) - cpus->map[0].cpu = -1; + RC_CHK_ACCESS(cpus)->map[0].cpu = -1; return cpus; } @@ -42,21 +42,28 @@ static void cpu_map__delete(struct perf_cpu_map *map) if (map) { WARN_ONCE(refcount_read(perf_cpu_map__refcnt(map)) != 0, "cpu_map refcnt unbalanced\n"); - free(map); + RC_CHK_FREE(map); } } struct perf_cpu_map *perf_cpu_map__get(struct perf_cpu_map *map) { - if (map) + struct perf_cpu_map *result; + + if (RC_CHK_GET(result, map)) refcount_inc(perf_cpu_map__refcnt(map)); - return map; + + return result; } void perf_cpu_map__put(struct perf_cpu_map *map) { - if (map && refcount_dec_and_test(perf_cpu_map__refcnt(map))) - cpu_map__delete(map); + if (map) { + if (refcount_dec_and_test(perf_cpu_map__refcnt(map))) + cpu_map__delete(map); + else + RC_CHK_PUT(map); + } } static struct perf_cpu_map *cpu_map__default_new(void) @@ -73,7 +80,7 @@ static struct perf_cpu_map *cpu_map__default_new(void) int i; for (i = 0; i < nr_cpus; ++i) - cpus->map[i].cpu = i; + RC_CHK_ACCESS(cpus)->map[i].cpu = i; } return cpus; @@ -99,15 +106,15 @@ static struct perf_cpu_map *cpu_map__trim_new(int nr_cpus, const struct perf_cpu int i, j; if (cpus != NULL) { - memcpy(cpus->map, tmp_cpus, payload_size); - qsort(cpus->map, nr_cpus, sizeof(struct perf_cpu), cmp_cpu); + memcpy(RC_CHK_ACCESS(cpus)->map, tmp_cpus, payload_size); + qsort(RC_CHK_ACCESS(cpus)->map, nr_cpus, sizeof(struct perf_cpu), cmp_cpu); /* Remove dups */ j = 0; for (i = 0; i < nr_cpus; i++) { - if (i == 0 || cpus->map[i].cpu != cpus->map[i - 1].cpu) - cpus->map[j++].cpu = cpus->map[i].cpu; + if (i == 0 || RC_CHK_ACCESS(cpus)->map[i].cpu != RC_CHK_ACCESS(cpus)->map[i - 1].cpu) + RC_CHK_ACCESS(cpus)->map[j++].cpu = RC_CHK_ACCESS(cpus)->map[i].cpu; } - cpus->nr = j; + perf_cpu_map__set_nr(cpus, j); assert(j <= nr_cpus); } return cpus; @@ -268,20 +275,20 @@ struct perf_cpu perf_cpu_map__cpu(const struct perf_cpu_map *cpus, int idx) .cpu = -1 }; - if (cpus && idx < cpus->nr) - return cpus->map[idx]; + if (cpus && idx < RC_CHK_ACCESS(cpus)->nr) + return RC_CHK_ACCESS(cpus)->map[idx]; return result; } int perf_cpu_map__nr(const struct perf_cpu_map *cpus) { - return cpus ? cpus->nr : 1; + return cpus ? RC_CHK_ACCESS(cpus)->nr : 1; } bool perf_cpu_map__empty(const struct perf_cpu_map *map) { - return map ? map->map[0].cpu == -1 : true; + return map ? RC_CHK_ACCESS(map)->map[0].cpu == -1 : true; } int perf_cpu_map__idx(const struct perf_cpu_map *cpus, struct perf_cpu cpu) @@ -292,10 +299,10 @@ int perf_cpu_map__idx(const struct perf_cpu_map *cpus, struct perf_cpu cpu) return -1; low = 0; - high = cpus->nr; + high = RC_CHK_ACCESS(cpus)->nr; while (low < high) { int idx = (low + high) / 2; - struct perf_cpu cpu_at_idx = cpus->map[idx]; + struct perf_cpu cpu_at_idx = RC_CHK_ACCESS(cpus)->map[idx]; if (cpu_at_idx.cpu == cpu.cpu) return idx; @@ -321,7 +328,7 @@ struct perf_cpu perf_cpu_map__max(const struct perf_cpu_map *map) }; // cpu_map__trim_new() qsort()s it, cpu_map__default_new() sorts it as well. - return map->nr > 0 ? map->map[map->nr - 1] : result; + return RC_CHK_ACCESS(map)->nr > 0 ? RC_CHK_ACCESS(map)->map[RC_CHK_ACCESS(map)->nr - 1] : result; } /** Is 'b' a subset of 'a'. */ @@ -329,15 +336,15 @@ bool perf_cpu_map__is_subset(const struct perf_cpu_map *a, const struct perf_cpu { if (a == b || !b) return true; - if (!a || b->nr > a->nr) + if (!a || RC_CHK_ACCESS(b)->nr > RC_CHK_ACCESS(a)->nr) return false; - for (int i = 0, j = 0; i < a->nr; i++) { - if (a->map[i].cpu > b->map[j].cpu) + for (int i = 0, j = 0; i < RC_CHK_ACCESS(a)->nr; i++) { + if (RC_CHK_ACCESS(a)->map[i].cpu > RC_CHK_ACCESS(b)->map[j].cpu) return false; - if (a->map[i].cpu == b->map[j].cpu) { + if (RC_CHK_ACCESS(a)->map[i].cpu == RC_CHK_ACCESS(b)->map[j].cpu) { j++; - if (j == b->nr) + if (j == RC_CHK_ACCESS(b)->nr) return true; } } @@ -367,27 +374,27 @@ struct perf_cpu_map *perf_cpu_map__merge(struct perf_cpu_map *orig, return perf_cpu_map__get(other); } - tmp_len = orig->nr + other->nr; + tmp_len = RC_CHK_ACCESS(orig)->nr + RC_CHK_ACCESS(other)->nr; tmp_cpus = malloc(tmp_len * sizeof(struct perf_cpu)); if (!tmp_cpus) return NULL; /* Standard merge algorithm from wikipedia */ i = j = k = 0; - while (i < orig->nr && j < other->nr) { - if (orig->map[i].cpu <= other->map[j].cpu) { - if (orig->map[i].cpu == other->map[j].cpu) + while (i < RC_CHK_ACCESS(orig)->nr && j < RC_CHK_ACCESS(other)->nr) { + if (RC_CHK_ACCESS(orig)->map[i].cpu <= RC_CHK_ACCESS(other)->map[j].cpu) { + if (RC_CHK_ACCESS(orig)->map[i].cpu == RC_CHK_ACCESS(other)->map[j].cpu) j++; - tmp_cpus[k++] = orig->map[i++]; + tmp_cpus[k++] = RC_CHK_ACCESS(orig)->map[i++]; } else - tmp_cpus[k++] = other->map[j++]; + tmp_cpus[k++] = RC_CHK_ACCESS(other)->map[j++]; } - while (i < orig->nr) - tmp_cpus[k++] = orig->map[i++]; + while (i < RC_CHK_ACCESS(orig)->nr) + tmp_cpus[k++] = RC_CHK_ACCESS(orig)->map[i++]; - while (j < other->nr) - tmp_cpus[k++] = other->map[j++]; + while (j < RC_CHK_ACCESS(other)->nr) + tmp_cpus[k++] = RC_CHK_ACCESS(other)->map[j++]; assert(k <= tmp_len); merged = cpu_map__trim_new(k, tmp_cpus); diff --git a/tools/lib/perf/include/internal/cpumap.h b/tools/lib/perf/include/internal/cpumap.h index 1e840dd53a11..49649eb51ce4 100644 --- a/tools/lib/perf/include/internal/cpumap.h +++ b/tools/lib/perf/include/internal/cpumap.h @@ -4,6 +4,7 @@ #include #include +#include /** * A sized, reference counted, sorted array of integers representing CPU @@ -12,7 +13,7 @@ * gaps if CPU numbers were used. For events associated with a pid, rather than * a CPU, a single dummy map with an entry of -1 is used. */ -struct perf_cpu_map { +DECLARE_RC_STRUCT(perf_cpu_map) { refcount_t refcnt; /** Length of the map array. */ int nr; @@ -32,6 +33,6 @@ void perf_cpu_map__set_nr(struct perf_cpu_map *map, int nr_cpus); static inline refcount_t *perf_cpu_map__refcnt(struct perf_cpu_map *map) { - return &map->refcnt; + return &RC_CHK_ACCESS(map)->refcnt; } #endif /* __LIBPERF_INTERNAL_CPUMAP_H */ diff --git a/tools/perf/util/cpumap.c b/tools/perf/util/cpumap.c index 240557de129e..75d9c73e0184 100644 --- a/tools/perf/util/cpumap.c +++ b/tools/perf/util/cpumap.c @@ -77,9 +77,9 @@ static struct perf_cpu_map *cpu_map__from_entries(const struct perf_record_cpu_m * otherwise it would become 65535. */ if (data->cpus_data.cpu[i] == (u16) -1) - map->map[i].cpu = -1; + RC_CHK_ACCESS(map)->map[i].cpu = -1; else - map->map[i].cpu = (int) data->cpus_data.cpu[i]; + RC_CHK_ACCESS(map)->map[i].cpu = (int) data->cpus_data.cpu[i]; } } @@ -107,7 +107,7 @@ static struct perf_cpu_map *cpu_map__from_mask(const struct perf_record_cpu_map_ perf_record_cpu_map_data__read_one_mask(data, i, local_copy); for_each_set_bit(cpu, local_copy, 64) - map->map[j++].cpu = cpu + cpus_per_i; + RC_CHK_ACCESS(map)->map[j++].cpu = cpu + cpus_per_i; } return map; @@ -124,11 +124,11 @@ static struct perf_cpu_map *cpu_map__from_range(const struct perf_record_cpu_map return NULL; if (data->range_cpu_data.any_cpu) - map->map[i++].cpu = -1; + RC_CHK_ACCESS(map)->map[i++].cpu = -1; for (int cpu = data->range_cpu_data.start_cpu; cpu <= data->range_cpu_data.end_cpu; i++, cpu++) - map->map[i].cpu = cpu; + RC_CHK_ACCESS(map)->map[i].cpu = cpu; return map; } @@ -164,7 +164,7 @@ struct perf_cpu_map *perf_cpu_map__empty_new(int nr) if (cpus != NULL) { for (int i = 0; i < nr; i++) - cpus->map[i].cpu = -1; + RC_CHK_ACCESS(cpus)->map[i].cpu = -1; } return cpus; diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 760c848c9fa2..65d0eb9a740a 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -2015,9 +2015,9 @@ int perf_pmu__cpus_match(struct perf_pmu *pmu, struct perf_cpu_map *cpus, perf_cpu_map__for_each_cpu(cpu, i, cpus) { if (!perf_cpu_map__has(pmu_cpus, cpu)) - unmatched_cpus->map[unmatched_nr++] = cpu; + RC_CHK_ACCESS(unmatched_cpus)->map[unmatched_nr++] = cpu; else - matched_cpus->map[matched_nr++] = cpu; + RC_CHK_ACCESS(matched_cpus)->map[matched_nr++] = cpu; } perf_cpu_map__set_nr(unmatched_cpus, unmatched_nr); -- cgit v1.2.3-58-ga151 From 7031edac9dbc0f880c9fbaa40ca08b5de34239c6 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Mon, 17 Apr 2023 18:28:01 -0300 Subject: perf dso: Add dso__filename_with_chroot() to reduce number of accesses to dso->nsinfo members We'll need to reference count dso->nsinfo, so reduce the number of direct accesses by having a shorter form of obtaining a filename with a chroot (namespace one). Cc: Adrian Hunter Cc: Alexey Bayduraev Cc: Dmitriy Vyukov Cc: Ian Rogers Cc: Jiri Olsa Cc: Namhyung Kim Cc: Riccardo Mancini Cc: Stephane Eranian Cc: Stephen Brennan Link: https://lore.kernel.org/lkml/ZD26ZlqSbgSyH5lX@kernel.org [ Used nsinfo__pid(dso->nsinfo), as it was already present ] Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-inject.c | 4 +--- tools/perf/util/annotate.c | 3 +-- tools/perf/util/dso.c | 7 ++++++- tools/perf/util/dso.h | 2 ++ tools/perf/util/dsos.c | 3 +-- tools/perf/util/symbol.c | 3 +-- 6 files changed, 12 insertions(+), 10 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-inject.c b/tools/perf/builtin-inject.c index 76723ac314b6..61766eead4f4 100644 --- a/tools/perf/builtin-inject.c +++ b/tools/perf/builtin-inject.c @@ -630,10 +630,8 @@ static int dso__read_build_id(struct dso *dso) if (filename__read_build_id(dso->long_name, &dso->bid) > 0) dso->has_build_id = true; else if (dso->nsinfo) { - char *new_name; + char *new_name = dso__filename_with_chroot(dso, dso->long_name); - new_name = filename_with_chroot(dso->nsinfo->pid, - dso->long_name); if (new_name && filename__read_build_id(new_name, &dso->bid) > 0) dso->has_build_id = true; free(new_name); diff --git a/tools/perf/util/annotate.c b/tools/perf/util/annotate.c index e2693a1c28d5..ca9f0add68f4 100644 --- a/tools/perf/util/annotate.c +++ b/tools/perf/util/annotate.c @@ -1692,8 +1692,7 @@ fallback: mutex_lock(&dso->lock); if (access(filename, R_OK) && errno == ENOENT && dso->nsinfo) { - char *new_name = filename_with_chroot(dso->nsinfo->pid, - filename); + char *new_name = dso__filename_with_chroot(dso, filename); if (new_name) { strlcpy(filename, new_name, filename_size); free(new_name); diff --git a/tools/perf/util/dso.c b/tools/perf/util/dso.c index e36b418df2c6..a86614599269 100644 --- a/tools/perf/util/dso.c +++ b/tools/perf/util/dso.c @@ -491,6 +491,11 @@ static int do_open(char *name) return -1; } +char *dso__filename_with_chroot(const struct dso *dso, const char *filename) +{ + return filename_with_chroot(nsinfo__pid(dso->nsinfo), filename); +} + static int __open_dso(struct dso *dso, struct machine *machine) { int fd = -EINVAL; @@ -515,7 +520,7 @@ static int __open_dso(struct dso *dso, struct machine *machine) if (errno != ENOENT || dso->nsinfo == NULL) goto out; - new_name = filename_with_chroot(dso->nsinfo->pid, name); + new_name = dso__filename_with_chroot(dso, name); if (!new_name) goto out; diff --git a/tools/perf/util/dso.h b/tools/perf/util/dso.h index 58d94175e714..0b7c7633b9f6 100644 --- a/tools/perf/util/dso.h +++ b/tools/perf/util/dso.h @@ -266,6 +266,8 @@ static inline bool dso__has_symbols(const struct dso *dso) return !RB_EMPTY_ROOT(&dso->symbols.rb_root); } +char *dso__filename_with_chroot(const struct dso *dso, const char *filename); + bool dso__sorted_by_name(const struct dso *dso); void dso__set_sorted_by_name(struct dso *dso); void dso__sort_by_name(struct dso *dso); diff --git a/tools/perf/util/dsos.c b/tools/perf/util/dsos.c index 2bd23e4cf19e..cf80aa42dd07 100644 --- a/tools/perf/util/dsos.c +++ b/tools/perf/util/dsos.c @@ -91,8 +91,7 @@ bool __dsos__read_build_ids(struct list_head *head, bool with_hits) have_build_id = true; pos->has_build_id = true; } else if (errno == ENOENT && pos->nsinfo) { - char *new_name = filename_with_chroot(pos->nsinfo->pid, - pos->long_name); + char *new_name = dso__filename_with_chroot(pos, pos->long_name); if (new_name && filename__read_build_id(new_name, &pos->bid) > 0) { diff --git a/tools/perf/util/symbol.c b/tools/perf/util/symbol.c index 91ebf93e0c20..e7f63670688e 100644 --- a/tools/perf/util/symbol.c +++ b/tools/perf/util/symbol.c @@ -1963,8 +1963,7 @@ int dso__load(struct dso *dso, struct map *map) is_reg = is_regular_file(name); if (!is_reg && errno == ENOENT && dso->nsinfo) { - char *new_name = filename_with_chroot(dso->nsinfo->pid, - name); + char *new_name = dso__filename_with_chroot(dso, name); if (new_name) { is_reg = is_regular_file(new_name); strlcpy(name, new_name, PATH_MAX); -- cgit v1.2.3-58-ga151 From c35ce1d918c12900375a60165c908de47856900d Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Mon, 17 Apr 2023 18:51:57 -0300 Subject: perf namespaces: Add reference count checking Add reference count checking controlled by REFCNT_CHECKING ifdef. The reference count checking interposes an allocated pointer between the reference counted struct on a get and frees the pointer on a put. Accesses after a put cause faults and use after free, missed puts are caughts as leaks and double puts are double frees. This checking helped resolve a memory leak and use after free: https://lore.kernel.org/linux-perf-users/CAP-5=fWZH20L4kv-BwVtGLwR=Em3AOOT+Q4QGivvQuYn5AsPRg@mail.gmail.com/ Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexey Bayduraev Cc: Dmitriy Vyukov Cc: Jiri Olsa Cc: Namhyung Kim Cc: Riccardo Mancini Cc: Stephane Eranian Cc: Stephen Brennan Link: https://lore.kernel.org/lkml/20230407230405.2931830-4-irogers@google.com [ Extracted from a larger patch ] Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/namespaces.c | 132 +++++++++++++++++++++++++------------------ tools/perf/util/namespaces.h | 3 +- 2 files changed, 78 insertions(+), 57 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/namespaces.c b/tools/perf/util/namespaces.c index dd536220cdb9..8a3b7bd27b19 100644 --- a/tools/perf/util/namespaces.c +++ b/tools/perf/util/namespaces.c @@ -60,7 +60,7 @@ void namespaces__free(struct namespaces *namespaces) free(namespaces); } -static int nsinfo__get_nspid(struct nsinfo *nsi, const char *path) +static int nsinfo__get_nspid(pid_t *tgid, pid_t *nstgid, bool *in_pidns, const char *path) { FILE *f = NULL; char *statln = NULL; @@ -74,19 +74,18 @@ static int nsinfo__get_nspid(struct nsinfo *nsi, const char *path) while (getline(&statln, &linesz, f) != -1) { /* Use tgid if CONFIG_PID_NS is not defined. */ if (strstr(statln, "Tgid:") != NULL) { - nsi->tgid = (pid_t)strtol(strrchr(statln, '\t'), - NULL, 10); - nsi->nstgid = nsinfo__tgid(nsi); + *tgid = (pid_t)strtol(strrchr(statln, '\t'), NULL, 10); + *nstgid = *tgid; } if (strstr(statln, "NStgid:") != NULL) { nspid = strrchr(statln, '\t'); - nsi->nstgid = (pid_t)strtol(nspid, NULL, 10); + *nstgid = (pid_t)strtol(nspid, NULL, 10); /* * If innermost tgid is not the first, process is in a different * PID namespace. */ - nsi->in_pidns = (statln + sizeof("NStgid:") - 1) != nspid; + *in_pidns = (statln + sizeof("NStgid:") - 1) != nspid; break; } } @@ -121,8 +120,8 @@ int nsinfo__init(struct nsinfo *nsi) * want to switch as part of looking up dso/map data. */ if (old_stat.st_ino != new_stat.st_ino) { - nsi->need_setns = true; - nsi->mntns_path = newns; + RC_CHK_ACCESS(nsi)->need_setns = true; + RC_CHK_ACCESS(nsi)->mntns_path = newns; newns = NULL; } @@ -132,13 +131,26 @@ int nsinfo__init(struct nsinfo *nsi) if (snprintf(spath, PATH_MAX, "/proc/%d/status", nsinfo__pid(nsi)) >= PATH_MAX) goto out; - rv = nsinfo__get_nspid(nsi, spath); + rv = nsinfo__get_nspid(&RC_CHK_ACCESS(nsi)->tgid, &RC_CHK_ACCESS(nsi)->nstgid, + &RC_CHK_ACCESS(nsi)->in_pidns, spath); out: free(newns); return rv; } +static struct nsinfo *nsinfo__alloc(void) +{ + struct nsinfo *res; + RC_STRUCT(nsinfo) *nsi; + + nsi = calloc(1, sizeof(*nsi)); + if (ADD_RC_CHK(res, nsi)) + refcount_set(&nsi->refcnt, 1); + + return res; +} + struct nsinfo *nsinfo__new(pid_t pid) { struct nsinfo *nsi; @@ -146,22 +158,21 @@ struct nsinfo *nsinfo__new(pid_t pid) if (pid == 0) return NULL; - nsi = calloc(1, sizeof(*nsi)); - if (nsi != NULL) { - nsi->pid = pid; - nsi->tgid = pid; - nsi->nstgid = pid; - nsi->need_setns = false; - nsi->in_pidns = false; - /* Init may fail if the process exits while we're trying to look - * at its proc information. In that case, save the pid but - * don't try to enter the namespace. - */ - if (nsinfo__init(nsi) == -1) - nsi->need_setns = false; + nsi = nsinfo__alloc(); + if (!nsi) + return NULL; - refcount_set(&nsi->refcnt, 1); - } + RC_CHK_ACCESS(nsi)->pid = pid; + RC_CHK_ACCESS(nsi)->tgid = pid; + RC_CHK_ACCESS(nsi)->nstgid = pid; + RC_CHK_ACCESS(nsi)->need_setns = false; + RC_CHK_ACCESS(nsi)->in_pidns = false; + /* Init may fail if the process exits while we're trying to look at its + * proc information. In that case, save the pid but don't try to enter + * the namespace. + */ + if (nsinfo__init(nsi) == -1) + RC_CHK_ACCESS(nsi)->need_setns = false; return nsi; } @@ -173,21 +184,21 @@ struct nsinfo *nsinfo__copy(const struct nsinfo *nsi) if (nsi == NULL) return NULL; - nnsi = calloc(1, sizeof(*nnsi)); - if (nnsi != NULL) { - nnsi->pid = nsinfo__pid(nsi); - nnsi->tgid = nsinfo__tgid(nsi); - nnsi->nstgid = nsinfo__nstgid(nsi); - nnsi->need_setns = nsinfo__need_setns(nsi); - nnsi->in_pidns = nsinfo__in_pidns(nsi); - if (nsi->mntns_path) { - nnsi->mntns_path = strdup(nsi->mntns_path); - if (!nnsi->mntns_path) { - free(nnsi); - return NULL; - } + nnsi = nsinfo__alloc(); + if (!nnsi) + return NULL; + + RC_CHK_ACCESS(nnsi)->pid = nsinfo__pid(nsi); + RC_CHK_ACCESS(nnsi)->tgid = nsinfo__tgid(nsi); + RC_CHK_ACCESS(nnsi)->nstgid = nsinfo__nstgid(nsi); + RC_CHK_ACCESS(nnsi)->need_setns = nsinfo__need_setns(nsi); + RC_CHK_ACCESS(nnsi)->in_pidns = nsinfo__in_pidns(nsi); + if (RC_CHK_ACCESS(nsi)->mntns_path) { + RC_CHK_ACCESS(nnsi)->mntns_path = strdup(RC_CHK_ACCESS(nsi)->mntns_path); + if (!RC_CHK_ACCESS(nnsi)->mntns_path) { + nsinfo__put(nnsi); + return NULL; } - refcount_set(&nnsi->refcnt, 1); } return nnsi; @@ -195,51 +206,60 @@ struct nsinfo *nsinfo__copy(const struct nsinfo *nsi) static void nsinfo__delete(struct nsinfo *nsi) { - zfree(&nsi->mntns_path); - free(nsi); + if (nsi) { + WARN_ONCE(refcount_read(&RC_CHK_ACCESS(nsi)->refcnt) != 0, + "nsinfo refcnt unbalanced\n"); + zfree(&RC_CHK_ACCESS(nsi)->mntns_path); + RC_CHK_FREE(nsi); + } } struct nsinfo *nsinfo__get(struct nsinfo *nsi) { - if (nsi) - refcount_inc(&nsi->refcnt); - return nsi; + struct nsinfo *result; + + if (RC_CHK_GET(result, nsi)) + refcount_inc(&RC_CHK_ACCESS(nsi)->refcnt); + + return result; } void nsinfo__put(struct nsinfo *nsi) { - if (nsi && refcount_dec_and_test(&nsi->refcnt)) + if (nsi && refcount_dec_and_test(&RC_CHK_ACCESS(nsi)->refcnt)) nsinfo__delete(nsi); + else + RC_CHK_PUT(nsi); } bool nsinfo__need_setns(const struct nsinfo *nsi) { - return nsi->need_setns; + return RC_CHK_ACCESS(nsi)->need_setns; } void nsinfo__clear_need_setns(struct nsinfo *nsi) { - nsi->need_setns = false; + RC_CHK_ACCESS(nsi)->need_setns = false; } pid_t nsinfo__tgid(const struct nsinfo *nsi) { - return nsi->tgid; + return RC_CHK_ACCESS(nsi)->tgid; } pid_t nsinfo__nstgid(const struct nsinfo *nsi) { - return nsi->nstgid; + return RC_CHK_ACCESS(nsi)->nstgid; } pid_t nsinfo__pid(const struct nsinfo *nsi) { - return nsi->pid; + return RC_CHK_ACCESS(nsi)->pid; } pid_t nsinfo__in_pidns(const struct nsinfo *nsi) { - return nsi->in_pidns; + return RC_CHK_ACCESS(nsi)->in_pidns; } void nsinfo__mountns_enter(struct nsinfo *nsi, @@ -256,7 +276,7 @@ void nsinfo__mountns_enter(struct nsinfo *nsi, nc->oldns = -1; nc->newns = -1; - if (!nsi || !nsi->need_setns) + if (!nsi || !RC_CHK_ACCESS(nsi)->need_setns) return; if (snprintf(curpath, PATH_MAX, "/proc/self/ns/mnt") >= PATH_MAX) @@ -270,7 +290,7 @@ void nsinfo__mountns_enter(struct nsinfo *nsi, if (oldns < 0) goto errout; - newns = open(nsi->mntns_path, O_RDONLY); + newns = open(RC_CHK_ACCESS(nsi)->mntns_path, O_RDONLY); if (newns < 0) goto errout; @@ -339,9 +359,9 @@ int nsinfo__stat(const char *filename, struct stat *st, struct nsinfo *nsi) bool nsinfo__is_in_root_namespace(void) { - struct nsinfo nsi; + pid_t tgid = 0, nstgid = 0; + bool in_pidns = false; - memset(&nsi, 0x0, sizeof(nsi)); - nsinfo__get_nspid(&nsi, "/proc/self/status"); - return !nsi.in_pidns; + nsinfo__get_nspid(&tgid, &nstgid, &in_pidns, "/proc/self/status"); + return !in_pidns; } diff --git a/tools/perf/util/namespaces.h b/tools/perf/util/namespaces.h index 567829262c42..8c0731c6cbb7 100644 --- a/tools/perf/util/namespaces.h +++ b/tools/perf/util/namespaces.h @@ -13,6 +13,7 @@ #include #include #include +#include #ifndef HAVE_SETNS_SUPPORT int setns(int fd, int nstype); @@ -29,7 +30,7 @@ struct namespaces { struct namespaces *namespaces__new(struct perf_record_namespaces *event); void namespaces__free(struct namespaces *namespaces); -struct nsinfo { +DECLARE_RC_STRUCT(nsinfo) { pid_t pid; pid_t tgid; pid_t nstgid; -- cgit v1.2.3-58-ga151 From 4d623903f1ed63a06e469c4ce45231440d1be5b6 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Mon, 17 Apr 2023 22:11:58 -0300 Subject: perf namespaces: Use the need_setns() accessors instead of accessing ->need_setns directly This uses pre-existing accessors and reduces the use of RC_CHK_ACCESS(nsi). Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/namespaces.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/namespaces.c b/tools/perf/util/namespaces.c index 8a3b7bd27b19..214a8391e07c 100644 --- a/tools/perf/util/namespaces.c +++ b/tools/perf/util/namespaces.c @@ -165,14 +165,14 @@ struct nsinfo *nsinfo__new(pid_t pid) RC_CHK_ACCESS(nsi)->pid = pid; RC_CHK_ACCESS(nsi)->tgid = pid; RC_CHK_ACCESS(nsi)->nstgid = pid; - RC_CHK_ACCESS(nsi)->need_setns = false; + nsinfo__clear_need_setns(nsi); RC_CHK_ACCESS(nsi)->in_pidns = false; /* Init may fail if the process exits while we're trying to look at its * proc information. In that case, save the pid but don't try to enter * the namespace. */ if (nsinfo__init(nsi) == -1) - RC_CHK_ACCESS(nsi)->need_setns = false; + nsinfo__clear_need_setns(nsi); return nsi; } @@ -276,7 +276,7 @@ void nsinfo__mountns_enter(struct nsinfo *nsi, nc->oldns = -1; nc->newns = -1; - if (!nsi || !RC_CHK_ACCESS(nsi)->need_setns) + if (!nsi || !nsinfo__need_setns(nsi)) return; if (snprintf(curpath, PATH_MAX, "/proc/self/ns/mnt") >= PATH_MAX) -- cgit v1.2.3-58-ga151 From f94c21dfd02e98aa0fcb9b453a1198e76ede60e7 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Mon, 17 Apr 2023 22:11:58 -0300 Subject: perf namespaces: Introduce nsinfo__refcnt() accessor to avoid accessing ->refcnt directly To reduces the use of RC_CHK_ACCESS(nsi). Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/namespaces.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/namespaces.c b/tools/perf/util/namespaces.c index 214a8391e07c..2f9fb1e2769c 100644 --- a/tools/perf/util/namespaces.c +++ b/tools/perf/util/namespaces.c @@ -204,11 +204,15 @@ struct nsinfo *nsinfo__copy(const struct nsinfo *nsi) return nnsi; } +static refcount_t *nsinfo__refcnt(struct nsinfo *nsi) +{ + return &RC_CHK_ACCESS(nsi)->refcnt; +} + static void nsinfo__delete(struct nsinfo *nsi) { if (nsi) { - WARN_ONCE(refcount_read(&RC_CHK_ACCESS(nsi)->refcnt) != 0, - "nsinfo refcnt unbalanced\n"); + WARN_ONCE(refcount_read(nsinfo__refcnt(nsi)) != 0, "nsinfo refcnt unbalanced\n"); zfree(&RC_CHK_ACCESS(nsi)->mntns_path); RC_CHK_FREE(nsi); } @@ -219,14 +223,14 @@ struct nsinfo *nsinfo__get(struct nsinfo *nsi) struct nsinfo *result; if (RC_CHK_GET(result, nsi)) - refcount_inc(&RC_CHK_ACCESS(nsi)->refcnt); + refcount_inc(nsinfo__refcnt(nsi)); return result; } void nsinfo__put(struct nsinfo *nsi) { - if (nsi && refcount_dec_and_test(&RC_CHK_ACCESS(nsi)->refcnt)) + if (nsi && refcount_dec_and_test(nsinfo__refcnt(nsi))) nsinfo__delete(nsi); else RC_CHK_PUT(nsi); -- cgit v1.2.3-58-ga151 From 2d1acd3f10baed49329c1b201cafb060aeb377e0 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Mon, 17 Apr 2023 22:11:58 -0300 Subject: perf namespaces: Introduce nsinfo__mntns_path() accessor to avoid accessing ->mntns_path directly To reduce the use of RC_CHK_ACCESS(nsi). Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/namespaces.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/namespaces.c b/tools/perf/util/namespaces.c index 2f9fb1e2769c..cb185c5659d6 100644 --- a/tools/perf/util/namespaces.c +++ b/tools/perf/util/namespaces.c @@ -177,6 +177,11 @@ struct nsinfo *nsinfo__new(pid_t pid) return nsi; } +static const char *nsinfo__mntns_path(const struct nsinfo *nsi) +{ + return RC_CHK_ACCESS(nsi)->mntns_path; +} + struct nsinfo *nsinfo__copy(const struct nsinfo *nsi) { struct nsinfo *nnsi; @@ -193,8 +198,8 @@ struct nsinfo *nsinfo__copy(const struct nsinfo *nsi) RC_CHK_ACCESS(nnsi)->nstgid = nsinfo__nstgid(nsi); RC_CHK_ACCESS(nnsi)->need_setns = nsinfo__need_setns(nsi); RC_CHK_ACCESS(nnsi)->in_pidns = nsinfo__in_pidns(nsi); - if (RC_CHK_ACCESS(nsi)->mntns_path) { - RC_CHK_ACCESS(nnsi)->mntns_path = strdup(RC_CHK_ACCESS(nsi)->mntns_path); + if (nsinfo__mntns_path(nsi)) { + RC_CHK_ACCESS(nnsi)->mntns_path = strdup(nsinfo__mntns_path(nsi)); if (!RC_CHK_ACCESS(nnsi)->mntns_path) { nsinfo__put(nnsi); return NULL; @@ -294,7 +299,7 @@ void nsinfo__mountns_enter(struct nsinfo *nsi, if (oldns < 0) goto errout; - newns = open(RC_CHK_ACCESS(nsi)->mntns_path, O_RDONLY); + newns = open(nsinfo__mntns_path(nsi), O_RDONLY); if (newns < 0) goto errout; -- cgit v1.2.3-58-ga151 From de047c1091854f0c0561f3d199c2ea2e344f10a5 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Mon, 17 Apr 2023 18:48:26 +0100 Subject: perf script task-analyzer: Fix spelling mistake "miliseconds" -> "milliseconds" There is a spelling mistake in the help for the --ms option. Fix it. Signed-off-by: Colin Ian King Acked-by: Hagen Paul Pfeifer Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Petar Gligoric Cc: Peter Zijlstra Cc: kernel-janitors@vger.kernel.org Link: https://lore.kernel.org/r/20230417174826.52963-1-colin.i.king@gmail.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/scripts/python/task-analyzer.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/scripts/python/task-analyzer.py b/tools/perf/scripts/python/task-analyzer.py index 52e8dae9b1f0..3f1df9894246 100755 --- a/tools/perf/scripts/python/task-analyzer.py +++ b/tools/perf/scripts/python/task-analyzer.py @@ -114,7 +114,7 @@ def _parse_args(): "--ns", action="store_true", help="show timestamps in nanoseconds" ) parser.add_argument( - "--ms", action="store_true", help="show timestamps in miliseconds" + "--ms", action="store_true", help="show timestamps in milliseconds" ) parser.add_argument( "--extended-times", -- cgit v1.2.3-58-ga151 From b550bc90bb8218da8c944f28b99cb372ad969749 Mon Sep 17 00:00:00 2001 From: James Clark Date: Tue, 18 Apr 2023 15:12:03 +0100 Subject: perf cs-etm: Fix segfault in dso lookup map__dso() is called before thread__find_map() which always results in a null pointer dereference. Fix it by finding first, then checking if it exists. Fixes: 63df0e4bc368adbd ("perf map: Add accessor for dso") Signed-off-by: James Clark Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: John Garry Cc: Leo Yan Cc: Mark Rutland Cc: Mathieu Poirier Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Suzuki Poulouse Cc: Will Deacon Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230418141203.673465-1-james.clark@arm.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/cs-etm.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 103865968700..8dd81ddd9e4e 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -885,9 +885,11 @@ static u32 cs_etm__mem_access(struct cs_etm_queue *etmq, u8 trace_chan_id, thread = etmq->etm->unknown_thread; } - dso = map__dso(al.map); + if (!thread__find_map(thread, cpumode, address, &al)) + return 0; - if (!thread__find_map(thread, cpumode, address, &al) || !dso) + dso = map__dso(al.map); + if (!dso) return 0; if (dso->data.status == DSO_DATA_STATUS_ERROR && -- cgit v1.2.3-58-ga151 From 3ad1be6faef9a482c3098928220fcafaa51a1283 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Tue, 18 Apr 2023 12:46:02 -0300 Subject: perf dso: Fix use before NULL check introduced by map__dso() introduction James Clark noticed that the recent 63df0e4bc368adbd ("perf map: Add accessor for dso") patch accessed map->dso before the 'map' variable was NULL checked, which is a change in logic that leads to segmentation faults, so comb thru that patch to fix similar cases. Fixes: 63df0e4bc368adbd ("perf map: Add accessor for dso") Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Leo Yan Cc: Mark Rutland Cc: Mathieu Poirier Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Will Deacon Link: https://lore.kernel.org/lkml/ZD68RYCVT8hqPuxr@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-script.c | 7 +++---- tools/perf/ui/browsers/hists.c | 4 ++-- tools/perf/util/sort.c | 2 +- 3 files changed, 6 insertions(+), 7 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index 8fba247b798c..006f522d0e7f 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -1075,8 +1075,7 @@ static int grab_bb(u8 *buffer, u64 start, u64 end, return 0; } - dso = map__dso(al.map); - if (!thread__find_map(thread, *cpumode, start, &al) || !dso) { + if (!thread__find_map(thread, *cpumode, start, &al) || (dso = map__dso(al.map)) == NULL) { pr_debug("\tcannot resolve %" PRIx64 "-%" PRIx64 "\n", start, end); return 0; } @@ -1106,9 +1105,9 @@ static int map__fprintf_srccode(struct map *map, u64 addr, FILE *fp, struct srcc unsigned line; int len; char *srccode; - struct dso *dso = map__dso(map); + struct dso *dso; - if (!map || !dso) + if (!map || (dso = map__dso(map)) == NULL) return 0; srcfile = get_srcline_split(dso, map__rip_2objdump(map, addr), diff --git a/tools/perf/ui/browsers/hists.c b/tools/perf/ui/browsers/hists.c index ab70e5f5fad2..69c81759a64f 100644 --- a/tools/perf/ui/browsers/hists.c +++ b/tools/perf/ui/browsers/hists.c @@ -2499,9 +2499,9 @@ add_annotate_opt(struct hist_browser *browser __maybe_unused, struct map_symbol *ms, u64 addr) { - struct dso *dso = map__dso(ms->map); + struct dso *dso; - if (!ms->map || !dso || dso->annotate_warned) + if (!ms->map || (dso = map__dso(ms->map)) == NULL || dso->annotate_warned) return 0; if (!ms->sym) diff --git a/tools/perf/util/sort.c b/tools/perf/util/sort.c index f2ffaf90648e..31b1cd0935e2 100644 --- a/tools/perf/util/sort.c +++ b/tools/perf/util/sort.c @@ -1568,7 +1568,7 @@ static int hist_entry__dcacheline_snprintf(struct hist_entry *he, char *bf, if (he->mem_info) { struct map *map = he->mem_info->daddr.ms.map; - struct dso *dso = map__dso(map); + struct dso *dso = map ? map__dso(map) : NULL; addr = cl_address(he->mem_info->daddr.al_addr, chk_double_cl); ms = &he->mem_info->daddr.ms; -- cgit v1.2.3-58-ga151 From fe693d951e3c303b4fb6c712f8affecbe9e8b001 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Tue, 18 Apr 2023 17:33:48 -0300 Subject: perf maps: Add maps__refcnt() accessor to allow checking maps pointer To remove one more direct access to 'struct maps' so that we can intercept accesses to its instantiations and refcount check it to catch use after free, etc. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/thread-maps-share.c | 12 ++++++------ tools/perf/util/maps.c | 6 +++--- tools/perf/util/maps.h | 5 +++++ 3 files changed, 14 insertions(+), 9 deletions(-) (limited to 'tools') diff --git a/tools/perf/tests/thread-maps-share.c b/tools/perf/tests/thread-maps-share.c index 84edd82c519e..caf8fbe7c440 100644 --- a/tools/perf/tests/thread-maps-share.c +++ b/tools/perf/tests/thread-maps-share.c @@ -43,7 +43,7 @@ static int test__thread_maps_share(struct test_suite *test __maybe_unused, int s leader && t1 && t2 && t3 && other); maps = leader->maps; - TEST_ASSERT_EQUAL("wrong refcnt", refcount_read(&maps->refcnt), 4); + TEST_ASSERT_EQUAL("wrong refcnt", refcount_read(maps__refcnt(maps)), 4); /* test the maps pointer is shared */ TEST_ASSERT_VAL("maps don't match", maps == t1->maps); @@ -71,25 +71,25 @@ static int test__thread_maps_share(struct test_suite *test __maybe_unused, int s machine__remove_thread(machine, other_leader); other_maps = other->maps; - TEST_ASSERT_EQUAL("wrong refcnt", refcount_read(&other_maps->refcnt), 2); + TEST_ASSERT_EQUAL("wrong refcnt", refcount_read(maps__refcnt(other_maps)), 2); TEST_ASSERT_VAL("maps don't match", other_maps == other_leader->maps); /* release thread group */ thread__put(leader); - TEST_ASSERT_EQUAL("wrong refcnt", refcount_read(&maps->refcnt), 3); + TEST_ASSERT_EQUAL("wrong refcnt", refcount_read(maps__refcnt(maps)), 3); thread__put(t1); - TEST_ASSERT_EQUAL("wrong refcnt", refcount_read(&maps->refcnt), 2); + TEST_ASSERT_EQUAL("wrong refcnt", refcount_read(maps__refcnt(maps)), 2); thread__put(t2); - TEST_ASSERT_EQUAL("wrong refcnt", refcount_read(&maps->refcnt), 1); + TEST_ASSERT_EQUAL("wrong refcnt", refcount_read(maps__refcnt(maps)), 1); thread__put(t3); /* release other group */ thread__put(other_leader); - TEST_ASSERT_EQUAL("wrong refcnt", refcount_read(&other_maps->refcnt), 1); + TEST_ASSERT_EQUAL("wrong refcnt", refcount_read(maps__refcnt(other_maps)), 1); thread__put(other); diff --git a/tools/perf/util/maps.c b/tools/perf/util/maps.c index 5afed53ea0b4..953dc20d55d7 100644 --- a/tools/perf/util/maps.c +++ b/tools/perf/util/maps.c @@ -12,13 +12,13 @@ static void maps__init(struct maps *maps, struct machine *machine) { + refcount_set(maps__refcnt(maps), 1); maps->entries = RB_ROOT; init_rwsem(maps__lock(maps)); maps->machine = machine; maps->last_search_by_name = NULL; maps->nr_maps = 0; maps->maps_by_name = NULL; - refcount_set(&maps->refcnt, 1); } static void __maps__free_maps_by_name(struct maps *maps) @@ -180,14 +180,14 @@ void maps__delete(struct maps *maps) struct maps *maps__get(struct maps *maps) { if (maps) - refcount_inc(&maps->refcnt); + refcount_inc(maps__refcnt(maps)); return maps; } void maps__put(struct maps *maps) { - if (maps && refcount_dec_and_test(&maps->refcnt)) + if (maps && refcount_dec_and_test(maps__refcnt(maps))) maps__delete(maps); } diff --git a/tools/perf/util/maps.h b/tools/perf/util/maps.h index bde3390c7096..cfb1b79d1671 100644 --- a/tools/perf/util/maps.h +++ b/tools/perf/util/maps.h @@ -88,6 +88,11 @@ static inline unsigned int maps__nr_maps(const struct maps *maps) return maps->nr_maps; } +static inline refcount_t *maps__refcnt(struct maps *maps) +{ + return &maps->refcnt; +} + #ifdef HAVE_LIBUNWIND_SUPPORT static inline void *maps__addr_space(struct maps *maps) { -- cgit v1.2.3-58-ga151 From a07dacad8ac40d1beadb640fe341b5198c1cf097 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Tue, 18 Apr 2023 17:45:34 -0300 Subject: perf maps: Use maps__nr_maps() instead of open coded maps->nr_maps To use the existing accessor and be consistent. Signef-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/machine.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c index 25738775834e..85787672d335 100644 --- a/tools/perf/util/machine.c +++ b/tools/perf/util/machine.c @@ -435,7 +435,7 @@ static struct thread *findnew_guest_code(struct machine *machine, return NULL; /* Assume maps are set up if there are any */ - if (thread->maps->nr_maps) + if (maps__nr_maps(thread->maps)) return thread; host_thread = machine__find_thread(host_machine, -1, pid); -- cgit v1.2.3-58-ga151 From 8f12692b7e61e5fb5d3e4f6692d6675f62eeebdc Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Wed, 19 Apr 2023 10:48:37 -0300 Subject: perf maps: Add reference count checking Add reference count checking to make sure of good use of get and put. Add and use accessors to reduce RC_CHK clutter. The only significant issue was in tests/thread-maps-share.c where reference counts were released in the reverse order to acquisition, leading to a use after put. This was fixed by reversing the put order. Committer notes: Extracted from a larger patch removing bits that were covered by the use of pre-existing maps__ accessors (e.g. maps__nr_maps()) and new ones added (maps__refcnt()) to reduce RC_CHK_ACCESS(maps)-> source code pollution. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexey Bayduraev Cc: Dmitriy Vyukov Cc: Jiri Olsa Cc: Namhyung Kim Cc: Riccardo Mancini Cc: Stephane Eranian Cc: Stephen Brennan Link: https://lore.kernel.org/lkml/20230407230405.2931830-5-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/thread-maps-share.c | 8 +++--- tools/perf/util/maps.c | 47 ++++++++++++++++++-------------- tools/perf/util/maps.h | 19 +++++++------ tools/perf/util/symbol.c | 13 +++++---- tools/perf/util/unwind-libdw.c | 2 +- tools/perf/util/unwind-libunwind-local.c | 2 +- tools/perf/util/unwind-libunwind.c | 2 +- 7 files changed, 50 insertions(+), 43 deletions(-) (limited to 'tools') diff --git a/tools/perf/tests/thread-maps-share.c b/tools/perf/tests/thread-maps-share.c index caf8fbe7c440..75ce8aedfc78 100644 --- a/tools/perf/tests/thread-maps-share.c +++ b/tools/perf/tests/thread-maps-share.c @@ -46,9 +46,9 @@ static int test__thread_maps_share(struct test_suite *test __maybe_unused, int s TEST_ASSERT_EQUAL("wrong refcnt", refcount_read(maps__refcnt(maps)), 4); /* test the maps pointer is shared */ - TEST_ASSERT_VAL("maps don't match", maps == t1->maps); - TEST_ASSERT_VAL("maps don't match", maps == t2->maps); - TEST_ASSERT_VAL("maps don't match", maps == t3->maps); + TEST_ASSERT_VAL("maps don't match", RC_CHK_ACCESS(maps) == RC_CHK_ACCESS(t1->maps)); + TEST_ASSERT_VAL("maps don't match", RC_CHK_ACCESS(maps) == RC_CHK_ACCESS(t2->maps)); + TEST_ASSERT_VAL("maps don't match", RC_CHK_ACCESS(maps) == RC_CHK_ACCESS(t3->maps)); /* * Verify the other leader was created by previous call. @@ -73,7 +73,7 @@ static int test__thread_maps_share(struct test_suite *test __maybe_unused, int s other_maps = other->maps; TEST_ASSERT_EQUAL("wrong refcnt", refcount_read(maps__refcnt(other_maps)), 2); - TEST_ASSERT_VAL("maps don't match", other_maps == other_leader->maps); + TEST_ASSERT_VAL("maps don't match", RC_CHK_ACCESS(other_maps) == RC_CHK_ACCESS(other_leader->maps)); /* release thread group */ thread__put(leader); diff --git a/tools/perf/util/maps.c b/tools/perf/util/maps.c index 953dc20d55d7..8a13396acd1a 100644 --- a/tools/perf/util/maps.c +++ b/tools/perf/util/maps.c @@ -13,12 +13,12 @@ static void maps__init(struct maps *maps, struct machine *machine) { refcount_set(maps__refcnt(maps), 1); - maps->entries = RB_ROOT; init_rwsem(maps__lock(maps)); - maps->machine = machine; - maps->last_search_by_name = NULL; - maps->nr_maps = 0; - maps->maps_by_name = NULL; + RC_CHK_ACCESS(maps)->entries = RB_ROOT; + RC_CHK_ACCESS(maps)->machine = machine; + RC_CHK_ACCESS(maps)->last_search_by_name = NULL; + RC_CHK_ACCESS(maps)->nr_maps = 0; + RC_CHK_ACCESS(maps)->maps_by_name = NULL; } static void __maps__free_maps_by_name(struct maps *maps) @@ -29,8 +29,8 @@ static void __maps__free_maps_by_name(struct maps *maps) for (unsigned int i = 0; i < maps__nr_maps(maps); i++) map__put(maps__maps_by_name(maps)[i]); - zfree(&maps->maps_by_name); - maps->nr_maps_allocated = 0; + zfree(&RC_CHK_ACCESS(maps)->maps_by_name); + RC_CHK_ACCESS(maps)->nr_maps_allocated = 0; } static int __maps__insert(struct maps *maps, struct map *map) @@ -71,7 +71,7 @@ int maps__insert(struct maps *maps, struct map *map) if (err) goto out; - ++maps->nr_maps; + ++RC_CHK_ACCESS(maps)->nr_maps; if (dso && dso->kernel) { struct kmap *kmap = map__kmap(map); @@ -88,7 +88,7 @@ int maps__insert(struct maps *maps, struct map *map) * inserted map and resort. */ if (maps__maps_by_name(maps)) { - if (maps__nr_maps(maps) > maps->nr_maps_allocated) { + if (maps__nr_maps(maps) > RC_CHK_ACCESS(maps)->nr_maps_allocated) { int nr_allocate = maps__nr_maps(maps) * 2; struct map **maps_by_name = realloc(maps__maps_by_name(maps), nr_allocate * sizeof(map)); @@ -99,8 +99,8 @@ int maps__insert(struct maps *maps, struct map *map) goto out; } - maps->maps_by_name = maps_by_name; - maps->nr_maps_allocated = nr_allocate; + RC_CHK_ACCESS(maps)->maps_by_name = maps_by_name; + RC_CHK_ACCESS(maps)->nr_maps_allocated = nr_allocate; } maps__maps_by_name(maps)[maps__nr_maps(maps) - 1] = map__get(map); __maps__sort_by_name(maps); @@ -122,15 +122,15 @@ void maps__remove(struct maps *maps, struct map *map) struct map_rb_node *rb_node; down_write(maps__lock(maps)); - if (maps->last_search_by_name == map) - maps->last_search_by_name = NULL; + if (RC_CHK_ACCESS(maps)->last_search_by_name == map) + RC_CHK_ACCESS(maps)->last_search_by_name = NULL; rb_node = maps__find_node(maps, map); assert(rb_node->map == map); __maps__remove(maps, rb_node); if (maps__maps_by_name(maps)) __maps__free_maps_by_name(maps); - --maps->nr_maps; + --RC_CHK_ACCESS(maps)->nr_maps; up_write(maps__lock(maps)); } @@ -162,33 +162,38 @@ bool maps__empty(struct maps *maps) struct maps *maps__new(struct machine *machine) { - struct maps *maps = zalloc(sizeof(*maps)); + struct maps *result; + RC_STRUCT(maps) *maps = zalloc(sizeof(*maps)); - if (maps != NULL) - maps__init(maps, machine); + if (ADD_RC_CHK(result, maps)) + maps__init(result, machine); - return maps; + return result; } void maps__delete(struct maps *maps) { maps__exit(maps); unwind__finish_access(maps); - free(maps); + RC_CHK_FREE(maps); } struct maps *maps__get(struct maps *maps) { - if (maps) + struct maps *result; + + if (RC_CHK_GET(result, maps)) refcount_inc(maps__refcnt(maps)); - return maps; + return result; } void maps__put(struct maps *maps) { if (maps && refcount_dec_and_test(maps__refcnt(maps))) maps__delete(maps); + else + RC_CHK_PUT(maps); } struct symbol *maps__find_symbol(struct maps *maps, u64 addr, struct map **mapp) diff --git a/tools/perf/util/maps.h b/tools/perf/util/maps.h index cfb1b79d1671..d2963456cfbe 100644 --- a/tools/perf/util/maps.h +++ b/tools/perf/util/maps.h @@ -8,6 +8,7 @@ #include #include #include "rwsem.h" +#include struct ref_reloc_sym; struct machine; @@ -32,7 +33,7 @@ struct map *maps__find(struct maps *maps, u64 addr); for (map = maps__first(maps), next = map_rb_node__next(map); map; \ map = next, next = map_rb_node__next(map)) -struct maps { +DECLARE_RC_STRUCT(maps) { struct rb_root entries; struct rw_semaphore lock; struct machine *machine; @@ -65,43 +66,43 @@ void maps__put(struct maps *maps); static inline struct rb_root *maps__entries(struct maps *maps) { - return &maps->entries; + return &RC_CHK_ACCESS(maps)->entries; } static inline struct machine *maps__machine(struct maps *maps) { - return maps->machine; + return RC_CHK_ACCESS(maps)->machine; } static inline struct rw_semaphore *maps__lock(struct maps *maps) { - return &maps->lock; + return &RC_CHK_ACCESS(maps)->lock; } static inline struct map **maps__maps_by_name(struct maps *maps) { - return maps->maps_by_name; + return RC_CHK_ACCESS(maps)->maps_by_name; } static inline unsigned int maps__nr_maps(const struct maps *maps) { - return maps->nr_maps; + return RC_CHK_ACCESS(maps)->nr_maps; } static inline refcount_t *maps__refcnt(struct maps *maps) { - return &maps->refcnt; + return &RC_CHK_ACCESS(maps)->refcnt; } #ifdef HAVE_LIBUNWIND_SUPPORT static inline void *maps__addr_space(struct maps *maps) { - return maps->addr_space; + return RC_CHK_ACCESS(maps)->addr_space; } static inline const struct unwind_libunwind_ops *maps__unwind_libunwind_ops(const struct maps *maps) { - return maps->unwind_libunwind_ops; + return RC_CHK_ACCESS(maps)->unwind_libunwind_ops; } #endif diff --git a/tools/perf/util/symbol.c b/tools/perf/util/symbol.c index e7f63670688e..01fa5560a0bb 100644 --- a/tools/perf/util/symbol.c +++ b/tools/perf/util/symbol.c @@ -2096,8 +2096,8 @@ static int map__groups__sort_by_name_from_rbtree(struct maps *maps) up_read(maps__lock(maps)); down_write(maps__lock(maps)); - maps->maps_by_name = maps_by_name; - maps->nr_maps_allocated = maps__nr_maps(maps); + RC_CHK_ACCESS(maps)->maps_by_name = maps_by_name; + RC_CHK_ACCESS(maps)->nr_maps_allocated = maps__nr_maps(maps); maps__for_each_entry(maps, rb_node) maps_by_name[i++] = map__get(rb_node->map); @@ -2132,11 +2132,12 @@ struct map *maps__find_by_name(struct maps *maps, const char *name) down_read(maps__lock(maps)); - if (maps->last_search_by_name) { - const struct dso *dso = map__dso(maps->last_search_by_name); + + if (RC_CHK_ACCESS(maps)->last_search_by_name) { + const struct dso *dso = map__dso(RC_CHK_ACCESS(maps)->last_search_by_name); if (strcmp(dso->short_name, name) == 0) { - map = maps->last_search_by_name; + map = RC_CHK_ACCESS(maps)->last_search_by_name; goto out_unlock; } } @@ -2156,7 +2157,7 @@ struct map *maps__find_by_name(struct maps *maps, const char *name) map = rb_node->map; dso = map__dso(map); if (strcmp(dso->short_name, name) == 0) { - maps->last_search_by_name = map; + RC_CHK_ACCESS(maps)->last_search_by_name = map; goto out_unlock; } } diff --git a/tools/perf/util/unwind-libdw.c b/tools/perf/util/unwind-libdw.c index 9565f9906e5d..bdccfc511b7e 100644 --- a/tools/perf/util/unwind-libdw.c +++ b/tools/perf/util/unwind-libdw.c @@ -230,7 +230,7 @@ int unwind__get_entries(unwind_entry_cb_t cb, void *arg, struct unwind_info *ui, ui_buf = { .sample = data, .thread = thread, - .machine = thread->maps->machine, + .machine = RC_CHK_ACCESS(thread->maps)->machine, .cb = cb, .arg = arg, .max_stack = max_stack, diff --git a/tools/perf/util/unwind-libunwind-local.c b/tools/perf/util/unwind-libunwind-local.c index f9a52af48de4..83dd79dcd597 100644 --- a/tools/perf/util/unwind-libunwind-local.c +++ b/tools/perf/util/unwind-libunwind-local.c @@ -677,7 +677,7 @@ static int _unwind__prepare_access(struct maps *maps) { void *addr_space = unw_create_addr_space(&accessors, 0); - maps->addr_space = addr_space; + RC_CHK_ACCESS(maps)->addr_space = addr_space; if (!addr_space) { pr_err("unwind: Can't create unwind address space.\n"); return -ENOMEM; diff --git a/tools/perf/util/unwind-libunwind.c b/tools/perf/util/unwind-libunwind.c index 4378daaafcd3..b54968e6a4e4 100644 --- a/tools/perf/util/unwind-libunwind.c +++ b/tools/perf/util/unwind-libunwind.c @@ -14,7 +14,7 @@ struct unwind_libunwind_ops __weak *arm64_unwind_libunwind_ops; static void unwind__register_ops(struct maps *maps, struct unwind_libunwind_ops *ops) { - maps->unwind_libunwind_ops = ops; + RC_CHK_ACCESS(maps)->unwind_libunwind_ops = ops; } int unwind__prepare_access(struct maps *maps, struct map *map, bool *initialized) -- cgit v1.2.3-58-ga151 From e1805aae1e0f648351913e7f5a8a7530a90c8634 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 19 Apr 2023 10:57:57 -0300 Subject: perf map: Add missing conversions to map__refcnt() Some conversions weren't performed in 4e8db2d7520f780f ("perf map: Add map__refcnt() accessor to use in the maps test"), fix it. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/map.c | 6 +++--- tools/perf/util/map.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/map.c b/tools/perf/util/map.c index d81b6ca18ee9..b6a8935026eb 100644 --- a/tools/perf/util/map.c +++ b/tools/perf/util/map.c @@ -112,7 +112,7 @@ void map__init(struct map *map, u64 start, u64 end, u64 pgoff, struct dso *dso) map->map_ip = map__dso_map_ip; map->unmap_ip = map__dso_unmap_ip; map->erange_warned = false; - refcount_set(&map->refcnt, 1); + refcount_set(map__refcnt(map), 1); } struct map *map__new(struct machine *machine, u64 start, u64 len, @@ -292,7 +292,7 @@ bool map__has_symbols(const struct map *map) static void map__exit(struct map *map) { - BUG_ON(refcount_read(&map->refcnt) != 0); + BUG_ON(refcount_read(map__refcnt(map)) != 0); dso__zput(map->dso); } @@ -304,7 +304,7 @@ void map__delete(struct map *map) void map__put(struct map *map) { - if (map && refcount_dec_and_test(&map->refcnt)) + if (map && refcount_dec_and_test(map__refcnt(map))) map__delete(map); } diff --git a/tools/perf/util/map.h b/tools/perf/util/map.h index f89ab7c2d327..4f7d9505f7ff 100644 --- a/tools/perf/util/map.h +++ b/tools/perf/util/map.h @@ -159,7 +159,7 @@ struct map *map__clone(struct map *map); static inline struct map *map__get(struct map *map) { if (map) - refcount_inc(&map->refcnt); + refcount_inc(map__refcnt(map)); return map; } -- cgit v1.2.3-58-ga151 From e6a9efcee55f084a5450e4853ecbbaa0b086dcd0 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 19 Apr 2023 12:24:12 -0300 Subject: perf map: Add set_ methods for map->{start,end,pgoff,pgoff,reloc,erange_warned,dso,map_ip,unmap_ip,priv} To have a way to intercept usage of the reference counted struct map. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-top.c | 4 +-- tools/perf/tests/maps.c | 16 ++++----- tools/perf/tests/vmlinux-kallsyms.c | 4 +-- tools/perf/util/machine.c | 23 ++++++------- tools/perf/util/map.c | 20 ++++++------ tools/perf/util/map.h | 65 +++++++++++++++++++++++++++++++++++++ tools/perf/util/maps.c | 6 ++-- tools/perf/util/symbol-elf.c | 26 +++++++-------- tools/perf/util/symbol.c | 33 ++++++++++--------- 9 files changed, 132 insertions(+), 65 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c index 5d448c36ed22..eb5740154bc0 100644 --- a/tools/perf/builtin-top.c +++ b/tools/perf/builtin-top.c @@ -191,7 +191,7 @@ static void ui__warn_map_erange(struct map *map, struct symbol *sym, u64 ip) if (use_browser <= 0) sleep(5); - map->erange_warned = true; + map__set_erange_warned(map, true); } static void perf_top__record_precise_ip(struct perf_top *top, @@ -225,7 +225,7 @@ static void perf_top__record_precise_ip(struct perf_top *top, */ mutex_unlock(&he->hists->lock); - if (err == -ERANGE && !he->ms.map->erange_warned) + if (err == -ERANGE && !map__erange_warned(he->ms.map)) ui__warn_map_erange(he->ms.map, sym, ip); else if (err == -ENOMEM) { pr_err("Not enough memory for annotating '%s' symbol!\n", diff --git a/tools/perf/tests/maps.c b/tools/perf/tests/maps.c index a6278f9c8b71..8c0eb5cf8bb5 100644 --- a/tools/perf/tests/maps.c +++ b/tools/perf/tests/maps.c @@ -95,8 +95,8 @@ static int test__maps__merge_in(struct test_suite *t __maybe_unused, int subtest map = dso__new_map(bpf_progs[i].name); TEST_ASSERT_VAL("failed to create map", map); - map->start = bpf_progs[i].start; - map->end = bpf_progs[i].end; + map__set_start(map, bpf_progs[i].start); + map__set_end(map, bpf_progs[i].end); TEST_ASSERT_VAL("failed to insert map", maps__insert(maps, map) == 0); map__put(map); } @@ -111,16 +111,16 @@ static int test__maps__merge_in(struct test_suite *t __maybe_unused, int subtest TEST_ASSERT_VAL("failed to create map", map_kcore3); /* kcore1 map overlaps over all bpf maps */ - map_kcore1->start = 100; - map_kcore1->end = 1000; + map__set_start(map_kcore1, 100); + map__set_end(map_kcore1, 1000); /* kcore2 map hides behind bpf_prog_2 */ - map_kcore2->start = 550; - map_kcore2->end = 570; + map__set_start(map_kcore2, 550); + map__set_end(map_kcore2, 570); /* kcore3 map hides behind bpf_prog_3, kcore1 and adds new map */ - map_kcore3->start = 880; - map_kcore3->end = 1100; + map__set_start(map_kcore3, 880); + map__set_end(map_kcore3, 1100); ret = maps__merge_in(maps, map_kcore1); TEST_ASSERT_VAL("failed to merge map", !ret); diff --git a/tools/perf/tests/vmlinux-kallsyms.c b/tools/perf/tests/vmlinux-kallsyms.c index af511233c764..1078a93b01aa 100644 --- a/tools/perf/tests/vmlinux-kallsyms.c +++ b/tools/perf/tests/vmlinux-kallsyms.c @@ -304,7 +304,7 @@ next_pair: dso->short_name : dso->name)); if (pair) { - pair->priv = 1; + map__set_priv(pair, 1); } else { if (!header_printed) { pr_info("WARN: Maps only in vmlinux:\n"); @@ -340,7 +340,7 @@ next_pair: pr_info(":\nWARN: *%" PRIx64 "-%" PRIx64 " %" PRIx64, map__start(pair), map__end(pair), map__pgoff(pair)); pr_info(" %s\n", dso->name); - pair->priv = 1; + map__set_priv(pair, 1); } } diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c index 85787672d335..8ccbe48e23bd 100644 --- a/tools/perf/util/machine.c +++ b/tools/perf/util/machine.c @@ -910,8 +910,8 @@ static int machine__process_ksymbol_register(struct machine *machine, dso__set_loaded(dso); } - map->start = event->ksymbol.addr; - map->end = map__start(map) + event->ksymbol.len; + map__set_start(map, event->ksymbol.addr); + map__set_end(map, map__start(map) + event->ksymbol.len); err = maps__insert(machine__kernel_maps(machine), map); if (err) { err = -ENOMEM; @@ -1218,8 +1218,8 @@ int machine__create_extra_kernel_map(struct machine *machine, if (!map) return -ENOMEM; - map->end = xm->end; - map->pgoff = xm->pgoff; + map__set_end(map, xm->end); + map__set_pgoff(map, xm->pgoff); kmap = map__kmap(map); @@ -1291,7 +1291,7 @@ int machine__map_x86_64_entry_trampolines(struct machine *machine, dest_map = maps__find(kmaps, map__pgoff(map)); if (dest_map != map) - map->pgoff = map__map_ip(dest_map, map__pgoff(map)); + map__set_pgoff(map, map__map_ip(dest_map, map__pgoff(map))); found = true; } if (found || machine->trampolines_mapped) @@ -1342,7 +1342,8 @@ __machine__create_kernel_maps(struct machine *machine, struct dso *kernel) if (machine->vmlinux_map == NULL) return -ENOMEM; - machine->vmlinux_map->map_ip = machine->vmlinux_map->unmap_ip = identity__map_ip; + map__set_map_ip(machine->vmlinux_map, identity__map_ip); + map__set_unmap_ip(machine->vmlinux_map, identity__map_ip); return maps__insert(machine__kernel_maps(machine), machine->vmlinux_map); } @@ -1623,7 +1624,7 @@ static int machine__create_module(void *arg, const char *name, u64 start, map = machine__addnew_module_map(machine, start, name); if (map == NULL) return -1; - map->end = start + size; + map__set_end(map, start + size); dso__kernel_module_get_build_id(map__dso(map), machine->root_dir); map__put(map); @@ -1659,14 +1660,14 @@ static int machine__create_modules(struct machine *machine) static void machine__set_kernel_mmap(struct machine *machine, u64 start, u64 end) { - machine->vmlinux_map->start = start; - machine->vmlinux_map->end = end; + map__set_start(machine->vmlinux_map, start); + map__set_end(machine->vmlinux_map, end); /* * Be a bit paranoid here, some perf.data file came with * a zero sized synthesized MMAP event for the kernel. */ if (start == 0 && end == 0) - machine->vmlinux_map->end = ~0ULL; + map__set_end(machine->vmlinux_map, ~0ULL); } static int machine__update_kernel_mmap(struct machine *machine, @@ -1810,7 +1811,7 @@ static int machine__process_kernel_mmap_event(struct machine *machine, if (map == NULL) goto out_problem; - map->end = map__start(map) + xm->end - xm->start; + map__set_end(map, map__start(map) + xm->end - xm->start); if (build_id__is_defined(bid)) dso__set_build_id(map__dso(map), bid); diff --git a/tools/perf/util/map.c b/tools/perf/util/map.c index b6a8935026eb..bdd2742fa35b 100644 --- a/tools/perf/util/map.c +++ b/tools/perf/util/map.c @@ -104,14 +104,14 @@ static inline bool replace_android_lib(const char *filename, char *newfilename) void map__init(struct map *map, u64 start, u64 end, u64 pgoff, struct dso *dso) { - map->start = start; - map->end = end; - map->pgoff = pgoff; - map->reloc = 0; - map->dso = dso__get(dso); - map->map_ip = map__dso_map_ip; - map->unmap_ip = map__dso_unmap_ip; - map->erange_warned = false; + map__set_start(map, start); + map__set_end(map, end); + map__set_pgoff(map, pgoff); + map__set_reloc(map, 0); + map__set_dso(map, dso__get(dso)); + map__set_map_ip(map, map__dso_map_ip); + map__set_unmap_ip(map, map__dso_unmap_ip); + map__set_erange_warned(map, false); refcount_set(map__refcnt(map), 1); } @@ -317,7 +317,7 @@ void map__fixup_start(struct map *map) if (nd != NULL) { struct symbol *sym = rb_entry(nd, struct symbol, rb_node); - map->start = sym->start; + map__set_start(map, sym->start); } } @@ -329,7 +329,7 @@ void map__fixup_end(struct map *map) if (nd != NULL) { struct symbol *sym = rb_entry(nd, struct symbol, rb_node); - map->end = sym->end; + map__set_end(map, sym->end); } } diff --git a/tools/perf/util/map.h b/tools/perf/util/map.h index 4f7d9505f7ff..0760c671314d 100644 --- a/tools/perf/util/map.h +++ b/tools/perf/util/map.h @@ -62,6 +62,16 @@ static inline u64 map__unmap_ip(const struct map *map, u64 ip) return map->unmap_ip(map, ip); } +static inline void *map__map_ip_ptr(struct map *map) +{ + return map->map_ip; +} + +static inline void* map__unmap_ip_ptr(struct map *map) +{ + return map->unmap_ip; +} + static inline u64 map__start(const struct map *map) { return map->start; @@ -102,6 +112,11 @@ static inline refcount_t *map__refcnt(struct map *map) return &map->refcnt; } +static inline bool map__erange_warned(struct map *map) +{ + return map->erange_warned; +} + static inline size_t map__size(const struct map *map) { return map__end(map) - map__start(map); @@ -231,4 +246,54 @@ static inline int is_no_dso_memory(const char *filename) !strncmp(filename, "/SYSV", 5) || !strcmp(filename, "[heap]"); } + +static inline void map__set_start(struct map *map, u64 start) +{ + map->start = start; +} + +static inline void map__set_end(struct map *map, u64 end) +{ + map->end = end; +} + +static inline void map__set_pgoff(struct map *map, u64 pgoff) +{ + map->pgoff = pgoff; +} + +static inline void map__add_pgoff(struct map *map, u64 inc) +{ + map->pgoff += inc; +} + +static inline void map__set_reloc(struct map *map, u64 reloc) +{ + map->reloc = reloc; +} + +static inline void map__set_priv(struct map *map, int priv) +{ + map->priv = priv; +} + +static inline void map__set_erange_warned(struct map *map, bool erange_warned) +{ + map->erange_warned = erange_warned; +} + +static inline void map__set_dso(struct map *map, struct dso *dso) +{ + map->dso = dso; +} + +static inline void map__set_map_ip(struct map *map, u64 (*map_ip)(const struct map *map, u64 ip)) +{ + map->map_ip = map_ip; +} + +static inline void map__set_unmap_ip(struct map *map, u64 (*unmap_ip)(const struct map *map, u64 rip)) +{ + map->unmap_ip = unmap_ip; +} #endif /* __PERF_MAP_H */ diff --git a/tools/perf/util/maps.c b/tools/perf/util/maps.c index 8a13396acd1a..df2fc8221f3c 100644 --- a/tools/perf/util/maps.c +++ b/tools/perf/util/maps.c @@ -339,7 +339,7 @@ int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp) goto put_map; } - before->end = map__start(map); + map__set_end(before, map__start(map)); err = __maps__insert(maps, before); if (err) { map__put(before); @@ -359,8 +359,8 @@ int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp) goto put_map; } - after->start = map__end(map); - after->pgoff += map__end(map) - map__start(pos->map); + map__set_start(after, map__end(map)); + map__add_pgoff(after, map__end(map) - map__start(pos->map)); assert(map__map_ip(pos->map, map__end(map)) == map__map_ip(after, map__end(map))); err = __maps__insert(maps, after); diff --git a/tools/perf/util/symbol-elf.c b/tools/perf/util/symbol-elf.c index 35724f6a84fa..2a165d83aac4 100644 --- a/tools/perf/util/symbol-elf.c +++ b/tools/perf/util/symbol-elf.c @@ -1354,11 +1354,11 @@ static int dso__process_kernel_symbol(struct dso *dso, struct map *map, */ if (*remap_kernel && dso->kernel && !kmodule) { *remap_kernel = false; - map->start = shdr->sh_addr + ref_reloc(kmap); - map->end = map__start(map) + shdr->sh_size; - map->pgoff = shdr->sh_offset; - map->map_ip = map__dso_map_ip; - map->unmap_ip = map__dso_unmap_ip; + map__set_start(map, shdr->sh_addr + ref_reloc(kmap)); + map__set_end(map, map__start(map) + shdr->sh_size); + map__set_pgoff(map, shdr->sh_offset); + map__set_map_ip(map, map__dso_map_ip); + map__set_unmap_ip(map, map__dso_unmap_ip); /* Ensure maps are correctly ordered */ if (kmaps) { int err; @@ -1379,7 +1379,7 @@ static int dso__process_kernel_symbol(struct dso *dso, struct map *map, */ if (*remap_kernel && kmodule) { *remap_kernel = false; - map->pgoff = shdr->sh_offset; + map__set_pgoff(map, shdr->sh_offset); } *curr_mapp = map; @@ -1414,11 +1414,12 @@ static int dso__process_kernel_symbol(struct dso *dso, struct map *map, map__kmap(curr_map)->kmaps = kmaps; if (adjust_kernel_syms) { - curr_map->start = shdr->sh_addr + ref_reloc(kmap); - curr_map->end = map__start(curr_map) + shdr->sh_size; - curr_map->pgoff = shdr->sh_offset; + map__set_start(curr_map, shdr->sh_addr + ref_reloc(kmap)); + map__set_end(curr_map, map__start(curr_map) + shdr->sh_size); + map__set_pgoff(curr_map, shdr->sh_offset); } else { - curr_map->map_ip = curr_map->unmap_ip = identity__map_ip; + map__set_map_ip(curr_map, identity__map_ip); + map__set_unmap_ip(curr_map, identity__map_ip); } curr_dso->symtab_type = dso->symtab_type; if (maps__insert(kmaps, curr_map)) @@ -1525,8 +1526,7 @@ dso__load_sym_internal(struct dso *dso, struct map *map, struct symsrc *syms_ss, if (strcmp(elf_name, kmap->ref_reloc_sym->name)) continue; kmap->ref_reloc_sym->unrelocated_addr = sym.st_value; - map->reloc = kmap->ref_reloc_sym->addr - - kmap->ref_reloc_sym->unrelocated_addr; + map__set_reloc(map, kmap->ref_reloc_sym->addr - kmap->ref_reloc_sym->unrelocated_addr); break; } } @@ -1536,7 +1536,7 @@ dso__load_sym_internal(struct dso *dso, struct map *map, struct symsrc *syms_ss, * attempted to prelink vdso to its virtual address. */ if (dso__is_vdso(dso)) - map->reloc = map__start(map) - dso->text_offset; + map__set_reloc(map, map__start(map) - dso->text_offset); dso->adjust_symbols = runtime_ss->adjust_symbols || ref_reloc(kmap); /* diff --git a/tools/perf/util/symbol.c b/tools/perf/util/symbol.c index 01fa5560a0bb..35d860f95b18 100644 --- a/tools/perf/util/symbol.c +++ b/tools/perf/util/symbol.c @@ -279,7 +279,7 @@ void maps__fixup_end(struct maps *maps) maps__for_each_entry(maps, curr) { if (prev != NULL && !map__end(prev->map)) - prev->map->end = map__start(curr->map); + map__set_end(prev->map, map__start(curr->map)); prev = curr; } @@ -289,7 +289,7 @@ void maps__fixup_end(struct maps *maps) * last map final address. */ if (curr && !map__end(curr->map)) - curr->map->end = ~0ULL; + map__set_end(curr->map, ~0ULL); up_write(maps__lock(maps)); } @@ -944,7 +944,8 @@ static int maps__split_kallsyms(struct maps *kmaps, struct dso *dso, u64 delta, return -1; } - curr_map->map_ip = curr_map->unmap_ip = identity__map_ip; + map__set_map_ip(curr_map, identity__map_ip); + map__set_unmap_ip(curr_map, identity__map_ip); if (maps__insert(kmaps, curr_map)) { dso__put(ndso); return -1; @@ -1250,8 +1251,8 @@ static int kcore_mapfn(u64 start, u64 len, u64 pgoff, void *data) return -ENOMEM; } - list_node->map->end = map__start(list_node->map) + len; - list_node->map->pgoff = pgoff; + map__set_end(list_node->map, map__start(list_node->map) + len); + map__set_pgoff(list_node->map, pgoff); list_add(&list_node->node, &md->maps); @@ -1286,7 +1287,7 @@ int maps__merge_in(struct maps *kmaps, struct map *new_map) * |new......| -> |new..| * |old....| -> |old....| */ - new_map->end = map__start(old_map); + map__set_end(new_map, map__start(old_map)); } else { /* * |new.............| -> |new..| |new..| @@ -1306,10 +1307,10 @@ int maps__merge_in(struct maps *kmaps, struct map *new_map) goto out; } - m->map->end = map__start(old_map); + map__set_end(m->map, map__start(old_map)); list_add_tail(&m->node, &merged); - new_map->pgoff += map__end(old_map) - map__start(new_map); - new_map->start = map__end(old_map); + map__add_pgoff(new_map, map__end(old_map) - map__start(new_map)); + map__set_start(new_map, map__end(old_map)); } } else { /* @@ -1329,8 +1330,8 @@ int maps__merge_in(struct maps *kmaps, struct map *new_map) * |new......| -> |new...| * |old....| -> |old....| */ - new_map->pgoff += map__end(old_map) - map__start(new_map); - new_map->start = map__end(old_map); + map__add_pgoff(new_map, map__end(old_map) - map__start(new_map)); + map__set_start(new_map, map__end(old_map)); } } } @@ -1457,11 +1458,11 @@ static int dso__load_kcore(struct dso *dso, struct map *map, list_del_init(&new_node->node); if (new_map == replacement_map) { - map->start = map__start(new_map); - map->end = map__end(new_map); - map->pgoff = map__pgoff(new_map); - map->map_ip = new_map->map_ip; - map->unmap_ip = new_map->unmap_ip; + map__set_start(map, map__start(new_map)); + map__set_end(map, map__end(new_map)); + map__set_pgoff(map, map__pgoff(new_map)); + map__set_map_ip(map, map__map_ip_ptr(new_map)); + map__set_unmap_ip(map, map__unmap_ip_ptr(new_map)); /* Ensure maps are correctly ordered */ map__get(map); maps__remove(kmaps, map); -- cgit v1.2.3-58-ga151 From 2832ef81d4c75d4f0e3945bd2cb0b7012313cbb3 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Wed, 19 Apr 2023 12:57:53 -0300 Subject: perf map: Add reference count checking There's no strict get/put policy with map that leads to leaks or use after free. Reference count checking identifies correct pairing of gets and puts. Committer notes: Extracted from a larger patch removing bits that were covered by the use of pre-existing map__ accessors (e.g. maps__nr_maps()) and new ones added (map__refcnt() and the maps__set_ ones) to reduce RC_CHK_ACCESS(maps)-> source code pollution. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexey Bayduraev Cc: Dmitriy Vyukov Cc: Jiri Olsa Cc: Namhyung Kim Cc: Riccardo Mancini Cc: Stephane Eranian Cc: Stephen Brennan Link: https://lore.kernel.org/lkml/20230407230405.2931830-6-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/hists_link.c | 2 +- tools/perf/util/machine.c | 2 +- tools/perf/util/map.c | 43 ++++++++++++++++++-------------- tools/perf/util/map.h | 58 +++++++++++++++++++++++-------------------- tools/perf/util/maps.c | 4 +-- tools/perf/util/symbol.c | 4 +-- 6 files changed, 62 insertions(+), 51 deletions(-) (limited to 'tools') diff --git a/tools/perf/tests/hists_link.c b/tools/perf/tests/hists_link.c index 64ce8097889c..141e2972e34f 100644 --- a/tools/perf/tests/hists_link.c +++ b/tools/perf/tests/hists_link.c @@ -145,7 +145,7 @@ static int find_sample(struct sample *samples, size_t nr_samples, { while (nr_samples--) { if (samples->thread == t && - samples->map == m && + RC_CHK_ACCESS(samples->map) == RC_CHK_ACCESS(m) && samples->sym == s) return 1; samples++; diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c index 8ccbe48e23bd..9e02e19c1b7a 100644 --- a/tools/perf/util/machine.c +++ b/tools/perf/util/machine.c @@ -953,7 +953,7 @@ static int machine__process_ksymbol_unregister(struct machine *machine, if (!map) return 0; - if (map != machine->vmlinux_map) + if (RC_CHK_ACCESS(map) != RC_CHK_ACCESS(machine->vmlinux_map)) maps__remove(machine__kernel_maps(machine), map); else { struct dso *dso = map__dso(map); diff --git a/tools/perf/util/map.c b/tools/perf/util/map.c index bdd2742fa35b..b7f890950909 100644 --- a/tools/perf/util/map.c +++ b/tools/perf/util/map.c @@ -120,11 +120,13 @@ struct map *map__new(struct machine *machine, u64 start, u64 len, u32 prot, u32 flags, struct build_id *bid, char *filename, struct thread *thread) { - struct map *map = malloc(sizeof(*map)); + struct map *result; + RC_STRUCT(map) *map; struct nsinfo *nsi = NULL; struct nsinfo *nnsi; - if (map != NULL) { + map = malloc(sizeof(*map)); + if (ADD_RC_CHK(result, map)) { char newfilename[PATH_MAX]; struct dso *dso, *header_bid_dso; int anon, no_dso, vdso, android; @@ -167,7 +169,7 @@ struct map *map__new(struct machine *machine, u64 start, u64 len, if (dso == NULL) goto out_delete; - map__init(map, start, start + len, pgoff, dso); + map__init(result, start, start + len, pgoff, dso); if (anon || no_dso) { map->map_ip = map->unmap_ip = identity__map_ip; @@ -204,10 +206,10 @@ struct map *map__new(struct machine *machine, u64 start, u64 len, } dso__put(dso); } - return map; + return result; out_delete: nsinfo__put(nsi); - free(map); + RC_CHK_FREE(result); return NULL; } @@ -218,16 +220,18 @@ out_delete: */ struct map *map__new2(u64 start, struct dso *dso) { - struct map *map = calloc(1, (sizeof(*map) + - (dso->kernel ? sizeof(struct kmap) : 0))); - if (map != NULL) { + struct map *result; + RC_STRUCT(map) *map; + + map = calloc(1, sizeof(*map) + (dso->kernel ? sizeof(struct kmap) : 0)); + if (ADD_RC_CHK(result, map)) { /* * ->end will be filled after we load all the symbols */ - map__init(map, start, 0, 0, dso); + map__init(result, start, 0, 0, dso); } - return map; + return result; } bool __map__is_kernel(const struct map *map) @@ -293,19 +297,21 @@ bool map__has_symbols(const struct map *map) static void map__exit(struct map *map) { BUG_ON(refcount_read(map__refcnt(map)) != 0); - dso__zput(map->dso); + dso__zput(RC_CHK_ACCESS(map)->dso); } void map__delete(struct map *map) { map__exit(map); - free(map); + RC_CHK_FREE(map); } void map__put(struct map *map) { if (map && refcount_dec_and_test(map__refcnt(map))) map__delete(map); + else + RC_CHK_PUT(map); } void map__fixup_start(struct map *map) @@ -400,20 +406,21 @@ struct symbol *map__find_symbol_by_name(struct map *map, const char *name) struct map *map__clone(struct map *from) { - size_t size = sizeof(struct map); - struct map *map; + struct map *result; + RC_STRUCT(map) *map; + size_t size = sizeof(RC_STRUCT(map)); struct dso *dso = map__dso(from); if (dso && dso->kernel) size += sizeof(struct kmap); - map = memdup(from, size); - if (map != NULL) { + map = memdup(RC_CHK_ACCESS(from), size); + if (ADD_RC_CHK(result, map)) { refcount_set(&map->refcnt, 1); map->dso = dso__get(dso); } - return map; + return result; } size_t map__fprintf(struct map *map, FILE *fp) @@ -567,7 +574,7 @@ struct kmap *__map__kmap(struct map *map) if (!dso || !dso->kernel) return NULL; - return (struct kmap *)(map + 1); + return (struct kmap *)(&RC_CHK_ACCESS(map)[1]); } struct kmap *map__kmap(struct map *map) diff --git a/tools/perf/util/map.h b/tools/perf/util/map.h index 0760c671314d..823ab7fc0acf 100644 --- a/tools/perf/util/map.h +++ b/tools/perf/util/map.h @@ -10,12 +10,13 @@ #include #include #include +#include struct dso; struct maps; struct machine; -struct map { +DECLARE_RC_STRUCT(map) { u64 start; u64 end; bool erange_warned:1; @@ -49,72 +50,72 @@ u64 identity__map_ip(const struct map *map __maybe_unused, u64 ip); static inline struct dso *map__dso(const struct map *map) { - return map->dso; + return RC_CHK_ACCESS(map)->dso; } static inline u64 map__map_ip(const struct map *map, u64 ip) { - return map->map_ip(map, ip); + return RC_CHK_ACCESS(map)->map_ip(map, ip); } static inline u64 map__unmap_ip(const struct map *map, u64 ip) { - return map->unmap_ip(map, ip); + return RC_CHK_ACCESS(map)->unmap_ip(map, ip); } static inline void *map__map_ip_ptr(struct map *map) { - return map->map_ip; + return RC_CHK_ACCESS(map)->map_ip; } static inline void* map__unmap_ip_ptr(struct map *map) { - return map->unmap_ip; + return RC_CHK_ACCESS(map)->unmap_ip; } static inline u64 map__start(const struct map *map) { - return map->start; + return RC_CHK_ACCESS(map)->start; } static inline u64 map__end(const struct map *map) { - return map->end; + return RC_CHK_ACCESS(map)->end; } static inline u64 map__pgoff(const struct map *map) { - return map->pgoff; + return RC_CHK_ACCESS(map)->pgoff; } static inline u64 map__reloc(const struct map *map) { - return map->reloc; + return RC_CHK_ACCESS(map)->reloc; } static inline u32 map__flags(const struct map *map) { - return map->flags; + return RC_CHK_ACCESS(map)->flags; } static inline u32 map__prot(const struct map *map) { - return map->prot; + return RC_CHK_ACCESS(map)->prot; } static inline bool map__priv(const struct map *map) { - return map->priv; + return RC_CHK_ACCESS(map)->priv; } static inline refcount_t *map__refcnt(struct map *map) { - return &map->refcnt; + return &RC_CHK_ACCESS(map)->refcnt; } static inline bool map__erange_warned(struct map *map) { - return map->erange_warned; + return RC_CHK_ACCESS(map)->erange_warned; } static inline size_t map__size(const struct map *map) @@ -173,9 +174,12 @@ struct map *map__clone(struct map *map); static inline struct map *map__get(struct map *map) { - if (map) + struct map *result; + + if (RC_CHK_GET(result, map)) refcount_inc(map__refcnt(map)); - return map; + + return result; } void map__put(struct map *map); @@ -249,51 +253,51 @@ static inline int is_no_dso_memory(const char *filename) static inline void map__set_start(struct map *map, u64 start) { - map->start = start; + RC_CHK_ACCESS(map)->start = start; } static inline void map__set_end(struct map *map, u64 end) { - map->end = end; + RC_CHK_ACCESS(map)->end = end; } static inline void map__set_pgoff(struct map *map, u64 pgoff) { - map->pgoff = pgoff; + RC_CHK_ACCESS(map)->pgoff = pgoff; } static inline void map__add_pgoff(struct map *map, u64 inc) { - map->pgoff += inc; + RC_CHK_ACCESS(map)->pgoff += inc; } static inline void map__set_reloc(struct map *map, u64 reloc) { - map->reloc = reloc; + RC_CHK_ACCESS(map)->reloc = reloc; } static inline void map__set_priv(struct map *map, int priv) { - map->priv = priv; + RC_CHK_ACCESS(map)->priv = priv; } static inline void map__set_erange_warned(struct map *map, bool erange_warned) { - map->erange_warned = erange_warned; + RC_CHK_ACCESS(map)->erange_warned = erange_warned; } static inline void map__set_dso(struct map *map, struct dso *dso) { - map->dso = dso; + RC_CHK_ACCESS(map)->dso = dso; } static inline void map__set_map_ip(struct map *map, u64 (*map_ip)(const struct map *map, u64 ip)) { - map->map_ip = map_ip; + RC_CHK_ACCESS(map)->map_ip = map_ip; } static inline void map__set_unmap_ip(struct map *map, u64 (*unmap_ip)(const struct map *map, u64 rip)) { - map->unmap_ip = unmap_ip; + RC_CHK_ACCESS(map)->unmap_ip = unmap_ip; } #endif /* __PERF_MAP_H */ diff --git a/tools/perf/util/maps.c b/tools/perf/util/maps.c index df2fc8221f3c..1aeb1db58fe5 100644 --- a/tools/perf/util/maps.c +++ b/tools/perf/util/maps.c @@ -126,7 +126,7 @@ void maps__remove(struct maps *maps, struct map *map) RC_CHK_ACCESS(maps)->last_search_by_name = NULL; rb_node = maps__find_node(maps, map); - assert(rb_node->map == map); + assert(rb_node->RC_CHK_ACCESS(map) == RC_CHK_ACCESS(map)); __maps__remove(maps, rb_node); if (maps__maps_by_name(maps)) __maps__free_maps_by_name(maps); @@ -420,7 +420,7 @@ struct map_rb_node *maps__find_node(struct maps *maps, struct map *map) struct map_rb_node *rb_node; maps__for_each_entry(maps, rb_node) { - if (rb_node->map == map) + if (rb_node->RC_CHK_ACCESS(map) == RC_CHK_ACCESS(map)) return rb_node; } return NULL; diff --git a/tools/perf/util/symbol.c b/tools/perf/util/symbol.c index 35d860f95b18..6b9c55784b56 100644 --- a/tools/perf/util/symbol.c +++ b/tools/perf/util/symbol.c @@ -865,7 +865,7 @@ static int maps__split_kallsyms(struct maps *kmaps, struct dso *dso, u64 delta, *module++ = '\0'; curr_map_dso = map__dso(curr_map); if (strcmp(curr_map_dso->short_name, module)) { - if (curr_map != initial_map && + if (RC_CHK_ACCESS(curr_map) != RC_CHK_ACCESS(initial_map) && dso->kernel == DSO_SPACE__KERNEL_GUEST && machine__is_default_guest(machine)) { /* @@ -1457,7 +1457,7 @@ static int dso__load_kcore(struct dso *dso, struct map *map, list_del_init(&new_node->node); - if (new_map == replacement_map) { + if (RC_CHK_ACCESS(new_map) == RC_CHK_ACCESS(replacement_map)) { map__set_start(map, map__start(new_map)); map__set_end(map, map__end(new_map)); map__set_pgoff(map, map__pgoff(new_map)); -- cgit v1.2.3-58-ga151 From 686c511866b4634734be9d6e827e4e55b877d35e Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 19 Apr 2023 13:47:03 -0300 Subject: perf build: Test the refcnt check build Make sure we test build the currently added REFCNT_CHECKING infrastructure. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/make | 2 ++ 1 file changed, 2 insertions(+) (limited to 'tools') diff --git a/tools/perf/tests/make b/tools/perf/tests/make index 96896d498641..d75876126631 100644 --- a/tools/perf/tests/make +++ b/tools/perf/tests/make @@ -95,6 +95,7 @@ make_no_syscall_tbl := NO_SYSCALL_TABLE=1 make_with_clangllvm := LIBCLANGLLVM=1 make_no_libpfm4 := NO_LIBPFM4=1 make_with_gtk2 := GTK2=1 +make_refcnt_check := EXTRA_CFLAGS="-DREFCNT_CHECKING=1" make_tags := tags make_cscope := cscope make_help := help @@ -159,6 +160,7 @@ run += make_with_babeltrace run += make_with_coresight run += make_with_clangllvm run += make_no_libpfm4 +run += make_refcnt_check run += make_help run += make_doc run += make_perf_o -- cgit v1.2.3-58-ga151 From 265b0de2f0f293f98173abb336edb63921b9c282 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 19 Apr 2023 16:30:05 -0300 Subject: perf probe: Add missing 0x prefix for addresses printed in hexadecimal To fix this confusing warning: # perf probe -l Failed to find debug information for address 798240 probe_main:prometheus_new_counter__return (on github.com/prometheus/client_golang/prometheus.NewCounter%return in /home/acme/git/prometheus-uprobes/main with counter) # As that 798240 is printed with PRIx64 but has no letters, better print the 0x prefix to disambiguate. Cc: Adrian Hunter Cc: Ian Rogers Cc: Jiri Olsa Cc: Masami Hiramatsu Cc: Namhyung Kim Link: https://lore.kernel.org/lkml/ZEBCyFu2GjTw6qOi@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/probe-finder.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/probe-finder.c b/tools/perf/util/probe-finder.c index 54b49ce85c9f..f171360b0ef4 100644 --- a/tools/perf/util/probe-finder.c +++ b/tools/perf/util/probe-finder.c @@ -1729,7 +1729,7 @@ int debuginfo__find_probe_point(struct debuginfo *dbg, u64 addr, addr += baseaddr; /* Find cu die */ if (!dwarf_addrdie(dbg->dbg, (Dwarf_Addr)addr, &cudie)) { - pr_warning("Failed to find debug information for address %" PRIx64 "\n", + pr_warning("Failed to find debug information for address %#" PRIx64 "\n", addr); ret = -EINVAL; goto end; -- cgit v1.2.3-58-ga151 From edd4cab2d492daa5e45bd45e44084a2b9880f224 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Wed, 19 Apr 2023 20:04:30 -0700 Subject: perf test: Fix maps use after put Fix a use after put reference count issue. maps is copied from leader, but the leader is put on line 79 and then maps is used to read the reference count below - so a use after put, with the put of maps happening within thread__put. Fix by reversing the order of puts so that the leader is put last. To explain the reference count checker, I wrote this up as a little example here: https://perf.wiki.kernel.org/index.php/Reference_Count_Checking Note, the bug was introduced by the committer and wasn't present in the original reference count patch set. Committer notes: Yes, the bug predated your patch and is detected by the reference count checking you contributed. This was just part of splitting up your series into smaller chunks, in this case either we fix the problem detected while developing this reference counting infrastructure before the patch introducing REFCNT_CHECKING or fix it later after the merged infrastructure, when built with EXTRA_CFLAGS="-DREFCNT_CHECKING=1" detects it when running 'perf test', which is what this patch does. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Link: http://lore.kernel.org/lkml/20230420030430.489243-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/thread-maps-share.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'tools') diff --git a/tools/perf/tests/thread-maps-share.c b/tools/perf/tests/thread-maps-share.c index 75ce8aedfc78..858e725318a9 100644 --- a/tools/perf/tests/thread-maps-share.c +++ b/tools/perf/tests/thread-maps-share.c @@ -76,16 +76,16 @@ static int test__thread_maps_share(struct test_suite *test __maybe_unused, int s TEST_ASSERT_VAL("maps don't match", RC_CHK_ACCESS(other_maps) == RC_CHK_ACCESS(other_leader->maps)); /* release thread group */ - thread__put(leader); + thread__put(t3); TEST_ASSERT_EQUAL("wrong refcnt", refcount_read(maps__refcnt(maps)), 3); - thread__put(t1); + thread__put(t2); TEST_ASSERT_EQUAL("wrong refcnt", refcount_read(maps__refcnt(maps)), 2); - thread__put(t2); + thread__put(t1); TEST_ASSERT_EQUAL("wrong refcnt", refcount_read(maps__refcnt(maps)), 1); - thread__put(t3); + thread__put(leader); /* release other group */ thread__put(other_leader); -- cgit v1.2.3-58-ga151 From 9be6ab181b7b8d6114e225ae3c7c01bb6380cf8a Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 20 Apr 2023 10:18:12 -0700 Subject: libperf rc_check: Enable implicitly with sanitizers If using leak sanitizer then implicitly enable reference count checking. Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230420171812.561603-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/lib/perf/include/internal/rc_check.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'tools') diff --git a/tools/lib/perf/include/internal/rc_check.h b/tools/lib/perf/include/internal/rc_check.h index c0626d8beb59..d5d771ccdc7b 100644 --- a/tools/lib/perf/include/internal/rc_check.h +++ b/tools/lib/perf/include/internal/rc_check.h @@ -5,6 +5,14 @@ #include #include +/* + * Enable reference count checking implicitly with leak checking, which is + * integrated into address sanitizer. + */ +#if defined(LEAK_SANITIZER) || defined(ADDRESS_SANITIZER) +#define REFCNT_CHECKING 1 +#endif + /* * Shared reference count checking macros. * -- cgit v1.2.3-58-ga151 From ce1d3bc2733224573600e5564203345caea814eb Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Thu, 20 Apr 2023 15:54:11 -0300 Subject: perf evsel: Introduce evsel__name_is() method to check if the evsel name is equal to a given string This makes the logic a bit clear by avoiding the !strcmp() pattern and also a way to intercept the pointer if we need to do extra validation on it or to do lazy setting of evsel->name via evsel__name(evsel). Reviewed-by: "Liang, Kan" Cc: Adrian Hunter Cc: Ian Rogers Cc: Jiri Olsa Cc: Namhyung Kim Link: https://lore.kernel.org/lkml/ZEGLM8VehJbS0gP2@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/arm64/util/kvm-stat.c | 4 ++-- tools/perf/arch/powerpc/util/kvm-stat.c | 4 ++-- tools/perf/arch/x86/util/kvm-stat.c | 8 ++++---- tools/perf/builtin-kvm.c | 6 +++--- tools/perf/builtin-stat.c | 2 +- tools/perf/tests/expand-cgroup.c | 2 +- tools/perf/tests/parse-events.c | 12 ++++++------ tools/perf/tests/parse-metric.c | 2 +- tools/perf/tests/pmu-events.c | 2 +- tools/perf/util/evlist.c | 4 ++-- tools/perf/util/evsel.c | 7 ++++++- tools/perf/util/evsel.h | 1 + tools/perf/util/sort.c | 2 +- 13 files changed, 31 insertions(+), 25 deletions(-) (limited to 'tools') diff --git a/tools/perf/arch/arm64/util/kvm-stat.c b/tools/perf/arch/arm64/util/kvm-stat.c index 72ca9bb45804..6611aa21cba9 100644 --- a/tools/perf/arch/arm64/util/kvm-stat.c +++ b/tools/perf/arch/arm64/util/kvm-stat.c @@ -44,14 +44,14 @@ static bool event_begin(struct evsel *evsel, struct perf_sample *sample __maybe_unused, struct event_key *key __maybe_unused) { - return !strcmp(evsel->name, kvm_entry_trace); + return evsel__name_is(evsel, kvm_entry_trace); } static bool event_end(struct evsel *evsel, struct perf_sample *sample, struct event_key *key) { - if (!strcmp(evsel->name, kvm_exit_trace)) { + if (evsel__name_is(evsel, kvm_exit_trace)) { event_get_key(evsel, sample, key); return true; } diff --git a/tools/perf/arch/powerpc/util/kvm-stat.c b/tools/perf/arch/powerpc/util/kvm-stat.c index d04a08c9fd19..ea1220d66b67 100644 --- a/tools/perf/arch/powerpc/util/kvm-stat.c +++ b/tools/perf/arch/powerpc/util/kvm-stat.c @@ -60,13 +60,13 @@ static bool hcall_event_end(struct evsel *evsel, struct perf_sample *sample __maybe_unused, struct event_key *key __maybe_unused) { - return (!strcmp(evsel->name, kvm_events_tp[3])); + return (evsel__name_is(evsel, kvm_events_tp[3])); } static bool hcall_event_begin(struct evsel *evsel, struct perf_sample *sample, struct event_key *key) { - if (!strcmp(evsel->name, kvm_events_tp[2])) { + if (evsel__name_is(evsel, kvm_events_tp[2])) { hcall_event_get_key(evsel, sample, key); return true; } diff --git a/tools/perf/arch/x86/util/kvm-stat.c b/tools/perf/arch/x86/util/kvm-stat.c index ef513def03ba..424716518b75 100644 --- a/tools/perf/arch/x86/util/kvm-stat.c +++ b/tools/perf/arch/x86/util/kvm-stat.c @@ -46,7 +46,7 @@ static bool mmio_event_begin(struct evsel *evsel, return true; /* MMIO write begin event in kernel. */ - if (!strcmp(evsel->name, "kvm:kvm_mmio") && + if (evsel__name_is(evsel, "kvm:kvm_mmio") && evsel__intval(evsel, sample, "type") == KVM_TRACE_MMIO_WRITE) { mmio_event_get_key(evsel, sample, key); return true; @@ -63,7 +63,7 @@ static bool mmio_event_end(struct evsel *evsel, struct perf_sample *sample, return true; /* MMIO read end event in kernel.*/ - if (!strcmp(evsel->name, "kvm:kvm_mmio") && + if (evsel__name_is(evsel, "kvm:kvm_mmio") && evsel__intval(evsel, sample, "type") == KVM_TRACE_MMIO_READ) { mmio_event_get_key(evsel, sample, key); return true; @@ -101,7 +101,7 @@ static bool ioport_event_begin(struct evsel *evsel, struct perf_sample *sample, struct event_key *key) { - if (!strcmp(evsel->name, "kvm:kvm_pio")) { + if (evsel__name_is(evsel, "kvm:kvm_pio")) { ioport_event_get_key(evsel, sample, key); return true; } @@ -145,7 +145,7 @@ static bool msr_event_begin(struct evsel *evsel, struct perf_sample *sample, struct event_key *key) { - if (!strcmp(evsel->name, "kvm:kvm_msr")) { + if (evsel__name_is(evsel, "kvm:kvm_msr")) { msr_event_get_key(evsel, sample, key); return true; } diff --git a/tools/perf/builtin-kvm.c b/tools/perf/builtin-kvm.c index 747d19336340..71165036e4ca 100644 --- a/tools/perf/builtin-kvm.c +++ b/tools/perf/builtin-kvm.c @@ -625,7 +625,7 @@ void exit_event_get_key(struct evsel *evsel, bool kvm_exit_event(struct evsel *evsel) { - return !strcmp(evsel->name, kvm_exit_trace); + return evsel__name_is(evsel, kvm_exit_trace); } bool exit_event_begin(struct evsel *evsel, @@ -641,7 +641,7 @@ bool exit_event_begin(struct evsel *evsel, bool kvm_entry_event(struct evsel *evsel) { - return !strcmp(evsel->name, kvm_entry_trace); + return evsel__name_is(evsel, kvm_entry_trace); } bool exit_event_end(struct evsel *evsel, @@ -878,7 +878,7 @@ static bool is_child_event(struct perf_kvm_stat *kvm, return false; for (; child_ops->name; child_ops++) { - if (!strcmp(evsel->name, child_ops->name)) { + if (evsel__name_is(evsel, child_ops->name)) { child_ops->get_key(evsel, sample, key); return true; } diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index d3cbee7460fc..efda63f6bf32 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -2170,7 +2170,7 @@ static void setup_system_wide(int forks) evlist__for_each_entry(evsel_list, counter) { if (!counter->core.requires_cpu && - strcmp(counter->name, "duration_time")) { + !evsel__name_is(counter, "duration_time")) { return; } } diff --git a/tools/perf/tests/expand-cgroup.c b/tools/perf/tests/expand-cgroup.c index ec340880a848..9c1a1f18db75 100644 --- a/tools/perf/tests/expand-cgroup.c +++ b/tools/perf/tests/expand-cgroup.c @@ -61,7 +61,7 @@ static int test_expand_events(struct evlist *evlist, i = 0; evlist__for_each_entry(evlist, evsel) { - if (strcmp(evsel->name, ev_name[i % nr_events])) { + if (!evsel__name_is(evsel, ev_name[i % nr_events])) { pr_debug("event name doesn't match:\n"); pr_debug(" evsel[%d]: %s\n expected: %s\n", i, evsel->name, ev_name[i % nr_events]); diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-events.c index 6eb1400443ad..8068cfd89b84 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -1401,7 +1401,7 @@ static int test__checkevent_config_symbol(struct evlist *evlist) { struct evsel *evsel = evlist__first(evlist); - TEST_ASSERT_VAL("wrong name setting", strcmp(evsel->name, "insn") == 0); + TEST_ASSERT_VAL("wrong name setting", evsel__name_is(evsel, "insn")); return TEST_OK; } @@ -1409,7 +1409,7 @@ static int test__checkevent_config_raw(struct evlist *evlist) { struct evsel *evsel = evlist__first(evlist); - TEST_ASSERT_VAL("wrong name setting", strcmp(evsel->name, "rawpmu") == 0); + TEST_ASSERT_VAL("wrong name setting", evsel__name_is(evsel, "rawpmu")); return TEST_OK; } @@ -1417,7 +1417,7 @@ static int test__checkevent_config_num(struct evlist *evlist) { struct evsel *evsel = evlist__first(evlist); - TEST_ASSERT_VAL("wrong name setting", strcmp(evsel->name, "numpmu") == 0); + TEST_ASSERT_VAL("wrong name setting", evsel__name_is(evsel, "numpmu")); return TEST_OK; } @@ -1425,7 +1425,7 @@ static int test__checkevent_config_cache(struct evlist *evlist) { struct evsel *evsel = evlist__first(evlist); - TEST_ASSERT_VAL("wrong name setting", strcmp(evsel->name, "cachepmu") == 0); + TEST_ASSERT_VAL("wrong name setting", evsel__name_is(evsel, "cachepmu")); return TEST_OK; } @@ -1438,7 +1438,7 @@ static int test__intel_pt(struct evlist *evlist) { struct evsel *evsel = evlist__first(evlist); - TEST_ASSERT_VAL("wrong name setting", strcmp(evsel->name, "intel_pt//u") == 0); + TEST_ASSERT_VAL("wrong name setting", evsel__name_is(evsel, "intel_pt//u")); return TEST_OK; } @@ -1446,7 +1446,7 @@ static int test__checkevent_complex_name(struct evlist *evlist) { struct evsel *evsel = evlist__first(evlist); - TEST_ASSERT_VAL("wrong complex name parsing", strcmp(evsel->name, "COMPLEX_CYCLES_NAME:orig=cycles,desc=chip-clock-ticks") == 0); + TEST_ASSERT_VAL("wrong complex name parsing", evsel__name_is(evsel, "COMPLEX_CYCLES_NAME:orig=cycles,desc=chip-clock-ticks")); return TEST_OK; } diff --git a/tools/perf/tests/parse-metric.c b/tools/perf/tests/parse-metric.c index c43b056f9fa3..1185b79e6274 100644 --- a/tools/perf/tests/parse-metric.c +++ b/tools/perf/tests/parse-metric.c @@ -39,7 +39,7 @@ static void load_runtime_stat(struct evlist *evlist, struct value *vals) evlist__for_each_entry(evlist, evsel) { count = find_value(evsel->name, vals); evsel->stats->aggr->counts.val = count; - if (!strcmp(evsel->name, "duration_time")) + if (evsel__name_is(evsel, "duration_time")) update_stats(&walltime_nsecs_stats, count); } } diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c index 7f8e86452527..1dff863b9711 100644 --- a/tools/perf/tests/pmu-events.c +++ b/tools/perf/tests/pmu-events.c @@ -866,7 +866,7 @@ static int test__parsing_callback(const struct pmu_metric *pm, evlist__alloc_aggr_stats(evlist, 1); evlist__for_each_entry(evlist, evsel) { evsel->stats->aggr->counts.val = k; - if (!strcmp(evsel->name, "duration_time")) + if (evsel__name_is(evsel, "duration_time")) update_stats(&walltime_nsecs_stats, k); k++; } diff --git a/tools/perf/util/evlist.c b/tools/perf/util/evlist.c index 2260e27adf44..a0504316b06f 100644 --- a/tools/perf/util/evlist.c +++ b/tools/perf/util/evlist.c @@ -467,7 +467,7 @@ static int evsel__strcmp(struct evsel *pos, char *evsel_name) return 0; if (evsel__is_dummy_event(pos)) return 1; - return strcmp(pos->name, evsel_name); + return !evsel__name_is(pos, evsel_name); } static int evlist__is_enabled(struct evlist *evlist) @@ -1706,7 +1706,7 @@ struct evsel *evlist__find_evsel_by_str(struct evlist *evlist, const char *str) evlist__for_each_entry(evlist, evsel) { if (!evsel->name) continue; - if (strcmp(str, evsel->name) == 0) + if (evsel__name_is(evsel, str)) return evsel; } diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index a85a987128aa..356c07f03be6 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -821,6 +821,11 @@ out_unknown: return "unknown"; } +bool evsel__name_is(struct evsel *evsel, const char *name) +{ + return !strcmp(evsel__name(evsel), name); +} + const char *evsel__group_pmu_name(const struct evsel *evsel) { const struct evsel *leader; @@ -1146,7 +1151,7 @@ static void evsel__set_default_freq_period(struct record_opts *opts, static bool evsel__is_offcpu_event(struct evsel *evsel) { - return evsel__is_bpf_output(evsel) && !strcmp(evsel->name, OFFCPU_EVENT); + return evsel__is_bpf_output(evsel) && evsel__name_is(evsel, OFFCPU_EVENT); } /* diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h index 68072ec655ce..1e5d640e4a9b 100644 --- a/tools/perf/util/evsel.h +++ b/tools/perf/util/evsel.h @@ -282,6 +282,7 @@ int arch_evsel__hw_name(struct evsel *evsel, char *bf, size_t size); int __evsel__hw_cache_type_op_res_name(u8 type, u8 op, u8 result, char *bf, size_t size); const char *evsel__name(struct evsel *evsel); +bool evsel__name_is(struct evsel *evsel, const char *name); const char *evsel__group_pmu_name(const struct evsel *evsel); const char *evsel__metric_id(const struct evsel *evsel); diff --git a/tools/perf/util/sort.c b/tools/perf/util/sort.c index 31b1cd0935e2..650cd8df4041 100644 --- a/tools/perf/util/sort.c +++ b/tools/perf/util/sort.c @@ -2893,7 +2893,7 @@ static struct evsel *find_evsel(struct evlist *evlist, char *event_name) full_name = !!strchr(event_name, ':'); evlist__for_each_entry(evlist, pos) { /* case 2 */ - if (full_name && !strcmp(pos->name, event_name)) + if (full_name && evsel__name_is(pos, event_name)) return pos; /* case 3 */ if (!full_name && strstr(pos->name, event_name)) { -- cgit v1.2.3-58-ga151 From 449067f3fc9f340da54e383738286881e6634d0b Mon Sep 17 00:00:00 2001 From: James Clark Date: Mon, 24 Apr 2023 14:47:41 +0100 Subject: perf cs-etm: Fix timeless decode mode detection In this context, timeless refers to the trace data rather than the perf event data. But when detecting whether there are timestamps in the trace data or not, the presence of a timestamp flag on any perf event is used. Since commit f42c0ce573df ("perf record: Always get text_poke events with --kcore option") timestamps were added to a tracking event when --kcore is used which breaks this detection mechanism. Fix it by detecting if trace timestamps exist by looking at the ETM config flags. This would have always been a more accurate way of doing it anyway. This fixes the following error message when using --kcore with Coresight: $ perf record --kcore -e cs_etm// --per-thread $ perf report The perf.data/data data has no samples! Fixes: f42c0ce573df79d1 ("perf record: Always get text_poke events with --kcore option") Reported-by: Yang Shi Signed-off-by: James Clark Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: John Garry Cc: Leo Yan Cc: Mark Rutland Cc: Mathieu Poirier Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Suzuki Poulouse Cc: Will Deacon Cc: coresight@lists.linaro.org Cc: denik@google.com Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/lkml/CAHbLzkrJQTrYBtPkf=jf3OpQ-yBcJe7XkvQstX9j2frz4WF-SQ@mail.gmail.com/ Link: https://lore.kernel.org/r/20230424134748.228137-2-james.clark@arm.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/cs-etm.c | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 8dd81ddd9e4e..50593289d53c 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -2684,26 +2684,29 @@ static int cs_etm__process_auxtrace_event(struct perf_session *session, return 0; } -static bool cs_etm__is_timeless_decoding(struct cs_etm_auxtrace *etm) +static int cs_etm__setup_timeless_decoding(struct cs_etm_auxtrace *etm) { struct evsel *evsel; struct evlist *evlist = etm->session->evlist; - bool timeless_decoding = true; /* Override timeless mode with user input from --itrace=Z */ - if (etm->synth_opts.timeless_decoding) - return true; + if (etm->synth_opts.timeless_decoding) { + etm->timeless_decoding = true; + return 0; + } /* - * Circle through the list of event and complain if we find one - * with the time bit set. + * Find the cs_etm evsel and look at what its timestamp setting was */ - evlist__for_each_entry(evlist, evsel) { - if ((evsel->core.attr.sample_type & PERF_SAMPLE_TIME)) - timeless_decoding = false; - } + evlist__for_each_entry(evlist, evsel) + if (cs_etm__evsel_is_auxtrace(etm->session, evsel)) { + etm->timeless_decoding = + !(evsel->core.attr.config & BIT(ETM_OPT_TS)); + return 0; + } - return timeless_decoding; + pr_err("CS ETM: Couldn't find ETM evsel\n"); + return -EINVAL; } /* @@ -3155,7 +3158,6 @@ int cs_etm__process_auxtrace_info_full(union perf_event *event, etm->snapshot_mode = (ptr[CS_ETM_SNAPSHOT] != 0); etm->metadata = metadata; etm->auxtrace_type = auxtrace_info->type; - etm->timeless_decoding = cs_etm__is_timeless_decoding(etm); /* Use virtual timestamps if all ETMs report ts_source = 1 */ etm->has_virtual_ts = cs_etm__has_virtual_ts(metadata, num_cpu); @@ -3172,6 +3174,10 @@ int cs_etm__process_auxtrace_info_full(union perf_event *event, etm->auxtrace.evsel_is_auxtrace = cs_etm__evsel_is_auxtrace; session->auxtrace = &etm->auxtrace; + err = cs_etm__setup_timeless_decoding(etm); + if (err) + return err; + etm->unknown_thread = thread__new(999999999, 999999999); if (!etm->unknown_thread) { err = -ENOMEM; -- cgit v1.2.3-58-ga151 From 6593f019c26cbdee3432f28a3d1ffac9605cf562 Mon Sep 17 00:00:00 2001 From: James Clark Date: Mon, 24 Apr 2023 14:47:42 +0100 Subject: perf tools: Add util function for overriding user set config values There is some duplicated code to only override config values if they haven't already been set by the user so make a util function for this. Signed-off-by: James Clark Acked-by: Adrian Hunter Cc: Alexander Shishkin Cc: Denis Nikitin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: John Garry Cc: Leo Yan Cc: Mark Rutland Cc: Mathieu Poirier Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Suzuki Poulouse Cc: Will Deacon Cc: Yang Shi Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230424134748.228137-3-james.clark@arm.com [ Moved evsel__set_config_if_unset() to util/pmu.c to avoid dragging stuff into the python binding ] Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/arm64/util/arm-spe.c | 26 ++------------------------ tools/perf/arch/x86/util/intel-pt.c | 22 ++-------------------- tools/perf/util/evsel.h | 3 +++ tools/perf/util/pmu.c | 30 ++++++++++++++++++++++++++++++ 4 files changed, 37 insertions(+), 44 deletions(-) (limited to 'tools') diff --git a/tools/perf/arch/arm64/util/arm-spe.c b/tools/perf/arch/arm64/util/arm-spe.c index ef497a29e814..3b1676ff03f9 100644 --- a/tools/perf/arch/arm64/util/arm-spe.c +++ b/tools/perf/arch/arm64/util/arm-spe.c @@ -36,29 +36,6 @@ struct arm_spe_recording { bool *wrapped; }; -static void arm_spe_set_timestamp(struct auxtrace_record *itr, - struct evsel *evsel) -{ - struct arm_spe_recording *ptr; - struct perf_pmu *arm_spe_pmu; - struct evsel_config_term *term = evsel__get_config_term(evsel, CFG_CHG); - u64 user_bits = 0, bit; - - ptr = container_of(itr, struct arm_spe_recording, itr); - arm_spe_pmu = ptr->arm_spe_pmu; - - if (term) - user_bits = term->val.cfg_chg; - - bit = perf_pmu__format_bits(&arm_spe_pmu->format, "ts_enable"); - - /* Skip if user has set it */ - if (bit & user_bits) - return; - - evsel->core.attr.config |= bit; -} - static size_t arm_spe_info_priv_size(struct auxtrace_record *itr __maybe_unused, struct evlist *evlist __maybe_unused) @@ -238,7 +215,8 @@ static int arm_spe_recording_options(struct auxtrace_record *itr, */ if (!perf_cpu_map__empty(cpus)) { evsel__set_sample_bit(arm_spe_evsel, CPU); - arm_spe_set_timestamp(itr, arm_spe_evsel); + evsel__set_config_if_unset(arm_spe_pmu, arm_spe_evsel, + "ts_enable", 1); } /* diff --git a/tools/perf/arch/x86/util/intel-pt.c b/tools/perf/arch/x86/util/intel-pt.c index 2cff11de9d8a..17336da08b58 100644 --- a/tools/perf/arch/x86/util/intel-pt.c +++ b/tools/perf/arch/x86/util/intel-pt.c @@ -576,25 +576,6 @@ out: return err; } -static void intel_pt_config_sample_mode(struct perf_pmu *intel_pt_pmu, - struct evsel *evsel) -{ - u64 user_bits = 0, bits; - struct evsel_config_term *term = evsel__get_config_term(evsel, CFG_CHG); - - if (term) - user_bits = term->val.cfg_chg; - - bits = perf_pmu__format_bits(&intel_pt_pmu->format, "psb_period"); - - /* Did user change psb_period */ - if (bits & user_bits) - return; - - /* Set psb_period to 0 */ - evsel->core.attr.config &= ~bits; -} - static void intel_pt_min_max_sample_sz(struct evlist *evlist, size_t *min_sz, size_t *max_sz) { @@ -686,7 +667,8 @@ static int intel_pt_recording_options(struct auxtrace_record *itr, return 0; if (opts->auxtrace_sample_mode) - intel_pt_config_sample_mode(intel_pt_pmu, intel_pt_evsel); + evsel__set_config_if_unset(intel_pt_pmu, intel_pt_evsel, + "psb_period", 0); err = intel_pt_validate_config(intel_pt_pmu, intel_pt_evsel); if (err) diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h index 1e5d640e4a9b..35805dcdb1b9 100644 --- a/tools/perf/util/evsel.h +++ b/tools/perf/util/evsel.h @@ -530,4 +530,7 @@ bool arch_evsel__must_be_in_group(const struct evsel *evsel); ((((src) >> (pos)) & ((1ull << (size)) - 1)) << (63 - ((pos) + (size) - 1))) u64 evsel__bitfield_swap_branch_flags(u64 value); +void evsel__set_config_if_unset(struct perf_pmu *pmu, struct evsel *evsel, + const char *config_name, u64 val); + #endif /* __PERF_EVSEL_H */ diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 65d0eb9a740a..ad209c88a124 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -33,6 +33,7 @@ #include "strbuf.h" #include "fncache.h" #include "pmu-hybrid.h" +#include "util/evsel_config.h" struct perf_pmu perf_pmu__fake; @@ -1056,6 +1057,35 @@ bool evsel__is_aux_event(const struct evsel *evsel) return pmu && pmu->auxtrace; } +/* + * Set @config_name to @val as long as the user hasn't already set or cleared it + * by passing a config term on the command line. + * + * @val is the value to put into the bits specified by @config_name rather than + * the bit pattern. It is shifted into position by this function, so to set + * something to true, pass 1 for val rather than a pre shifted value. + */ +#define field_prep(_mask, _val) (((_val) << (ffsll(_mask) - 1)) & (_mask)) +void evsel__set_config_if_unset(struct perf_pmu *pmu, struct evsel *evsel, + const char *config_name, u64 val) +{ + u64 user_bits = 0, bits; + struct evsel_config_term *term = evsel__get_config_term(evsel, CFG_CHG); + + if (term) + user_bits = term->val.cfg_chg; + + bits = perf_pmu__format_bits(&pmu->format, config_name); + + /* Do nothing if the user changed the value */ + if (bits & user_bits) + return; + + /* Otherwise replace it */ + evsel->core.attr.config &= ~bits; + evsel->core.attr.config |= field_prep(bits, val); +} + struct perf_pmu *perf_pmu__find(const char *name) { struct perf_pmu *pmu; -- cgit v1.2.3-58-ga151 From 3963d84b1bf0af98f604c85436076a1eb46373f3 Mon Sep 17 00:00:00 2001 From: James Clark Date: Mon, 24 Apr 2023 14:47:43 +0100 Subject: perf cs-etm: Don't test full_auxtrace because it's always set There is no path in cs-etm where this isn't true so it doesn't need to be tested. Also re-order the beginning of cs_etm_recording_options() so that nothing is done until the early exit is passed. Signed-off-by: James Clark Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Denis Nikitin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: John Garry Cc: Leo Yan Cc: Mark Rutland Cc: Mathieu Poirier Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Suzuki Poulouse Cc: Will Deacon Cc: Yang Shi Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230424134748.228137-4-james.clark@arm.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/arm/util/cs-etm.c | 56 +++++++++++++++++---------------------- 1 file changed, 25 insertions(+), 31 deletions(-) (limited to 'tools') diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c index e02a9bfc3d42..f9b9ebf7fffc 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -319,13 +319,6 @@ static int cs_etm_recording_options(struct auxtrace_record *itr, bool privileged = perf_event_paranoid_check(-1); int err = 0; - ptr->evlist = evlist; - ptr->snapshot_mode = opts->auxtrace_snapshot_mode; - - if (!record_opts__no_switch_events(opts) && - perf_can_record_switch_events()) - opts->record_switch_events = true; - evlist__for_each_entry(evlist, evsel) { if (evsel->core.attr.type == cs_etm_pmu->type) { if (cs_etm_evsel) { @@ -333,11 +326,7 @@ static int cs_etm_recording_options(struct auxtrace_record *itr, CORESIGHT_ETM_PMU_NAME); return -EINVAL; } - evsel->core.attr.freq = 0; - evsel->core.attr.sample_period = 1; - evsel->needs_auxtrace_mmap = true; cs_etm_evsel = evsel; - opts->full_auxtrace = true; } } @@ -345,6 +334,18 @@ static int cs_etm_recording_options(struct auxtrace_record *itr, if (!cs_etm_evsel) return 0; + ptr->evlist = evlist; + ptr->snapshot_mode = opts->auxtrace_snapshot_mode; + + if (!record_opts__no_switch_events(opts) && + perf_can_record_switch_events()) + opts->record_switch_events = true; + + cs_etm_evsel->core.attr.freq = 0; + cs_etm_evsel->core.attr.sample_period = 1; + cs_etm_evsel->needs_auxtrace_mmap = true; + opts->full_auxtrace = true; + ret = cs_etm_set_sink_attr(cs_etm_pmu, cs_etm_evsel); if (ret) return ret; @@ -414,8 +415,8 @@ static int cs_etm_recording_options(struct auxtrace_record *itr, } } - /* We are in full trace mode but '-m,xyz' wasn't specified */ - if (opts->full_auxtrace && !opts->auxtrace_mmap_pages) { + /* Buffer sizes weren't specified with '-m,xyz' so give some defaults */ + if (!opts->auxtrace_mmap_pages) { if (privileged) { opts->auxtrace_mmap_pages = MiB(4) / page_size; } else { @@ -423,7 +424,6 @@ static int cs_etm_recording_options(struct auxtrace_record *itr, if (opts->mmap_pages == UINT_MAX) opts->mmap_pages = KiB(256) / page_size; } - } if (opts->auxtrace_snapshot_mode) @@ -454,23 +454,17 @@ static int cs_etm_recording_options(struct auxtrace_record *itr, } /* Add dummy event to keep tracking */ - if (opts->full_auxtrace) { - struct evsel *tracking_evsel; - - err = parse_event(evlist, "dummy:u"); - if (err) - goto out; - - tracking_evsel = evlist__last(evlist); - evlist__set_tracking_event(evlist, tracking_evsel); - - tracking_evsel->core.attr.freq = 0; - tracking_evsel->core.attr.sample_period = 1; - - /* In per-cpu case, always need the time of mmap events etc */ - if (!perf_cpu_map__empty(cpus)) - evsel__set_sample_bit(tracking_evsel, TIME); - } + err = parse_event(evlist, "dummy:u"); + if (err) + goto out; + evsel = evlist__last(evlist); + evlist__set_tracking_event(evlist, evsel); + evsel->core.attr.freq = 0; + evsel->core.attr.sample_period = 1; + + /* In per-cpu case, always need the time of mmap events etc */ + if (!perf_cpu_map__empty(cpus)) + evsel__set_sample_bit(evsel, TIME); out: return err; -- cgit v1.2.3-58-ga151 From 35c51f83dd1ed5db9ddf90e90caf5cb2aa608a35 Mon Sep 17 00:00:00 2001 From: James Clark Date: Mon, 24 Apr 2023 14:47:44 +0100 Subject: perf cs-etm: Validate options after applying them Currently the cs_etm_set_option() function both validates and applies the config options. Because it's only called when they are added automatically, there are some paths where the user can apply the option on the command line and skip the validation. By moving it to the end it covers both cases. Also, options don't need to be re-applied anyway, Perf handles parsing and applying the config terms automatically. Signed-off-by: James Clark Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Denis Nikitin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: John Garry Cc: Leo Yan Cc: Mark Rutland Cc: Mathieu Poirier Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Suzuki Poulouse Cc: Will Deacon Cc: Yang Shi Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230424134748.228137-5-james.clark@arm.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/arm/util/cs-etm.c | 152 +++++++++++++++++--------------------- 1 file changed, 68 insertions(+), 84 deletions(-) (limited to 'tools') diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c index f9b9ebf7fffc..af0a2400c655 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -69,21 +69,29 @@ static const char * const metadata_ete_ro[] = { static bool cs_etm_is_etmv4(struct auxtrace_record *itr, int cpu); static bool cs_etm_is_ete(struct auxtrace_record *itr, int cpu); -static int cs_etm_set_context_id(struct auxtrace_record *itr, - struct evsel *evsel, int cpu) +static int cs_etm_validate_context_id(struct auxtrace_record *itr, + struct evsel *evsel, int cpu) { - struct cs_etm_recording *ptr; - struct perf_pmu *cs_etm_pmu; + struct cs_etm_recording *ptr = + container_of(itr, struct cs_etm_recording, itr); + struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu; char path[PATH_MAX]; - int err = -EINVAL; + int err; u32 val; - u64 contextid; + u64 contextid = + evsel->core.attr.config & + (perf_pmu__format_bits(&cs_etm_pmu->format, "contextid1") | + perf_pmu__format_bits(&cs_etm_pmu->format, "contextid2")); - ptr = container_of(itr, struct cs_etm_recording, itr); - cs_etm_pmu = ptr->cs_etm_pmu; + if (!contextid) + return 0; - if (!cs_etm_is_etmv4(itr, cpu)) - goto out; + /* Not supported in etmv3 */ + if (!cs_etm_is_etmv4(itr, cpu)) { + pr_err("%s: contextid not supported in ETMv3, disable with %s/contextid=0/\n", + CORESIGHT_ETM_PMU_NAME, CORESIGHT_ETM_PMU_NAME); + return -EINVAL; + } /* Get a handle on TRCIDR2 */ snprintf(path, PATH_MAX, "cpu%d/%s", @@ -92,27 +100,13 @@ static int cs_etm_set_context_id(struct auxtrace_record *itr, /* There was a problem reading the file, bailing out */ if (err != 1) { - pr_err("%s: can't read file %s\n", - CORESIGHT_ETM_PMU_NAME, path); - goto out; + pr_err("%s: can't read file %s\n", CORESIGHT_ETM_PMU_NAME, + path); + return err; } - /* User has configured for PID tracing, respects it. */ - contextid = evsel->core.attr.config & - (BIT(ETM_OPT_CTXTID) | BIT(ETM_OPT_CTXTID2)); - - /* - * If user doesn't configure the contextid format, parse PMU format and - * enable PID tracing according to the "contextid" format bits: - * - * If bit ETM_OPT_CTXTID is set, trace CONTEXTIDR_EL1; - * If bit ETM_OPT_CTXTID2 is set, trace CONTEXTIDR_EL2. - */ - if (!contextid) - contextid = perf_pmu__format_bits(&cs_etm_pmu->format, - "contextid"); - - if (contextid & BIT(ETM_OPT_CTXTID)) { + if (contextid & + perf_pmu__format_bits(&cs_etm_pmu->format, "contextid1")) { /* * TRCIDR2.CIDSIZE, bit [9-5], indicates whether contextID * tracing is supported: @@ -122,14 +116,14 @@ static int cs_etm_set_context_id(struct auxtrace_record *itr, */ val = BMVAL(val, 5, 9); if (!val || val != 0x4) { - pr_err("%s: CONTEXTIDR_EL1 isn't supported\n", - CORESIGHT_ETM_PMU_NAME); - err = -EINVAL; - goto out; + pr_err("%s: CONTEXTIDR_EL1 isn't supported, disable with %s/contextid1=0/\n", + CORESIGHT_ETM_PMU_NAME, CORESIGHT_ETM_PMU_NAME); + return -EINVAL; } } - if (contextid & BIT(ETM_OPT_CTXTID2)) { + if (contextid & + perf_pmu__format_bits(&cs_etm_pmu->format, "contextid2")) { /* * TRCIDR2.VMIDOPT[30:29] != 0 and * TRCIDR2.VMIDSIZE[14:10] == 0b00100 (32bit virtual contextid) @@ -138,35 +132,34 @@ static int cs_etm_set_context_id(struct auxtrace_record *itr, * Any value of VMIDSIZE >= 4 (i.e, > 32bit) is fine for us. */ if (!BMVAL(val, 29, 30) || BMVAL(val, 10, 14) < 4) { - pr_err("%s: CONTEXTIDR_EL2 isn't supported\n", - CORESIGHT_ETM_PMU_NAME); - err = -EINVAL; - goto out; + pr_err("%s: CONTEXTIDR_EL2 isn't supported, disable with %s/contextid2=0/\n", + CORESIGHT_ETM_PMU_NAME, CORESIGHT_ETM_PMU_NAME); + return -EINVAL; } } - /* All good, let the kernel know */ - evsel->core.attr.config |= contextid; - err = 0; - -out: - return err; + return 0; } -static int cs_etm_set_timestamp(struct auxtrace_record *itr, - struct evsel *evsel, int cpu) +static int cs_etm_validate_timestamp(struct auxtrace_record *itr, + struct evsel *evsel, int cpu) { - struct cs_etm_recording *ptr; - struct perf_pmu *cs_etm_pmu; + struct cs_etm_recording *ptr = + container_of(itr, struct cs_etm_recording, itr); + struct perf_pmu *cs_etm_pmu = ptr->cs_etm_pmu; char path[PATH_MAX]; - int err = -EINVAL; + int err; u32 val; - ptr = container_of(itr, struct cs_etm_recording, itr); - cs_etm_pmu = ptr->cs_etm_pmu; + if (!(evsel->core.attr.config & + perf_pmu__format_bits(&cs_etm_pmu->format, "timestamp"))) + return 0; - if (!cs_etm_is_etmv4(itr, cpu)) - goto out; + if (!cs_etm_is_etmv4(itr, cpu)) { + pr_err("%s: timestamp not supported in ETMv3, disable with %s/timestamp=0/\n", + CORESIGHT_ETM_PMU_NAME, CORESIGHT_ETM_PMU_NAME); + return -EINVAL; + } /* Get a handle on TRCIRD0 */ snprintf(path, PATH_MAX, "cpu%d/%s", @@ -177,7 +170,7 @@ static int cs_etm_set_timestamp(struct auxtrace_record *itr, if (err != 1) { pr_err("%s: can't read file %s\n", CORESIGHT_ETM_PMU_NAME, path); - goto out; + return err; } /* @@ -189,24 +182,21 @@ static int cs_etm_set_timestamp(struct auxtrace_record *itr, */ val &= GENMASK(28, 24); if (!val) { - err = -EINVAL; - goto out; + return -EINVAL; } - /* All good, let the kernel know */ - evsel->core.attr.config |= (1 << ETM_OPT_TS); - err = 0; - -out: - return err; + return 0; } -#define ETM_SET_OPT_CTXTID (1 << 0) -#define ETM_SET_OPT_TS (1 << 1) -#define ETM_SET_OPT_MASK (ETM_SET_OPT_CTXTID | ETM_SET_OPT_TS) - -static int cs_etm_set_option(struct auxtrace_record *itr, - struct evsel *evsel, u32 option) +/* + * Check whether the requested timestamp and contextid options should be + * available on all requested CPUs and if not, tell the user how to override. + * The kernel will silently disable any unavailable options so a warning here + * first is better. In theory the kernel could still disable the option for + * some other reason so this is best effort only. + */ +static int cs_etm_validate_config(struct auxtrace_record *itr, + struct evsel *evsel) { int i, err = -EINVAL; struct perf_cpu_map *event_cpus = evsel->evlist->core.user_requested_cpus; @@ -220,18 +210,11 @@ static int cs_etm_set_option(struct auxtrace_record *itr, !perf_cpu_map__has(online_cpus, cpu)) continue; - if (option & BIT(ETM_OPT_CTXTID)) { - err = cs_etm_set_context_id(itr, evsel, i); - if (err) - goto out; - } - if (option & BIT(ETM_OPT_TS)) { - err = cs_etm_set_timestamp(itr, evsel, i); - if (err) - goto out; - } - if (option & ~(BIT(ETM_OPT_CTXTID) | BIT(ETM_OPT_TS))) - /* Nothing else is currently supported */ + err = cs_etm_validate_context_id(itr, evsel, i); + if (err) + goto out; + err = cs_etm_validate_timestamp(itr, evsel, i); + if (err) goto out; } @@ -447,10 +430,10 @@ static int cs_etm_recording_options(struct auxtrace_record *itr, * when a context switch happened. */ if (!perf_cpu_map__empty(cpus)) { - err = cs_etm_set_option(itr, cs_etm_evsel, - BIT(ETM_OPT_CTXTID) | BIT(ETM_OPT_TS)); - if (err) - goto out; + cs_etm_evsel->core.attr.config |= + perf_pmu__format_bits(&cs_etm_pmu->format, "timestamp"); + cs_etm_evsel->core.attr.config |= + perf_pmu__format_bits(&cs_etm_pmu->format, "contextid"); } /* Add dummy event to keep tracking */ @@ -466,6 +449,7 @@ static int cs_etm_recording_options(struct auxtrace_record *itr, if (!perf_cpu_map__empty(cpus)) evsel__set_sample_bit(evsel, TIME); + err = cs_etm_validate_config(itr, cs_etm_evsel); out: return err; } -- cgit v1.2.3-58-ga151 From 7bfc1544d91121dddd3a6e7a289b03b63c660b57 Mon Sep 17 00:00:00 2001 From: James Clark Date: Mon, 24 Apr 2023 14:47:45 +0100 Subject: perf cs-etm: Allow user to override timestamp and contextid settings Timestamps and context tracking are automatically enabled in per-core mode and it's impossible to override this. Use the new utility function to set them conditionally. Signed-off-by: James Clark Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Denis Nikitin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: John Garry Cc: Leo Yan Cc: Mark Rutland Cc: Mathieu Poirier Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Suzuki Poulouse Cc: Will Deacon Cc: Yang Shi Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230424134748.228137-6-james.clark@arm.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/arm/util/cs-etm.c | 29 +++++++++++++++++++++++------ tools/perf/arch/arm/util/pmu.c | 2 ++ tools/perf/util/cs-etm.h | 2 ++ 3 files changed, 27 insertions(+), 6 deletions(-) (limited to 'tools') diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c index af0a2400c655..77cb03e6ff87 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -324,8 +324,6 @@ static int cs_etm_recording_options(struct auxtrace_record *itr, perf_can_record_switch_events()) opts->record_switch_events = true; - cs_etm_evsel->core.attr.freq = 0; - cs_etm_evsel->core.attr.sample_period = 1; cs_etm_evsel->needs_auxtrace_mmap = true; opts->full_auxtrace = true; @@ -430,10 +428,10 @@ static int cs_etm_recording_options(struct auxtrace_record *itr, * when a context switch happened. */ if (!perf_cpu_map__empty(cpus)) { - cs_etm_evsel->core.attr.config |= - perf_pmu__format_bits(&cs_etm_pmu->format, "timestamp"); - cs_etm_evsel->core.attr.config |= - perf_pmu__format_bits(&cs_etm_pmu->format, "contextid"); + evsel__set_config_if_unset(cs_etm_pmu, cs_etm_evsel, + "timestamp", 1); + evsel__set_config_if_unset(cs_etm_pmu, cs_etm_evsel, + "contextid", 1); } /* Add dummy event to keep tracking */ @@ -914,3 +912,22 @@ struct auxtrace_record *cs_etm_record_init(int *err) out: return NULL; } + +/* + * Set a default config to enable the user changed config tracking mechanism + * (CFG_CHG and evsel__set_config_if_unset()). If no default is set then user + * changes aren't tracked. + */ +struct perf_event_attr * +cs_etm_get_default_config(struct perf_pmu *pmu __maybe_unused) +{ + struct perf_event_attr *attr; + + attr = zalloc(sizeof(struct perf_event_attr)); + if (!attr) + return NULL; + + attr->sample_period = 1; + + return attr; +} diff --git a/tools/perf/arch/arm/util/pmu.c b/tools/perf/arch/arm/util/pmu.c index 887c8addc491..860a8b42b4b5 100644 --- a/tools/perf/arch/arm/util/pmu.c +++ b/tools/perf/arch/arm/util/pmu.c @@ -12,6 +12,7 @@ #include "arm-spe.h" #include "hisi-ptt.h" #include "../../../util/pmu.h" +#include "../cs-etm.h" struct perf_event_attr *perf_pmu__get_default_config(struct perf_pmu *pmu __maybe_unused) @@ -20,6 +21,7 @@ struct perf_event_attr if (!strcmp(pmu->name, CORESIGHT_ETM_PMU_NAME)) { /* add ETM default config here */ pmu->selectable = true; + return cs_etm_get_default_config(pmu); #if defined(__aarch64__) } else if (strstarts(pmu->name, ARM_SPE_PMU_NAME)) { return arm_spe_pmu_default_config(pmu); diff --git a/tools/perf/util/cs-etm.h b/tools/perf/util/cs-etm.h index 661f029322e4..16333d35bed4 100644 --- a/tools/perf/util/cs-etm.h +++ b/tools/perf/util/cs-etm.h @@ -12,6 +12,7 @@ #include struct perf_session; +struct perf_pmu; /* * Versioning header in case things need to change in the future. That way @@ -228,6 +229,7 @@ struct cs_etm_packet_queue { int cs_etm__process_auxtrace_info(union perf_event *event, struct perf_session *session); +struct perf_event_attr *cs_etm_get_default_config(struct perf_pmu *pmu); #ifdef HAVE_CSTRACE_SUPPORT int cs_etm__get_cpu(u8 trace_chan_id, int *cpu); -- cgit v1.2.3-58-ga151 From 1764ce069bb05c630de2f108aadb66eaa470131e Mon Sep 17 00:00:00 2001 From: James Clark Date: Mon, 24 Apr 2023 14:47:46 +0100 Subject: perf cs-etm: Use bool type for boolean values Using u8 for boolean values makes the code a bit more difficult to read so be more explicit by using bool. Signed-off-by: James Clark Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Denis Nikitin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: John Garry Cc: Leo Yan Cc: Mark Rutland Cc: Mathieu Poirier Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Suzuki Poulouse Cc: Will Deacon Cc: Yang Shi Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230424134748.228137-7-james.clark@arm.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 8 ++++---- tools/perf/util/cs-etm.c | 8 ++++---- tools/perf/util/cs-etm.h | 4 ++-- 3 files changed, 10 insertions(+), 10 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h index 92a855fbe5b8..21d403f55d96 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h @@ -60,10 +60,10 @@ struct cs_etm_decoder_params { int operation; void (*packet_printer)(const char *msg); cs_etm_mem_cb_type mem_acc_cb; - u8 formatted; - u8 fsyncs; - u8 hsyncs; - u8 frame_aligned; + bool formatted; + bool fsyncs; + bool hsyncs; + bool frame_aligned; void *data; }; diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 50593289d53c..e048949bf655 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -50,10 +50,10 @@ struct cs_etm_auxtrace { struct thread *unknown_thread; struct perf_tsc_conversion tc; - u8 timeless_decoding; - u8 snapshot_mode; - u8 data_queued; - u8 has_virtual_ts; /* Virtual/Kernel timestamps in the trace. */ + bool timeless_decoding; + bool snapshot_mode; + bool data_queued; + bool has_virtual_ts; /* Virtual/Kernel timestamps in the trace. */ int num_cpu; u64 latest_kernel_timestamp; diff --git a/tools/perf/util/cs-etm.h b/tools/perf/util/cs-etm.h index 16333d35bed4..70cac0375b34 100644 --- a/tools/perf/util/cs-etm.h +++ b/tools/perf/util/cs-etm.h @@ -179,8 +179,8 @@ struct cs_etm_packet { u32 last_instr_subtype; u32 flags; u32 exception_number; - u8 last_instr_cond; - u8 last_instr_taken_branch; + bool last_instr_cond; + bool last_instr_taken_branch; u8 last_instr_size; u8 trace_chan_id; int cpu; -- cgit v1.2.3-58-ga151 From d1efa4a0a696e487f349f837f53a0db88f8f0d74 Mon Sep 17 00:00:00 2001 From: James Clark Date: Mon, 24 Apr 2023 14:47:47 +0100 Subject: perf cs-etm: Add separate decode paths for timeless and per-thread modes Timeless and per-thread are orthogonal concepts that are currently treated as if they are the same (per-thread == timeless). This breaks when you modify the command line or itrace options to something that the current logic doesn't expect. For example: # Force timeless with Z --itrace=Zi10i # Or inconsistent record options -e cs_etm/timestamp=1/ --per-thread Adding Z for decoding in per-cpu mode is particularly bad because in per-thread mode trace channel IDs are discarded and all assumed to be 0, which would mix trace from different CPUs in per-cpu mode. Although the results might not be perfect in all scenarios, if the user requests no timestamps, it should still be possible to decode in either mode. Especially if the relative times of samples in different processes aren't interesting, quite a bit of space can be saved by turning off timestamps in per-cpu mode. Signed-off-by: James Clark Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Denis Nikitin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: John Garry Cc: Leo Yan Cc: Mark Rutland Cc: Mathieu Poirier Cc: Mike Leach Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Suzuki Poulouse Cc: Will Deacon Cc: Yang Shi Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230424134748.228137-8-james.clark@arm.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/shell/test_arm_coresight.sh | 24 ++++ tools/perf/util/cs-etm.c | 162 ++++++++++++++++++++------- 2 files changed, 148 insertions(+), 38 deletions(-) (limited to 'tools') diff --git a/tools/perf/tests/shell/test_arm_coresight.sh b/tools/perf/tests/shell/test_arm_coresight.sh index 565ce525c40b..482009e17bda 100755 --- a/tools/perf/tests/shell/test_arm_coresight.sh +++ b/tools/perf/tests/shell/test_arm_coresight.sh @@ -150,6 +150,8 @@ arm_cs_etm_system_wide_test() { echo "Recording trace with system wide mode" perf record -o ${perfdata} -e cs_etm// -a -- ls > /dev/null 2>&1 + # System-wide mode should include perf samples so test for that + # instead of ls perf_script_branch_samples perf && perf_report_branch_samples perf && perf_report_instruction_samples perf @@ -182,7 +184,29 @@ arm_cs_etm_snapshot_test() { arm_cs_report "CoreSight snapshot testing" $err } +arm_cs_etm_basic_test() { + echo "Recording trace with '$*'" + perf record -o ${perfdata} "$@" -- ls > /dev/null 2>&1 + + perf_script_branch_samples ls && + perf_report_branch_samples ls && + perf_report_instruction_samples ls + + err=$? + arm_cs_report "CoreSight basic testing with '$*'" $err +} + arm_cs_etm_traverse_path_test arm_cs_etm_system_wide_test arm_cs_etm_snapshot_test + +# Test all combinations of per-thread, system-wide and normal mode with +# and without timestamps +arm_cs_etm_basic_test -e cs_etm/timestamp=0/ --per-thread +arm_cs_etm_basic_test -e cs_etm/timestamp=1/ --per-thread +arm_cs_etm_basic_test -e cs_etm/timestamp=0/ -a +arm_cs_etm_basic_test -e cs_etm/timestamp=1/ -a +arm_cs_etm_basic_test -e cs_etm/timestamp=0/ +arm_cs_etm_basic_test -e cs_etm/timestamp=1/ + exit $glb_err diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index e048949bf655..456994564d6e 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -50,7 +50,22 @@ struct cs_etm_auxtrace { struct thread *unknown_thread; struct perf_tsc_conversion tc; + /* + * Timeless has no timestamps in the trace so overlapping mmap lookups + * are less accurate but produces smaller trace data. We use context IDs + * in the trace instead of matching timestamps with fork records so + * they're not really needed in the general case. Overlapping mmaps + * happen in cases like between a fork and an exec. + */ bool timeless_decoding; + + /* + * Per-thread ignores the trace channel ID and instead assumes that + * everything in a buffer comes from the same process regardless of + * which CPU it ran on. It also implies no context IDs so the TID is + * taken from the auxtrace buffer. + */ + bool per_thread_decoding; bool snapshot_mode; bool data_queued; bool has_virtual_ts; /* Virtual/Kernel timestamps in the trace. */ @@ -98,7 +113,7 @@ struct cs_etm_queue { /* RB tree for quick conversion between traceID and metadata pointers */ static struct intlist *traceid_list; -static int cs_etm__process_queues(struct cs_etm_auxtrace *etm); +static int cs_etm__process_timestamped_queues(struct cs_etm_auxtrace *etm); static int cs_etm__process_timeless_queues(struct cs_etm_auxtrace *etm, pid_t tid); static int cs_etm__get_data_block(struct cs_etm_queue *etmq); @@ -492,7 +507,7 @@ static struct cs_etm_traceid_queue struct cs_etm_traceid_queue *tidq, **traceid_queues; struct cs_etm_auxtrace *etm = etmq->etm; - if (etm->timeless_decoding) + if (etm->per_thread_decoding) trace_chan_id = CS_ETM_PER_THREAD_TRACEID; traceid_queues_list = etmq->traceid_queues_list; @@ -731,10 +746,15 @@ static int cs_etm__flush_events(struct perf_session *session, if (!tool->ordered_events) return -EINVAL; - if (etm->timeless_decoding) + if (etm->timeless_decoding) { + /* + * Pass tid = -1 to process all queues. But likely they will have + * already been processed on PERF_RECORD_EXIT anyway. + */ return cs_etm__process_timeless_queues(etm, -1); + } - return cs_etm__process_queues(etm); + return cs_etm__process_timestamped_queues(etm); } static void cs_etm__free_traceid_queues(struct cs_etm_queue *etmq) @@ -1066,7 +1086,7 @@ static int cs_etm__queue_first_cs_timestamp(struct cs_etm_auxtrace *etm, * chronological order. * * Note that packets decoded above are still in the traceID's packet - * queue and will be processed in cs_etm__process_queues(). + * queue and will be processed in cs_etm__process_timestamped_queues(). */ cs_queue_nr = TO_CS_QUEUE_NR(queue_nr, trace_chan_id); ret = auxtrace_heap__add(&etm->heap, cs_queue_nr, cs_timestamp); @@ -1347,9 +1367,7 @@ static inline u64 cs_etm__resolve_sample_time(struct cs_etm_queue *etmq, struct cs_etm_auxtrace *etm = etmq->etm; struct cs_etm_packet_queue *packet_queue = &tidq->packet_queue; - if (etm->timeless_decoding) - return 0; - else if (etm->has_virtual_ts) + if (!etm->timeless_decoding && etm->has_virtual_ts) return packet_queue->cs_timestamp; else return etm->latest_kernel_timestamp; @@ -2329,7 +2347,7 @@ static void cs_etm__clear_all_traceid_queues(struct cs_etm_queue *etmq) } } -static int cs_etm__run_decoder(struct cs_etm_queue *etmq) +static int cs_etm__run_per_thread_timeless_decoder(struct cs_etm_queue *etmq) { int err = 0; struct cs_etm_traceid_queue *tidq; @@ -2367,6 +2385,51 @@ static int cs_etm__run_decoder(struct cs_etm_queue *etmq) return err; } +static int cs_etm__run_per_cpu_timeless_decoder(struct cs_etm_queue *etmq) +{ + int idx, err = 0; + struct cs_etm_traceid_queue *tidq; + struct int_node *inode; + + /* Go through each buffer in the queue and decode them one by one */ + while (1) { + err = cs_etm__get_data_block(etmq); + if (err <= 0) + return err; + + /* Run trace decoder until buffer consumed or end of trace */ + do { + err = cs_etm__decode_data_block(etmq); + if (err) + return err; + + /* + * cs_etm__run_per_thread_timeless_decoder() runs on a + * single traceID queue because each TID has a separate + * buffer. But here in per-cpu mode we need to iterate + * over each channel instead. + */ + intlist__for_each_entry(inode, + etmq->traceid_queues_list) { + idx = (int)(intptr_t)inode->priv; + tidq = etmq->traceid_queues[idx]; + cs_etm__process_traceid_queue(etmq, tidq); + } + } while (etmq->buf_len); + + intlist__for_each_entry(inode, etmq->traceid_queues_list) { + idx = (int)(intptr_t)inode->priv; + tidq = etmq->traceid_queues[idx]; + /* Flush any remaining branch stack entries */ + err = cs_etm__end_block(etmq, tidq); + if (err) + return err; + } + } + + return err; +} + static int cs_etm__process_timeless_queues(struct cs_etm_auxtrace *etm, pid_t tid) { @@ -2381,22 +2444,30 @@ static int cs_etm__process_timeless_queues(struct cs_etm_auxtrace *etm, if (!etmq) continue; - tidq = cs_etm__etmq_get_traceid_queue(etmq, - CS_ETM_PER_THREAD_TRACEID); + /* + * Per-cpu mode has contextIDs in the trace and the decoder + * calls cs_etm__set_pid_tid_cpu() automatically so no need + * to do this here + */ + if (etm->per_thread_decoding) { + tidq = cs_etm__etmq_get_traceid_queue( + etmq, CS_ETM_PER_THREAD_TRACEID); - if (!tidq) - continue; + if (!tidq) + continue; - if ((tid == -1) || (tidq->tid == tid)) { - cs_etm__set_pid_tid_cpu(etm, tidq); - cs_etm__run_decoder(etmq); - } + if ((tid == -1) || (tidq->tid == tid)) { + cs_etm__set_pid_tid_cpu(etm, tidq); + cs_etm__run_per_thread_timeless_decoder(etmq); + } + } else + cs_etm__run_per_cpu_timeless_decoder(etmq); } return 0; } -static int cs_etm__process_queues(struct cs_etm_auxtrace *etm) +static int cs_etm__process_timestamped_queues(struct cs_etm_auxtrace *etm) { int ret = 0; unsigned int cs_queue_nr, queue_nr, i; @@ -2573,7 +2644,6 @@ static int cs_etm__process_event(struct perf_session *session, struct perf_sample *sample, struct perf_tool *tool) { - u64 sample_kernel_timestamp; struct cs_etm_auxtrace *etm = container_of(session->auxtrace, struct cs_etm_auxtrace, auxtrace); @@ -2586,33 +2656,39 @@ static int cs_etm__process_event(struct perf_session *session, return -EINVAL; } - if (sample->time && (sample->time != (u64) -1)) - sample_kernel_timestamp = sample->time; - else - sample_kernel_timestamp = 0; - - /* - * Don't wait for cs_etm__flush_events() in per-thread/timeless mode to start the decode. We - * need the tid of the PERF_RECORD_EXIT event to assign to the synthesised samples because - * ETM_OPT_CTXTID is not enabled. - */ - if (etm->timeless_decoding && - event->header.type == PERF_RECORD_EXIT) - return cs_etm__process_timeless_queues(etm, - event->fork.tid); + switch (event->header.type) { + case PERF_RECORD_EXIT: + /* + * Don't need to wait for cs_etm__flush_events() in per-thread mode to + * start the decode because we know there will be no more trace from + * this thread. All this does is emit samples earlier than waiting for + * the flush in other modes, but with timestamps it makes sense to wait + * for flush so that events from different threads are interleaved + * properly. + */ + if (etm->per_thread_decoding && etm->timeless_decoding) + return cs_etm__process_timeless_queues(etm, + event->fork.tid); + break; - if (event->header.type == PERF_RECORD_ITRACE_START) + case PERF_RECORD_ITRACE_START: return cs_etm__process_itrace_start(etm, event); - else if (event->header.type == PERF_RECORD_SWITCH_CPU_WIDE) + + case PERF_RECORD_SWITCH_CPU_WIDE: return cs_etm__process_switch_cpu_wide(etm, event); - if (!etm->timeless_decoding && event->header.type == PERF_RECORD_AUX) { + case PERF_RECORD_AUX: /* * Record the latest kernel timestamp available in the header * for samples so that synthesised samples occur from this point * onwards. */ - etm->latest_kernel_timestamp = sample_kernel_timestamp; + if (sample->time && (sample->time != (u64)-1)) + etm->latest_kernel_timestamp = sample->time; + break; + + default: + break; } return 0; @@ -2821,10 +2897,20 @@ static int cs_etm__queue_aux_fragment(struct perf_session *session, off_t file_o * Return 'not found' if mismatch. */ if (auxtrace_event->cpu == (__u32) -1) { + etm->per_thread_decoding = true; if (auxtrace_event->tid != sample->tid) return 1; - } else if (auxtrace_event->cpu != sample->cpu) + } else if (auxtrace_event->cpu != sample->cpu) { + if (etm->per_thread_decoding) { + /* + * Found a per-cpu buffer after a per-thread one was + * already found + */ + pr_err("CS ETM: Inconsistent per-thread/per-cpu mode.\n"); + return -EINVAL; + } return 1; + } if (aux_event->flags & PERF_AUX_FLAG_OVERWRITE) { /* -- cgit v1.2.3-58-ga151 From 0463ca3d7159bb86efa6f36ca70a41bb711bc6f8 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Wed, 26 Apr 2023 00:00:17 -0700 Subject: perf stat: Avoid SEGV on counter->name Switch to use evsel__name() that doesn't return NULL for hardware and similar events. Reviewed-by: Kan Liang Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Ahmad Yasin Cc: Alexander Shishkin Cc: Andi Kleen Cc: Athira Rajeev Cc: Caleb Biggers Cc: Edward Baker Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kang Minchul Cc: Leo Yan Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Rob Herring Cc: Samantha Alt Cc: Stephane Eranian Cc: Sumanth Korikkar Cc: Suzuki Poulouse Cc: Thomas Richter Cc: Tiezhu Yang Cc: Weilin Wang Cc: Xing Zhengjun Cc: Yang Jihong Link: https://lore.kernel.org/r/20230426070050.1315519-8-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/stat-display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/stat-display.c b/tools/perf/util/stat-display.c index e6035ecbeee8..73b2ff2ddf29 100644 --- a/tools/perf/util/stat-display.c +++ b/tools/perf/util/stat-display.c @@ -747,7 +747,7 @@ static void uniquify_event_name(struct evsel *counter) int ret = 0; if (counter->uniquified_name || counter->use_config_name || - !counter->pmu_name || !strncmp(counter->name, counter->pmu_name, + !counter->pmu_name || !strncmp(evsel__name(counter), counter->pmu_name, strlen(counter->pmu_name))) return; -- cgit v1.2.3-58-ga151 From 06bff3d98cf2cfef225f8190bb679f3f8cb89912 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 28 Apr 2023 00:37:27 -0700 Subject: perf stat: Disable TopdownL1 on hybrid Bugs with event parsing, event grouping and metrics causes the TopdownL1 metricgroup to crash the perf command. Temporarily disable the group if no events/metrics are spcecified. Reviewed-by: Kan Liang Signed-off-by: Ian Rogers Cc: Adrian Hunter Cc: Ahmad Yasin Cc: Alexander Shishkin Cc: Andi Kleen Cc: Athira Rajeev Cc: Caleb Biggers Cc: Edward Baker Cc: Florian Fischer Cc: Ingo Molnar Cc: James Clark Cc: Jiri Olsa Cc: John Garry Cc: Kajol Jain Cc: Kang Minchul Cc: Leo Yan Cc: Mark Rutland Cc: Namhyung Kim Cc: Perry Taylor Cc: Peter Zijlstra Cc: Ravi Bangoria Cc: Rob Herring Cc: Samantha Alt Cc: Stephane Eranian Cc: Sumanth Korikkar Cc: Suzuki Poulouse Cc: Thomas Richter Cc: Tiezhu Yang Cc: Weilin Wang Cc: Xing Zhengjun Cc: Yang Jihong Link: https://lore.kernel.org/r/20230428073809.1803624-2-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-stat.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index efda63f6bf32..be9677aa642f 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -1885,7 +1885,12 @@ static int add_default_attributes(void) * Add TopdownL1 metrics if they exist. To minimize * multiplexing, don't request threshold computation. */ - if (metricgroup__has_metric("TopdownL1") && + /* + * TODO: TopdownL1 is disabled on hybrid CPUs to avoid a crashes + * caused by exposing latent bugs. This is fixed properly in: + * https://lore.kernel.org/lkml/bff481ba-e60a-763f-0aa0-3ee53302c480@linux.intel.com/ + */ + if (metricgroup__has_metric("TopdownL1") && !perf_pmu__has_hybrid() && metricgroup__parse_groups(evsel_list, "TopdownL1", /*metric_no_group=*/false, /*metric_no_merge=*/false, @@ -1894,6 +1899,7 @@ static int add_default_attributes(void) stat_config.system_wide, &stat_config.metric_events) < 0) return -1; + /* Platform specific attrs */ if (evlist__add_default_attrs(evsel_list, default_null_attrs) < 0) return -1; -- cgit v1.2.3-58-ga151 From e53de7b65a3ca59af268c78df2d773f277f717fd Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Thu, 27 Apr 2023 16:48:32 -0700 Subject: perf lock contention: Fix struct rq lock access The BPF CO-RE's ignore suffix rule requires three underscores. Otherwise it'd fail like below: $ sudo perf lock contention -ab libbpf: prog 'collect_lock_syms': BPF program load failed: Invalid argument libbpf: prog 'collect_lock_syms': -- BEGIN PROG LOAD LOG -- reg type unsupported for arg#0 function collect_lock_syms#380 ; int BPF_PROG(collect_lock_syms) 0: (b7) r6 = 0 ; R6_w=0 1: (b7) r7 = 0 ; R7_w=0 2: (b7) r9 = 1 ; R9_w=1 3: failed to resolve CO-RE relocation [381] struct rq__new.__lock (0:0 @ offset 0) Fixes: 0c1228486befa3d6 ("perf lock contention: Support pre-5.14 kernels") Signed-off-by: Namhyung Kim Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Andrii Nakryiko Cc: Hao Luo Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Peter Zijlstra Cc: Song Liu Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230427234833.1576130-1-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/bpf_skel/lock_contention.bpf.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/bpf_skel/lock_contention.bpf.c b/tools/perf/util/bpf_skel/lock_contention.bpf.c index 8911e2a077d8..30c193078bdb 100644 --- a/tools/perf/util/bpf_skel/lock_contention.bpf.c +++ b/tools/perf/util/bpf_skel/lock_contention.bpf.c @@ -418,11 +418,11 @@ int contention_end(u64 *ctx) extern struct rq runqueues __ksym; -struct rq__old { +struct rq___old { raw_spinlock_t lock; } __attribute__((preserve_access_index)); -struct rq__new { +struct rq___new { raw_spinlock_t __lock; } __attribute__((preserve_access_index)); @@ -434,8 +434,8 @@ int BPF_PROG(collect_lock_syms) for (int i = 0; i < MAX_CPUS; i++) { struct rq *rq = bpf_per_cpu_ptr(&runqueues, i); - struct rq__new *rq_new = (void *)rq; - struct rq__old *rq_old = (void *)rq; + struct rq___new *rq_new = (void *)rq; + struct rq___old *rq_old = (void *)rq; if (rq == NULL) break; -- cgit v1.2.3-58-ga151 From b9f82b5c63bf5390da19e879275a792a959a8dac Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Thu, 27 Apr 2023 16:48:33 -0700 Subject: perf lock contention: Rework offset calculation with BPF CO-RE It seems BPF CO-RE reloc doesn't work well with the pattern that gets the field-offset only. Use offsetof() to make it explicit so that the compiler would generate the correct code. Fixes: 0c1228486befa3d6 ("perf lock contention: Support pre-5.14 kernels") Signed-off-by: Namhyung Kim Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Andrii Nakryiko Cc: Hao Luo Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Peter Zijlstra Cc: Song Liu Cc: bpf@vger.kernel.org Co-developed-by: Andrii Nakryiko Link: https://lore.kernel.org/r/20230427234833.1576130-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/bpf_skel/lock_contention.bpf.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/bpf_skel/lock_contention.bpf.c b/tools/perf/util/bpf_skel/lock_contention.bpf.c index 30c193078bdb..8d3cfbb3cc65 100644 --- a/tools/perf/util/bpf_skel/lock_contention.bpf.c +++ b/tools/perf/util/bpf_skel/lock_contention.bpf.c @@ -429,21 +429,21 @@ struct rq___new { SEC("raw_tp/bpf_test_finish") int BPF_PROG(collect_lock_syms) { - __u64 lock_addr; + __u64 lock_addr, lock_off; __u32 lock_flag; + if (bpf_core_field_exists(struct rq___new, __lock)) + lock_off = offsetof(struct rq___new, __lock); + else + lock_off = offsetof(struct rq___old, lock); + for (int i = 0; i < MAX_CPUS; i++) { struct rq *rq = bpf_per_cpu_ptr(&runqueues, i); - struct rq___new *rq_new = (void *)rq; - struct rq___old *rq_old = (void *)rq; if (rq == NULL) break; - if (bpf_core_field_exists(rq_new->__lock)) - lock_addr = (__u64)&rq_new->__lock; - else - lock_addr = (__u64)&rq_old->lock; + lock_addr = (__u64)(void *)rq + lock_off; lock_flag = LOCK_CLASS_RQLOCK; bpf_map_update_elem(&lock_syms, &lock_addr, &lock_flag, BPF_ANY); } -- cgit v1.2.3-58-ga151 From 7586d11d36fad5e6a28736be7ac8f9495e28289a Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Thu, 27 Apr 2023 16:05:01 -0700 Subject: perf list: Fix memory leaks in print_tracepoint_events() It should free entries (not only the array) filled by scandirat() after use. Reviewed-by: Ian Rogers Signed-off-by: Namhyung Kim Cc: Adrian Hunter Cc: Ingo Molnar Cc: Jiri Olsa Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230427230502.1526136-1-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/print-events.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/print-events.c b/tools/perf/util/print-events.c index 386b1ab0b60e..f5b2ea0c4fa1 100644 --- a/tools/perf/util/print-events.c +++ b/tools/perf/util/print-events.c @@ -83,11 +83,11 @@ void print_tracepoint_events(const struct print_callbacks *print_cb __maybe_unus if (sys_dirent->d_type != DT_DIR || !strcmp(sys_dirent->d_name, ".") || !strcmp(sys_dirent->d_name, "..")) - continue; + goto next_sys; dir_fd = openat(events_fd, sys_dirent->d_name, O_PATH); if (dir_fd < 0) - continue; + goto next_sys; evt_items = scandirat(events_fd, sys_dirent->d_name, &evt_namelist, NULL, alphasort); for (int j = 0; j < evt_items; j++) { @@ -98,12 +98,12 @@ void print_tracepoint_events(const struct print_callbacks *print_cb __maybe_unus if (evt_dirent->d_type != DT_DIR || !strcmp(evt_dirent->d_name, ".") || !strcmp(evt_dirent->d_name, "..")) - continue; + goto next_evt; snprintf(evt_path, sizeof(evt_path), "%s/id", evt_dirent->d_name); evt_fd = openat(dir_fd, evt_path, O_RDONLY); if (evt_fd < 0) - continue; + goto next_evt; close(evt_fd); snprintf(evt_path, MAXPATHLEN, "%s:%s", @@ -119,9 +119,13 @@ void print_tracepoint_events(const struct print_callbacks *print_cb __maybe_unus /*desc=*/NULL, /*long_desc=*/NULL, /*encoding_desc=*/NULL); +next_evt: + free(evt_namelist[j]); } close(dir_fd); free(evt_namelist); +next_sys: + free(sys_namelist[i]); } free(sys_namelist); -- cgit v1.2.3-58-ga151 From 6a7b57d85f4a6232d435eac945b325d9048f030c Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Thu, 27 Apr 2023 16:05:02 -0700 Subject: perf list: Modify the warning message about scandirat(3) It should mention scandirat() instead of scandir(). Signed-off-by: Namhyung Kim Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Ingo Molnar Cc: Jiri Olsa Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230427230502.1526136-2-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/print-events.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/print-events.c b/tools/perf/util/print-events.c index f5b2ea0c4fa1..ee145cec42c0 100644 --- a/tools/perf/util/print-events.c +++ b/tools/perf/util/print-events.c @@ -131,7 +131,7 @@ next_sys: free(sys_namelist); } #else - printf("\nWARNING: Your libc doesn't have the scandir function, please ask its maintainers to implement it.\n" + printf("\nWARNING: Your libc doesn't have the scandirat function, please ask its maintainers to implement it.\n" " As a rough fallback, please do 'ls %s' to see the available tracepoint events.\n", events_path); #endif close(events_fd); -- cgit v1.2.3-58-ga151 From 1511e4696acb715a4fe48be89e1e691daec91c0e Mon Sep 17 00:00:00 2001 From: Yang Jihong Date: Thu, 27 Apr 2023 01:28:41 +0000 Subject: perf symbols: Fix return incorrect build_id size in elf_read_build_id() In elf_read_build_id(), if gnu build_id is found, should return the size of the actually copied data. If descsz is greater thanBuild_ID_SIZE, write_buildid data access may occur. Fixes: be96ea8ffa788dcc ("perf symbols: Fix issue with binaries using 16-bytes buildids (v2)") Reported-by: Will Ochowicz Signed-off-by: Yang Jihong Tested-by: Will Ochowicz Acked-by: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Leo Yan Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Stephane Eranian Link: https://lore.kernel.org/lkml/CWLP265MB49702F7BA3D6D8F13E4B1A719C649@CWLP265MB4970.GBRP265.PROD.OUTLOOK.COM/T/ Link: https://lore.kernel.org/r/20230427012841.231729-1-yangjihong1@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/symbol-elf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/symbol-elf.c b/tools/perf/util/symbol-elf.c index 2a165d83aac4..ca75285aa656 100644 --- a/tools/perf/util/symbol-elf.c +++ b/tools/perf/util/symbol-elf.c @@ -886,7 +886,7 @@ static int elf_read_build_id(Elf *elf, void *bf, size_t size) size_t sz = min(size, descsz); memcpy(bf, ptr, sz); memset(bf + sz, 0, size - sz); - err = descsz; + err = sz; break; } } -- cgit v1.2.3-58-ga151 From 0e20f4311254193fbf9eebafb4dc5c922a885397 Mon Sep 17 00:00:00 2001 From: Changbin Du Date: Tue, 18 Apr 2023 11:18:23 +0800 Subject: perf script: Print raw ip instead of binary offset for callchain Before this, the raw ip is printed for non-callchain and dso offset for callchain. This inconsistent output for address may confuse people. And mostly what we expect is the raw ip. 'dso offset' is printed in callchain: $ perf script ... ls 1341034 2739463.008343: 2162417 cycles: ffffffff99d657a7 [unknown] ([unknown]) ffffffff99e00b67 [unknown] ([unknown]) 235d3 memset+0x53 (/usr/lib/x86_64-linux-gnu/ld-2.31.so) # dso offset a61b _dl_map_object+0x1bb (/usr/lib/x86_64-linux-gnu/ld-2.31.so) raw ip is printed for non-callchain: $ perf script -G ... ls 1341034 2739463.008876: 2053304 cycles: ffffffffc1596923 [unknown] ([unknown]) ls 1341034 2739463.009381: 1917049 cycles: 14def8e149e6 __strcoll_l+0xd96 (/usr/lib/x86_64-linux-gnu/libc-2.31.so) # raw ip Let's have consistent output for it. Later I'll add a new field 'dsoff' to print dso offset. Signed-off-by: Changbin Du Acked-by: Adrian Hunter Cc: Alexander Shishkin Cc: Hui Wang Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230418031825.1262579-2-changbin.du@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/evsel_fprintf.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'tools') diff --git a/tools/perf/util/evsel_fprintf.c b/tools/perf/util/evsel_fprintf.c index a09ac00810b7..cc80ec554c0a 100644 --- a/tools/perf/util/evsel_fprintf.c +++ b/tools/perf/util/evsel_fprintf.c @@ -153,13 +153,8 @@ int sample__fprintf_callchain(struct perf_sample *sample, int left_alignment, if (map) addr = map__map_ip(map, node->ip); - if (print_ip) { - /* Show binary offset for userspace addr */ - if (map && !map__dso(map)->kernel) - printed += fprintf(fp, "%c%16" PRIx64, s, addr); - else - printed += fprintf(fp, "%c%16" PRIx64, s, node->ip); - } + if (print_ip) + printed += fprintf(fp, "%c%16" PRIx64, s, node->ip); if (print_sym) { printed += fprintf(fp, " "); -- cgit v1.2.3-58-ga151 From 69b0e112612be9e325ea682263d895f3c675772f Mon Sep 17 00:00:00 2001 From: Sriram Yagnaraman Date: Wed, 26 Apr 2023 12:41:49 +0200 Subject: perf script: Add new parameter in kfree_skb tracepoint to the python scripts using it Include reason parameter that was added in commit c504e5c2f9648a1e ("net: skb: introduce kfree_skb_reason()") Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Sriram Yagnaraman Link: https://lore.kernel.org/r/20230426104149.14089-1-sriram.yagnaraman@est.tech Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/scripts/python/net_dropmonitor.py | 4 ++-- tools/perf/scripts/python/netdev-times.py | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'tools') diff --git a/tools/perf/scripts/python/net_dropmonitor.py b/tools/perf/scripts/python/net_dropmonitor.py index 101059971738..a97e7a6e0940 100755 --- a/tools/perf/scripts/python/net_dropmonitor.py +++ b/tools/perf/scripts/python/net_dropmonitor.py @@ -68,9 +68,9 @@ def trace_end(): get_kallsyms_table() print_drop_table() -# called from perf, when it finds a correspoinding event +# called from perf, when it finds a corresponding event def skb__kfree_skb(name, context, cpu, sec, nsec, pid, comm, callchain, - skbaddr, location, protocol): + skbaddr, location, protocol, reason): slocation = str(location) try: drop_log[slocation] = drop_log[slocation] + 1 diff --git a/tools/perf/scripts/python/netdev-times.py b/tools/perf/scripts/python/netdev-times.py index a0cfc7fe5908..00552eeb7178 100644 --- a/tools/perf/scripts/python/netdev-times.py +++ b/tools/perf/scripts/python/netdev-times.py @@ -288,9 +288,9 @@ def net__net_dev_xmit(name, context, cpu, sec, nsec, pid, comm, callchain, all_event_list.append(event_info) def skb__kfree_skb(name, context, cpu, sec, nsec, pid, comm, callchain, - skbaddr, protocol, location): + skbaddr, location, protocol, reason): event_info = (name, context, cpu, nsecs(sec, nsec), pid, comm, - skbaddr, protocol, location) + skbaddr, location, protocol, reason) all_event_list.append(event_info) def skb__consume_skb(name, context, cpu, sec, nsec, pid, comm, callchain, skbaddr): @@ -430,7 +430,7 @@ def handle_net_dev_xmit(event_info): def handle_kfree_skb(event_info): (name, context, cpu, time, pid, comm, - skbaddr, protocol, location) = event_info + skbaddr, location, protocol, reason) = event_info for i in range(len(tx_queue_list)): skb = tx_queue_list[i] if skb['skbaddr'] == skbaddr: -- cgit v1.2.3-58-ga151 From c31380140f11195abb5b5f576355f886d32afd1c Mon Sep 17 00:00:00 2001 From: Changbin Du Date: Wed, 26 Apr 2023 11:22:46 +0800 Subject: perf unwind: Suppress massive unsupported target platform errors When cross-analyzing perf data recorded on an another platform, massive unsupported target platform errors are printed. So let's show this message as warning and only once. Signed-off-by: Changbin Du Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Hui Wang Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230426032246.3608596-1-changbin.du@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/unwind-libunwind.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/unwind-libunwind.c b/tools/perf/util/unwind-libunwind.c index b54968e6a4e4..375d23d9a590 100644 --- a/tools/perf/util/unwind-libunwind.c +++ b/tools/perf/util/unwind-libunwind.c @@ -56,7 +56,7 @@ int unwind__prepare_access(struct maps *maps, struct map *map, bool *initialized } if (!ops) { - pr_err("unwind: target platform=%s is not supported\n", arch); + pr_warning_once("unwind: target platform=%s is not supported\n", arch); return 0; } out_register: -- cgit v1.2.3-58-ga151 From d199226143f0ef6919131120319766ece514314e Mon Sep 17 00:00:00 2001 From: James Clark Date: Tue, 25 Apr 2023 11:44:13 +0100 Subject: perf build: Fix unescaped # in perf build-test With the following bash and make versions: $ make --version GNU Make 4.2.1 Built for aarch64-unknown-linux-gnu $ bash --version GNU bash, version 5.0.17(1)-release (aarch64-unknown-linux-gnu) This error is encountered when running the build-test target: $ make -C tools/perf build-test tests/make:181: *** unterminated call to function 'shell': missing ')'. Stop. make: *** [Makefile:103: build-test] Error 2 Fix it by escaping the # which was causing make to interpret the rest of the line as a comment leaving the unclosed opening bracket. Fixes: 56d5229471ee1634 ("tools build: Pass libbpf feature only if libbpf 1.0+") Signed-off-by: James Clark Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: bpf@vger.kernel.org Link: https://lore.kernel.org/r/20230425104414.1723571-1-james.clark@arm.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/make | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/tests/make b/tools/perf/tests/make index d75876126631..8dd3f8090352 100644 --- a/tools/perf/tests/make +++ b/tools/perf/tests/make @@ -178,7 +178,7 @@ run += make_install_prefix_slash # run += make_install_pdf run += make_minimal -old_libbpf := $(shell echo "#include " | $(CC) -E -dM -x c -| egrep -q "define[[:space:]]+LIBBPF_MAJOR_VERSION[[:space:]]+0{1}") +old_libbpf := $(shell echo '\#include ' | $(CC) -E -dM -x c -| egrep -q "define[[:space:]]+LIBBPF_MAJOR_VERSION[[:space:]]+0{1}") ifneq ($(old_libbpf),) run += make_libbpf_dynamic -- cgit v1.2.3-58-ga151 From 6bf86cada3eb8ec3eb80cdce5280e7a22dac8b01 Mon Sep 17 00:00:00 2001 From: Ganapatrao Kulkarni Date: Thu, 20 Apr 2023 22:52:53 -0700 Subject: perf cs-etm: Add fix for coresight trace for any range of CPUs The current implementation supports coresight trace decode for a range of CPUs, if the first CPU is CPU0. Perf report segfaults, if tried for sparse CPUs list and also for any range of CPUs(non zero first CPU). Adding a fix to perf report for any range of CPUs and for sparse list. Signed-off-by: Ganapatrao Kulkarni Link: https://lore.kernel.org/r/20230421055253.83912-1-gankulkarni@os.amperecomputing.com Cc: suzuki.poulose@arm.com Cc: acme@kernel.org Cc: mathieu.poirier@linaro.org Cc: mike.leach@linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: darren@os.amperecomputing.com Cc: scclevenger@os.amperecomputing.com Cc: scott@os.amperecomputing.com Cc: linux-kernel@vger.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/cs-etm.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 456994564d6e..91299cc56bf7 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -290,6 +290,25 @@ static int cs_etm__metadata_set_trace_id(u8 trace_chan_id, u64 *cpu_metadata) (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ }) +/* + * Get a metadata for a specific cpu from an array. + * + */ +static u64 *get_cpu_data(struct cs_etm_auxtrace *etm, int cpu) +{ + int i; + u64 *metadata = NULL; + + for (i = 0; i < etm->num_cpu; i++) { + if (etm->metadata[i][CS_ETM_CPU] == (u64)cpu) { + metadata = etm->metadata[i]; + break; + } + } + + return metadata; +} + /* * Handle the PERF_RECORD_AUX_OUTPUT_HW_ID event. * @@ -359,8 +378,11 @@ static int cs_etm__process_aux_output_hw_id(struct perf_session *session, return 0; } + cpu_data = get_cpu_data(etm, cpu); + if (cpu_data == NULL) + return err; + /* not one we've seen before - lets map it */ - cpu_data = etm->metadata[cpu]; err = cs_etm__map_trace_id(trace_chan_id, cpu_data); if (err) return err; -- cgit v1.2.3-58-ga151 From 9b86c49710eec7b4fbb78a0232b2dd0972a2b576 Mon Sep 17 00:00:00 2001 From: Yang Jihong Date: Fri, 21 Apr 2023 02:59:53 +0000 Subject: perf tracepoint: Fix memory leak in is_valid_tracepoint() When is_valid_tracepoint() returns 1, need to call put_events_file() to free `dir_path`. Fixes: 25a7d914274de386 ("perf parse-events: Use get/put_events_file()") Signed-off-by: Yang Jihong Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230421025953.173826-1-yangjihong1@huawei.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/tracepoint.c | 1 + 1 file changed, 1 insertion(+) (limited to 'tools') diff --git a/tools/perf/util/tracepoint.c b/tools/perf/util/tracepoint.c index 89ef56c43311..92dd8b455b90 100644 --- a/tools/perf/util/tracepoint.c +++ b/tools/perf/util/tracepoint.c @@ -50,6 +50,7 @@ int is_valid_tracepoint(const char *event_string) sys_dirent->d_name, evt_dirent->d_name); if (!strcmp(evt_path, event_string)) { closedir(evt_dir); + put_events_file(dir_path); closedir(sys_dir); return 1; } -- cgit v1.2.3-58-ga151 From 311693ce81c9da3724d4294a4c3769a3b30b6a7f Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Wed, 3 May 2023 10:11:34 +0200 Subject: perf test record+probe_libc_inet_pton: Fix call chain match on s390 With Fedora 38 the perf test 86 probe libc's inet_pton fails on s390. The call chain of the ping command changed. The functions text_to_binary_address() and gaih_inet() do not show up in the call chain anymore. Output before: # ./perf test -v 86 86: probe libc's inet_pton & backtrace it with ping : --- start --- test child forked, pid 541050 fgrep: warning: fgrep is obsolescent; using grep -F fgrep: warning: fgrep is obsolescent; using grep -F BFD: DWARF error: could not find variable specification at offset 0x22011 ... ping 541078 [002] 348826.679581: probe_libc:inet_pton_1: (3ffad84b940) 14b940 __GI___inet_pton+0x0 (/usr/lib64/libc.so.6) 10e9c3 __GI_getaddrinfo+0xeb3 (inlined) 4397 main+0x737 (/usr/bin/ping) FAIL: expected backtrace entry "gaih_inet.*\+0x[[:xdigit:]]\ +[[:space:]]\(/usr/lib64/libc.so.6|inlined\)$" got "4397 main+0x737 (/usr/bin/ping)" test child finished with -1 ---- end ---- probe libc's inet_pton & backtrace it with ping: FAILED! # Output after: # ./perf test -v 86 86: probe libc's inet_pton & backtrace it with ping : --- start --- test child forked, pid 541098 fgrep: warning: fgrep is obsolescent; using grep -F fgrep: warning: fgrep is obsolescent; using grep -F BFD: DWARF error: could not find variable specification at offset 0x309d1 ... ping 541126 [006] 349309.099067: probe_libc:inet_pton_1: (3ffb7f4b940) 14b940 __GI___inet_pton+0x0 (/usr/lib64/libc.so.6) 10e9c3 __GI_getaddrinfo+0xeb3 (inlined) 4397 main+0x737 (/usr/bin/ping) test child finished with 0 ---- end ---- probe libc's inet_pton & backtrace it with ping: Ok # Signed-off-by: Thomas Richter Cc: Heiko Carstens Cc: Sumanth Korikkar Cc: Sven Schnelle Cc: Vasily Gorbik Link: https://lore.kernel.org/r/20230503081134.3372415-1-tmricht@linux.ibm.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/shell/record+probe_libc_inet_pton.sh | 2 -- 1 file changed, 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/tests/shell/record+probe_libc_inet_pton.sh b/tools/perf/tests/shell/record+probe_libc_inet_pton.sh index b4149b2db4c6..4c739056cb65 100755 --- a/tools/perf/tests/shell/record+probe_libc_inet_pton.sh +++ b/tools/perf/tests/shell/record+probe_libc_inet_pton.sh @@ -38,8 +38,6 @@ trace_libc_inet_pton_backtrace() { case "$(uname -m)" in s390x) eventattr='call-graph=dwarf,max-stack=4' - echo "text_to_binary_address.*\+0x[[:xdigit:]]+[[:space:]]\($libc|inlined\)$" >> $expected - echo "gaih_inet.*\+0x[[:xdigit:]]+[[:space:]]\($libc|inlined\)$" >> $expected echo "(__GI_)?getaddrinfo\+0x[[:xdigit:]]+[[:space:]]\($libc|inlined\)$" >> $expected echo "main\+0x[[:xdigit:]]+[[:space:]]\(.*/bin/ping.*\)$" >> $expected ;; -- cgit v1.2.3-58-ga151 From 1f85d016768ff19f060f3cce014a43c761de8259 Mon Sep 17 00:00:00 2001 From: Thomas Richter Date: Wed, 3 May 2023 10:12:55 +0200 Subject: perf test record+probe_libc_inet_pton: Fix call chain match on x86_64 The test case probe libc's inet_pton & backtrace it with ping fails with Fedora 38 on x86_64. Function getaddrinfo() does not show up in the call chain anymore: # ./perf script ping 1803 [000] 728.567146: probe_libc:inet_pton: (7f5275afc840) 133840 __GI___inet_pton+0x0 (/usr/lib64/libc.so.6) 27b4a __libc_start_call_main+0x7a (/usr/lib64/libc.so.6) 27c0b __libc_start_main@@GLIBC_2.34+0x8b (/usr/lib64/libc.so.6) ping 1803 [000] 728.567184: probe_libc:inet_pton: (7f5275afc840) 133840 __GI___inet_pton+0x0 (/usr/lib64/libc.so.6) 493e main+0xcde (/usr/bin/ping) 27b4a __libc_start_call_main+0x7a (/usr/lib64/libc.so.6) # which causes the test case to fail. Remove function getaddrinfo() from list of expected functions. Output before: # ./perf test 'libc' 91: probe libc's inet_pton & backtrace it with ping : FAILED! # Output after: # ./perf test 'libc' 91: probe libc's inet_pton & backtrace it with ping : Ok # Signed-off-by: Thomas Richter Tested-by: Arnaldo Carvalho de Melo Cc: Heiko Carstens Cc: Sumanth Korikkar Cc: Sven Schnelle Cc: Vasily Gorbik Link: https://lore.kernel.org/r/20230503081255.3372986-1-tmricht@linux.ibm.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/shell/record+probe_libc_inet_pton.sh | 1 - 1 file changed, 1 deletion(-) (limited to 'tools') diff --git a/tools/perf/tests/shell/record+probe_libc_inet_pton.sh b/tools/perf/tests/shell/record+probe_libc_inet_pton.sh index 4c739056cb65..bbb5b3d185fa 100755 --- a/tools/perf/tests/shell/record+probe_libc_inet_pton.sh +++ b/tools/perf/tests/shell/record+probe_libc_inet_pton.sh @@ -49,7 +49,6 @@ trace_libc_inet_pton_backtrace() { ;; *) eventattr='max-stack=3' - echo "getaddrinfo\+0x[[:xdigit:]]+[[:space:]]\($libc\)$" >> $expected echo ".*(\+0x[[:xdigit:]]+|\[unknown\])[[:space:]]\(.*/bin/ping.*\)$" >> $expected ;; esac -- cgit v1.2.3-58-ga151 From ecc68ee216c6c5b2f84915e1441adf436f1b019b Mon Sep 17 00:00:00 2001 From: Dmitrii Dolgov <9erthalion6@gmail.com> Date: Wed, 12 Apr 2023 20:23:16 +0200 Subject: perf stat: Separate bperf from bpf_profiler It seems that perf stat -b doesn't produce any results: $ perf stat -e cycles -b 4 -I 10000 -vvv Control descriptor is not initialized cycles: 0 0 0 time counts unit events 10.007641640 cycles Looks like this happens because fentry/fexit progs are getting loaded, but the corresponding perf event is not enabled and not added into the events bpf map. I think there is some mixing up between two type of bpf support, one for bperf and one for bpf_profiler. Both are identified via evsel__is_bpf, based on which perf events are enabled, but for the latter (bpf_profiler) a perf event is required. Using evsel__is_bperf to check only bperf produces expected results: $ perf stat -e cycles -b 4 -I 10000 -vvv Control descriptor is not initialized ------------------------------------------------------------ perf_event_attr: size 136 sample_type IDENTIFIER read_format TOTAL_TIME_ENABLED|TOTAL_TIME_RUNNING disabled 1 exclude_guest 1 ------------------------------------------------------------ sys_perf_event_open: pid -1 cpu 0 group_fd -1 flags 0x8 = 3 ------------------------------------------------------------ [...perf_event_attr for other CPUs...] ------------------------------------------------------------ cycles: 309426 169009 169009 time counts unit events 10.010091271 309426 cycles The final numbers correspond (at least in the level of magnitude) to the same metric obtained via bpftool. Fixes: 112cb56164bc2108 ("perf stat: Introduce config stat.bpf-counter-events") Reviewed-by: Song Liu Signed-off-by: Dmitrii Dolgov <9erthalion6@gmail.com> Tested-by: Song Liu Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Namhyung Kim Cc: Song Liu Link: https://lore.kernel.org/r/20230412182316.11628-1-9erthalion6@gmail.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/builtin-stat.c | 4 ++-- tools/perf/util/evsel.h | 5 +++++ 2 files changed, 7 insertions(+), 2 deletions(-) (limited to 'tools') diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index be9677aa642f..cc9fa48d636f 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -712,7 +712,7 @@ static int __run_perf_stat(int argc, const char **argv, int run_idx) counter->reset_group = false; if (bpf_counter__load(counter, &target)) return -1; - if (!evsel__is_bpf(counter)) + if (!(evsel__is_bperf(counter))) all_counters_use_bpf = false; } @@ -728,7 +728,7 @@ static int __run_perf_stat(int argc, const char **argv, int run_idx) if (counter->reset_group || counter->errored) continue; - if (evsel__is_bpf(counter)) + if (evsel__is_bperf(counter)) continue; try_again: if (create_perf_stat_counter(counter, &stat_config, &target, diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h index 35805dcdb1b9..d575390d80bc 100644 --- a/tools/perf/util/evsel.h +++ b/tools/perf/util/evsel.h @@ -269,6 +269,11 @@ static inline bool evsel__is_bpf(struct evsel *evsel) return evsel->bpf_counter_ops != NULL; } +static inline bool evsel__is_bperf(struct evsel *evsel) +{ + return evsel->bpf_counter_ops != NULL && list_empty(&evsel->bpf_counter_list); +} + #define EVSEL__MAX_ALIASES 8 extern const char *const evsel__hw_cache[PERF_COUNT_HW_CACHE_MAX][EVSEL__MAX_ALIASES]; -- cgit v1.2.3-58-ga151 From a887466562b425bd6183bf75b523c1477c9fd22d Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Thu, 4 May 2023 19:03:51 -0300 Subject: perf bpf skels: Stop using vmlinux.h generated from BTF, use subset of used structs + CO-RE Linus reported a build break due to using a vmlinux without a BTF elf section to generate the vmlinux.h header with bpftool for use in the BPF tools in tools/perf/util/bpf_skel/*.bpf.c. Instead add a vmlinux.h file with the structs needed with the fields the tools need, marking the structs with __attribute__((preserve_access_index)), so that libbpf's CO-RE code can fixup the struct field offsets. In some cases the vmlinux.h file that was being generated by bpftool from the kernel BTF information was not needed at all, just including linux/bpf.h, sometimes linux/perf_event.h was enough as non-UAPI types were not being used. To keep te patch small, include those UAPI headers from the trimmed down vmlinux.h file, that then provides the tools with just the structs and the subset of its fields needed for them. Testing it: # perf lock contention -b find / > /dev/null ^C contended total wait max wait avg wait type caller 7 53.59 us 10.86 us 7.66 us rwlock:R start_this_handle+0xa0 2 30.35 us 21.99 us 15.17 us rwsem:R iterate_dir+0x52 1 9.04 us 9.04 us 9.04 us rwlock:W start_this_handle+0x291 1 8.73 us 8.73 us 8.73 us spinlock raw_spin_rq_lock_nested+0x1e # # perf lock contention -abl find / > /dev/null ^C contended total wait max wait avg wait address symbol 1 262.96 ms 262.96 ms 262.96 ms ffff8e67502d0170 (mutex) 12 244.24 us 39.91 us 20.35 us ffff8e6af56f8070 mmap_lock (rwsem) 7 30.28 us 6.85 us 4.33 us ffff8e6c865f1d40 rq_lock (spinlock) 3 7.42 us 4.03 us 2.47 us ffff8e6c864b1d40 rq_lock (spinlock) 2 3.72 us 2.19 us 1.86 us ffff8e6c86571d40 rq_lock (spinlock) 1 2.42 us 2.42 us 2.42 us ffff8e6c86471d40 rq_lock (spinlock) 4 2.11 us 559 ns 527 ns ffffffff9a146c80 rcu_state (spinlock) 3 1.45 us 818 ns 482 ns ffff8e674ae8384c (rwlock) 1 870 ns 870 ns 870 ns ffff8e68456ee060 (rwlock) 1 663 ns 663 ns 663 ns ffff8e6c864f1d40 rq_lock (spinlock) 1 573 ns 573 ns 573 ns ffff8e6c86531d40 rq_lock (spinlock) 1 472 ns 472 ns 472 ns ffff8e6c86431740 (spinlock) 1 397 ns 397 ns 397 ns ffff8e67413a4f04 (spinlock) # # perf test offcpu 95: perf record offcpu profiling tests : Ok # # perf kwork latency --use-bpf Starting trace, Hit to stop and report ^C Kwork Name | Cpu | Avg delay | Count | Max delay | Max delay start | Max delay end | -------------------------------------------------------------------------------------------------------------------------------- (w)flush_memcg_stats_dwork | 0000 | 1056.212 ms | 2 | 2112.345 ms | 550113.229573 s | 550115.341919 s | (w)toggle_allocation_gate | 0000 | 10.144 ms | 62 | 416.389 ms | 550113.453518 s | 550113.869907 s | (w)0xffff8e6748e28080 | 0002 | 0.623 ms | 1 | 0.623 ms | 550110.989841 s | 550110.990464 s | (w)vmstat_shepherd | 0000 | 0.586 ms | 10 | 2.828 ms | 550111.971536 s | 550111.974364 s | (w)vmstat_update | 0007 | 0.363 ms | 5 | 1.634 ms | 550113.222520 s | 550113.224154 s | (w)vmstat_update | 0000 | 0.324 ms | 10 | 2.827 ms | 550111.971526 s | 550111.974354 s | (w)0xffff8e674c5f4a58 | 0002 | 0.102 ms | 5 | 0.134 ms | 550110.989839 s | 550110.989972 s | (w)psi_avgs_work | 0001 | 0.086 ms | 3 | 0.107 ms | 550114.957852 s | 550114.957959 s | (w)psi_avgs_work | 0000 | 0.079 ms | 5 | 0.100 ms | 550118.605668 s | 550118.605768 s | (w)kfree_rcu_monitor | 0006 | 0.079 ms | 1 | 0.079 ms | 550110.925821 s | 550110.925900 s | (w)psi_avgs_work | 0004 | 0.079 ms | 1 | 0.079 ms | 550109.581835 s | 550109.581914 s | (w)psi_avgs_work | 0001 | 0.078 ms | 1 | 0.078 ms | 550109.197809 s | 550109.197887 s | (w)psi_avgs_work | 0002 | 0.077 ms | 5 | 0.086 ms | 550110.669819 s | 550110.669905 s | # strace -e bpf -o perf-stat-bpf-counters.output perf stat -e cycles --bpf-counters sleep 1 Performance counter stats for 'sleep 1': 6,197,983 cycles 1.003922848 seconds time elapsed 0.000000000 seconds user 0.002032000 seconds sys # head -7 perf-stat-bpf-counters.output bpf(BPF_OBJ_GET, {pathname="/sys/fs/bpf/perf_attr_map", bpf_fd=0, file_flags=0}, 16) = 3 bpf(BPF_OBJ_GET_INFO_BY_FD, {info={bpf_fd=3, info_len=88, info=0x7ffcead64990}}, 16) = 0 bpf(BPF_MAP_LOOKUP_ELEM, {map_fd=3, key=0x24129e0, value=0x7ffcead65a48, flags=BPF_ANY}, 32) = 0 bpf(BPF_LINK_GET_FD_BY_ID, {link_id=1252}, 12) = -1 ENOENT (No such file or directory) bpf(BPF_PROG_LOAD, {prog_type=BPF_PROG_TYPE_SOCKET_FILTER, insn_cnt=2, insns=0x7ffcead65780, license="GPL", log_level=0, log_size=0, log_buf=NULL, kern_version=KERNEL_VERSION(0, 0, 0), prog_flags=0, prog_name="", prog_ifindex=0, expected_attach_type=BPF_CGROUP_INET_INGRESS, prog_btf_fd=0, func_info_rec_size=0, +func_info=NULL, func_info_cnt=0, line_info_rec_size=0, line_info=NULL, line_info_cnt=0, attach_btf_id=0, attach_prog_fd=0}, 116) = 4 bpf(BPF_PROG_LOAD, {prog_type=BPF_PROG_TYPE_SOCKET_FILTER, insn_cnt=2, insns=0x7ffcead65920, license="GPL", log_level=0, log_size=0, log_buf=NULL, kern_version=KERNEL_VERSION(0, 0, 0), prog_flags=0, prog_name="", prog_ifindex=0, expected_attach_type=BPF_CGROUP_INET_INGRESS, prog_btf_fd=0, func_info_rec_size=0, +func_info=NULL, func_info_cnt=0, line_info_rec_size=0, line_info=NULL, line_info_cnt=0, attach_btf_id=0, attach_prog_fd=0, fd_array=NULL}, 128) = 4 bpf(BPF_BTF_LOAD, {btf="\237\353\1\0\30\0\0\0\0\0\0\0\20\0\0\0\20\0\0\0\5\0\0\0\1\0\0\0\0\0\0\1"..., btf_log_buf=NULL, btf_size=45, btf_log_size=0, btf_log_level=0}, 28) = 4 # Reported-by: Linus Torvalds Suggested-by: Andrii Nakryiko Tested-by: Namhyung Kim Tested-by: Song Liu Cc: Adrian Hunter Cc: Alexei Starovoitov Cc: Ian Rogers Cc: Jiri Olsa Co-developed-by: Jiri Olsa Link: https://lore.kernel.org/lkml/ZFU1PJrn8YtHIqno@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Makefile.perf | 20 +---- tools/perf/util/bpf_skel/.gitignore | 1 - tools/perf/util/bpf_skel/vmlinux.h | 173 ++++++++++++++++++++++++++++++++++++ 3 files changed, 174 insertions(+), 20 deletions(-) create mode 100644 tools/perf/util/bpf_skel/vmlinux.h (limited to 'tools') diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf index 48aba186ceb5..61c33d100b2b 100644 --- a/tools/perf/Makefile.perf +++ b/tools/perf/Makefile.perf @@ -1063,25 +1063,7 @@ $(BPFTOOL): | $(SKEL_TMP_OUT) $(Q)CFLAGS= $(MAKE) -C ../bpf/bpftool \ OUTPUT=$(SKEL_TMP_OUT)/ bootstrap -VMLINUX_BTF_PATHS ?= $(if $(O),$(O)/vmlinux) \ - $(if $(KBUILD_OUTPUT),$(KBUILD_OUTPUT)/vmlinux) \ - ../../vmlinux \ - /sys/kernel/btf/vmlinux \ - /boot/vmlinux-$(shell uname -r) -VMLINUX_BTF ?= $(abspath $(firstword $(wildcard $(VMLINUX_BTF_PATHS)))) - -$(SKEL_OUT)/vmlinux.h: $(VMLINUX_BTF) $(BPFTOOL) -ifeq ($(VMLINUX_H),) - $(QUIET_GEN)$(BPFTOOL) btf dump file $< format c > $@ || \ - (echo "Failure to generate vmlinux.h needed for the recommended BPF skeleton support." && \ - echo "To disable this use the build option NO_BPF_SKEL=1." && \ - echo "Alternatively point at a pre-generated vmlinux.h with VMLINUX_H=." && \ - false) -else - $(Q)cp "$(VMLINUX_H)" $@ -endif - -$(SKEL_TMP_OUT)/%.bpf.o: util/bpf_skel/%.bpf.c $(LIBBPF) $(SKEL_OUT)/vmlinux.h | $(SKEL_TMP_OUT) +$(SKEL_TMP_OUT)/%.bpf.o: util/bpf_skel/%.bpf.c $(LIBBPF) | $(SKEL_TMP_OUT) $(QUIET_CLANG)$(CLANG) -g -O2 -target bpf -Wall -Werror $(BPF_INCLUDE) \ -c $(filter util/bpf_skel/%.bpf.c,$^) -o $@ && $(LLVM_STRIP) -g $@ diff --git a/tools/perf/util/bpf_skel/.gitignore b/tools/perf/util/bpf_skel/.gitignore index cd01455e1b53..7a1c832825de 100644 --- a/tools/perf/util/bpf_skel/.gitignore +++ b/tools/perf/util/bpf_skel/.gitignore @@ -1,4 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only .tmp *.skel.h -vmlinux.h diff --git a/tools/perf/util/bpf_skel/vmlinux.h b/tools/perf/util/bpf_skel/vmlinux.h new file mode 100644 index 000000000000..449b1ea91fc4 --- /dev/null +++ b/tools/perf/util/bpf_skel/vmlinux.h @@ -0,0 +1,173 @@ +#ifndef __VMLINUX_H +#define __VMLINUX_H + +#include +#include +#include +#include + +// non-UAPI kernel data structures, used in the .bpf.c BPF tool component. + +// Just the fields used in these tools preserving the access index so that +// libbpf can fixup offsets with the ones used in the kernel when loading the +// BPF bytecode, if they differ from what is used here. + +typedef __u8 u8; +typedef __u32 u32; +typedef __u64 u64; +typedef __s64 s64; + +typedef int pid_t; + +enum cgroup_subsys_id { + perf_event_cgrp_id = 8, +}; + +enum { + HI_SOFTIRQ = 0, + TIMER_SOFTIRQ, + NET_TX_SOFTIRQ, + NET_RX_SOFTIRQ, + BLOCK_SOFTIRQ, + IRQ_POLL_SOFTIRQ, + TASKLET_SOFTIRQ, + SCHED_SOFTIRQ, + HRTIMER_SOFTIRQ, + RCU_SOFTIRQ, /* Preferable RCU should always be the last softirq */ + + NR_SOFTIRQS +}; + +typedef struct { + s64 counter; +} __attribute__((preserve_access_index)) atomic64_t; + +typedef atomic64_t atomic_long_t; + +struct raw_spinlock { + int rawlock; +} __attribute__((preserve_access_index)); + +typedef struct raw_spinlock raw_spinlock_t; + +typedef struct { + struct raw_spinlock rlock; +} __attribute__((preserve_access_index)) spinlock_t; + +struct sighand_struct { + spinlock_t siglock; +} __attribute__((preserve_access_index)); + +struct rw_semaphore { + atomic_long_t owner; +} __attribute__((preserve_access_index)); + +struct mutex { + atomic_long_t owner; +} __attribute__((preserve_access_index)); + +struct kernfs_node { + u64 id; +} __attribute__((preserve_access_index)); + +struct cgroup { + struct kernfs_node *kn; + int level; +} __attribute__((preserve_access_index)); + +struct cgroup_subsys_state { + struct cgroup *cgroup; +} __attribute__((preserve_access_index)); + +struct css_set { + struct cgroup_subsys_state *subsys[13]; + struct cgroup *dfl_cgrp; +} __attribute__((preserve_access_index)); + +struct mm_struct { + struct rw_semaphore mmap_lock; +} __attribute__((preserve_access_index)); + +struct task_struct { + unsigned int flags; + struct mm_struct *mm; + pid_t pid; + pid_t tgid; + char comm[16]; + struct sighand_struct *sighand; + struct css_set *cgroups; +} __attribute__((preserve_access_index)); + +struct trace_entry { + short unsigned int type; + unsigned char flags; + unsigned char preempt_count; + int pid; +} __attribute__((preserve_access_index)); + +struct trace_event_raw_irq_handler_entry { + struct trace_entry ent; + int irq; + u32 __data_loc_name; + char __data[]; +} __attribute__((preserve_access_index)); + +struct trace_event_raw_irq_handler_exit { + struct trace_entry ent; + int irq; + int ret; + char __data[]; +} __attribute__((preserve_access_index)); + +struct trace_event_raw_softirq { + struct trace_entry ent; + unsigned int vec; + char __data[]; +} __attribute__((preserve_access_index)); + +struct trace_event_raw_workqueue_execute_start { + struct trace_entry ent; + void *work; + void *function; + char __data[]; +} __attribute__((preserve_access_index)); + +struct trace_event_raw_workqueue_execute_end { + struct trace_entry ent; + void *work; + void *function; + char __data[]; +} __attribute__((preserve_access_index)); + +struct trace_event_raw_workqueue_activate_work { + struct trace_entry ent; + void *work; + char __data[]; +} __attribute__((preserve_access_index)); + +struct perf_sample_data { + u64 addr; + u64 period; + union perf_sample_weight weight; + u64 txn; + union perf_mem_data_src data_src; + u64 ip; + struct { + u32 pid; + u32 tid; + } tid_entry; + u64 time; + u64 id; + struct { + u32 cpu; + } cpu_entry; + u64 phys_addr; + u64 data_page_size; + u64 code_page_size; +} __attribute__((__aligned__(64))) __attribute__((preserve_access_index)); + +struct bpf_perf_event_data_kern { + struct perf_sample_data *data; + struct perf_event *event; +} __attribute__((preserve_access_index)); +#endif // __VMLINUX_H -- cgit v1.2.3-58-ga151 From 6c73f819b6b6d6f052e8dbe3f66f0693554ddf48 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Fri, 5 May 2023 13:41:19 -0700 Subject: perf metrics: Fix SEGV with --for-each-cgroup Ensure the metric threshold is copied correctly or else a use of uninitialized memory happens. Fixes: d0a3052f6faefffc ("perf metric: Compute and print threshold values") Reported-by: Namhyung Kim Signed-off-by: Ian Rogers Tested-by: Namhyung Kim Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kajol Jain Cc: Mark Rutland Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230505204119.3443491-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/metricgroup.c | 1 + 1 file changed, 1 insertion(+) (limited to 'tools') diff --git a/tools/perf/util/metricgroup.c b/tools/perf/util/metricgroup.c index 4b9a16291b96..c566c6859302 100644 --- a/tools/perf/util/metricgroup.c +++ b/tools/perf/util/metricgroup.c @@ -1730,6 +1730,7 @@ int metricgroup__copy_metric_events(struct evlist *evlist, struct cgroup *cgrp, return -ENOMEM; new_expr->metric_expr = old_expr->metric_expr; + new_expr->metric_threshold = old_expr->metric_threshold; new_expr->metric_name = strdup(old_expr->metric_name); if (!new_expr->metric_name) return -ENOMEM; -- cgit v1.2.3-58-ga151 From c3e6df97fa25ff310c3d5e7f1644248e072e3cb0 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Sat, 6 May 2023 18:06:43 -0300 Subject: Revert "perf build: Warn for BPF skeletons if endian mismatches" This reverts commit 51924ae69eea5bc90b5da525fbcf4bbd5f8551b3. We need to better polish building with BPF skels, so revert back to making it an experimental feature that has to be explicitely enabled using BUILD_BPF_SKEL=1. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Makefile.config | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) (limited to 'tools') diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index 71442c54c25f..16bea51f0bcd 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -663,17 +663,14 @@ ifndef NO_BPF_SKEL $(call feature_check,clang-bpf-co-re) ifeq ($(feature-clang-bpf-co-re), 0) dummy := $(error: ERROR: BPF skeletons unsupported. clang too old/not installed or build with NO_BPF_SKEL=1.) + else + ifeq ($(filter -DHAVE_LIBBPF_SUPPORT, $(CFLAGS)),) + dummy := $(error: ERROR: BPF skeletons unsupported. BPF skeleton support requires libbpf or build with NO_BPF_SKEL=1.) + else + $(call detected,CONFIG_PERF_BPF_SKEL) + CFLAGS += -DHAVE_BPF_SKEL + endif endif - ifeq ($(filter -DHAVE_LIBBPF_SUPPORT, $(CFLAGS)),) - dummy := $(error: ERROR: BPF skeletons unsupported. BPF skeleton support requires libbpf or build with NO_BPF_SKEL=1.) - endif - host_byte_order=$(echo ""|$(HOSTCC) -dM -E -|grep __BYTE_ORDER__) - target_byte_order=$(echo ""|$(CC) -dM -E -|grep __BYTE_ORDER__) - ifneq ($(host_byte_order), $(target_byte_order)) - $(warning Possibly mismatched host and target endianness may break BPF skeletons) - endif - $(call detected,CONFIG_PERF_BPF_SKEL) - CFLAGS += -DHAVE_BPF_SKEL endif dwarf-post-unwind := 1 -- cgit v1.2.3-58-ga151 From 9a2d5178b9d51e1c5f9e08989ff97fc8d4893f31 Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Sat, 6 May 2023 18:07:37 -0300 Subject: Revert "perf build: Make BUILD_BPF_SKEL default, rename to NO_BPF_SKEL" This reverts commit a980755beb5aca9002e1c95ba519b83a44242b5b. We need to better polish building with BPF skels, so revert back to making it an experimental feature that has to be explicitely enabled using BUILD_BPF_SKEL=1. Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Makefile.config | 19 +++++++------------ tools/perf/Makefile.perf | 8 ++++---- tools/perf/builtin-lock.c | 2 +- tools/perf/builtin-record.c | 2 +- tools/perf/builtin-version.c | 1 - tools/perf/tests/shell/record_offcpu.sh | 2 +- 6 files changed, 14 insertions(+), 20 deletions(-) (limited to 'tools') diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index 16bea51f0bcd..ee467af49b62 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -415,7 +415,6 @@ ifdef NO_LIBELF NO_LIBUNWIND := 1 NO_LIBDW_DWARF_UNWIND := 1 NO_LIBBPF := 1 - NO_BPF_SKEL := 1 NO_JVMTI := 1 else ifeq ($(feature-libelf), 0) @@ -655,22 +654,18 @@ ifndef NO_LIBBPF msg := $(warning BPF API too old. Please install recent kernel headers. BPF support in 'perf record' is disabled.) NO_LIBBPF := 1 endif -else - NO_BPF_SKEL := 1 endif -ifndef NO_BPF_SKEL +ifdef BUILD_BPF_SKEL $(call feature_check,clang-bpf-co-re) ifeq ($(feature-clang-bpf-co-re), 0) - dummy := $(error: ERROR: BPF skeletons unsupported. clang too old/not installed or build with NO_BPF_SKEL=1.) - else - ifeq ($(filter -DHAVE_LIBBPF_SUPPORT, $(CFLAGS)),) - dummy := $(error: ERROR: BPF skeletons unsupported. BPF skeleton support requires libbpf or build with NO_BPF_SKEL=1.) - else - $(call detected,CONFIG_PERF_BPF_SKEL) - CFLAGS += -DHAVE_BPF_SKEL - endif + dummy := $(error Error: clang too old/not installed. Please install recent clang to build with BUILD_BPF_SKEL) + endif + ifeq ($(filter -DHAVE_LIBBPF_SUPPORT, $(CFLAGS)),) + dummy := $(error Error: BPF skeleton support requires libbpf) endif + $(call detected,CONFIG_PERF_BPF_SKEL) + CFLAGS += -DHAVE_BPF_SKEL endif dwarf-post-unwind := 1 diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf index 61c33d100b2b..a42a6a99c2bc 100644 --- a/tools/perf/Makefile.perf +++ b/tools/perf/Makefile.perf @@ -124,7 +124,7 @@ include ../scripts/utilities.mak # # Define NO_LIBDEBUGINFOD if you do not want support debuginfod # -# Define NO_BPF_SKEL to disable BPF skeletons +# Define BUILD_BPF_SKEL to enable BPF skeletons # # Define BUILD_NONDISTRO to enable building an linking against libbfd and # libiberty distribution license incompatible libraries. @@ -1055,7 +1055,7 @@ SKELETONS += $(SKEL_OUT)/kwork_trace.skel.h $(SKEL_OUT)/sample_filter.skel.h $(SKEL_TMP_OUT) $(LIBAPI_OUTPUT) $(LIBBPF_OUTPUT) $(LIBPERF_OUTPUT) $(LIBSUBCMD_OUTPUT) $(LIBSYMBOL_OUTPUT): $(Q)$(MKDIR) -p $@ -ifndef NO_BPF_SKEL +ifdef BUILD_BPF_SKEL BPFTOOL := $(SKEL_TMP_OUT)/bootstrap/bpftool BPF_INCLUDE := -I$(SKEL_TMP_OUT)/.. -I$(LIBBPF_INCLUDE) @@ -1074,11 +1074,11 @@ bpf-skel: $(SKELETONS) .PRECIOUS: $(SKEL_TMP_OUT)/%.bpf.o -else # NO_BPF_SKEL +else # BUILD_BPF_SKEL bpf-skel: -endif # NO_BPF_SKEL +endif # BUILD_BPF_SKEL bpf-skel-clean: $(call QUIET_CLEAN, bpf-skel) $(RM) -r $(SKEL_TMP_OUT) $(SKELETONS) diff --git a/tools/perf/builtin-lock.c b/tools/perf/builtin-lock.c index ecb1fac8ba3c..70b14ba5fdd5 100644 --- a/tools/perf/builtin-lock.c +++ b/tools/perf/builtin-lock.c @@ -2387,7 +2387,7 @@ int cmd_lock(int argc, const char **argv) #ifndef HAVE_BPF_SKEL set_option_nobuild(contention_options, 'b', "use-bpf", - "NO_BPF_SKEL=1", false); + "no BUILD_BPF_SKEL=1", false); #endif if (argc) { argc = parse_options(argc, argv, contention_options, diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c index 7b7e74a56346..efa03e4ac2c9 100644 --- a/tools/perf/builtin-record.c +++ b/tools/perf/builtin-record.c @@ -3981,7 +3981,7 @@ int cmd_record(int argc, const char **argv) #ifndef HAVE_BPF_SKEL # define set_nobuild(s, l, m, c) set_option_nobuild(record_options, s, l, m, c) - set_nobuild('\0', "off-cpu", "NO_BPF_SKEL=1", true); + set_nobuild('\0', "off-cpu", "no BUILD_BPF_SKEL=1", true); # undef set_nobuild #endif diff --git a/tools/perf/builtin-version.c b/tools/perf/builtin-version.c index 1872c90a6667..e5859c70e195 100644 --- a/tools/perf/builtin-version.c +++ b/tools/perf/builtin-version.c @@ -81,7 +81,6 @@ static void library_status(void) STATUS(HAVE_ZSTD_SUPPORT, zstd); STATUS(HAVE_LIBPFM, libpfm4); STATUS(HAVE_LIBTRACEEVENT, libtraceevent); - STATUS(HAVE_BPF_SKEL, BPF skeletons); } int cmd_version(int argc, const char **argv) diff --git a/tools/perf/tests/shell/record_offcpu.sh b/tools/perf/tests/shell/record_offcpu.sh index 155d4856551a..f062ae9a95e1 100755 --- a/tools/perf/tests/shell/record_offcpu.sh +++ b/tools/perf/tests/shell/record_offcpu.sh @@ -28,7 +28,7 @@ test_offcpu_priv() { err=2 return fi - if perf version --build-options 2>&1 | grep HAVE_BPF_SKEL | grep -q OFF + if perf record --off-cpu -o /dev/null --quiet true 2>&1 | grep BUILD_BPF_SKEL then echo "off-cpu test [Skipped missing BPF support]" err=2 -- cgit v1.2.3-58-ga151